rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<14>(0h2000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<18>(0h2f000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<27>(0h4000000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<19>(0h40000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = or(_T_323, _T_328) node _T_365 = or(_T_364, _T_333) node _T_366 = or(_T_365, _T_338) node _T_367 = or(_T_366, _T_343) node _T_368 = or(_T_367, _T_348) node _T_369 = or(_T_368, _T_353) node _T_370 = or(_T_369, _T_358) node _T_371 = or(_T_370, _T_363) node _T_372 = and(_T_318, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_T_317, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_374, UInt<1>(0h1), "") : assert_2 node _T_378 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<7>(0h40)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_24) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<7>(0h41)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_25) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_391 = shr(io.in.a.bits.source, 2) node _T_392 = eq(_T_391, UInt<7>(0h42)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_26) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_397 = shr(io.in.a.bits.source, 2) node _T_398 = eq(_T_397, UInt<7>(0h43)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_27) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_404 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_405 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<1>(0h0)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_28) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<1>(0h1)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_29) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_418 = shr(io.in.a.bits.source, 5) node _T_419 = eq(_T_418, UInt<2>(0h2)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_30) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_424 = shr(io.in.a.bits.source, 5) node _T_425 = eq(_T_424, UInt<2>(0h3)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_31) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<3>(0h4)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_32) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_436 = shr(io.in.a.bits.source, 5) node _T_437 = eq(_T_436, UInt<3>(0h5)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_33) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_442 = shr(io.in.a.bits.source, 5) node _T_443 = eq(_T_442, UInt<3>(0h6)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_34) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h7)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_35) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_378 connect _WIRE[1], _T_384 connect _WIRE[2], _T_390 connect _WIRE[3], _T_396 connect _WIRE[4], _T_402 connect _WIRE[5], _T_403 connect _WIRE[6], _T_404 connect _WIRE[7], _T_405 connect _WIRE[8], _T_411 connect _WIRE[9], _T_417 connect _WIRE[10], _T_423 connect _WIRE[11], _T_429 connect _WIRE[12], _T_435 connect _WIRE[13], _T_441 connect _WIRE[14], _T_447 connect _WIRE[15], _T_453 connect _WIRE[16], _T_454 node _T_455 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_456 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[5], _T_455, UInt<1>(0h0)) node _T_462 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = or(_T_456, _T_457) node _T_474 = or(_T_473, _T_458) node _T_475 = or(_T_474, _T_459) node _T_476 = or(_T_475, _T_460) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_462) node _T_479 = or(_T_478, _T_463) node _T_480 = or(_T_479, _T_464) node _T_481 = or(_T_480, _T_465) node _T_482 = or(_T_481, _T_466) node _T_483 = or(_T_482, _T_467) node _T_484 = or(_T_483, _T_468) node _T_485 = or(_T_484, _T_469) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_471) node _T_488 = or(_T_487, _T_472) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_488 node _T_489 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_490 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<14>(0h2000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<17>(0h10000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<18>(0h2f000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<13>(0h1000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_529 = cvt(_T_528) node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000))) node _T_531 = asSInt(_T_530) node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0))) node _T_533 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<19>(0h40000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = or(_T_497, _T_502) node _T_539 = or(_T_538, _T_507) node _T_540 = or(_T_539, _T_512) node _T_541 = or(_T_540, _T_517) node _T_542 = or(_T_541, _T_522) node _T_543 = or(_T_542, _T_527) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_537) node _T_546 = and(_T_492, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_WIRE_1, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_548, UInt<1>(0h1), "") : assert_3 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(source_ok, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_555 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_555, UInt<1>(0h1), "") : assert_5 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(is_aligned, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_562 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_562, UInt<1>(0h1), "") : assert_7 node _T_566 = not(io.in.a.bits.mask) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_567, UInt<1>(0h1), "") : assert_8 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_571, UInt<1>(0h1), "") : assert_9 node _T_575 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<7>(0h40)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_36) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<7>(0h41)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_37) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<7>(0h42)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_38) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<7>(0h43)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_39) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_605 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_606 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_607 = shr(io.in.a.bits.source, 5) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_40) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_613 = shr(io.in.a.bits.source, 5) node _T_614 = eq(_T_613, UInt<1>(0h1)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_41) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_619 = shr(io.in.a.bits.source, 5) node _T_620 = eq(_T_619, UInt<2>(0h2)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_42) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_624 = and(_T_622, _T_623) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_625 = shr(io.in.a.bits.source, 5) node _T_626 = eq(_T_625, UInt<2>(0h3)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_43) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_631 = shr(io.in.a.bits.source, 5) node _T_632 = eq(_T_631, UInt<3>(0h4)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_44) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_637 = shr(io.in.a.bits.source, 5) node _T_638 = eq(_T_637, UInt<3>(0h5)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_45) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_643 = shr(io.in.a.bits.source, 5) node _T_644 = eq(_T_643, UInt<3>(0h6)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_46) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_649 = shr(io.in.a.bits.source, 5) node _T_650 = eq(_T_649, UInt<3>(0h7)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_47) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_656 = or(_T_579, _T_585) node _T_657 = or(_T_656, _T_591) node _T_658 = or(_T_657, _T_597) node _T_659 = or(_T_658, _T_603) node _T_660 = or(_T_659, _T_604) node _T_661 = or(_T_660, _T_605) node _T_662 = or(_T_661, _T_606) node _T_663 = or(_T_662, _T_612) node _T_664 = or(_T_663, _T_618) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_630) node _T_667 = or(_T_666, _T_636) node _T_668 = or(_T_667, _T_642) node _T_669 = or(_T_668, _T_648) node _T_670 = or(_T_669, _T_654) node _T_671 = or(_T_670, _T_655) node _T_672 = and(_T_578, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<14>(0h2000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<13>(0h1000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<17>(0h10000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<18>(0h2f000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<17>(0h10000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<27>(0h4000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<19>(0h40000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_679, _T_684) node _T_721 = or(_T_720, _T_689) node _T_722 = or(_T_721, _T_694) node _T_723 = or(_T_722, _T_699) node _T_724 = or(_T_723, _T_704) node _T_725 = or(_T_724, _T_709) node _T_726 = or(_T_725, _T_714) node _T_727 = or(_T_726, _T_719) node _T_728 = and(_T_674, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = and(_T_673, _T_729) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_730, UInt<1>(0h1), "") : assert_10 node _T_734 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_735 = shr(io.in.a.bits.source, 2) node _T_736 = eq(_T_735, UInt<7>(0h40)) node _T_737 = leq(UInt<1>(0h0), uncommonBits_48) node _T_738 = and(_T_736, _T_737) node _T_739 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_740 = and(_T_738, _T_739) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_741 = shr(io.in.a.bits.source, 2) node _T_742 = eq(_T_741, UInt<7>(0h41)) node _T_743 = leq(UInt<1>(0h0), uncommonBits_49) node _T_744 = and(_T_742, _T_743) node _T_745 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_746 = and(_T_744, _T_745) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_747 = shr(io.in.a.bits.source, 2) node _T_748 = eq(_T_747, UInt<7>(0h42)) node _T_749 = leq(UInt<1>(0h0), uncommonBits_50) node _T_750 = and(_T_748, _T_749) node _T_751 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_752 = and(_T_750, _T_751) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_753 = shr(io.in.a.bits.source, 2) node _T_754 = eq(_T_753, UInt<7>(0h43)) node _T_755 = leq(UInt<1>(0h0), uncommonBits_51) node _T_756 = and(_T_754, _T_755) node _T_757 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_760 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_761 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_762 = shr(io.in.a.bits.source, 5) node _T_763 = eq(_T_762, UInt<1>(0h0)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_52) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_767 = and(_T_765, _T_766) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_768 = shr(io.in.a.bits.source, 5) node _T_769 = eq(_T_768, UInt<1>(0h1)) node _T_770 = leq(UInt<1>(0h0), uncommonBits_53) node _T_771 = and(_T_769, _T_770) node _T_772 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_773 = and(_T_771, _T_772) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_774 = shr(io.in.a.bits.source, 5) node _T_775 = eq(_T_774, UInt<2>(0h2)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_54) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_780 = shr(io.in.a.bits.source, 5) node _T_781 = eq(_T_780, UInt<2>(0h3)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_55) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_786 = shr(io.in.a.bits.source, 5) node _T_787 = eq(_T_786, UInt<3>(0h4)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_56) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_792 = shr(io.in.a.bits.source, 5) node _T_793 = eq(_T_792, UInt<3>(0h5)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_57) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_797 = and(_T_795, _T_796) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_798 = shr(io.in.a.bits.source, 5) node _T_799 = eq(_T_798, UInt<3>(0h6)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_58) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_803 = and(_T_801, _T_802) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_804 = shr(io.in.a.bits.source, 5) node _T_805 = eq(_T_804, UInt<3>(0h7)) node _T_806 = leq(UInt<1>(0h0), uncommonBits_59) node _T_807 = and(_T_805, _T_806) node _T_808 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_809 = and(_T_807, _T_808) node _T_810 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_734 connect _WIRE_2[1], _T_740 connect _WIRE_2[2], _T_746 connect _WIRE_2[3], _T_752 connect _WIRE_2[4], _T_758 connect _WIRE_2[5], _T_759 connect _WIRE_2[6], _T_760 connect _WIRE_2[7], _T_761 connect _WIRE_2[8], _T_767 connect _WIRE_2[9], _T_773 connect _WIRE_2[10], _T_779 connect _WIRE_2[11], _T_785 connect _WIRE_2[12], _T_791 connect _WIRE_2[13], _T_797 connect _WIRE_2[14], _T_803 connect _WIRE_2[15], _T_809 connect _WIRE_2[16], _T_810 node _T_811 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_812 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_813 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_814 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_815 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_816 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = mux(_WIRE_2[5], _T_811, UInt<1>(0h0)) node _T_818 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_820 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_821 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_822 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_824 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_825 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_826 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_827 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_828 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_829 = or(_T_812, _T_813) node _T_830 = or(_T_829, _T_814) node _T_831 = or(_T_830, _T_815) node _T_832 = or(_T_831, _T_816) node _T_833 = or(_T_832, _T_817) node _T_834 = or(_T_833, _T_818) node _T_835 = or(_T_834, _T_819) node _T_836 = or(_T_835, _T_820) node _T_837 = or(_T_836, _T_821) node _T_838 = or(_T_837, _T_822) node _T_839 = or(_T_838, _T_823) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_825) node _T_842 = or(_T_841, _T_826) node _T_843 = or(_T_842, _T_827) node _T_844 = or(_T_843, _T_828) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_844 node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<14>(0h2000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<19>(0h40000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = or(_T_853, _T_858) node _T_895 = or(_T_894, _T_863) node _T_896 = or(_T_895, _T_868) node _T_897 = or(_T_896, _T_873) node _T_898 = or(_T_897, _T_878) node _T_899 = or(_T_898, _T_883) node _T_900 = or(_T_899, _T_888) node _T_901 = or(_T_900, _T_893) node _T_902 = and(_T_848, _T_901) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = and(_WIRE_3, _T_903) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_904, UInt<1>(0h1), "") : assert_11 node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_911 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_911, UInt<1>(0h1), "") : assert_13 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(is_aligned, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_918 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_918, UInt<1>(0h1), "") : assert_15 node _T_922 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_922, UInt<1>(0h1), "") : assert_16 node _T_926 = not(io.in.a.bits.mask) node _T_927 = eq(_T_926, UInt<1>(0h0)) node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(_T_927, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_927, UInt<1>(0h1), "") : assert_17 node _T_931 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_931, UInt<1>(0h1), "") : assert_18 node _T_935 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_935 : node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<7>(0h40)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_60) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<7>(0h41)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_61) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<7>(0h42)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_62) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<7>(0h43)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_63) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _T_964 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_967 = shr(io.in.a.bits.source, 5) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = leq(UInt<1>(0h0), uncommonBits_64) node _T_970 = and(_T_968, _T_969) node _T_971 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_972 = and(_T_970, _T_971) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_973 = shr(io.in.a.bits.source, 5) node _T_974 = eq(_T_973, UInt<1>(0h1)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_65) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_978 = and(_T_976, _T_977) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_979 = shr(io.in.a.bits.source, 5) node _T_980 = eq(_T_979, UInt<2>(0h2)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_66) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_985 = shr(io.in.a.bits.source, 5) node _T_986 = eq(_T_985, UInt<2>(0h3)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_67) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_991 = shr(io.in.a.bits.source, 5) node _T_992 = eq(_T_991, UInt<3>(0h4)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_68) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_996 = and(_T_994, _T_995) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_997 = shr(io.in.a.bits.source, 5) node _T_998 = eq(_T_997, UInt<3>(0h5)) node _T_999 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1000 = and(_T_998, _T_999) node _T_1001 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1002 = and(_T_1000, _T_1001) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1003 = shr(io.in.a.bits.source, 5) node _T_1004 = eq(_T_1003, UInt<3>(0h6)) node _T_1005 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1006 = and(_T_1004, _T_1005) node _T_1007 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1008 = and(_T_1006, _T_1007) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1009 = shr(io.in.a.bits.source, 5) node _T_1010 = eq(_T_1009, UInt<3>(0h7)) node _T_1011 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1016 = or(_T_939, _T_945) node _T_1017 = or(_T_1016, _T_951) node _T_1018 = or(_T_1017, _T_957) node _T_1019 = or(_T_1018, _T_963) node _T_1020 = or(_T_1019, _T_964) node _T_1021 = or(_T_1020, _T_965) node _T_1022 = or(_T_1021, _T_966) node _T_1023 = or(_T_1022, _T_972) node _T_1024 = or(_T_1023, _T_978) node _T_1025 = or(_T_1024, _T_984) node _T_1026 = or(_T_1025, _T_990) node _T_1027 = or(_T_1026, _T_996) node _T_1028 = or(_T_1027, _T_1002) node _T_1029 = or(_T_1028, _T_1008) node _T_1030 = or(_T_1029, _T_1014) node _T_1031 = or(_T_1030, _T_1015) node _T_1032 = and(_T_938, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_19 node _T_1037 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1038 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1039 = and(_T_1037, _T_1038) node _T_1040 = or(UInt<1>(0h0), _T_1039) node _T_1041 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1042 = cvt(_T_1041) node _T_1043 = and(_T_1042, asSInt(UInt<13>(0h1000))) node _T_1044 = asSInt(_T_1043) node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0))) node _T_1046 = and(_T_1040, _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1048 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<14>(0h2000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<18>(0h2f000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1067 = cvt(_T_1066) node _T_1068 = and(_T_1067, asSInt(UInt<17>(0h10000))) node _T_1069 = asSInt(_T_1068) node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0))) node _T_1071 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1072 = cvt(_T_1071) node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000))) node _T_1074 = asSInt(_T_1073) node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1077 = cvt(_T_1076) node _T_1078 = and(_T_1077, asSInt(UInt<27>(0h4000000))) node _T_1079 = asSInt(_T_1078) node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0))) node _T_1081 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1082 = cvt(_T_1081) node _T_1083 = and(_T_1082, asSInt(UInt<13>(0h1000))) node _T_1084 = asSInt(_T_1083) node _T_1085 = eq(_T_1084, asSInt(UInt<1>(0h0))) node _T_1086 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<19>(0h40000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1055, _T_1060) node _T_1092 = or(_T_1091, _T_1065) node _T_1093 = or(_T_1092, _T_1070) node _T_1094 = or(_T_1093, _T_1075) node _T_1095 = or(_T_1094, _T_1080) node _T_1096 = or(_T_1095, _T_1085) node _T_1097 = or(_T_1096, _T_1090) node _T_1098 = and(_T_1050, _T_1097) node _T_1099 = or(UInt<1>(0h0), _T_1046) node _T_1100 = or(_T_1099, _T_1098) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_20 node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(is_aligned, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1110 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_23 node _T_1114 = eq(io.in.a.bits.mask, mask) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_24 node _T_1118 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_25 node _T_1122 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1122 : node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1127 = shr(io.in.a.bits.source, 2) node _T_1128 = eq(_T_1127, UInt<7>(0h40)) node _T_1129 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1132 = and(_T_1130, _T_1131) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1133 = shr(io.in.a.bits.source, 2) node _T_1134 = eq(_T_1133, UInt<7>(0h41)) node _T_1135 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1138 = and(_T_1136, _T_1137) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_1139 = shr(io.in.a.bits.source, 2) node _T_1140 = eq(_T_1139, UInt<7>(0h42)) node _T_1141 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1145 = shr(io.in.a.bits.source, 2) node _T_1146 = eq(_T_1145, UInt<7>(0h43)) node _T_1147 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1152 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1153 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_1154 = shr(io.in.a.bits.source, 5) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) node _T_1156 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_1159 = and(_T_1157, _T_1158) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_1160 = shr(io.in.a.bits.source, 5) node _T_1161 = eq(_T_1160, UInt<1>(0h1)) node _T_1162 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_1165 = and(_T_1163, _T_1164) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_1166 = shr(io.in.a.bits.source, 5) node _T_1167 = eq(_T_1166, UInt<2>(0h2)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_1172 = shr(io.in.a.bits.source, 5) node _T_1173 = eq(_T_1172, UInt<2>(0h3)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_1178 = shr(io.in.a.bits.source, 5) node _T_1179 = eq(_T_1178, UInt<3>(0h4)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_1184 = shr(io.in.a.bits.source, 5) node _T_1185 = eq(_T_1184, UInt<3>(0h5)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_1190 = shr(io.in.a.bits.source, 5) node _T_1191 = eq(_T_1190, UInt<3>(0h6)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_1196 = shr(io.in.a.bits.source, 5) node _T_1197 = eq(_T_1196, UInt<3>(0h7)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1203 = or(_T_1126, _T_1132) node _T_1204 = or(_T_1203, _T_1138) node _T_1205 = or(_T_1204, _T_1144) node _T_1206 = or(_T_1205, _T_1150) node _T_1207 = or(_T_1206, _T_1151) node _T_1208 = or(_T_1207, _T_1152) node _T_1209 = or(_T_1208, _T_1153) node _T_1210 = or(_T_1209, _T_1159) node _T_1211 = or(_T_1210, _T_1165) node _T_1212 = or(_T_1211, _T_1171) node _T_1213 = or(_T_1212, _T_1177) node _T_1214 = or(_T_1213, _T_1183) node _T_1215 = or(_T_1214, _T_1189) node _T_1216 = or(_T_1215, _T_1195) node _T_1217 = or(_T_1216, _T_1201) node _T_1218 = or(_T_1217, _T_1202) node _T_1219 = and(_T_1125, _T_1218) node _T_1220 = or(UInt<1>(0h0), _T_1219) node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1223 = and(_T_1221, _T_1222) node _T_1224 = or(UInt<1>(0h0), _T_1223) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = and(_T_1224, _T_1229) node _T_1231 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1232 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1233) node _T_1235 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<14>(0h2000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<18>(0h2f000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<17>(0h10000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<27>(0h4000000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<13>(0h1000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<19>(0h40000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = or(_T_1239, _T_1244) node _T_1271 = or(_T_1270, _T_1249) node _T_1272 = or(_T_1271, _T_1254) node _T_1273 = or(_T_1272, _T_1259) node _T_1274 = or(_T_1273, _T_1264) node _T_1275 = or(_T_1274, _T_1269) node _T_1276 = and(_T_1234, _T_1275) node _T_1277 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1278 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = and(_T_1277, _T_1282) node _T_1284 = or(UInt<1>(0h0), _T_1230) node _T_1285 = or(_T_1284, _T_1276) node _T_1286 = or(_T_1285, _T_1283) node _T_1287 = and(_T_1220, _T_1286) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_26 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(is_aligned, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1297 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_29 node _T_1301 = eq(io.in.a.bits.mask, mask) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_30 node _T_1305 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1305 : node _T_1306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1310 = shr(io.in.a.bits.source, 2) node _T_1311 = eq(_T_1310, UInt<7>(0h40)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1316 = shr(io.in.a.bits.source, 2) node _T_1317 = eq(_T_1316, UInt<7>(0h41)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1322 = shr(io.in.a.bits.source, 2) node _T_1323 = eq(_T_1322, UInt<7>(0h42)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1327 = and(_T_1325, _T_1326) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1328 = shr(io.in.a.bits.source, 2) node _T_1329 = eq(_T_1328, UInt<7>(0h43)) node _T_1330 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1331 = and(_T_1329, _T_1330) node _T_1332 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1335 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1336 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1337 = shr(io.in.a.bits.source, 5) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) node _T_1339 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1342 = and(_T_1340, _T_1341) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1343 = shr(io.in.a.bits.source, 5) node _T_1344 = eq(_T_1343, UInt<1>(0h1)) node _T_1345 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1348 = and(_T_1346, _T_1347) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1349 = shr(io.in.a.bits.source, 5) node _T_1350 = eq(_T_1349, UInt<2>(0h2)) node _T_1351 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1352 = and(_T_1350, _T_1351) node _T_1353 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1354 = and(_T_1352, _T_1353) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1355 = shr(io.in.a.bits.source, 5) node _T_1356 = eq(_T_1355, UInt<2>(0h3)) node _T_1357 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1358 = and(_T_1356, _T_1357) node _T_1359 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1360 = and(_T_1358, _T_1359) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1361 = shr(io.in.a.bits.source, 5) node _T_1362 = eq(_T_1361, UInt<3>(0h4)) node _T_1363 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1366 = and(_T_1364, _T_1365) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1367 = shr(io.in.a.bits.source, 5) node _T_1368 = eq(_T_1367, UInt<3>(0h5)) node _T_1369 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1370 = and(_T_1368, _T_1369) node _T_1371 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1372 = and(_T_1370, _T_1371) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1373 = shr(io.in.a.bits.source, 5) node _T_1374 = eq(_T_1373, UInt<3>(0h6)) node _T_1375 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1376 = and(_T_1374, _T_1375) node _T_1377 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1378 = and(_T_1376, _T_1377) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1379 = shr(io.in.a.bits.source, 5) node _T_1380 = eq(_T_1379, UInt<3>(0h7)) node _T_1381 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1386 = or(_T_1309, _T_1315) node _T_1387 = or(_T_1386, _T_1321) node _T_1388 = or(_T_1387, _T_1327) node _T_1389 = or(_T_1388, _T_1333) node _T_1390 = or(_T_1389, _T_1334) node _T_1391 = or(_T_1390, _T_1335) node _T_1392 = or(_T_1391, _T_1336) node _T_1393 = or(_T_1392, _T_1342) node _T_1394 = or(_T_1393, _T_1348) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1360) node _T_1397 = or(_T_1396, _T_1366) node _T_1398 = or(_T_1397, _T_1372) node _T_1399 = or(_T_1398, _T_1378) node _T_1400 = or(_T_1399, _T_1384) node _T_1401 = or(_T_1400, _T_1385) node _T_1402 = and(_T_1308, _T_1401) node _T_1403 = or(UInt<1>(0h0), _T_1402) node _T_1404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1405 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1406 = and(_T_1404, _T_1405) node _T_1407 = or(UInt<1>(0h0), _T_1406) node _T_1408 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1409 = cvt(_T_1408) node _T_1410 = and(_T_1409, asSInt(UInt<13>(0h1000))) node _T_1411 = asSInt(_T_1410) node _T_1412 = eq(_T_1411, asSInt(UInt<1>(0h0))) node _T_1413 = and(_T_1407, _T_1412) node _T_1414 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1415 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1416 = and(_T_1414, _T_1415) node _T_1417 = or(UInt<1>(0h0), _T_1416) node _T_1418 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<14>(0h2000))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1424 = cvt(_T_1423) node _T_1425 = and(_T_1424, asSInt(UInt<18>(0h2f000))) node _T_1426 = asSInt(_T_1425) node _T_1427 = eq(_T_1426, asSInt(UInt<1>(0h0))) node _T_1428 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1429 = cvt(_T_1428) node _T_1430 = and(_T_1429, asSInt(UInt<17>(0h10000))) node _T_1431 = asSInt(_T_1430) node _T_1432 = eq(_T_1431, asSInt(UInt<1>(0h0))) node _T_1433 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1434 = cvt(_T_1433) node _T_1435 = and(_T_1434, asSInt(UInt<13>(0h1000))) node _T_1436 = asSInt(_T_1435) node _T_1437 = eq(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1439 = cvt(_T_1438) node _T_1440 = and(_T_1439, asSInt(UInt<27>(0h4000000))) node _T_1441 = asSInt(_T_1440) node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0))) node _T_1443 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<13>(0h1000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<19>(0h40000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1422, _T_1427) node _T_1454 = or(_T_1453, _T_1432) node _T_1455 = or(_T_1454, _T_1437) node _T_1456 = or(_T_1455, _T_1442) node _T_1457 = or(_T_1456, _T_1447) node _T_1458 = or(_T_1457, _T_1452) node _T_1459 = and(_T_1417, _T_1458) node _T_1460 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1461 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<17>(0h10000))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = and(_T_1460, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1413) node _T_1468 = or(_T_1467, _T_1459) node _T_1469 = or(_T_1468, _T_1466) node _T_1470 = and(_T_1403, _T_1469) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_31 node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(is_aligned, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1480 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_34 node _T_1484 = not(mask) node _T_1485 = and(io.in.a.bits.mask, _T_1484) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_35 node _T_1490 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1495 = shr(io.in.a.bits.source, 2) node _T_1496 = eq(_T_1495, UInt<7>(0h40)) node _T_1497 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1500 = and(_T_1498, _T_1499) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1501 = shr(io.in.a.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<7>(0h41)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1507 = shr(io.in.a.bits.source, 2) node _T_1508 = eq(_T_1507, UInt<7>(0h42)) node _T_1509 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1510 = and(_T_1508, _T_1509) node _T_1511 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1512 = and(_T_1510, _T_1511) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1513 = shr(io.in.a.bits.source, 2) node _T_1514 = eq(_T_1513, UInt<7>(0h43)) node _T_1515 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1516 = and(_T_1514, _T_1515) node _T_1517 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1518 = and(_T_1516, _T_1517) node _T_1519 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1520 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1521 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1522 = shr(io.in.a.bits.source, 5) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) node _T_1524 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1525 = and(_T_1523, _T_1524) node _T_1526 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1527 = and(_T_1525, _T_1526) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1528 = shr(io.in.a.bits.source, 5) node _T_1529 = eq(_T_1528, UInt<1>(0h1)) node _T_1530 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1531 = and(_T_1529, _T_1530) node _T_1532 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1533 = and(_T_1531, _T_1532) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1534 = shr(io.in.a.bits.source, 5) node _T_1535 = eq(_T_1534, UInt<2>(0h2)) node _T_1536 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1539 = and(_T_1537, _T_1538) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1540 = shr(io.in.a.bits.source, 5) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1545 = and(_T_1543, _T_1544) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1546 = shr(io.in.a.bits.source, 5) node _T_1547 = eq(_T_1546, UInt<3>(0h4)) node _T_1548 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1549 = and(_T_1547, _T_1548) node _T_1550 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1551 = and(_T_1549, _T_1550) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1552 = shr(io.in.a.bits.source, 5) node _T_1553 = eq(_T_1552, UInt<3>(0h5)) node _T_1554 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1557 = and(_T_1555, _T_1556) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1558 = shr(io.in.a.bits.source, 5) node _T_1559 = eq(_T_1558, UInt<3>(0h6)) node _T_1560 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1563 = and(_T_1561, _T_1562) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1564 = shr(io.in.a.bits.source, 5) node _T_1565 = eq(_T_1564, UInt<3>(0h7)) node _T_1566 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1569 = and(_T_1567, _T_1568) node _T_1570 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1571 = or(_T_1494, _T_1500) node _T_1572 = or(_T_1571, _T_1506) node _T_1573 = or(_T_1572, _T_1512) node _T_1574 = or(_T_1573, _T_1518) node _T_1575 = or(_T_1574, _T_1519) node _T_1576 = or(_T_1575, _T_1520) node _T_1577 = or(_T_1576, _T_1521) node _T_1578 = or(_T_1577, _T_1527) node _T_1579 = or(_T_1578, _T_1533) node _T_1580 = or(_T_1579, _T_1539) node _T_1581 = or(_T_1580, _T_1545) node _T_1582 = or(_T_1581, _T_1551) node _T_1583 = or(_T_1582, _T_1557) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1569) node _T_1586 = or(_T_1585, _T_1570) node _T_1587 = and(_T_1493, _T_1586) node _T_1588 = or(UInt<1>(0h0), _T_1587) node _T_1589 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1590 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = or(UInt<1>(0h0), _T_1591) node _T_1593 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1594 = cvt(_T_1593) node _T_1595 = and(_T_1594, asSInt(UInt<14>(0h2000))) node _T_1596 = asSInt(_T_1595) node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0))) node _T_1598 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1599 = cvt(_T_1598) node _T_1600 = and(_T_1599, asSInt(UInt<13>(0h1000))) node _T_1601 = asSInt(_T_1600) node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0))) node _T_1603 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1604 = cvt(_T_1603) node _T_1605 = and(_T_1604, asSInt(UInt<18>(0h2f000))) node _T_1606 = asSInt(_T_1605) node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0))) node _T_1608 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1609 = cvt(_T_1608) node _T_1610 = and(_T_1609, asSInt(UInt<17>(0h10000))) node _T_1611 = asSInt(_T_1610) node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0))) node _T_1613 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1614 = cvt(_T_1613) node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000))) node _T_1616 = asSInt(_T_1615) node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0))) node _T_1618 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<27>(0h4000000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<19>(0h40000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = or(_T_1597, _T_1602) node _T_1634 = or(_T_1633, _T_1607) node _T_1635 = or(_T_1634, _T_1612) node _T_1636 = or(_T_1635, _T_1617) node _T_1637 = or(_T_1636, _T_1622) node _T_1638 = or(_T_1637, _T_1627) node _T_1639 = or(_T_1638, _T_1632) node _T_1640 = and(_T_1592, _T_1639) node _T_1641 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1642 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1643 = cvt(_T_1642) node _T_1644 = and(_T_1643, asSInt(UInt<17>(0h10000))) node _T_1645 = asSInt(_T_1644) node _T_1646 = eq(_T_1645, asSInt(UInt<1>(0h0))) node _T_1647 = and(_T_1641, _T_1646) node _T_1648 = or(UInt<1>(0h0), _T_1640) node _T_1649 = or(_T_1648, _T_1647) node _T_1650 = and(_T_1588, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_36 node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(source_ok, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(is_aligned, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1660 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_39 node _T_1664 = eq(io.in.a.bits.mask, mask) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_40 node _T_1668 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1668 : node _T_1669 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1670 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1673 = shr(io.in.a.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<7>(0h40)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1679 = shr(io.in.a.bits.source, 2) node _T_1680 = eq(_T_1679, UInt<7>(0h41)) node _T_1681 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1684 = and(_T_1682, _T_1683) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1685 = shr(io.in.a.bits.source, 2) node _T_1686 = eq(_T_1685, UInt<7>(0h42)) node _T_1687 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1688 = and(_T_1686, _T_1687) node _T_1689 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1690 = and(_T_1688, _T_1689) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1691 = shr(io.in.a.bits.source, 2) node _T_1692 = eq(_T_1691, UInt<7>(0h43)) node _T_1693 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1694 = and(_T_1692, _T_1693) node _T_1695 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1696 = and(_T_1694, _T_1695) node _T_1697 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1698 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1699 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1700 = shr(io.in.a.bits.source, 5) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) node _T_1702 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1705 = and(_T_1703, _T_1704) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1706 = shr(io.in.a.bits.source, 5) node _T_1707 = eq(_T_1706, UInt<1>(0h1)) node _T_1708 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1709 = and(_T_1707, _T_1708) node _T_1710 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1711 = and(_T_1709, _T_1710) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1712 = shr(io.in.a.bits.source, 5) node _T_1713 = eq(_T_1712, UInt<2>(0h2)) node _T_1714 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1717 = and(_T_1715, _T_1716) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1718 = shr(io.in.a.bits.source, 5) node _T_1719 = eq(_T_1718, UInt<2>(0h3)) node _T_1720 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1723 = and(_T_1721, _T_1722) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1724 = shr(io.in.a.bits.source, 5) node _T_1725 = eq(_T_1724, UInt<3>(0h4)) node _T_1726 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1729 = and(_T_1727, _T_1728) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1730 = shr(io.in.a.bits.source, 5) node _T_1731 = eq(_T_1730, UInt<3>(0h5)) node _T_1732 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1733 = and(_T_1731, _T_1732) node _T_1734 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1735 = and(_T_1733, _T_1734) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1736 = shr(io.in.a.bits.source, 5) node _T_1737 = eq(_T_1736, UInt<3>(0h6)) node _T_1738 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1739 = and(_T_1737, _T_1738) node _T_1740 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1741 = and(_T_1739, _T_1740) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1742 = shr(io.in.a.bits.source, 5) node _T_1743 = eq(_T_1742, UInt<3>(0h7)) node _T_1744 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1745 = and(_T_1743, _T_1744) node _T_1746 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1747 = and(_T_1745, _T_1746) node _T_1748 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1749 = or(_T_1672, _T_1678) node _T_1750 = or(_T_1749, _T_1684) node _T_1751 = or(_T_1750, _T_1690) node _T_1752 = or(_T_1751, _T_1696) node _T_1753 = or(_T_1752, _T_1697) node _T_1754 = or(_T_1753, _T_1698) node _T_1755 = or(_T_1754, _T_1699) node _T_1756 = or(_T_1755, _T_1705) node _T_1757 = or(_T_1756, _T_1711) node _T_1758 = or(_T_1757, _T_1717) node _T_1759 = or(_T_1758, _T_1723) node _T_1760 = or(_T_1759, _T_1729) node _T_1761 = or(_T_1760, _T_1735) node _T_1762 = or(_T_1761, _T_1741) node _T_1763 = or(_T_1762, _T_1747) node _T_1764 = or(_T_1763, _T_1748) node _T_1765 = and(_T_1671, _T_1764) node _T_1766 = or(UInt<1>(0h0), _T_1765) node _T_1767 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1768 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1769 = and(_T_1767, _T_1768) node _T_1770 = or(UInt<1>(0h0), _T_1769) node _T_1771 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1772 = cvt(_T_1771) node _T_1773 = and(_T_1772, asSInt(UInt<14>(0h2000))) node _T_1774 = asSInt(_T_1773) node _T_1775 = eq(_T_1774, asSInt(UInt<1>(0h0))) node _T_1776 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1777 = cvt(_T_1776) node _T_1778 = and(_T_1777, asSInt(UInt<13>(0h1000))) node _T_1779 = asSInt(_T_1778) node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1782 = cvt(_T_1781) node _T_1783 = and(_T_1782, asSInt(UInt<18>(0h2f000))) node _T_1784 = asSInt(_T_1783) node _T_1785 = eq(_T_1784, asSInt(UInt<1>(0h0))) node _T_1786 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1787 = cvt(_T_1786) node _T_1788 = and(_T_1787, asSInt(UInt<17>(0h10000))) node _T_1789 = asSInt(_T_1788) node _T_1790 = eq(_T_1789, asSInt(UInt<1>(0h0))) node _T_1791 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1792 = cvt(_T_1791) node _T_1793 = and(_T_1792, asSInt(UInt<13>(0h1000))) node _T_1794 = asSInt(_T_1793) node _T_1795 = eq(_T_1794, asSInt(UInt<1>(0h0))) node _T_1796 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1797 = cvt(_T_1796) node _T_1798 = and(_T_1797, asSInt(UInt<27>(0h4000000))) node _T_1799 = asSInt(_T_1798) node _T_1800 = eq(_T_1799, asSInt(UInt<1>(0h0))) node _T_1801 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1802 = cvt(_T_1801) node _T_1803 = and(_T_1802, asSInt(UInt<13>(0h1000))) node _T_1804 = asSInt(_T_1803) node _T_1805 = eq(_T_1804, asSInt(UInt<1>(0h0))) node _T_1806 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1807 = cvt(_T_1806) node _T_1808 = and(_T_1807, asSInt(UInt<19>(0h40000))) node _T_1809 = asSInt(_T_1808) node _T_1810 = eq(_T_1809, asSInt(UInt<1>(0h0))) node _T_1811 = or(_T_1775, _T_1780) node _T_1812 = or(_T_1811, _T_1785) node _T_1813 = or(_T_1812, _T_1790) node _T_1814 = or(_T_1813, _T_1795) node _T_1815 = or(_T_1814, _T_1800) node _T_1816 = or(_T_1815, _T_1805) node _T_1817 = or(_T_1816, _T_1810) node _T_1818 = and(_T_1770, _T_1817) node _T_1819 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1820 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1821 = cvt(_T_1820) node _T_1822 = and(_T_1821, asSInt(UInt<17>(0h10000))) node _T_1823 = asSInt(_T_1822) node _T_1824 = eq(_T_1823, asSInt(UInt<1>(0h0))) node _T_1825 = and(_T_1819, _T_1824) node _T_1826 = or(UInt<1>(0h0), _T_1818) node _T_1827 = or(_T_1826, _T_1825) node _T_1828 = and(_T_1766, _T_1827) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_41 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(source_ok, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_44 node _T_1842 = eq(io.in.a.bits.mask, mask) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_45 node _T_1846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1851 = shr(io.in.a.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<7>(0h40)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1857 = shr(io.in.a.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<7>(0h41)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1863 = shr(io.in.a.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<7>(0h42)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1869 = shr(io.in.a.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<7>(0h43)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _T_1875 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1876 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1877 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1878 = shr(io.in.a.bits.source, 5) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1883 = and(_T_1881, _T_1882) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1884 = shr(io.in.a.bits.source, 5) node _T_1885 = eq(_T_1884, UInt<1>(0h1)) node _T_1886 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1887 = and(_T_1885, _T_1886) node _T_1888 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1889 = and(_T_1887, _T_1888) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1890 = shr(io.in.a.bits.source, 5) node _T_1891 = eq(_T_1890, UInt<2>(0h2)) node _T_1892 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1893 = and(_T_1891, _T_1892) node _T_1894 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1895 = and(_T_1893, _T_1894) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1896 = shr(io.in.a.bits.source, 5) node _T_1897 = eq(_T_1896, UInt<2>(0h3)) node _T_1898 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1901 = and(_T_1899, _T_1900) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1902 = shr(io.in.a.bits.source, 5) node _T_1903 = eq(_T_1902, UInt<3>(0h4)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1908 = shr(io.in.a.bits.source, 5) node _T_1909 = eq(_T_1908, UInt<3>(0h5)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1914 = shr(io.in.a.bits.source, 5) node _T_1915 = eq(_T_1914, UInt<3>(0h6)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1920 = shr(io.in.a.bits.source, 5) node _T_1921 = eq(_T_1920, UInt<3>(0h7)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1927 = or(_T_1850, _T_1856) node _T_1928 = or(_T_1927, _T_1862) node _T_1929 = or(_T_1928, _T_1868) node _T_1930 = or(_T_1929, _T_1874) node _T_1931 = or(_T_1930, _T_1875) node _T_1932 = or(_T_1931, _T_1876) node _T_1933 = or(_T_1932, _T_1877) node _T_1934 = or(_T_1933, _T_1883) node _T_1935 = or(_T_1934, _T_1889) node _T_1936 = or(_T_1935, _T_1895) node _T_1937 = or(_T_1936, _T_1901) node _T_1938 = or(_T_1937, _T_1907) node _T_1939 = or(_T_1938, _T_1913) node _T_1940 = or(_T_1939, _T_1919) node _T_1941 = or(_T_1940, _T_1925) node _T_1942 = or(_T_1941, _T_1926) node _T_1943 = and(_T_1849, _T_1942) node _T_1944 = or(UInt<1>(0h0), _T_1943) node _T_1945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1947 = and(_T_1945, _T_1946) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1950 = cvt(_T_1949) node _T_1951 = and(_T_1950, asSInt(UInt<13>(0h1000))) node _T_1952 = asSInt(_T_1951) node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0))) node _T_1954 = and(_T_1948, _T_1953) node _T_1955 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1956 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1957 = cvt(_T_1956) node _T_1958 = and(_T_1957, asSInt(UInt<14>(0h2000))) node _T_1959 = asSInt(_T_1958) node _T_1960 = eq(_T_1959, asSInt(UInt<1>(0h0))) node _T_1961 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1962 = cvt(_T_1961) node _T_1963 = and(_T_1962, asSInt(UInt<17>(0h10000))) node _T_1964 = asSInt(_T_1963) node _T_1965 = eq(_T_1964, asSInt(UInt<1>(0h0))) node _T_1966 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1967 = cvt(_T_1966) node _T_1968 = and(_T_1967, asSInt(UInt<18>(0h2f000))) node _T_1969 = asSInt(_T_1968) node _T_1970 = eq(_T_1969, asSInt(UInt<1>(0h0))) node _T_1971 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1972 = cvt(_T_1971) node _T_1973 = and(_T_1972, asSInt(UInt<17>(0h10000))) node _T_1974 = asSInt(_T_1973) node _T_1975 = eq(_T_1974, asSInt(UInt<1>(0h0))) node _T_1976 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1977 = cvt(_T_1976) node _T_1978 = and(_T_1977, asSInt(UInt<13>(0h1000))) node _T_1979 = asSInt(_T_1978) node _T_1980 = eq(_T_1979, asSInt(UInt<1>(0h0))) node _T_1981 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<27>(0h4000000))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1987 = cvt(_T_1986) node _T_1988 = and(_T_1987, asSInt(UInt<13>(0h1000))) node _T_1989 = asSInt(_T_1988) node _T_1990 = eq(_T_1989, asSInt(UInt<1>(0h0))) node _T_1991 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1992 = cvt(_T_1991) node _T_1993 = and(_T_1992, asSInt(UInt<19>(0h40000))) node _T_1994 = asSInt(_T_1993) node _T_1995 = eq(_T_1994, asSInt(UInt<1>(0h0))) node _T_1996 = or(_T_1960, _T_1965) node _T_1997 = or(_T_1996, _T_1970) node _T_1998 = or(_T_1997, _T_1975) node _T_1999 = or(_T_1998, _T_1980) node _T_2000 = or(_T_1999, _T_1985) node _T_2001 = or(_T_2000, _T_1990) node _T_2002 = or(_T_2001, _T_1995) node _T_2003 = and(_T_1955, _T_2002) node _T_2004 = or(UInt<1>(0h0), _T_1954) node _T_2005 = or(_T_2004, _T_2003) node _T_2006 = and(_T_1944, _T_2005) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_46 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(source_ok, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(is_aligned, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2016 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_49 node _T_2020 = eq(io.in.a.bits.mask, mask) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_50 node _T_2024 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(_T_2024, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2024, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2028 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2032 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2032 : node _T_2033 = asUInt(reset) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(source_ok_1, UInt<1>(0h0)) when _T_2035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_54 node _T_2040 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_55 node _T_2044 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_56 node _T_2048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2049 = asUInt(reset) node _T_2050 = eq(_T_2049, UInt<1>(0h0)) when _T_2050 : node _T_2051 = eq(_T_2048, UInt<1>(0h0)) when _T_2051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2048, UInt<1>(0h1), "") : assert_57 node _T_2052 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2052 : node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_1, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(sink_ok, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2059 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(_T_2059, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2059, UInt<1>(0h1), "") : assert_60 node _T_2063 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_61 node _T_2067 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_62 node _T_2071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_63 node _T_2075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2076 = or(UInt<1>(0h1), _T_2075) node _T_2077 = asUInt(reset) node _T_2078 = eq(_T_2077, UInt<1>(0h0)) when _T_2078 : node _T_2079 = eq(_T_2076, UInt<1>(0h0)) when _T_2079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2076, UInt<1>(0h1), "") : assert_64 node _T_2080 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2080 : node _T_2081 = asUInt(reset) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) when _T_2082 : node _T_2083 = eq(source_ok_1, UInt<1>(0h0)) when _T_2083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2084 = asUInt(reset) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) when _T_2085 : node _T_2086 = eq(sink_ok, UInt<1>(0h0)) when _T_2086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2087 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2088 = asUInt(reset) node _T_2089 = eq(_T_2088, UInt<1>(0h0)) when _T_2089 : node _T_2090 = eq(_T_2087, UInt<1>(0h0)) when _T_2090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2087, UInt<1>(0h1), "") : assert_67 node _T_2091 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2092 = asUInt(reset) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) when _T_2093 : node _T_2094 = eq(_T_2091, UInt<1>(0h0)) when _T_2094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2091, UInt<1>(0h1), "") : assert_68 node _T_2095 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(_T_2095, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2095, UInt<1>(0h1), "") : assert_69 node _T_2099 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2100 = or(_T_2099, io.in.d.bits.corrupt) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_70 node _T_2104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2105 = or(UInt<1>(0h1), _T_2104) node _T_2106 = asUInt(reset) node _T_2107 = eq(_T_2106, UInt<1>(0h0)) when _T_2107 : node _T_2108 = eq(_T_2105, UInt<1>(0h0)) when _T_2108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2105, UInt<1>(0h1), "") : assert_71 node _T_2109 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2109 : node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_1, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2113 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_73 node _T_2117 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2118 = asUInt(reset) node _T_2119 = eq(_T_2118, UInt<1>(0h0)) when _T_2119 : node _T_2120 = eq(_T_2117, UInt<1>(0h0)) when _T_2120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2117, UInt<1>(0h1), "") : assert_74 node _T_2121 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2122 = or(UInt<1>(0h1), _T_2121) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_75 node _T_2126 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2126 : node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(source_ok_1, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2130 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_77 node _T_2134 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2135 = or(_T_2134, io.in.d.bits.corrupt) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_78 node _T_2139 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2140 = or(UInt<1>(0h1), _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_79 node _T_2144 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2144 : node _T_2145 = asUInt(reset) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) when _T_2146 : node _T_2147 = eq(source_ok_1, UInt<1>(0h0)) when _T_2147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2148 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2149 = asUInt(reset) node _T_2150 = eq(_T_2149, UInt<1>(0h0)) when _T_2150 : node _T_2151 = eq(_T_2148, UInt<1>(0h0)) when _T_2151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2148, UInt<1>(0h1), "") : assert_81 node _T_2152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_82 node _T_2156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2157 = or(UInt<1>(0h1), _T_2156) node _T_2158 = asUInt(reset) node _T_2159 = eq(_T_2158, UInt<1>(0h0)) when _T_2159 : node _T_2160 = eq(_T_2157, UInt<1>(0h0)) when _T_2160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2157, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2161 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2165 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2169 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(_T_2169, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2169, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2173 = eq(a_first, UInt<1>(0h0)) node _T_2174 = and(io.in.a.valid, _T_2173) when _T_2174 : node _T_2175 = eq(io.in.a.bits.opcode, opcode) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_87 node _T_2179 = eq(io.in.a.bits.param, param) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_88 node _T_2183 = eq(io.in.a.bits.size, size) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_89 node _T_2187 = eq(io.in.a.bits.source, source) node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(_T_2187, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2187, UInt<1>(0h1), "") : assert_90 node _T_2191 = eq(io.in.a.bits.address, address) node _T_2192 = asUInt(reset) node _T_2193 = eq(_T_2192, UInt<1>(0h0)) when _T_2193 : node _T_2194 = eq(_T_2191, UInt<1>(0h0)) when _T_2194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2191, UInt<1>(0h1), "") : assert_91 node _T_2195 = and(io.in.a.ready, io.in.a.valid) node _T_2196 = and(_T_2195, a_first) when _T_2196 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2197 = eq(d_first, UInt<1>(0h0)) node _T_2198 = and(io.in.d.valid, _T_2197) when _T_2198 : node _T_2199 = eq(io.in.d.bits.opcode, opcode_1) node _T_2200 = asUInt(reset) node _T_2201 = eq(_T_2200, UInt<1>(0h0)) when _T_2201 : node _T_2202 = eq(_T_2199, UInt<1>(0h0)) when _T_2202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2199, UInt<1>(0h1), "") : assert_92 node _T_2203 = eq(io.in.d.bits.param, param_1) node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : node _T_2206 = eq(_T_2203, UInt<1>(0h0)) when _T_2206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2203, UInt<1>(0h1), "") : assert_93 node _T_2207 = eq(io.in.d.bits.size, size_1) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(_T_2207, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2207, UInt<1>(0h1), "") : assert_94 node _T_2211 = eq(io.in.d.bits.source, source_1) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_95 node _T_2215 = eq(io.in.d.bits.sink, sink) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_96 node _T_2219 = eq(io.in.d.bits.denied, denied) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_97 node _T_2223 = and(io.in.d.ready, io.in.d.valid) node _T_2224 = and(_T_2223, d_first) when _T_2224 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<4104> connect a_sizes_set, UInt<4104>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2225 = and(io.in.a.valid, a_first_1) node _T_2226 = and(_T_2225, UInt<1>(0h1)) when _T_2226 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2227 = and(io.in.a.ready, io.in.a.valid) node _T_2228 = and(_T_2227, a_first_1) node _T_2229 = and(_T_2228, UInt<1>(0h1)) when _T_2229 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2230 = dshr(inflight, io.in.a.bits.source) node _T_2231 = bits(_T_2230, 0, 0) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<4104> connect d_sizes_clr, UInt<4104>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2236 = and(io.in.d.valid, d_first_1) node _T_2237 = and(_T_2236, UInt<1>(0h1)) node _T_2238 = eq(d_release_ack, UInt<1>(0h0)) node _T_2239 = and(_T_2237, _T_2238) when _T_2239 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2240 = and(io.in.d.ready, io.in.d.valid) node _T_2241 = and(_T_2240, d_first_1) node _T_2242 = and(_T_2241, UInt<1>(0h1)) node _T_2243 = eq(d_release_ack, UInt<1>(0h0)) node _T_2244 = and(_T_2242, _T_2243) when _T_2244 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2245 = and(io.in.d.valid, d_first_1) node _T_2246 = and(_T_2245, UInt<1>(0h1)) node _T_2247 = eq(d_release_ack, UInt<1>(0h0)) node _T_2248 = and(_T_2246, _T_2247) when _T_2248 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2249 = dshr(inflight, io.in.d.bits.source) node _T_2250 = bits(_T_2249, 0, 0) node _T_2251 = or(_T_2250, same_cycle_resp) node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(_T_2251, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2251, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2255 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2256 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2257 = or(_T_2255, _T_2256) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_100 node _T_2261 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_101 else : node _T_2265 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2266 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2267 = or(_T_2265, _T_2266) node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : node _T_2270 = eq(_T_2267, UInt<1>(0h0)) when _T_2270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2267, UInt<1>(0h1), "") : assert_102 node _T_2271 = eq(io.in.d.bits.size, a_size_lookup) node _T_2272 = asUInt(reset) node _T_2273 = eq(_T_2272, UInt<1>(0h0)) when _T_2273 : node _T_2274 = eq(_T_2271, UInt<1>(0h0)) when _T_2274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2271, UInt<1>(0h1), "") : assert_103 node _T_2275 = and(io.in.d.valid, d_first_1) node _T_2276 = and(_T_2275, a_first_1) node _T_2277 = and(_T_2276, io.in.a.valid) node _T_2278 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = eq(d_release_ack, UInt<1>(0h0)) node _T_2281 = and(_T_2279, _T_2280) when _T_2281 : node _T_2282 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2283 = or(_T_2282, io.in.a.ready) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_104 node _T_2287 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2288 = orr(a_set_wo_ready) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) node _T_2290 = or(_T_2287, _T_2289) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_2294 = orr(inflight) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) node _T_2296 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2297 = or(_T_2295, _T_2296) node _T_2298 = lt(watchdog, plusarg_reader.out) node _T_2299 = or(_T_2297, _T_2298) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2303 = and(io.in.a.ready, io.in.a.valid) node _T_2304 = and(io.in.d.ready, io.in.d.valid) node _T_2305 = or(_T_2303, _T_2304) when _T_2305 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<4104> connect c_sizes_set, UInt<4104>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2306 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2307 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2308 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2309 = and(_T_2307, _T_2308) node _T_2310 = and(_T_2306, _T_2309) when _T_2310 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2311 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2312 = and(_T_2311, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2313 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2314 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2315 = and(_T_2313, _T_2314) node _T_2316 = and(_T_2312, _T_2315) when _T_2316 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2317 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2318 = bits(_T_2317, 0, 0) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<4104> connect d_sizes_clr_1, UInt<4104>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2323 = and(io.in.d.valid, d_first_2) node _T_2324 = and(_T_2323, UInt<1>(0h1)) node _T_2325 = and(_T_2324, d_release_ack_1) when _T_2325 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2326 = and(io.in.d.ready, io.in.d.valid) node _T_2327 = and(_T_2326, d_first_2) node _T_2328 = and(_T_2327, UInt<1>(0h1)) node _T_2329 = and(_T_2328, d_release_ack_1) when _T_2329 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2330 = and(io.in.d.valid, d_first_2) node _T_2331 = and(_T_2330, UInt<1>(0h1)) node _T_2332 = and(_T_2331, d_release_ack_1) when _T_2332 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2333 = dshr(inflight_1, io.in.d.bits.source) node _T_2334 = bits(_T_2333, 0, 0) node _T_2335 = or(_T_2334, same_cycle_resp_1) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2339 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_109 else : node _T_2343 = eq(io.in.d.bits.size, c_size_lookup) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_110 node _T_2347 = and(io.in.d.valid, d_first_2) node _T_2348 = and(_T_2347, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2349 = and(_T_2348, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2350 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2351 = and(_T_2349, _T_2350) node _T_2352 = and(_T_2351, d_release_ack_1) node _T_2353 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2354 = and(_T_2352, _T_2353) when _T_2354 : node _T_2355 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2356 = or(_T_2355, _WIRE_27.ready) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_111 node _T_2360 = orr(c_set_wo_ready) when _T_2360 : node _T_2361 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_2365 = orr(inflight_1) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) node _T_2367 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2368 = or(_T_2366, _T_2367) node _T_2369 = lt(watchdog_1, plusarg_reader_1.out) node _T_2370 = or(_T_2368, _T_2369) node _T_2371 = asUInt(reset) node _T_2372 = eq(_T_2371, UInt<1>(0h0)) when _T_2372 : node _T_2373 = eq(_T_2370, UInt<1>(0h0)) when _T_2373 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_2370, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2374 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2375 = and(io.in.d.ready, io.in.d.valid) node _T_2376 = or(_T_2374, _T_2375) when _T_2376 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 5) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h1f)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 5) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h1f)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_24 = shr(io.in.a.bits.source, 5) node _source_ok_T_25 = eq(_source_ok_T_24, UInt<3>(0h4)) node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26) node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_30 = shr(io.in.a.bits.source, 5) node _source_ok_T_31 = eq(_source_ok_T_30, UInt<3>(0h5)) node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_36 = shr(io.in.a.bits.source, 5) node _source_ok_T_37 = eq(_source_ok_T_36, UInt<3>(0h6)) node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_42 = shr(io.in.a.bits.source, 5) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<3>(0h7)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 connect _source_ok_WIRE[4], _source_ok_T_29 connect _source_ok_WIRE[5], _source_ok_T_35 connect _source_ok_WIRE[6], _source_ok_T_41 connect _source_ok_WIRE[7], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_17 = shr(io.in.a.bits.source, 5) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_30 = shr(io.in.a.bits.source, 5) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_43 = shr(io.in.a.bits.source, 5) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_56 = shr(io.in.a.bits.source, 5) node _T_57 = eq(_T_56, UInt<3>(0h4)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_4) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<1>(0h0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_69 = shr(io.in.a.bits.source, 5) node _T_70 = eq(_T_69, UInt<3>(0h5)) node _T_71 = leq(UInt<1>(0h0), uncommonBits_5) node _T_72 = and(_T_70, _T_71) node _T_73 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = or(_T_75, _T_80) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_82 = shr(io.in.a.bits.source, 5) node _T_83 = eq(_T_82, UInt<3>(0h6)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_6) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(_T_87, UInt<1>(0h0)) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_95 = shr(io.in.a.bits.source, 5) node _T_96 = eq(_T_95, UInt<3>(0h7)) node _T_97 = leq(UInt<1>(0h0), uncommonBits_7) node _T_98 = and(_T_96, _T_97) node _T_99 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_100 = and(_T_98, _T_99) node _T_101 = eq(_T_100, UInt<1>(0h0)) node _T_102 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = or(_T_101, _T_106) node _T_108 = and(_T_16, _T_29) node _T_109 = and(_T_108, _T_42) node _T_110 = and(_T_109, _T_55) node _T_111 = and(_T_110, _T_68) node _T_112 = and(_T_111, _T_81) node _T_113 = and(_T_112, _T_94) node _T_114 = and(_T_113, _T_107) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_114, UInt<1>(0h1), "") : assert_1 node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_118 : node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_121 = and(_T_119, _T_120) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_122 = shr(io.in.a.bits.source, 5) node _T_123 = eq(_T_122, UInt<1>(0h0)) node _T_124 = leq(UInt<1>(0h0), uncommonBits_8) node _T_125 = and(_T_123, _T_124) node _T_126 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_127 = and(_T_125, _T_126) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_128 = shr(io.in.a.bits.source, 5) node _T_129 = eq(_T_128, UInt<1>(0h1)) node _T_130 = leq(UInt<1>(0h0), uncommonBits_9) node _T_131 = and(_T_129, _T_130) node _T_132 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_133 = and(_T_131, _T_132) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_134 = shr(io.in.a.bits.source, 5) node _T_135 = eq(_T_134, UInt<2>(0h2)) node _T_136 = leq(UInt<1>(0h0), uncommonBits_10) node _T_137 = and(_T_135, _T_136) node _T_138 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_139 = and(_T_137, _T_138) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<2>(0h3)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_11) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0) node _T_146 = shr(io.in.a.bits.source, 5) node _T_147 = eq(_T_146, UInt<3>(0h4)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_12) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_12, UInt<5>(0h1f)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<3>(0h5)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_13) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_13, UInt<5>(0h1f)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_158 = shr(io.in.a.bits.source, 5) node _T_159 = eq(_T_158, UInt<3>(0h6)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_14) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_163 = and(_T_161, _T_162) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_164 = shr(io.in.a.bits.source, 5) node _T_165 = eq(_T_164, UInt<3>(0h7)) node _T_166 = leq(UInt<1>(0h0), uncommonBits_15) node _T_167 = and(_T_165, _T_166) node _T_168 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(_T_127, _T_133) node _T_171 = or(_T_170, _T_139) node _T_172 = or(_T_171, _T_145) node _T_173 = or(_T_172, _T_151) node _T_174 = or(_T_173, _T_157) node _T_175 = or(_T_174, _T_163) node _T_176 = or(_T_175, _T_169) node _T_177 = and(_T_121, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<14>(0h2000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_191 = cvt(_T_190) node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000))) node _T_193 = asSInt(_T_192) node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0))) node _T_195 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<18>(0h2f000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_201 = cvt(_T_200) node _T_202 = and(_T_201, asSInt(UInt<17>(0h10000))) node _T_203 = asSInt(_T_202) node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<27>(0h4000000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<19>(0h40000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = or(_T_184, _T_189) node _T_226 = or(_T_225, _T_194) node _T_227 = or(_T_226, _T_199) node _T_228 = or(_T_227, _T_204) node _T_229 = or(_T_228, _T_209) node _T_230 = or(_T_229, _T_214) node _T_231 = or(_T_230, _T_219) node _T_232 = or(_T_231, _T_224) node _T_233 = and(_T_179, _T_232) node _T_234 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_235 = or(UInt<1>(0h0), _T_234) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<29>(0h10000000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_240, _T_245) node _T_247 = and(_T_235, _T_246) node _T_248 = or(UInt<1>(0h0), _T_233) node _T_249 = or(_T_248, _T_247) node _T_250 = and(_T_178, _T_249) node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(_T_250, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_250, UInt<1>(0h1), "") : assert_2 node _T_254 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_255 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_256 = and(_T_254, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<14>(0h2000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<13>(0h1000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<17>(0h10000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<18>(0h2f000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<17>(0h10000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<27>(0h4000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<19>(0h40000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_262, _T_267) node _T_314 = or(_T_313, _T_272) node _T_315 = or(_T_314, _T_277) node _T_316 = or(_T_315, _T_282) node _T_317 = or(_T_316, _T_287) node _T_318 = or(_T_317, _T_292) node _T_319 = or(_T_318, _T_297) node _T_320 = or(_T_319, _T_302) node _T_321 = or(_T_320, _T_307) node _T_322 = or(_T_321, _T_312) node _T_323 = and(_T_257, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = and(UInt<1>(0h0), _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_325, UInt<1>(0h1), "") : assert_3 node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(source_ok, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_332 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_332, UInt<1>(0h1), "") : assert_5 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(is_aligned, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_339 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_339, UInt<1>(0h1), "") : assert_7 node _T_343 = not(io.in.a.bits.mask) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_344, UInt<1>(0h1), "") : assert_8 node _T_348 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_348, UInt<1>(0h1), "") : assert_9 node _T_352 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_352 : node _T_353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_354 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_355 = and(_T_353, _T_354) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_356 = shr(io.in.a.bits.source, 5) node _T_357 = eq(_T_356, UInt<1>(0h0)) node _T_358 = leq(UInt<1>(0h0), uncommonBits_16) node _T_359 = and(_T_357, _T_358) node _T_360 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_361 = and(_T_359, _T_360) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_362 = shr(io.in.a.bits.source, 5) node _T_363 = eq(_T_362, UInt<1>(0h1)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_367 = and(_T_365, _T_366) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_368 = shr(io.in.a.bits.source, 5) node _T_369 = eq(_T_368, UInt<2>(0h2)) node _T_370 = leq(UInt<1>(0h0), uncommonBits_18) node _T_371 = and(_T_369, _T_370) node _T_372 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<2>(0h3)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_19) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_380 = shr(io.in.a.bits.source, 5) node _T_381 = eq(_T_380, UInt<3>(0h4)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_20) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_386 = shr(io.in.a.bits.source, 5) node _T_387 = eq(_T_386, UInt<3>(0h5)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_21) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_392 = shr(io.in.a.bits.source, 5) node _T_393 = eq(_T_392, UInt<3>(0h6)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_22) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_398 = shr(io.in.a.bits.source, 5) node _T_399 = eq(_T_398, UInt<3>(0h7)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_23) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(_T_361, _T_367) node _T_405 = or(_T_404, _T_373) node _T_406 = or(_T_405, _T_379) node _T_407 = or(_T_406, _T_385) node _T_408 = or(_T_407, _T_391) node _T_409 = or(_T_408, _T_397) node _T_410 = or(_T_409, _T_403) node _T_411 = and(_T_355, _T_410) node _T_412 = or(UInt<1>(0h0), _T_411) node _T_413 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<19>(0h40000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = or(_T_418, _T_423) node _T_460 = or(_T_459, _T_428) node _T_461 = or(_T_460, _T_433) node _T_462 = or(_T_461, _T_438) node _T_463 = or(_T_462, _T_443) node _T_464 = or(_T_463, _T_448) node _T_465 = or(_T_464, _T_453) node _T_466 = or(_T_465, _T_458) node _T_467 = and(_T_413, _T_466) node _T_468 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_469 = or(UInt<1>(0h0), _T_468) node _T_470 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<17>(0h10000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<29>(0h10000000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = or(_T_474, _T_479) node _T_481 = and(_T_469, _T_480) node _T_482 = or(UInt<1>(0h0), _T_467) node _T_483 = or(_T_482, _T_481) node _T_484 = and(_T_412, _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_484, UInt<1>(0h1), "") : assert_10 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<14>(0h2000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<17>(0h10000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<19>(0h40000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<29>(0h10000000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = or(_T_496, _T_501) node _T_548 = or(_T_547, _T_506) node _T_549 = or(_T_548, _T_511) node _T_550 = or(_T_549, _T_516) node _T_551 = or(_T_550, _T_521) node _T_552 = or(_T_551, _T_526) node _T_553 = or(_T_552, _T_531) node _T_554 = or(_T_553, _T_536) node _T_555 = or(_T_554, _T_541) node _T_556 = or(_T_555, _T_546) node _T_557 = and(_T_491, _T_556) node _T_558 = or(UInt<1>(0h0), _T_557) node _T_559 = and(UInt<1>(0h0), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_559, UInt<1>(0h1), "") : assert_11 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_566 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_566, UInt<1>(0h1), "") : assert_13 node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(is_aligned, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_573 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_573, UInt<1>(0h1), "") : assert_15 node _T_577 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_577, UInt<1>(0h1), "") : assert_16 node _T_581 = not(io.in.a.bits.mask) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_582, UInt<1>(0h1), "") : assert_17 node _T_586 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_586, UInt<1>(0h1), "") : assert_18 node _T_590 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_590 : node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0) node _T_594 = shr(io.in.a.bits.source, 5) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_24) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_24, UInt<5>(0h1f)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0) node _T_600 = shr(io.in.a.bits.source, 5) node _T_601 = eq(_T_600, UInt<1>(0h1)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_25) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_25, UInt<5>(0h1f)) node _T_605 = and(_T_603, _T_604) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0) node _T_606 = shr(io.in.a.bits.source, 5) node _T_607 = eq(_T_606, UInt<2>(0h2)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_26) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_26, UInt<5>(0h1f)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0) node _T_612 = shr(io.in.a.bits.source, 5) node _T_613 = eq(_T_612, UInt<2>(0h3)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_27) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_27, UInt<5>(0h1f)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_618 = shr(io.in.a.bits.source, 5) node _T_619 = eq(_T_618, UInt<3>(0h4)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_28) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_624 = shr(io.in.a.bits.source, 5) node _T_625 = eq(_T_624, UInt<3>(0h5)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_29) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_630 = shr(io.in.a.bits.source, 5) node _T_631 = eq(_T_630, UInt<3>(0h6)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_30) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_636 = shr(io.in.a.bits.source, 5) node _T_637 = eq(_T_636, UInt<3>(0h7)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_31) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_641 = and(_T_639, _T_640) node _T_642 = or(_T_599, _T_605) node _T_643 = or(_T_642, _T_611) node _T_644 = or(_T_643, _T_617) node _T_645 = or(_T_644, _T_623) node _T_646 = or(_T_645, _T_629) node _T_647 = or(_T_646, _T_635) node _T_648 = or(_T_647, _T_641) node _T_649 = and(_T_593, _T_648) node _T_650 = or(UInt<1>(0h0), _T_649) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_650, UInt<1>(0h1), "") : assert_19 node _T_654 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_655 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_656 = and(_T_654, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = and(_T_657, _T_662) node _T_664 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_665 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_666 = and(_T_664, _T_665) node _T_667 = or(UInt<1>(0h0), _T_666) node _T_668 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<14>(0h2000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<18>(0h2f000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<17>(0h10000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<13>(0h1000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<27>(0h4000000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<19>(0h40000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<29>(0h10000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = or(_T_672, _T_677) node _T_719 = or(_T_718, _T_682) node _T_720 = or(_T_719, _T_687) node _T_721 = or(_T_720, _T_692) node _T_722 = or(_T_721, _T_697) node _T_723 = or(_T_722, _T_702) node _T_724 = or(_T_723, _T_707) node _T_725 = or(_T_724, _T_712) node _T_726 = or(_T_725, _T_717) node _T_727 = and(_T_667, _T_726) node _T_728 = or(UInt<1>(0h0), _T_663) node _T_729 = or(_T_728, _T_727) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_729, UInt<1>(0h1), "") : assert_20 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(source_ok, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(is_aligned, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_739 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_739, UInt<1>(0h1), "") : assert_23 node _T_743 = eq(io.in.a.bits.mask, mask) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_743, UInt<1>(0h1), "") : assert_24 node _T_747 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_747, UInt<1>(0h1), "") : assert_25 node _T_751 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_751 : node _T_752 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_753 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_755 = shr(io.in.a.bits.source, 5) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_32) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_761 = shr(io.in.a.bits.source, 5) node _T_762 = eq(_T_761, UInt<1>(0h1)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_33) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_767 = shr(io.in.a.bits.source, 5) node _T_768 = eq(_T_767, UInt<2>(0h2)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_34) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_773 = shr(io.in.a.bits.source, 5) node _T_774 = eq(_T_773, UInt<2>(0h3)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_35) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_779 = shr(io.in.a.bits.source, 5) node _T_780 = eq(_T_779, UInt<3>(0h4)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_36) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_785 = shr(io.in.a.bits.source, 5) node _T_786 = eq(_T_785, UInt<3>(0h5)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_37) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_790 = and(_T_788, _T_789) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_791 = shr(io.in.a.bits.source, 5) node _T_792 = eq(_T_791, UInt<3>(0h6)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_38) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_797 = shr(io.in.a.bits.source, 5) node _T_798 = eq(_T_797, UInt<3>(0h7)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_39) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_802 = and(_T_800, _T_801) node _T_803 = or(_T_760, _T_766) node _T_804 = or(_T_803, _T_772) node _T_805 = or(_T_804, _T_778) node _T_806 = or(_T_805, _T_784) node _T_807 = or(_T_806, _T_790) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_802) node _T_810 = and(_T_754, _T_809) node _T_811 = or(UInt<1>(0h0), _T_810) node _T_812 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_813 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_814 = and(_T_812, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_817 = cvt(_T_816) node _T_818 = and(_T_817, asSInt(UInt<13>(0h1000))) node _T_819 = asSInt(_T_818) node _T_820 = eq(_T_819, asSInt(UInt<1>(0h0))) node _T_821 = and(_T_815, _T_820) node _T_822 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_823 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_824 = and(_T_822, _T_823) node _T_825 = or(UInt<1>(0h0), _T_824) node _T_826 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<14>(0h2000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_832 = cvt(_T_831) node _T_833 = and(_T_832, asSInt(UInt<18>(0h2f000))) node _T_834 = asSInt(_T_833) node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0))) node _T_836 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_837 = cvt(_T_836) node _T_838 = and(_T_837, asSInt(UInt<17>(0h10000))) node _T_839 = asSInt(_T_838) node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0))) node _T_841 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_842 = cvt(_T_841) node _T_843 = and(_T_842, asSInt(UInt<13>(0h1000))) node _T_844 = asSInt(_T_843) node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0))) node _T_846 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<27>(0h4000000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<19>(0h40000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<29>(0h10000000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = or(_T_830, _T_835) node _T_872 = or(_T_871, _T_840) node _T_873 = or(_T_872, _T_845) node _T_874 = or(_T_873, _T_850) node _T_875 = or(_T_874, _T_855) node _T_876 = or(_T_875, _T_860) node _T_877 = or(_T_876, _T_865) node _T_878 = or(_T_877, _T_870) node _T_879 = and(_T_825, _T_878) node _T_880 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_881 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = and(_T_880, _T_885) node _T_887 = or(UInt<1>(0h0), _T_821) node _T_888 = or(_T_887, _T_879) node _T_889 = or(_T_888, _T_886) node _T_890 = and(_T_811, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_890, UInt<1>(0h1), "") : assert_26 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_900 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_900, UInt<1>(0h1), "") : assert_29 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_904, UInt<1>(0h1), "") : assert_30 node _T_908 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_908 : node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_911 = and(_T_909, _T_910) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_912 = shr(io.in.a.bits.source, 5) node _T_913 = eq(_T_912, UInt<1>(0h0)) node _T_914 = leq(UInt<1>(0h0), uncommonBits_40) node _T_915 = and(_T_913, _T_914) node _T_916 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_917 = and(_T_915, _T_916) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_918 = shr(io.in.a.bits.source, 5) node _T_919 = eq(_T_918, UInt<1>(0h1)) node _T_920 = leq(UInt<1>(0h0), uncommonBits_41) node _T_921 = and(_T_919, _T_920) node _T_922 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_923 = and(_T_921, _T_922) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_924 = shr(io.in.a.bits.source, 5) node _T_925 = eq(_T_924, UInt<2>(0h2)) node _T_926 = leq(UInt<1>(0h0), uncommonBits_42) node _T_927 = and(_T_925, _T_926) node _T_928 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_929 = and(_T_927, _T_928) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_930 = shr(io.in.a.bits.source, 5) node _T_931 = eq(_T_930, UInt<2>(0h3)) node _T_932 = leq(UInt<1>(0h0), uncommonBits_43) node _T_933 = and(_T_931, _T_932) node _T_934 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_935 = and(_T_933, _T_934) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_936 = shr(io.in.a.bits.source, 5) node _T_937 = eq(_T_936, UInt<3>(0h4)) node _T_938 = leq(UInt<1>(0h0), uncommonBits_44) node _T_939 = and(_T_937, _T_938) node _T_940 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_941 = and(_T_939, _T_940) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_942 = shr(io.in.a.bits.source, 5) node _T_943 = eq(_T_942, UInt<3>(0h5)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_45) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_948 = shr(io.in.a.bits.source, 5) node _T_949 = eq(_T_948, UInt<3>(0h6)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_46) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_954 = shr(io.in.a.bits.source, 5) node _T_955 = eq(_T_954, UInt<3>(0h7)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_47) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_959 = and(_T_957, _T_958) node _T_960 = or(_T_917, _T_923) node _T_961 = or(_T_960, _T_929) node _T_962 = or(_T_961, _T_935) node _T_963 = or(_T_962, _T_941) node _T_964 = or(_T_963, _T_947) node _T_965 = or(_T_964, _T_953) node _T_966 = or(_T_965, _T_959) node _T_967 = and(_T_911, _T_966) node _T_968 = or(UInt<1>(0h0), _T_967) node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_971 = and(_T_969, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<13>(0h1000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = and(_T_972, _T_977) node _T_979 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_980 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_981 = and(_T_979, _T_980) node _T_982 = or(UInt<1>(0h0), _T_981) node _T_983 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<14>(0h2000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_989 = cvt(_T_988) node _T_990 = and(_T_989, asSInt(UInt<18>(0h2f000))) node _T_991 = asSInt(_T_990) node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0))) node _T_993 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_994 = cvt(_T_993) node _T_995 = and(_T_994, asSInt(UInt<17>(0h10000))) node _T_996 = asSInt(_T_995) node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0))) node _T_998 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1004 = cvt(_T_1003) node _T_1005 = and(_T_1004, asSInt(UInt<17>(0h10000))) node _T_1006 = asSInt(_T_1005) node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0))) node _T_1008 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<27>(0h4000000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<19>(0h40000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<29>(0h10000000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = or(_T_987, _T_992) node _T_1029 = or(_T_1028, _T_997) node _T_1030 = or(_T_1029, _T_1002) node _T_1031 = or(_T_1030, _T_1007) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1017) node _T_1034 = or(_T_1033, _T_1022) node _T_1035 = or(_T_1034, _T_1027) node _T_1036 = and(_T_982, _T_1035) node _T_1037 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1038 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<17>(0h10000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = and(_T_1037, _T_1042) node _T_1044 = or(UInt<1>(0h0), _T_978) node _T_1045 = or(_T_1044, _T_1036) node _T_1046 = or(_T_1045, _T_1043) node _T_1047 = and(_T_968, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_31 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1057 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_34 node _T_1061 = not(mask) node _T_1062 = and(io.in.a.bits.mask, _T_1061) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_35 node _T_1067 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1067 : node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1070 = and(_T_1068, _T_1069) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0) node _T_1071 = shr(io.in.a.bits.source, 5) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1074 = and(_T_1072, _T_1073) node _T_1075 = leq(uncommonBits_48, UInt<5>(0h1f)) node _T_1076 = and(_T_1074, _T_1075) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0) node _T_1077 = shr(io.in.a.bits.source, 5) node _T_1078 = eq(_T_1077, UInt<1>(0h1)) node _T_1079 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = leq(uncommonBits_49, UInt<5>(0h1f)) node _T_1082 = and(_T_1080, _T_1081) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_1083 = shr(io.in.a.bits.source, 5) node _T_1084 = eq(_T_1083, UInt<2>(0h2)) node _T_1085 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_1088 = and(_T_1086, _T_1087) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_1089 = shr(io.in.a.bits.source, 5) node _T_1090 = eq(_T_1089, UInt<2>(0h3)) node _T_1091 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_1094 = and(_T_1092, _T_1093) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_1095 = shr(io.in.a.bits.source, 5) node _T_1096 = eq(_T_1095, UInt<3>(0h4)) node _T_1097 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1098 = and(_T_1096, _T_1097) node _T_1099 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_1100 = and(_T_1098, _T_1099) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_1101 = shr(io.in.a.bits.source, 5) node _T_1102 = eq(_T_1101, UInt<3>(0h5)) node _T_1103 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1104 = and(_T_1102, _T_1103) node _T_1105 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_1106 = and(_T_1104, _T_1105) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_1107 = shr(io.in.a.bits.source, 5) node _T_1108 = eq(_T_1107, UInt<3>(0h6)) node _T_1109 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_1112 = and(_T_1110, _T_1111) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_1113 = shr(io.in.a.bits.source, 5) node _T_1114 = eq(_T_1113, UInt<3>(0h7)) node _T_1115 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = or(_T_1076, _T_1082) node _T_1120 = or(_T_1119, _T_1088) node _T_1121 = or(_T_1120, _T_1094) node _T_1122 = or(_T_1121, _T_1100) node _T_1123 = or(_T_1122, _T_1106) node _T_1124 = or(_T_1123, _T_1112) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = and(_T_1070, _T_1125) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1129 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = or(UInt<1>(0h0), _T_1130) node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<14>(0h2000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<17>(0h10000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<27>(0h4000000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<19>(0h40000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<29>(0h10000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = or(_T_1136, _T_1141) node _T_1183 = or(_T_1182, _T_1146) node _T_1184 = or(_T_1183, _T_1151) node _T_1185 = or(_T_1184, _T_1156) node _T_1186 = or(_T_1185, _T_1161) node _T_1187 = or(_T_1186, _T_1166) node _T_1188 = or(_T_1187, _T_1171) node _T_1189 = or(_T_1188, _T_1176) node _T_1190 = or(_T_1189, _T_1181) node _T_1191 = and(_T_1131, _T_1190) node _T_1192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<17>(0h10000))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = and(_T_1192, _T_1197) node _T_1199 = or(UInt<1>(0h0), _T_1191) node _T_1200 = or(_T_1199, _T_1198) node _T_1201 = and(_T_1127, _T_1200) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_36 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(source_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(is_aligned, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1211 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_39 node _T_1215 = eq(io.in.a.bits.mask, mask) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_40 node _T_1219 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1219 : node _T_1220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1222 = and(_T_1220, _T_1221) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_1223 = shr(io.in.a.bits.source, 5) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) node _T_1225 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_1228 = and(_T_1226, _T_1227) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_1229 = shr(io.in.a.bits.source, 5) node _T_1230 = eq(_T_1229, UInt<1>(0h1)) node _T_1231 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1232 = and(_T_1230, _T_1231) node _T_1233 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_1234 = and(_T_1232, _T_1233) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_1235 = shr(io.in.a.bits.source, 5) node _T_1236 = eq(_T_1235, UInt<2>(0h2)) node _T_1237 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1238 = and(_T_1236, _T_1237) node _T_1239 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_1240 = and(_T_1238, _T_1239) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_1241 = shr(io.in.a.bits.source, 5) node _T_1242 = eq(_T_1241, UInt<2>(0h3)) node _T_1243 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1244 = and(_T_1242, _T_1243) node _T_1245 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_1246 = and(_T_1244, _T_1245) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_1247 = shr(io.in.a.bits.source, 5) node _T_1248 = eq(_T_1247, UInt<3>(0h4)) node _T_1249 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1250 = and(_T_1248, _T_1249) node _T_1251 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_1252 = and(_T_1250, _T_1251) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_1253 = shr(io.in.a.bits.source, 5) node _T_1254 = eq(_T_1253, UInt<3>(0h5)) node _T_1255 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1256 = and(_T_1254, _T_1255) node _T_1257 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_1258 = and(_T_1256, _T_1257) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_1259 = shr(io.in.a.bits.source, 5) node _T_1260 = eq(_T_1259, UInt<3>(0h6)) node _T_1261 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_1264 = and(_T_1262, _T_1263) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_1265 = shr(io.in.a.bits.source, 5) node _T_1266 = eq(_T_1265, UInt<3>(0h7)) node _T_1267 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = or(_T_1228, _T_1234) node _T_1272 = or(_T_1271, _T_1240) node _T_1273 = or(_T_1272, _T_1246) node _T_1274 = or(_T_1273, _T_1252) node _T_1275 = or(_T_1274, _T_1258) node _T_1276 = or(_T_1275, _T_1264) node _T_1277 = or(_T_1276, _T_1270) node _T_1278 = and(_T_1222, _T_1277) node _T_1279 = or(UInt<1>(0h0), _T_1278) node _T_1280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1281 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1285 = cvt(_T_1284) node _T_1286 = and(_T_1285, asSInt(UInt<14>(0h2000))) node _T_1287 = asSInt(_T_1286) node _T_1288 = eq(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1290 = cvt(_T_1289) node _T_1291 = and(_T_1290, asSInt(UInt<13>(0h1000))) node _T_1292 = asSInt(_T_1291) node _T_1293 = eq(_T_1292, asSInt(UInt<1>(0h0))) node _T_1294 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<18>(0h2f000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1300 = cvt(_T_1299) node _T_1301 = and(_T_1300, asSInt(UInt<17>(0h10000))) node _T_1302 = asSInt(_T_1301) node _T_1303 = eq(_T_1302, asSInt(UInt<1>(0h0))) node _T_1304 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1305 = cvt(_T_1304) node _T_1306 = and(_T_1305, asSInt(UInt<13>(0h1000))) node _T_1307 = asSInt(_T_1306) node _T_1308 = eq(_T_1307, asSInt(UInt<1>(0h0))) node _T_1309 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1310 = cvt(_T_1309) node _T_1311 = and(_T_1310, asSInt(UInt<17>(0h10000))) node _T_1312 = asSInt(_T_1311) node _T_1313 = eq(_T_1312, asSInt(UInt<1>(0h0))) node _T_1314 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<27>(0h4000000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<19>(0h40000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<29>(0h10000000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = or(_T_1288, _T_1293) node _T_1335 = or(_T_1334, _T_1298) node _T_1336 = or(_T_1335, _T_1303) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1313) node _T_1339 = or(_T_1338, _T_1318) node _T_1340 = or(_T_1339, _T_1323) node _T_1341 = or(_T_1340, _T_1328) node _T_1342 = or(_T_1341, _T_1333) node _T_1343 = and(_T_1283, _T_1342) node _T_1344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<17>(0h10000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = and(_T_1344, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1343) node _T_1352 = or(_T_1351, _T_1350) node _T_1353 = and(_T_1279, _T_1352) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_41 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1363 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_44 node _T_1367 = eq(io.in.a.bits.mask, mask) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_45 node _T_1371 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1371 : node _T_1372 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1373 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1374 = and(_T_1372, _T_1373) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_1375 = shr(io.in.a.bits.source, 5) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_1381 = shr(io.in.a.bits.source, 5) node _T_1382 = eq(_T_1381, UInt<1>(0h1)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_1386 = and(_T_1384, _T_1385) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_1387 = shr(io.in.a.bits.source, 5) node _T_1388 = eq(_T_1387, UInt<2>(0h2)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_1393 = shr(io.in.a.bits.source, 5) node _T_1394 = eq(_T_1393, UInt<2>(0h3)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_1399 = shr(io.in.a.bits.source, 5) node _T_1400 = eq(_T_1399, UInt<3>(0h4)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_1405 = shr(io.in.a.bits.source, 5) node _T_1406 = eq(_T_1405, UInt<3>(0h5)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1410 = and(_T_1408, _T_1409) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1411 = shr(io.in.a.bits.source, 5) node _T_1412 = eq(_T_1411, UInt<3>(0h6)) node _T_1413 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1416 = and(_T_1414, _T_1415) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1417 = shr(io.in.a.bits.source, 5) node _T_1418 = eq(_T_1417, UInt<3>(0h7)) node _T_1419 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1422 = and(_T_1420, _T_1421) node _T_1423 = or(_T_1380, _T_1386) node _T_1424 = or(_T_1423, _T_1392) node _T_1425 = or(_T_1424, _T_1398) node _T_1426 = or(_T_1425, _T_1404) node _T_1427 = or(_T_1426, _T_1410) node _T_1428 = or(_T_1427, _T_1416) node _T_1429 = or(_T_1428, _T_1422) node _T_1430 = and(_T_1374, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1433 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = and(_T_1435, _T_1440) node _T_1442 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1443 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<14>(0h2000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<17>(0h10000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1454 = cvt(_T_1453) node _T_1455 = and(_T_1454, asSInt(UInt<18>(0h2f000))) node _T_1456 = asSInt(_T_1455) node _T_1457 = eq(_T_1456, asSInt(UInt<1>(0h0))) node _T_1458 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1459 = cvt(_T_1458) node _T_1460 = and(_T_1459, asSInt(UInt<17>(0h10000))) node _T_1461 = asSInt(_T_1460) node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) node _T_1463 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1464 = cvt(_T_1463) node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) node _T_1466 = asSInt(_T_1465) node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) node _T_1468 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1469 = cvt(_T_1468) node _T_1470 = and(_T_1469, asSInt(UInt<27>(0h4000000))) node _T_1471 = asSInt(_T_1470) node _T_1472 = eq(_T_1471, asSInt(UInt<1>(0h0))) node _T_1473 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1474 = cvt(_T_1473) node _T_1475 = and(_T_1474, asSInt(UInt<13>(0h1000))) node _T_1476 = asSInt(_T_1475) node _T_1477 = eq(_T_1476, asSInt(UInt<1>(0h0))) node _T_1478 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1479 = cvt(_T_1478) node _T_1480 = and(_T_1479, asSInt(UInt<19>(0h40000))) node _T_1481 = asSInt(_T_1480) node _T_1482 = eq(_T_1481, asSInt(UInt<1>(0h0))) node _T_1483 = or(_T_1447, _T_1452) node _T_1484 = or(_T_1483, _T_1457) node _T_1485 = or(_T_1484, _T_1462) node _T_1486 = or(_T_1485, _T_1467) node _T_1487 = or(_T_1486, _T_1472) node _T_1488 = or(_T_1487, _T_1477) node _T_1489 = or(_T_1488, _T_1482) node _T_1490 = and(_T_1442, _T_1489) node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h10000))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h10000000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1441) node _T_1508 = or(_T_1507, _T_1490) node _T_1509 = or(_T_1508, _T_1506) node _T_1510 = and(_T_1431, _T_1509) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_46 node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(source_ok, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(is_aligned, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1520 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_49 node _T_1524 = eq(io.in.a.bits.mask, mask) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_50 node _T_1528 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1532 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 5) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<1>(0h0)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 5) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<1>(0h1)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 5) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<2>(0h2)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 5) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<2>(0h3)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 5) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<3>(0h4)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h1f)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 5) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<3>(0h5)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h1f)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 5) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<3>(0h6)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_96 = shr(io.in.d.bits.source, 5) node _source_ok_T_97 = eq(_source_ok_T_96, UInt<3>(0h7)) node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98) node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_59 connect _source_ok_WIRE_1[1], _source_ok_T_65 connect _source_ok_WIRE_1[2], _source_ok_T_71 connect _source_ok_WIRE_1[3], _source_ok_T_77 connect _source_ok_WIRE_1[4], _source_ok_T_83 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_95 connect _source_ok_WIRE_1[7], _source_ok_T_101 node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1536 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1536 : node _T_1537 = asUInt(reset) node _T_1538 = eq(_T_1537, UInt<1>(0h0)) when _T_1538 : node _T_1539 = eq(source_ok_1, UInt<1>(0h0)) when _T_1539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1540 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(_T_1540, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1540, UInt<1>(0h1), "") : assert_54 node _T_1544 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_55 node _T_1548 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_56 node _T_1552 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_57 node _T_1556 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1556 : node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(source_ok_1, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(sink_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1563 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_60 node _T_1567 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_61 node _T_1571 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_62 node _T_1575 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_63 node _T_1579 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1580 = or(UInt<1>(0h1), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_64 node _T_1584 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1584 : node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(source_ok_1, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(sink_ok, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1591 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_67 node _T_1595 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_68 node _T_1599 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_69 node _T_1603 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1604 = or(_T_1603, io.in.d.bits.corrupt) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_70 node _T_1608 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1609 = or(UInt<1>(0h1), _T_1608) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_71 node _T_1613 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1613 : node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(source_ok_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1617 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_73 node _T_1621 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_74 node _T_1625 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1626 = or(UInt<1>(0h1), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_75 node _T_1630 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1630 : node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(source_ok_1, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1634 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(_T_1634, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1634, UInt<1>(0h1), "") : assert_77 node _T_1638 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1639 = or(_T_1638, io.in.d.bits.corrupt) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_78 node _T_1643 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1644 = or(UInt<1>(0h1), _T_1643) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_79 node _T_1648 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1648 : node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(source_ok_1, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1652 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(_T_1652, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1652, UInt<1>(0h1), "") : assert_81 node _T_1656 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_82 node _T_1660 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1661 = or(UInt<1>(0h1), _T_1660) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1665 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1669 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1673 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1677 = eq(a_first, UInt<1>(0h0)) node _T_1678 = and(io.in.a.valid, _T_1677) when _T_1678 : node _T_1679 = eq(io.in.a.bits.opcode, opcode) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_87 node _T_1683 = eq(io.in.a.bits.param, param) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_88 node _T_1687 = eq(io.in.a.bits.size, size) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_89 node _T_1691 = eq(io.in.a.bits.source, source) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_90 node _T_1695 = eq(io.in.a.bits.address, address) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_91 node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first) when _T_1700 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1701 = eq(d_first, UInt<1>(0h0)) node _T_1702 = and(io.in.d.valid, _T_1701) when _T_1702 : node _T_1703 = eq(io.in.d.bits.opcode, opcode_1) node _T_1704 = asUInt(reset) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) when _T_1705 : node _T_1706 = eq(_T_1703, UInt<1>(0h0)) when _T_1706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1703, UInt<1>(0h1), "") : assert_92 node _T_1707 = eq(io.in.d.bits.param, param_1) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_93 node _T_1711 = eq(io.in.d.bits.size, size_1) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_94 node _T_1715 = eq(io.in.d.bits.source, source_1) node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(_T_1715, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1715, UInt<1>(0h1), "") : assert_95 node _T_1719 = eq(io.in.d.bits.sink, sink) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_96 node _T_1723 = eq(io.in.d.bits.denied, denied) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_97 node _T_1727 = and(io.in.d.ready, io.in.d.valid) node _T_1728 = and(_T_1727, d_first) when _T_1728 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes : UInt<2048>, clock, reset, UInt<2048>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<256> connect a_set, UInt<256>(0h0) wire a_set_wo_ready : UInt<256> connect a_set_wo_ready, UInt<256>(0h0) wire a_opcodes_set : UInt<1024> connect a_opcodes_set, UInt<1024>(0h0) wire a_sizes_set : UInt<2048> connect a_sizes_set, UInt<2048>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1729 = and(io.in.a.valid, a_first_1) node _T_1730 = and(_T_1729, UInt<1>(0h1)) when _T_1730 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1731 = and(io.in.a.ready, io.in.a.valid) node _T_1732 = and(_T_1731, a_first_1) node _T_1733 = and(_T_1732, UInt<1>(0h1)) when _T_1733 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1734 = dshr(inflight, io.in.a.bits.source) node _T_1735 = bits(_T_1734, 0, 0) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<256> connect d_clr, UInt<256>(0h0) wire d_clr_wo_ready : UInt<256> connect d_clr_wo_ready, UInt<256>(0h0) wire d_opcodes_clr : UInt<1024> connect d_opcodes_clr, UInt<1024>(0h0) wire d_sizes_clr : UInt<2048> connect d_sizes_clr, UInt<2048>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1740 = and(io.in.d.valid, d_first_1) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = eq(d_release_ack, UInt<1>(0h0)) node _T_1743 = and(_T_1741, _T_1742) when _T_1743 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1744 = and(io.in.d.ready, io.in.d.valid) node _T_1745 = and(_T_1744, d_first_1) node _T_1746 = and(_T_1745, UInt<1>(0h1)) node _T_1747 = eq(d_release_ack, UInt<1>(0h0)) node _T_1748 = and(_T_1746, _T_1747) when _T_1748 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1749 = and(io.in.d.valid, d_first_1) node _T_1750 = and(_T_1749, UInt<1>(0h1)) node _T_1751 = eq(d_release_ack, UInt<1>(0h0)) node _T_1752 = and(_T_1750, _T_1751) when _T_1752 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1753 = dshr(inflight, io.in.d.bits.source) node _T_1754 = bits(_T_1753, 0, 0) node _T_1755 = or(_T_1754, same_cycle_resp) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1759 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1760 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = asUInt(reset) node _T_1763 = eq(_T_1762, UInt<1>(0h0)) when _T_1763 : node _T_1764 = eq(_T_1761, UInt<1>(0h0)) when _T_1764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1761, UInt<1>(0h1), "") : assert_100 node _T_1765 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_101 else : node _T_1769 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1770 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_102 node _T_1775 = eq(io.in.d.bits.size, a_size_lookup) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_103 node _T_1779 = and(io.in.d.valid, d_first_1) node _T_1780 = and(_T_1779, a_first_1) node _T_1781 = and(_T_1780, io.in.a.valid) node _T_1782 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1783 = and(_T_1781, _T_1782) node _T_1784 = eq(d_release_ack, UInt<1>(0h0)) node _T_1785 = and(_T_1783, _T_1784) when _T_1785 : node _T_1786 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1787 = or(_T_1786, io.in.a.ready) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_104 node _T_1791 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1792 = orr(a_set_wo_ready) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = or(_T_1791, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_131 node _T_1798 = orr(inflight) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1801 = or(_T_1799, _T_1800) node _T_1802 = lt(watchdog, plusarg_reader.out) node _T_1803 = or(_T_1801, _T_1802) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1807 = and(io.in.a.ready, io.in.a.valid) node _T_1808 = and(io.in.d.ready, io.in.d.valid) node _T_1809 = or(_T_1807, _T_1808) when _T_1809 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes_1 : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes_1 : UInt<2048>, clock, reset, UInt<2048>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<256> connect c_set, UInt<256>(0h0) wire c_set_wo_ready : UInt<256> connect c_set_wo_ready, UInt<256>(0h0) wire c_opcodes_set : UInt<1024> connect c_opcodes_set, UInt<1024>(0h0) wire c_sizes_set : UInt<2048> connect c_sizes_set, UInt<2048>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1810 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1811 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1812 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1813 = and(_T_1811, _T_1812) node _T_1814 = and(_T_1810, _T_1813) when _T_1814 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1815 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1816 = and(_T_1815, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1817 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1818 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = and(_T_1816, _T_1819) when _T_1820 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1821 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1822 = bits(_T_1821, 0, 0) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(_T_1823, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1823, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<256> connect d_clr_1, UInt<256>(0h0) wire d_clr_wo_ready_1 : UInt<256> connect d_clr_wo_ready_1, UInt<256>(0h0) wire d_opcodes_clr_1 : UInt<1024> connect d_opcodes_clr_1, UInt<1024>(0h0) wire d_sizes_clr_1 : UInt<2048> connect d_sizes_clr_1, UInt<2048>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1827 = and(io.in.d.valid, d_first_2) node _T_1828 = and(_T_1827, UInt<1>(0h1)) node _T_1829 = and(_T_1828, d_release_ack_1) when _T_1829 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1830 = and(io.in.d.ready, io.in.d.valid) node _T_1831 = and(_T_1830, d_first_2) node _T_1832 = and(_T_1831, UInt<1>(0h1)) node _T_1833 = and(_T_1832, d_release_ack_1) when _T_1833 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1834 = and(io.in.d.valid, d_first_2) node _T_1835 = and(_T_1834, UInt<1>(0h1)) node _T_1836 = and(_T_1835, d_release_ack_1) when _T_1836 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1837 = dshr(inflight_1, io.in.d.bits.source) node _T_1838 = bits(_T_1837, 0, 0) node _T_1839 = or(_T_1838, same_cycle_resp_1) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1843 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_109 else : node _T_1847 = eq(io.in.d.bits.size, c_size_lookup) node _T_1848 = asUInt(reset) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) when _T_1849 : node _T_1850 = eq(_T_1847, UInt<1>(0h0)) when _T_1850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1847, UInt<1>(0h1), "") : assert_110 node _T_1851 = and(io.in.d.valid, d_first_2) node _T_1852 = and(_T_1851, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1853 = and(_T_1852, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1854 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1855 = and(_T_1853, _T_1854) node _T_1856 = and(_T_1855, d_release_ack_1) node _T_1857 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1858 = and(_T_1856, _T_1857) when _T_1858 : node _T_1859 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1860 = or(_T_1859, _WIRE_23.ready) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_111 node _T_1864 = orr(c_set_wo_ready) when _T_1864 : node _T_1865 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_132 node _T_1869 = orr(inflight_1) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) node _T_1871 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1872 = or(_T_1870, _T_1871) node _T_1873 = lt(watchdog_1, plusarg_reader_1.out) node _T_1874 = or(_T_1872, _T_1873) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1878 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1879 = and(io.in.d.ready, io.in.d.valid) node _T_1880 = or(_T_1878, _T_1879) when _T_1880 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [255:0] inflight; // @[Monitor.scala:614:27] reg [1023:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2047:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [255:0] inflight_1; // @[Monitor.scala:726:35] reg [2047:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e8_s24( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire roundingMode_min = io_roundingMode == 3'h2; // @[MulAddRecFN.scala:186:45] wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:190:42] wire [25:0] _sigSum_T_3 = io_mulAddResult[48] ? io_fromPreMul_highAlignedSigC + 26'h1 : io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:192:{16,32}, :193:47] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[47:24]} : {1'h0, io_fromPreMul_highAlignedSigC[25:24], _sigSum_T_3[23:0], io_mulAddResult[47:25]}; // @[MulAddRecFN.scala:192:16, :205:12, :206:{13,20}, :209:{46,71}, :210:23] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:205:12, :219:24] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2])); // @[primitives.scala:52:21, :76:56] wire [50:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + {50'h0, io_fromPreMul_doSubMags}; // @[MulAddRecFN.scala:192:16, :196:28, :232:36, :234:12, :235:{13,20}, :236:41] wire [4:0] notCDom_normDistReduced2 = notCDom_absSigSum[50] ? 5'h0 : (\|(notCDom_absSigSum[49:48])) ? 5'h1 : (\|(notCDom_absSigSum[47:46])) ? 5'h2 : (\|(notCDom_absSigSum[45:44])) ? 5'h3 : (\|(notCDom_absSigSum[43:42])) ? 5'h4 : (\|(notCDom_absSigSum[41:40])) ? 5'h5 : (\|(notCDom_absSigSum[39:38])) ? 5'h6 : (\|(notCDom_absSigSum[37:36])) ? 5'h7 : (\|(notCDom_absSigSum[35:34])) ? 5'h8 : (\|(notCDom_absSigSum[33:32])) ? 5'h9 : (\|(notCDom_absSigSum[31:30])) ? 5'hA : (\|(notCDom_absSigSum[29:28])) ? 5'hB : (\|(notCDom_absSigSum[27:26])) ? 5'hC : (\|(notCDom_absSigSum[25:24])) ? 5'hD : (\|(notCDom_absSigSum[23:22])) ? 5'hE : (\|(notCDom_absSigSum[21:20])) ? 5'hF : (\|(notCDom_absSigSum[19:18])) ? 5'h10 : (\|(notCDom_absSigSum[17:16])) ? 5'h11 : (\|(notCDom_absSigSum[15:14])) ? 5'h12 : (\|(notCDom_absSigSum[13:12])) ? 5'h13 : (\|(notCDom_absSigSum[11:10])) ? 5'h14 : (\|(notCDom_absSigSum[9:8])) ? 5'h15 : (\|(notCDom_absSigSum[7:6])) ? 5'h16 : (\|(notCDom_absSigSum[5:4])) ? 5'h17 : {4'hC, ~(\|(notCDom_absSigSum[3:2]))}; // @[Mux.scala:50:70] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1])); // @[Mux.scala:50:70] wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0; // @[primitives.scala:103:54] wire notNaN_isInfProd = io_fromPreMul_isInfA \| io_fromPreMul_isInfB; // @[MulAddRecFN.scala:264:49] wire notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC; // @[MulAddRecFN.scala:264:49, :265:44] wire notNaN_addZeros = (io_fromPreMul_isZeroA \| io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:267:{32,58}] assign io_invalidExc = io_fromPreMul_isSigNaNAny \| io_fromPreMul_isInfA & io_fromPreMul_isZeroB \| io_fromPreMul_isZeroA & io_fromPreMul_isInfB \| ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7, :264:49, :271:35, :272:{31,57}, :273:{32,57}, :274:{10,36}, :275:61, :276:35] assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB \| io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isInf = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] assign io_rawOut_isZero = notNaN_addZeros \| ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; // @[MulAddRecFN.scala:169:7, :255:50, :267:58, :282:25, :283:{14,42}] assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd \| io_fromPreMul_isInfC & opSignC \| notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC \| notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd \| opSignC) \| ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]); // @[MulAddRecFN.scala:169:7, :186:45, :190:42, :192:16, :232:36, :255:50, :257:12, :259:36, :264:49, :265:44, :267:58, :285:{27,54}, :286:{31,43}, :287:{26,29,48}, :288:{36,48}, :289:{26,46}, :290:{37,50}, :291:{10,28,31,49}, :292:17] assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[49:24], (\|{_CDom_mainSig_T[23:21], {\|(CDom_absSigSum[20:17]), \|(CDom_absSigSum[16:13]), \|(CDom_absSigSum[12:9]), \|(CDom_absSigSum[8:5]), \|(CDom_absSigSum[4:1]), CDom_absSigSum[0]} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6]}}) \| (io_fromPreMul_doSubMags ? io_mulAddResult[23:0] != 24'hFFFFFF : (\|(io_mulAddResult[24:0])))} : {_notCDom_mainSig_T[51:26], \|{_notCDom_mainSig_T[25:23], {\|{\|(notCDom_absSigSum[23:22]), \|(notCDom_absSigSum[21:20])}, \|{\|(notCDom_absSigSum[19:18]), \|(notCDom_absSigSum[17:16])}, \|{\|(notCDom_absSigSum[15:14]), \|(notCDom_absSigSum[13:12])}, \|{\|(notCDom_absSigSum[11:10]), \|(notCDom_absSigSum[9:8])}, \|{\|(notCDom_absSigSum[7:6]), \|(notCDom_absSigSum[5:4])}, \|{\|(notCDom_absSigSum[3:2]), \|(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6]}}}; // @[primitives.scala:76:56, :77:20, :78:22, :103:{33,54}, :120:{33,54}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_13 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_13( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_57 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_57( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module PE_443 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_187 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_443( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_187 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_3 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_3( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControlRemapper_2 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn	module ReRoCCManagerControlRemapper_2( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_109 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_109( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_147 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_162 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_147( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_162 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TageBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire f3_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} node _T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node lo = cat(_T_1, _T) node hi = cat(_T_3, _T_2) node _T_4 = cat(hi, lo) node lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _T_5 = cat(hi_1, lo_1) node lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _T_6 = cat(hi_2, lo_2) node lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _T_7 = cat(hi_3, lo_3) node _T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node lo_4 = cat(_T_9, _T_8) node hi_4 = cat(_T_11, _T_10) node _T_12 = cat(hi_4, lo_4) node lo_5 = cat(_T_5, _T_4) node hi_hi = cat(_T_12, _T_7) node hi_5 = cat(hi_hi, _T_6) node _T_13 = cat(hi_5, lo_5) inst tt_0_1 of TageTable_6 connect tt_0_1.clock, clock connect tt_0_1.reset, reset reg t_io_f1_req_valid_REG : UInt<1>, clock connect t_io_f1_req_valid_REG, io.f0_valid connect tt_0_1.io.f1_req_valid, t_io_f1_req_valid_REG reg t_io_f1_req_pc_REG : UInt, clock connect t_io_f1_req_pc_REG, io.f0_pc connect tt_0_1.io.f1_req_pc, t_io_f1_req_pc_REG connect tt_0_1.io.f1_req_ghist, io.f1_ghist inst tt_1_1 of TageTable_7 connect tt_1_1.clock, clock connect tt_1_1.reset, reset reg t_io_f1_req_valid_REG_1 : UInt<1>, clock connect t_io_f1_req_valid_REG_1, io.f0_valid connect tt_1_1.io.f1_req_valid, t_io_f1_req_valid_REG_1 reg t_io_f1_req_pc_REG_1 : UInt, clock connect t_io_f1_req_pc_REG_1, io.f0_pc connect tt_1_1.io.f1_req_pc, t_io_f1_req_pc_REG_1 connect tt_1_1.io.f1_req_ghist, io.f1_ghist inst tt_2_1 of TageTable_8 connect tt_2_1.clock, clock connect tt_2_1.reset, reset reg t_io_f1_req_valid_REG_2 : UInt<1>, clock connect t_io_f1_req_valid_REG_2, io.f0_valid connect tt_2_1.io.f1_req_valid, t_io_f1_req_valid_REG_2 reg t_io_f1_req_pc_REG_2 : UInt, clock connect t_io_f1_req_pc_REG_2, io.f0_pc connect tt_2_1.io.f1_req_pc, t_io_f1_req_pc_REG_2 connect tt_2_1.io.f1_req_ghist, io.f1_ghist inst tt_3_1 of TageTable_9 connect tt_3_1.clock, clock connect tt_3_1.reset, reset reg t_io_f1_req_valid_REG_3 : UInt<1>, clock connect t_io_f1_req_valid_REG_3, io.f0_valid connect tt_3_1.io.f1_req_valid, t_io_f1_req_valid_REG_3 reg t_io_f1_req_pc_REG_3 : UInt, clock connect t_io_f1_req_pc_REG_3, io.f0_pc connect tt_3_1.io.f1_req_pc, t_io_f1_req_pc_REG_3 connect tt_3_1.io.f1_req_ghist, io.f1_ghist inst tt_4_1 of TageTable_10 connect tt_4_1.clock, clock connect tt_4_1.reset, reset reg t_io_f1_req_valid_REG_4 : UInt<1>, clock connect t_io_f1_req_valid_REG_4, io.f0_valid connect tt_4_1.io.f1_req_valid, t_io_f1_req_valid_REG_4 reg t_io_f1_req_pc_REG_4 : UInt, clock connect t_io_f1_req_pc_REG_4, io.f0_pc connect tt_4_1.io.f1_req_pc, t_io_f1_req_pc_REG_4 connect tt_4_1.io.f1_req_ghist, io.f1_ghist inst tt_5_1 of TageTable_11 connect tt_5_1.clock, clock connect tt_5_1.reset, reset reg t_io_f1_req_valid_REG_5 : UInt<1>, clock connect t_io_f1_req_valid_REG_5, io.f0_valid connect tt_5_1.io.f1_req_valid, t_io_f1_req_valid_REG_5 reg t_io_f1_req_pc_REG_5 : UInt, clock connect t_io_f1_req_pc_REG_5, io.f0_pc connect tt_5_1.io.f1_req_pc, t_io_f1_req_pc_REG_5 connect tt_5_1.io.f1_req_ghist, io.f1_ghist wire f3_resps : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4][6] connect f3_resps[0], tt_0_1.io.f3_resp connect f3_resps[1], tt_1_1.io.f3_resp connect f3_resps[2], tt_2_1.io.f3_resp connect f3_resps[3], tt_3_1.io.f3_resp connect f3_resps[4], tt_4_1.io.f3_resp connect f3_resps[5], tt_5_1.io.f3_resp wire s1_update_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} wire _s1_update_meta_WIRE : UInt<56> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 2, 0) connect s1_update_meta.allocate[0].bits, _s1_update_meta_T node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 3) connect s1_update_meta.allocate[0].valid, _s1_update_meta_T_1 node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 6, 4) connect s1_update_meta.allocate[1].bits, _s1_update_meta_T_2 node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 7) connect s1_update_meta.allocate[1].valid, _s1_update_meta_T_3 node _s1_update_meta_T_4 = bits(_s1_update_meta_WIRE, 10, 8) connect s1_update_meta.allocate[2].bits, _s1_update_meta_T_4 node _s1_update_meta_T_5 = bits(_s1_update_meta_WIRE, 11, 11) connect s1_update_meta.allocate[2].valid, _s1_update_meta_T_5 node _s1_update_meta_T_6 = bits(_s1_update_meta_WIRE, 14, 12) connect s1_update_meta.allocate[3].bits, _s1_update_meta_T_6 node _s1_update_meta_T_7 = bits(_s1_update_meta_WIRE, 15, 15) connect s1_update_meta.allocate[3].valid, _s1_update_meta_T_7 node _s1_update_meta_T_8 = bits(_s1_update_meta_WIRE, 18, 16) connect s1_update_meta.provider_ctr[0], _s1_update_meta_T_8 node _s1_update_meta_T_9 = bits(_s1_update_meta_WIRE, 21, 19) connect s1_update_meta.provider_ctr[1], _s1_update_meta_T_9 node _s1_update_meta_T_10 = bits(_s1_update_meta_WIRE, 24, 22) connect s1_update_meta.provider_ctr[2], _s1_update_meta_T_10 node _s1_update_meta_T_11 = bits(_s1_update_meta_WIRE, 27, 25) connect s1_update_meta.provider_ctr[3], _s1_update_meta_T_11 node _s1_update_meta_T_12 = bits(_s1_update_meta_WIRE, 29, 28) connect s1_update_meta.provider_u[0], _s1_update_meta_T_12 node _s1_update_meta_T_13 = bits(_s1_update_meta_WIRE, 31, 30) connect s1_update_meta.provider_u[1], _s1_update_meta_T_13 node _s1_update_meta_T_14 = bits(_s1_update_meta_WIRE, 33, 32) connect s1_update_meta.provider_u[2], _s1_update_meta_T_14 node _s1_update_meta_T_15 = bits(_s1_update_meta_WIRE, 35, 34) connect s1_update_meta.provider_u[3], _s1_update_meta_T_15 node _s1_update_meta_T_16 = bits(_s1_update_meta_WIRE, 36, 36) connect s1_update_meta.alt_differs[0], _s1_update_meta_T_16 node _s1_update_meta_T_17 = bits(_s1_update_meta_WIRE, 37, 37) connect s1_update_meta.alt_differs[1], _s1_update_meta_T_17 node _s1_update_meta_T_18 = bits(_s1_update_meta_WIRE, 38, 38) connect s1_update_meta.alt_differs[2], _s1_update_meta_T_18 node _s1_update_meta_T_19 = bits(_s1_update_meta_WIRE, 39, 39) connect s1_update_meta.alt_differs[3], _s1_update_meta_T_19 node _s1_update_meta_T_20 = bits(_s1_update_meta_WIRE, 42, 40) connect s1_update_meta.provider[0].bits, _s1_update_meta_T_20 node _s1_update_meta_T_21 = bits(_s1_update_meta_WIRE, 43, 43) connect s1_update_meta.provider[0].valid, _s1_update_meta_T_21 node _s1_update_meta_T_22 = bits(_s1_update_meta_WIRE, 46, 44) connect s1_update_meta.provider[1].bits, _s1_update_meta_T_22 node _s1_update_meta_T_23 = bits(_s1_update_meta_WIRE, 47, 47) connect s1_update_meta.provider[1].valid, _s1_update_meta_T_23 node _s1_update_meta_T_24 = bits(_s1_update_meta_WIRE, 50, 48) connect s1_update_meta.provider[2].bits, _s1_update_meta_T_24 node _s1_update_meta_T_25 = bits(_s1_update_meta_WIRE, 51, 51) connect s1_update_meta.provider[2].valid, _s1_update_meta_T_25 node _s1_update_meta_T_26 = bits(_s1_update_meta_WIRE, 54, 52) connect s1_update_meta.provider[3].bits, _s1_update_meta_T_26 node _s1_update_meta_T_27 = bits(_s1_update_meta_WIRE, 55, 55) connect s1_update_meta.provider[3].valid, _s1_update_meta_T_27 node _s1_update_mispredict_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_mispredict_mask_T_1 = mux(s1_update.bits.cfi_mispredicted, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_mispredict_mask = and(_s1_update_mispredict_mask_T, _s1_update_mispredict_mask_T_1) wire _s1_update_mask_WIRE : UInt<1>[4][6] connect _s1_update_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_mask : UInt<1>[4][6] connect s1_update_mask, _s1_update_mask_WIRE wire _s1_update_u_mask_WIRE : UInt<1>[4][6] connect _s1_update_u_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_u_mask : UInt<1>[4][6] connect s1_update_u_mask, _s1_update_u_mask_WIRE wire s1_update_taken : UInt<1>[4][6] wire s1_update_old_ctr : UInt<3>[4][6] wire s1_update_alloc : UInt<1>[4][6] wire s1_update_u : UInt<2>[4][6] invalidate s1_update_taken[0][0] invalidate s1_update_taken[0][1] invalidate s1_update_taken[0][2] invalidate s1_update_taken[0][3] invalidate s1_update_taken[1][0] invalidate s1_update_taken[1][1] invalidate s1_update_taken[1][2] invalidate s1_update_taken[1][3] invalidate s1_update_taken[2][0] invalidate s1_update_taken[2][1] invalidate s1_update_taken[2][2] invalidate s1_update_taken[2][3] invalidate s1_update_taken[3][0] invalidate s1_update_taken[3][1] invalidate s1_update_taken[3][2] invalidate s1_update_taken[3][3] invalidate s1_update_taken[4][0] invalidate s1_update_taken[4][1] invalidate s1_update_taken[4][2] invalidate s1_update_taken[4][3] invalidate s1_update_taken[5][0] invalidate s1_update_taken[5][1] invalidate s1_update_taken[5][2] invalidate s1_update_taken[5][3] invalidate s1_update_old_ctr[0][0] invalidate s1_update_old_ctr[0][1] invalidate s1_update_old_ctr[0][2] invalidate s1_update_old_ctr[0][3] invalidate s1_update_old_ctr[1][0] invalidate s1_update_old_ctr[1][1] invalidate s1_update_old_ctr[1][2] invalidate s1_update_old_ctr[1][3] invalidate s1_update_old_ctr[2][0] invalidate s1_update_old_ctr[2][1] invalidate s1_update_old_ctr[2][2] invalidate s1_update_old_ctr[2][3] invalidate s1_update_old_ctr[3][0] invalidate s1_update_old_ctr[3][1] invalidate s1_update_old_ctr[3][2] invalidate s1_update_old_ctr[3][3] invalidate s1_update_old_ctr[4][0] invalidate s1_update_old_ctr[4][1] invalidate s1_update_old_ctr[4][2] invalidate s1_update_old_ctr[4][3] invalidate s1_update_old_ctr[5][0] invalidate s1_update_old_ctr[5][1] invalidate s1_update_old_ctr[5][2] invalidate s1_update_old_ctr[5][3] invalidate s1_update_alloc[0][0] invalidate s1_update_alloc[0][1] invalidate s1_update_alloc[0][2] invalidate s1_update_alloc[0][3] invalidate s1_update_alloc[1][0] invalidate s1_update_alloc[1][1] invalidate s1_update_alloc[1][2] invalidate s1_update_alloc[1][3] invalidate s1_update_alloc[2][0] invalidate s1_update_alloc[2][1] invalidate s1_update_alloc[2][2] invalidate s1_update_alloc[2][3] invalidate s1_update_alloc[3][0] invalidate s1_update_alloc[3][1] invalidate s1_update_alloc[3][2] invalidate s1_update_alloc[3][3] invalidate s1_update_alloc[4][0] invalidate s1_update_alloc[4][1] invalidate s1_update_alloc[4][2] invalidate s1_update_alloc[4][3] invalidate s1_update_alloc[5][0] invalidate s1_update_alloc[5][1] invalidate s1_update_alloc[5][2] invalidate s1_update_alloc[5][3] invalidate s1_update_u[0][0] invalidate s1_update_u[0][1] invalidate s1_update_u[0][2] invalidate s1_update_u[0][3] invalidate s1_update_u[1][0] invalidate s1_update_u[1][1] invalidate s1_update_u[1][2] invalidate s1_update_u[1][3] invalidate s1_update_u[2][0] invalidate s1_update_u[2][1] invalidate s1_update_u[2][2] invalidate s1_update_u[2][3] invalidate s1_update_u[3][0] invalidate s1_update_u[3][1] invalidate s1_update_u[3][2] invalidate s1_update_u[3][3] invalidate s1_update_u[4][0] invalidate s1_update_u[4][1] invalidate s1_update_u[4][2] invalidate s1_update_u[4][3] invalidate s1_update_u[5][0] invalidate s1_update_u[5][1] invalidate s1_update_u[5][2] invalidate s1_update_u[5][3] wire final_altpred : UInt<1> connect final_altpred, io.resp_in[0].f3[0].taken connect io.resp.f3[0].taken, io.resp_in[0].f3[0].taken when f3_resps[0][0].valid : node _io_resp_f3_0_taken_T = eq(f3_resps[0][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_1 = eq(f3_resps[0][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_2 = or(_io_resp_f3_0_taken_T, _io_resp_f3_0_taken_T_1) node _io_resp_f3_0_taken_T_3 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_4 = mux(_io_resp_f3_0_taken_T_2, io.resp_in[0].f3[0].taken, _io_resp_f3_0_taken_T_3) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_4 connect final_altpred, io.resp_in[0].f3[0].taken node _T_14 = or(UInt<1>(0h0), f3_resps[0][0].valid) node _T_15 = mux(f3_resps[0][0].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_16 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _T_17 = mux(f3_resps[0][0].valid, _T_16, io.resp_in[0].f3[0].taken) when f3_resps[1][0].valid : node _io_resp_f3_0_taken_T_5 = eq(f3_resps[1][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_6 = eq(f3_resps[1][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_7 = or(_io_resp_f3_0_taken_T_5, _io_resp_f3_0_taken_T_6) node _io_resp_f3_0_taken_T_8 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_9 = mux(_io_resp_f3_0_taken_T_7, _T_17, _io_resp_f3_0_taken_T_8) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_9 connect final_altpred, _T_17 node _T_18 = or(_T_14, f3_resps[1][0].valid) node _T_19 = mux(f3_resps[1][0].valid, UInt<1>(0h1), _T_15) node _T_20 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _T_21 = mux(f3_resps[1][0].valid, _T_20, _T_17) when f3_resps[2][0].valid : node _io_resp_f3_0_taken_T_10 = eq(f3_resps[2][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_11 = eq(f3_resps[2][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_12 = or(_io_resp_f3_0_taken_T_10, _io_resp_f3_0_taken_T_11) node _io_resp_f3_0_taken_T_13 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_14 = mux(_io_resp_f3_0_taken_T_12, _T_21, _io_resp_f3_0_taken_T_13) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_14 connect final_altpred, _T_21 node _T_22 = or(_T_18, f3_resps[2][0].valid) node _T_23 = mux(f3_resps[2][0].valid, UInt<2>(0h2), _T_19) node _T_24 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _T_25 = mux(f3_resps[2][0].valid, _T_24, _T_21) when f3_resps[3][0].valid : node _io_resp_f3_0_taken_T_15 = eq(f3_resps[3][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_16 = eq(f3_resps[3][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_17 = or(_io_resp_f3_0_taken_T_15, _io_resp_f3_0_taken_T_16) node _io_resp_f3_0_taken_T_18 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_19 = mux(_io_resp_f3_0_taken_T_17, _T_25, _io_resp_f3_0_taken_T_18) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_19 connect final_altpred, _T_25 node _T_26 = or(_T_22, f3_resps[3][0].valid) node _T_27 = mux(f3_resps[3][0].valid, UInt<2>(0h3), _T_23) node _T_28 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _T_29 = mux(f3_resps[3][0].valid, _T_28, _T_25) when f3_resps[4][0].valid : node _io_resp_f3_0_taken_T_20 = eq(f3_resps[4][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_21 = eq(f3_resps[4][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_22 = or(_io_resp_f3_0_taken_T_20, _io_resp_f3_0_taken_T_21) node _io_resp_f3_0_taken_T_23 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_24 = mux(_io_resp_f3_0_taken_T_22, _T_29, _io_resp_f3_0_taken_T_23) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_24 connect final_altpred, _T_29 node _T_30 = or(_T_26, f3_resps[4][0].valid) node _T_31 = mux(f3_resps[4][0].valid, UInt<3>(0h4), _T_27) node _T_32 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _T_33 = mux(f3_resps[4][0].valid, _T_32, _T_29) when f3_resps[5][0].valid : node _io_resp_f3_0_taken_T_25 = eq(f3_resps[5][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_26 = eq(f3_resps[5][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_27 = or(_io_resp_f3_0_taken_T_25, _io_resp_f3_0_taken_T_26) node _io_resp_f3_0_taken_T_28 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_29 = mux(_io_resp_f3_0_taken_T_27, _T_33, _io_resp_f3_0_taken_T_28) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_29 connect final_altpred, _T_33 node _T_34 = or(_T_30, f3_resps[5][0].valid) node _T_35 = mux(f3_resps[5][0].valid, UInt<3>(0h5), _T_31) node _T_36 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _T_37 = mux(f3_resps[5][0].valid, _T_36, _T_33) connect f3_meta.provider[0].valid, _T_34 connect f3_meta.provider[0].bits, _T_35 node _f3_meta_alt_differs_0_T = neq(final_altpred, io.resp.f3[0].taken) connect f3_meta.alt_differs[0], _f3_meta_alt_differs_0_T connect f3_meta.provider_u[0], f3_resps[_T_35][0].bits.u connect f3_meta.provider_ctr[0], f3_resps[_T_35][0].bits.ctr node _allocatable_slots_T = eq(f3_resps[0][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_1 = eq(f3_resps[0][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_2 = and(_allocatable_slots_T, _allocatable_slots_T_1) node _allocatable_slots_T_3 = eq(f3_resps[1][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_4 = eq(f3_resps[1][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_5 = and(_allocatable_slots_T_3, _allocatable_slots_T_4) node _allocatable_slots_T_6 = eq(f3_resps[2][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_7 = eq(f3_resps[2][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_8 = and(_allocatable_slots_T_6, _allocatable_slots_T_7) node _allocatable_slots_T_9 = eq(f3_resps[3][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_10 = eq(f3_resps[3][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_11 = and(_allocatable_slots_T_9, _allocatable_slots_T_10) node _allocatable_slots_T_12 = eq(f3_resps[4][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_13 = eq(f3_resps[4][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_14 = and(_allocatable_slots_T_12, _allocatable_slots_T_13) node _allocatable_slots_T_15 = eq(f3_resps[5][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_16 = eq(f3_resps[5][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_17 = and(_allocatable_slots_T_15, _allocatable_slots_T_16) wire _allocatable_slots_WIRE : UInt<1>[6] connect _allocatable_slots_WIRE[0], _allocatable_slots_T_2 connect _allocatable_slots_WIRE[1], _allocatable_slots_T_5 connect _allocatable_slots_WIRE[2], _allocatable_slots_T_8 connect _allocatable_slots_WIRE[3], _allocatable_slots_T_11 connect _allocatable_slots_WIRE[4], _allocatable_slots_T_14 connect _allocatable_slots_WIRE[5], _allocatable_slots_T_17 node allocatable_slots_lo_hi = cat(_allocatable_slots_WIRE[2], _allocatable_slots_WIRE[1]) node allocatable_slots_lo = cat(allocatable_slots_lo_hi, _allocatable_slots_WIRE[0]) node allocatable_slots_hi_hi = cat(_allocatable_slots_WIRE[5], _allocatable_slots_WIRE[4]) node allocatable_slots_hi = cat(allocatable_slots_hi_hi, _allocatable_slots_WIRE[3]) node _allocatable_slots_T_18 = cat(allocatable_slots_hi, allocatable_slots_lo) node _allocatable_slots_T_19 = dshl(UInt<1>(0h1), _T_35) node _allocatable_slots_T_20 = dshr(_allocatable_slots_T_19, UInt<1>(0h0)) node _allocatable_slots_T_21 = dshr(_allocatable_slots_T_19, UInt<1>(0h1)) node _allocatable_slots_T_22 = dshr(_allocatable_slots_T_19, UInt<2>(0h2)) node _allocatable_slots_T_23 = dshr(_allocatable_slots_T_19, UInt<2>(0h3)) node _allocatable_slots_T_24 = dshr(_allocatable_slots_T_19, UInt<3>(0h4)) node _allocatable_slots_T_25 = dshr(_allocatable_slots_T_19, UInt<3>(0h5)) node _allocatable_slots_T_26 = dshr(_allocatable_slots_T_19, UInt<3>(0h6)) node _allocatable_slots_T_27 = dshr(_allocatable_slots_T_19, UInt<3>(0h7)) node _allocatable_slots_T_28 = or(_allocatable_slots_T_20, _allocatable_slots_T_21) node _allocatable_slots_T_29 = or(_allocatable_slots_T_28, _allocatable_slots_T_22) node _allocatable_slots_T_30 = or(_allocatable_slots_T_29, _allocatable_slots_T_23) node _allocatable_slots_T_31 = or(_allocatable_slots_T_30, _allocatable_slots_T_24) node _allocatable_slots_T_32 = or(_allocatable_slots_T_31, _allocatable_slots_T_25) node _allocatable_slots_T_33 = or(_allocatable_slots_T_32, _allocatable_slots_T_26) node _allocatable_slots_T_34 = or(_allocatable_slots_T_33, _allocatable_slots_T_27) node _allocatable_slots_T_35 = mux(_T_34, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_36 = and(_allocatable_slots_T_34, _allocatable_slots_T_35) node _allocatable_slots_T_37 = not(_allocatable_slots_T_36) node allocatable_slots = and(_allocatable_slots_T_18, _allocatable_slots_T_37) inst alloc_lfsr_prng of MaxPeriodFibonacciLFSR_9 connect alloc_lfsr_prng.clock, clock connect alloc_lfsr_prng.reset, reset connect alloc_lfsr_prng.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng.io.seed.bits[0] invalidate alloc_lfsr_prng.io.seed.bits[1] invalidate alloc_lfsr_prng.io.seed.bits[2] invalidate alloc_lfsr_prng.io.seed.bits[3] invalidate alloc_lfsr_prng.io.seed.bits[4] invalidate alloc_lfsr_prng.io.seed.bits[5] connect alloc_lfsr_prng.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi = cat(alloc_lfsr_prng.io.out[2], alloc_lfsr_prng.io.out[1]) node alloc_lfsr_lo = cat(alloc_lfsr_lo_hi, alloc_lfsr_prng.io.out[0]) node alloc_lfsr_hi_hi = cat(alloc_lfsr_prng.io.out[5], alloc_lfsr_prng.io.out[4]) node alloc_lfsr_hi = cat(alloc_lfsr_hi_hi, alloc_lfsr_prng.io.out[3]) node alloc_lfsr = cat(alloc_lfsr_hi, alloc_lfsr_lo) node _first_entry_T = bits(allocatable_slots, 0, 0) node _first_entry_T_1 = bits(allocatable_slots, 1, 1) node _first_entry_T_2 = bits(allocatable_slots, 2, 2) node _first_entry_T_3 = bits(allocatable_slots, 3, 3) node _first_entry_T_4 = bits(allocatable_slots, 4, 4) node _first_entry_T_5 = bits(allocatable_slots, 5, 5) node _first_entry_T_6 = bits(allocatable_slots, 6, 6) node _first_entry_T_7 = bits(allocatable_slots, 7, 7) node _first_entry_T_8 = mux(_first_entry_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_9 = mux(_first_entry_T_5, UInt<3>(0h5), _first_entry_T_8) node _first_entry_T_10 = mux(_first_entry_T_4, UInt<3>(0h4), _first_entry_T_9) node _first_entry_T_11 = mux(_first_entry_T_3, UInt<2>(0h3), _first_entry_T_10) node _first_entry_T_12 = mux(_first_entry_T_2, UInt<2>(0h2), _first_entry_T_11) node _first_entry_T_13 = mux(_first_entry_T_1, UInt<1>(0h1), _first_entry_T_12) node first_entry = mux(_first_entry_T, UInt<1>(0h0), _first_entry_T_13) node _masked_entry_T = and(allocatable_slots, alloc_lfsr) node _masked_entry_T_1 = bits(_masked_entry_T, 0, 0) node _masked_entry_T_2 = bits(_masked_entry_T, 1, 1) node _masked_entry_T_3 = bits(_masked_entry_T, 2, 2) node _masked_entry_T_4 = bits(_masked_entry_T, 3, 3) node _masked_entry_T_5 = bits(_masked_entry_T, 4, 4) node _masked_entry_T_6 = bits(_masked_entry_T, 5, 5) node _masked_entry_T_7 = bits(_masked_entry_T, 6, 6) node _masked_entry_T_8 = bits(_masked_entry_T, 7, 7) node _masked_entry_T_9 = mux(_masked_entry_T_7, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_10 = mux(_masked_entry_T_6, UInt<3>(0h5), _masked_entry_T_9) node _masked_entry_T_11 = mux(_masked_entry_T_5, UInt<3>(0h4), _masked_entry_T_10) node _masked_entry_T_12 = mux(_masked_entry_T_4, UInt<2>(0h3), _masked_entry_T_11) node _masked_entry_T_13 = mux(_masked_entry_T_3, UInt<2>(0h2), _masked_entry_T_12) node _masked_entry_T_14 = mux(_masked_entry_T_2, UInt<1>(0h1), _masked_entry_T_13) node masked_entry = mux(_masked_entry_T_1, UInt<1>(0h0), _masked_entry_T_14) node _alloc_entry_T = dshr(allocatable_slots, masked_entry) node _alloc_entry_T_1 = bits(_alloc_entry_T, 0, 0) node alloc_entry = mux(_alloc_entry_T_1, masked_entry, first_entry) node _f3_meta_allocate_0_valid_T = neq(allocatable_slots, UInt<1>(0h0)) connect f3_meta.allocate[0].valid, _f3_meta_allocate_0_valid_T connect f3_meta.allocate[0].bits, alloc_entry node _update_was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _update_was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T) node update_was_taken = and(_update_was_taken_T_1, s1_update.bits.cfi_taken) node _T_38 = bits(s1_update.bits.br_mask, 0, 0) node _T_39 = and(_T_38, s1_update.valid) node _T_40 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_41 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = and(_T_39, _T_43) when _T_44 : when s1_update_meta.provider[0].valid : connect s1_update_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) node _new_u_T = bits(s1_update_mispredict_mask, 0, 0) node _new_u_T_1 = eq(s1_update_meta.alt_differs[0], UInt<1>(0h0)) node _new_u_T_2 = eq(s1_update_meta.provider_u[0], UInt<1>(0h0)) node _new_u_T_3 = sub(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_4 = tail(_new_u_T_3, 1) node _new_u_T_5 = mux(_new_u_T_2, UInt<1>(0h0), _new_u_T_4) node _new_u_T_6 = eq(s1_update_meta.provider_u[0], UInt<2>(0h3)) node _new_u_T_7 = add(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_8 = tail(_new_u_T_7, 1) node _new_u_T_9 = mux(_new_u_T_6, UInt<2>(0h3), _new_u_T_8) node _new_u_T_10 = mux(_new_u_T, _new_u_T_5, _new_u_T_9) node new_u = mux(_new_u_T_1, s1_update_meta.provider_u[0], _new_u_T_10) connect s1_update_u[s1_update_meta.provider[0].bits][0], new_u connect s1_update_taken[s1_update_meta.provider[0].bits][0], update_was_taken connect s1_update_old_ctr[s1_update_meta.provider[0].bits][0], s1_update_meta.provider_ctr[0] connect s1_update_alloc[s1_update_meta.provider[0].bits][0], UInt<1>(0h0) wire final_altpred_1 : UInt<1> connect final_altpred_1, io.resp_in[0].f3[1].taken connect io.resp.f3[1].taken, io.resp_in[0].f3[1].taken when f3_resps[0][1].valid : node _io_resp_f3_1_taken_T = eq(f3_resps[0][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_1 = eq(f3_resps[0][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_2 = or(_io_resp_f3_1_taken_T, _io_resp_f3_1_taken_T_1) node _io_resp_f3_1_taken_T_3 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_4 = mux(_io_resp_f3_1_taken_T_2, io.resp_in[0].f3[1].taken, _io_resp_f3_1_taken_T_3) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_4 connect final_altpred_1, io.resp_in[0].f3[1].taken node _T_45 = or(UInt<1>(0h0), f3_resps[0][1].valid) node _T_46 = mux(f3_resps[0][1].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _T_48 = mux(f3_resps[0][1].valid, _T_47, io.resp_in[0].f3[1].taken) when f3_resps[1][1].valid : node _io_resp_f3_1_taken_T_5 = eq(f3_resps[1][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_6 = eq(f3_resps[1][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_7 = or(_io_resp_f3_1_taken_T_5, _io_resp_f3_1_taken_T_6) node _io_resp_f3_1_taken_T_8 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_9 = mux(_io_resp_f3_1_taken_T_7, _T_48, _io_resp_f3_1_taken_T_8) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_9 connect final_altpred_1, _T_48 node _T_49 = or(_T_45, f3_resps[1][1].valid) node _T_50 = mux(f3_resps[1][1].valid, UInt<1>(0h1), _T_46) node _T_51 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _T_52 = mux(f3_resps[1][1].valid, _T_51, _T_48) when f3_resps[2][1].valid : node _io_resp_f3_1_taken_T_10 = eq(f3_resps[2][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_11 = eq(f3_resps[2][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_12 = or(_io_resp_f3_1_taken_T_10, _io_resp_f3_1_taken_T_11) node _io_resp_f3_1_taken_T_13 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_14 = mux(_io_resp_f3_1_taken_T_12, _T_52, _io_resp_f3_1_taken_T_13) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_14 connect final_altpred_1, _T_52 node _T_53 = or(_T_49, f3_resps[2][1].valid) node _T_54 = mux(f3_resps[2][1].valid, UInt<2>(0h2), _T_50) node _T_55 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _T_56 = mux(f3_resps[2][1].valid, _T_55, _T_52) when f3_resps[3][1].valid : node _io_resp_f3_1_taken_T_15 = eq(f3_resps[3][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_16 = eq(f3_resps[3][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_17 = or(_io_resp_f3_1_taken_T_15, _io_resp_f3_1_taken_T_16) node _io_resp_f3_1_taken_T_18 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_19 = mux(_io_resp_f3_1_taken_T_17, _T_56, _io_resp_f3_1_taken_T_18) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_19 connect final_altpred_1, _T_56 node _T_57 = or(_T_53, f3_resps[3][1].valid) node _T_58 = mux(f3_resps[3][1].valid, UInt<2>(0h3), _T_54) node _T_59 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _T_60 = mux(f3_resps[3][1].valid, _T_59, _T_56) when f3_resps[4][1].valid : node _io_resp_f3_1_taken_T_20 = eq(f3_resps[4][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_21 = eq(f3_resps[4][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_22 = or(_io_resp_f3_1_taken_T_20, _io_resp_f3_1_taken_T_21) node _io_resp_f3_1_taken_T_23 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_24 = mux(_io_resp_f3_1_taken_T_22, _T_60, _io_resp_f3_1_taken_T_23) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_24 connect final_altpred_1, _T_60 node _T_61 = or(_T_57, f3_resps[4][1].valid) node _T_62 = mux(f3_resps[4][1].valid, UInt<3>(0h4), _T_58) node _T_63 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _T_64 = mux(f3_resps[4][1].valid, _T_63, _T_60) when f3_resps[5][1].valid : node _io_resp_f3_1_taken_T_25 = eq(f3_resps[5][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_26 = eq(f3_resps[5][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_27 = or(_io_resp_f3_1_taken_T_25, _io_resp_f3_1_taken_T_26) node _io_resp_f3_1_taken_T_28 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_29 = mux(_io_resp_f3_1_taken_T_27, _T_64, _io_resp_f3_1_taken_T_28) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_29 connect final_altpred_1, _T_64 node _T_65 = or(_T_61, f3_resps[5][1].valid) node _T_66 = mux(f3_resps[5][1].valid, UInt<3>(0h5), _T_62) node _T_67 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _T_68 = mux(f3_resps[5][1].valid, _T_67, _T_64) connect f3_meta.provider[1].valid, _T_65 connect f3_meta.provider[1].bits, _T_66 node _f3_meta_alt_differs_1_T = neq(final_altpred_1, io.resp.f3[1].taken) connect f3_meta.alt_differs[1], _f3_meta_alt_differs_1_T connect f3_meta.provider_u[1], f3_resps[_T_66][1].bits.u connect f3_meta.provider_ctr[1], f3_resps[_T_66][1].bits.ctr node _allocatable_slots_T_38 = eq(f3_resps[0][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_39 = eq(f3_resps[0][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_40 = and(_allocatable_slots_T_38, _allocatable_slots_T_39) node _allocatable_slots_T_41 = eq(f3_resps[1][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_42 = eq(f3_resps[1][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_43 = and(_allocatable_slots_T_41, _allocatable_slots_T_42) node _allocatable_slots_T_44 = eq(f3_resps[2][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_45 = eq(f3_resps[2][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_46 = and(_allocatable_slots_T_44, _allocatable_slots_T_45) node _allocatable_slots_T_47 = eq(f3_resps[3][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_48 = eq(f3_resps[3][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_49 = and(_allocatable_slots_T_47, _allocatable_slots_T_48) node _allocatable_slots_T_50 = eq(f3_resps[4][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_51 = eq(f3_resps[4][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_52 = and(_allocatable_slots_T_50, _allocatable_slots_T_51) node _allocatable_slots_T_53 = eq(f3_resps[5][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_54 = eq(f3_resps[5][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_55 = and(_allocatable_slots_T_53, _allocatable_slots_T_54) wire _allocatable_slots_WIRE_1 : UInt<1>[6] connect _allocatable_slots_WIRE_1[0], _allocatable_slots_T_40 connect _allocatable_slots_WIRE_1[1], _allocatable_slots_T_43 connect _allocatable_slots_WIRE_1[2], _allocatable_slots_T_46 connect _allocatable_slots_WIRE_1[3], _allocatable_slots_T_49 connect _allocatable_slots_WIRE_1[4], _allocatable_slots_T_52 connect _allocatable_slots_WIRE_1[5], _allocatable_slots_T_55 node allocatable_slots_lo_hi_1 = cat(_allocatable_slots_WIRE_1[2], _allocatable_slots_WIRE_1[1]) node allocatable_slots_lo_1 = cat(allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1[0]) node allocatable_slots_hi_hi_1 = cat(_allocatable_slots_WIRE_1[5], _allocatable_slots_WIRE_1[4]) node allocatable_slots_hi_1 = cat(allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1[3]) node _allocatable_slots_T_56 = cat(allocatable_slots_hi_1, allocatable_slots_lo_1) node _allocatable_slots_T_57 = dshl(UInt<1>(0h1), _T_66) node _allocatable_slots_T_58 = dshr(_allocatable_slots_T_57, UInt<1>(0h0)) node _allocatable_slots_T_59 = dshr(_allocatable_slots_T_57, UInt<1>(0h1)) node _allocatable_slots_T_60 = dshr(_allocatable_slots_T_57, UInt<2>(0h2)) node _allocatable_slots_T_61 = dshr(_allocatable_slots_T_57, UInt<2>(0h3)) node _allocatable_slots_T_62 = dshr(_allocatable_slots_T_57, UInt<3>(0h4)) node _allocatable_slots_T_63 = dshr(_allocatable_slots_T_57, UInt<3>(0h5)) node _allocatable_slots_T_64 = dshr(_allocatable_slots_T_57, UInt<3>(0h6)) node _allocatable_slots_T_65 = dshr(_allocatable_slots_T_57, UInt<3>(0h7)) node _allocatable_slots_T_66 = or(_allocatable_slots_T_58, _allocatable_slots_T_59) node _allocatable_slots_T_67 = or(_allocatable_slots_T_66, _allocatable_slots_T_60) node _allocatable_slots_T_68 = or(_allocatable_slots_T_67, _allocatable_slots_T_61) node _allocatable_slots_T_69 = or(_allocatable_slots_T_68, _allocatable_slots_T_62) node _allocatable_slots_T_70 = or(_allocatable_slots_T_69, _allocatable_slots_T_63) node _allocatable_slots_T_71 = or(_allocatable_slots_T_70, _allocatable_slots_T_64) node _allocatable_slots_T_72 = or(_allocatable_slots_T_71, _allocatable_slots_T_65) node _allocatable_slots_T_73 = mux(_T_65, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_74 = and(_allocatable_slots_T_72, _allocatable_slots_T_73) node _allocatable_slots_T_75 = not(_allocatable_slots_T_74) node allocatable_slots_1 = and(_allocatable_slots_T_56, _allocatable_slots_T_75) inst alloc_lfsr_prng_1 of MaxPeriodFibonacciLFSR_10 connect alloc_lfsr_prng_1.clock, clock connect alloc_lfsr_prng_1.reset, reset connect alloc_lfsr_prng_1.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_1.io.seed.bits[0] invalidate alloc_lfsr_prng_1.io.seed.bits[1] invalidate alloc_lfsr_prng_1.io.seed.bits[2] invalidate alloc_lfsr_prng_1.io.seed.bits[3] invalidate alloc_lfsr_prng_1.io.seed.bits[4] invalidate alloc_lfsr_prng_1.io.seed.bits[5] connect alloc_lfsr_prng_1.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_1 = cat(alloc_lfsr_prng_1.io.out[2], alloc_lfsr_prng_1.io.out[1]) node alloc_lfsr_lo_1 = cat(alloc_lfsr_lo_hi_1, alloc_lfsr_prng_1.io.out[0]) node alloc_lfsr_hi_hi_1 = cat(alloc_lfsr_prng_1.io.out[5], alloc_lfsr_prng_1.io.out[4]) node alloc_lfsr_hi_1 = cat(alloc_lfsr_hi_hi_1, alloc_lfsr_prng_1.io.out[3]) node alloc_lfsr_1 = cat(alloc_lfsr_hi_1, alloc_lfsr_lo_1) node _first_entry_T_14 = bits(allocatable_slots_1, 0, 0) node _first_entry_T_15 = bits(allocatable_slots_1, 1, 1) node _first_entry_T_16 = bits(allocatable_slots_1, 2, 2) node _first_entry_T_17 = bits(allocatable_slots_1, 3, 3) node _first_entry_T_18 = bits(allocatable_slots_1, 4, 4) node _first_entry_T_19 = bits(allocatable_slots_1, 5, 5) node _first_entry_T_20 = bits(allocatable_slots_1, 6, 6) node _first_entry_T_21 = bits(allocatable_slots_1, 7, 7) node _first_entry_T_22 = mux(_first_entry_T_20, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_23 = mux(_first_entry_T_19, UInt<3>(0h5), _first_entry_T_22) node _first_entry_T_24 = mux(_first_entry_T_18, UInt<3>(0h4), _first_entry_T_23) node _first_entry_T_25 = mux(_first_entry_T_17, UInt<2>(0h3), _first_entry_T_24) node _first_entry_T_26 = mux(_first_entry_T_16, UInt<2>(0h2), _first_entry_T_25) node _first_entry_T_27 = mux(_first_entry_T_15, UInt<1>(0h1), _first_entry_T_26) node first_entry_1 = mux(_first_entry_T_14, UInt<1>(0h0), _first_entry_T_27) node _masked_entry_T_15 = and(allocatable_slots_1, alloc_lfsr_1) node _masked_entry_T_16 = bits(_masked_entry_T_15, 0, 0) node _masked_entry_T_17 = bits(_masked_entry_T_15, 1, 1) node _masked_entry_T_18 = bits(_masked_entry_T_15, 2, 2) node _masked_entry_T_19 = bits(_masked_entry_T_15, 3, 3) node _masked_entry_T_20 = bits(_masked_entry_T_15, 4, 4) node _masked_entry_T_21 = bits(_masked_entry_T_15, 5, 5) node _masked_entry_T_22 = bits(_masked_entry_T_15, 6, 6) node _masked_entry_T_23 = bits(_masked_entry_T_15, 7, 7) node _masked_entry_T_24 = mux(_masked_entry_T_22, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_25 = mux(_masked_entry_T_21, UInt<3>(0h5), _masked_entry_T_24) node _masked_entry_T_26 = mux(_masked_entry_T_20, UInt<3>(0h4), _masked_entry_T_25) node _masked_entry_T_27 = mux(_masked_entry_T_19, UInt<2>(0h3), _masked_entry_T_26) node _masked_entry_T_28 = mux(_masked_entry_T_18, UInt<2>(0h2), _masked_entry_T_27) node _masked_entry_T_29 = mux(_masked_entry_T_17, UInt<1>(0h1), _masked_entry_T_28) node masked_entry_1 = mux(_masked_entry_T_16, UInt<1>(0h0), _masked_entry_T_29) node _alloc_entry_T_2 = dshr(allocatable_slots_1, masked_entry_1) node _alloc_entry_T_3 = bits(_alloc_entry_T_2, 0, 0) node alloc_entry_1 = mux(_alloc_entry_T_3, masked_entry_1, first_entry_1) node _f3_meta_allocate_1_valid_T = neq(allocatable_slots_1, UInt<1>(0h0)) connect f3_meta.allocate[1].valid, _f3_meta_allocate_1_valid_T connect f3_meta.allocate[1].bits, alloc_entry_1 node _update_was_taken_T_2 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _update_was_taken_T_3 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_2) node update_was_taken_1 = and(_update_was_taken_T_3, s1_update.bits.cfi_taken) node _T_69 = bits(s1_update.bits.br_mask, 1, 1) node _T_70 = and(_T_69, s1_update.valid) node _T_71 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_72 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_73 = or(_T_71, _T_72) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = and(_T_70, _T_74) when _T_75 : when s1_update_meta.provider[1].valid : connect s1_update_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) node _new_u_T_11 = bits(s1_update_mispredict_mask, 1, 1) node _new_u_T_12 = eq(s1_update_meta.alt_differs[1], UInt<1>(0h0)) node _new_u_T_13 = eq(s1_update_meta.provider_u[1], UInt<1>(0h0)) node _new_u_T_14 = sub(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_15 = tail(_new_u_T_14, 1) node _new_u_T_16 = mux(_new_u_T_13, UInt<1>(0h0), _new_u_T_15) node _new_u_T_17 = eq(s1_update_meta.provider_u[1], UInt<2>(0h3)) node _new_u_T_18 = add(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_19 = tail(_new_u_T_18, 1) node _new_u_T_20 = mux(_new_u_T_17, UInt<2>(0h3), _new_u_T_19) node _new_u_T_21 = mux(_new_u_T_11, _new_u_T_16, _new_u_T_20) node new_u_1 = mux(_new_u_T_12, s1_update_meta.provider_u[1], _new_u_T_21) connect s1_update_u[s1_update_meta.provider[1].bits][1], new_u_1 connect s1_update_taken[s1_update_meta.provider[1].bits][1], update_was_taken_1 connect s1_update_old_ctr[s1_update_meta.provider[1].bits][1], s1_update_meta.provider_ctr[1] connect s1_update_alloc[s1_update_meta.provider[1].bits][1], UInt<1>(0h0) wire final_altpred_2 : UInt<1> connect final_altpred_2, io.resp_in[0].f3[2].taken connect io.resp.f3[2].taken, io.resp_in[0].f3[2].taken when f3_resps[0][2].valid : node _io_resp_f3_2_taken_T = eq(f3_resps[0][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_1 = eq(f3_resps[0][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_2 = or(_io_resp_f3_2_taken_T, _io_resp_f3_2_taken_T_1) node _io_resp_f3_2_taken_T_3 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_4 = mux(_io_resp_f3_2_taken_T_2, io.resp_in[0].f3[2].taken, _io_resp_f3_2_taken_T_3) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_4 connect final_altpred_2, io.resp_in[0].f3[2].taken node _T_76 = or(UInt<1>(0h0), f3_resps[0][2].valid) node _T_77 = mux(f3_resps[0][2].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_78 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _T_79 = mux(f3_resps[0][2].valid, _T_78, io.resp_in[0].f3[2].taken) when f3_resps[1][2].valid : node _io_resp_f3_2_taken_T_5 = eq(f3_resps[1][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_6 = eq(f3_resps[1][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_7 = or(_io_resp_f3_2_taken_T_5, _io_resp_f3_2_taken_T_6) node _io_resp_f3_2_taken_T_8 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_9 = mux(_io_resp_f3_2_taken_T_7, _T_79, _io_resp_f3_2_taken_T_8) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_9 connect final_altpred_2, _T_79 node _T_80 = or(_T_76, f3_resps[1][2].valid) node _T_81 = mux(f3_resps[1][2].valid, UInt<1>(0h1), _T_77) node _T_82 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _T_83 = mux(f3_resps[1][2].valid, _T_82, _T_79) when f3_resps[2][2].valid : node _io_resp_f3_2_taken_T_10 = eq(f3_resps[2][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_11 = eq(f3_resps[2][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_12 = or(_io_resp_f3_2_taken_T_10, _io_resp_f3_2_taken_T_11) node _io_resp_f3_2_taken_T_13 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_14 = mux(_io_resp_f3_2_taken_T_12, _T_83, _io_resp_f3_2_taken_T_13) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_14 connect final_altpred_2, _T_83 node _T_84 = or(_T_80, f3_resps[2][2].valid) node _T_85 = mux(f3_resps[2][2].valid, UInt<2>(0h2), _T_81) node _T_86 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _T_87 = mux(f3_resps[2][2].valid, _T_86, _T_83) when f3_resps[3][2].valid : node _io_resp_f3_2_taken_T_15 = eq(f3_resps[3][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_16 = eq(f3_resps[3][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_17 = or(_io_resp_f3_2_taken_T_15, _io_resp_f3_2_taken_T_16) node _io_resp_f3_2_taken_T_18 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_19 = mux(_io_resp_f3_2_taken_T_17, _T_87, _io_resp_f3_2_taken_T_18) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_19 connect final_altpred_2, _T_87 node _T_88 = or(_T_84, f3_resps[3][2].valid) node _T_89 = mux(f3_resps[3][2].valid, UInt<2>(0h3), _T_85) node _T_90 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _T_91 = mux(f3_resps[3][2].valid, _T_90, _T_87) when f3_resps[4][2].valid : node _io_resp_f3_2_taken_T_20 = eq(f3_resps[4][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_21 = eq(f3_resps[4][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_22 = or(_io_resp_f3_2_taken_T_20, _io_resp_f3_2_taken_T_21) node _io_resp_f3_2_taken_T_23 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_24 = mux(_io_resp_f3_2_taken_T_22, _T_91, _io_resp_f3_2_taken_T_23) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_24 connect final_altpred_2, _T_91 node _T_92 = or(_T_88, f3_resps[4][2].valid) node _T_93 = mux(f3_resps[4][2].valid, UInt<3>(0h4), _T_89) node _T_94 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _T_95 = mux(f3_resps[4][2].valid, _T_94, _T_91) when f3_resps[5][2].valid : node _io_resp_f3_2_taken_T_25 = eq(f3_resps[5][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_26 = eq(f3_resps[5][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_27 = or(_io_resp_f3_2_taken_T_25, _io_resp_f3_2_taken_T_26) node _io_resp_f3_2_taken_T_28 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_29 = mux(_io_resp_f3_2_taken_T_27, _T_95, _io_resp_f3_2_taken_T_28) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_29 connect final_altpred_2, _T_95 node _T_96 = or(_T_92, f3_resps[5][2].valid) node _T_97 = mux(f3_resps[5][2].valid, UInt<3>(0h5), _T_93) node _T_98 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _T_99 = mux(f3_resps[5][2].valid, _T_98, _T_95) connect f3_meta.provider[2].valid, _T_96 connect f3_meta.provider[2].bits, _T_97 node _f3_meta_alt_differs_2_T = neq(final_altpred_2, io.resp.f3[2].taken) connect f3_meta.alt_differs[2], _f3_meta_alt_differs_2_T connect f3_meta.provider_u[2], f3_resps[_T_97][2].bits.u connect f3_meta.provider_ctr[2], f3_resps[_T_97][2].bits.ctr node _allocatable_slots_T_76 = eq(f3_resps[0][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_77 = eq(f3_resps[0][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_78 = and(_allocatable_slots_T_76, _allocatable_slots_T_77) node _allocatable_slots_T_79 = eq(f3_resps[1][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_80 = eq(f3_resps[1][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_81 = and(_allocatable_slots_T_79, _allocatable_slots_T_80) node _allocatable_slots_T_82 = eq(f3_resps[2][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_83 = eq(f3_resps[2][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_84 = and(_allocatable_slots_T_82, _allocatable_slots_T_83) node _allocatable_slots_T_85 = eq(f3_resps[3][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_86 = eq(f3_resps[3][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_87 = and(_allocatable_slots_T_85, _allocatable_slots_T_86) node _allocatable_slots_T_88 = eq(f3_resps[4][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_89 = eq(f3_resps[4][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_90 = and(_allocatable_slots_T_88, _allocatable_slots_T_89) node _allocatable_slots_T_91 = eq(f3_resps[5][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_92 = eq(f3_resps[5][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_93 = and(_allocatable_slots_T_91, _allocatable_slots_T_92) wire _allocatable_slots_WIRE_2 : UInt<1>[6] connect _allocatable_slots_WIRE_2[0], _allocatable_slots_T_78 connect _allocatable_slots_WIRE_2[1], _allocatable_slots_T_81 connect _allocatable_slots_WIRE_2[2], _allocatable_slots_T_84 connect _allocatable_slots_WIRE_2[3], _allocatable_slots_T_87 connect _allocatable_slots_WIRE_2[4], _allocatable_slots_T_90 connect _allocatable_slots_WIRE_2[5], _allocatable_slots_T_93 node allocatable_slots_lo_hi_2 = cat(_allocatable_slots_WIRE_2[2], _allocatable_slots_WIRE_2[1]) node allocatable_slots_lo_2 = cat(allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2[0]) node allocatable_slots_hi_hi_2 = cat(_allocatable_slots_WIRE_2[5], _allocatable_slots_WIRE_2[4]) node allocatable_slots_hi_2 = cat(allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2[3]) node _allocatable_slots_T_94 = cat(allocatable_slots_hi_2, allocatable_slots_lo_2) node _allocatable_slots_T_95 = dshl(UInt<1>(0h1), _T_97) node _allocatable_slots_T_96 = dshr(_allocatable_slots_T_95, UInt<1>(0h0)) node _allocatable_slots_T_97 = dshr(_allocatable_slots_T_95, UInt<1>(0h1)) node _allocatable_slots_T_98 = dshr(_allocatable_slots_T_95, UInt<2>(0h2)) node _allocatable_slots_T_99 = dshr(_allocatable_slots_T_95, UInt<2>(0h3)) node _allocatable_slots_T_100 = dshr(_allocatable_slots_T_95, UInt<3>(0h4)) node _allocatable_slots_T_101 = dshr(_allocatable_slots_T_95, UInt<3>(0h5)) node _allocatable_slots_T_102 = dshr(_allocatable_slots_T_95, UInt<3>(0h6)) node _allocatable_slots_T_103 = dshr(_allocatable_slots_T_95, UInt<3>(0h7)) node _allocatable_slots_T_104 = or(_allocatable_slots_T_96, _allocatable_slots_T_97) node _allocatable_slots_T_105 = or(_allocatable_slots_T_104, _allocatable_slots_T_98) node _allocatable_slots_T_106 = or(_allocatable_slots_T_105, _allocatable_slots_T_99) node _allocatable_slots_T_107 = or(_allocatable_slots_T_106, _allocatable_slots_T_100) node _allocatable_slots_T_108 = or(_allocatable_slots_T_107, _allocatable_slots_T_101) node _allocatable_slots_T_109 = or(_allocatable_slots_T_108, _allocatable_slots_T_102) node _allocatable_slots_T_110 = or(_allocatable_slots_T_109, _allocatable_slots_T_103) node _allocatable_slots_T_111 = mux(_T_96, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_112 = and(_allocatable_slots_T_110, _allocatable_slots_T_111) node _allocatable_slots_T_113 = not(_allocatable_slots_T_112) node allocatable_slots_2 = and(_allocatable_slots_T_94, _allocatable_slots_T_113) inst alloc_lfsr_prng_2 of MaxPeriodFibonacciLFSR_11 connect alloc_lfsr_prng_2.clock, clock connect alloc_lfsr_prng_2.reset, reset connect alloc_lfsr_prng_2.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_2.io.seed.bits[0] invalidate alloc_lfsr_prng_2.io.seed.bits[1] invalidate alloc_lfsr_prng_2.io.seed.bits[2] invalidate alloc_lfsr_prng_2.io.seed.bits[3] invalidate alloc_lfsr_prng_2.io.seed.bits[4] invalidate alloc_lfsr_prng_2.io.seed.bits[5] connect alloc_lfsr_prng_2.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_2 = cat(alloc_lfsr_prng_2.io.out[2], alloc_lfsr_prng_2.io.out[1]) node alloc_lfsr_lo_2 = cat(alloc_lfsr_lo_hi_2, alloc_lfsr_prng_2.io.out[0]) node alloc_lfsr_hi_hi_2 = cat(alloc_lfsr_prng_2.io.out[5], alloc_lfsr_prng_2.io.out[4]) node alloc_lfsr_hi_2 = cat(alloc_lfsr_hi_hi_2, alloc_lfsr_prng_2.io.out[3]) node alloc_lfsr_2 = cat(alloc_lfsr_hi_2, alloc_lfsr_lo_2) node _first_entry_T_28 = bits(allocatable_slots_2, 0, 0) node _first_entry_T_29 = bits(allocatable_slots_2, 1, 1) node _first_entry_T_30 = bits(allocatable_slots_2, 2, 2) node _first_entry_T_31 = bits(allocatable_slots_2, 3, 3) node _first_entry_T_32 = bits(allocatable_slots_2, 4, 4) node _first_entry_T_33 = bits(allocatable_slots_2, 5, 5) node _first_entry_T_34 = bits(allocatable_slots_2, 6, 6) node _first_entry_T_35 = bits(allocatable_slots_2, 7, 7) node _first_entry_T_36 = mux(_first_entry_T_34, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_37 = mux(_first_entry_T_33, UInt<3>(0h5), _first_entry_T_36) node _first_entry_T_38 = mux(_first_entry_T_32, UInt<3>(0h4), _first_entry_T_37) node _first_entry_T_39 = mux(_first_entry_T_31, UInt<2>(0h3), _first_entry_T_38) node _first_entry_T_40 = mux(_first_entry_T_30, UInt<2>(0h2), _first_entry_T_39) node _first_entry_T_41 = mux(_first_entry_T_29, UInt<1>(0h1), _first_entry_T_40) node first_entry_2 = mux(_first_entry_T_28, UInt<1>(0h0), _first_entry_T_41) node _masked_entry_T_30 = and(allocatable_slots_2, alloc_lfsr_2) node _masked_entry_T_31 = bits(_masked_entry_T_30, 0, 0) node _masked_entry_T_32 = bits(_masked_entry_T_30, 1, 1) node _masked_entry_T_33 = bits(_masked_entry_T_30, 2, 2) node _masked_entry_T_34 = bits(_masked_entry_T_30, 3, 3) node _masked_entry_T_35 = bits(_masked_entry_T_30, 4, 4) node _masked_entry_T_36 = bits(_masked_entry_T_30, 5, 5) node _masked_entry_T_37 = bits(_masked_entry_T_30, 6, 6) node _masked_entry_T_38 = bits(_masked_entry_T_30, 7, 7) node _masked_entry_T_39 = mux(_masked_entry_T_37, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_40 = mux(_masked_entry_T_36, UInt<3>(0h5), _masked_entry_T_39) node _masked_entry_T_41 = mux(_masked_entry_T_35, UInt<3>(0h4), _masked_entry_T_40) node _masked_entry_T_42 = mux(_masked_entry_T_34, UInt<2>(0h3), _masked_entry_T_41) node _masked_entry_T_43 = mux(_masked_entry_T_33, UInt<2>(0h2), _masked_entry_T_42) node _masked_entry_T_44 = mux(_masked_entry_T_32, UInt<1>(0h1), _masked_entry_T_43) node masked_entry_2 = mux(_masked_entry_T_31, UInt<1>(0h0), _masked_entry_T_44) node _alloc_entry_T_4 = dshr(allocatable_slots_2, masked_entry_2) node _alloc_entry_T_5 = bits(_alloc_entry_T_4, 0, 0) node alloc_entry_2 = mux(_alloc_entry_T_5, masked_entry_2, first_entry_2) node _f3_meta_allocate_2_valid_T = neq(allocatable_slots_2, UInt<1>(0h0)) connect f3_meta.allocate[2].valid, _f3_meta_allocate_2_valid_T connect f3_meta.allocate[2].bits, alloc_entry_2 node _update_was_taken_T_4 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _update_was_taken_T_5 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_4) node update_was_taken_2 = and(_update_was_taken_T_5, s1_update.bits.cfi_taken) node _T_100 = bits(s1_update.bits.br_mask, 2, 2) node _T_101 = and(_T_100, s1_update.valid) node _T_102 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_103 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_104 = or(_T_102, _T_103) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = and(_T_101, _T_105) when _T_106 : when s1_update_meta.provider[2].valid : connect s1_update_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) node _new_u_T_22 = bits(s1_update_mispredict_mask, 2, 2) node _new_u_T_23 = eq(s1_update_meta.alt_differs[2], UInt<1>(0h0)) node _new_u_T_24 = eq(s1_update_meta.provider_u[2], UInt<1>(0h0)) node _new_u_T_25 = sub(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_26 = tail(_new_u_T_25, 1) node _new_u_T_27 = mux(_new_u_T_24, UInt<1>(0h0), _new_u_T_26) node _new_u_T_28 = eq(s1_update_meta.provider_u[2], UInt<2>(0h3)) node _new_u_T_29 = add(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_30 = tail(_new_u_T_29, 1) node _new_u_T_31 = mux(_new_u_T_28, UInt<2>(0h3), _new_u_T_30) node _new_u_T_32 = mux(_new_u_T_22, _new_u_T_27, _new_u_T_31) node new_u_2 = mux(_new_u_T_23, s1_update_meta.provider_u[2], _new_u_T_32) connect s1_update_u[s1_update_meta.provider[2].bits][2], new_u_2 connect s1_update_taken[s1_update_meta.provider[2].bits][2], update_was_taken_2 connect s1_update_old_ctr[s1_update_meta.provider[2].bits][2], s1_update_meta.provider_ctr[2] connect s1_update_alloc[s1_update_meta.provider[2].bits][2], UInt<1>(0h0) wire final_altpred_3 : UInt<1> connect final_altpred_3, io.resp_in[0].f3[3].taken connect io.resp.f3[3].taken, io.resp_in[0].f3[3].taken when f3_resps[0][3].valid : node _io_resp_f3_3_taken_T = eq(f3_resps[0][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_1 = eq(f3_resps[0][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_2 = or(_io_resp_f3_3_taken_T, _io_resp_f3_3_taken_T_1) node _io_resp_f3_3_taken_T_3 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_4 = mux(_io_resp_f3_3_taken_T_2, io.resp_in[0].f3[3].taken, _io_resp_f3_3_taken_T_3) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_4 connect final_altpred_3, io.resp_in[0].f3[3].taken node _T_107 = or(UInt<1>(0h0), f3_resps[0][3].valid) node _T_108 = mux(f3_resps[0][3].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_109 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _T_110 = mux(f3_resps[0][3].valid, _T_109, io.resp_in[0].f3[3].taken) when f3_resps[1][3].valid : node _io_resp_f3_3_taken_T_5 = eq(f3_resps[1][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_6 = eq(f3_resps[1][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_7 = or(_io_resp_f3_3_taken_T_5, _io_resp_f3_3_taken_T_6) node _io_resp_f3_3_taken_T_8 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_9 = mux(_io_resp_f3_3_taken_T_7, _T_110, _io_resp_f3_3_taken_T_8) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_9 connect final_altpred_3, _T_110 node _T_111 = or(_T_107, f3_resps[1][3].valid) node _T_112 = mux(f3_resps[1][3].valid, UInt<1>(0h1), _T_108) node _T_113 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _T_114 = mux(f3_resps[1][3].valid, _T_113, _T_110) when f3_resps[2][3].valid : node _io_resp_f3_3_taken_T_10 = eq(f3_resps[2][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_11 = eq(f3_resps[2][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_12 = or(_io_resp_f3_3_taken_T_10, _io_resp_f3_3_taken_T_11) node _io_resp_f3_3_taken_T_13 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_14 = mux(_io_resp_f3_3_taken_T_12, _T_114, _io_resp_f3_3_taken_T_13) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_14 connect final_altpred_3, _T_114 node _T_115 = or(_T_111, f3_resps[2][3].valid) node _T_116 = mux(f3_resps[2][3].valid, UInt<2>(0h2), _T_112) node _T_117 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _T_118 = mux(f3_resps[2][3].valid, _T_117, _T_114) when f3_resps[3][3].valid : node _io_resp_f3_3_taken_T_15 = eq(f3_resps[3][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_16 = eq(f3_resps[3][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_17 = or(_io_resp_f3_3_taken_T_15, _io_resp_f3_3_taken_T_16) node _io_resp_f3_3_taken_T_18 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_19 = mux(_io_resp_f3_3_taken_T_17, _T_118, _io_resp_f3_3_taken_T_18) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_19 connect final_altpred_3, _T_118 node _T_119 = or(_T_115, f3_resps[3][3].valid) node _T_120 = mux(f3_resps[3][3].valid, UInt<2>(0h3), _T_116) node _T_121 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _T_122 = mux(f3_resps[3][3].valid, _T_121, _T_118) when f3_resps[4][3].valid : node _io_resp_f3_3_taken_T_20 = eq(f3_resps[4][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_21 = eq(f3_resps[4][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_22 = or(_io_resp_f3_3_taken_T_20, _io_resp_f3_3_taken_T_21) node _io_resp_f3_3_taken_T_23 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_24 = mux(_io_resp_f3_3_taken_T_22, _T_122, _io_resp_f3_3_taken_T_23) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_24 connect final_altpred_3, _T_122 node _T_123 = or(_T_119, f3_resps[4][3].valid) node _T_124 = mux(f3_resps[4][3].valid, UInt<3>(0h4), _T_120) node _T_125 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _T_126 = mux(f3_resps[4][3].valid, _T_125, _T_122) when f3_resps[5][3].valid : node _io_resp_f3_3_taken_T_25 = eq(f3_resps[5][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_26 = eq(f3_resps[5][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_27 = or(_io_resp_f3_3_taken_T_25, _io_resp_f3_3_taken_T_26) node _io_resp_f3_3_taken_T_28 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_29 = mux(_io_resp_f3_3_taken_T_27, _T_126, _io_resp_f3_3_taken_T_28) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_29 connect final_altpred_3, _T_126 node _T_127 = or(_T_123, f3_resps[5][3].valid) node _T_128 = mux(f3_resps[5][3].valid, UInt<3>(0h5), _T_124) node _T_129 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _T_130 = mux(f3_resps[5][3].valid, _T_129, _T_126) connect f3_meta.provider[3].valid, _T_127 connect f3_meta.provider[3].bits, _T_128 node _f3_meta_alt_differs_3_T = neq(final_altpred_3, io.resp.f3[3].taken) connect f3_meta.alt_differs[3], _f3_meta_alt_differs_3_T connect f3_meta.provider_u[3], f3_resps[_T_128][3].bits.u connect f3_meta.provider_ctr[3], f3_resps[_T_128][3].bits.ctr node _allocatable_slots_T_114 = eq(f3_resps[0][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_115 = eq(f3_resps[0][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_116 = and(_allocatable_slots_T_114, _allocatable_slots_T_115) node _allocatable_slots_T_117 = eq(f3_resps[1][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_118 = eq(f3_resps[1][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_119 = and(_allocatable_slots_T_117, _allocatable_slots_T_118) node _allocatable_slots_T_120 = eq(f3_resps[2][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_121 = eq(f3_resps[2][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_122 = and(_allocatable_slots_T_120, _allocatable_slots_T_121) node _allocatable_slots_T_123 = eq(f3_resps[3][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_124 = eq(f3_resps[3][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_125 = and(_allocatable_slots_T_123, _allocatable_slots_T_124) node _allocatable_slots_T_126 = eq(f3_resps[4][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_127 = eq(f3_resps[4][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_128 = and(_allocatable_slots_T_126, _allocatable_slots_T_127) node _allocatable_slots_T_129 = eq(f3_resps[5][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_130 = eq(f3_resps[5][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_131 = and(_allocatable_slots_T_129, _allocatable_slots_T_130) wire _allocatable_slots_WIRE_3 : UInt<1>[6] connect _allocatable_slots_WIRE_3[0], _allocatable_slots_T_116 connect _allocatable_slots_WIRE_3[1], _allocatable_slots_T_119 connect _allocatable_slots_WIRE_3[2], _allocatable_slots_T_122 connect _allocatable_slots_WIRE_3[3], _allocatable_slots_T_125 connect _allocatable_slots_WIRE_3[4], _allocatable_slots_T_128 connect _allocatable_slots_WIRE_3[5], _allocatable_slots_T_131 node allocatable_slots_lo_hi_3 = cat(_allocatable_slots_WIRE_3[2], _allocatable_slots_WIRE_3[1]) node allocatable_slots_lo_3 = cat(allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3[0]) node allocatable_slots_hi_hi_3 = cat(_allocatable_slots_WIRE_3[5], _allocatable_slots_WIRE_3[4]) node allocatable_slots_hi_3 = cat(allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3[3]) node _allocatable_slots_T_132 = cat(allocatable_slots_hi_3, allocatable_slots_lo_3) node _allocatable_slots_T_133 = dshl(UInt<1>(0h1), _T_128) node _allocatable_slots_T_134 = dshr(_allocatable_slots_T_133, UInt<1>(0h0)) node _allocatable_slots_T_135 = dshr(_allocatable_slots_T_133, UInt<1>(0h1)) node _allocatable_slots_T_136 = dshr(_allocatable_slots_T_133, UInt<2>(0h2)) node _allocatable_slots_T_137 = dshr(_allocatable_slots_T_133, UInt<2>(0h3)) node _allocatable_slots_T_138 = dshr(_allocatable_slots_T_133, UInt<3>(0h4)) node _allocatable_slots_T_139 = dshr(_allocatable_slots_T_133, UInt<3>(0h5)) node _allocatable_slots_T_140 = dshr(_allocatable_slots_T_133, UInt<3>(0h6)) node _allocatable_slots_T_141 = dshr(_allocatable_slots_T_133, UInt<3>(0h7)) node _allocatable_slots_T_142 = or(_allocatable_slots_T_134, _allocatable_slots_T_135) node _allocatable_slots_T_143 = or(_allocatable_slots_T_142, _allocatable_slots_T_136) node _allocatable_slots_T_144 = or(_allocatable_slots_T_143, _allocatable_slots_T_137) node _allocatable_slots_T_145 = or(_allocatable_slots_T_144, _allocatable_slots_T_138) node _allocatable_slots_T_146 = or(_allocatable_slots_T_145, _allocatable_slots_T_139) node _allocatable_slots_T_147 = or(_allocatable_slots_T_146, _allocatable_slots_T_140) node _allocatable_slots_T_148 = or(_allocatable_slots_T_147, _allocatable_slots_T_141) node _allocatable_slots_T_149 = mux(_T_127, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_150 = and(_allocatable_slots_T_148, _allocatable_slots_T_149) node _allocatable_slots_T_151 = not(_allocatable_slots_T_150) node allocatable_slots_3 = and(_allocatable_slots_T_132, _allocatable_slots_T_151) inst alloc_lfsr_prng_3 of MaxPeriodFibonacciLFSR_12 connect alloc_lfsr_prng_3.clock, clock connect alloc_lfsr_prng_3.reset, reset connect alloc_lfsr_prng_3.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_3.io.seed.bits[0] invalidate alloc_lfsr_prng_3.io.seed.bits[1] invalidate alloc_lfsr_prng_3.io.seed.bits[2] invalidate alloc_lfsr_prng_3.io.seed.bits[3] invalidate alloc_lfsr_prng_3.io.seed.bits[4] invalidate alloc_lfsr_prng_3.io.seed.bits[5] connect alloc_lfsr_prng_3.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_3 = cat(alloc_lfsr_prng_3.io.out[2], alloc_lfsr_prng_3.io.out[1]) node alloc_lfsr_lo_3 = cat(alloc_lfsr_lo_hi_3, alloc_lfsr_prng_3.io.out[0]) node alloc_lfsr_hi_hi_3 = cat(alloc_lfsr_prng_3.io.out[5], alloc_lfsr_prng_3.io.out[4]) node alloc_lfsr_hi_3 = cat(alloc_lfsr_hi_hi_3, alloc_lfsr_prng_3.io.out[3]) node alloc_lfsr_3 = cat(alloc_lfsr_hi_3, alloc_lfsr_lo_3) node _first_entry_T_42 = bits(allocatable_slots_3, 0, 0) node _first_entry_T_43 = bits(allocatable_slots_3, 1, 1) node _first_entry_T_44 = bits(allocatable_slots_3, 2, 2) node _first_entry_T_45 = bits(allocatable_slots_3, 3, 3) node _first_entry_T_46 = bits(allocatable_slots_3, 4, 4) node _first_entry_T_47 = bits(allocatable_slots_3, 5, 5) node _first_entry_T_48 = bits(allocatable_slots_3, 6, 6) node _first_entry_T_49 = bits(allocatable_slots_3, 7, 7) node _first_entry_T_50 = mux(_first_entry_T_48, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_51 = mux(_first_entry_T_47, UInt<3>(0h5), _first_entry_T_50) node _first_entry_T_52 = mux(_first_entry_T_46, UInt<3>(0h4), _first_entry_T_51) node _first_entry_T_53 = mux(_first_entry_T_45, UInt<2>(0h3), _first_entry_T_52) node _first_entry_T_54 = mux(_first_entry_T_44, UInt<2>(0h2), _first_entry_T_53) node _first_entry_T_55 = mux(_first_entry_T_43, UInt<1>(0h1), _first_entry_T_54) node first_entry_3 = mux(_first_entry_T_42, UInt<1>(0h0), _first_entry_T_55) node _masked_entry_T_45 = and(allocatable_slots_3, alloc_lfsr_3) node _masked_entry_T_46 = bits(_masked_entry_T_45, 0, 0) node _masked_entry_T_47 = bits(_masked_entry_T_45, 1, 1) node _masked_entry_T_48 = bits(_masked_entry_T_45, 2, 2) node _masked_entry_T_49 = bits(_masked_entry_T_45, 3, 3) node _masked_entry_T_50 = bits(_masked_entry_T_45, 4, 4) node _masked_entry_T_51 = bits(_masked_entry_T_45, 5, 5) node _masked_entry_T_52 = bits(_masked_entry_T_45, 6, 6) node _masked_entry_T_53 = bits(_masked_entry_T_45, 7, 7) node _masked_entry_T_54 = mux(_masked_entry_T_52, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_55 = mux(_masked_entry_T_51, UInt<3>(0h5), _masked_entry_T_54) node _masked_entry_T_56 = mux(_masked_entry_T_50, UInt<3>(0h4), _masked_entry_T_55) node _masked_entry_T_57 = mux(_masked_entry_T_49, UInt<2>(0h3), _masked_entry_T_56) node _masked_entry_T_58 = mux(_masked_entry_T_48, UInt<2>(0h2), _masked_entry_T_57) node _masked_entry_T_59 = mux(_masked_entry_T_47, UInt<1>(0h1), _masked_entry_T_58) node masked_entry_3 = mux(_masked_entry_T_46, UInt<1>(0h0), _masked_entry_T_59) node _alloc_entry_T_6 = dshr(allocatable_slots_3, masked_entry_3) node _alloc_entry_T_7 = bits(_alloc_entry_T_6, 0, 0) node alloc_entry_3 = mux(_alloc_entry_T_7, masked_entry_3, first_entry_3) node _f3_meta_allocate_3_valid_T = neq(allocatable_slots_3, UInt<1>(0h0)) connect f3_meta.allocate[3].valid, _f3_meta_allocate_3_valid_T connect f3_meta.allocate[3].bits, alloc_entry_3 node _update_was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _update_was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_6) node update_was_taken_3 = and(_update_was_taken_T_7, s1_update.bits.cfi_taken) node _T_131 = bits(s1_update.bits.br_mask, 3, 3) node _T_132 = and(_T_131, s1_update.valid) node _T_133 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_134 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_135 = or(_T_133, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = and(_T_132, _T_136) when _T_137 : when s1_update_meta.provider[3].valid : connect s1_update_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) node _new_u_T_33 = bits(s1_update_mispredict_mask, 3, 3) node _new_u_T_34 = eq(s1_update_meta.alt_differs[3], UInt<1>(0h0)) node _new_u_T_35 = eq(s1_update_meta.provider_u[3], UInt<1>(0h0)) node _new_u_T_36 = sub(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_37 = tail(_new_u_T_36, 1) node _new_u_T_38 = mux(_new_u_T_35, UInt<1>(0h0), _new_u_T_37) node _new_u_T_39 = eq(s1_update_meta.provider_u[3], UInt<2>(0h3)) node _new_u_T_40 = add(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_41 = tail(_new_u_T_40, 1) node _new_u_T_42 = mux(_new_u_T_39, UInt<2>(0h3), _new_u_T_41) node _new_u_T_43 = mux(_new_u_T_33, _new_u_T_38, _new_u_T_42) node new_u_3 = mux(_new_u_T_34, s1_update_meta.provider_u[3], _new_u_T_43) connect s1_update_u[s1_update_meta.provider[3].bits][3], new_u_3 connect s1_update_taken[s1_update_meta.provider[3].bits][3], update_was_taken_3 connect s1_update_old_ctr[s1_update_meta.provider[3].bits][3], s1_update_meta.provider_ctr[3] connect s1_update_alloc[s1_update_meta.provider[3].bits][3], UInt<1>(0h0) node _T_138 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_139 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_140 = or(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = and(s1_update.valid, _T_141) node _T_143 = and(_T_142, s1_update.bits.cfi_mispredicted) node _T_144 = and(_T_143, s1_update.bits.cfi_idx.valid) when _T_144 : when s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].valid : connect s1_update_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_taken[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], s1_update.bits.cfi_taken connect s1_update_alloc[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) else : node _decr_mask_T = dshl(UInt<1>(0h1), s1_update_meta.provider[s1_update.bits.cfi_idx.bits].bits) node _decr_mask_T_1 = dshr(_decr_mask_T, UInt<1>(0h0)) node _decr_mask_T_2 = dshr(_decr_mask_T, UInt<1>(0h1)) node _decr_mask_T_3 = dshr(_decr_mask_T, UInt<2>(0h2)) node _decr_mask_T_4 = dshr(_decr_mask_T, UInt<2>(0h3)) node _decr_mask_T_5 = dshr(_decr_mask_T, UInt<3>(0h4)) node _decr_mask_T_6 = dshr(_decr_mask_T, UInt<3>(0h5)) node _decr_mask_T_7 = dshr(_decr_mask_T, UInt<3>(0h6)) node _decr_mask_T_8 = dshr(_decr_mask_T, UInt<3>(0h7)) node _decr_mask_T_9 = or(_decr_mask_T_1, _decr_mask_T_2) node _decr_mask_T_10 = or(_decr_mask_T_9, _decr_mask_T_3) node _decr_mask_T_11 = or(_decr_mask_T_10, _decr_mask_T_4) node _decr_mask_T_12 = or(_decr_mask_T_11, _decr_mask_T_5) node _decr_mask_T_13 = or(_decr_mask_T_12, _decr_mask_T_6) node _decr_mask_T_14 = or(_decr_mask_T_13, _decr_mask_T_7) node _decr_mask_T_15 = or(_decr_mask_T_14, _decr_mask_T_8) node _decr_mask_T_16 = not(_decr_mask_T_15) node decr_mask = mux(s1_update_meta.provider[s1_update.bits.cfi_idx.bits].valid, _decr_mask_T_16, UInt<1>(0h0)) node _T_145 = bits(decr_mask, 0, 0) when _T_145 : connect s1_update_u_mask[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_146 = bits(decr_mask, 1, 1) when _T_146 : connect s1_update_u_mask[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_147 = bits(decr_mask, 2, 2) when _T_147 : connect s1_update_u_mask[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_148 = bits(decr_mask, 3, 3) when _T_148 : connect s1_update_u_mask[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_149 = bits(decr_mask, 4, 4) when _T_149 : connect s1_update_u_mask[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_150 = bits(decr_mask, 5, 5) when _T_150 : connect s1_update_u_mask[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) reg tt_0_1_io_update_mask_0_REG : UInt<1>, clock connect tt_0_1_io_update_mask_0_REG, s1_update_mask[0][0] connect tt_0_1.io.update_mask[0], tt_0_1_io_update_mask_0_REG reg tt_0_1_io_update_taken_0_REG : UInt<1>, clock connect tt_0_1_io_update_taken_0_REG, s1_update_taken[0][0] connect tt_0_1.io.update_taken[0], tt_0_1_io_update_taken_0_REG reg tt_0_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_0_REG, s1_update_alloc[0][0] connect tt_0_1.io.update_alloc[0], tt_0_1_io_update_alloc_0_REG reg tt_0_1_io_update_old_ctr_0_REG : UInt, clock connect tt_0_1_io_update_old_ctr_0_REG, s1_update_old_ctr[0][0] connect tt_0_1.io.update_old_ctr[0], tt_0_1_io_update_old_ctr_0_REG reg tt_0_1_io_update_u_mask_0_REG : UInt, clock connect tt_0_1_io_update_u_mask_0_REG, s1_update_u_mask[0][0] connect tt_0_1.io.update_u_mask[0], tt_0_1_io_update_u_mask_0_REG reg tt_0_1_io_update_u_0_REG : UInt, clock connect tt_0_1_io_update_u_0_REG, s1_update_u[0][0] connect tt_0_1.io.update_u[0], tt_0_1_io_update_u_0_REG reg tt_0_1_io_update_mask_1_REG : UInt<1>, clock connect tt_0_1_io_update_mask_1_REG, s1_update_mask[0][1] connect tt_0_1.io.update_mask[1], tt_0_1_io_update_mask_1_REG reg tt_0_1_io_update_taken_1_REG : UInt<1>, clock connect tt_0_1_io_update_taken_1_REG, s1_update_taken[0][1] connect tt_0_1.io.update_taken[1], tt_0_1_io_update_taken_1_REG reg tt_0_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_1_REG, s1_update_alloc[0][1] connect tt_0_1.io.update_alloc[1], tt_0_1_io_update_alloc_1_REG reg tt_0_1_io_update_old_ctr_1_REG : UInt, clock connect tt_0_1_io_update_old_ctr_1_REG, s1_update_old_ctr[0][1] connect tt_0_1.io.update_old_ctr[1], tt_0_1_io_update_old_ctr_1_REG reg tt_0_1_io_update_u_mask_1_REG : UInt, clock connect tt_0_1_io_update_u_mask_1_REG, s1_update_u_mask[0][1] connect tt_0_1.io.update_u_mask[1], tt_0_1_io_update_u_mask_1_REG reg tt_0_1_io_update_u_1_REG : UInt, clock connect tt_0_1_io_update_u_1_REG, s1_update_u[0][1] connect tt_0_1.io.update_u[1], tt_0_1_io_update_u_1_REG reg tt_0_1_io_update_mask_2_REG : UInt<1>, clock connect tt_0_1_io_update_mask_2_REG, s1_update_mask[0][2] connect tt_0_1.io.update_mask[2], tt_0_1_io_update_mask_2_REG reg tt_0_1_io_update_taken_2_REG : UInt<1>, clock connect tt_0_1_io_update_taken_2_REG, s1_update_taken[0][2] connect tt_0_1.io.update_taken[2], tt_0_1_io_update_taken_2_REG reg tt_0_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_2_REG, s1_update_alloc[0][2] connect tt_0_1.io.update_alloc[2], tt_0_1_io_update_alloc_2_REG reg tt_0_1_io_update_old_ctr_2_REG : UInt, clock connect tt_0_1_io_update_old_ctr_2_REG, s1_update_old_ctr[0][2] connect tt_0_1.io.update_old_ctr[2], tt_0_1_io_update_old_ctr_2_REG reg tt_0_1_io_update_u_mask_2_REG : UInt, clock connect tt_0_1_io_update_u_mask_2_REG, s1_update_u_mask[0][2] connect tt_0_1.io.update_u_mask[2], tt_0_1_io_update_u_mask_2_REG reg tt_0_1_io_update_u_2_REG : UInt, clock connect tt_0_1_io_update_u_2_REG, s1_update_u[0][2] connect tt_0_1.io.update_u[2], tt_0_1_io_update_u_2_REG reg tt_0_1_io_update_mask_3_REG : UInt<1>, clock connect tt_0_1_io_update_mask_3_REG, s1_update_mask[0][3] connect tt_0_1.io.update_mask[3], tt_0_1_io_update_mask_3_REG reg tt_0_1_io_update_taken_3_REG : UInt<1>, clock connect tt_0_1_io_update_taken_3_REG, s1_update_taken[0][3] connect tt_0_1.io.update_taken[3], tt_0_1_io_update_taken_3_REG reg tt_0_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_3_REG, s1_update_alloc[0][3] connect tt_0_1.io.update_alloc[3], tt_0_1_io_update_alloc_3_REG reg tt_0_1_io_update_old_ctr_3_REG : UInt, clock connect tt_0_1_io_update_old_ctr_3_REG, s1_update_old_ctr[0][3] connect tt_0_1.io.update_old_ctr[3], tt_0_1_io_update_old_ctr_3_REG reg tt_0_1_io_update_u_mask_3_REG : UInt, clock connect tt_0_1_io_update_u_mask_3_REG, s1_update_u_mask[0][3] connect tt_0_1.io.update_u_mask[3], tt_0_1_io_update_u_mask_3_REG reg tt_0_1_io_update_u_3_REG : UInt, clock connect tt_0_1_io_update_u_3_REG, s1_update_u[0][3] connect tt_0_1.io.update_u[3], tt_0_1_io_update_u_3_REG reg tt_0_1_io_update_pc_REG : UInt, clock connect tt_0_1_io_update_pc_REG, s1_update.bits.pc connect tt_0_1.io.update_pc, tt_0_1_io_update_pc_REG reg tt_0_1_io_update_hist_REG : UInt, clock connect tt_0_1_io_update_hist_REG, s1_update.bits.ghist connect tt_0_1.io.update_hist, tt_0_1_io_update_hist_REG reg tt_1_1_io_update_mask_0_REG : UInt<1>, clock connect tt_1_1_io_update_mask_0_REG, s1_update_mask[1][0] connect tt_1_1.io.update_mask[0], tt_1_1_io_update_mask_0_REG reg tt_1_1_io_update_taken_0_REG : UInt<1>, clock connect tt_1_1_io_update_taken_0_REG, s1_update_taken[1][0] connect tt_1_1.io.update_taken[0], tt_1_1_io_update_taken_0_REG reg tt_1_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_0_REG, s1_update_alloc[1][0] connect tt_1_1.io.update_alloc[0], tt_1_1_io_update_alloc_0_REG reg tt_1_1_io_update_old_ctr_0_REG : UInt, clock connect tt_1_1_io_update_old_ctr_0_REG, s1_update_old_ctr[1][0] connect tt_1_1.io.update_old_ctr[0], tt_1_1_io_update_old_ctr_0_REG reg tt_1_1_io_update_u_mask_0_REG : UInt, clock connect tt_1_1_io_update_u_mask_0_REG, s1_update_u_mask[1][0] connect tt_1_1.io.update_u_mask[0], tt_1_1_io_update_u_mask_0_REG reg tt_1_1_io_update_u_0_REG : UInt, clock connect tt_1_1_io_update_u_0_REG, s1_update_u[1][0] connect tt_1_1.io.update_u[0], tt_1_1_io_update_u_0_REG reg tt_1_1_io_update_mask_1_REG : UInt<1>, clock connect tt_1_1_io_update_mask_1_REG, s1_update_mask[1][1] connect tt_1_1.io.update_mask[1], tt_1_1_io_update_mask_1_REG reg tt_1_1_io_update_taken_1_REG : UInt<1>, clock connect tt_1_1_io_update_taken_1_REG, s1_update_taken[1][1] connect tt_1_1.io.update_taken[1], tt_1_1_io_update_taken_1_REG reg tt_1_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_1_REG, s1_update_alloc[1][1] connect tt_1_1.io.update_alloc[1], tt_1_1_io_update_alloc_1_REG reg tt_1_1_io_update_old_ctr_1_REG : UInt, clock connect tt_1_1_io_update_old_ctr_1_REG, s1_update_old_ctr[1][1] connect tt_1_1.io.update_old_ctr[1], tt_1_1_io_update_old_ctr_1_REG reg tt_1_1_io_update_u_mask_1_REG : UInt, clock connect tt_1_1_io_update_u_mask_1_REG, s1_update_u_mask[1][1] connect tt_1_1.io.update_u_mask[1], tt_1_1_io_update_u_mask_1_REG reg tt_1_1_io_update_u_1_REG : UInt, clock connect tt_1_1_io_update_u_1_REG, s1_update_u[1][1] connect tt_1_1.io.update_u[1], tt_1_1_io_update_u_1_REG reg tt_1_1_io_update_mask_2_REG : UInt<1>, clock connect tt_1_1_io_update_mask_2_REG, s1_update_mask[1][2] connect tt_1_1.io.update_mask[2], tt_1_1_io_update_mask_2_REG reg tt_1_1_io_update_taken_2_REG : UInt<1>, clock connect tt_1_1_io_update_taken_2_REG, s1_update_taken[1][2] connect tt_1_1.io.update_taken[2], tt_1_1_io_update_taken_2_REG reg tt_1_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_2_REG, s1_update_alloc[1][2] connect tt_1_1.io.update_alloc[2], tt_1_1_io_update_alloc_2_REG reg tt_1_1_io_update_old_ctr_2_REG : UInt, clock connect tt_1_1_io_update_old_ctr_2_REG, s1_update_old_ctr[1][2] connect tt_1_1.io.update_old_ctr[2], tt_1_1_io_update_old_ctr_2_REG reg tt_1_1_io_update_u_mask_2_REG : UInt, clock connect tt_1_1_io_update_u_mask_2_REG, s1_update_u_mask[1][2] connect tt_1_1.io.update_u_mask[2], tt_1_1_io_update_u_mask_2_REG reg tt_1_1_io_update_u_2_REG : UInt, clock connect tt_1_1_io_update_u_2_REG, s1_update_u[1][2] connect tt_1_1.io.update_u[2], tt_1_1_io_update_u_2_REG reg tt_1_1_io_update_mask_3_REG : UInt<1>, clock connect tt_1_1_io_update_mask_3_REG, s1_update_mask[1][3] connect tt_1_1.io.update_mask[3], tt_1_1_io_update_mask_3_REG reg tt_1_1_io_update_taken_3_REG : UInt<1>, clock connect tt_1_1_io_update_taken_3_REG, s1_update_taken[1][3] connect tt_1_1.io.update_taken[3], tt_1_1_io_update_taken_3_REG reg tt_1_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_3_REG, s1_update_alloc[1][3] connect tt_1_1.io.update_alloc[3], tt_1_1_io_update_alloc_3_REG reg tt_1_1_io_update_old_ctr_3_REG : UInt, clock connect tt_1_1_io_update_old_ctr_3_REG, s1_update_old_ctr[1][3] connect tt_1_1.io.update_old_ctr[3], tt_1_1_io_update_old_ctr_3_REG reg tt_1_1_io_update_u_mask_3_REG : UInt, clock connect tt_1_1_io_update_u_mask_3_REG, s1_update_u_mask[1][3] connect tt_1_1.io.update_u_mask[3], tt_1_1_io_update_u_mask_3_REG reg tt_1_1_io_update_u_3_REG : UInt, clock connect tt_1_1_io_update_u_3_REG, s1_update_u[1][3] connect tt_1_1.io.update_u[3], tt_1_1_io_update_u_3_REG reg tt_1_1_io_update_pc_REG : UInt, clock connect tt_1_1_io_update_pc_REG, s1_update.bits.pc connect tt_1_1.io.update_pc, tt_1_1_io_update_pc_REG reg tt_1_1_io_update_hist_REG : UInt, clock connect tt_1_1_io_update_hist_REG, s1_update.bits.ghist connect tt_1_1.io.update_hist, tt_1_1_io_update_hist_REG reg tt_2_1_io_update_mask_0_REG : UInt<1>, clock connect tt_2_1_io_update_mask_0_REG, s1_update_mask[2][0] connect tt_2_1.io.update_mask[0], tt_2_1_io_update_mask_0_REG reg tt_2_1_io_update_taken_0_REG : UInt<1>, clock connect tt_2_1_io_update_taken_0_REG, s1_update_taken[2][0] connect tt_2_1.io.update_taken[0], tt_2_1_io_update_taken_0_REG reg tt_2_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_0_REG, s1_update_alloc[2][0] connect tt_2_1.io.update_alloc[0], tt_2_1_io_update_alloc_0_REG reg tt_2_1_io_update_old_ctr_0_REG : UInt, clock connect tt_2_1_io_update_old_ctr_0_REG, s1_update_old_ctr[2][0] connect tt_2_1.io.update_old_ctr[0], tt_2_1_io_update_old_ctr_0_REG reg tt_2_1_io_update_u_mask_0_REG : UInt, clock connect tt_2_1_io_update_u_mask_0_REG, s1_update_u_mask[2][0] connect tt_2_1.io.update_u_mask[0], tt_2_1_io_update_u_mask_0_REG reg tt_2_1_io_update_u_0_REG : UInt, clock connect tt_2_1_io_update_u_0_REG, s1_update_u[2][0] connect tt_2_1.io.update_u[0], tt_2_1_io_update_u_0_REG reg tt_2_1_io_update_mask_1_REG : UInt<1>, clock connect tt_2_1_io_update_mask_1_REG, s1_update_mask[2][1] connect tt_2_1.io.update_mask[1], tt_2_1_io_update_mask_1_REG reg tt_2_1_io_update_taken_1_REG : UInt<1>, clock connect tt_2_1_io_update_taken_1_REG, s1_update_taken[2][1] connect tt_2_1.io.update_taken[1], tt_2_1_io_update_taken_1_REG reg tt_2_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_1_REG, s1_update_alloc[2][1] connect tt_2_1.io.update_alloc[1], tt_2_1_io_update_alloc_1_REG reg tt_2_1_io_update_old_ctr_1_REG : UInt, clock connect tt_2_1_io_update_old_ctr_1_REG, s1_update_old_ctr[2][1] connect tt_2_1.io.update_old_ctr[1], tt_2_1_io_update_old_ctr_1_REG reg tt_2_1_io_update_u_mask_1_REG : UInt, clock connect tt_2_1_io_update_u_mask_1_REG, s1_update_u_mask[2][1] connect tt_2_1.io.update_u_mask[1], tt_2_1_io_update_u_mask_1_REG reg tt_2_1_io_update_u_1_REG : UInt, clock connect tt_2_1_io_update_u_1_REG, s1_update_u[2][1] connect tt_2_1.io.update_u[1], tt_2_1_io_update_u_1_REG reg tt_2_1_io_update_mask_2_REG : UInt<1>, clock connect tt_2_1_io_update_mask_2_REG, s1_update_mask[2][2] connect tt_2_1.io.update_mask[2], tt_2_1_io_update_mask_2_REG reg tt_2_1_io_update_taken_2_REG : UInt<1>, clock connect tt_2_1_io_update_taken_2_REG, s1_update_taken[2][2] connect tt_2_1.io.update_taken[2], tt_2_1_io_update_taken_2_REG reg tt_2_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_2_REG, s1_update_alloc[2][2] connect tt_2_1.io.update_alloc[2], tt_2_1_io_update_alloc_2_REG reg tt_2_1_io_update_old_ctr_2_REG : UInt, clock connect tt_2_1_io_update_old_ctr_2_REG, s1_update_old_ctr[2][2] connect tt_2_1.io.update_old_ctr[2], tt_2_1_io_update_old_ctr_2_REG reg tt_2_1_io_update_u_mask_2_REG : UInt, clock connect tt_2_1_io_update_u_mask_2_REG, s1_update_u_mask[2][2] connect tt_2_1.io.update_u_mask[2], tt_2_1_io_update_u_mask_2_REG reg tt_2_1_io_update_u_2_REG : UInt, clock connect tt_2_1_io_update_u_2_REG, s1_update_u[2][2] connect tt_2_1.io.update_u[2], tt_2_1_io_update_u_2_REG reg tt_2_1_io_update_mask_3_REG : UInt<1>, clock connect tt_2_1_io_update_mask_3_REG, s1_update_mask[2][3] connect tt_2_1.io.update_mask[3], tt_2_1_io_update_mask_3_REG reg tt_2_1_io_update_taken_3_REG : UInt<1>, clock connect tt_2_1_io_update_taken_3_REG, s1_update_taken[2][3] connect tt_2_1.io.update_taken[3], tt_2_1_io_update_taken_3_REG reg tt_2_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_3_REG, s1_update_alloc[2][3] connect tt_2_1.io.update_alloc[3], tt_2_1_io_update_alloc_3_REG reg tt_2_1_io_update_old_ctr_3_REG : UInt, clock connect tt_2_1_io_update_old_ctr_3_REG, s1_update_old_ctr[2][3] connect tt_2_1.io.update_old_ctr[3], tt_2_1_io_update_old_ctr_3_REG reg tt_2_1_io_update_u_mask_3_REG : UInt, clock connect tt_2_1_io_update_u_mask_3_REG, s1_update_u_mask[2][3] connect tt_2_1.io.update_u_mask[3], tt_2_1_io_update_u_mask_3_REG reg tt_2_1_io_update_u_3_REG : UInt, clock connect tt_2_1_io_update_u_3_REG, s1_update_u[2][3] connect tt_2_1.io.update_u[3], tt_2_1_io_update_u_3_REG reg tt_2_1_io_update_pc_REG : UInt, clock connect tt_2_1_io_update_pc_REG, s1_update.bits.pc connect tt_2_1.io.update_pc, tt_2_1_io_update_pc_REG reg tt_2_1_io_update_hist_REG : UInt, clock connect tt_2_1_io_update_hist_REG, s1_update.bits.ghist connect tt_2_1.io.update_hist, tt_2_1_io_update_hist_REG reg tt_3_1_io_update_mask_0_REG : UInt<1>, clock connect tt_3_1_io_update_mask_0_REG, s1_update_mask[3][0] connect tt_3_1.io.update_mask[0], tt_3_1_io_update_mask_0_REG reg tt_3_1_io_update_taken_0_REG : UInt<1>, clock connect tt_3_1_io_update_taken_0_REG, s1_update_taken[3][0] connect tt_3_1.io.update_taken[0], tt_3_1_io_update_taken_0_REG reg tt_3_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_0_REG, s1_update_alloc[3][0] connect tt_3_1.io.update_alloc[0], tt_3_1_io_update_alloc_0_REG reg tt_3_1_io_update_old_ctr_0_REG : UInt, clock connect tt_3_1_io_update_old_ctr_0_REG, s1_update_old_ctr[3][0] connect tt_3_1.io.update_old_ctr[0], tt_3_1_io_update_old_ctr_0_REG reg tt_3_1_io_update_u_mask_0_REG : UInt, clock connect tt_3_1_io_update_u_mask_0_REG, s1_update_u_mask[3][0] connect tt_3_1.io.update_u_mask[0], tt_3_1_io_update_u_mask_0_REG reg tt_3_1_io_update_u_0_REG : UInt, clock connect tt_3_1_io_update_u_0_REG, s1_update_u[3][0] connect tt_3_1.io.update_u[0], tt_3_1_io_update_u_0_REG reg tt_3_1_io_update_mask_1_REG : UInt<1>, clock connect tt_3_1_io_update_mask_1_REG, s1_update_mask[3][1] connect tt_3_1.io.update_mask[1], tt_3_1_io_update_mask_1_REG reg tt_3_1_io_update_taken_1_REG : UInt<1>, clock connect tt_3_1_io_update_taken_1_REG, s1_update_taken[3][1] connect tt_3_1.io.update_taken[1], tt_3_1_io_update_taken_1_REG reg tt_3_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_1_REG, s1_update_alloc[3][1] connect tt_3_1.io.update_alloc[1], tt_3_1_io_update_alloc_1_REG reg tt_3_1_io_update_old_ctr_1_REG : UInt, clock connect tt_3_1_io_update_old_ctr_1_REG, s1_update_old_ctr[3][1] connect tt_3_1.io.update_old_ctr[1], tt_3_1_io_update_old_ctr_1_REG reg tt_3_1_io_update_u_mask_1_REG : UInt, clock connect tt_3_1_io_update_u_mask_1_REG, s1_update_u_mask[3][1] connect tt_3_1.io.update_u_mask[1], tt_3_1_io_update_u_mask_1_REG reg tt_3_1_io_update_u_1_REG : UInt, clock connect tt_3_1_io_update_u_1_REG, s1_update_u[3][1] connect tt_3_1.io.update_u[1], tt_3_1_io_update_u_1_REG reg tt_3_1_io_update_mask_2_REG : UInt<1>, clock connect tt_3_1_io_update_mask_2_REG, s1_update_mask[3][2] connect tt_3_1.io.update_mask[2], tt_3_1_io_update_mask_2_REG reg tt_3_1_io_update_taken_2_REG : UInt<1>, clock connect tt_3_1_io_update_taken_2_REG, s1_update_taken[3][2] connect tt_3_1.io.update_taken[2], tt_3_1_io_update_taken_2_REG reg tt_3_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_2_REG, s1_update_alloc[3][2] connect tt_3_1.io.update_alloc[2], tt_3_1_io_update_alloc_2_REG reg tt_3_1_io_update_old_ctr_2_REG : UInt, clock connect tt_3_1_io_update_old_ctr_2_REG, s1_update_old_ctr[3][2] connect tt_3_1.io.update_old_ctr[2], tt_3_1_io_update_old_ctr_2_REG reg tt_3_1_io_update_u_mask_2_REG : UInt, clock connect tt_3_1_io_update_u_mask_2_REG, s1_update_u_mask[3][2] connect tt_3_1.io.update_u_mask[2], tt_3_1_io_update_u_mask_2_REG reg tt_3_1_io_update_u_2_REG : UInt, clock connect tt_3_1_io_update_u_2_REG, s1_update_u[3][2] connect tt_3_1.io.update_u[2], tt_3_1_io_update_u_2_REG reg tt_3_1_io_update_mask_3_REG : UInt<1>, clock connect tt_3_1_io_update_mask_3_REG, s1_update_mask[3][3] connect tt_3_1.io.update_mask[3], tt_3_1_io_update_mask_3_REG reg tt_3_1_io_update_taken_3_REG : UInt<1>, clock connect tt_3_1_io_update_taken_3_REG, s1_update_taken[3][3] connect tt_3_1.io.update_taken[3], tt_3_1_io_update_taken_3_REG reg tt_3_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_3_REG, s1_update_alloc[3][3] connect tt_3_1.io.update_alloc[3], tt_3_1_io_update_alloc_3_REG reg tt_3_1_io_update_old_ctr_3_REG : UInt, clock connect tt_3_1_io_update_old_ctr_3_REG, s1_update_old_ctr[3][3] connect tt_3_1.io.update_old_ctr[3], tt_3_1_io_update_old_ctr_3_REG reg tt_3_1_io_update_u_mask_3_REG : UInt, clock connect tt_3_1_io_update_u_mask_3_REG, s1_update_u_mask[3][3] connect tt_3_1.io.update_u_mask[3], tt_3_1_io_update_u_mask_3_REG reg tt_3_1_io_update_u_3_REG : UInt, clock connect tt_3_1_io_update_u_3_REG, s1_update_u[3][3] connect tt_3_1.io.update_u[3], tt_3_1_io_update_u_3_REG reg tt_3_1_io_update_pc_REG : UInt, clock connect tt_3_1_io_update_pc_REG, s1_update.bits.pc connect tt_3_1.io.update_pc, tt_3_1_io_update_pc_REG reg tt_3_1_io_update_hist_REG : UInt, clock connect tt_3_1_io_update_hist_REG, s1_update.bits.ghist connect tt_3_1.io.update_hist, tt_3_1_io_update_hist_REG reg tt_4_1_io_update_mask_0_REG : UInt<1>, clock connect tt_4_1_io_update_mask_0_REG, s1_update_mask[4][0] connect tt_4_1.io.update_mask[0], tt_4_1_io_update_mask_0_REG reg tt_4_1_io_update_taken_0_REG : UInt<1>, clock connect tt_4_1_io_update_taken_0_REG, s1_update_taken[4][0] connect tt_4_1.io.update_taken[0], tt_4_1_io_update_taken_0_REG reg tt_4_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_0_REG, s1_update_alloc[4][0] connect tt_4_1.io.update_alloc[0], tt_4_1_io_update_alloc_0_REG reg tt_4_1_io_update_old_ctr_0_REG : UInt, clock connect tt_4_1_io_update_old_ctr_0_REG, s1_update_old_ctr[4][0] connect tt_4_1.io.update_old_ctr[0], tt_4_1_io_update_old_ctr_0_REG reg tt_4_1_io_update_u_mask_0_REG : UInt, clock connect tt_4_1_io_update_u_mask_0_REG, s1_update_u_mask[4][0] connect tt_4_1.io.update_u_mask[0], tt_4_1_io_update_u_mask_0_REG reg tt_4_1_io_update_u_0_REG : UInt, clock connect tt_4_1_io_update_u_0_REG, s1_update_u[4][0] connect tt_4_1.io.update_u[0], tt_4_1_io_update_u_0_REG reg tt_4_1_io_update_mask_1_REG : UInt<1>, clock connect tt_4_1_io_update_mask_1_REG, s1_update_mask[4][1] connect tt_4_1.io.update_mask[1], tt_4_1_io_update_mask_1_REG reg tt_4_1_io_update_taken_1_REG : UInt<1>, clock connect tt_4_1_io_update_taken_1_REG, s1_update_taken[4][1] connect tt_4_1.io.update_taken[1], tt_4_1_io_update_taken_1_REG reg tt_4_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_1_REG, s1_update_alloc[4][1] connect tt_4_1.io.update_alloc[1], tt_4_1_io_update_alloc_1_REG reg tt_4_1_io_update_old_ctr_1_REG : UInt, clock connect tt_4_1_io_update_old_ctr_1_REG, s1_update_old_ctr[4][1] connect tt_4_1.io.update_old_ctr[1], tt_4_1_io_update_old_ctr_1_REG reg tt_4_1_io_update_u_mask_1_REG : UInt, clock connect tt_4_1_io_update_u_mask_1_REG, s1_update_u_mask[4][1] connect tt_4_1.io.update_u_mask[1], tt_4_1_io_update_u_mask_1_REG reg tt_4_1_io_update_u_1_REG : UInt, clock connect tt_4_1_io_update_u_1_REG, s1_update_u[4][1] connect tt_4_1.io.update_u[1], tt_4_1_io_update_u_1_REG reg tt_4_1_io_update_mask_2_REG : UInt<1>, clock connect tt_4_1_io_update_mask_2_REG, s1_update_mask[4][2] connect tt_4_1.io.update_mask[2], tt_4_1_io_update_mask_2_REG reg tt_4_1_io_update_taken_2_REG : UInt<1>, clock connect tt_4_1_io_update_taken_2_REG, s1_update_taken[4][2] connect tt_4_1.io.update_taken[2], tt_4_1_io_update_taken_2_REG reg tt_4_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_2_REG, s1_update_alloc[4][2] connect tt_4_1.io.update_alloc[2], tt_4_1_io_update_alloc_2_REG reg tt_4_1_io_update_old_ctr_2_REG : UInt, clock connect tt_4_1_io_update_old_ctr_2_REG, s1_update_old_ctr[4][2] connect tt_4_1.io.update_old_ctr[2], tt_4_1_io_update_old_ctr_2_REG reg tt_4_1_io_update_u_mask_2_REG : UInt, clock connect tt_4_1_io_update_u_mask_2_REG, s1_update_u_mask[4][2] connect tt_4_1.io.update_u_mask[2], tt_4_1_io_update_u_mask_2_REG reg tt_4_1_io_update_u_2_REG : UInt, clock connect tt_4_1_io_update_u_2_REG, s1_update_u[4][2] connect tt_4_1.io.update_u[2], tt_4_1_io_update_u_2_REG reg tt_4_1_io_update_mask_3_REG : UInt<1>, clock connect tt_4_1_io_update_mask_3_REG, s1_update_mask[4][3] connect tt_4_1.io.update_mask[3], tt_4_1_io_update_mask_3_REG reg tt_4_1_io_update_taken_3_REG : UInt<1>, clock connect tt_4_1_io_update_taken_3_REG, s1_update_taken[4][3] connect tt_4_1.io.update_taken[3], tt_4_1_io_update_taken_3_REG reg tt_4_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_3_REG, s1_update_alloc[4][3] connect tt_4_1.io.update_alloc[3], tt_4_1_io_update_alloc_3_REG reg tt_4_1_io_update_old_ctr_3_REG : UInt, clock connect tt_4_1_io_update_old_ctr_3_REG, s1_update_old_ctr[4][3] connect tt_4_1.io.update_old_ctr[3], tt_4_1_io_update_old_ctr_3_REG reg tt_4_1_io_update_u_mask_3_REG : UInt, clock connect tt_4_1_io_update_u_mask_3_REG, s1_update_u_mask[4][3] connect tt_4_1.io.update_u_mask[3], tt_4_1_io_update_u_mask_3_REG reg tt_4_1_io_update_u_3_REG : UInt, clock connect tt_4_1_io_update_u_3_REG, s1_update_u[4][3] connect tt_4_1.io.update_u[3], tt_4_1_io_update_u_3_REG reg tt_4_1_io_update_pc_REG : UInt, clock connect tt_4_1_io_update_pc_REG, s1_update.bits.pc connect tt_4_1.io.update_pc, tt_4_1_io_update_pc_REG reg tt_4_1_io_update_hist_REG : UInt, clock connect tt_4_1_io_update_hist_REG, s1_update.bits.ghist connect tt_4_1.io.update_hist, tt_4_1_io_update_hist_REG reg tt_5_1_io_update_mask_0_REG : UInt<1>, clock connect tt_5_1_io_update_mask_0_REG, s1_update_mask[5][0] connect tt_5_1.io.update_mask[0], tt_5_1_io_update_mask_0_REG reg tt_5_1_io_update_taken_0_REG : UInt<1>, clock connect tt_5_1_io_update_taken_0_REG, s1_update_taken[5][0] connect tt_5_1.io.update_taken[0], tt_5_1_io_update_taken_0_REG reg tt_5_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_0_REG, s1_update_alloc[5][0] connect tt_5_1.io.update_alloc[0], tt_5_1_io_update_alloc_0_REG reg tt_5_1_io_update_old_ctr_0_REG : UInt, clock connect tt_5_1_io_update_old_ctr_0_REG, s1_update_old_ctr[5][0] connect tt_5_1.io.update_old_ctr[0], tt_5_1_io_update_old_ctr_0_REG reg tt_5_1_io_update_u_mask_0_REG : UInt, clock connect tt_5_1_io_update_u_mask_0_REG, s1_update_u_mask[5][0] connect tt_5_1.io.update_u_mask[0], tt_5_1_io_update_u_mask_0_REG reg tt_5_1_io_update_u_0_REG : UInt, clock connect tt_5_1_io_update_u_0_REG, s1_update_u[5][0] connect tt_5_1.io.update_u[0], tt_5_1_io_update_u_0_REG reg tt_5_1_io_update_mask_1_REG : UInt<1>, clock connect tt_5_1_io_update_mask_1_REG, s1_update_mask[5][1] connect tt_5_1.io.update_mask[1], tt_5_1_io_update_mask_1_REG reg tt_5_1_io_update_taken_1_REG : UInt<1>, clock connect tt_5_1_io_update_taken_1_REG, s1_update_taken[5][1] connect tt_5_1.io.update_taken[1], tt_5_1_io_update_taken_1_REG reg tt_5_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_1_REG, s1_update_alloc[5][1] connect tt_5_1.io.update_alloc[1], tt_5_1_io_update_alloc_1_REG reg tt_5_1_io_update_old_ctr_1_REG : UInt, clock connect tt_5_1_io_update_old_ctr_1_REG, s1_update_old_ctr[5][1] connect tt_5_1.io.update_old_ctr[1], tt_5_1_io_update_old_ctr_1_REG reg tt_5_1_io_update_u_mask_1_REG : UInt, clock connect tt_5_1_io_update_u_mask_1_REG, s1_update_u_mask[5][1] connect tt_5_1.io.update_u_mask[1], tt_5_1_io_update_u_mask_1_REG reg tt_5_1_io_update_u_1_REG : UInt, clock connect tt_5_1_io_update_u_1_REG, s1_update_u[5][1] connect tt_5_1.io.update_u[1], tt_5_1_io_update_u_1_REG reg tt_5_1_io_update_mask_2_REG : UInt<1>, clock connect tt_5_1_io_update_mask_2_REG, s1_update_mask[5][2] connect tt_5_1.io.update_mask[2], tt_5_1_io_update_mask_2_REG reg tt_5_1_io_update_taken_2_REG : UInt<1>, clock connect tt_5_1_io_update_taken_2_REG, s1_update_taken[5][2] connect tt_5_1.io.update_taken[2], tt_5_1_io_update_taken_2_REG reg tt_5_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_2_REG, s1_update_alloc[5][2] connect tt_5_1.io.update_alloc[2], tt_5_1_io_update_alloc_2_REG reg tt_5_1_io_update_old_ctr_2_REG : UInt, clock connect tt_5_1_io_update_old_ctr_2_REG, s1_update_old_ctr[5][2] connect tt_5_1.io.update_old_ctr[2], tt_5_1_io_update_old_ctr_2_REG reg tt_5_1_io_update_u_mask_2_REG : UInt, clock connect tt_5_1_io_update_u_mask_2_REG, s1_update_u_mask[5][2] connect tt_5_1.io.update_u_mask[2], tt_5_1_io_update_u_mask_2_REG reg tt_5_1_io_update_u_2_REG : UInt, clock connect tt_5_1_io_update_u_2_REG, s1_update_u[5][2] connect tt_5_1.io.update_u[2], tt_5_1_io_update_u_2_REG reg tt_5_1_io_update_mask_3_REG : UInt<1>, clock connect tt_5_1_io_update_mask_3_REG, s1_update_mask[5][3] connect tt_5_1.io.update_mask[3], tt_5_1_io_update_mask_3_REG reg tt_5_1_io_update_taken_3_REG : UInt<1>, clock connect tt_5_1_io_update_taken_3_REG, s1_update_taken[5][3] connect tt_5_1.io.update_taken[3], tt_5_1_io_update_taken_3_REG reg tt_5_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_3_REG, s1_update_alloc[5][3] connect tt_5_1.io.update_alloc[3], tt_5_1_io_update_alloc_3_REG reg tt_5_1_io_update_old_ctr_3_REG : UInt, clock connect tt_5_1_io_update_old_ctr_3_REG, s1_update_old_ctr[5][3] connect tt_5_1.io.update_old_ctr[3], tt_5_1_io_update_old_ctr_3_REG reg tt_5_1_io_update_u_mask_3_REG : UInt, clock connect tt_5_1_io_update_u_mask_3_REG, s1_update_u_mask[5][3] connect tt_5_1.io.update_u_mask[3], tt_5_1_io_update_u_mask_3_REG reg tt_5_1_io_update_u_3_REG : UInt, clock connect tt_5_1_io_update_u_3_REG, s1_update_u[5][3] connect tt_5_1.io.update_u[3], tt_5_1_io_update_u_3_REG reg tt_5_1_io_update_pc_REG : UInt, clock connect tt_5_1_io_update_pc_REG, s1_update.bits.pc connect tt_5_1.io.update_pc, tt_5_1_io_update_pc_REG reg tt_5_1_io_update_hist_REG : UInt, clock connect tt_5_1_io_update_hist_REG, s1_update.bits.ghist connect tt_5_1.io.update_hist, tt_5_1_io_update_hist_REG node _io_f3_meta_T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _io_f3_meta_T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _io_f3_meta_T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _io_f3_meta_T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node io_f3_meta_lo = cat(_io_f3_meta_T_1, _io_f3_meta_T) node io_f3_meta_hi = cat(_io_f3_meta_T_3, _io_f3_meta_T_2) node _io_f3_meta_T_4 = cat(io_f3_meta_hi, io_f3_meta_lo) node io_f3_meta_lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node io_f3_meta_hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _io_f3_meta_T_5 = cat(io_f3_meta_hi_1, io_f3_meta_lo_1) node io_f3_meta_lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node io_f3_meta_hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _io_f3_meta_T_6 = cat(io_f3_meta_hi_2, io_f3_meta_lo_2) node io_f3_meta_lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node io_f3_meta_hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _io_f3_meta_T_7 = cat(io_f3_meta_hi_3, io_f3_meta_lo_3) node _io_f3_meta_T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _io_f3_meta_T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _io_f3_meta_T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _io_f3_meta_T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node io_f3_meta_lo_4 = cat(_io_f3_meta_T_9, _io_f3_meta_T_8) node io_f3_meta_hi_4 = cat(_io_f3_meta_T_11, _io_f3_meta_T_10) node _io_f3_meta_T_12 = cat(io_f3_meta_hi_4, io_f3_meta_lo_4) node io_f3_meta_lo_5 = cat(_io_f3_meta_T_5, _io_f3_meta_T_4) node io_f3_meta_hi_hi = cat(_io_f3_meta_T_12, _io_f3_meta_T_7) node io_f3_meta_hi_5 = cat(io_f3_meta_hi_hi, _io_f3_meta_T_6) node _io_f3_meta_T_13 = cat(io_f3_meta_hi_5, io_f3_meta_lo_5) connect io.f3_meta, _io_f3_meta_T_13	module TageBranchPredictorBank_1( // @[tage.scala:198:7] input clock, // @[tage.scala:198:7] input reset, // @[tage.scala:198:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [2:0] s1_update_meta_provider_ctr_3; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_2; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_1; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_0; // @[tage.scala:236:52] wire _alloc_lfsr_prng_3_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire io_f0_valid_0 = io_f0_valid; // @[tage.scala:198:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[tage.scala:198:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[tage.scala:198:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_f3_fire_0 = io_f3_fire; // @[tage.scala:198:7] wire io_update_valid_0 = io_update_valid; // @[tage.scala:198:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[tage.scala:198:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[tage.scala:198:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[tage.scala:198:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[tage.scala:198:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[tage.scala:198:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[tage.scala:198:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[tage.scala:198:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[tage.scala:198:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[tage.scala:198:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[tage.scala:198:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[tage.scala:198:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[tage.scala:198:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[tage.scala:198:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[tage.scala:198:7] wire io_f1_lhist = 1'h0; // @[tage.scala:198:7] wire _s1_update_mask_WIRE_0_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_u_mask_WIRE_0_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_3 = 1'h0; // @[tage.scala:241:50] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_taken_0; // @[tage.scala:198:7] wire io_resp_f3_1_taken_0; // @[tage.scala:198:7] wire io_resp_f3_2_taken_0; // @[tage.scala:198:7] wire io_resp_f3_3_taken_0; // @[tage.scala:198:7] wire [119:0] io_f3_meta_0; // @[tage.scala:198:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [36:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _f3_meta_alt_differs_0_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_1_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_2_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_3_T; // @[tage.scala:275:48] wire _f3_meta_allocate_0_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry; // @[tage.scala:289:26] wire _f3_meta_allocate_1_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_1; // @[tage.scala:289:26] wire _f3_meta_allocate_2_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_2; // @[tage.scala:289:26] wire _f3_meta_allocate_3_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_3; // @[tage.scala:289:26] wire f3_meta_provider_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_0_bits; // @[tage.scala:212:21] wire f3_meta_provider_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_1_bits; // @[tage.scala:212:21] wire f3_meta_provider_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_2_bits; // @[tage.scala:212:21] wire f3_meta_provider_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_3_bits; // @[tage.scala:212:21] wire f3_meta_alt_differs_0; // @[tage.scala:212:21] wire f3_meta_alt_differs_1; // @[tage.scala:212:21] wire f3_meta_alt_differs_2; // @[tage.scala:212:21] wire f3_meta_alt_differs_3; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_0; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_1; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_2; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_3; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_0; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_1; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_2; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_3; // @[tage.scala:212:21] wire f3_meta_allocate_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_0_bits; // @[tage.scala:212:21] wire f3_meta_allocate_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_1_bits; // @[tage.scala:212:21] wire f3_meta_allocate_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_2_bits; // @[tage.scala:212:21] wire f3_meta_allocate_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_3_bits; // @[tage.scala:212:21] wire [3:0] _io_f3_meta_T = {f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_1 = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_2 = {f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_3 = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits, f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits, f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33] wire [5:0] _GEN = {f3_meta_provider_ctr_1, f3_meta_provider_ctr_0}; // @[tage.scala:212:21, :213:33] wire [5:0] lo_1; // @[tage.scala:213:33] assign lo_1 = _GEN; // @[tage.scala:213:33] wire [5:0] io_f3_meta_lo_1; // @[tage.scala:359:25] assign io_f3_meta_lo_1 = _GEN; // @[tage.scala:213:33, :359:25] wire [5:0] _GEN_0 = {f3_meta_provider_ctr_3, f3_meta_provider_ctr_2}; // @[tage.scala:212:21, :213:33] wire [5:0] hi_1; // @[tage.scala:213:33] assign hi_1 = _GEN_0; // @[tage.scala:213:33] wire [5:0] io_f3_meta_hi_1; // @[tage.scala:359:25] assign io_f3_meta_hi_1 = _GEN_0; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_1 = {f3_meta_provider_u_1, f3_meta_provider_u_0}; // @[tage.scala:212:21, :213:33] wire [3:0] lo_2; // @[tage.scala:213:33] assign lo_2 = _GEN_1; // @[tage.scala:213:33] wire [3:0] io_f3_meta_lo_2; // @[tage.scala:359:25] assign io_f3_meta_lo_2 = _GEN_1; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_2 = {f3_meta_provider_u_3, f3_meta_provider_u_2}; // @[tage.scala:212:21, :213:33] wire [3:0] hi_2; // @[tage.scala:213:33] assign hi_2 = _GEN_2; // @[tage.scala:213:33] wire [3:0] io_f3_meta_hi_2; // @[tage.scala:359:25] assign io_f3_meta_hi_2 = _GEN_2; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_3 = {f3_meta_alt_differs_1, f3_meta_alt_differs_0}; // @[tage.scala:212:21, :213:33] wire [1:0] lo_3; // @[tage.scala:213:33] assign lo_3 = _GEN_3; // @[tage.scala:213:33] wire [1:0] io_f3_meta_lo_3; // @[tage.scala:359:25] assign io_f3_meta_lo_3 = _GEN_3; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_4 = {f3_meta_alt_differs_3, f3_meta_alt_differs_2}; // @[tage.scala:212:21, :213:33] wire [1:0] hi_3; // @[tage.scala:213:33] assign hi_3 = _GEN_4; // @[tage.scala:213:33] wire [1:0] io_f3_meta_hi_3; // @[tage.scala:359:25] assign io_f3_meta_hi_3 = _GEN_4; // @[tage.scala:213:33, :359:25] wire [3:0] _io_f3_meta_T_8 = {f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_9 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_10 = {f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_11 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo_4 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits, f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi_4 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits, f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33] wire [27:0] lo_5 = {hi_1, lo_1, hi, lo}; // @[tage.scala:213:33] wire [19:0] hi_hi = {hi_4, lo_4, hi_3, lo_3}; // @[tage.scala:213:33] wire [27:0] hi_5 = {hi_hi, hi_2, lo_2}; // @[tage.scala:213:33] reg t_io_f1_req_valid_REG; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_1; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_1; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_2; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_2; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_3; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_3; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_4; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_4; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_5; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_5; // @[tage.scala:226:35] wire [2:0] f3_resps_0_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_0_bits_u; // @[tage.scala:234:25] wire f3_resps_0_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_1_bits_u; // @[tage.scala:234:25] wire f3_resps_0_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_2_bits_u; // @[tage.scala:234:25] wire f3_resps_0_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_3_bits_u; // @[tage.scala:234:25] wire f3_resps_0_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_0_bits_u; // @[tage.scala:234:25] wire f3_resps_1_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_1_bits_u; // @[tage.scala:234:25] wire f3_resps_1_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_2_bits_u; // @[tage.scala:234:25] wire f3_resps_1_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_3_bits_u; // @[tage.scala:234:25] wire f3_resps_1_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_0_bits_u; // @[tage.scala:234:25] wire f3_resps_2_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_1_bits_u; // @[tage.scala:234:25] wire f3_resps_2_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_2_bits_u; // @[tage.scala:234:25] wire f3_resps_2_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_3_bits_u; // @[tage.scala:234:25] wire f3_resps_2_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_0_bits_u; // @[tage.scala:234:25] wire f3_resps_3_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_1_bits_u; // @[tage.scala:234:25] wire f3_resps_3_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_2_bits_u; // @[tage.scala:234:25] wire f3_resps_3_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_3_bits_u; // @[tage.scala:234:25] wire f3_resps_3_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_0_bits_u; // @[tage.scala:234:25] wire f3_resps_4_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_1_bits_u; // @[tage.scala:234:25] wire f3_resps_4_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_2_bits_u; // @[tage.scala:234:25] wire f3_resps_4_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_3_bits_u; // @[tage.scala:234:25] wire f3_resps_4_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_0_bits_u; // @[tage.scala:234:25] wire f3_resps_5_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_1_bits_u; // @[tage.scala:234:25] wire f3_resps_5_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_2_bits_u; // @[tage.scala:234:25] wire f3_resps_5_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_3_bits_u; // @[tage.scala:234:25] wire f3_resps_5_3_valid; // @[tage.scala:234:25] wire _s1_update_meta_T_21; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_20; // @[tage.scala:236:52] wire _s1_update_meta_T_23; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_22; // @[tage.scala:236:52] wire _s1_update_meta_T_25; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_24; // @[tage.scala:236:52] wire _s1_update_meta_T_27; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_26; // @[tage.scala:236:52] wire _s1_update_meta_T_16; // @[tage.scala:236:52] wire _s1_update_meta_T_17; // @[tage.scala:236:52] wire _s1_update_meta_T_18; // @[tage.scala:236:52] wire _s1_update_meta_T_19; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_12; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_13; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_14; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_15; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_8; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_9; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_10; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_11; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire _s1_update_meta_T_1; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T; // @[tage.scala:236:52] wire _s1_update_meta_T_3; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_2; // @[tage.scala:236:52] wire _s1_update_meta_T_5; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_4; // @[tage.scala:236:52] wire _s1_update_meta_T_7; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_6; // @[tage.scala:236:52] wire s1_update_meta_provider_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_0_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_1_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_2_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_3_bits; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_0; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_1; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_2; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_3; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_0; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_1; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_2; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_3; // @[tage.scala:236:52] wire s1_update_meta_allocate_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_0_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_1_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_2_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_3_bits; // @[tage.scala:236:52] wire [55:0] _s1_update_meta_WIRE = s1_update_bits_meta[55:0]; // @[tage.scala:236:52] assign _s1_update_meta_T = _s1_update_meta_WIRE[2:0]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_bits = _s1_update_meta_T; // @[tage.scala:236:52] assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_valid = _s1_update_meta_T_1; // @[tage.scala:236:52] assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[6:4]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_bits = _s1_update_meta_T_2; // @[tage.scala:236:52] assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_valid = _s1_update_meta_T_3; // @[tage.scala:236:52] assign _s1_update_meta_T_4 = _s1_update_meta_WIRE[10:8]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_bits = _s1_update_meta_T_4; // @[tage.scala:236:52] assign _s1_update_meta_T_5 = _s1_update_meta_WIRE[11]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_valid = _s1_update_meta_T_5; // @[tage.scala:236:52] assign _s1_update_meta_T_6 = _s1_update_meta_WIRE[14:12]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_bits = _s1_update_meta_T_6; // @[tage.scala:236:52] assign _s1_update_meta_T_7 = _s1_update_meta_WIRE[15]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_valid = _s1_update_meta_T_7; // @[tage.scala:236:52] assign _s1_update_meta_T_8 = _s1_update_meta_WIRE[18:16]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_0 = _s1_update_meta_T_8; // @[tage.scala:236:52] assign _s1_update_meta_T_9 = _s1_update_meta_WIRE[21:19]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_1 = _s1_update_meta_T_9; // @[tage.scala:236:52] assign _s1_update_meta_T_10 = _s1_update_meta_WIRE[24:22]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_2 = _s1_update_meta_T_10; // @[tage.scala:236:52] assign _s1_update_meta_T_11 = _s1_update_meta_WIRE[27:25]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_3 = _s1_update_meta_T_11; // @[tage.scala:236:52] assign _s1_update_meta_T_12 = _s1_update_meta_WIRE[29:28]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_0 = _s1_update_meta_T_12; // @[tage.scala:236:52] assign _s1_update_meta_T_13 = _s1_update_meta_WIRE[31:30]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_1 = _s1_update_meta_T_13; // @[tage.scala:236:52] assign _s1_update_meta_T_14 = _s1_update_meta_WIRE[33:32]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_2 = _s1_update_meta_T_14; // @[tage.scala:236:52] assign _s1_update_meta_T_15 = _s1_update_meta_WIRE[35:34]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_3 = _s1_update_meta_T_15; // @[tage.scala:236:52] assign _s1_update_meta_T_16 = _s1_update_meta_WIRE[36]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_0 = _s1_update_meta_T_16; // @[tage.scala:236:52] assign _s1_update_meta_T_17 = _s1_update_meta_WIRE[37]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_1 = _s1_update_meta_T_17; // @[tage.scala:236:52] assign _s1_update_meta_T_18 = _s1_update_meta_WIRE[38]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_2 = _s1_update_meta_T_18; // @[tage.scala:236:52] assign _s1_update_meta_T_19 = _s1_update_meta_WIRE[39]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_3 = _s1_update_meta_T_19; // @[tage.scala:236:52] assign _s1_update_meta_T_20 = _s1_update_meta_WIRE[42:40]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_bits = _s1_update_meta_T_20; // @[tage.scala:236:52] assign _s1_update_meta_T_21 = _s1_update_meta_WIRE[43]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_valid = _s1_update_meta_T_21; // @[tage.scala:236:52] assign _s1_update_meta_T_22 = _s1_update_meta_WIRE[46:44]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_bits = _s1_update_meta_T_22; // @[tage.scala:236:52] assign _s1_update_meta_T_23 = _s1_update_meta_WIRE[47]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_valid = _s1_update_meta_T_23; // @[tage.scala:236:52] assign _s1_update_meta_T_24 = _s1_update_meta_WIRE[50:48]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_bits = _s1_update_meta_T_24; // @[tage.scala:236:52] assign _s1_update_meta_T_25 = _s1_update_meta_WIRE[51]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_valid = _s1_update_meta_T_25; // @[tage.scala:236:52] assign _s1_update_meta_T_26 = _s1_update_meta_WIRE[54:52]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_bits = _s1_update_meta_T_26; // @[tage.scala:236:52] assign _s1_update_meta_T_27 = _s1_update_meta_WIRE[55]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_valid = _s1_update_meta_T_27; // @[tage.scala:236:52] wire [3:0] _s1_update_mispredict_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire [3:0] _s1_update_mispredict_mask_T_1 = {4{s1_update_bits_cfi_mispredicted}}; // @[tage.scala:238:9] wire [3:0] s1_update_mispredict_mask = _s1_update_mispredict_mask_T & _s1_update_mispredict_mask_T_1; // @[OneHot.scala:58:35] wire s1_update_mask_0_0; // @[tage.scala:240:33] wire s1_update_mask_0_1; // @[tage.scala:240:33] wire s1_update_mask_0_2; // @[tage.scala:240:33] wire s1_update_mask_0_3; // @[tage.scala:240:33] wire s1_update_mask_1_0; // @[tage.scala:240:33] wire s1_update_mask_1_1; // @[tage.scala:240:33] wire s1_update_mask_1_2; // @[tage.scala:240:33] wire s1_update_mask_1_3; // @[tage.scala:240:33] wire s1_update_mask_2_0; // @[tage.scala:240:33] wire s1_update_mask_2_1; // @[tage.scala:240:33] wire s1_update_mask_2_2; // @[tage.scala:240:33] wire s1_update_mask_2_3; // @[tage.scala:240:33] wire s1_update_mask_3_0; // @[tage.scala:240:33] wire s1_update_mask_3_1; // @[tage.scala:240:33] wire s1_update_mask_3_2; // @[tage.scala:240:33] wire s1_update_mask_3_3; // @[tage.scala:240:33] wire s1_update_mask_4_0; // @[tage.scala:240:33] wire s1_update_mask_4_1; // @[tage.scala:240:33] wire s1_update_mask_4_2; // @[tage.scala:240:33] wire s1_update_mask_4_3; // @[tage.scala:240:33] wire s1_update_mask_5_0; // @[tage.scala:240:33] wire s1_update_mask_5_1; // @[tage.scala:240:33] wire s1_update_mask_5_2; // @[tage.scala:240:33] wire s1_update_mask_5_3; // @[tage.scala:240:33] wire s1_update_u_mask_0_0; // @[tage.scala:241:35] wire s1_update_u_mask_0_1; // @[tage.scala:241:35] wire s1_update_u_mask_0_2; // @[tage.scala:241:35] wire s1_update_u_mask_0_3; // @[tage.scala:241:35] wire s1_update_u_mask_1_0; // @[tage.scala:241:35] wire s1_update_u_mask_1_1; // @[tage.scala:241:35] wire s1_update_u_mask_1_2; // @[tage.scala:241:35] wire s1_update_u_mask_1_3; // @[tage.scala:241:35] wire s1_update_u_mask_2_0; // @[tage.scala:241:35] wire s1_update_u_mask_2_1; // @[tage.scala:241:35] wire s1_update_u_mask_2_2; // @[tage.scala:241:35] wire s1_update_u_mask_2_3; // @[tage.scala:241:35] wire s1_update_u_mask_3_0; // @[tage.scala:241:35] wire s1_update_u_mask_3_1; // @[tage.scala:241:35] wire s1_update_u_mask_3_2; // @[tage.scala:241:35] wire s1_update_u_mask_3_3; // @[tage.scala:241:35] wire s1_update_u_mask_4_0; // @[tage.scala:241:35] wire s1_update_u_mask_4_1; // @[tage.scala:241:35] wire s1_update_u_mask_4_2; // @[tage.scala:241:35] wire s1_update_u_mask_4_3; // @[tage.scala:241:35] wire s1_update_u_mask_5_0; // @[tage.scala:241:35] wire s1_update_u_mask_5_1; // @[tage.scala:241:35] wire s1_update_u_mask_5_2; // @[tage.scala:241:35] wire s1_update_u_mask_5_3; // @[tage.scala:241:35] wire s1_update_taken_0_0; // @[tage.scala:243:31] wire s1_update_taken_0_1; // @[tage.scala:243:31] wire s1_update_taken_0_2; // @[tage.scala:243:31] wire s1_update_taken_0_3; // @[tage.scala:243:31] wire s1_update_taken_1_0; // @[tage.scala:243:31] wire s1_update_taken_1_1; // @[tage.scala:243:31] wire s1_update_taken_1_2; // @[tage.scala:243:31] wire s1_update_taken_1_3; // @[tage.scala:243:31] wire s1_update_taken_2_0; // @[tage.scala:243:31] wire s1_update_taken_2_1; // @[tage.scala:243:31] wire s1_update_taken_2_2; // @[tage.scala:243:31] wire s1_update_taken_2_3; // @[tage.scala:243:31] wire s1_update_taken_3_0; // @[tage.scala:243:31] wire s1_update_taken_3_1; // @[tage.scala:243:31] wire s1_update_taken_3_2; // @[tage.scala:243:31] wire s1_update_taken_3_3; // @[tage.scala:243:31] wire s1_update_taken_4_0; // @[tage.scala:243:31] wire s1_update_taken_4_1; // @[tage.scala:243:31] wire s1_update_taken_4_2; // @[tage.scala:243:31] wire s1_update_taken_4_3; // @[tage.scala:243:31] wire s1_update_taken_5_0; // @[tage.scala:243:31] wire s1_update_taken_5_1; // @[tage.scala:243:31] wire s1_update_taken_5_2; // @[tage.scala:243:31] wire s1_update_taken_5_3; // @[tage.scala:243:31] wire s1_update_alloc_0_0; // @[tage.scala:245:31] wire s1_update_alloc_0_1; // @[tage.scala:245:31] wire s1_update_alloc_0_2; // @[tage.scala:245:31] wire s1_update_alloc_0_3; // @[tage.scala:245:31] wire s1_update_alloc_1_0; // @[tage.scala:245:31] wire s1_update_alloc_1_1; // @[tage.scala:245:31] wire s1_update_alloc_1_2; // @[tage.scala:245:31] wire s1_update_alloc_1_3; // @[tage.scala:245:31] wire s1_update_alloc_2_0; // @[tage.scala:245:31] wire s1_update_alloc_2_1; // @[tage.scala:245:31] wire s1_update_alloc_2_2; // @[tage.scala:245:31] wire s1_update_alloc_2_3; // @[tage.scala:245:31] wire s1_update_alloc_3_0; // @[tage.scala:245:31] wire s1_update_alloc_3_1; // @[tage.scala:245:31] wire s1_update_alloc_3_2; // @[tage.scala:245:31] wire s1_update_alloc_3_3; // @[tage.scala:245:31] wire s1_update_alloc_4_0; // @[tage.scala:245:31] wire s1_update_alloc_4_1; // @[tage.scala:245:31] wire s1_update_alloc_4_2; // @[tage.scala:245:31] wire s1_update_alloc_4_3; // @[tage.scala:245:31] wire s1_update_alloc_5_0; // @[tage.scala:245:31] wire s1_update_alloc_5_1; // @[tage.scala:245:31] wire s1_update_alloc_5_2; // @[tage.scala:245:31] wire s1_update_alloc_5_3; // @[tage.scala:245:31] wire [1:0] s1_update_u_0_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_3; // @[tage.scala:246:31] wire final_altpred; // @[tage.scala:256:33] wire _io_resp_f3_0_taken_T = f3_resps_0_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_1 = f3_resps_0_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_2 = _io_resp_f3_0_taken_T \| _io_resp_f3_0_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_3 = f3_resps_0_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_4 = _io_resp_f3_0_taken_T_2 ? io_resp_in_0_f3_0_taken_0 : _io_resp_f3_0_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_17 = f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_5 = f3_resps_1_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_6 = f3_resps_1_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_7 = _io_resp_f3_0_taken_T_5 \| _io_resp_f3_0_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_8 = f3_resps_1_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_9 = _io_resp_f3_0_taken_T_7 ? _T_17 : _io_resp_f3_0_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_21 = f3_resps_1_0_valid ? f3_resps_1_0_bits_ctr[2] : _T_17; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_10 = f3_resps_2_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_11 = f3_resps_2_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_12 = _io_resp_f3_0_taken_T_10 \| _io_resp_f3_0_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_13 = f3_resps_2_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_14 = _io_resp_f3_0_taken_T_12 ? _T_21 : _io_resp_f3_0_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_25 = f3_resps_2_0_valid ? f3_resps_2_0_bits_ctr[2] : _T_21; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_15 = f3_resps_3_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_16 = f3_resps_3_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_17 = _io_resp_f3_0_taken_T_15 \| _io_resp_f3_0_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_18 = f3_resps_3_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_19 = _io_resp_f3_0_taken_T_17 ? _T_25 : _io_resp_f3_0_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_29 = f3_resps_3_0_valid ? f3_resps_3_0_bits_ctr[2] : _T_25; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_20 = f3_resps_4_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_21 = f3_resps_4_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_22 = _io_resp_f3_0_taken_T_20 \| _io_resp_f3_0_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_23 = f3_resps_4_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_24 = _io_resp_f3_0_taken_T_22 ? _T_29 : _io_resp_f3_0_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_33 = f3_resps_4_0_valid ? f3_resps_4_0_bits_ctr[2] : _T_29; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_25 = f3_resps_5_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_26 = f3_resps_5_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_27 = _io_resp_f3_0_taken_T_25 \| _io_resp_f3_0_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_28 = f3_resps_5_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_29 = _io_resp_f3_0_taken_T_27 ? _T_33 : _io_resp_f3_0_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_0_taken_0 = f3_resps_5_0_valid ? _io_resp_f3_0_taken_T_29 : f3_resps_4_0_valid ? _io_resp_f3_0_taken_T_24 : f3_resps_3_0_valid ? _io_resp_f3_0_taken_T_19 : f3_resps_2_0_valid ? _io_resp_f3_0_taken_T_14 : f3_resps_1_0_valid ? _io_resp_f3_0_taken_T_9 : f3_resps_0_0_valid ? _io_resp_f3_0_taken_T_4 : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred = f3_resps_5_0_valid ? _T_33 : f3_resps_4_0_valid ? _T_29 : f3_resps_3_0_valid ? _T_25 : f3_resps_2_0_valid ? _T_21 : f3_resps_1_0_valid & f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_0_valid = f3_resps_0_0_valid \| f3_resps_1_0_valid \| f3_resps_2_0_valid \| f3_resps_3_0_valid \| f3_resps_4_0_valid \| f3_resps_5_0_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_0_bits = f3_resps_5_0_valid ? 3'h5 : f3_resps_4_0_valid ? 3'h4 : {1'h0, f3_resps_3_0_valid ? 2'h3 : f3_resps_2_0_valid ? 2'h2 : {1'h0, f3_resps_1_0_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_0_T = final_altpred != io_resp_f3_0_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_0 = _f3_meta_alt_differs_0_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_5 = {{f3_resps_0_0_bits_ctr}, {f3_resps_0_0_bits_ctr}, {f3_resps_5_0_bits_ctr}, {f3_resps_4_0_bits_ctr}, {f3_resps_3_0_bits_ctr}, {f3_resps_2_0_bits_ctr}, {f3_resps_1_0_bits_ctr}, {f3_resps_0_0_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_0 = _GEN_5[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_6 = {{f3_resps_0_0_bits_u}, {f3_resps_0_0_bits_u}, {f3_resps_5_0_bits_u}, {f3_resps_4_0_bits_u}, {f3_resps_3_0_bits_u}, {f3_resps_2_0_bits_u}, {f3_resps_1_0_bits_u}, {f3_resps_0_0_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_0 = _GEN_6[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T = ~f3_resps_0_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_1 = f3_resps_0_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_2 = _allocatable_slots_T & _allocatable_slots_T_1; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_0 = _allocatable_slots_T_2; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_3 = ~f3_resps_1_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_4 = f3_resps_1_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_5 = _allocatable_slots_T_3 & _allocatable_slots_T_4; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1 = _allocatable_slots_T_5; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_6 = ~f3_resps_2_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_7 = f3_resps_2_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_8 = _allocatable_slots_T_6 & _allocatable_slots_T_7; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2 = _allocatable_slots_T_8; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_9 = ~f3_resps_3_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_10 = f3_resps_3_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_11 = _allocatable_slots_T_9 & _allocatable_slots_T_10; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3 = _allocatable_slots_T_11; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_12 = ~f3_resps_4_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_13 = f3_resps_4_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_14 = _allocatable_slots_T_12 & _allocatable_slots_T_13; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_4 = _allocatable_slots_T_14; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_15 = ~f3_resps_5_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_16 = f3_resps_5_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_17 = _allocatable_slots_T_15 & _allocatable_slots_T_16; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_5 = _allocatable_slots_T_17; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi = {_allocatable_slots_WIRE_2, _allocatable_slots_WIRE_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo = {allocatable_slots_lo_hi, _allocatable_slots_WIRE_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi = {_allocatable_slots_WIRE_5, _allocatable_slots_WIRE_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi = {allocatable_slots_hi_hi, _allocatable_slots_WIRE_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_18 = {allocatable_slots_hi, allocatable_slots_lo}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_19 = 8'h1 << f3_meta_provider_0_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_20 = _allocatable_slots_T_19; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_21 = {1'h0, _allocatable_slots_T_19[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_22 = {2'h0, _allocatable_slots_T_19[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_23 = {3'h0, _allocatable_slots_T_19[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_24 = {4'h0, _allocatable_slots_T_19[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_25 = {5'h0, _allocatable_slots_T_19[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_26 = {6'h0, _allocatable_slots_T_19[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_27 = {7'h0, _allocatable_slots_T_19[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_28 = _allocatable_slots_T_20 \| _allocatable_slots_T_21; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_29 = _allocatable_slots_T_28 \| _allocatable_slots_T_22; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_30 = _allocatable_slots_T_29 \| _allocatable_slots_T_23; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_31 = _allocatable_slots_T_30 \| _allocatable_slots_T_24; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_32 = _allocatable_slots_T_31 \| _allocatable_slots_T_25; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_33 = _allocatable_slots_T_32 \| _allocatable_slots_T_26; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_34 = _allocatable_slots_T_33 \| _allocatable_slots_T_27; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_35 = {6{f3_meta_provider_0_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_36 = {2'h0, _allocatable_slots_T_34[5:0] & _allocatable_slots_T_35}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_37 = ~_allocatable_slots_T_36; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots = {2'h0, _allocatable_slots_T_37[5:0] & _allocatable_slots_T_18}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi = {_alloc_lfsr_prng_io_out_2, _alloc_lfsr_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo = {alloc_lfsr_lo_hi, _alloc_lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi = {_alloc_lfsr_prng_io_out_5, _alloc_lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi = {alloc_lfsr_hi_hi, _alloc_lfsr_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr = {alloc_lfsr_hi, alloc_lfsr_lo}; // @[PRNG.scala:95:17] wire _first_entry_T = allocatable_slots[0]; // @[OneHot.scala:48:45] wire _first_entry_T_1 = allocatable_slots[1]; // @[OneHot.scala:48:45] wire _first_entry_T_2 = allocatable_slots[2]; // @[OneHot.scala:48:45] wire _first_entry_T_3 = allocatable_slots[3]; // @[OneHot.scala:48:45] wire _first_entry_T_4 = allocatable_slots[4]; // @[OneHot.scala:48:45] wire _first_entry_T_5 = allocatable_slots[5]; // @[OneHot.scala:48:45] wire _first_entry_T_6 = allocatable_slots[6]; // @[OneHot.scala:48:45] wire _first_entry_T_7 = allocatable_slots[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_8 = {2'h3, ~_first_entry_T_6}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_9 = _first_entry_T_5 ? 3'h5 : _first_entry_T_8; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_10 = _first_entry_T_4 ? 3'h4 : _first_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_11 = _first_entry_T_3 ? 3'h3 : _first_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_12 = _first_entry_T_2 ? 3'h2 : _first_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_13 = _first_entry_T_1 ? 3'h1 : _first_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] first_entry = _first_entry_T ? 3'h0 : _first_entry_T_13; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T = {2'h0, allocatable_slots[5:0] & alloc_lfsr}; // @[PRNG.scala:95:17] wire _masked_entry_T_1 = _masked_entry_T[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_2 = _masked_entry_T[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_3 = _masked_entry_T[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_4 = _masked_entry_T[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_5 = _masked_entry_T[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_6 = _masked_entry_T[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_7 = _masked_entry_T[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_8 = _masked_entry_T[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_9 = {2'h3, ~_masked_entry_T_7}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_10 = _masked_entry_T_6 ? 3'h5 : _masked_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_11 = _masked_entry_T_5 ? 3'h4 : _masked_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_12 = _masked_entry_T_4 ? 3'h3 : _masked_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_13 = _masked_entry_T_3 ? 3'h2 : _masked_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_14 = _masked_entry_T_2 ? 3'h1 : _masked_entry_T_13; // @[OneHot.scala:48:45] wire [2:0] masked_entry = _masked_entry_T_1 ? 3'h0 : _masked_entry_T_14; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T = allocatable_slots >> masked_entry; // @[Mux.scala:50:70] wire _alloc_entry_T_1 = _alloc_entry_T[0]; // @[tage.scala:289:44] assign alloc_entry = _alloc_entry_T_1 ? masked_entry : first_entry; // @[Mux.scala:50:70] assign f3_meta_allocate_0_bits = alloc_entry; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_0_valid_T = \|allocatable_slots; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_0_valid = _f3_meta_allocate_0_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[tage.scala:297:58] wire _update_was_taken_T_1 = s1_update_bits_cfi_idx_valid & _update_was_taken_T; // @[tage.scala:296:58, :297:58] wire update_was_taken = _update_was_taken_T_1 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire [4:0] _GEN_7 = {s1_update_bits_is_mispredict_update \| s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30] wire _T_44 = s1_update_bits_br_mask[0] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_8 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_9 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_10 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_11 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_12 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_13 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T = s1_update_mispredict_mask[0]; // @[tage.scala:237:73, :308:52] wire _new_u_T_1 = ~s1_update_meta_alt_differs_0; // @[tage.scala:217:9, :236:52] wire _new_u_T_2 = s1_update_meta_provider_u_0 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_14 = {1'h0, s1_update_meta_provider_u_0}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_3 = _GEN_14 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_4 = _new_u_T_3[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_5 = _new_u_T_2 ? 2'h0 : _new_u_T_4; // @[tage.scala:218:{24,27,43}] wire _new_u_T_6 = &s1_update_meta_provider_u_0; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_7 = _GEN_14 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_8 = _new_u_T_7[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_9 = _new_u_T_6 ? 2'h3 : _new_u_T_8; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_10 = _new_u_T ? _new_u_T_5 : _new_u_T_9; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u = _new_u_T_1 ? s1_update_meta_provider_u_0 : _new_u_T_10; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_1; // @[tage.scala:256:33] wire _io_resp_f3_1_taken_T = f3_resps_0_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_1 = f3_resps_0_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_2 = _io_resp_f3_1_taken_T \| _io_resp_f3_1_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_3 = f3_resps_0_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_4 = _io_resp_f3_1_taken_T_2 ? io_resp_in_0_f3_1_taken_0 : _io_resp_f3_1_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_48 = f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_5 = f3_resps_1_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_6 = f3_resps_1_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_7 = _io_resp_f3_1_taken_T_5 \| _io_resp_f3_1_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_8 = f3_resps_1_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_9 = _io_resp_f3_1_taken_T_7 ? _T_48 : _io_resp_f3_1_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_52 = f3_resps_1_1_valid ? f3_resps_1_1_bits_ctr[2] : _T_48; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_10 = f3_resps_2_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_11 = f3_resps_2_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_12 = _io_resp_f3_1_taken_T_10 \| _io_resp_f3_1_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_13 = f3_resps_2_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_14 = _io_resp_f3_1_taken_T_12 ? _T_52 : _io_resp_f3_1_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_56 = f3_resps_2_1_valid ? f3_resps_2_1_bits_ctr[2] : _T_52; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_15 = f3_resps_3_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_16 = f3_resps_3_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_17 = _io_resp_f3_1_taken_T_15 \| _io_resp_f3_1_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_18 = f3_resps_3_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_19 = _io_resp_f3_1_taken_T_17 ? _T_56 : _io_resp_f3_1_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_60 = f3_resps_3_1_valid ? f3_resps_3_1_bits_ctr[2] : _T_56; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_20 = f3_resps_4_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_21 = f3_resps_4_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_22 = _io_resp_f3_1_taken_T_20 \| _io_resp_f3_1_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_23 = f3_resps_4_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_24 = _io_resp_f3_1_taken_T_22 ? _T_60 : _io_resp_f3_1_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_64 = f3_resps_4_1_valid ? f3_resps_4_1_bits_ctr[2] : _T_60; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_25 = f3_resps_5_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_26 = f3_resps_5_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_27 = _io_resp_f3_1_taken_T_25 \| _io_resp_f3_1_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_28 = f3_resps_5_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_29 = _io_resp_f3_1_taken_T_27 ? _T_64 : _io_resp_f3_1_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_1_taken_0 = f3_resps_5_1_valid ? _io_resp_f3_1_taken_T_29 : f3_resps_4_1_valid ? _io_resp_f3_1_taken_T_24 : f3_resps_3_1_valid ? _io_resp_f3_1_taken_T_19 : f3_resps_2_1_valid ? _io_resp_f3_1_taken_T_14 : f3_resps_1_1_valid ? _io_resp_f3_1_taken_T_9 : f3_resps_0_1_valid ? _io_resp_f3_1_taken_T_4 : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_1 = f3_resps_5_1_valid ? _T_64 : f3_resps_4_1_valid ? _T_60 : f3_resps_3_1_valid ? _T_56 : f3_resps_2_1_valid ? _T_52 : f3_resps_1_1_valid & f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_1_valid = f3_resps_0_1_valid \| f3_resps_1_1_valid \| f3_resps_2_1_valid \| f3_resps_3_1_valid \| f3_resps_4_1_valid \| f3_resps_5_1_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_1_bits = f3_resps_5_1_valid ? 3'h5 : f3_resps_4_1_valid ? 3'h4 : {1'h0, f3_resps_3_1_valid ? 2'h3 : f3_resps_2_1_valid ? 2'h2 : {1'h0, f3_resps_1_1_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_1_T = final_altpred_1 != io_resp_f3_1_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_1 = _f3_meta_alt_differs_1_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_15 = {{f3_resps_0_1_bits_ctr}, {f3_resps_0_1_bits_ctr}, {f3_resps_5_1_bits_ctr}, {f3_resps_4_1_bits_ctr}, {f3_resps_3_1_bits_ctr}, {f3_resps_2_1_bits_ctr}, {f3_resps_1_1_bits_ctr}, {f3_resps_0_1_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_1 = _GEN_15[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_16 = {{f3_resps_0_1_bits_u}, {f3_resps_0_1_bits_u}, {f3_resps_5_1_bits_u}, {f3_resps_4_1_bits_u}, {f3_resps_3_1_bits_u}, {f3_resps_2_1_bits_u}, {f3_resps_1_1_bits_u}, {f3_resps_0_1_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_1 = _GEN_16[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_38 = ~f3_resps_0_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_39 = f3_resps_0_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_40 = _allocatable_slots_T_38 & _allocatable_slots_T_39; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_0 = _allocatable_slots_T_40; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_41 = ~f3_resps_1_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_42 = f3_resps_1_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_43 = _allocatable_slots_T_41 & _allocatable_slots_T_42; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_1 = _allocatable_slots_T_43; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_44 = ~f3_resps_2_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_45 = f3_resps_2_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_46 = _allocatable_slots_T_44 & _allocatable_slots_T_45; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_2 = _allocatable_slots_T_46; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_47 = ~f3_resps_3_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_48 = f3_resps_3_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_49 = _allocatable_slots_T_47 & _allocatable_slots_T_48; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_3 = _allocatable_slots_T_49; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_50 = ~f3_resps_4_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_51 = f3_resps_4_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_52 = _allocatable_slots_T_50 & _allocatable_slots_T_51; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_4 = _allocatable_slots_T_52; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_53 = ~f3_resps_5_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_54 = f3_resps_5_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_55 = _allocatable_slots_T_53 & _allocatable_slots_T_54; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_5 = _allocatable_slots_T_55; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_1 = {_allocatable_slots_WIRE_1_2, _allocatable_slots_WIRE_1_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_1 = {allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_1 = {_allocatable_slots_WIRE_1_5, _allocatable_slots_WIRE_1_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_1 = {allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_56 = {allocatable_slots_hi_1, allocatable_slots_lo_1}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_57 = 8'h1 << f3_meta_provider_1_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_58 = _allocatable_slots_T_57; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_59 = {1'h0, _allocatable_slots_T_57[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_60 = {2'h0, _allocatable_slots_T_57[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_61 = {3'h0, _allocatable_slots_T_57[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_62 = {4'h0, _allocatable_slots_T_57[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_63 = {5'h0, _allocatable_slots_T_57[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_64 = {6'h0, _allocatable_slots_T_57[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_65 = {7'h0, _allocatable_slots_T_57[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_66 = _allocatable_slots_T_58 \| _allocatable_slots_T_59; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_67 = _allocatable_slots_T_66 \| _allocatable_slots_T_60; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_68 = _allocatable_slots_T_67 \| _allocatable_slots_T_61; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_69 = _allocatable_slots_T_68 \| _allocatable_slots_T_62; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_70 = _allocatable_slots_T_69 \| _allocatable_slots_T_63; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_71 = _allocatable_slots_T_70 \| _allocatable_slots_T_64; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_72 = _allocatable_slots_T_71 \| _allocatable_slots_T_65; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_73 = {6{f3_meta_provider_1_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_74 = {2'h0, _allocatable_slots_T_72[5:0] & _allocatable_slots_T_73}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_75 = ~_allocatable_slots_T_74; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_1 = {2'h0, _allocatable_slots_T_75[5:0] & _allocatable_slots_T_56}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_1 = {_alloc_lfsr_prng_1_io_out_2, _alloc_lfsr_prng_1_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_1 = {alloc_lfsr_lo_hi_1, _alloc_lfsr_prng_1_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_1 = {_alloc_lfsr_prng_1_io_out_5, _alloc_lfsr_prng_1_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_1 = {alloc_lfsr_hi_hi_1, _alloc_lfsr_prng_1_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_1 = {alloc_lfsr_hi_1, alloc_lfsr_lo_1}; // @[PRNG.scala:95:17] wire _first_entry_T_14 = allocatable_slots_1[0]; // @[OneHot.scala:48:45] wire _first_entry_T_15 = allocatable_slots_1[1]; // @[OneHot.scala:48:45] wire _first_entry_T_16 = allocatable_slots_1[2]; // @[OneHot.scala:48:45] wire _first_entry_T_17 = allocatable_slots_1[3]; // @[OneHot.scala:48:45] wire _first_entry_T_18 = allocatable_slots_1[4]; // @[OneHot.scala:48:45] wire _first_entry_T_19 = allocatable_slots_1[5]; // @[OneHot.scala:48:45] wire _first_entry_T_20 = allocatable_slots_1[6]; // @[OneHot.scala:48:45] wire _first_entry_T_21 = allocatable_slots_1[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_22 = {2'h3, ~_first_entry_T_20}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_23 = _first_entry_T_19 ? 3'h5 : _first_entry_T_22; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_24 = _first_entry_T_18 ? 3'h4 : _first_entry_T_23; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_25 = _first_entry_T_17 ? 3'h3 : _first_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_26 = _first_entry_T_16 ? 3'h2 : _first_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_27 = _first_entry_T_15 ? 3'h1 : _first_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] first_entry_1 = _first_entry_T_14 ? 3'h0 : _first_entry_T_27; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_15 = {2'h0, allocatable_slots_1[5:0] & alloc_lfsr_1}; // @[PRNG.scala:95:17] wire _masked_entry_T_16 = _masked_entry_T_15[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_17 = _masked_entry_T_15[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_18 = _masked_entry_T_15[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_19 = _masked_entry_T_15[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_20 = _masked_entry_T_15[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_21 = _masked_entry_T_15[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_22 = _masked_entry_T_15[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_23 = _masked_entry_T_15[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_24 = {2'h3, ~_masked_entry_T_22}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_25 = _masked_entry_T_21 ? 3'h5 : _masked_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_26 = _masked_entry_T_20 ? 3'h4 : _masked_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_27 = _masked_entry_T_19 ? 3'h3 : _masked_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_28 = _masked_entry_T_18 ? 3'h2 : _masked_entry_T_27; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_29 = _masked_entry_T_17 ? 3'h1 : _masked_entry_T_28; // @[OneHot.scala:48:45] wire [2:0] masked_entry_1 = _masked_entry_T_16 ? 3'h0 : _masked_entry_T_29; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_2 = allocatable_slots_1 >> masked_entry_1; // @[Mux.scala:50:70] wire _alloc_entry_T_3 = _alloc_entry_T_2[0]; // @[tage.scala:289:44] assign alloc_entry_1 = _alloc_entry_T_3 ? masked_entry_1 : first_entry_1; // @[Mux.scala:50:70] assign f3_meta_allocate_1_bits = alloc_entry_1; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_1_valid_T = \|allocatable_slots_1; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_1_valid = _f3_meta_allocate_1_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_2 = s1_update_bits_cfi_idx_bits == 2'h1; // @[tage.scala:297:58] wire _update_was_taken_T_3 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_2; // @[tage.scala:296:58, :297:58] wire update_was_taken_1 = _update_was_taken_T_3 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_75 = s1_update_bits_br_mask[1] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_17 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_18 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_19 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_20 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_21 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_22 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_11 = s1_update_mispredict_mask[1]; // @[tage.scala:237:73, :308:52] wire _new_u_T_12 = ~s1_update_meta_alt_differs_1; // @[tage.scala:217:9, :236:52] wire _new_u_T_13 = s1_update_meta_provider_u_1 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_23 = {1'h0, s1_update_meta_provider_u_1}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_14 = _GEN_23 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_15 = _new_u_T_14[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_16 = _new_u_T_13 ? 2'h0 : _new_u_T_15; // @[tage.scala:218:{24,27,43}] wire _new_u_T_17 = &s1_update_meta_provider_u_1; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_18 = _GEN_23 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_19 = _new_u_T_18[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_20 = _new_u_T_17 ? 2'h3 : _new_u_T_19; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_21 = _new_u_T_11 ? _new_u_T_16 : _new_u_T_20; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_1 = _new_u_T_12 ? s1_update_meta_provider_u_1 : _new_u_T_21; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_2; // @[tage.scala:256:33] wire _io_resp_f3_2_taken_T = f3_resps_0_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_1 = f3_resps_0_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_2 = _io_resp_f3_2_taken_T \| _io_resp_f3_2_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_3 = f3_resps_0_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_4 = _io_resp_f3_2_taken_T_2 ? io_resp_in_0_f3_2_taken_0 : _io_resp_f3_2_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_79 = f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_5 = f3_resps_1_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_6 = f3_resps_1_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_7 = _io_resp_f3_2_taken_T_5 \| _io_resp_f3_2_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_8 = f3_resps_1_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_9 = _io_resp_f3_2_taken_T_7 ? _T_79 : _io_resp_f3_2_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_83 = f3_resps_1_2_valid ? f3_resps_1_2_bits_ctr[2] : _T_79; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_10 = f3_resps_2_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_11 = f3_resps_2_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_12 = _io_resp_f3_2_taken_T_10 \| _io_resp_f3_2_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_13 = f3_resps_2_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_14 = _io_resp_f3_2_taken_T_12 ? _T_83 : _io_resp_f3_2_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_87 = f3_resps_2_2_valid ? f3_resps_2_2_bits_ctr[2] : _T_83; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_15 = f3_resps_3_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_16 = f3_resps_3_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_17 = _io_resp_f3_2_taken_T_15 \| _io_resp_f3_2_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_18 = f3_resps_3_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_19 = _io_resp_f3_2_taken_T_17 ? _T_87 : _io_resp_f3_2_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_91 = f3_resps_3_2_valid ? f3_resps_3_2_bits_ctr[2] : _T_87; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_20 = f3_resps_4_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_21 = f3_resps_4_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_22 = _io_resp_f3_2_taken_T_20 \| _io_resp_f3_2_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_23 = f3_resps_4_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_24 = _io_resp_f3_2_taken_T_22 ? _T_91 : _io_resp_f3_2_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_95 = f3_resps_4_2_valid ? f3_resps_4_2_bits_ctr[2] : _T_91; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_25 = f3_resps_5_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_26 = f3_resps_5_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_27 = _io_resp_f3_2_taken_T_25 \| _io_resp_f3_2_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_28 = f3_resps_5_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_29 = _io_resp_f3_2_taken_T_27 ? _T_95 : _io_resp_f3_2_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_2_taken_0 = f3_resps_5_2_valid ? _io_resp_f3_2_taken_T_29 : f3_resps_4_2_valid ? _io_resp_f3_2_taken_T_24 : f3_resps_3_2_valid ? _io_resp_f3_2_taken_T_19 : f3_resps_2_2_valid ? _io_resp_f3_2_taken_T_14 : f3_resps_1_2_valid ? _io_resp_f3_2_taken_T_9 : f3_resps_0_2_valid ? _io_resp_f3_2_taken_T_4 : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_2 = f3_resps_5_2_valid ? _T_95 : f3_resps_4_2_valid ? _T_91 : f3_resps_3_2_valid ? _T_87 : f3_resps_2_2_valid ? _T_83 : f3_resps_1_2_valid & f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_2_valid = f3_resps_0_2_valid \| f3_resps_1_2_valid \| f3_resps_2_2_valid \| f3_resps_3_2_valid \| f3_resps_4_2_valid \| f3_resps_5_2_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_2_bits = f3_resps_5_2_valid ? 3'h5 : f3_resps_4_2_valid ? 3'h4 : {1'h0, f3_resps_3_2_valid ? 2'h3 : f3_resps_2_2_valid ? 2'h2 : {1'h0, f3_resps_1_2_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_2_T = final_altpred_2 != io_resp_f3_2_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_2 = _f3_meta_alt_differs_2_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_24 = {{f3_resps_0_2_bits_ctr}, {f3_resps_0_2_bits_ctr}, {f3_resps_5_2_bits_ctr}, {f3_resps_4_2_bits_ctr}, {f3_resps_3_2_bits_ctr}, {f3_resps_2_2_bits_ctr}, {f3_resps_1_2_bits_ctr}, {f3_resps_0_2_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_2 = _GEN_24[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_25 = {{f3_resps_0_2_bits_u}, {f3_resps_0_2_bits_u}, {f3_resps_5_2_bits_u}, {f3_resps_4_2_bits_u}, {f3_resps_3_2_bits_u}, {f3_resps_2_2_bits_u}, {f3_resps_1_2_bits_u}, {f3_resps_0_2_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_2 = _GEN_25[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_76 = ~f3_resps_0_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_77 = f3_resps_0_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_78 = _allocatable_slots_T_76 & _allocatable_slots_T_77; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_0 = _allocatable_slots_T_78; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_79 = ~f3_resps_1_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_80 = f3_resps_1_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_81 = _allocatable_slots_T_79 & _allocatable_slots_T_80; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_1 = _allocatable_slots_T_81; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_82 = ~f3_resps_2_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_83 = f3_resps_2_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_84 = _allocatable_slots_T_82 & _allocatable_slots_T_83; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_2 = _allocatable_slots_T_84; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_85 = ~f3_resps_3_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_86 = f3_resps_3_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_87 = _allocatable_slots_T_85 & _allocatable_slots_T_86; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_3 = _allocatable_slots_T_87; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_88 = ~f3_resps_4_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_89 = f3_resps_4_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_90 = _allocatable_slots_T_88 & _allocatable_slots_T_89; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_4 = _allocatable_slots_T_90; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_91 = ~f3_resps_5_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_92 = f3_resps_5_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_93 = _allocatable_slots_T_91 & _allocatable_slots_T_92; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_5 = _allocatable_slots_T_93; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_2 = {_allocatable_slots_WIRE_2_2, _allocatable_slots_WIRE_2_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_2 = {allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_2 = {_allocatable_slots_WIRE_2_5, _allocatable_slots_WIRE_2_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_2 = {allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_94 = {allocatable_slots_hi_2, allocatable_slots_lo_2}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_95 = 8'h1 << f3_meta_provider_2_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_96 = _allocatable_slots_T_95; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_97 = {1'h0, _allocatable_slots_T_95[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_98 = {2'h0, _allocatable_slots_T_95[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_99 = {3'h0, _allocatable_slots_T_95[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_100 = {4'h0, _allocatable_slots_T_95[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_101 = {5'h0, _allocatable_slots_T_95[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_102 = {6'h0, _allocatable_slots_T_95[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_103 = {7'h0, _allocatable_slots_T_95[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_104 = _allocatable_slots_T_96 \| _allocatable_slots_T_97; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_105 = _allocatable_slots_T_104 \| _allocatable_slots_T_98; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_106 = _allocatable_slots_T_105 \| _allocatable_slots_T_99; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_107 = _allocatable_slots_T_106 \| _allocatable_slots_T_100; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_108 = _allocatable_slots_T_107 \| _allocatable_slots_T_101; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_109 = _allocatable_slots_T_108 \| _allocatable_slots_T_102; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_110 = _allocatable_slots_T_109 \| _allocatable_slots_T_103; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_111 = {6{f3_meta_provider_2_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_112 = {2'h0, _allocatable_slots_T_110[5:0] & _allocatable_slots_T_111}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_113 = ~_allocatable_slots_T_112; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_2 = {2'h0, _allocatable_slots_T_113[5:0] & _allocatable_slots_T_94}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_2 = {_alloc_lfsr_prng_2_io_out_2, _alloc_lfsr_prng_2_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_2 = {alloc_lfsr_lo_hi_2, _alloc_lfsr_prng_2_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_2 = {_alloc_lfsr_prng_2_io_out_5, _alloc_lfsr_prng_2_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_2 = {alloc_lfsr_hi_hi_2, _alloc_lfsr_prng_2_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_2 = {alloc_lfsr_hi_2, alloc_lfsr_lo_2}; // @[PRNG.scala:95:17] wire _first_entry_T_28 = allocatable_slots_2[0]; // @[OneHot.scala:48:45] wire _first_entry_T_29 = allocatable_slots_2[1]; // @[OneHot.scala:48:45] wire _first_entry_T_30 = allocatable_slots_2[2]; // @[OneHot.scala:48:45] wire _first_entry_T_31 = allocatable_slots_2[3]; // @[OneHot.scala:48:45] wire _first_entry_T_32 = allocatable_slots_2[4]; // @[OneHot.scala:48:45] wire _first_entry_T_33 = allocatable_slots_2[5]; // @[OneHot.scala:48:45] wire _first_entry_T_34 = allocatable_slots_2[6]; // @[OneHot.scala:48:45] wire _first_entry_T_35 = allocatable_slots_2[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_36 = {2'h3, ~_first_entry_T_34}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_37 = _first_entry_T_33 ? 3'h5 : _first_entry_T_36; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_38 = _first_entry_T_32 ? 3'h4 : _first_entry_T_37; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_39 = _first_entry_T_31 ? 3'h3 : _first_entry_T_38; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_40 = _first_entry_T_30 ? 3'h2 : _first_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_41 = _first_entry_T_29 ? 3'h1 : _first_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] first_entry_2 = _first_entry_T_28 ? 3'h0 : _first_entry_T_41; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_30 = {2'h0, allocatable_slots_2[5:0] & alloc_lfsr_2}; // @[PRNG.scala:95:17] wire _masked_entry_T_31 = _masked_entry_T_30[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_32 = _masked_entry_T_30[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_33 = _masked_entry_T_30[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_34 = _masked_entry_T_30[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_35 = _masked_entry_T_30[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_36 = _masked_entry_T_30[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_37 = _masked_entry_T_30[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_38 = _masked_entry_T_30[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_39 = {2'h3, ~_masked_entry_T_37}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_40 = _masked_entry_T_36 ? 3'h5 : _masked_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_41 = _masked_entry_T_35 ? 3'h4 : _masked_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_42 = _masked_entry_T_34 ? 3'h3 : _masked_entry_T_41; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_43 = _masked_entry_T_33 ? 3'h2 : _masked_entry_T_42; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_44 = _masked_entry_T_32 ? 3'h1 : _masked_entry_T_43; // @[OneHot.scala:48:45] wire [2:0] masked_entry_2 = _masked_entry_T_31 ? 3'h0 : _masked_entry_T_44; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_4 = allocatable_slots_2 >> masked_entry_2; // @[Mux.scala:50:70] wire _alloc_entry_T_5 = _alloc_entry_T_4[0]; // @[tage.scala:289:44] assign alloc_entry_2 = _alloc_entry_T_5 ? masked_entry_2 : first_entry_2; // @[Mux.scala:50:70] assign f3_meta_allocate_2_bits = alloc_entry_2; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_2_valid_T = \|allocatable_slots_2; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_2_valid = _f3_meta_allocate_2_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_4 = s1_update_bits_cfi_idx_bits == 2'h2; // @[tage.scala:297:58] wire _update_was_taken_T_5 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_4; // @[tage.scala:296:58, :297:58] wire update_was_taken_2 = _update_was_taken_T_5 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_106 = s1_update_bits_br_mask[2] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_26 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_27 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_28 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_29 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_30 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_31 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_22 = s1_update_mispredict_mask[2]; // @[tage.scala:237:73, :308:52] wire _new_u_T_23 = ~s1_update_meta_alt_differs_2; // @[tage.scala:217:9, :236:52] wire _new_u_T_24 = s1_update_meta_provider_u_2 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_32 = {1'h0, s1_update_meta_provider_u_2}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_25 = _GEN_32 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_26 = _new_u_T_25[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_27 = _new_u_T_24 ? 2'h0 : _new_u_T_26; // @[tage.scala:218:{24,27,43}] wire _new_u_T_28 = &s1_update_meta_provider_u_2; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_29 = _GEN_32 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_30 = _new_u_T_29[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_31 = _new_u_T_28 ? 2'h3 : _new_u_T_30; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_32 = _new_u_T_22 ? _new_u_T_27 : _new_u_T_31; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_2 = _new_u_T_23 ? s1_update_meta_provider_u_2 : _new_u_T_32; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_3; // @[tage.scala:256:33] wire _io_resp_f3_3_taken_T = f3_resps_0_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_1 = f3_resps_0_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_2 = _io_resp_f3_3_taken_T \| _io_resp_f3_3_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_3 = f3_resps_0_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_4 = _io_resp_f3_3_taken_T_2 ? io_resp_in_0_f3_3_taken_0 : _io_resp_f3_3_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_110 = f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_5 = f3_resps_1_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_6 = f3_resps_1_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_7 = _io_resp_f3_3_taken_T_5 \| _io_resp_f3_3_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_8 = f3_resps_1_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_9 = _io_resp_f3_3_taken_T_7 ? _T_110 : _io_resp_f3_3_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_114 = f3_resps_1_3_valid ? f3_resps_1_3_bits_ctr[2] : _T_110; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_10 = f3_resps_2_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_11 = f3_resps_2_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_12 = _io_resp_f3_3_taken_T_10 \| _io_resp_f3_3_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_13 = f3_resps_2_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_14 = _io_resp_f3_3_taken_T_12 ? _T_114 : _io_resp_f3_3_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_118 = f3_resps_2_3_valid ? f3_resps_2_3_bits_ctr[2] : _T_114; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_15 = f3_resps_3_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_16 = f3_resps_3_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_17 = _io_resp_f3_3_taken_T_15 \| _io_resp_f3_3_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_18 = f3_resps_3_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_19 = _io_resp_f3_3_taken_T_17 ? _T_118 : _io_resp_f3_3_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_122 = f3_resps_3_3_valid ? f3_resps_3_3_bits_ctr[2] : _T_118; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_20 = f3_resps_4_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_21 = f3_resps_4_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_22 = _io_resp_f3_3_taken_T_20 \| _io_resp_f3_3_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_23 = f3_resps_4_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_24 = _io_resp_f3_3_taken_T_22 ? _T_122 : _io_resp_f3_3_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_126 = f3_resps_4_3_valid ? f3_resps_4_3_bits_ctr[2] : _T_122; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_25 = f3_resps_5_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_26 = f3_resps_5_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_27 = _io_resp_f3_3_taken_T_25 \| _io_resp_f3_3_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_28 = f3_resps_5_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_29 = _io_resp_f3_3_taken_T_27 ? _T_126 : _io_resp_f3_3_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_3_taken_0 = f3_resps_5_3_valid ? _io_resp_f3_3_taken_T_29 : f3_resps_4_3_valid ? _io_resp_f3_3_taken_T_24 : f3_resps_3_3_valid ? _io_resp_f3_3_taken_T_19 : f3_resps_2_3_valid ? _io_resp_f3_3_taken_T_14 : f3_resps_1_3_valid ? _io_resp_f3_3_taken_T_9 : f3_resps_0_3_valid ? _io_resp_f3_3_taken_T_4 : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_3 = f3_resps_5_3_valid ? _T_126 : f3_resps_4_3_valid ? _T_122 : f3_resps_3_3_valid ? _T_118 : f3_resps_2_3_valid ? _T_114 : f3_resps_1_3_valid & f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_3_valid = f3_resps_0_3_valid \| f3_resps_1_3_valid \| f3_resps_2_3_valid \| f3_resps_3_3_valid \| f3_resps_4_3_valid \| f3_resps_5_3_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_3_bits = f3_resps_5_3_valid ? 3'h5 : f3_resps_4_3_valid ? 3'h4 : {1'h0, f3_resps_3_3_valid ? 2'h3 : f3_resps_2_3_valid ? 2'h2 : {1'h0, f3_resps_1_3_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_3_T = final_altpred_3 != io_resp_f3_3_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_3 = _f3_meta_alt_differs_3_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_33 = {{f3_resps_0_3_bits_ctr}, {f3_resps_0_3_bits_ctr}, {f3_resps_5_3_bits_ctr}, {f3_resps_4_3_bits_ctr}, {f3_resps_3_3_bits_ctr}, {f3_resps_2_3_bits_ctr}, {f3_resps_1_3_bits_ctr}, {f3_resps_0_3_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_3 = _GEN_33[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_34 = {{f3_resps_0_3_bits_u}, {f3_resps_0_3_bits_u}, {f3_resps_5_3_bits_u}, {f3_resps_4_3_bits_u}, {f3_resps_3_3_bits_u}, {f3_resps_2_3_bits_u}, {f3_resps_1_3_bits_u}, {f3_resps_0_3_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_3 = _GEN_34[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_114 = ~f3_resps_0_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_115 = f3_resps_0_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_116 = _allocatable_slots_T_114 & _allocatable_slots_T_115; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_0 = _allocatable_slots_T_116; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_117 = ~f3_resps_1_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_118 = f3_resps_1_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_119 = _allocatable_slots_T_117 & _allocatable_slots_T_118; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_1 = _allocatable_slots_T_119; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_120 = ~f3_resps_2_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_121 = f3_resps_2_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_122 = _allocatable_slots_T_120 & _allocatable_slots_T_121; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_2 = _allocatable_slots_T_122; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_123 = ~f3_resps_3_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_124 = f3_resps_3_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_125 = _allocatable_slots_T_123 & _allocatable_slots_T_124; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_3 = _allocatable_slots_T_125; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_126 = ~f3_resps_4_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_127 = f3_resps_4_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_128 = _allocatable_slots_T_126 & _allocatable_slots_T_127; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_4 = _allocatable_slots_T_128; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_129 = ~f3_resps_5_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_130 = f3_resps_5_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_131 = _allocatable_slots_T_129 & _allocatable_slots_T_130; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_5 = _allocatable_slots_T_131; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_3 = {_allocatable_slots_WIRE_3_2, _allocatable_slots_WIRE_3_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_3 = {allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_3 = {_allocatable_slots_WIRE_3_5, _allocatable_slots_WIRE_3_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_3 = {allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_132 = {allocatable_slots_hi_3, allocatable_slots_lo_3}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_133 = 8'h1 << f3_meta_provider_3_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_134 = _allocatable_slots_T_133; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_135 = {1'h0, _allocatable_slots_T_133[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_136 = {2'h0, _allocatable_slots_T_133[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_137 = {3'h0, _allocatable_slots_T_133[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_138 = {4'h0, _allocatable_slots_T_133[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_139 = {5'h0, _allocatable_slots_T_133[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_140 = {6'h0, _allocatable_slots_T_133[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_141 = {7'h0, _allocatable_slots_T_133[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_142 = _allocatable_slots_T_134 \| _allocatable_slots_T_135; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_143 = _allocatable_slots_T_142 \| _allocatable_slots_T_136; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_144 = _allocatable_slots_T_143 \| _allocatable_slots_T_137; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_145 = _allocatable_slots_T_144 \| _allocatable_slots_T_138; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_146 = _allocatable_slots_T_145 \| _allocatable_slots_T_139; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_147 = _allocatable_slots_T_146 \| _allocatable_slots_T_140; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_148 = _allocatable_slots_T_147 \| _allocatable_slots_T_141; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_149 = {6{f3_meta_provider_3_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_150 = {2'h0, _allocatable_slots_T_148[5:0] & _allocatable_slots_T_149}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_151 = ~_allocatable_slots_T_150; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_3 = {2'h0, _allocatable_slots_T_151[5:0] & _allocatable_slots_T_132}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_3 = {_alloc_lfsr_prng_3_io_out_2, _alloc_lfsr_prng_3_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_3 = {alloc_lfsr_lo_hi_3, _alloc_lfsr_prng_3_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_3 = {_alloc_lfsr_prng_3_io_out_5, _alloc_lfsr_prng_3_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_3 = {alloc_lfsr_hi_hi_3, _alloc_lfsr_prng_3_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_3 = {alloc_lfsr_hi_3, alloc_lfsr_lo_3}; // @[PRNG.scala:95:17] wire _first_entry_T_42 = allocatable_slots_3[0]; // @[OneHot.scala:48:45] wire _first_entry_T_43 = allocatable_slots_3[1]; // @[OneHot.scala:48:45] wire _first_entry_T_44 = allocatable_slots_3[2]; // @[OneHot.scala:48:45] wire _first_entry_T_45 = allocatable_slots_3[3]; // @[OneHot.scala:48:45] wire _first_entry_T_46 = allocatable_slots_3[4]; // @[OneHot.scala:48:45] wire _first_entry_T_47 = allocatable_slots_3[5]; // @[OneHot.scala:48:45] wire _first_entry_T_48 = allocatable_slots_3[6]; // @[OneHot.scala:48:45] wire _first_entry_T_49 = allocatable_slots_3[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_50 = {2'h3, ~_first_entry_T_48}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_51 = _first_entry_T_47 ? 3'h5 : _first_entry_T_50; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_52 = _first_entry_T_46 ? 3'h4 : _first_entry_T_51; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_53 = _first_entry_T_45 ? 3'h3 : _first_entry_T_52; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_54 = _first_entry_T_44 ? 3'h2 : _first_entry_T_53; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_55 = _first_entry_T_43 ? 3'h1 : _first_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] first_entry_3 = _first_entry_T_42 ? 3'h0 : _first_entry_T_55; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_45 = {2'h0, allocatable_slots_3[5:0] & alloc_lfsr_3}; // @[PRNG.scala:95:17] wire _masked_entry_T_46 = _masked_entry_T_45[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_47 = _masked_entry_T_45[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_48 = _masked_entry_T_45[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_49 = _masked_entry_T_45[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_50 = _masked_entry_T_45[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_51 = _masked_entry_T_45[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_52 = _masked_entry_T_45[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_53 = _masked_entry_T_45[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_54 = {2'h3, ~_masked_entry_T_52}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_55 = _masked_entry_T_51 ? 3'h5 : _masked_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_56 = _masked_entry_T_50 ? 3'h4 : _masked_entry_T_55; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_57 = _masked_entry_T_49 ? 3'h3 : _masked_entry_T_56; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_58 = _masked_entry_T_48 ? 3'h2 : _masked_entry_T_57; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_59 = _masked_entry_T_47 ? 3'h1 : _masked_entry_T_58; // @[OneHot.scala:48:45] wire [2:0] masked_entry_3 = _masked_entry_T_46 ? 3'h0 : _masked_entry_T_59; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_6 = allocatable_slots_3 >> masked_entry_3; // @[Mux.scala:50:70] wire _alloc_entry_T_7 = _alloc_entry_T_6[0]; // @[tage.scala:289:44] assign alloc_entry_3 = _alloc_entry_T_7 ? masked_entry_3 : first_entry_3; // @[Mux.scala:50:70] assign f3_meta_allocate_3_bits = alloc_entry_3; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_3_valid_T = \|allocatable_slots_3; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_3_valid = _f3_meta_allocate_3_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_6 = &s1_update_bits_cfi_idx_bits; // @[tage.scala:297:58] wire _update_was_taken_T_7 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_6; // @[tage.scala:296:58, :297:58] wire update_was_taken_3 = _update_was_taken_T_7 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_137 = s1_update_bits_br_mask[3] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_35 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_36 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_37 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_38 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_39 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_40 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_33 = s1_update_mispredict_mask[3]; // @[tage.scala:237:73, :308:52] wire _new_u_T_34 = ~s1_update_meta_alt_differs_3; // @[tage.scala:217:9, :236:52] wire _new_u_T_35 = s1_update_meta_provider_u_3 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_41 = {1'h0, s1_update_meta_provider_u_3}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_36 = _GEN_41 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_37 = _new_u_T_36[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_38 = _new_u_T_35 ? 2'h0 : _new_u_T_37; // @[tage.scala:218:{24,27,43}] wire _new_u_T_39 = &s1_update_meta_provider_u_3; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_40 = _GEN_41 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_41 = _new_u_T_40[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_42 = _new_u_T_39 ? 2'h3 : _new_u_T_41; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_43 = _new_u_T_33 ? _new_u_T_38 : _new_u_T_42; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_3 = _new_u_T_34 ? s1_update_meta_provider_u_3 : _new_u_T_43; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire _T_144 = s1_update_valid & _GEN_7 == 5'h0 & s1_update_bits_cfi_mispredicted & s1_update_bits_cfi_idx_valid; // @[OneHot.scala:58:35] wire [3:0] _GEN_42 = {{s1_update_meta_allocate_3_valid}, {s1_update_meta_allocate_2_valid}, {s1_update_meta_allocate_1_valid}, {s1_update_meta_allocate_0_valid}}; // @[tage.scala:236:52, :320:27] wire _GEN_43 = _GEN_42[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire [3:0][2:0] _GEN_44 = {{s1_update_meta_allocate_3_bits}, {s1_update_meta_allocate_2_bits}, {s1_update_meta_allocate_1_bits}, {s1_update_meta_allocate_0_bits}}; // @[tage.scala:236:52, :320:27] wire [2:0] _GEN_45 = _GEN_44[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire _GEN_46 = _GEN_45 == 3'h0; // @[tage.scala:320:27, :321:43] wire _GEN_47 = _T_144 & _GEN_43 & _GEN_46; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_0_0 = _GEN_47 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_0 = s1_update_alloc_0_0 \| _GEN_8; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_1 = _GEN_47 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_1 = s1_update_alloc_0_1 \| _GEN_17; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_2 = _GEN_47 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_2 = s1_update_alloc_0_2 \| _GEN_26; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_3 = _GEN_47 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_3 = s1_update_alloc_0_3 \| _GEN_35; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_48 = _GEN_45 == 3'h1; // @[tage.scala:218:43, :320:27, :321:43] wire _GEN_49 = _T_144 & _GEN_43 & _GEN_48; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_1_0 = _GEN_49 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_0 = s1_update_alloc_1_0 \| _GEN_9; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_1 = _GEN_49 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_1 = s1_update_alloc_1_1 \| _GEN_18; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_2 = _GEN_49 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_2 = s1_update_alloc_1_2 \| _GEN_27; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_3 = _GEN_49 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_3 = s1_update_alloc_1_3 \| _GEN_36; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_50 = _GEN_45 == 3'h2; // @[tage.scala:320:27, :321:43] wire _GEN_51 = _T_144 & _GEN_43 & _GEN_50; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_2_0 = _GEN_51 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_0 = s1_update_alloc_2_0 \| _GEN_10; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_1 = _GEN_51 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_1 = s1_update_alloc_2_1 \| _GEN_19; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_2 = _GEN_51 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_2 = s1_update_alloc_2_2 \| _GEN_28; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_3 = _GEN_51 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_3 = s1_update_alloc_2_3 \| _GEN_37; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_52 = _GEN_45 == 3'h3; // @[tage.scala:265:40, :320:27, :321:43] wire _GEN_53 = _T_144 & _GEN_43 & _GEN_52; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_3_0 = _GEN_53 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_0 = s1_update_alloc_3_0 \| _GEN_11; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_1 = _GEN_53 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_1 = s1_update_alloc_3_1 \| _GEN_20; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_2 = _GEN_53 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_2 = s1_update_alloc_3_2 \| _GEN_29; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_3 = _GEN_53 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_3 = s1_update_alloc_3_3 \| _GEN_38; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_54 = _GEN_45 == 3'h4; // @[tage.scala:320:27, :321:43] wire _GEN_55 = _T_144 & _GEN_43 & _GEN_54; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_4_0 = _GEN_55 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_0 = s1_update_alloc_4_0 \| _GEN_12; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_1 = _GEN_55 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_1 = s1_update_alloc_4_1 \| _GEN_21; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_2 = _GEN_55 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_2 = s1_update_alloc_4_2 \| _GEN_30; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_3 = _GEN_55 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_3 = s1_update_alloc_4_3 \| _GEN_39; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_56 = _GEN_45 == 3'h5; // @[tage.scala:320:27, :321:43] wire _GEN_57 = _T_144 & _GEN_43 & _GEN_56; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_5_0 = _GEN_57 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_0 = s1_update_alloc_5_0 \| _GEN_13; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_1 = _GEN_57 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_1 = s1_update_alloc_5_1 \| _GEN_22; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_2 = _GEN_57 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_2 = s1_update_alloc_5_2 \| _GEN_31; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_3 = _GEN_57 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_3 = s1_update_alloc_5_3 \| _GEN_40; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_58 = _GEN_46 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_0 = _T_144 & _GEN_43 & _GEN_58 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_59 = _GEN_46 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_1 = _T_144 & _GEN_43 & _GEN_59 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_60 = _GEN_46 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_2 = _T_144 & _GEN_43 & _GEN_60 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_61 = _GEN_46 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_3 = _T_144 & _GEN_43 & _GEN_61 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_62 = _GEN_48 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_0 = _T_144 & _GEN_43 & _GEN_62 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_63 = _GEN_48 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_1 = _T_144 & _GEN_43 & _GEN_63 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_64 = _GEN_48 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_2 = _T_144 & _GEN_43 & _GEN_64 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_65 = _GEN_48 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_3 = _T_144 & _GEN_43 & _GEN_65 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_66 = _GEN_50 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_0 = _T_144 & _GEN_43 & _GEN_66 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_67 = _GEN_50 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_1 = _T_144 & _GEN_43 & _GEN_67 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_68 = _GEN_50 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_2 = _T_144 & _GEN_43 & _GEN_68 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_69 = _GEN_50 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_3 = _T_144 & _GEN_43 & _GEN_69 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_70 = _GEN_52 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_0 = _T_144 & _GEN_43 & _GEN_70 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_71 = _GEN_52 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_1 = _T_144 & _GEN_43 & _GEN_71 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_72 = _GEN_52 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_2 = _T_144 & _GEN_43 & _GEN_72 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_73 = _GEN_52 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_3 = _T_144 & _GEN_43 & _GEN_73 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_74 = _GEN_54 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_0 = _T_144 & _GEN_43 & _GEN_74 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_75 = _GEN_54 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_1 = _T_144 & _GEN_43 & _GEN_75 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_76 = _GEN_54 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_2 = _T_144 & _GEN_43 & _GEN_76 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_77 = _GEN_54 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_3 = _T_144 & _GEN_43 & _GEN_77 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_78 = _GEN_56 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_0 = _T_144 & _GEN_43 & _GEN_78 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_79 = _GEN_56 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_1 = _T_144 & _GEN_43 & _GEN_79 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_80 = _GEN_56 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_2 = _T_144 & _GEN_43 & _GEN_80 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_81 = _GEN_56 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_3 = _T_144 & _GEN_43 & _GEN_81 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire [3:0] _GEN_82 = {{s1_update_meta_provider_3_valid}, {s1_update_meta_provider_2_valid}, {s1_update_meta_provider_1_valid}, {s1_update_meta_provider_0_valid}}; // @[OneHot.scala:58:35] wire [3:0][2:0] _GEN_83 = {{s1_update_meta_provider_3_bits}, {s1_update_meta_provider_2_bits}, {s1_update_meta_provider_1_bits}, {s1_update_meta_provider_0_bits}}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T = 8'h1 << _GEN_83[s1_update_bits_cfi_idx_bits]; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_1 = _decr_mask_T; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_2 = {1'h0, _decr_mask_T[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_3 = {2'h0, _decr_mask_T[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_4 = {3'h0, _decr_mask_T[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_5 = {4'h0, _decr_mask_T[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_6 = {5'h0, _decr_mask_T[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_7 = {6'h0, _decr_mask_T[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_8 = {7'h0, _decr_mask_T[7]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_9 = _decr_mask_T_1 \| _decr_mask_T_2; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_10 = _decr_mask_T_9 \| _decr_mask_T_3; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_11 = _decr_mask_T_10 \| _decr_mask_T_4; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_12 = _decr_mask_T_11 \| _decr_mask_T_5; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_13 = _decr_mask_T_12 \| _decr_mask_T_6; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_14 = _decr_mask_T_13 \| _decr_mask_T_7; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_15 = _decr_mask_T_14 \| _decr_mask_T_8; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_16 = ~_decr_mask_T_15; // @[util.scala:373:45] wire [7:0] decr_mask = _GEN_82[s1_update_bits_cfi_idx_bits] ? _decr_mask_T_16 : 8'h0; // @[OneHot.scala:58:35] assign s1_update_u_mask_0_0 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T \| _GEN_8 : decr_mask[0] & _update_was_taken_T \| _GEN_8) : _GEN_8; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_1 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_2 \| _GEN_17 : decr_mask[0] & _update_was_taken_T_2 \| _GEN_17) : _GEN_17; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_2 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_4 \| _GEN_26 : decr_mask[0] & _update_was_taken_T_4 \| _GEN_26) : _GEN_26; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_3 = _T_144 ? (_GEN_43 ? _GEN_46 & (&s1_update_bits_cfi_idx_bits) \| _GEN_35 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits) \| _GEN_35) : _GEN_35; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_0_0 = _T_144 & (_GEN_43 ? _GEN_58 : decr_mask[0] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_1 = _T_144 & (_GEN_43 ? _GEN_59 : decr_mask[0] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_2 = _T_144 & (_GEN_43 ? _GEN_60 : decr_mask[0] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_3 = _T_144 & (_GEN_43 ? _GEN_61 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_1_0 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T \| _GEN_9 : decr_mask[1] & _update_was_taken_T \| _GEN_9) : _GEN_9; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_1 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_2 \| _GEN_18 : decr_mask[1] & _update_was_taken_T_2 \| _GEN_18) : _GEN_18; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_2 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_4 \| _GEN_27 : decr_mask[1] & _update_was_taken_T_4 \| _GEN_27) : _GEN_27; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_3 = _T_144 ? (_GEN_43 ? _GEN_48 & (&s1_update_bits_cfi_idx_bits) \| _GEN_36 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits) \| _GEN_36) : _GEN_36; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_1_0 = _T_144 & (_GEN_43 ? _GEN_62 : decr_mask[1] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_1 = _T_144 & (_GEN_43 ? _GEN_63 : decr_mask[1] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_2 = _T_144 & (_GEN_43 ? _GEN_64 : decr_mask[1] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_3 = _T_144 & (_GEN_43 ? _GEN_65 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_2_0 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T \| _GEN_10 : decr_mask[2] & _update_was_taken_T \| _GEN_10) : _GEN_10; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_1 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_2 \| _GEN_19 : decr_mask[2] & _update_was_taken_T_2 \| _GEN_19) : _GEN_19; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_2 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_4 \| _GEN_28 : decr_mask[2] & _update_was_taken_T_4 \| _GEN_28) : _GEN_28; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_3 = _T_144 ? (_GEN_43 ? _GEN_50 & (&s1_update_bits_cfi_idx_bits) \| _GEN_37 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits) \| _GEN_37) : _GEN_37; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_2_0 = _T_144 & (_GEN_43 ? _GEN_66 : decr_mask[2] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_1 = _T_144 & (_GEN_43 ? _GEN_67 : decr_mask[2] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_2 = _T_144 & (_GEN_43 ? _GEN_68 : decr_mask[2] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_3 = _T_144 & (_GEN_43 ? _GEN_69 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_3_0 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T \| _GEN_11 : decr_mask[3] & _update_was_taken_T \| _GEN_11) : _GEN_11; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_1 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_2 \| _GEN_20 : decr_mask[3] & _update_was_taken_T_2 \| _GEN_20) : _GEN_20; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_2 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_4 \| _GEN_29 : decr_mask[3] & _update_was_taken_T_4 \| _GEN_29) : _GEN_29; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_3 = _T_144 ? (_GEN_43 ? _GEN_52 & (&s1_update_bits_cfi_idx_bits) \| _GEN_38 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits) \| _GEN_38) : _GEN_38; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_3_0 = _T_144 & (_GEN_43 ? _GEN_70 : decr_mask[3] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_1 = _T_144 & (_GEN_43 ? _GEN_71 : decr_mask[3] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_2 = _T_144 & (_GEN_43 ? _GEN_72 : decr_mask[3] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_3 = _T_144 & (_GEN_43 ? _GEN_73 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_4_0 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T \| _GEN_12 : decr_mask[4] & _update_was_taken_T \| _GEN_12) : _GEN_12; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_1 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_2 \| _GEN_21 : decr_mask[4] & _update_was_taken_T_2 \| _GEN_21) : _GEN_21; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_2 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_4 \| _GEN_30 : decr_mask[4] & _update_was_taken_T_4 \| _GEN_30) : _GEN_30; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_3 = _T_144 ? (_GEN_43 ? _GEN_54 & (&s1_update_bits_cfi_idx_bits) \| _GEN_39 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits) \| _GEN_39) : _GEN_39; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_4_0 = _T_144 & (_GEN_43 ? _GEN_74 : decr_mask[4] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_1 = _T_144 & (_GEN_43 ? _GEN_75 : decr_mask[4] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_2 = _T_144 & (_GEN_43 ? _GEN_76 : decr_mask[4] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_3 = _T_144 & (_GEN_43 ? _GEN_77 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_5_0 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T \| _GEN_13 : decr_mask[5] & _update_was_taken_T \| _GEN_13) : _GEN_13; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_1 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_2 \| _GEN_22 : decr_mask[5] & _update_was_taken_T_2 \| _GEN_22) : _GEN_22; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_2 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_4 \| _GEN_31 : decr_mask[5] & _update_was_taken_T_4 \| _GEN_31) : _GEN_31; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_3 = _T_144 ? (_GEN_43 ? _GEN_56 & (&s1_update_bits_cfi_idx_bits) \| _GEN_40 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits) \| _GEN_40) : _GEN_40; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_5_0 = _T_144 & (_GEN_43 ? _GEN_78 : decr_mask[5] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_1 = _T_144 & (_GEN_43 ? _GEN_79 : decr_mask[5] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_2 = _T_144 & (_GEN_43 ? _GEN_80 : decr_mask[5] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_3 = _T_144 & (_GEN_43 ? _GEN_81 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] reg tt_0_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_0_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_0_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_1_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_1_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_1_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_2_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_2_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_2_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_3_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_3_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_3_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_4_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_4_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_4_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_5_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_5_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_5_1_io_update_hist_REG; // @[tage.scala:354:41] wire [7:0] io_f3_meta_lo = {_io_f3_meta_T_1, _io_f3_meta_T}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi = {_io_f3_meta_T_3, _io_f3_meta_T_2}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_4 = {io_f3_meta_hi, io_f3_meta_lo}; // @[tage.scala:359:25] wire [11:0] _io_f3_meta_T_5 = {io_f3_meta_hi_1, io_f3_meta_lo_1}; // @[tage.scala:359:25] wire [7:0] _io_f3_meta_T_6 = {io_f3_meta_hi_2, io_f3_meta_lo_2}; // @[tage.scala:359:25] wire [3:0] _io_f3_meta_T_7 = {io_f3_meta_hi_3, io_f3_meta_lo_3}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_lo_4 = {_io_f3_meta_T_9, _io_f3_meta_T_8}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi_4 = {_io_f3_meta_T_11, _io_f3_meta_T_10}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_12 = {io_f3_meta_hi_4, io_f3_meta_lo_4}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_lo_5 = {_io_f3_meta_T_5, _io_f3_meta_T_4}; // @[tage.scala:359:25] wire [19:0] io_f3_meta_hi_hi = {_io_f3_meta_T_12, _io_f3_meta_T_7}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_hi_5 = {io_f3_meta_hi_hi, _io_f3_meta_T_6}; // @[tage.scala:359:25] wire [55:0] _io_f3_meta_T_13 = {io_f3_meta_hi_5, io_f3_meta_lo_5}; // @[tage.scala:359:25] assign io_f3_meta_0 = {64'h0, _io_f3_meta_T_13}; // @[tage.scala:198:7, :359:{14,25}] always @(posedge clock) begin // @[tage.scala:198:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[tage.scala:198:7] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[tage.scala:198:7] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[tage.scala:198:7] s1_update_valid <= io_update_valid_0; // @[tage.scala:198:7] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[tage.scala:198:7] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[tage.scala:198:7] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[tage.scala:198:7] s1_update_bits_pc <= io_update_bits_pc_0; // @[tage.scala:198:7] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[tage.scala:198:7] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[tage.scala:198:7] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[tage.scala:198:7] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[tage.scala:198:7] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[tage.scala:198:7] s1_update_bits_target <= io_update_bits_target_0; // @[tage.scala:198:7] s1_update_bits_meta <= io_update_bits_meta_0; // @[tage.scala:198:7] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[tage.scala:198:7] t_io_f1_req_valid_REG <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_1 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_1 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_2 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_2 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_3 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_3 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_4 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_4 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_5 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_5 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] tt_0_1_io_update_mask_0_REG <= s1_update_mask_0_0; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_0_REG <= s1_update_taken_0_0; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_0_REG <= s1_update_alloc_0_0; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_0_0; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_0_REG <= s1_update_u_mask_0_0; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_0_REG <= s1_update_u_0_0; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_1_REG <= s1_update_mask_0_1; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_1_REG <= s1_update_taken_0_1; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_1_REG <= s1_update_alloc_0_1; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_0_1; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_1_REG <= s1_update_u_mask_0_1; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_1_REG <= s1_update_u_0_1; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_2_REG <= s1_update_mask_0_2; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_2_REG <= s1_update_taken_0_2; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_2_REG <= s1_update_alloc_0_2; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_0_2; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_2_REG <= s1_update_u_mask_0_2; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_2_REG <= s1_update_u_0_2; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_3_REG <= s1_update_mask_0_3; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_3_REG <= s1_update_taken_0_3; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_3_REG <= s1_update_alloc_0_3; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_0_3; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_3_REG <= s1_update_u_mask_0_3; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_3_REG <= s1_update_u_0_3; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_0_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_1_1_io_update_mask_0_REG <= s1_update_mask_1_0; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_0_REG <= s1_update_taken_1_0; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_0_REG <= s1_update_alloc_1_0; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_1_0; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_0_REG <= s1_update_u_mask_1_0; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_0_REG <= s1_update_u_1_0; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_1_REG <= s1_update_mask_1_1; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_1_REG <= s1_update_taken_1_1; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_1_REG <= s1_update_alloc_1_1; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_1_1; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_1_REG <= s1_update_u_mask_1_1; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_1_REG <= s1_update_u_1_1; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_2_REG <= s1_update_mask_1_2; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_2_REG <= s1_update_taken_1_2; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_2_REG <= s1_update_alloc_1_2; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_1_2; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_2_REG <= s1_update_u_mask_1_2; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_2_REG <= s1_update_u_1_2; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_3_REG <= s1_update_mask_1_3; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_3_REG <= s1_update_taken_1_3; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_3_REG <= s1_update_alloc_1_3; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_1_3; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_3_REG <= s1_update_u_mask_1_3; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_3_REG <= s1_update_u_1_3; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_1_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_2_1_io_update_mask_0_REG <= s1_update_mask_2_0; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_0_REG <= s1_update_taken_2_0; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_0_REG <= s1_update_alloc_2_0; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_2_0; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_0_REG <= s1_update_u_mask_2_0; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_0_REG <= s1_update_u_2_0; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_1_REG <= s1_update_mask_2_1; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_1_REG <= s1_update_taken_2_1; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_1_REG <= s1_update_alloc_2_1; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_2_1; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_1_REG <= s1_update_u_mask_2_1; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_1_REG <= s1_update_u_2_1; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_2_REG <= s1_update_mask_2_2; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_2_REG <= s1_update_taken_2_2; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_2_REG <= s1_update_alloc_2_2; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_2_2; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_2_REG <= s1_update_u_mask_2_2; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_2_REG <= s1_update_u_2_2; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_3_REG <= s1_update_mask_2_3; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_3_REG <= s1_update_taken_2_3; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_3_REG <= s1_update_alloc_2_3; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_2_3; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_3_REG <= s1_update_u_mask_2_3; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_3_REG <= s1_update_u_2_3; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_2_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_3_1_io_update_mask_0_REG <= s1_update_mask_3_0; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_0_REG <= s1_update_taken_3_0; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_0_REG <= s1_update_alloc_3_0; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_3_0; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_0_REG <= s1_update_u_mask_3_0; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_0_REG <= s1_update_u_3_0; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_1_REG <= s1_update_mask_3_1; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_1_REG <= s1_update_taken_3_1; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_1_REG <= s1_update_alloc_3_1; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_3_1; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_1_REG <= s1_update_u_mask_3_1; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_1_REG <= s1_update_u_3_1; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_2_REG <= s1_update_mask_3_2; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_2_REG <= s1_update_taken_3_2; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_2_REG <= s1_update_alloc_3_2; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_3_2; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_2_REG <= s1_update_u_mask_3_2; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_2_REG <= s1_update_u_3_2; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_3_REG <= s1_update_mask_3_3; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_3_REG <= s1_update_taken_3_3; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_3_REG <= s1_update_alloc_3_3; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_3_3; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_3_REG <= s1_update_u_mask_3_3; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_3_REG <= s1_update_u_3_3; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_3_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_4_1_io_update_mask_0_REG <= s1_update_mask_4_0; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_0_REG <= s1_update_taken_4_0; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_0_REG <= s1_update_alloc_4_0; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_4_0; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_0_REG <= s1_update_u_mask_4_0; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_0_REG <= s1_update_u_4_0; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_1_REG <= s1_update_mask_4_1; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_1_REG <= s1_update_taken_4_1; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_1_REG <= s1_update_alloc_4_1; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_4_1; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_1_REG <= s1_update_u_mask_4_1; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_1_REG <= s1_update_u_4_1; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_2_REG <= s1_update_mask_4_2; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_2_REG <= s1_update_taken_4_2; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_2_REG <= s1_update_alloc_4_2; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_4_2; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_2_REG <= s1_update_u_mask_4_2; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_2_REG <= s1_update_u_4_2; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_3_REG <= s1_update_mask_4_3; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_3_REG <= s1_update_taken_4_3; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_3_REG <= s1_update_alloc_4_3; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_4_3; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_3_REG <= s1_update_u_mask_4_3; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_3_REG <= s1_update_u_4_3; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_4_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_5_1_io_update_mask_0_REG <= s1_update_mask_5_0; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_0_REG <= s1_update_taken_5_0; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_0_REG <= s1_update_alloc_5_0; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_5_0; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_0_REG <= s1_update_u_mask_5_0; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_0_REG <= s1_update_u_5_0; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_1_REG <= s1_update_mask_5_1; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_1_REG <= s1_update_taken_5_1; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_1_REG <= s1_update_alloc_5_1; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_5_1; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_1_REG <= s1_update_u_mask_5_1; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_1_REG <= s1_update_u_5_1; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_2_REG <= s1_update_mask_5_2; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_2_REG <= s1_update_taken_5_2; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_2_REG <= s1_update_alloc_5_2; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_5_2; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_2_REG <= s1_update_u_mask_5_2; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_2_REG <= s1_update_u_5_2; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_3_REG <= s1_update_mask_5_3; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_3_REG <= s1_update_taken_5_3; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_3_REG <= s1_update_alloc_5_3; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_5_3; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_3_REG <= s1_update_u_mask_5_3; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_3_REG <= s1_update_u_5_3; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_5_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] always @(posedge) TageTable_6 tt_0_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_0_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_0_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_0_0_bits_u), .io_f3_resp_1_valid (f3_resps_0_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_0_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_0_1_bits_u), .io_f3_resp_2_valid (f3_resps_0_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_0_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_0_2_bits_u), .io_f3_resp_3_valid (f3_resps_0_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_0_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_0_3_bits_u), .io_update_mask_0 (tt_0_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_0_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_0_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_0_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_0_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_0_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_0_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_0_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_0_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_0_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_0_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_0_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_0_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_0_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_0_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_0_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_0_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_0_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_0_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_0_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_0_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_0_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_0_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_0_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_0_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_0_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_7 tt_1_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_1), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_1), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_1_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_1_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_1_0_bits_u), .io_f3_resp_1_valid (f3_resps_1_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_1_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_1_1_bits_u), .io_f3_resp_2_valid (f3_resps_1_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_1_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_1_2_bits_u), .io_f3_resp_3_valid (f3_resps_1_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_1_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_1_3_bits_u), .io_update_mask_0 (tt_1_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_1_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_1_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_1_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_1_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_1_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_1_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_1_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_1_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_1_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_1_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_1_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_1_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_1_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_1_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_1_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_1_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_1_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_1_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_1_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_1_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_1_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_1_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_1_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_1_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_1_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_8 tt_2_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_2), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_2), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_2_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_2_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_2_0_bits_u), .io_f3_resp_1_valid (f3_resps_2_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_2_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_2_1_bits_u), .io_f3_resp_2_valid (f3_resps_2_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_2_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_2_2_bits_u), .io_f3_resp_3_valid (f3_resps_2_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_2_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_2_3_bits_u), .io_update_mask_0 (tt_2_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_2_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_2_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_2_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_2_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_2_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_2_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_2_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_2_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_2_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_2_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_2_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_2_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_2_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_2_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_2_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_2_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_2_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_2_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_2_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_2_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_2_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_2_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_2_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_2_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_2_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_9 tt_3_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_3), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_3), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_3_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_3_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_3_0_bits_u), .io_f3_resp_1_valid (f3_resps_3_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_3_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_3_1_bits_u), .io_f3_resp_2_valid (f3_resps_3_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_3_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_3_2_bits_u), .io_f3_resp_3_valid (f3_resps_3_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_3_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_3_3_bits_u), .io_update_mask_0 (tt_3_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_3_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_3_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_3_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_3_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_3_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_3_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_3_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_3_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_3_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_3_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_3_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_3_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_3_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_3_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_3_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_3_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_3_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_3_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_3_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_3_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_3_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_3_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_3_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_3_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_3_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_10 tt_4_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_4), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_4), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_4_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_4_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_4_0_bits_u), .io_f3_resp_1_valid (f3_resps_4_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_4_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_4_1_bits_u), .io_f3_resp_2_valid (f3_resps_4_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_4_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_4_2_bits_u), .io_f3_resp_3_valid (f3_resps_4_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_4_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_4_3_bits_u), .io_update_mask_0 (tt_4_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_4_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_4_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_4_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_4_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_4_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_4_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_4_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_4_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_4_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_4_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_4_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_4_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_4_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_4_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_4_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_4_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_4_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_4_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_4_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_4_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_4_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_4_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_4_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_4_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_4_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_11 tt_5_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_5), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_5), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_5_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_5_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_5_0_bits_u), .io_f3_resp_1_valid (f3_resps_5_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_5_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_5_1_bits_u), .io_f3_resp_2_valid (f3_resps_5_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_5_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_5_2_bits_u), .io_f3_resp_3_valid (f3_resps_5_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_5_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_5_3_bits_u), .io_update_mask_0 (tt_5_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_5_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_5_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_5_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_5_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_5_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_5_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_5_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_5_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_5_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_5_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_5_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_5_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_5_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_5_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_5_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_5_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_5_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_5_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_5_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_5_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_5_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_5_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_5_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_5_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_5_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] MaxPeriodFibonacciLFSR_9 alloc_lfsr_prng ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_io_out_0), .io_out_1 (_alloc_lfsr_prng_io_out_1), .io_out_2 (_alloc_lfsr_prng_io_out_2), .io_out_3 (_alloc_lfsr_prng_io_out_3), .io_out_4 (_alloc_lfsr_prng_io_out_4), .io_out_5 (_alloc_lfsr_prng_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_10 alloc_lfsr_prng_1 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_1_io_out_0), .io_out_1 (_alloc_lfsr_prng_1_io_out_1), .io_out_2 (_alloc_lfsr_prng_1_io_out_2), .io_out_3 (_alloc_lfsr_prng_1_io_out_3), .io_out_4 (_alloc_lfsr_prng_1_io_out_4), .io_out_5 (_alloc_lfsr_prng_1_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_11 alloc_lfsr_prng_2 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_2_io_out_0), .io_out_1 (_alloc_lfsr_prng_2_io_out_1), .io_out_2 (_alloc_lfsr_prng_2_io_out_2), .io_out_3 (_alloc_lfsr_prng_2_io_out_3), .io_out_4 (_alloc_lfsr_prng_2_io_out_4), .io_out_5 (_alloc_lfsr_prng_2_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_12 alloc_lfsr_prng_3 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_3_io_out_0), .io_out_1 (_alloc_lfsr_prng_3_io_out_1), .io_out_2 (_alloc_lfsr_prng_3_io_out_2), .io_out_3 (_alloc_lfsr_prng_3_io_out_3), .io_out_4 (_alloc_lfsr_prng_3_io_out_4), .io_out_5 (_alloc_lfsr_prng_3_io_out_5) ); // @[PRNG.scala:91:22] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_f3_meta = io_f3_meta_0; // @[tage.scala:198:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_26 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_26( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_12 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_12( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_104 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_104( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_128 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_128( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_5 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_5( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 connect _source_ok_WIRE[10], _source_ok_T_45 node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _T_127 = and(_T_11, _T_24) node _T_128 = and(_T_127, _T_37) node _T_129 = and(_T_128, _T_50) node _T_130 = and(_T_129, _T_63) node _T_131 = and(_T_130, _T_76) node _T_132 = and(_T_131, _T_89) node _T_133 = and(_T_132, _T_102) node _T_134 = and(_T_133, _T_110) node _T_135 = and(_T_134, _T_118) node _T_136 = and(_T_135, _T_126) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_136, UInt<1>(0h1), "") : assert_1 node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_140 : node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_7) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<1>(0h1)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_8) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h2)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_9) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<2>(0h3)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_10) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_169 = shr(io.in.a.bits.source, 3) node _T_170 = eq(_T_169, UInt<2>(0h3)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_11) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_175 = shr(io.in.a.bits.source, 3) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_12) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_181 = shr(io.in.a.bits.source, 3) node _T_182 = eq(_T_181, UInt<4>(0h8)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_190 = or(_T_144, _T_150) node _T_191 = or(_T_190, _T_156) node _T_192 = or(_T_191, _T_162) node _T_193 = or(_T_192, _T_168) node _T_194 = or(_T_193, _T_174) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_186) node _T_197 = or(_T_196, _T_187) node _T_198 = or(_T_197, _T_188) node _T_199 = or(_T_198, _T_189) node _T_200 = and(_T_143, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = and(_T_202, _T_207) node _T_209 = or(UInt<1>(0h0), _T_208) node _T_210 = and(_T_201, _T_209) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_210, UInt<1>(0h1), "") : assert_2 node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_14) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<1>(0h1)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_15) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_227 = shr(io.in.a.bits.source, 2) node _T_228 = eq(_T_227, UInt<2>(0h2)) node _T_229 = leq(UInt<1>(0h0), uncommonBits_16) node _T_230 = and(_T_228, _T_229) node _T_231 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<2>(0h3)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_239 = shr(io.in.a.bits.source, 3) node _T_240 = eq(_T_239, UInt<2>(0h3)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_18) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_245 = shr(io.in.a.bits.source, 3) node _T_246 = eq(_T_245, UInt<2>(0h2)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_19) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_251 = shr(io.in.a.bits.source, 3) node _T_252 = eq(_T_251, UInt<4>(0h8)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_20) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_256 = and(_T_254, _T_255) node _T_257 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_258 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_259 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_214 connect _WIRE[1], _T_220 connect _WIRE[2], _T_226 connect _WIRE[3], _T_232 connect _WIRE[4], _T_238 connect _WIRE[5], _T_244 connect _WIRE[6], _T_250 connect _WIRE[7], _T_256 connect _WIRE[8], _T_257 connect _WIRE[9], _T_258 connect _WIRE[10], _T_259 node _T_260 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_261 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_262 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_265 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_266 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_267 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = mux(_WIRE[7], _T_260, UInt<1>(0h0)) node _T_269 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = or(_T_261, _T_262) node _T_273 = or(_T_272, _T_263) node _T_274 = or(_T_273, _T_264) node _T_275 = or(_T_274, _T_265) node _T_276 = or(_T_275, _T_266) node _T_277 = or(_T_276, _T_267) node _T_278 = or(_T_277, _T_268) node _T_279 = or(_T_278, _T_269) node _T_280 = or(_T_279, _T_270) node _T_281 = or(_T_280, _T_271) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_281 node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_284 = and(_T_282, _T_283) node _T_285 = or(UInt<1>(0h0), _T_284) node _T_286 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_WIRE_1, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_293, UInt<1>(0h1), "") : assert_3 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(source_ok, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_300 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_301 = asUInt(reset) node _T_302 = eq(_T_301, UInt<1>(0h0)) when _T_302 : node _T_303 = eq(_T_300, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_300, UInt<1>(0h1), "") : assert_5 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(is_aligned, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_307 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_307, UInt<1>(0h1), "") : assert_7 node _T_311 = not(io.in.a.bits.mask) node _T_312 = eq(_T_311, UInt<1>(0h0)) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_312, UInt<1>(0h1), "") : assert_8 node _T_316 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_316, UInt<1>(0h1), "") : assert_9 node _T_320 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_320 : node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_323 = and(_T_321, _T_322) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_21) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<1>(0h1)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_22) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<2>(0h2)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_23) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<2>(0h3)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_24) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_349 = shr(io.in.a.bits.source, 3) node _T_350 = eq(_T_349, UInt<2>(0h3)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_25) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_355 = shr(io.in.a.bits.source, 3) node _T_356 = eq(_T_355, UInt<2>(0h2)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_26) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_361 = shr(io.in.a.bits.source, 3) node _T_362 = eq(_T_361, UInt<4>(0h8)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_27) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_368 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_369 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_370 = or(_T_324, _T_330) node _T_371 = or(_T_370, _T_336) node _T_372 = or(_T_371, _T_342) node _T_373 = or(_T_372, _T_348) node _T_374 = or(_T_373, _T_354) node _T_375 = or(_T_374, _T_360) node _T_376 = or(_T_375, _T_366) node _T_377 = or(_T_376, _T_367) node _T_378 = or(_T_377, _T_368) node _T_379 = or(_T_378, _T_369) node _T_380 = and(_T_323, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<13>(0h1000))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = and(_T_382, _T_387) node _T_389 = or(UInt<1>(0h0), _T_388) node _T_390 = and(_T_381, _T_389) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_390, UInt<1>(0h1), "") : assert_10 node _T_394 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_395 = shr(io.in.a.bits.source, 2) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = leq(UInt<1>(0h0), uncommonBits_28) node _T_398 = and(_T_396, _T_397) node _T_399 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_400 = and(_T_398, _T_399) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_401 = shr(io.in.a.bits.source, 2) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_29) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<2>(0h2)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_30) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<2>(0h3)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_31) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_419 = shr(io.in.a.bits.source, 3) node _T_420 = eq(_T_419, UInt<2>(0h3)) node _T_421 = leq(UInt<1>(0h0), uncommonBits_32) node _T_422 = and(_T_420, _T_421) node _T_423 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_424 = and(_T_422, _T_423) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_425 = shr(io.in.a.bits.source, 3) node _T_426 = eq(_T_425, UInt<2>(0h2)) node _T_427 = leq(UInt<1>(0h0), uncommonBits_33) node _T_428 = and(_T_426, _T_427) node _T_429 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_430 = and(_T_428, _T_429) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_431 = shr(io.in.a.bits.source, 3) node _T_432 = eq(_T_431, UInt<4>(0h8)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_34) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_436 = and(_T_434, _T_435) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_439 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_394 connect _WIRE_2[1], _T_400 connect _WIRE_2[2], _T_406 connect _WIRE_2[3], _T_412 connect _WIRE_2[4], _T_418 connect _WIRE_2[5], _T_424 connect _WIRE_2[6], _T_430 connect _WIRE_2[7], _T_436 connect _WIRE_2[8], _T_437 connect _WIRE_2[9], _T_438 connect _WIRE_2[10], _T_439 node _T_440 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_441 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_442 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_443 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_444 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_445 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_446 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_447 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = mux(_WIRE_2[7], _T_440, UInt<1>(0h0)) node _T_449 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_450 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = or(_T_441, _T_442) node _T_453 = or(_T_452, _T_443) node _T_454 = or(_T_453, _T_444) node _T_455 = or(_T_454, _T_445) node _T_456 = or(_T_455, _T_446) node _T_457 = or(_T_456, _T_447) node _T_458 = or(_T_457, _T_448) node _T_459 = or(_T_458, _T_449) node _T_460 = or(_T_459, _T_450) node _T_461 = or(_T_460, _T_451) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_461 node _T_462 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_463 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_464 = and(_T_462, _T_463) node _T_465 = or(UInt<1>(0h0), _T_464) node _T_466 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<13>(0h1000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = and(_T_465, _T_470) node _T_472 = or(UInt<1>(0h0), _T_471) node _T_473 = and(_WIRE_3, _T_472) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_473, UInt<1>(0h1), "") : assert_11 node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(source_ok, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_480 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_480, UInt<1>(0h1), "") : assert_13 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_487 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_487, UInt<1>(0h1), "") : assert_15 node _T_491 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_491, UInt<1>(0h1), "") : assert_16 node _T_495 = not(io.in.a.bits.mask) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_496, UInt<1>(0h1), "") : assert_17 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_500, UInt<1>(0h1), "") : assert_18 node _T_504 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_509 = shr(io.in.a.bits.source, 2) node _T_510 = eq(_T_509, UInt<1>(0h0)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_35) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h1)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_36) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<2>(0h2)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_37) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h3)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_38) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_533 = shr(io.in.a.bits.source, 3) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_39) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<2>(0h2)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_40) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_545 = shr(io.in.a.bits.source, 3) node _T_546 = eq(_T_545, UInt<4>(0h8)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_41) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_550 = and(_T_548, _T_549) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_553 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_554 = or(_T_508, _T_514) node _T_555 = or(_T_554, _T_520) node _T_556 = or(_T_555, _T_526) node _T_557 = or(_T_556, _T_532) node _T_558 = or(_T_557, _T_538) node _T_559 = or(_T_558, _T_544) node _T_560 = or(_T_559, _T_550) node _T_561 = or(_T_560, _T_551) node _T_562 = or(_T_561, _T_552) node _T_563 = or(_T_562, _T_553) node _T_564 = and(_T_507, _T_563) node _T_565 = or(UInt<1>(0h0), _T_564) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_565, UInt<1>(0h1), "") : assert_19 node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = and(_T_572, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_579, UInt<1>(0h1), "") : assert_20 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(is_aligned, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_589 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_589, UInt<1>(0h1), "") : assert_23 node _T_593 = eq(io.in.a.bits.mask, mask) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_593, UInt<1>(0h1), "") : assert_24 node _T_597 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_597, UInt<1>(0h1), "") : assert_25 node _T_601 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_601 : node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_604 = and(_T_602, _T_603) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_606 = shr(io.in.a.bits.source, 2) node _T_607 = eq(_T_606, UInt<1>(0h0)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_42) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_612 = shr(io.in.a.bits.source, 2) node _T_613 = eq(_T_612, UInt<1>(0h1)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_43) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_618 = shr(io.in.a.bits.source, 2) node _T_619 = eq(_T_618, UInt<2>(0h2)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_44) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_624 = shr(io.in.a.bits.source, 2) node _T_625 = eq(_T_624, UInt<2>(0h3)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_45) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_630 = shr(io.in.a.bits.source, 3) node _T_631 = eq(_T_630, UInt<2>(0h3)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_46) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_636 = shr(io.in.a.bits.source, 3) node _T_637 = eq(_T_636, UInt<2>(0h2)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_47) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_641 = and(_T_639, _T_640) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_642 = shr(io.in.a.bits.source, 3) node _T_643 = eq(_T_642, UInt<4>(0h8)) node _T_644 = leq(UInt<1>(0h0), uncommonBits_48) node _T_645 = and(_T_643, _T_644) node _T_646 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_647 = and(_T_645, _T_646) node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_650 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_651 = or(_T_605, _T_611) node _T_652 = or(_T_651, _T_617) node _T_653 = or(_T_652, _T_623) node _T_654 = or(_T_653, _T_629) node _T_655 = or(_T_654, _T_635) node _T_656 = or(_T_655, _T_641) node _T_657 = or(_T_656, _T_647) node _T_658 = or(_T_657, _T_648) node _T_659 = or(_T_658, _T_649) node _T_660 = or(_T_659, _T_650) node _T_661 = and(_T_604, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_664 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<13>(0h1000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = and(_T_662, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_674, UInt<1>(0h1), "") : assert_26 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(source_ok, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_684, UInt<1>(0h1), "") : assert_29 node _T_688 = eq(io.in.a.bits.mask, mask) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_688, UInt<1>(0h1), "") : assert_30 node _T_692 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_49) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_50) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_51) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_52) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_721 = shr(io.in.a.bits.source, 3) node _T_722 = eq(_T_721, UInt<2>(0h3)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_53) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_727 = shr(io.in.a.bits.source, 3) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_54) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_733 = shr(io.in.a.bits.source, 3) node _T_734 = eq(_T_733, UInt<4>(0h8)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_55) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_740 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_741 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_742 = or(_T_696, _T_702) node _T_743 = or(_T_742, _T_708) node _T_744 = or(_T_743, _T_714) node _T_745 = or(_T_744, _T_720) node _T_746 = or(_T_745, _T_726) node _T_747 = or(_T_746, _T_732) node _T_748 = or(_T_747, _T_738) node _T_749 = or(_T_748, _T_739) node _T_750 = or(_T_749, _T_740) node _T_751 = or(_T_750, _T_741) node _T_752 = and(_T_695, _T_751) node _T_753 = or(UInt<1>(0h0), _T_752) node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_756 = and(_T_754, _T_755) node _T_757 = or(UInt<1>(0h0), _T_756) node _T_758 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = and(_T_757, _T_762) node _T_764 = or(UInt<1>(0h0), _T_763) node _T_765 = and(_T_753, _T_764) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_765, UInt<1>(0h1), "") : assert_31 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(source_ok, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_775 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_775, UInt<1>(0h1), "") : assert_34 node _T_779 = not(mask) node _T_780 = and(io.in.a.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_781, UInt<1>(0h1), "") : assert_35 node _T_785 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<1>(0h0)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_56) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_796 = shr(io.in.a.bits.source, 2) node _T_797 = eq(_T_796, UInt<1>(0h1)) node _T_798 = leq(UInt<1>(0h0), uncommonBits_57) node _T_799 = and(_T_797, _T_798) node _T_800 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<2>(0h2)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_58) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<2>(0h3)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_59) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_814 = shr(io.in.a.bits.source, 3) node _T_815 = eq(_T_814, UInt<2>(0h3)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_60) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_820 = shr(io.in.a.bits.source, 3) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_61) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_826 = shr(io.in.a.bits.source, 3) node _T_827 = eq(_T_826, UInt<4>(0h8)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_62) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_833 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_834 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_835 = or(_T_789, _T_795) node _T_836 = or(_T_835, _T_801) node _T_837 = or(_T_836, _T_807) node _T_838 = or(_T_837, _T_813) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_825) node _T_841 = or(_T_840, _T_831) node _T_842 = or(_T_841, _T_832) node _T_843 = or(_T_842, _T_833) node _T_844 = or(_T_843, _T_834) node _T_845 = and(_T_788, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_848 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = and(_T_847, _T_852) node _T_854 = or(UInt<1>(0h0), _T_853) node _T_855 = and(_T_846, _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_855, UInt<1>(0h1), "") : assert_36 node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(source_ok, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(is_aligned, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_865 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_865, UInt<1>(0h1), "") : assert_39 node _T_869 = eq(io.in.a.bits.mask, mask) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_869, UInt<1>(0h1), "") : assert_40 node _T_873 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_873 : node _T_874 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_875 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_876 = and(_T_874, _T_875) node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<1>(0h0)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_63) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_884 = shr(io.in.a.bits.source, 2) node _T_885 = eq(_T_884, UInt<1>(0h1)) node _T_886 = leq(UInt<1>(0h0), uncommonBits_64) node _T_887 = and(_T_885, _T_886) node _T_888 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_889 = and(_T_887, _T_888) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_890 = shr(io.in.a.bits.source, 2) node _T_891 = eq(_T_890, UInt<2>(0h2)) node _T_892 = leq(UInt<1>(0h0), uncommonBits_65) node _T_893 = and(_T_891, _T_892) node _T_894 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_895 = and(_T_893, _T_894) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_896 = shr(io.in.a.bits.source, 2) node _T_897 = eq(_T_896, UInt<2>(0h3)) node _T_898 = leq(UInt<1>(0h0), uncommonBits_66) node _T_899 = and(_T_897, _T_898) node _T_900 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_901 = and(_T_899, _T_900) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_902 = shr(io.in.a.bits.source, 3) node _T_903 = eq(_T_902, UInt<2>(0h3)) node _T_904 = leq(UInt<1>(0h0), uncommonBits_67) node _T_905 = and(_T_903, _T_904) node _T_906 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_907 = and(_T_905, _T_906) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_908 = shr(io.in.a.bits.source, 3) node _T_909 = eq(_T_908, UInt<2>(0h2)) node _T_910 = leq(UInt<1>(0h0), uncommonBits_68) node _T_911 = and(_T_909, _T_910) node _T_912 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_913 = and(_T_911, _T_912) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_914 = shr(io.in.a.bits.source, 3) node _T_915 = eq(_T_914, UInt<4>(0h8)) node _T_916 = leq(UInt<1>(0h0), uncommonBits_69) node _T_917 = and(_T_915, _T_916) node _T_918 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_919 = and(_T_917, _T_918) node _T_920 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_921 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_922 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_923 = or(_T_877, _T_883) node _T_924 = or(_T_923, _T_889) node _T_925 = or(_T_924, _T_895) node _T_926 = or(_T_925, _T_901) node _T_927 = or(_T_926, _T_907) node _T_928 = or(_T_927, _T_913) node _T_929 = or(_T_928, _T_919) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_921) node _T_932 = or(_T_931, _T_922) node _T_933 = and(_T_876, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_936 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<13>(0h1000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = and(_T_935, _T_940) node _T_942 = or(UInt<1>(0h0), _T_941) node _T_943 = and(_T_934, _T_942) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_943, UInt<1>(0h1), "") : assert_41 node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(source_ok, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(is_aligned, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_953 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_953, UInt<1>(0h1), "") : assert_44 node _T_957 = eq(io.in.a.bits.mask, mask) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_957, UInt<1>(0h1), "") : assert_45 node _T_961 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_961 : node _T_962 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_963 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_964 = and(_T_962, _T_963) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_966 = shr(io.in.a.bits.source, 2) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_70) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_971 = and(_T_969, _T_970) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_972 = shr(io.in.a.bits.source, 2) node _T_973 = eq(_T_972, UInt<1>(0h1)) node _T_974 = leq(UInt<1>(0h0), uncommonBits_71) node _T_975 = and(_T_973, _T_974) node _T_976 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_977 = and(_T_975, _T_976) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<2>(0h2)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_72) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<2>(0h3)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_73) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_990 = shr(io.in.a.bits.source, 3) node _T_991 = eq(_T_990, UInt<2>(0h3)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_74) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_996 = shr(io.in.a.bits.source, 3) node _T_997 = eq(_T_996, UInt<2>(0h2)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_75) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1002 = shr(io.in.a.bits.source, 3) node _T_1003 = eq(_T_1002, UInt<4>(0h8)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1009 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1010 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1011 = or(_T_965, _T_971) node _T_1012 = or(_T_1011, _T_977) node _T_1013 = or(_T_1012, _T_983) node _T_1014 = or(_T_1013, _T_989) node _T_1015 = or(_T_1014, _T_995) node _T_1016 = or(_T_1015, _T_1001) node _T_1017 = or(_T_1016, _T_1007) node _T_1018 = or(_T_1017, _T_1008) node _T_1019 = or(_T_1018, _T_1009) node _T_1020 = or(_T_1019, _T_1010) node _T_1021 = and(_T_964, _T_1020) node _T_1022 = or(UInt<1>(0h0), _T_1021) node _T_1023 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1024 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<13>(0h1000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = and(_T_1023, _T_1028) node _T_1030 = or(UInt<1>(0h0), _T_1029) node _T_1031 = and(_T_1022, _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_46 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(source_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(is_aligned, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1041 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_49 node _T_1045 = eq(io.in.a.bits.mask, mask) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_50 node _T_1049 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1053 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_52 node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 2) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_92 = shr(io.in.d.bits.source, 3) node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8)) node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_55 connect _source_ok_WIRE_1[1], _source_ok_T_61 connect _source_ok_WIRE_1[2], _source_ok_T_67 connect _source_ok_WIRE_1[3], _source_ok_T_73 connect _source_ok_WIRE_1[4], _source_ok_T_79 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_91 connect _source_ok_WIRE_1[7], _source_ok_T_97 connect _source_ok_WIRE_1[8], _source_ok_T_98 connect _source_ok_WIRE_1[9], _source_ok_T_99 connect _source_ok_WIRE_1[10], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1061 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_54 node _T_1065 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_55 node _T_1069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_56 node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_57 node _T_1077 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1077 : node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(source_ok_1, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(sink_ok, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1084 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_60 node _T_1088 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_61 node _T_1092 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_62 node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_63 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(UInt<1>(0h0), _T_1100) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_64 node _T_1105 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(source_ok_1, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(sink_ok, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1112 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_67 node _T_1116 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_68 node _T_1120 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_69 node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1125 = or(_T_1124, io.in.d.bits.corrupt) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_70 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = or(UInt<1>(0h0), _T_1129) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_71 node _T_1134 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1134 : node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(source_ok_1, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1138 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_73 node _T_1142 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_74 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h0), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_75 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_77 node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1160 = or(_T_1159, io.in.d.bits.corrupt) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_78 node _T_1164 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1165 = or(UInt<1>(0h0), _T_1164) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_79 node _T_1169 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1169 : node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(source_ok_1, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_81 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_82 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h0), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1186 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1190 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1194 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1198 = eq(a_first, UInt<1>(0h0)) node _T_1199 = and(io.in.a.valid, _T_1198) when _T_1199 : node _T_1200 = eq(io.in.a.bits.opcode, opcode) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_87 node _T_1204 = eq(io.in.a.bits.param, param) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_88 node _T_1208 = eq(io.in.a.bits.size, size) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_89 node _T_1212 = eq(io.in.a.bits.source, source) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_90 node _T_1216 = eq(io.in.a.bits.address, address) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_91 node _T_1220 = and(io.in.a.ready, io.in.a.valid) node _T_1221 = and(_T_1220, a_first) when _T_1221 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1222 = eq(d_first, UInt<1>(0h0)) node _T_1223 = and(io.in.d.valid, _T_1222) when _T_1223 : node _T_1224 = eq(io.in.d.bits.opcode, opcode_1) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.d.bits.param, param_1) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_93 node _T_1232 = eq(io.in.d.bits.size, size_1) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_94 node _T_1236 = eq(io.in.d.bits.source, source_1) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_95 node _T_1240 = eq(io.in.d.bits.sink, sink) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_96 node _T_1244 = eq(io.in.d.bits.denied, denied) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_97 node _T_1248 = and(io.in.d.ready, io.in.d.valid) node _T_1249 = and(_T_1248, d_first) when _T_1249 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1250 = and(io.in.a.valid, a_first_1) node _T_1251 = and(_T_1250, UInt<1>(0h1)) when _T_1251 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1252 = and(io.in.a.ready, io.in.a.valid) node _T_1253 = and(_T_1252, a_first_1) node _T_1254 = and(_T_1253, UInt<1>(0h1)) when _T_1254 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1255 = dshr(inflight, io.in.a.bits.source) node _T_1256 = bits(_T_1255, 0, 0) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(_T_1257, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1257, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1261 = and(io.in.d.valid, d_first_1) node _T_1262 = and(_T_1261, UInt<1>(0h1)) node _T_1263 = eq(d_release_ack, UInt<1>(0h0)) node _T_1264 = and(_T_1262, _T_1263) when _T_1264 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1265 = and(io.in.d.ready, io.in.d.valid) node _T_1266 = and(_T_1265, d_first_1) node _T_1267 = and(_T_1266, UInt<1>(0h1)) node _T_1268 = eq(d_release_ack, UInt<1>(0h0)) node _T_1269 = and(_T_1267, _T_1268) when _T_1269 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1270 = and(io.in.d.valid, d_first_1) node _T_1271 = and(_T_1270, UInt<1>(0h1)) node _T_1272 = eq(d_release_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1274 = dshr(inflight, io.in.d.bits.source) node _T_1275 = bits(_T_1274, 0, 0) node _T_1276 = or(_T_1275, same_cycle_resp) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1280 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1281 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1282 = or(_T_1280, _T_1281) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_100 node _T_1286 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_101 else : node _T_1290 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1291 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1292 = or(_T_1290, _T_1291) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_102 node _T_1296 = eq(io.in.d.bits.size, a_size_lookup) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_103 node _T_1300 = and(io.in.d.valid, d_first_1) node _T_1301 = and(_T_1300, a_first_1) node _T_1302 = and(_T_1301, io.in.a.valid) node _T_1303 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1304 = and(_T_1302, _T_1303) node _T_1305 = eq(d_release_ack, UInt<1>(0h0)) node _T_1306 = and(_T_1304, _T_1305) when _T_1306 : node _T_1307 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1308 = or(_T_1307, io.in.a.ready) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_1312 = orr(inflight) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) node _T_1314 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1315 = or(_T_1313, _T_1314) node _T_1316 = lt(watchdog, plusarg_reader.out) node _T_1317 = or(_T_1315, _T_1316) node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(_T_1317, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1317, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1321 = and(io.in.a.ready, io.in.a.valid) node _T_1322 = and(io.in.d.ready, io.in.d.valid) node _T_1323 = or(_T_1321, _T_1322) when _T_1323 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1324 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1325 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1326 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = and(_T_1324, _T_1327) when _T_1328 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1329 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1330 = and(_T_1329, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1331 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1332 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = and(_T_1330, _T_1333) when _T_1334 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1335 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1336 = bits(_T_1335, 0, 0) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1341 = and(io.in.d.valid, d_first_2) node _T_1342 = and(_T_1341, UInt<1>(0h1)) node _T_1343 = and(_T_1342, d_release_ack_1) when _T_1343 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1344 = and(io.in.d.ready, io.in.d.valid) node _T_1345 = and(_T_1344, d_first_2) node _T_1346 = and(_T_1345, UInt<1>(0h1)) node _T_1347 = and(_T_1346, d_release_ack_1) when _T_1347 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1348 = and(io.in.d.valid, d_first_2) node _T_1349 = and(_T_1348, UInt<1>(0h1)) node _T_1350 = and(_T_1349, d_release_ack_1) when _T_1350 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1351 = dshr(inflight_1, io.in.d.bits.source) node _T_1352 = bits(_T_1351, 0, 0) node _T_1353 = or(_T_1352, same_cycle_resp_1) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1357 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_108 else : node _T_1361 = eq(io.in.d.bits.size, c_size_lookup) node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(_T_1361, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1361, UInt<1>(0h1), "") : assert_109 node _T_1365 = and(io.in.d.valid, d_first_2) node _T_1366 = and(_T_1365, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1367 = and(_T_1366, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1368 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1369 = and(_T_1367, _T_1368) node _T_1370 = and(_T_1369, d_release_ack_1) node _T_1371 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1372 = and(_T_1370, _T_1371) when _T_1372 : node _T_1373 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1374 = or(_T_1373, _WIRE_27.ready) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_1378 = orr(inflight_1) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) node _T_1380 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1381 = or(_T_1379, _T_1380) node _T_1382 = lt(watchdog_1, plusarg_reader_1.out) node _T_1383 = or(_T_1381, _T_1382) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1387 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1388 = and(io.in.d.ready, io.in.d.valid) node _T_1389 = or(_T_1387, _T_1388) when _T_1389 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1321 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1321; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1321; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1389 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1389; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1389; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1389; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1254 = _T_1321 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1254 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1254 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1254 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1254 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1254 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1300 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1300 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1269 = _T_1389 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1269 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1269 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1269 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1365 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1365 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1347 = _T_1389 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1347 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1347 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1347 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SodorInternalTile : input clock : Clock input reset : Reset output io : { flip debug_port : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, master_port : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}[1], flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} inst core of Core connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector invalidate core.io.hartid invalidate core.io.interrupt.meip invalidate core.io.interrupt.msip invalidate core.io.interrupt.mtip invalidate core.io.interrupt.debug invalidate core.io.mem.resp.bits.data invalidate core.io.mem.resp.valid invalidate core.io.mem.req.bits.typ invalidate core.io.mem.req.bits.fcn invalidate core.io.mem.req.bits.data invalidate core.io.mem.req.bits.addr invalidate core.io.mem.req.valid invalidate core.io.mem.req.ready invalidate core.io.dcpath.halt invalidate core.io.ddpath.resetpc invalidate core.io.ddpath.rdata invalidate core.io.ddpath.validreq invalidate core.io.ddpath.wdata invalidate core.io.ddpath.addr inst memory of AsyncScratchPadMemory connect memory.clock, clock connect memory.reset, reset inst router of SodorRequestRouter connect router.clock, clock connect router.reset, reset connect router.io.corePort, core.io.mem connect memory.io.core_ports[0], router.io.scratchPort connect router.io.masterPort.resp, io.master_port[0].resp connect io.master_port[0].req.bits, router.io.masterPort.req.bits connect io.master_port[0].req.valid, router.io.masterPort.req.valid connect router.io.masterPort.req.ready, io.master_port[0].req.ready connect router.io.respAddress, core.io.mem.req.bits.addr connect memory.io.debug_port, io.debug_port connect core.io.interrupt, io.interrupt connect core.io.hartid, io.hartid connect core.io.reset_vector, io.reset_vector	module SodorInternalTile( // @[sodor_internal_tile.scala:117:7] input clock, // @[sodor_internal_tile.scala:117:7] input reset, // @[sodor_internal_tile.scala:117:7] input io_debug_port_req_valid, // @[sodor_internal_tile.scala:34:14] input [31:0] io_debug_port_req_bits_addr, // @[sodor_internal_tile.scala:34:14] input [31:0] io_debug_port_req_bits_data, // @[sodor_internal_tile.scala:34:14] input io_debug_port_req_bits_fcn, // @[sodor_internal_tile.scala:34:14] input [2:0] io_debug_port_req_bits_typ, // @[sodor_internal_tile.scala:34:14] output io_debug_port_resp_valid, // @[sodor_internal_tile.scala:34:14] output [31:0] io_debug_port_resp_bits_data, // @[sodor_internal_tile.scala:34:14] input io_master_port_0_req_ready, // @[sodor_internal_tile.scala:34:14] output io_master_port_0_req_valid, // @[sodor_internal_tile.scala:34:14] output [31:0] io_master_port_0_req_bits_addr, // @[sodor_internal_tile.scala:34:14] output [31:0] io_master_port_0_req_bits_data, // @[sodor_internal_tile.scala:34:14] output io_master_port_0_req_bits_fcn, // @[sodor_internal_tile.scala:34:14] output [2:0] io_master_port_0_req_bits_typ, // @[sodor_internal_tile.scala:34:14] input io_master_port_0_resp_valid, // @[sodor_internal_tile.scala:34:14] input [31:0] io_master_port_0_resp_bits_data, // @[sodor_internal_tile.scala:34:14] input io_interrupt_debug, // @[sodor_internal_tile.scala:34:14] input io_interrupt_mtip, // @[sodor_internal_tile.scala:34:14] input io_interrupt_msip, // @[sodor_internal_tile.scala:34:14] input io_interrupt_meip, // @[sodor_internal_tile.scala:34:14] input io_hartid // @[sodor_internal_tile.scala:34:14] ); wire _router_io_scratchPort_req_valid; // @[sodor_internal_tile.scala:126:24] wire [31:0] _router_io_scratchPort_req_bits_addr; // @[sodor_internal_tile.scala:126:24] wire [31:0] _router_io_scratchPort_req_bits_data; // @[sodor_internal_tile.scala:126:24] wire _router_io_scratchPort_req_bits_fcn; // @[sodor_internal_tile.scala:126:24] wire [2:0] _router_io_scratchPort_req_bits_typ; // @[sodor_internal_tile.scala:126:24] wire _router_io_corePort_req_ready; // @[sodor_internal_tile.scala:126:24] wire _router_io_corePort_resp_valid; // @[sodor_internal_tile.scala:126:24] wire [31:0] _router_io_corePort_resp_bits_data; // @[sodor_internal_tile.scala:126:24] wire _memory_io_core_ports_0_resp_valid; // @[sodor_internal_tile.scala:122:22] wire [31:0] _memory_io_core_ports_0_resp_bits_data; // @[sodor_internal_tile.scala:122:22] wire _core_io_mem_req_valid; // @[sodor_internal_tile.scala:120:22] wire [31:0] _core_io_mem_req_bits_addr; // @[sodor_internal_tile.scala:120:22] wire [31:0] _core_io_mem_req_bits_data; // @[sodor_internal_tile.scala:120:22] wire _core_io_mem_req_bits_fcn; // @[sodor_internal_tile.scala:120:22] wire [2:0] _core_io_mem_req_bits_typ; // @[sodor_internal_tile.scala:120:22] wire io_debug_port_req_valid_0 = io_debug_port_req_valid; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_debug_port_req_bits_addr_0 = io_debug_port_req_bits_addr; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_debug_port_req_bits_data_0 = io_debug_port_req_bits_data; // @[sodor_internal_tile.scala:117:7] wire io_debug_port_req_bits_fcn_0 = io_debug_port_req_bits_fcn; // @[sodor_internal_tile.scala:117:7] wire [2:0] io_debug_port_req_bits_typ_0 = io_debug_port_req_bits_typ; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_req_ready_0 = io_master_port_0_req_ready; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_resp_valid_0 = io_master_port_0_resp_valid; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_master_port_0_resp_bits_data_0 = io_master_port_0_resp_bits_data; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[sodor_internal_tile.scala:117:7] wire io_hartid_0 = io_hartid; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_reset_vector = 32'h10000; // @[sodor_internal_tile.scala:34:14, :117:7, :120:22] wire io_debug_port_req_ready = 1'h1; // @[sodor_internal_tile.scala:34:14, :117:7, :122:22, :126:24] wire [31:0] io_debug_port_resp_bits_data_0; // @[sodor_internal_tile.scala:117:7] wire io_debug_port_resp_valid_0; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_master_port_0_req_bits_addr_0; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_master_port_0_req_bits_data_0; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_req_bits_fcn_0; // @[sodor_internal_tile.scala:117:7] wire [2:0] io_master_port_0_req_bits_typ_0; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_req_valid_0; // @[sodor_internal_tile.scala:117:7] Core core ( // @[sodor_internal_tile.scala:120:22] .clock (clock), .reset (reset), .io_mem_req_ready (_router_io_corePort_req_ready), // @[sodor_internal_tile.scala:126:24] .io_mem_req_valid (_core_io_mem_req_valid), .io_mem_req_bits_addr (_core_io_mem_req_bits_addr), .io_mem_req_bits_data (_core_io_mem_req_bits_data), .io_mem_req_bits_fcn (_core_io_mem_req_bits_fcn), .io_mem_req_bits_typ (_core_io_mem_req_bits_typ), .io_mem_resp_valid (_router_io_corePort_resp_valid), // @[sodor_internal_tile.scala:126:24] .io_mem_resp_bits_data (_router_io_corePort_resp_bits_data), // @[sodor_internal_tile.scala:126:24] .io_interrupt_debug (io_interrupt_debug_0), // @[sodor_internal_tile.scala:117:7] .io_interrupt_mtip (io_interrupt_mtip_0), // @[sodor_internal_tile.scala:117:7] .io_interrupt_msip (io_interrupt_msip_0), // @[sodor_internal_tile.scala:117:7] .io_interrupt_meip (io_interrupt_meip_0), // @[sodor_internal_tile.scala:117:7] .io_hartid (io_hartid_0) // @[sodor_internal_tile.scala:117:7] ); // @[sodor_internal_tile.scala:120:22] AsyncScratchPadMemory memory ( // @[sodor_internal_tile.scala:122:22] .clock (clock), .reset (reset), .io_core_ports_0_req_valid (_router_io_scratchPort_req_valid), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_addr (_router_io_scratchPort_req_bits_addr), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_data (_router_io_scratchPort_req_bits_data), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_fcn (_router_io_scratchPort_req_bits_fcn), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_typ (_router_io_scratchPort_req_bits_typ), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_resp_valid (_memory_io_core_ports_0_resp_valid), .io_core_ports_0_resp_bits_data (_memory_io_core_ports_0_resp_bits_data), .io_debug_port_req_valid (io_debug_port_req_valid_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_addr (io_debug_port_req_bits_addr_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_data (io_debug_port_req_bits_data_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_fcn (io_debug_port_req_bits_fcn_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_typ (io_debug_port_req_bits_typ_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_resp_valid (io_debug_port_resp_valid_0), .io_debug_port_resp_bits_data (io_debug_port_resp_bits_data_0) ); // @[sodor_internal_tile.scala:122:22] SodorRequestRouter router ( // @[sodor_internal_tile.scala:126:24] .clock (clock), .reset (reset), .io_masterPort_req_ready (io_master_port_0_req_ready_0), // @[sodor_internal_tile.scala:117:7] .io_masterPort_req_valid (io_master_port_0_req_valid_0), .io_masterPort_req_bits_addr (io_master_port_0_req_bits_addr_0), .io_masterPort_req_bits_data (io_master_port_0_req_bits_data_0), .io_masterPort_req_bits_fcn (io_master_port_0_req_bits_fcn_0), .io_masterPort_req_bits_typ (io_master_port_0_req_bits_typ_0), .io_masterPort_resp_valid (io_master_port_0_resp_valid_0), // @[sodor_internal_tile.scala:117:7] .io_masterPort_resp_bits_data (io_master_port_0_resp_bits_data_0), // @[sodor_internal_tile.scala:117:7] .io_scratchPort_req_valid (_router_io_scratchPort_req_valid), .io_scratchPort_req_bits_addr (_router_io_scratchPort_req_bits_addr), .io_scratchPort_req_bits_data (_router_io_scratchPort_req_bits_data), .io_scratchPort_req_bits_fcn (_router_io_scratchPort_req_bits_fcn), .io_scratchPort_req_bits_typ (_router_io_scratchPort_req_bits_typ), .io_scratchPort_resp_valid (_memory_io_core_ports_0_resp_valid), // @[sodor_internal_tile.scala:122:22] .io_scratchPort_resp_bits_data (_memory_io_core_ports_0_resp_bits_data), // @[sodor_internal_tile.scala:122:22] .io_corePort_req_ready (_router_io_corePort_req_ready), .io_corePort_req_valid (_core_io_mem_req_valid), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_addr (_core_io_mem_req_bits_addr), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_data (_core_io_mem_req_bits_data), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_fcn (_core_io_mem_req_bits_fcn), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_typ (_core_io_mem_req_bits_typ), // @[sodor_internal_tile.scala:120:22] .io_corePort_resp_valid (_router_io_corePort_resp_valid), .io_corePort_resp_bits_data (_router_io_corePort_resp_bits_data), .io_respAddress (_core_io_mem_req_bits_addr) // @[sodor_internal_tile.scala:120:22] ); // @[sodor_internal_tile.scala:126:24] assign io_debug_port_resp_valid = io_debug_port_resp_valid_0; // @[sodor_internal_tile.scala:117:7] assign io_debug_port_resp_bits_data = io_debug_port_resp_bits_data_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_valid = io_master_port_0_req_valid_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_addr = io_master_port_0_req_bits_addr_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_data = io_master_port_0_req_bits_data_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_fcn = io_master_port_0_req_bits_fcn_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_typ = io_master_port_0_req_bits_typ_0; // @[sodor_internal_tile.scala:117:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CaptureChain_JTAGIdcodeBundle : input clock : Clock input reset : Reset output io : { flip chainIn : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, chainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, capture : { flip bits : { version : UInt<4>, partNumber : UInt<16>, mfrId : UInt<11>, always1 : UInt<1>}, capture : UInt<1>}} connect io.chainOut.shift, io.chainIn.shift connect io.chainOut.capture, io.chainIn.capture connect io.chainOut.update, io.chainIn.update reg regs_0 : UInt<1>, clock reg regs_1 : UInt<1>, clock reg regs_2 : UInt<1>, clock reg regs_3 : UInt<1>, clock reg regs_4 : UInt<1>, clock reg regs_5 : UInt<1>, clock reg regs_6 : UInt<1>, clock reg regs_7 : UInt<1>, clock reg regs_8 : UInt<1>, clock reg regs_9 : UInt<1>, clock reg regs_10 : UInt<1>, clock reg regs_11 : UInt<1>, clock reg regs_12 : UInt<1>, clock reg regs_13 : UInt<1>, clock reg regs_14 : UInt<1>, clock reg regs_15 : UInt<1>, clock reg regs_16 : UInt<1>, clock reg regs_17 : UInt<1>, clock reg regs_18 : UInt<1>, clock reg regs_19 : UInt<1>, clock reg regs_20 : UInt<1>, clock reg regs_21 : UInt<1>, clock reg regs_22 : UInt<1>, clock reg regs_23 : UInt<1>, clock reg regs_24 : UInt<1>, clock reg regs_25 : UInt<1>, clock reg regs_26 : UInt<1>, clock reg regs_27 : UInt<1>, clock reg regs_28 : UInt<1>, clock reg regs_29 : UInt<1>, clock reg regs_30 : UInt<1>, clock reg regs_31 : UInt<1>, clock connect io.chainOut.data, regs_0 when io.chainIn.capture : node regs_0_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_0_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_0_T = cat(regs_0_hi, regs_0_lo) node _regs_0_T_1 = bits(_regs_0_T, 0, 0) connect regs_0, _regs_0_T_1 node regs_1_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_1_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_1_T = cat(regs_1_hi, regs_1_lo) node _regs_1_T_1 = bits(_regs_1_T, 1, 1) connect regs_1, _regs_1_T_1 node regs_2_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_2_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_2_T = cat(regs_2_hi, regs_2_lo) node _regs_2_T_1 = bits(_regs_2_T, 2, 2) connect regs_2, _regs_2_T_1 node regs_3_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_3_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_3_T = cat(regs_3_hi, regs_3_lo) node _regs_3_T_1 = bits(_regs_3_T, 3, 3) connect regs_3, _regs_3_T_1 node regs_4_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_4_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_4_T = cat(regs_4_hi, regs_4_lo) node _regs_4_T_1 = bits(_regs_4_T, 4, 4) connect regs_4, _regs_4_T_1 node regs_5_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_5_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_5_T = cat(regs_5_hi, regs_5_lo) node _regs_5_T_1 = bits(_regs_5_T, 5, 5) connect regs_5, _regs_5_T_1 node regs_6_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_6_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_6_T = cat(regs_6_hi, regs_6_lo) node _regs_6_T_1 = bits(_regs_6_T, 6, 6) connect regs_6, _regs_6_T_1 node regs_7_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_7_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_7_T = cat(regs_7_hi, regs_7_lo) node _regs_7_T_1 = bits(_regs_7_T, 7, 7) connect regs_7, _regs_7_T_1 node regs_8_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_8_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_8_T = cat(regs_8_hi, regs_8_lo) node _regs_8_T_1 = bits(_regs_8_T, 8, 8) connect regs_8, _regs_8_T_1 node regs_9_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_9_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_9_T = cat(regs_9_hi, regs_9_lo) node _regs_9_T_1 = bits(_regs_9_T, 9, 9) connect regs_9, _regs_9_T_1 node regs_10_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_10_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_10_T = cat(regs_10_hi, regs_10_lo) node _regs_10_T_1 = bits(_regs_10_T, 10, 10) connect regs_10, _regs_10_T_1 node regs_11_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_11_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_11_T = cat(regs_11_hi, regs_11_lo) node _regs_11_T_1 = bits(_regs_11_T, 11, 11) connect regs_11, _regs_11_T_1 node regs_12_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_12_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_12_T = cat(regs_12_hi, regs_12_lo) node _regs_12_T_1 = bits(_regs_12_T, 12, 12) connect regs_12, _regs_12_T_1 node regs_13_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_13_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_13_T = cat(regs_13_hi, regs_13_lo) node _regs_13_T_1 = bits(_regs_13_T, 13, 13) connect regs_13, _regs_13_T_1 node regs_14_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_14_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_14_T = cat(regs_14_hi, regs_14_lo) node _regs_14_T_1 = bits(_regs_14_T, 14, 14) connect regs_14, _regs_14_T_1 node regs_15_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_15_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_15_T = cat(regs_15_hi, regs_15_lo) node _regs_15_T_1 = bits(_regs_15_T, 15, 15) connect regs_15, _regs_15_T_1 node regs_16_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_16_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_16_T = cat(regs_16_hi, regs_16_lo) node _regs_16_T_1 = bits(_regs_16_T, 16, 16) connect regs_16, _regs_16_T_1 node regs_17_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_17_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_17_T = cat(regs_17_hi, regs_17_lo) node _regs_17_T_1 = bits(_regs_17_T, 17, 17) connect regs_17, _regs_17_T_1 node regs_18_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_18_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_18_T = cat(regs_18_hi, regs_18_lo) node _regs_18_T_1 = bits(_regs_18_T, 18, 18) connect regs_18, _regs_18_T_1 node regs_19_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_19_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_19_T = cat(regs_19_hi, regs_19_lo) node _regs_19_T_1 = bits(_regs_19_T, 19, 19) connect regs_19, _regs_19_T_1 node regs_20_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_20_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_20_T = cat(regs_20_hi, regs_20_lo) node _regs_20_T_1 = bits(_regs_20_T, 20, 20) connect regs_20, _regs_20_T_1 node regs_21_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_21_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_21_T = cat(regs_21_hi, regs_21_lo) node _regs_21_T_1 = bits(_regs_21_T, 21, 21) connect regs_21, _regs_21_T_1 node regs_22_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_22_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_22_T = cat(regs_22_hi, regs_22_lo) node _regs_22_T_1 = bits(_regs_22_T, 22, 22) connect regs_22, _regs_22_T_1 node regs_23_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_23_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_23_T = cat(regs_23_hi, regs_23_lo) node _regs_23_T_1 = bits(_regs_23_T, 23, 23) connect regs_23, _regs_23_T_1 node regs_24_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_24_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_24_T = cat(regs_24_hi, regs_24_lo) node _regs_24_T_1 = bits(_regs_24_T, 24, 24) connect regs_24, _regs_24_T_1 node regs_25_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_25_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_25_T = cat(regs_25_hi, regs_25_lo) node _regs_25_T_1 = bits(_regs_25_T, 25, 25) connect regs_25, _regs_25_T_1 node regs_26_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_26_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_26_T = cat(regs_26_hi, regs_26_lo) node _regs_26_T_1 = bits(_regs_26_T, 26, 26) connect regs_26, _regs_26_T_1 node regs_27_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_27_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_27_T = cat(regs_27_hi, regs_27_lo) node _regs_27_T_1 = bits(_regs_27_T, 27, 27) connect regs_27, _regs_27_T_1 node regs_28_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_28_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_28_T = cat(regs_28_hi, regs_28_lo) node _regs_28_T_1 = bits(_regs_28_T, 28, 28) connect regs_28, _regs_28_T_1 node regs_29_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_29_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_29_T = cat(regs_29_hi, regs_29_lo) node _regs_29_T_1 = bits(_regs_29_T, 29, 29) connect regs_29, _regs_29_T_1 node regs_30_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_30_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_30_T = cat(regs_30_hi, regs_30_lo) node _regs_30_T_1 = bits(_regs_30_T, 30, 30) connect regs_30, _regs_30_T_1 node regs_31_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_31_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_31_T = cat(regs_31_hi, regs_31_lo) node _regs_31_T_1 = bits(_regs_31_T, 31, 31) connect regs_31, _regs_31_T_1 connect io.capture.capture, UInt<1>(0h1) else : when io.chainIn.shift : connect regs_31, io.chainIn.data connect regs_0, regs_1 connect regs_1, regs_2 connect regs_2, regs_3 connect regs_3, regs_4 connect regs_4, regs_5 connect regs_5, regs_6 connect regs_6, regs_7 connect regs_7, regs_8 connect regs_8, regs_9 connect regs_9, regs_10 connect regs_10, regs_11 connect regs_11, regs_12 connect regs_12, regs_13 connect regs_13, regs_14 connect regs_14, regs_15 connect regs_15, regs_16 connect regs_16, regs_17 connect regs_17, regs_18 connect regs_18, regs_19 connect regs_19, regs_20 connect regs_20, regs_21 connect regs_21, regs_22 connect regs_22, regs_23 connect regs_23, regs_24 connect regs_24, regs_25 connect regs_25, regs_26 connect regs_26, regs_27 connect regs_27, regs_28 connect regs_28, regs_29 connect regs_29, regs_30 connect regs_30, regs_31 connect io.capture.capture, UInt<1>(0h0) else : connect io.capture.capture, UInt<1>(0h0) node _T = and(io.chainIn.capture, io.chainIn.update) node _T_1 = eq(_T, UInt<1>(0h0)) node _T_2 = and(io.chainIn.capture, io.chainIn.shift) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = and(_T_1, _T_3) node _T_5 = and(io.chainIn.update, io.chainIn.shift) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = and(_T_4, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at JtagShifter.scala:118 assert(!(io.chainIn.capture && io.chainIn.update)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert	module CaptureChain_JTAGIdcodeBundle( // @[JtagShifter.scala:89:7] input clock, // @[JtagShifter.scala:89:7] input reset, // @[JtagShifter.scala:89:7] input io_chainIn_shift, // @[JtagShifter.scala:94:14] input io_chainIn_data, // @[JtagShifter.scala:94:14] input io_chainIn_capture, // @[JtagShifter.scala:94:14] input io_chainIn_update, // @[JtagShifter.scala:94:14] output io_chainOut_data // @[JtagShifter.scala:94:14] ); reg regs_0; // @[JtagShifter.scala:102:39] reg regs_1; // @[JtagShifter.scala:102:39] reg regs_2; // @[JtagShifter.scala:102:39] reg regs_3; // @[JtagShifter.scala:102:39] reg regs_4; // @[JtagShifter.scala:102:39] reg regs_5; // @[JtagShifter.scala:102:39] reg regs_6; // @[JtagShifter.scala:102:39] reg regs_7; // @[JtagShifter.scala:102:39] reg regs_8; // @[JtagShifter.scala:102:39] reg regs_9; // @[JtagShifter.scala:102:39] reg regs_10; // @[JtagShifter.scala:102:39] reg regs_11; // @[JtagShifter.scala:102:39] reg regs_12; // @[JtagShifter.scala:102:39] reg regs_13; // @[JtagShifter.scala:102:39] reg regs_14; // @[JtagShifter.scala:102:39] reg regs_15; // @[JtagShifter.scala:102:39] reg regs_16; // @[JtagShifter.scala:102:39] reg regs_17; // @[JtagShifter.scala:102:39] reg regs_18; // @[JtagShifter.scala:102:39] reg regs_19; // @[JtagShifter.scala:102:39] reg regs_20; // @[JtagShifter.scala:102:39] reg regs_21; // @[JtagShifter.scala:102:39] reg regs_22; // @[JtagShifter.scala:102:39] reg regs_23; // @[JtagShifter.scala:102:39] reg regs_24; // @[JtagShifter.scala:102:39] reg regs_25; // @[JtagShifter.scala:102:39] reg regs_26; // @[JtagShifter.scala:102:39] reg regs_27; // @[JtagShifter.scala:102:39] reg regs_28; // @[JtagShifter.scala:102:39] reg regs_29; // @[JtagShifter.scala:102:39] reg regs_30; // @[JtagShifter.scala:102:39] reg regs_31; // @[JtagShifter.scala:102:39]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<4>(0h8)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_141 = shr(io.in.a.bits.source, 2) node _T_142 = eq(_T_141, UInt<4>(0h8)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<4>(0h8)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<17>(0h10000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<4>(0h8)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<2>(0h2)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<4>(0h8)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<2>(0h2)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<4>(0h8)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<17>(0h10000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<4>(0h8)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<2>(0h2)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<17>(0h10000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = and(_T_547, _T_552) node _T_554 = or(UInt<1>(0h0), _T_553) node _T_555 = and(_T_546, _T_554) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_555, UInt<1>(0h1), "") : assert_26 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(source_ok, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(is_aligned, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_565 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_565, UInt<1>(0h1), "") : assert_29 node _T_569 = eq(io.in.a.bits.mask, mask) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_569, UInt<1>(0h1), "") : assert_30 node _T_573 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_573 : node _T_574 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_575 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_578 = shr(io.in.a.bits.source, 2) node _T_579 = eq(_T_578, UInt<1>(0h0)) node _T_580 = leq(UInt<1>(0h0), uncommonBits_35) node _T_581 = and(_T_579, _T_580) node _T_582 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_583 = and(_T_581, _T_582) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_584 = shr(io.in.a.bits.source, 2) node _T_585 = eq(_T_584, UInt<1>(0h1)) node _T_586 = leq(UInt<1>(0h0), uncommonBits_36) node _T_587 = and(_T_585, _T_586) node _T_588 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_589 = and(_T_587, _T_588) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_590 = shr(io.in.a.bits.source, 2) node _T_591 = eq(_T_590, UInt<2>(0h2)) node _T_592 = leq(UInt<1>(0h0), uncommonBits_37) node _T_593 = and(_T_591, _T_592) node _T_594 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_595 = and(_T_593, _T_594) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<2>(0h3)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_38) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<4>(0h8)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_39) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_39, UInt<2>(0h2)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_610 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_611 = or(_T_577, _T_583) node _T_612 = or(_T_611, _T_589) node _T_613 = or(_T_612, _T_595) node _T_614 = or(_T_613, _T_601) node _T_615 = or(_T_614, _T_607) node _T_616 = or(_T_615, _T_608) node _T_617 = or(_T_616, _T_609) node _T_618 = or(_T_617, _T_610) node _T_619 = and(_T_576, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_623 = cvt(_T_622) node _T_624 = and(_T_623, asSInt(UInt<17>(0h10000))) node _T_625 = asSInt(_T_624) node _T_626 = eq(_T_625, asSInt(UInt<1>(0h0))) node _T_627 = and(_T_621, _T_626) node _T_628 = or(UInt<1>(0h0), _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_629, UInt<1>(0h1), "") : assert_31 node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(source_ok, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(is_aligned, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_639 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_639, UInt<1>(0h1), "") : assert_34 node _T_643 = not(mask) node _T_644 = and(io.in.a.bits.mask, _T_643) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_645, UInt<1>(0h1), "") : assert_35 node _T_649 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_649 : node _T_650 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_651 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_652 = and(_T_650, _T_651) node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_654 = shr(io.in.a.bits.source, 2) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_40) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h1)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_41) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<2>(0h2)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_42) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h3)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_43) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<4>(0h8)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_44) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_44, UInt<2>(0h2)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_686 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_687 = or(_T_653, _T_659) node _T_688 = or(_T_687, _T_665) node _T_689 = or(_T_688, _T_671) node _T_690 = or(_T_689, _T_677) node _T_691 = or(_T_690, _T_683) node _T_692 = or(_T_691, _T_684) node _T_693 = or(_T_692, _T_685) node _T_694 = or(_T_693, _T_686) node _T_695 = and(_T_652, _T_694) node _T_696 = or(UInt<1>(0h0), _T_695) node _T_697 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_698 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<17>(0h10000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = and(_T_697, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = and(_T_696, _T_704) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_705, UInt<1>(0h1), "") : assert_36 node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(source_ok, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(is_aligned, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_715 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_715, UInt<1>(0h1), "") : assert_39 node _T_719 = eq(io.in.a.bits.mask, mask) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_719, UInt<1>(0h1), "") : assert_40 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _T_727 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_728 = shr(io.in.a.bits.source, 2) node _T_729 = eq(_T_728, UInt<1>(0h0)) node _T_730 = leq(UInt<1>(0h0), uncommonBits_45) node _T_731 = and(_T_729, _T_730) node _T_732 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_733 = and(_T_731, _T_732) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h1)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_46) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<2>(0h2)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_47) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h3)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_48) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<4>(0h8)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_49) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_49, UInt<2>(0h2)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_759 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_761 = or(_T_727, _T_733) node _T_762 = or(_T_761, _T_739) node _T_763 = or(_T_762, _T_745) node _T_764 = or(_T_763, _T_751) node _T_765 = or(_T_764, _T_757) node _T_766 = or(_T_765, _T_758) node _T_767 = or(_T_766, _T_759) node _T_768 = or(_T_767, _T_760) node _T_769 = and(_T_726, _T_768) node _T_770 = or(UInt<1>(0h0), _T_769) node _T_771 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_772 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_773 = cvt(_T_772) node _T_774 = and(_T_773, asSInt(UInt<17>(0h10000))) node _T_775 = asSInt(_T_774) node _T_776 = eq(_T_775, asSInt(UInt<1>(0h0))) node _T_777 = and(_T_771, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = and(_T_770, _T_778) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_779, UInt<1>(0h1), "") : assert_41 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(source_ok, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(is_aligned, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_789 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_789, UInt<1>(0h1), "") : assert_44 node _T_793 = eq(io.in.a.bits.mask, mask) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_793, UInt<1>(0h1), "") : assert_45 node _T_797 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_797 : node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<1>(0h0)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_50) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h1)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_51) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<2>(0h2)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_52) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h3)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_53) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<4>(0h8)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_54) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_54, UInt<2>(0h2)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_834 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_835 = or(_T_801, _T_807) node _T_836 = or(_T_835, _T_813) node _T_837 = or(_T_836, _T_819) node _T_838 = or(_T_837, _T_825) node _T_839 = or(_T_838, _T_831) node _T_840 = or(_T_839, _T_832) node _T_841 = or(_T_840, _T_833) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_800, _T_842) node _T_844 = or(UInt<1>(0h0), _T_843) node _T_845 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_846 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = and(_T_845, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = and(_T_844, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_853, UInt<1>(0h1), "") : assert_46 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_863 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_863, UInt<1>(0h1), "") : assert_49 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_867, UInt<1>(0h1), "") : assert_50 node _T_871 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(_T_871, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_871, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_875 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_875, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_879 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_879 : node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(source_ok_1, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_883 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_883, UInt<1>(0h1), "") : assert_54 node _T_887 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_887, UInt<1>(0h1), "") : assert_55 node _T_891 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_891, UInt<1>(0h1), "") : assert_56 node _T_895 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_895, UInt<1>(0h1), "") : assert_57 node _T_899 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_899 : node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(source_ok_1, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(sink_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_906 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_906, UInt<1>(0h1), "") : assert_60 node _T_910 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_910, UInt<1>(0h1), "") : assert_61 node _T_914 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_914, UInt<1>(0h1), "") : assert_62 node _T_918 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_918, UInt<1>(0h1), "") : assert_63 node _T_922 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_923 = or(UInt<1>(0h0), _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_923, UInt<1>(0h1), "") : assert_64 node _T_927 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_927 : node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(source_ok_1, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(sink_ok, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_934 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_934, UInt<1>(0h1), "") : assert_67 node _T_938 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_938, UInt<1>(0h1), "") : assert_68 node _T_942 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_942, UInt<1>(0h1), "") : assert_69 node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_947 = or(_T_946, io.in.d.bits.corrupt) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_947, UInt<1>(0h1), "") : assert_70 node _T_951 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_952, UInt<1>(0h1), "") : assert_71 node _T_956 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_956 : node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(source_ok_1, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_960 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_960, UInt<1>(0h1), "") : assert_73 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_964, UInt<1>(0h1), "") : assert_74 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_969, UInt<1>(0h1), "") : assert_75 node _T_973 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_977, UInt<1>(0h1), "") : assert_77 node _T_981 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_982 = or(_T_981, io.in.d.bits.corrupt) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_982, UInt<1>(0h1), "") : assert_78 node _T_986 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_987, UInt<1>(0h1), "") : assert_79 node _T_991 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_991 : node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(source_ok_1, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_995 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_995, UInt<1>(0h1), "") : assert_81 node _T_999 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_999, UInt<1>(0h1), "") : assert_82 node _T_1003 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1008 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1012 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1016 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1020 = eq(a_first, UInt<1>(0h0)) node _T_1021 = and(io.in.a.valid, _T_1020) when _T_1021 : node _T_1022 = eq(io.in.a.bits.opcode, opcode) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_87 node _T_1026 = eq(io.in.a.bits.param, param) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_88 node _T_1030 = eq(io.in.a.bits.size, size) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_89 node _T_1034 = eq(io.in.a.bits.source, source) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_90 node _T_1038 = eq(io.in.a.bits.address, address) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_91 node _T_1042 = and(io.in.a.ready, io.in.a.valid) node _T_1043 = and(_T_1042, a_first) when _T_1043 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1044 = eq(d_first, UInt<1>(0h0)) node _T_1045 = and(io.in.d.valid, _T_1044) when _T_1045 : node _T_1046 = eq(io.in.d.bits.opcode, opcode_1) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_92 node _T_1050 = eq(io.in.d.bits.param, param_1) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_93 node _T_1054 = eq(io.in.d.bits.size, size_1) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_94 node _T_1058 = eq(io.in.d.bits.source, source_1) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_95 node _T_1062 = eq(io.in.d.bits.sink, sink) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_96 node _T_1066 = eq(io.in.d.bits.denied, denied) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_97 node _T_1070 = and(io.in.d.ready, io.in.d.valid) node _T_1071 = and(_T_1070, d_first) when _T_1071 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1072 = and(io.in.a.valid, a_first_1) node _T_1073 = and(_T_1072, UInt<1>(0h1)) when _T_1073 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1074 = and(io.in.a.ready, io.in.a.valid) node _T_1075 = and(_T_1074, a_first_1) node _T_1076 = and(_T_1075, UInt<1>(0h1)) when _T_1076 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1077 = dshr(inflight, io.in.a.bits.source) node _T_1078 = bits(_T_1077, 0, 0) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1083 = and(io.in.d.valid, d_first_1) node _T_1084 = and(_T_1083, UInt<1>(0h1)) node _T_1085 = eq(d_release_ack, UInt<1>(0h0)) node _T_1086 = and(_T_1084, _T_1085) when _T_1086 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1087 = and(io.in.d.ready, io.in.d.valid) node _T_1088 = and(_T_1087, d_first_1) node _T_1089 = and(_T_1088, UInt<1>(0h1)) node _T_1090 = eq(d_release_ack, UInt<1>(0h0)) node _T_1091 = and(_T_1089, _T_1090) when _T_1091 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1092 = and(io.in.d.valid, d_first_1) node _T_1093 = and(_T_1092, UInt<1>(0h1)) node _T_1094 = eq(d_release_ack, UInt<1>(0h0)) node _T_1095 = and(_T_1093, _T_1094) when _T_1095 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1096 = dshr(inflight, io.in.d.bits.source) node _T_1097 = bits(_T_1096, 0, 0) node _T_1098 = or(_T_1097, same_cycle_resp) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1102 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1103 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1104 = or(_T_1102, _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_100 node _T_1108 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_101 else : node _T_1112 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1113 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1114 = or(_T_1112, _T_1113) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_102 node _T_1118 = eq(io.in.d.bits.size, a_size_lookup) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_103 node _T_1122 = and(io.in.d.valid, d_first_1) node _T_1123 = and(_T_1122, a_first_1) node _T_1124 = and(_T_1123, io.in.a.valid) node _T_1125 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = eq(d_release_ack, UInt<1>(0h0)) node _T_1128 = and(_T_1126, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1130 = or(_T_1129, io.in.a.ready) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_1134 = orr(inflight) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) node _T_1136 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) node _T_1138 = lt(watchdog, plusarg_reader.out) node _T_1139 = or(_T_1137, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1143 = and(io.in.a.ready, io.in.a.valid) node _T_1144 = and(io.in.d.ready, io.in.d.valid) node _T_1145 = or(_T_1143, _T_1144) when _T_1145 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1146 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1147 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1148 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1146, _T_1149) when _T_1150 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1151 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1152 = and(_T_1151, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1153 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1154 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = and(_T_1152, _T_1155) when _T_1156 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1157 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1158 = bits(_T_1157, 0, 0) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1163 = and(io.in.d.valid, d_first_2) node _T_1164 = and(_T_1163, UInt<1>(0h1)) node _T_1165 = and(_T_1164, d_release_ack_1) when _T_1165 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1166 = and(io.in.d.ready, io.in.d.valid) node _T_1167 = and(_T_1166, d_first_2) node _T_1168 = and(_T_1167, UInt<1>(0h1)) node _T_1169 = and(_T_1168, d_release_ack_1) when _T_1169 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1170 = and(io.in.d.valid, d_first_2) node _T_1171 = and(_T_1170, UInt<1>(0h1)) node _T_1172 = and(_T_1171, d_release_ack_1) when _T_1172 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1173 = dshr(inflight_1, io.in.d.bits.source) node _T_1174 = bits(_T_1173, 0, 0) node _T_1175 = or(_T_1174, same_cycle_resp_1) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1179 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_108 else : node _T_1183 = eq(io.in.d.bits.size, c_size_lookup) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_109 node _T_1187 = and(io.in.d.valid, d_first_2) node _T_1188 = and(_T_1187, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1189 = and(_T_1188, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1190 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = and(_T_1191, d_release_ack_1) node _T_1193 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) when _T_1194 : node _T_1195 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1196 = or(_T_1195, _WIRE_27.ready) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_1200 = orr(inflight_1) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1203 = or(_T_1201, _T_1202) node _T_1204 = lt(watchdog_1, plusarg_reader_1.out) node _T_1205 = or(_T_1203, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1209 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = or(_T_1209, _T_1210) when _T_1211 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [259:0] _inflight_opcodes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [259:0] _inflight_sizes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [64:0] _inflight_T_4 = 65'h1FFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [259:0] d_opcodes_clr_1 = 260'h0; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1 = 260'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [64:0] d_clr_1 = 65'h0; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1 = 65'h0; // @[Monitor.scala:775:34] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1143 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1143; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1143; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1211 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1211; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1211; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1211; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1076 = _T_1143 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1076 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1076 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1076 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1076 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1076 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_1122 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_4 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1122 ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1089 = _T_1211 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_1089 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1089 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1089 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_19 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_19 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_19( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_19 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_134 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_134( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_47 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_94 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_47 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0he) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0he)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_16 = eq(UInt<4>(0hb), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_95 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_47 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node _c_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[1], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], _c_T_1) node _c_T_2 = cat(c_hi, _c_T) node _c_T_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _c_T_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node c_hi_1 = cat(io.out_credit_available.`2`[0], _c_T_4) node _c_T_5 = cat(c_hi_1, _c_T_3) node _c_T_6 = and(_c_T_2, _c_T_5) node c = neq(_c_T_6, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node out_channel_oh_0 = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_channel_oh_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _out_bundle_bits_out_virt_channel_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _out_bundle_bits_out_virt_channel_T_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 1) node _out_bundle_bits_out_virt_channel_T_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[1], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_1, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_5 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_3, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_6 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_4, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_8 = or(_out_bundle_bits_out_virt_channel_T_7, _out_bundle_bits_out_virt_channel_T_6) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<1> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_8 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_47( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hE; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hE; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d32s7k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a32d32s7k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [3:0] saved_mask; // @[Repeater.scala:21:18] reg [31:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_223 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], chosen_oh : UInt<2>[1]} regreset lock_0 : UInt<2>, clock, reset, UInt<2>(0h0) node _unassigned_T = cat(io.in[1].valid, io.in[0].valid) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire choices : UInt<2>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = mux(_sel_T_6, UInt<4>(0h8), UInt<4>(0h0)) node _sel_T_8 = mux(_sel_T_5, UInt<4>(0h4), _sel_T_7) node _sel_T_9 = mux(_sel_T_4, UInt<4>(0h2), _sel_T_8) node sel = mux(_sel_T_3, UInt<4>(0h1), _sel_T_9) node _choices_0_T = shr(sel, 2) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = mux(_T_3, UInt<2>(0h2), UInt<2>(0h0)) node _T_5 = mux(_T_2, UInt<2>(0h1), _T_4) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) node in_tails = cat(io.in[1].bits.tail, io.in[0].bits.tail) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node in_valids = cat(_in_valids_T_3, _in_valids_T_1) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<2>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) wire _io_out_0_bits_WIRE : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>} node _io_out_0_bits_T_2 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_4 = or(_io_out_0_bits_T_2, _io_out_0_bits_T_3) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_4 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_out_0_bits_WIRE_3 : UInt<1>[5] node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_5, _io_out_0_bits_T_6) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_7 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_10 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_13 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_13 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_14, _io_out_0_bits_T_15) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_16 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_19 = or(_io_out_0_bits_T_17, _io_out_0_bits_T_18) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_19 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_9 : UInt<1>[5] node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_21 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_21) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_9[0], _io_out_0_bits_WIRE_10 node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_25 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_25 connect _io_out_0_bits_WIRE_9[1], _io_out_0_bits_WIRE_11 node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_28 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_27) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_28 connect _io_out_0_bits_WIRE_9[2], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_30) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_31 connect _io_out_0_bits_WIRE_9[3], _io_out_0_bits_WIRE_13 node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_34 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33) wire _io_out_0_bits_WIRE_14 : UInt<1> connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_34 connect _io_out_0_bits_WIRE_9[4], _io_out_0_bits_WIRE_14 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_9 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_6 = bits(chosen, 0, 0) node _T_7 = and(_T_6, io.out[0].ready) when _T_7 : connect io.in[0].ready, UInt<1>(0h1) node _T_8 = bits(chosen, 1, 1) node _T_9 = and(_T_8, io.out[0].ready) when _T_9 : connect io.in[1].ready, UInt<1>(0h1) node _T_10 = or(UInt<2>(0h0), chosen) node _T_11 = and(io.out[0].ready, io.out[0].valid) when _T_11 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_12 = and(io.out[0].ready, io.out[0].valid) when _T_12 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = or(_mask_T, _mask_T_1) connect mask, _mask_T_2 else : node _mask_T_3 = not(mask) node _mask_T_4 = eq(_mask_T_3, UInt<1>(0h0)) node _mask_T_5 = shl(mask, 1) node _mask_T_6 = or(_mask_T_5, UInt<1>(0h1)) node _mask_T_7 = mux(_mask_T_4, UInt<1>(0h0), _mask_T_6) connect mask, _mask_T_7	module SwitchArbiter_223( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [1:0] mask; // @[SwitchAllocator.scala:27:21] wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71] wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [1:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[1:0] \| sel[3:2]; // @[Mux.scala:50:70] wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38] mask <= 2'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[1], \|chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_196 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_196( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_102 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_108 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_102( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_108 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_fbus_from_debug_sb : input clock : Clock input reset : Reset output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst widget of TLWidthWidget1 connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect widget.auto.anon_out.d, tlIn.d connect tlIn.a.bits, widget.auto.anon_out.a.bits connect tlIn.a.valid, widget.auto.anon_out.a.valid connect widget.auto.anon_out.a.ready, tlIn.a.ready connect auto.tl_out, tlOut connect widget.auto.anon_in, auto.widget_anon_in extmodule plusarg_reader_84 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_85 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLInterconnectCoupler_fbus_from_debug_sb( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLWidthWidget1 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode), .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size), .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address), .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data), .auto_anon_in_d_ready (auto_widget_anon_in_d_ready), .auto_anon_in_d_valid (auto_widget_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt), .auto_anon_out_a_ready (auto_tl_out_a_ready), .auto_anon_out_a_valid (auto_tl_out_a_valid), .auto_anon_out_a_bits_opcode (auto_tl_out_a_bits_opcode), .auto_anon_out_a_bits_size (auto_tl_out_a_bits_size), .auto_anon_out_a_bits_address (auto_tl_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_tl_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_tl_out_a_bits_data), .auto_anon_out_d_ready (auto_tl_out_d_ready), .auto_anon_out_d_valid (auto_tl_out_d_valid), .auto_anon_out_d_bits_opcode (auto_tl_out_d_bits_opcode), .auto_anon_out_d_bits_param (auto_tl_out_d_bits_param), .auto_anon_out_d_bits_size (auto_tl_out_d_bits_size), .auto_anon_out_d_bits_sink (auto_tl_out_d_bits_sink), .auto_anon_out_d_bits_denied (auto_tl_out_d_bits_denied), .auto_anon_out_d_bits_data (auto_tl_out_d_bits_data), .auto_anon_out_d_bits_corrupt (auto_tl_out_d_bits_corrupt) ); // @[WidthWidget.scala:230:28] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_130 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_131 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_62( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1148 = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1148 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1148 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1148 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1148 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1148 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_26 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} [15] wire _valids_WIRE : UInt<1>[15] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) regreset valids : UInt<1>[15], clock, reset, _valids_WIRE reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[15], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask) node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0)) node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0)) node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0)) node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4) node _do_enq_T_6 = and(io.flush, io.enq.bits.uop.uses_ldq) node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0)) node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7) wire do_enq : UInt<1> connect do_enq, _do_enq_T_8 node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0)) node _valids_0_T_4 = and(valids[0], _valids_0_T_3) node _valids_0_T_5 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0)) node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6) connect valids[0], _valids_0_T_7 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0)) node _valids_1_T_4 = and(valids[1], _valids_1_T_3) node _valids_1_T_5 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0)) node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6) connect valids[1], _valids_1_T_7 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0)) node _valids_2_T_4 = and(valids[2], _valids_2_T_3) node _valids_2_T_5 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0)) node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6) connect valids[2], _valids_2_T_7 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0)) node _valids_3_T_4 = and(valids[3], _valids_3_T_3) node _valids_3_T_5 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0)) node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6) connect valids[3], _valids_3_T_7 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0)) node _valids_4_T_4 = and(valids[4], _valids_4_T_3) node _valids_4_T_5 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0)) node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6) connect valids[4], _valids_4_T_7 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0)) node _valids_5_T_4 = and(valids[5], _valids_5_T_3) node _valids_5_T_5 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0)) node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6) connect valids[5], _valids_5_T_7 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0)) node _valids_6_T_4 = and(valids[6], _valids_6_T_3) node _valids_6_T_5 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0)) node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6) connect valids[6], _valids_6_T_7 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0)) node _valids_7_T_4 = and(valids[7], _valids_7_T_3) node _valids_7_T_5 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0)) node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6) connect valids[7], _valids_7_T_7 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = or(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = eq(_valids_8_T_2, UInt<1>(0h0)) node _valids_8_T_4 = and(valids[8], _valids_8_T_3) node _valids_8_T_5 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_6 = eq(_valids_8_T_5, UInt<1>(0h0)) node _valids_8_T_7 = and(_valids_8_T_4, _valids_8_T_6) connect valids[8], _valids_8_T_7 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = or(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = eq(_valids_9_T_2, UInt<1>(0h0)) node _valids_9_T_4 = and(valids[9], _valids_9_T_3) node _valids_9_T_5 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_6 = eq(_valids_9_T_5, UInt<1>(0h0)) node _valids_9_T_7 = and(_valids_9_T_4, _valids_9_T_6) connect valids[9], _valids_9_T_7 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = or(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = eq(_valids_10_T_2, UInt<1>(0h0)) node _valids_10_T_4 = and(valids[10], _valids_10_T_3) node _valids_10_T_5 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_6 = eq(_valids_10_T_5, UInt<1>(0h0)) node _valids_10_T_7 = and(_valids_10_T_4, _valids_10_T_6) connect valids[10], _valids_10_T_7 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = or(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = eq(_valids_11_T_2, UInt<1>(0h0)) node _valids_11_T_4 = and(valids[11], _valids_11_T_3) node _valids_11_T_5 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_6 = eq(_valids_11_T_5, UInt<1>(0h0)) node _valids_11_T_7 = and(_valids_11_T_4, _valids_11_T_6) connect valids[11], _valids_11_T_7 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = or(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = eq(_valids_12_T_2, UInt<1>(0h0)) node _valids_12_T_4 = and(valids[12], _valids_12_T_3) node _valids_12_T_5 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_6 = eq(_valids_12_T_5, UInt<1>(0h0)) node _valids_12_T_7 = and(_valids_12_T_4, _valids_12_T_6) connect valids[12], _valids_12_T_7 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = or(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = eq(_valids_13_T_2, UInt<1>(0h0)) node _valids_13_T_4 = and(valids[13], _valids_13_T_3) node _valids_13_T_5 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_6 = eq(_valids_13_T_5, UInt<1>(0h0)) node _valids_13_T_7 = and(_valids_13_T_4, _valids_13_T_6) connect valids[13], _valids_13_T_7 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = or(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = eq(_valids_14_T_2, UInt<1>(0h0)) node _valids_14_T_4 = and(valids[14], _valids_14_T_3) node _valids_14_T_5 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_6 = eq(_valids_14_T_5, UInt<1>(0h0)) node _valids_14_T_7 = and(_valids_14_T_4, _valids_14_T_6) connect valids[14], _valids_14_T_7 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0he)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when wrap : connect enq_ptr_value, UInt<1>(0h0) when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0he)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 when wrap_1 : connect deq_ptr_value, UInt<1>(0h0) node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) connect io.deq.valid, _io_deq_valid_T_1 connect io.deq.bits, out node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = mux(maybe_full, UInt<4>(0hf), UInt<1>(0h0)) node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value) node _io_count_T_2 = add(UInt<4>(0hf), ptr_diff) node _io_count_T_3 = tail(_io_count_T_2, 1) node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff) node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4) connect io.count, _io_count_T_5	module BranchKillableQueue_26( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 \| _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 \| _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 \| _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 \| _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 \| _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 \| _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 \| _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 \| _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 \| _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 \| _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 \| _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 \| _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 \| _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 \| _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 \| _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 \| _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_133 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_389 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_133( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_389 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg s1_id : UInt, clock reg s2_id : UInt, clock connect s2_id, s1_id node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) connect io.mem.req.valid, _io_mem_req_valid_T connect io.requestor[0].req.ready, io.mem.req.ready node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 connect io.mem.req.bits, io.requestor[1].req.bits node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T connect s1_id, UInt<1>(0h1) connect io.mem.s1_kill, io.requestor[1].s1_kill connect io.mem.s1_data, io.requestor[1].s1_data connect io.mem.s2_kill, io.requestor[1].s2_kill when io.requestor[0].req.valid : connect io.mem.req.bits, io.requestor[0].req.bits node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 connect s1_id, UInt<1>(0h0) node _T = eq(s1_id, UInt<1>(0h0)) when _T : connect io.mem.s1_kill, io.requestor[0].s1_kill connect io.mem.s1_data, io.requestor[0].s1_data node _T_1 = eq(s2_id, UInt<1>(0h0)) when _T_1 : connect io.mem.s2_kill, io.requestor[0].s2_kill node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt connect io.requestor[0].s2_gpa, io.mem.s2_gpa connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[0].ordered, io.mem.ordered connect io.requestor[0].store_pending, io.mem.store_pending connect io.requestor[0].perf, io.mem.perf node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[0].s2_uncached, io.mem.s2_uncached connect io.requestor[0].s2_paddr, io.mem.s2_paddr connect io.requestor[0].clock_enabled, io.mem.clock_enabled connect io.requestor[0].resp.bits, io.mem.resp.bits node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T connect io.requestor[0].replay_next, io.mem.replay_next node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt connect io.requestor[1].s2_gpa, io.mem.s2_gpa connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[1].ordered, io.mem.ordered connect io.requestor[1].store_pending, io.mem.store_pending connect io.requestor[1].perf, io.mem.perf node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[1].s2_uncached, io.mem.s2_uncached connect io.requestor[1].s2_paddr, io.mem.s2_paddr connect io.requestor[1].clock_enabled, io.mem.clock_enabled connect io.requestor[1].resp.bits, io.mem.resp.bits node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T connect io.requestor[1].replay_next, io.mem.replay_next	module HellaCacheArbiter( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [6:0] io_requestor_0_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_0_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_0_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_0_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_1_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_xcpt, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [6:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_req_bits_tag_0 = io_requestor_0_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd_0 = io_requestor_0_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_size_0 = io_requestor_0_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed_0 = io_requestor_0_req_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp_0 = io_requestor_0_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_s1_data_data_0 = io_requestor_0_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled_0 = io_requestor_0_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [7:0] _io_mem_req_bits_tag_T = 8'h1; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_1_req_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [6:0] io_requestor_1_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_dprv = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_mem_keep_clock_enabled_T = io_requestor_0_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63] wire io_mem_req_bits_phys_0 = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] wire io_mem_req_bits_no_xcpt_0 = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] reg s1_id; // @[HellaCacheArbiter.scala:20:20] reg s2_id; // @[HellaCacheArbiter.scala:21:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58] assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T; // @[HellaCacheArbiter.scala:10:7, :23:81] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 \| io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_cmd_0 : io_requestor_1_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_size_0 : io_requestor_1_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_signed_0 = io_requestor_0_req_valid_0 & io_requestor_0_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = {2{io_requestor_0_req_valid_0}}; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 & io_requestor_0_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_no_resp_0 = io_requestor_0_req_valid_0 & io_requestor_0_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] wire [7:0] _io_mem_req_bits_tag_T_1 = {io_requestor_0_req_bits_tag_0, 1'h0}; // @[HellaCacheArbiter.scala:10:7, :34:35] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? _io_mem_req_bits_tag_T_1[6:0] : 7'h1; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26] assign io_mem_s1_kill_0 = s1_id ? io_requestor_1_s1_kill_0 : io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:30] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : io_requestor_0_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30] assign io_mem_s1_data_mask_0 = s1_id ? io_requestor_1_s1_data_mask_0 : 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :20:20, :33:25, :39:24, :50:26, :51:30] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_xcpt = io_mem_req_bits_no_xcpt_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_115 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_115 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 5) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h1f)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 5) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h1f)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_24 = shr(io.in.a.bits.source, 5) node _source_ok_T_25 = eq(_source_ok_T_24, UInt<3>(0h4)) node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26) node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_30 = shr(io.in.a.bits.source, 5) node _source_ok_T_31 = eq(_source_ok_T_30, UInt<3>(0h5)) node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_36 = shr(io.in.a.bits.source, 5) node _source_ok_T_37 = eq(_source_ok_T_36, UInt<3>(0h6)) node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_42 = shr(io.in.a.bits.source, 5) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<3>(0h7)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 connect _source_ok_WIRE[4], _source_ok_T_29 connect _source_ok_WIRE[5], _source_ok_T_35 connect _source_ok_WIRE[6], _source_ok_T_41 connect _source_ok_WIRE[7], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_17 = shr(io.in.a.bits.source, 5) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_30 = shr(io.in.a.bits.source, 5) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_43 = shr(io.in.a.bits.source, 5) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_56 = shr(io.in.a.bits.source, 5) node _T_57 = eq(_T_56, UInt<3>(0h4)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_4) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<1>(0h0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_69 = shr(io.in.a.bits.source, 5) node _T_70 = eq(_T_69, UInt<3>(0h5)) node _T_71 = leq(UInt<1>(0h0), uncommonBits_5) node _T_72 = and(_T_70, _T_71) node _T_73 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = or(_T_75, _T_80) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_82 = shr(io.in.a.bits.source, 5) node _T_83 = eq(_T_82, UInt<3>(0h6)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_6) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(_T_87, UInt<1>(0h0)) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_95 = shr(io.in.a.bits.source, 5) node _T_96 = eq(_T_95, UInt<3>(0h7)) node _T_97 = leq(UInt<1>(0h0), uncommonBits_7) node _T_98 = and(_T_96, _T_97) node _T_99 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_100 = and(_T_98, _T_99) node _T_101 = eq(_T_100, UInt<1>(0h0)) node _T_102 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = or(_T_101, _T_106) node _T_108 = and(_T_16, _T_29) node _T_109 = and(_T_108, _T_42) node _T_110 = and(_T_109, _T_55) node _T_111 = and(_T_110, _T_68) node _T_112 = and(_T_111, _T_81) node _T_113 = and(_T_112, _T_94) node _T_114 = and(_T_113, _T_107) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_114, UInt<1>(0h1), "") : assert_1 node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_118 : node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_121 = and(_T_119, _T_120) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_122 = shr(io.in.a.bits.source, 5) node _T_123 = eq(_T_122, UInt<1>(0h0)) node _T_124 = leq(UInt<1>(0h0), uncommonBits_8) node _T_125 = and(_T_123, _T_124) node _T_126 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_127 = and(_T_125, _T_126) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_128 = shr(io.in.a.bits.source, 5) node _T_129 = eq(_T_128, UInt<1>(0h1)) node _T_130 = leq(UInt<1>(0h0), uncommonBits_9) node _T_131 = and(_T_129, _T_130) node _T_132 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_133 = and(_T_131, _T_132) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_134 = shr(io.in.a.bits.source, 5) node _T_135 = eq(_T_134, UInt<2>(0h2)) node _T_136 = leq(UInt<1>(0h0), uncommonBits_10) node _T_137 = and(_T_135, _T_136) node _T_138 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_139 = and(_T_137, _T_138) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<2>(0h3)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_11) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0) node _T_146 = shr(io.in.a.bits.source, 5) node _T_147 = eq(_T_146, UInt<3>(0h4)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_12) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_12, UInt<5>(0h1f)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<3>(0h5)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_13) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_13, UInt<5>(0h1f)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_158 = shr(io.in.a.bits.source, 5) node _T_159 = eq(_T_158, UInt<3>(0h6)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_14) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_163 = and(_T_161, _T_162) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_164 = shr(io.in.a.bits.source, 5) node _T_165 = eq(_T_164, UInt<3>(0h7)) node _T_166 = leq(UInt<1>(0h0), uncommonBits_15) node _T_167 = and(_T_165, _T_166) node _T_168 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(_T_127, _T_133) node _T_171 = or(_T_170, _T_139) node _T_172 = or(_T_171, _T_145) node _T_173 = or(_T_172, _T_151) node _T_174 = or(_T_173, _T_157) node _T_175 = or(_T_174, _T_163) node _T_176 = or(_T_175, _T_169) node _T_177 = and(_T_121, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<14>(0h2000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_191 = cvt(_T_190) node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000))) node _T_193 = asSInt(_T_192) node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0))) node _T_195 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<18>(0h2f000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_201 = cvt(_T_200) node _T_202 = and(_T_201, asSInt(UInt<17>(0h10000))) node _T_203 = asSInt(_T_202) node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<27>(0h4000000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<19>(0h40000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = or(_T_184, _T_189) node _T_226 = or(_T_225, _T_194) node _T_227 = or(_T_226, _T_199) node _T_228 = or(_T_227, _T_204) node _T_229 = or(_T_228, _T_209) node _T_230 = or(_T_229, _T_214) node _T_231 = or(_T_230, _T_219) node _T_232 = or(_T_231, _T_224) node _T_233 = and(_T_179, _T_232) node _T_234 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_235 = or(UInt<1>(0h0), _T_234) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<29>(0h10000000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_240, _T_245) node _T_247 = and(_T_235, _T_246) node _T_248 = or(UInt<1>(0h0), _T_233) node _T_249 = or(_T_248, _T_247) node _T_250 = and(_T_178, _T_249) node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(_T_250, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_250, UInt<1>(0h1), "") : assert_2 node _T_254 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_255 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_256 = and(_T_254, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<14>(0h2000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<13>(0h1000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<17>(0h10000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<18>(0h2f000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<17>(0h10000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<27>(0h4000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<19>(0h40000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_262, _T_267) node _T_314 = or(_T_313, _T_272) node _T_315 = or(_T_314, _T_277) node _T_316 = or(_T_315, _T_282) node _T_317 = or(_T_316, _T_287) node _T_318 = or(_T_317, _T_292) node _T_319 = or(_T_318, _T_297) node _T_320 = or(_T_319, _T_302) node _T_321 = or(_T_320, _T_307) node _T_322 = or(_T_321, _T_312) node _T_323 = and(_T_257, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = and(UInt<1>(0h0), _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_325, UInt<1>(0h1), "") : assert_3 node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(source_ok, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_332 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_332, UInt<1>(0h1), "") : assert_5 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(is_aligned, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_339 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_339, UInt<1>(0h1), "") : assert_7 node _T_343 = not(io.in.a.bits.mask) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_344, UInt<1>(0h1), "") : assert_8 node _T_348 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_348, UInt<1>(0h1), "") : assert_9 node _T_352 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_352 : node _T_353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_354 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_355 = and(_T_353, _T_354) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_356 = shr(io.in.a.bits.source, 5) node _T_357 = eq(_T_356, UInt<1>(0h0)) node _T_358 = leq(UInt<1>(0h0), uncommonBits_16) node _T_359 = and(_T_357, _T_358) node _T_360 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_361 = and(_T_359, _T_360) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_362 = shr(io.in.a.bits.source, 5) node _T_363 = eq(_T_362, UInt<1>(0h1)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_367 = and(_T_365, _T_366) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_368 = shr(io.in.a.bits.source, 5) node _T_369 = eq(_T_368, UInt<2>(0h2)) node _T_370 = leq(UInt<1>(0h0), uncommonBits_18) node _T_371 = and(_T_369, _T_370) node _T_372 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<2>(0h3)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_19) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_380 = shr(io.in.a.bits.source, 5) node _T_381 = eq(_T_380, UInt<3>(0h4)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_20) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_386 = shr(io.in.a.bits.source, 5) node _T_387 = eq(_T_386, UInt<3>(0h5)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_21) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_392 = shr(io.in.a.bits.source, 5) node _T_393 = eq(_T_392, UInt<3>(0h6)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_22) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_398 = shr(io.in.a.bits.source, 5) node _T_399 = eq(_T_398, UInt<3>(0h7)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_23) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(_T_361, _T_367) node _T_405 = or(_T_404, _T_373) node _T_406 = or(_T_405, _T_379) node _T_407 = or(_T_406, _T_385) node _T_408 = or(_T_407, _T_391) node _T_409 = or(_T_408, _T_397) node _T_410 = or(_T_409, _T_403) node _T_411 = and(_T_355, _T_410) node _T_412 = or(UInt<1>(0h0), _T_411) node _T_413 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<19>(0h40000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = or(_T_418, _T_423) node _T_460 = or(_T_459, _T_428) node _T_461 = or(_T_460, _T_433) node _T_462 = or(_T_461, _T_438) node _T_463 = or(_T_462, _T_443) node _T_464 = or(_T_463, _T_448) node _T_465 = or(_T_464, _T_453) node _T_466 = or(_T_465, _T_458) node _T_467 = and(_T_413, _T_466) node _T_468 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_469 = or(UInt<1>(0h0), _T_468) node _T_470 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<17>(0h10000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<29>(0h10000000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = or(_T_474, _T_479) node _T_481 = and(_T_469, _T_480) node _T_482 = or(UInt<1>(0h0), _T_467) node _T_483 = or(_T_482, _T_481) node _T_484 = and(_T_412, _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_484, UInt<1>(0h1), "") : assert_10 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<14>(0h2000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<17>(0h10000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<19>(0h40000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<29>(0h10000000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = or(_T_496, _T_501) node _T_548 = or(_T_547, _T_506) node _T_549 = or(_T_548, _T_511) node _T_550 = or(_T_549, _T_516) node _T_551 = or(_T_550, _T_521) node _T_552 = or(_T_551, _T_526) node _T_553 = or(_T_552, _T_531) node _T_554 = or(_T_553, _T_536) node _T_555 = or(_T_554, _T_541) node _T_556 = or(_T_555, _T_546) node _T_557 = and(_T_491, _T_556) node _T_558 = or(UInt<1>(0h0), _T_557) node _T_559 = and(UInt<1>(0h0), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_559, UInt<1>(0h1), "") : assert_11 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_566 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_566, UInt<1>(0h1), "") : assert_13 node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(is_aligned, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_573 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_573, UInt<1>(0h1), "") : assert_15 node _T_577 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_577, UInt<1>(0h1), "") : assert_16 node _T_581 = not(io.in.a.bits.mask) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_582, UInt<1>(0h1), "") : assert_17 node _T_586 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_586, UInt<1>(0h1), "") : assert_18 node _T_590 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_590 : node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0) node _T_594 = shr(io.in.a.bits.source, 5) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_24) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_24, UInt<5>(0h1f)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0) node _T_600 = shr(io.in.a.bits.source, 5) node _T_601 = eq(_T_600, UInt<1>(0h1)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_25) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_25, UInt<5>(0h1f)) node _T_605 = and(_T_603, _T_604) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0) node _T_606 = shr(io.in.a.bits.source, 5) node _T_607 = eq(_T_606, UInt<2>(0h2)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_26) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_26, UInt<5>(0h1f)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0) node _T_612 = shr(io.in.a.bits.source, 5) node _T_613 = eq(_T_612, UInt<2>(0h3)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_27) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_27, UInt<5>(0h1f)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_618 = shr(io.in.a.bits.source, 5) node _T_619 = eq(_T_618, UInt<3>(0h4)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_28) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_624 = shr(io.in.a.bits.source, 5) node _T_625 = eq(_T_624, UInt<3>(0h5)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_29) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_630 = shr(io.in.a.bits.source, 5) node _T_631 = eq(_T_630, UInt<3>(0h6)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_30) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_636 = shr(io.in.a.bits.source, 5) node _T_637 = eq(_T_636, UInt<3>(0h7)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_31) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_641 = and(_T_639, _T_640) node _T_642 = or(_T_599, _T_605) node _T_643 = or(_T_642, _T_611) node _T_644 = or(_T_643, _T_617) node _T_645 = or(_T_644, _T_623) node _T_646 = or(_T_645, _T_629) node _T_647 = or(_T_646, _T_635) node _T_648 = or(_T_647, _T_641) node _T_649 = and(_T_593, _T_648) node _T_650 = or(UInt<1>(0h0), _T_649) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_650, UInt<1>(0h1), "") : assert_19 node _T_654 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_655 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_656 = and(_T_654, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = and(_T_657, _T_662) node _T_664 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_665 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_666 = and(_T_664, _T_665) node _T_667 = or(UInt<1>(0h0), _T_666) node _T_668 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<14>(0h2000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<18>(0h2f000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<17>(0h10000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<13>(0h1000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<27>(0h4000000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<19>(0h40000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<29>(0h10000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = or(_T_672, _T_677) node _T_719 = or(_T_718, _T_682) node _T_720 = or(_T_719, _T_687) node _T_721 = or(_T_720, _T_692) node _T_722 = or(_T_721, _T_697) node _T_723 = or(_T_722, _T_702) node _T_724 = or(_T_723, _T_707) node _T_725 = or(_T_724, _T_712) node _T_726 = or(_T_725, _T_717) node _T_727 = and(_T_667, _T_726) node _T_728 = or(UInt<1>(0h0), _T_663) node _T_729 = or(_T_728, _T_727) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_729, UInt<1>(0h1), "") : assert_20 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(source_ok, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(is_aligned, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_739 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_739, UInt<1>(0h1), "") : assert_23 node _T_743 = eq(io.in.a.bits.mask, mask) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_743, UInt<1>(0h1), "") : assert_24 node _T_747 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_747, UInt<1>(0h1), "") : assert_25 node _T_751 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_751 : node _T_752 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_753 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_755 = shr(io.in.a.bits.source, 5) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_32) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_761 = shr(io.in.a.bits.source, 5) node _T_762 = eq(_T_761, UInt<1>(0h1)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_33) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_767 = shr(io.in.a.bits.source, 5) node _T_768 = eq(_T_767, UInt<2>(0h2)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_34) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_773 = shr(io.in.a.bits.source, 5) node _T_774 = eq(_T_773, UInt<2>(0h3)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_35) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_779 = shr(io.in.a.bits.source, 5) node _T_780 = eq(_T_779, UInt<3>(0h4)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_36) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_785 = shr(io.in.a.bits.source, 5) node _T_786 = eq(_T_785, UInt<3>(0h5)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_37) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_790 = and(_T_788, _T_789) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_791 = shr(io.in.a.bits.source, 5) node _T_792 = eq(_T_791, UInt<3>(0h6)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_38) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_797 = shr(io.in.a.bits.source, 5) node _T_798 = eq(_T_797, UInt<3>(0h7)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_39) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_802 = and(_T_800, _T_801) node _T_803 = or(_T_760, _T_766) node _T_804 = or(_T_803, _T_772) node _T_805 = or(_T_804, _T_778) node _T_806 = or(_T_805, _T_784) node _T_807 = or(_T_806, _T_790) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_802) node _T_810 = and(_T_754, _T_809) node _T_811 = or(UInt<1>(0h0), _T_810) node _T_812 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_813 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_814 = and(_T_812, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_817 = cvt(_T_816) node _T_818 = and(_T_817, asSInt(UInt<13>(0h1000))) node _T_819 = asSInt(_T_818) node _T_820 = eq(_T_819, asSInt(UInt<1>(0h0))) node _T_821 = and(_T_815, _T_820) node _T_822 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_823 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_824 = and(_T_822, _T_823) node _T_825 = or(UInt<1>(0h0), _T_824) node _T_826 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<14>(0h2000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_832 = cvt(_T_831) node _T_833 = and(_T_832, asSInt(UInt<18>(0h2f000))) node _T_834 = asSInt(_T_833) node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0))) node _T_836 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_837 = cvt(_T_836) node _T_838 = and(_T_837, asSInt(UInt<17>(0h10000))) node _T_839 = asSInt(_T_838) node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0))) node _T_841 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_842 = cvt(_T_841) node _T_843 = and(_T_842, asSInt(UInt<13>(0h1000))) node _T_844 = asSInt(_T_843) node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0))) node _T_846 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<27>(0h4000000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<19>(0h40000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<29>(0h10000000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = or(_T_830, _T_835) node _T_872 = or(_T_871, _T_840) node _T_873 = or(_T_872, _T_845) node _T_874 = or(_T_873, _T_850) node _T_875 = or(_T_874, _T_855) node _T_876 = or(_T_875, _T_860) node _T_877 = or(_T_876, _T_865) node _T_878 = or(_T_877, _T_870) node _T_879 = and(_T_825, _T_878) node _T_880 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_881 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = and(_T_880, _T_885) node _T_887 = or(UInt<1>(0h0), _T_821) node _T_888 = or(_T_887, _T_879) node _T_889 = or(_T_888, _T_886) node _T_890 = and(_T_811, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_890, UInt<1>(0h1), "") : assert_26 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_900 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_900, UInt<1>(0h1), "") : assert_29 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_904, UInt<1>(0h1), "") : assert_30 node _T_908 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_908 : node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_911 = and(_T_909, _T_910) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_912 = shr(io.in.a.bits.source, 5) node _T_913 = eq(_T_912, UInt<1>(0h0)) node _T_914 = leq(UInt<1>(0h0), uncommonBits_40) node _T_915 = and(_T_913, _T_914) node _T_916 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_917 = and(_T_915, _T_916) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_918 = shr(io.in.a.bits.source, 5) node _T_919 = eq(_T_918, UInt<1>(0h1)) node _T_920 = leq(UInt<1>(0h0), uncommonBits_41) node _T_921 = and(_T_919, _T_920) node _T_922 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_923 = and(_T_921, _T_922) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_924 = shr(io.in.a.bits.source, 5) node _T_925 = eq(_T_924, UInt<2>(0h2)) node _T_926 = leq(UInt<1>(0h0), uncommonBits_42) node _T_927 = and(_T_925, _T_926) node _T_928 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_929 = and(_T_927, _T_928) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_930 = shr(io.in.a.bits.source, 5) node _T_931 = eq(_T_930, UInt<2>(0h3)) node _T_932 = leq(UInt<1>(0h0), uncommonBits_43) node _T_933 = and(_T_931, _T_932) node _T_934 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_935 = and(_T_933, _T_934) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_936 = shr(io.in.a.bits.source, 5) node _T_937 = eq(_T_936, UInt<3>(0h4)) node _T_938 = leq(UInt<1>(0h0), uncommonBits_44) node _T_939 = and(_T_937, _T_938) node _T_940 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_941 = and(_T_939, _T_940) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_942 = shr(io.in.a.bits.source, 5) node _T_943 = eq(_T_942, UInt<3>(0h5)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_45) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_948 = shr(io.in.a.bits.source, 5) node _T_949 = eq(_T_948, UInt<3>(0h6)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_46) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_954 = shr(io.in.a.bits.source, 5) node _T_955 = eq(_T_954, UInt<3>(0h7)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_47) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_959 = and(_T_957, _T_958) node _T_960 = or(_T_917, _T_923) node _T_961 = or(_T_960, _T_929) node _T_962 = or(_T_961, _T_935) node _T_963 = or(_T_962, _T_941) node _T_964 = or(_T_963, _T_947) node _T_965 = or(_T_964, _T_953) node _T_966 = or(_T_965, _T_959) node _T_967 = and(_T_911, _T_966) node _T_968 = or(UInt<1>(0h0), _T_967) node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_971 = and(_T_969, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<13>(0h1000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = and(_T_972, _T_977) node _T_979 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_980 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_981 = and(_T_979, _T_980) node _T_982 = or(UInt<1>(0h0), _T_981) node _T_983 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<14>(0h2000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_989 = cvt(_T_988) node _T_990 = and(_T_989, asSInt(UInt<18>(0h2f000))) node _T_991 = asSInt(_T_990) node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0))) node _T_993 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_994 = cvt(_T_993) node _T_995 = and(_T_994, asSInt(UInt<17>(0h10000))) node _T_996 = asSInt(_T_995) node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0))) node _T_998 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1004 = cvt(_T_1003) node _T_1005 = and(_T_1004, asSInt(UInt<17>(0h10000))) node _T_1006 = asSInt(_T_1005) node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0))) node _T_1008 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<27>(0h4000000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<19>(0h40000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<29>(0h10000000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = or(_T_987, _T_992) node _T_1029 = or(_T_1028, _T_997) node _T_1030 = or(_T_1029, _T_1002) node _T_1031 = or(_T_1030, _T_1007) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1017) node _T_1034 = or(_T_1033, _T_1022) node _T_1035 = or(_T_1034, _T_1027) node _T_1036 = and(_T_982, _T_1035) node _T_1037 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1038 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<17>(0h10000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = and(_T_1037, _T_1042) node _T_1044 = or(UInt<1>(0h0), _T_978) node _T_1045 = or(_T_1044, _T_1036) node _T_1046 = or(_T_1045, _T_1043) node _T_1047 = and(_T_968, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_31 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1057 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_34 node _T_1061 = not(mask) node _T_1062 = and(io.in.a.bits.mask, _T_1061) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_35 node _T_1067 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1067 : node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1070 = and(_T_1068, _T_1069) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0) node _T_1071 = shr(io.in.a.bits.source, 5) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1074 = and(_T_1072, _T_1073) node _T_1075 = leq(uncommonBits_48, UInt<5>(0h1f)) node _T_1076 = and(_T_1074, _T_1075) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0) node _T_1077 = shr(io.in.a.bits.source, 5) node _T_1078 = eq(_T_1077, UInt<1>(0h1)) node _T_1079 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = leq(uncommonBits_49, UInt<5>(0h1f)) node _T_1082 = and(_T_1080, _T_1081) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_1083 = shr(io.in.a.bits.source, 5) node _T_1084 = eq(_T_1083, UInt<2>(0h2)) node _T_1085 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_1088 = and(_T_1086, _T_1087) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_1089 = shr(io.in.a.bits.source, 5) node _T_1090 = eq(_T_1089, UInt<2>(0h3)) node _T_1091 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_1094 = and(_T_1092, _T_1093) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_1095 = shr(io.in.a.bits.source, 5) node _T_1096 = eq(_T_1095, UInt<3>(0h4)) node _T_1097 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1098 = and(_T_1096, _T_1097) node _T_1099 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_1100 = and(_T_1098, _T_1099) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_1101 = shr(io.in.a.bits.source, 5) node _T_1102 = eq(_T_1101, UInt<3>(0h5)) node _T_1103 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1104 = and(_T_1102, _T_1103) node _T_1105 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_1106 = and(_T_1104, _T_1105) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_1107 = shr(io.in.a.bits.source, 5) node _T_1108 = eq(_T_1107, UInt<3>(0h6)) node _T_1109 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_1112 = and(_T_1110, _T_1111) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_1113 = shr(io.in.a.bits.source, 5) node _T_1114 = eq(_T_1113, UInt<3>(0h7)) node _T_1115 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = or(_T_1076, _T_1082) node _T_1120 = or(_T_1119, _T_1088) node _T_1121 = or(_T_1120, _T_1094) node _T_1122 = or(_T_1121, _T_1100) node _T_1123 = or(_T_1122, _T_1106) node _T_1124 = or(_T_1123, _T_1112) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = and(_T_1070, _T_1125) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1129 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = or(UInt<1>(0h0), _T_1130) node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<14>(0h2000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<17>(0h10000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<27>(0h4000000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<19>(0h40000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<29>(0h10000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = or(_T_1136, _T_1141) node _T_1183 = or(_T_1182, _T_1146) node _T_1184 = or(_T_1183, _T_1151) node _T_1185 = or(_T_1184, _T_1156) node _T_1186 = or(_T_1185, _T_1161) node _T_1187 = or(_T_1186, _T_1166) node _T_1188 = or(_T_1187, _T_1171) node _T_1189 = or(_T_1188, _T_1176) node _T_1190 = or(_T_1189, _T_1181) node _T_1191 = and(_T_1131, _T_1190) node _T_1192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<17>(0h10000))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = and(_T_1192, _T_1197) node _T_1199 = or(UInt<1>(0h0), _T_1191) node _T_1200 = or(_T_1199, _T_1198) node _T_1201 = and(_T_1127, _T_1200) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_36 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(source_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(is_aligned, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1211 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_39 node _T_1215 = eq(io.in.a.bits.mask, mask) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_40 node _T_1219 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1219 : node _T_1220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1222 = and(_T_1220, _T_1221) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_1223 = shr(io.in.a.bits.source, 5) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) node _T_1225 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_1228 = and(_T_1226, _T_1227) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_1229 = shr(io.in.a.bits.source, 5) node _T_1230 = eq(_T_1229, UInt<1>(0h1)) node _T_1231 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1232 = and(_T_1230, _T_1231) node _T_1233 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_1234 = and(_T_1232, _T_1233) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_1235 = shr(io.in.a.bits.source, 5) node _T_1236 = eq(_T_1235, UInt<2>(0h2)) node _T_1237 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1238 = and(_T_1236, _T_1237) node _T_1239 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_1240 = and(_T_1238, _T_1239) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_1241 = shr(io.in.a.bits.source, 5) node _T_1242 = eq(_T_1241, UInt<2>(0h3)) node _T_1243 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1244 = and(_T_1242, _T_1243) node _T_1245 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_1246 = and(_T_1244, _T_1245) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_1247 = shr(io.in.a.bits.source, 5) node _T_1248 = eq(_T_1247, UInt<3>(0h4)) node _T_1249 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1250 = and(_T_1248, _T_1249) node _T_1251 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_1252 = and(_T_1250, _T_1251) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_1253 = shr(io.in.a.bits.source, 5) node _T_1254 = eq(_T_1253, UInt<3>(0h5)) node _T_1255 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1256 = and(_T_1254, _T_1255) node _T_1257 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_1258 = and(_T_1256, _T_1257) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_1259 = shr(io.in.a.bits.source, 5) node _T_1260 = eq(_T_1259, UInt<3>(0h6)) node _T_1261 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_1264 = and(_T_1262, _T_1263) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_1265 = shr(io.in.a.bits.source, 5) node _T_1266 = eq(_T_1265, UInt<3>(0h7)) node _T_1267 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = or(_T_1228, _T_1234) node _T_1272 = or(_T_1271, _T_1240) node _T_1273 = or(_T_1272, _T_1246) node _T_1274 = or(_T_1273, _T_1252) node _T_1275 = or(_T_1274, _T_1258) node _T_1276 = or(_T_1275, _T_1264) node _T_1277 = or(_T_1276, _T_1270) node _T_1278 = and(_T_1222, _T_1277) node _T_1279 = or(UInt<1>(0h0), _T_1278) node _T_1280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1281 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1285 = cvt(_T_1284) node _T_1286 = and(_T_1285, asSInt(UInt<14>(0h2000))) node _T_1287 = asSInt(_T_1286) node _T_1288 = eq(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1290 = cvt(_T_1289) node _T_1291 = and(_T_1290, asSInt(UInt<13>(0h1000))) node _T_1292 = asSInt(_T_1291) node _T_1293 = eq(_T_1292, asSInt(UInt<1>(0h0))) node _T_1294 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<18>(0h2f000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1300 = cvt(_T_1299) node _T_1301 = and(_T_1300, asSInt(UInt<17>(0h10000))) node _T_1302 = asSInt(_T_1301) node _T_1303 = eq(_T_1302, asSInt(UInt<1>(0h0))) node _T_1304 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1305 = cvt(_T_1304) node _T_1306 = and(_T_1305, asSInt(UInt<13>(0h1000))) node _T_1307 = asSInt(_T_1306) node _T_1308 = eq(_T_1307, asSInt(UInt<1>(0h0))) node _T_1309 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1310 = cvt(_T_1309) node _T_1311 = and(_T_1310, asSInt(UInt<17>(0h10000))) node _T_1312 = asSInt(_T_1311) node _T_1313 = eq(_T_1312, asSInt(UInt<1>(0h0))) node _T_1314 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<27>(0h4000000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<19>(0h40000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<29>(0h10000000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = or(_T_1288, _T_1293) node _T_1335 = or(_T_1334, _T_1298) node _T_1336 = or(_T_1335, _T_1303) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1313) node _T_1339 = or(_T_1338, _T_1318) node _T_1340 = or(_T_1339, _T_1323) node _T_1341 = or(_T_1340, _T_1328) node _T_1342 = or(_T_1341, _T_1333) node _T_1343 = and(_T_1283, _T_1342) node _T_1344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<17>(0h10000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = and(_T_1344, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1343) node _T_1352 = or(_T_1351, _T_1350) node _T_1353 = and(_T_1279, _T_1352) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_41 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1363 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_44 node _T_1367 = eq(io.in.a.bits.mask, mask) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_45 node _T_1371 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1371 : node _T_1372 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1373 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1374 = and(_T_1372, _T_1373) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_1375 = shr(io.in.a.bits.source, 5) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_1381 = shr(io.in.a.bits.source, 5) node _T_1382 = eq(_T_1381, UInt<1>(0h1)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_1386 = and(_T_1384, _T_1385) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_1387 = shr(io.in.a.bits.source, 5) node _T_1388 = eq(_T_1387, UInt<2>(0h2)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_1393 = shr(io.in.a.bits.source, 5) node _T_1394 = eq(_T_1393, UInt<2>(0h3)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_1399 = shr(io.in.a.bits.source, 5) node _T_1400 = eq(_T_1399, UInt<3>(0h4)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_1405 = shr(io.in.a.bits.source, 5) node _T_1406 = eq(_T_1405, UInt<3>(0h5)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1410 = and(_T_1408, _T_1409) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1411 = shr(io.in.a.bits.source, 5) node _T_1412 = eq(_T_1411, UInt<3>(0h6)) node _T_1413 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1416 = and(_T_1414, _T_1415) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1417 = shr(io.in.a.bits.source, 5) node _T_1418 = eq(_T_1417, UInt<3>(0h7)) node _T_1419 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1422 = and(_T_1420, _T_1421) node _T_1423 = or(_T_1380, _T_1386) node _T_1424 = or(_T_1423, _T_1392) node _T_1425 = or(_T_1424, _T_1398) node _T_1426 = or(_T_1425, _T_1404) node _T_1427 = or(_T_1426, _T_1410) node _T_1428 = or(_T_1427, _T_1416) node _T_1429 = or(_T_1428, _T_1422) node _T_1430 = and(_T_1374, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1433 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = and(_T_1435, _T_1440) node _T_1442 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1443 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<14>(0h2000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<17>(0h10000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1454 = cvt(_T_1453) node _T_1455 = and(_T_1454, asSInt(UInt<18>(0h2f000))) node _T_1456 = asSInt(_T_1455) node _T_1457 = eq(_T_1456, asSInt(UInt<1>(0h0))) node _T_1458 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1459 = cvt(_T_1458) node _T_1460 = and(_T_1459, asSInt(UInt<17>(0h10000))) node _T_1461 = asSInt(_T_1460) node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) node _T_1463 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1464 = cvt(_T_1463) node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) node _T_1466 = asSInt(_T_1465) node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) node _T_1468 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1469 = cvt(_T_1468) node _T_1470 = and(_T_1469, asSInt(UInt<27>(0h4000000))) node _T_1471 = asSInt(_T_1470) node _T_1472 = eq(_T_1471, asSInt(UInt<1>(0h0))) node _T_1473 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1474 = cvt(_T_1473) node _T_1475 = and(_T_1474, asSInt(UInt<13>(0h1000))) node _T_1476 = asSInt(_T_1475) node _T_1477 = eq(_T_1476, asSInt(UInt<1>(0h0))) node _T_1478 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1479 = cvt(_T_1478) node _T_1480 = and(_T_1479, asSInt(UInt<19>(0h40000))) node _T_1481 = asSInt(_T_1480) node _T_1482 = eq(_T_1481, asSInt(UInt<1>(0h0))) node _T_1483 = or(_T_1447, _T_1452) node _T_1484 = or(_T_1483, _T_1457) node _T_1485 = or(_T_1484, _T_1462) node _T_1486 = or(_T_1485, _T_1467) node _T_1487 = or(_T_1486, _T_1472) node _T_1488 = or(_T_1487, _T_1477) node _T_1489 = or(_T_1488, _T_1482) node _T_1490 = and(_T_1442, _T_1489) node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h10000))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h10000000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1441) node _T_1508 = or(_T_1507, _T_1490) node _T_1509 = or(_T_1508, _T_1506) node _T_1510 = and(_T_1431, _T_1509) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_46 node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(source_ok, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(is_aligned, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1520 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_49 node _T_1524 = eq(io.in.a.bits.mask, mask) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_50 node _T_1528 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1532 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 5) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<1>(0h0)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 5) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<1>(0h1)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 5) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<2>(0h2)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 5) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<2>(0h3)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 5) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<3>(0h4)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h1f)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 5) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<3>(0h5)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h1f)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 5) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<3>(0h6)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_96 = shr(io.in.d.bits.source, 5) node _source_ok_T_97 = eq(_source_ok_T_96, UInt<3>(0h7)) node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98) node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_59 connect _source_ok_WIRE_1[1], _source_ok_T_65 connect _source_ok_WIRE_1[2], _source_ok_T_71 connect _source_ok_WIRE_1[3], _source_ok_T_77 connect _source_ok_WIRE_1[4], _source_ok_T_83 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_95 connect _source_ok_WIRE_1[7], _source_ok_T_101 node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1536 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1536 : node _T_1537 = asUInt(reset) node _T_1538 = eq(_T_1537, UInt<1>(0h0)) when _T_1538 : node _T_1539 = eq(source_ok_1, UInt<1>(0h0)) when _T_1539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1540 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(_T_1540, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1540, UInt<1>(0h1), "") : assert_54 node _T_1544 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_55 node _T_1548 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_56 node _T_1552 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_57 node _T_1556 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1556 : node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(source_ok_1, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(sink_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1563 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_60 node _T_1567 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_61 node _T_1571 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_62 node _T_1575 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_63 node _T_1579 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1580 = or(UInt<1>(0h1), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_64 node _T_1584 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1584 : node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(source_ok_1, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(sink_ok, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1591 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_67 node _T_1595 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_68 node _T_1599 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_69 node _T_1603 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1604 = or(_T_1603, io.in.d.bits.corrupt) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_70 node _T_1608 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1609 = or(UInt<1>(0h1), _T_1608) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_71 node _T_1613 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1613 : node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(source_ok_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1617 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_73 node _T_1621 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_74 node _T_1625 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1626 = or(UInt<1>(0h1), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_75 node _T_1630 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1630 : node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(source_ok_1, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1634 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(_T_1634, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1634, UInt<1>(0h1), "") : assert_77 node _T_1638 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1639 = or(_T_1638, io.in.d.bits.corrupt) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_78 node _T_1643 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1644 = or(UInt<1>(0h1), _T_1643) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_79 node _T_1648 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1648 : node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(source_ok_1, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1652 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(_T_1652, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1652, UInt<1>(0h1), "") : assert_81 node _T_1656 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_82 node _T_1660 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1661 = or(UInt<1>(0h1), _T_1660) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1665 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1669 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1673 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1677 = eq(a_first, UInt<1>(0h0)) node _T_1678 = and(io.in.a.valid, _T_1677) when _T_1678 : node _T_1679 = eq(io.in.a.bits.opcode, opcode) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_87 node _T_1683 = eq(io.in.a.bits.param, param) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_88 node _T_1687 = eq(io.in.a.bits.size, size) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_89 node _T_1691 = eq(io.in.a.bits.source, source) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_90 node _T_1695 = eq(io.in.a.bits.address, address) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_91 node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first) when _T_1700 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1701 = eq(d_first, UInt<1>(0h0)) node _T_1702 = and(io.in.d.valid, _T_1701) when _T_1702 : node _T_1703 = eq(io.in.d.bits.opcode, opcode_1) node _T_1704 = asUInt(reset) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) when _T_1705 : node _T_1706 = eq(_T_1703, UInt<1>(0h0)) when _T_1706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1703, UInt<1>(0h1), "") : assert_92 node _T_1707 = eq(io.in.d.bits.param, param_1) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_93 node _T_1711 = eq(io.in.d.bits.size, size_1) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_94 node _T_1715 = eq(io.in.d.bits.source, source_1) node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(_T_1715, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1715, UInt<1>(0h1), "") : assert_95 node _T_1719 = eq(io.in.d.bits.sink, sink) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_96 node _T_1723 = eq(io.in.d.bits.denied, denied) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_97 node _T_1727 = and(io.in.d.ready, io.in.d.valid) node _T_1728 = and(_T_1727, d_first) when _T_1728 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes : UInt<2048>, clock, reset, UInt<2048>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<256> connect a_set, UInt<256>(0h0) wire a_set_wo_ready : UInt<256> connect a_set_wo_ready, UInt<256>(0h0) wire a_opcodes_set : UInt<1024> connect a_opcodes_set, UInt<1024>(0h0) wire a_sizes_set : UInt<2048> connect a_sizes_set, UInt<2048>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1729 = and(io.in.a.valid, a_first_1) node _T_1730 = and(_T_1729, UInt<1>(0h1)) when _T_1730 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1731 = and(io.in.a.ready, io.in.a.valid) node _T_1732 = and(_T_1731, a_first_1) node _T_1733 = and(_T_1732, UInt<1>(0h1)) when _T_1733 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1734 = dshr(inflight, io.in.a.bits.source) node _T_1735 = bits(_T_1734, 0, 0) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<256> connect d_clr, UInt<256>(0h0) wire d_clr_wo_ready : UInt<256> connect d_clr_wo_ready, UInt<256>(0h0) wire d_opcodes_clr : UInt<1024> connect d_opcodes_clr, UInt<1024>(0h0) wire d_sizes_clr : UInt<2048> connect d_sizes_clr, UInt<2048>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1740 = and(io.in.d.valid, d_first_1) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = eq(d_release_ack, UInt<1>(0h0)) node _T_1743 = and(_T_1741, _T_1742) when _T_1743 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1744 = and(io.in.d.ready, io.in.d.valid) node _T_1745 = and(_T_1744, d_first_1) node _T_1746 = and(_T_1745, UInt<1>(0h1)) node _T_1747 = eq(d_release_ack, UInt<1>(0h0)) node _T_1748 = and(_T_1746, _T_1747) when _T_1748 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1749 = and(io.in.d.valid, d_first_1) node _T_1750 = and(_T_1749, UInt<1>(0h1)) node _T_1751 = eq(d_release_ack, UInt<1>(0h0)) node _T_1752 = and(_T_1750, _T_1751) when _T_1752 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1753 = dshr(inflight, io.in.d.bits.source) node _T_1754 = bits(_T_1753, 0, 0) node _T_1755 = or(_T_1754, same_cycle_resp) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1759 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1760 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = asUInt(reset) node _T_1763 = eq(_T_1762, UInt<1>(0h0)) when _T_1763 : node _T_1764 = eq(_T_1761, UInt<1>(0h0)) when _T_1764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1761, UInt<1>(0h1), "") : assert_100 node _T_1765 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_101 else : node _T_1769 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1770 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_102 node _T_1775 = eq(io.in.d.bits.size, a_size_lookup) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_103 node _T_1779 = and(io.in.d.valid, d_first_1) node _T_1780 = and(_T_1779, a_first_1) node _T_1781 = and(_T_1780, io.in.a.valid) node _T_1782 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1783 = and(_T_1781, _T_1782) node _T_1784 = eq(d_release_ack, UInt<1>(0h0)) node _T_1785 = and(_T_1783, _T_1784) when _T_1785 : node _T_1786 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1787 = or(_T_1786, io.in.a.ready) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_104 node _T_1791 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1792 = orr(a_set_wo_ready) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = or(_T_1791, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_10 node _T_1798 = orr(inflight) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1801 = or(_T_1799, _T_1800) node _T_1802 = lt(watchdog, plusarg_reader.out) node _T_1803 = or(_T_1801, _T_1802) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1807 = and(io.in.a.ready, io.in.a.valid) node _T_1808 = and(io.in.d.ready, io.in.d.valid) node _T_1809 = or(_T_1807, _T_1808) when _T_1809 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes_1 : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes_1 : UInt<2048>, clock, reset, UInt<2048>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<256> connect c_set, UInt<256>(0h0) wire c_set_wo_ready : UInt<256> connect c_set_wo_ready, UInt<256>(0h0) wire c_opcodes_set : UInt<1024> connect c_opcodes_set, UInt<1024>(0h0) wire c_sizes_set : UInt<2048> connect c_sizes_set, UInt<2048>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1810 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1811 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1812 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1813 = and(_T_1811, _T_1812) node _T_1814 = and(_T_1810, _T_1813) when _T_1814 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1815 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1816 = and(_T_1815, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1817 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1818 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = and(_T_1816, _T_1819) when _T_1820 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1821 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1822 = bits(_T_1821, 0, 0) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(_T_1823, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1823, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<256> connect d_clr_1, UInt<256>(0h0) wire d_clr_wo_ready_1 : UInt<256> connect d_clr_wo_ready_1, UInt<256>(0h0) wire d_opcodes_clr_1 : UInt<1024> connect d_opcodes_clr_1, UInt<1024>(0h0) wire d_sizes_clr_1 : UInt<2048> connect d_sizes_clr_1, UInt<2048>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1827 = and(io.in.d.valid, d_first_2) node _T_1828 = and(_T_1827, UInt<1>(0h1)) node _T_1829 = and(_T_1828, d_release_ack_1) when _T_1829 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1830 = and(io.in.d.ready, io.in.d.valid) node _T_1831 = and(_T_1830, d_first_2) node _T_1832 = and(_T_1831, UInt<1>(0h1)) node _T_1833 = and(_T_1832, d_release_ack_1) when _T_1833 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1834 = and(io.in.d.valid, d_first_2) node _T_1835 = and(_T_1834, UInt<1>(0h1)) node _T_1836 = and(_T_1835, d_release_ack_1) when _T_1836 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1837 = dshr(inflight_1, io.in.d.bits.source) node _T_1838 = bits(_T_1837, 0, 0) node _T_1839 = or(_T_1838, same_cycle_resp_1) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1843 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_109 else : node _T_1847 = eq(io.in.d.bits.size, c_size_lookup) node _T_1848 = asUInt(reset) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) when _T_1849 : node _T_1850 = eq(_T_1847, UInt<1>(0h0)) when _T_1850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1847, UInt<1>(0h1), "") : assert_110 node _T_1851 = and(io.in.d.valid, d_first_2) node _T_1852 = and(_T_1851, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1853 = and(_T_1852, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1854 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1855 = and(_T_1853, _T_1854) node _T_1856 = and(_T_1855, d_release_ack_1) node _T_1857 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1858 = and(_T_1856, _T_1857) when _T_1858 : node _T_1859 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1860 = or(_T_1859, _WIRE_23.ready) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_111 node _T_1864 = orr(c_set_wo_ready) when _T_1864 : node _T_1865 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_11 node _T_1869 = orr(inflight_1) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) node _T_1871 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1872 = or(_T_1870, _T_1871) node _T_1873 = lt(watchdog_1, plusarg_reader_1.out) node _T_1874 = or(_T_1872, _T_1873) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1878 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1879 = and(io.in.d.ready, io.in.d.valid) node _T_1880 = or(_T_1878, _T_1879) when _T_1880 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [255:0] inflight; // @[Monitor.scala:614:27] reg [1023:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2047:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [255:0] inflight_1; // @[Monitor.scala:726:35] reg [2047:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Directory_5 : input clock : Clock input reset : Reset output io : { flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, flip read : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>}}, result : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, ready : UInt<1>} smem cc_dir : UInt<13>[16] [2048] inst write_q of Queue1_DirectoryWrite_5 connect write_q.clock, clock connect write_q.reset, reset connect write_q.io.enq.valid, io.write.valid connect write_q.io.enq.bits.data.tag, io.write.bits.data.tag connect write_q.io.enq.bits.data.clients, io.write.bits.data.clients connect write_q.io.enq.bits.data.state, io.write.bits.data.state connect write_q.io.enq.bits.data.dirty, io.write.bits.data.dirty connect write_q.io.enq.bits.way, io.write.bits.way connect write_q.io.enq.bits.set, io.write.bits.set connect io.write.ready, write_q.io.enq.ready regreset wipeCount : UInt<12>, clock, reset, UInt<12>(0h0) regreset wipeOff : UInt<1>, clock, reset, UInt<1>(0h1) connect wipeOff, UInt<1>(0h0) node wipeDone = bits(wipeCount, 11, 11) node wipeSet = bits(wipeCount, 10, 0) connect io.ready, wipeDone node _T = eq(wipeDone, UInt<1>(0h0)) node _T_1 = eq(wipeOff, UInt<1>(0h0)) node _T_2 = and(_T, _T_1) when _T_2 : node _wipeCount_T = add(wipeCount, UInt<1>(0h1)) node _wipeCount_T_1 = tail(_wipeCount_T, 1) connect wipeCount, _wipeCount_T_1 node _T_3 = eq(io.read.valid, UInt<1>(0h0)) node _T_4 = or(wipeDone, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:86 assert (wipeDone \|\| !io.read.valid)\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _wen_T = eq(wipeDone, UInt<1>(0h0)) node _wen_T_1 = eq(wipeOff, UInt<1>(0h0)) node _wen_T_2 = and(_wen_T, _wen_T_1) node wen = or(_wen_T_2, write_q.io.deq.valid) node _T_8 = eq(io.read.valid, UInt<1>(0h0)) node _T_9 = or(_T_8, wipeDone) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:91 assert (!io.read.valid \|\| wipeDone)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 node _q_io_deq_ready_T = eq(io.read.valid, UInt<1>(0h0)) connect write_q.io.deq.ready, _q_io_deq_ready_T node _T_13 = eq(io.read.valid, UInt<1>(0h0)) node _T_14 = and(_T_13, wen) when _T_14 : node _T_15 = mux(wipeDone, write_q.io.deq.bits.set, wipeSet) node lo = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_16 = cat(hi, lo) node _T_17 = mux(wipeDone, _T_16, UInt<1>(0h0)) node lo_1 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_1 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_18 = cat(hi_1, lo_1) node _T_19 = mux(wipeDone, _T_18, UInt<1>(0h0)) node lo_2 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_2 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_20 = cat(hi_2, lo_2) node _T_21 = mux(wipeDone, _T_20, UInt<1>(0h0)) node lo_3 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_3 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_22 = cat(hi_3, lo_3) node _T_23 = mux(wipeDone, _T_22, UInt<1>(0h0)) node lo_4 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_4 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_24 = cat(hi_4, lo_4) node _T_25 = mux(wipeDone, _T_24, UInt<1>(0h0)) node lo_5 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_5 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_26 = cat(hi_5, lo_5) node _T_27 = mux(wipeDone, _T_26, UInt<1>(0h0)) node lo_6 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_6 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_28 = cat(hi_6, lo_6) node _T_29 = mux(wipeDone, _T_28, UInt<1>(0h0)) node lo_7 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_7 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_30 = cat(hi_7, lo_7) node _T_31 = mux(wipeDone, _T_30, UInt<1>(0h0)) node lo_8 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_8 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_32 = cat(hi_8, lo_8) node _T_33 = mux(wipeDone, _T_32, UInt<1>(0h0)) node lo_9 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_9 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_34 = cat(hi_9, lo_9) node _T_35 = mux(wipeDone, _T_34, UInt<1>(0h0)) node lo_10 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_10 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_36 = cat(hi_10, lo_10) node _T_37 = mux(wipeDone, _T_36, UInt<1>(0h0)) node lo_11 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_11 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_38 = cat(hi_11, lo_11) node _T_39 = mux(wipeDone, _T_38, UInt<1>(0h0)) node lo_12 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_12 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_40 = cat(hi_12, lo_12) node _T_41 = mux(wipeDone, _T_40, UInt<1>(0h0)) node lo_13 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_13 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_42 = cat(hi_13, lo_13) node _T_43 = mux(wipeDone, _T_42, UInt<1>(0h0)) node lo_14 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_14 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_44 = cat(hi_14, lo_14) node _T_45 = mux(wipeDone, _T_44, UInt<1>(0h0)) node lo_15 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_15 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_46 = cat(hi_15, lo_15) node _T_47 = mux(wipeDone, _T_46, UInt<1>(0h0)) wire _WIRE : UInt<13>[16] connect _WIRE[0], _T_17 connect _WIRE[1], _T_19 connect _WIRE[2], _T_21 connect _WIRE[3], _T_23 connect _WIRE[4], _T_25 connect _WIRE[5], _T_27 connect _WIRE[6], _T_29 connect _WIRE[7], _T_31 connect _WIRE[8], _T_33 connect _WIRE[9], _T_35 connect _WIRE[10], _T_37 connect _WIRE[11], _T_39 connect _WIRE[12], _T_41 connect _WIRE[13], _T_43 connect _WIRE[14], _T_45 connect _WIRE[15], _T_47 node shiftAmount = bits(write_q.io.deq.bits.way, 3, 0) node _T_48 = dshl(UInt<1>(0h1), shiftAmount) node _T_49 = bits(_T_48, 15, 0) node _T_50 = bits(_T_49, 0, 0) node _T_51 = bits(_T_49, 1, 1) node _T_52 = bits(_T_49, 2, 2) node _T_53 = bits(_T_49, 3, 3) node _T_54 = bits(_T_49, 4, 4) node _T_55 = bits(_T_49, 5, 5) node _T_56 = bits(_T_49, 6, 6) node _T_57 = bits(_T_49, 7, 7) node _T_58 = bits(_T_49, 8, 8) node _T_59 = bits(_T_49, 9, 9) node _T_60 = bits(_T_49, 10, 10) node _T_61 = bits(_T_49, 11, 11) node _T_62 = bits(_T_49, 12, 12) node _T_63 = bits(_T_49, 13, 13) node _T_64 = bits(_T_49, 14, 14) node _T_65 = bits(_T_49, 15, 15) node _T_66 = eq(wipeDone, UInt<1>(0h0)) node _T_67 = or(_T_50, _T_66) node _T_68 = eq(wipeDone, UInt<1>(0h0)) node _T_69 = or(_T_51, _T_68) node _T_70 = eq(wipeDone, UInt<1>(0h0)) node _T_71 = or(_T_52, _T_70) node _T_72 = eq(wipeDone, UInt<1>(0h0)) node _T_73 = or(_T_53, _T_72) node _T_74 = eq(wipeDone, UInt<1>(0h0)) node _T_75 = or(_T_54, _T_74) node _T_76 = eq(wipeDone, UInt<1>(0h0)) node _T_77 = or(_T_55, _T_76) node _T_78 = eq(wipeDone, UInt<1>(0h0)) node _T_79 = or(_T_56, _T_78) node _T_80 = eq(wipeDone, UInt<1>(0h0)) node _T_81 = or(_T_57, _T_80) node _T_82 = eq(wipeDone, UInt<1>(0h0)) node _T_83 = or(_T_58, _T_82) node _T_84 = eq(wipeDone, UInt<1>(0h0)) node _T_85 = or(_T_59, _T_84) node _T_86 = eq(wipeDone, UInt<1>(0h0)) node _T_87 = or(_T_60, _T_86) node _T_88 = eq(wipeDone, UInt<1>(0h0)) node _T_89 = or(_T_61, _T_88) node _T_90 = eq(wipeDone, UInt<1>(0h0)) node _T_91 = or(_T_62, _T_90) node _T_92 = eq(wipeDone, UInt<1>(0h0)) node _T_93 = or(_T_63, _T_92) node _T_94 = eq(wipeDone, UInt<1>(0h0)) node _T_95 = or(_T_64, _T_94) node _T_96 = eq(wipeDone, UInt<1>(0h0)) node _T_97 = or(_T_65, _T_96) write mport MPORT = cc_dir[_T_15], clock when _T_67 : connect MPORT[0], _WIRE[0] when _T_69 : connect MPORT[1], _WIRE[1] when _T_71 : connect MPORT[2], _WIRE[2] when _T_73 : connect MPORT[3], _WIRE[3] when _T_75 : connect MPORT[4], _WIRE[4] when _T_77 : connect MPORT[5], _WIRE[5] when _T_79 : connect MPORT[6], _WIRE[6] when _T_81 : connect MPORT[7], _WIRE[7] when _T_83 : connect MPORT[8], _WIRE[8] when _T_85 : connect MPORT[9], _WIRE[9] when _T_87 : connect MPORT[10], _WIRE[10] when _T_89 : connect MPORT[11], _WIRE[11] when _T_91 : connect MPORT[12], _WIRE[12] when _T_93 : connect MPORT[13], _WIRE[13] when _T_95 : connect MPORT[14], _WIRE[14] when _T_97 : connect MPORT[15], _WIRE[15] regreset ren1 : UInt<1>, clock, reset, UInt<1>(0h0) connect ren1, ren1 connect ren1, io.read.valid node _bypass_T = and(ren1, write_q.io.deq.valid) wire _regout_WIRE : UInt<11> invalidate _regout_WIRE when io.read.valid : connect _regout_WIRE, io.read.bits.set read mport regout = cc_dir[_regout_WIRE], clock reg tag : UInt<9>, clock when io.read.valid : connect tag, io.read.bits.tag reg set : UInt<11>, clock when io.read.valid : connect set, io.read.bits.set inst victimLFSR_prng of MaxPeriodFibonacciLFSR_5 connect victimLFSR_prng.clock, clock connect victimLFSR_prng.reset, reset connect victimLFSR_prng.io.seed.valid, UInt<1>(0h0) invalidate victimLFSR_prng.io.seed.bits[0] invalidate victimLFSR_prng.io.seed.bits[1] invalidate victimLFSR_prng.io.seed.bits[2] invalidate victimLFSR_prng.io.seed.bits[3] invalidate victimLFSR_prng.io.seed.bits[4] invalidate victimLFSR_prng.io.seed.bits[5] invalidate victimLFSR_prng.io.seed.bits[6] invalidate victimLFSR_prng.io.seed.bits[7] invalidate victimLFSR_prng.io.seed.bits[8] invalidate victimLFSR_prng.io.seed.bits[9] invalidate victimLFSR_prng.io.seed.bits[10] invalidate victimLFSR_prng.io.seed.bits[11] invalidate victimLFSR_prng.io.seed.bits[12] invalidate victimLFSR_prng.io.seed.bits[13] invalidate victimLFSR_prng.io.seed.bits[14] invalidate victimLFSR_prng.io.seed.bits[15] connect victimLFSR_prng.io.increment, io.read.valid node victimLFSR_lo_lo_lo = cat(victimLFSR_prng.io.out[1], victimLFSR_prng.io.out[0]) node victimLFSR_lo_lo_hi = cat(victimLFSR_prng.io.out[3], victimLFSR_prng.io.out[2]) node victimLFSR_lo_lo = cat(victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo) node victimLFSR_lo_hi_lo = cat(victimLFSR_prng.io.out[5], victimLFSR_prng.io.out[4]) node victimLFSR_lo_hi_hi = cat(victimLFSR_prng.io.out[7], victimLFSR_prng.io.out[6]) node victimLFSR_lo_hi = cat(victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo) node victimLFSR_lo = cat(victimLFSR_lo_hi, victimLFSR_lo_lo) node victimLFSR_hi_lo_lo = cat(victimLFSR_prng.io.out[9], victimLFSR_prng.io.out[8]) node victimLFSR_hi_lo_hi = cat(victimLFSR_prng.io.out[11], victimLFSR_prng.io.out[10]) node victimLFSR_hi_lo = cat(victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo) node victimLFSR_hi_hi_lo = cat(victimLFSR_prng.io.out[13], victimLFSR_prng.io.out[12]) node victimLFSR_hi_hi_hi = cat(victimLFSR_prng.io.out[15], victimLFSR_prng.io.out[14]) node victimLFSR_hi_hi = cat(victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo) node victimLFSR_hi = cat(victimLFSR_hi_hi, victimLFSR_hi_lo) node _victimLFSR_T = cat(victimLFSR_hi, victimLFSR_lo) node victimLFSR = bits(_victimLFSR_T, 9, 0) node _victimLTE_T = leq(UInt<1>(0h0), victimLFSR) node _victimLTE_T_1 = leq(UInt<7>(0h40), victimLFSR) node _victimLTE_T_2 = leq(UInt<8>(0h80), victimLFSR) node _victimLTE_T_3 = leq(UInt<8>(0hc0), victimLFSR) node _victimLTE_T_4 = leq(UInt<9>(0h100), victimLFSR) node _victimLTE_T_5 = leq(UInt<9>(0h140), victimLFSR) node _victimLTE_T_6 = leq(UInt<9>(0h180), victimLFSR) node _victimLTE_T_7 = leq(UInt<9>(0h1c0), victimLFSR) node _victimLTE_T_8 = leq(UInt<10>(0h200), victimLFSR) node _victimLTE_T_9 = leq(UInt<10>(0h240), victimLFSR) node _victimLTE_T_10 = leq(UInt<10>(0h280), victimLFSR) node _victimLTE_T_11 = leq(UInt<10>(0h2c0), victimLFSR) node _victimLTE_T_12 = leq(UInt<10>(0h300), victimLFSR) node _victimLTE_T_13 = leq(UInt<10>(0h340), victimLFSR) node _victimLTE_T_14 = leq(UInt<10>(0h380), victimLFSR) node _victimLTE_T_15 = leq(UInt<10>(0h3c0), victimLFSR) node victimLTE_lo_lo_lo = cat(_victimLTE_T_1, _victimLTE_T) node victimLTE_lo_lo_hi = cat(_victimLTE_T_3, _victimLTE_T_2) node victimLTE_lo_lo = cat(victimLTE_lo_lo_hi, victimLTE_lo_lo_lo) node victimLTE_lo_hi_lo = cat(_victimLTE_T_5, _victimLTE_T_4) node victimLTE_lo_hi_hi = cat(_victimLTE_T_7, _victimLTE_T_6) node victimLTE_lo_hi = cat(victimLTE_lo_hi_hi, victimLTE_lo_hi_lo) node victimLTE_lo = cat(victimLTE_lo_hi, victimLTE_lo_lo) node victimLTE_hi_lo_lo = cat(_victimLTE_T_9, _victimLTE_T_8) node victimLTE_hi_lo_hi = cat(_victimLTE_T_11, _victimLTE_T_10) node victimLTE_hi_lo = cat(victimLTE_hi_lo_hi, victimLTE_hi_lo_lo) node victimLTE_hi_hi_lo = cat(_victimLTE_T_13, _victimLTE_T_12) node victimLTE_hi_hi_hi = cat(_victimLTE_T_15, _victimLTE_T_14) node victimLTE_hi_hi = cat(victimLTE_hi_hi_hi, victimLTE_hi_hi_lo) node victimLTE_hi = cat(victimLTE_hi_hi, victimLTE_hi_lo) node victimLTE = cat(victimLTE_hi, victimLTE_lo) node _victimSimp_T = bits(victimLTE, 15, 1) node victimSimp_hi = cat(UInt<1>(0h0), _victimSimp_T) node victimSimp = cat(victimSimp_hi, UInt<1>(0h1)) node _victimWayOH_T = bits(victimSimp, 15, 0) node _victimWayOH_T_1 = shr(victimSimp, 1) node _victimWayOH_T_2 = not(_victimWayOH_T_1) node victimWayOH = and(_victimWayOH_T, _victimWayOH_T_2) node victimWay_hi = bits(victimWayOH, 15, 8) node victimWay_lo = bits(victimWayOH, 7, 0) node _victimWay_T = orr(victimWay_hi) node _victimWay_T_1 = or(victimWay_hi, victimWay_lo) node victimWay_hi_1 = bits(_victimWay_T_1, 7, 4) node victimWay_lo_1 = bits(_victimWay_T_1, 3, 0) node _victimWay_T_2 = orr(victimWay_hi_1) node _victimWay_T_3 = or(victimWay_hi_1, victimWay_lo_1) node victimWay_hi_2 = bits(_victimWay_T_3, 3, 2) node victimWay_lo_2 = bits(_victimWay_T_3, 1, 0) node _victimWay_T_4 = orr(victimWay_hi_2) node _victimWay_T_5 = or(victimWay_hi_2, victimWay_lo_2) node _victimWay_T_6 = bits(_victimWay_T_5, 1, 1) node _victimWay_T_7 = cat(_victimWay_T_4, _victimWay_T_6) node _victimWay_T_8 = cat(_victimWay_T_2, _victimWay_T_7) node victimWay = cat(_victimWay_T, _victimWay_T_8) node _T_98 = eq(ren1, UInt<1>(0h0)) node _T_99 = bits(victimLTE, 0, 0) node _T_100 = eq(_T_99, UInt<1>(0h1)) node _T_101 = or(_T_98, _T_100) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:121 assert (!ren2 \|\| victimLTE(0) === 1.U)\n") : printf_2 assert(clock, _T_101, UInt<1>(0h1), "") : assert_2 node _T_105 = eq(ren1, UInt<1>(0h0)) node _T_106 = shr(victimSimp, 1) node _T_107 = not(victimSimp) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = or(_T_105, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:122 assert (!ren2 \|\| ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone\n") : printf_3 assert(clock, _T_110, UInt<1>(0h1), "") : assert_3 node _T_114 = eq(ren1, UInt<1>(0h0)) node _T_115 = bits(victimWayOH, 0, 0) node _T_116 = bits(victimWayOH, 1, 1) node _T_117 = bits(victimWayOH, 2, 2) node _T_118 = bits(victimWayOH, 3, 3) node _T_119 = bits(victimWayOH, 4, 4) node _T_120 = bits(victimWayOH, 5, 5) node _T_121 = bits(victimWayOH, 6, 6) node _T_122 = bits(victimWayOH, 7, 7) node _T_123 = bits(victimWayOH, 8, 8) node _T_124 = bits(victimWayOH, 9, 9) node _T_125 = bits(victimWayOH, 10, 10) node _T_126 = bits(victimWayOH, 11, 11) node _T_127 = bits(victimWayOH, 12, 12) node _T_128 = bits(victimWayOH, 13, 13) node _T_129 = bits(victimWayOH, 14, 14) node _T_130 = bits(victimWayOH, 15, 15) node _T_131 = add(_T_115, _T_116) node _T_132 = bits(_T_131, 1, 0) node _T_133 = add(_T_117, _T_118) node _T_134 = bits(_T_133, 1, 0) node _T_135 = add(_T_132, _T_134) node _T_136 = bits(_T_135, 2, 0) node _T_137 = add(_T_119, _T_120) node _T_138 = bits(_T_137, 1, 0) node _T_139 = add(_T_121, _T_122) node _T_140 = bits(_T_139, 1, 0) node _T_141 = add(_T_138, _T_140) node _T_142 = bits(_T_141, 2, 0) node _T_143 = add(_T_136, _T_142) node _T_144 = bits(_T_143, 3, 0) node _T_145 = add(_T_123, _T_124) node _T_146 = bits(_T_145, 1, 0) node _T_147 = add(_T_125, _T_126) node _T_148 = bits(_T_147, 1, 0) node _T_149 = add(_T_146, _T_148) node _T_150 = bits(_T_149, 2, 0) node _T_151 = add(_T_127, _T_128) node _T_152 = bits(_T_151, 1, 0) node _T_153 = add(_T_129, _T_130) node _T_154 = bits(_T_153, 1, 0) node _T_155 = add(_T_152, _T_154) node _T_156 = bits(_T_155, 2, 0) node _T_157 = add(_T_150, _T_156) node _T_158 = bits(_T_157, 3, 0) node _T_159 = add(_T_144, _T_158) node _T_160 = bits(_T_159, 4, 0) node _T_161 = eq(_T_160, UInt<1>(0h1)) node _T_162 = or(_T_114, _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:123 assert (!ren2 \|\| PopCount(victimWayOH) === 1.U)\n") : printf_4 assert(clock, _T_162, UInt<1>(0h1), "") : assert_4 node _setQuash_T = eq(write_q.io.deq.bits.set, set) node setQuash = and(write_q.io.deq.valid, _setQuash_T) node tagMatch = eq(write_q.io.deq.bits.data.tag, tag) node wayMatch = eq(write_q.io.deq.bits.way, victimWay) wire ways_0 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE : UInt<13> connect _ways_WIRE, regout[0] node _ways_T = bits(_ways_WIRE, 8, 0) connect ways_0.tag, _ways_T node _ways_T_1 = bits(_ways_WIRE, 9, 9) connect ways_0.clients, _ways_T_1 node _ways_T_2 = bits(_ways_WIRE, 11, 10) connect ways_0.state, _ways_T_2 node _ways_T_3 = bits(_ways_WIRE, 12, 12) connect ways_0.dirty, _ways_T_3 wire ways_1 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_1 : UInt<13> connect _ways_WIRE_1, regout[1] node _ways_T_4 = bits(_ways_WIRE_1, 8, 0) connect ways_1.tag, _ways_T_4 node _ways_T_5 = bits(_ways_WIRE_1, 9, 9) connect ways_1.clients, _ways_T_5 node _ways_T_6 = bits(_ways_WIRE_1, 11, 10) connect ways_1.state, _ways_T_6 node _ways_T_7 = bits(_ways_WIRE_1, 12, 12) connect ways_1.dirty, _ways_T_7 wire ways_2 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_2 : UInt<13> connect _ways_WIRE_2, regout[2] node _ways_T_8 = bits(_ways_WIRE_2, 8, 0) connect ways_2.tag, _ways_T_8 node _ways_T_9 = bits(_ways_WIRE_2, 9, 9) connect ways_2.clients, _ways_T_9 node _ways_T_10 = bits(_ways_WIRE_2, 11, 10) connect ways_2.state, _ways_T_10 node _ways_T_11 = bits(_ways_WIRE_2, 12, 12) connect ways_2.dirty, _ways_T_11 wire ways_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_3 : UInt<13> connect _ways_WIRE_3, regout[3] node _ways_T_12 = bits(_ways_WIRE_3, 8, 0) connect ways_3.tag, _ways_T_12 node _ways_T_13 = bits(_ways_WIRE_3, 9, 9) connect ways_3.clients, _ways_T_13 node _ways_T_14 = bits(_ways_WIRE_3, 11, 10) connect ways_3.state, _ways_T_14 node _ways_T_15 = bits(_ways_WIRE_3, 12, 12) connect ways_3.dirty, _ways_T_15 wire ways_4 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_4 : UInt<13> connect _ways_WIRE_4, regout[4] node _ways_T_16 = bits(_ways_WIRE_4, 8, 0) connect ways_4.tag, _ways_T_16 node _ways_T_17 = bits(_ways_WIRE_4, 9, 9) connect ways_4.clients, _ways_T_17 node _ways_T_18 = bits(_ways_WIRE_4, 11, 10) connect ways_4.state, _ways_T_18 node _ways_T_19 = bits(_ways_WIRE_4, 12, 12) connect ways_4.dirty, _ways_T_19 wire ways_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_5 : UInt<13> connect _ways_WIRE_5, regout[5] node _ways_T_20 = bits(_ways_WIRE_5, 8, 0) connect ways_5.tag, _ways_T_20 node _ways_T_21 = bits(_ways_WIRE_5, 9, 9) connect ways_5.clients, _ways_T_21 node _ways_T_22 = bits(_ways_WIRE_5, 11, 10) connect ways_5.state, _ways_T_22 node _ways_T_23 = bits(_ways_WIRE_5, 12, 12) connect ways_5.dirty, _ways_T_23 wire ways_6 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_6 : UInt<13> connect _ways_WIRE_6, regout[6] node _ways_T_24 = bits(_ways_WIRE_6, 8, 0) connect ways_6.tag, _ways_T_24 node _ways_T_25 = bits(_ways_WIRE_6, 9, 9) connect ways_6.clients, _ways_T_25 node _ways_T_26 = bits(_ways_WIRE_6, 11, 10) connect ways_6.state, _ways_T_26 node _ways_T_27 = bits(_ways_WIRE_6, 12, 12) connect ways_6.dirty, _ways_T_27 wire ways_7 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_7 : UInt<13> connect _ways_WIRE_7, regout[7] node _ways_T_28 = bits(_ways_WIRE_7, 8, 0) connect ways_7.tag, _ways_T_28 node _ways_T_29 = bits(_ways_WIRE_7, 9, 9) connect ways_7.clients, _ways_T_29 node _ways_T_30 = bits(_ways_WIRE_7, 11, 10) connect ways_7.state, _ways_T_30 node _ways_T_31 = bits(_ways_WIRE_7, 12, 12) connect ways_7.dirty, _ways_T_31 wire ways_8 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_8 : UInt<13> connect _ways_WIRE_8, regout[8] node _ways_T_32 = bits(_ways_WIRE_8, 8, 0) connect ways_8.tag, _ways_T_32 node _ways_T_33 = bits(_ways_WIRE_8, 9, 9) connect ways_8.clients, _ways_T_33 node _ways_T_34 = bits(_ways_WIRE_8, 11, 10) connect ways_8.state, _ways_T_34 node _ways_T_35 = bits(_ways_WIRE_8, 12, 12) connect ways_8.dirty, _ways_T_35 wire ways_9 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_9 : UInt<13> connect _ways_WIRE_9, regout[9] node _ways_T_36 = bits(_ways_WIRE_9, 8, 0) connect ways_9.tag, _ways_T_36 node _ways_T_37 = bits(_ways_WIRE_9, 9, 9) connect ways_9.clients, _ways_T_37 node _ways_T_38 = bits(_ways_WIRE_9, 11, 10) connect ways_9.state, _ways_T_38 node _ways_T_39 = bits(_ways_WIRE_9, 12, 12) connect ways_9.dirty, _ways_T_39 wire ways_10 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_10 : UInt<13> connect _ways_WIRE_10, regout[10] node _ways_T_40 = bits(_ways_WIRE_10, 8, 0) connect ways_10.tag, _ways_T_40 node _ways_T_41 = bits(_ways_WIRE_10, 9, 9) connect ways_10.clients, _ways_T_41 node _ways_T_42 = bits(_ways_WIRE_10, 11, 10) connect ways_10.state, _ways_T_42 node _ways_T_43 = bits(_ways_WIRE_10, 12, 12) connect ways_10.dirty, _ways_T_43 wire ways_11 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_11 : UInt<13> connect _ways_WIRE_11, regout[11] node _ways_T_44 = bits(_ways_WIRE_11, 8, 0) connect ways_11.tag, _ways_T_44 node _ways_T_45 = bits(_ways_WIRE_11, 9, 9) connect ways_11.clients, _ways_T_45 node _ways_T_46 = bits(_ways_WIRE_11, 11, 10) connect ways_11.state, _ways_T_46 node _ways_T_47 = bits(_ways_WIRE_11, 12, 12) connect ways_11.dirty, _ways_T_47 wire ways_12 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_12 : UInt<13> connect _ways_WIRE_12, regout[12] node _ways_T_48 = bits(_ways_WIRE_12, 8, 0) connect ways_12.tag, _ways_T_48 node _ways_T_49 = bits(_ways_WIRE_12, 9, 9) connect ways_12.clients, _ways_T_49 node _ways_T_50 = bits(_ways_WIRE_12, 11, 10) connect ways_12.state, _ways_T_50 node _ways_T_51 = bits(_ways_WIRE_12, 12, 12) connect ways_12.dirty, _ways_T_51 wire ways_13 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_13 : UInt<13> connect _ways_WIRE_13, regout[13] node _ways_T_52 = bits(_ways_WIRE_13, 8, 0) connect ways_13.tag, _ways_T_52 node _ways_T_53 = bits(_ways_WIRE_13, 9, 9) connect ways_13.clients, _ways_T_53 node _ways_T_54 = bits(_ways_WIRE_13, 11, 10) connect ways_13.state, _ways_T_54 node _ways_T_55 = bits(_ways_WIRE_13, 12, 12) connect ways_13.dirty, _ways_T_55 wire ways_14 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_14 : UInt<13> connect _ways_WIRE_14, regout[14] node _ways_T_56 = bits(_ways_WIRE_14, 8, 0) connect ways_14.tag, _ways_T_56 node _ways_T_57 = bits(_ways_WIRE_14, 9, 9) connect ways_14.clients, _ways_T_57 node _ways_T_58 = bits(_ways_WIRE_14, 11, 10) connect ways_14.state, _ways_T_58 node _ways_T_59 = bits(_ways_WIRE_14, 12, 12) connect ways_14.dirty, _ways_T_59 wire ways_15 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_15 : UInt<13> connect _ways_WIRE_15, regout[15] node _ways_T_60 = bits(_ways_WIRE_15, 8, 0) connect ways_15.tag, _ways_T_60 node _ways_T_61 = bits(_ways_WIRE_15, 9, 9) connect ways_15.clients, _ways_T_61 node _ways_T_62 = bits(_ways_WIRE_15, 11, 10) connect ways_15.state, _ways_T_62 node _ways_T_63 = bits(_ways_WIRE_15, 12, 12) connect ways_15.dirty, _ways_T_63 node _hits_T = eq(ways_0.tag, tag) node _hits_T_1 = neq(ways_0.state, UInt<2>(0h0)) node _hits_T_2 = and(_hits_T, _hits_T_1) node _hits_T_3 = eq(setQuash, UInt<1>(0h0)) node _hits_T_4 = neq(UInt<1>(0h0), write_q.io.deq.bits.way) node _hits_T_5 = or(_hits_T_3, _hits_T_4) node _hits_T_6 = and(_hits_T_2, _hits_T_5) node _hits_T_7 = eq(ways_1.tag, tag) node _hits_T_8 = neq(ways_1.state, UInt<2>(0h0)) node _hits_T_9 = and(_hits_T_7, _hits_T_8) node _hits_T_10 = eq(setQuash, UInt<1>(0h0)) node _hits_T_11 = neq(UInt<1>(0h1), write_q.io.deq.bits.way) node _hits_T_12 = or(_hits_T_10, _hits_T_11) node _hits_T_13 = and(_hits_T_9, _hits_T_12) node _hits_T_14 = eq(ways_2.tag, tag) node _hits_T_15 = neq(ways_2.state, UInt<2>(0h0)) node _hits_T_16 = and(_hits_T_14, _hits_T_15) node _hits_T_17 = eq(setQuash, UInt<1>(0h0)) node _hits_T_18 = neq(UInt<2>(0h2), write_q.io.deq.bits.way) node _hits_T_19 = or(_hits_T_17, _hits_T_18) node _hits_T_20 = and(_hits_T_16, _hits_T_19) node _hits_T_21 = eq(ways_3.tag, tag) node _hits_T_22 = neq(ways_3.state, UInt<2>(0h0)) node _hits_T_23 = and(_hits_T_21, _hits_T_22) node _hits_T_24 = eq(setQuash, UInt<1>(0h0)) node _hits_T_25 = neq(UInt<2>(0h3), write_q.io.deq.bits.way) node _hits_T_26 = or(_hits_T_24, _hits_T_25) node _hits_T_27 = and(_hits_T_23, _hits_T_26) node _hits_T_28 = eq(ways_4.tag, tag) node _hits_T_29 = neq(ways_4.state, UInt<2>(0h0)) node _hits_T_30 = and(_hits_T_28, _hits_T_29) node _hits_T_31 = eq(setQuash, UInt<1>(0h0)) node _hits_T_32 = neq(UInt<3>(0h4), write_q.io.deq.bits.way) node _hits_T_33 = or(_hits_T_31, _hits_T_32) node _hits_T_34 = and(_hits_T_30, _hits_T_33) node _hits_T_35 = eq(ways_5.tag, tag) node _hits_T_36 = neq(ways_5.state, UInt<2>(0h0)) node _hits_T_37 = and(_hits_T_35, _hits_T_36) node _hits_T_38 = eq(setQuash, UInt<1>(0h0)) node _hits_T_39 = neq(UInt<3>(0h5), write_q.io.deq.bits.way) node _hits_T_40 = or(_hits_T_38, _hits_T_39) node _hits_T_41 = and(_hits_T_37, _hits_T_40) node _hits_T_42 = eq(ways_6.tag, tag) node _hits_T_43 = neq(ways_6.state, UInt<2>(0h0)) node _hits_T_44 = and(_hits_T_42, _hits_T_43) node _hits_T_45 = eq(setQuash, UInt<1>(0h0)) node _hits_T_46 = neq(UInt<3>(0h6), write_q.io.deq.bits.way) node _hits_T_47 = or(_hits_T_45, _hits_T_46) node _hits_T_48 = and(_hits_T_44, _hits_T_47) node _hits_T_49 = eq(ways_7.tag, tag) node _hits_T_50 = neq(ways_7.state, UInt<2>(0h0)) node _hits_T_51 = and(_hits_T_49, _hits_T_50) node _hits_T_52 = eq(setQuash, UInt<1>(0h0)) node _hits_T_53 = neq(UInt<3>(0h7), write_q.io.deq.bits.way) node _hits_T_54 = or(_hits_T_52, _hits_T_53) node _hits_T_55 = and(_hits_T_51, _hits_T_54) node _hits_T_56 = eq(ways_8.tag, tag) node _hits_T_57 = neq(ways_8.state, UInt<2>(0h0)) node _hits_T_58 = and(_hits_T_56, _hits_T_57) node _hits_T_59 = eq(setQuash, UInt<1>(0h0)) node _hits_T_60 = neq(UInt<4>(0h8), write_q.io.deq.bits.way) node _hits_T_61 = or(_hits_T_59, _hits_T_60) node _hits_T_62 = and(_hits_T_58, _hits_T_61) node _hits_T_63 = eq(ways_9.tag, tag) node _hits_T_64 = neq(ways_9.state, UInt<2>(0h0)) node _hits_T_65 = and(_hits_T_63, _hits_T_64) node _hits_T_66 = eq(setQuash, UInt<1>(0h0)) node _hits_T_67 = neq(UInt<4>(0h9), write_q.io.deq.bits.way) node _hits_T_68 = or(_hits_T_66, _hits_T_67) node _hits_T_69 = and(_hits_T_65, _hits_T_68) node _hits_T_70 = eq(ways_10.tag, tag) node _hits_T_71 = neq(ways_10.state, UInt<2>(0h0)) node _hits_T_72 = and(_hits_T_70, _hits_T_71) node _hits_T_73 = eq(setQuash, UInt<1>(0h0)) node _hits_T_74 = neq(UInt<4>(0ha), write_q.io.deq.bits.way) node _hits_T_75 = or(_hits_T_73, _hits_T_74) node _hits_T_76 = and(_hits_T_72, _hits_T_75) node _hits_T_77 = eq(ways_11.tag, tag) node _hits_T_78 = neq(ways_11.state, UInt<2>(0h0)) node _hits_T_79 = and(_hits_T_77, _hits_T_78) node _hits_T_80 = eq(setQuash, UInt<1>(0h0)) node _hits_T_81 = neq(UInt<4>(0hb), write_q.io.deq.bits.way) node _hits_T_82 = or(_hits_T_80, _hits_T_81) node _hits_T_83 = and(_hits_T_79, _hits_T_82) node _hits_T_84 = eq(ways_12.tag, tag) node _hits_T_85 = neq(ways_12.state, UInt<2>(0h0)) node _hits_T_86 = and(_hits_T_84, _hits_T_85) node _hits_T_87 = eq(setQuash, UInt<1>(0h0)) node _hits_T_88 = neq(UInt<4>(0hc), write_q.io.deq.bits.way) node _hits_T_89 = or(_hits_T_87, _hits_T_88) node _hits_T_90 = and(_hits_T_86, _hits_T_89) node _hits_T_91 = eq(ways_13.tag, tag) node _hits_T_92 = neq(ways_13.state, UInt<2>(0h0)) node _hits_T_93 = and(_hits_T_91, _hits_T_92) node _hits_T_94 = eq(setQuash, UInt<1>(0h0)) node _hits_T_95 = neq(UInt<4>(0hd), write_q.io.deq.bits.way) node _hits_T_96 = or(_hits_T_94, _hits_T_95) node _hits_T_97 = and(_hits_T_93, _hits_T_96) node _hits_T_98 = eq(ways_14.tag, tag) node _hits_T_99 = neq(ways_14.state, UInt<2>(0h0)) node _hits_T_100 = and(_hits_T_98, _hits_T_99) node _hits_T_101 = eq(setQuash, UInt<1>(0h0)) node _hits_T_102 = neq(UInt<4>(0he), write_q.io.deq.bits.way) node _hits_T_103 = or(_hits_T_101, _hits_T_102) node _hits_T_104 = and(_hits_T_100, _hits_T_103) node _hits_T_105 = eq(ways_15.tag, tag) node _hits_T_106 = neq(ways_15.state, UInt<2>(0h0)) node _hits_T_107 = and(_hits_T_105, _hits_T_106) node _hits_T_108 = eq(setQuash, UInt<1>(0h0)) node _hits_T_109 = neq(UInt<4>(0hf), write_q.io.deq.bits.way) node _hits_T_110 = or(_hits_T_108, _hits_T_109) node _hits_T_111 = and(_hits_T_107, _hits_T_110) node hits_lo_lo_lo = cat(_hits_T_13, _hits_T_6) node hits_lo_lo_hi = cat(_hits_T_27, _hits_T_20) node hits_lo_lo = cat(hits_lo_lo_hi, hits_lo_lo_lo) node hits_lo_hi_lo = cat(_hits_T_41, _hits_T_34) node hits_lo_hi_hi = cat(_hits_T_55, _hits_T_48) node hits_lo_hi = cat(hits_lo_hi_hi, hits_lo_hi_lo) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo_lo = cat(_hits_T_69, _hits_T_62) node hits_hi_lo_hi = cat(_hits_T_83, _hits_T_76) node hits_hi_lo = cat(hits_hi_lo_hi, hits_hi_lo_lo) node hits_hi_hi_lo = cat(_hits_T_97, _hits_T_90) node hits_hi_hi_hi = cat(_hits_T_111, _hits_T_104) node hits_hi_hi = cat(hits_hi_hi_hi, hits_hi_hi_lo) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node hits = cat(hits_hi, hits_lo) node hit = orr(hits) connect io.result.valid, ren1 node _view__T = bits(hits, 0, 0) node _view__T_1 = bits(hits, 1, 1) node _view__T_2 = bits(hits, 2, 2) node _view__T_3 = bits(hits, 3, 3) node _view__T_4 = bits(hits, 4, 4) node _view__T_5 = bits(hits, 5, 5) node _view__T_6 = bits(hits, 6, 6) node _view__T_7 = bits(hits, 7, 7) node _view__T_8 = bits(hits, 8, 8) node _view__T_9 = bits(hits, 9, 9) node _view__T_10 = bits(hits, 10, 10) node _view__T_11 = bits(hits, 11, 11) node _view__T_12 = bits(hits, 12, 12) node _view__T_13 = bits(hits, 13, 13) node _view__T_14 = bits(hits, 14, 14) node _view__T_15 = bits(hits, 15, 15) wire _view__WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_16 = mux(_view__T, ways_0.tag, UInt<1>(0h0)) node _view__T_17 = mux(_view__T_1, ways_1.tag, UInt<1>(0h0)) node _view__T_18 = mux(_view__T_2, ways_2.tag, UInt<1>(0h0)) node _view__T_19 = mux(_view__T_3, ways_3.tag, UInt<1>(0h0)) node _view__T_20 = mux(_view__T_4, ways_4.tag, UInt<1>(0h0)) node _view__T_21 = mux(_view__T_5, ways_5.tag, UInt<1>(0h0)) node _view__T_22 = mux(_view__T_6, ways_6.tag, UInt<1>(0h0)) node _view__T_23 = mux(_view__T_7, ways_7.tag, UInt<1>(0h0)) node _view__T_24 = mux(_view__T_8, ways_8.tag, UInt<1>(0h0)) node _view__T_25 = mux(_view__T_9, ways_9.tag, UInt<1>(0h0)) node _view__T_26 = mux(_view__T_10, ways_10.tag, UInt<1>(0h0)) node _view__T_27 = mux(_view__T_11, ways_11.tag, UInt<1>(0h0)) node _view__T_28 = mux(_view__T_12, ways_12.tag, UInt<1>(0h0)) node _view__T_29 = mux(_view__T_13, ways_13.tag, UInt<1>(0h0)) node _view__T_30 = mux(_view__T_14, ways_14.tag, UInt<1>(0h0)) node _view__T_31 = mux(_view__T_15, ways_15.tag, UInt<1>(0h0)) node _view__T_32 = or(_view__T_16, _view__T_17) node _view__T_33 = or(_view__T_32, _view__T_18) node _view__T_34 = or(_view__T_33, _view__T_19) node _view__T_35 = or(_view__T_34, _view__T_20) node _view__T_36 = or(_view__T_35, _view__T_21) node _view__T_37 = or(_view__T_36, _view__T_22) node _view__T_38 = or(_view__T_37, _view__T_23) node _view__T_39 = or(_view__T_38, _view__T_24) node _view__T_40 = or(_view__T_39, _view__T_25) node _view__T_41 = or(_view__T_40, _view__T_26) node _view__T_42 = or(_view__T_41, _view__T_27) node _view__T_43 = or(_view__T_42, _view__T_28) node _view__T_44 = or(_view__T_43, _view__T_29) node _view__T_45 = or(_view__T_44, _view__T_30) node _view__T_46 = or(_view__T_45, _view__T_31) wire _view__WIRE_1 : UInt<9> connect _view__WIRE_1, _view__T_46 connect _view__WIRE.tag, _view__WIRE_1 node _view__T_47 = mux(_view__T, ways_0.clients, UInt<1>(0h0)) node _view__T_48 = mux(_view__T_1, ways_1.clients, UInt<1>(0h0)) node _view__T_49 = mux(_view__T_2, ways_2.clients, UInt<1>(0h0)) node _view__T_50 = mux(_view__T_3, ways_3.clients, UInt<1>(0h0)) node _view__T_51 = mux(_view__T_4, ways_4.clients, UInt<1>(0h0)) node _view__T_52 = mux(_view__T_5, ways_5.clients, UInt<1>(0h0)) node _view__T_53 = mux(_view__T_6, ways_6.clients, UInt<1>(0h0)) node _view__T_54 = mux(_view__T_7, ways_7.clients, UInt<1>(0h0)) node _view__T_55 = mux(_view__T_8, ways_8.clients, UInt<1>(0h0)) node _view__T_56 = mux(_view__T_9, ways_9.clients, UInt<1>(0h0)) node _view__T_57 = mux(_view__T_10, ways_10.clients, UInt<1>(0h0)) node _view__T_58 = mux(_view__T_11, ways_11.clients, UInt<1>(0h0)) node _view__T_59 = mux(_view__T_12, ways_12.clients, UInt<1>(0h0)) node _view__T_60 = mux(_view__T_13, ways_13.clients, UInt<1>(0h0)) node _view__T_61 = mux(_view__T_14, ways_14.clients, UInt<1>(0h0)) node _view__T_62 = mux(_view__T_15, ways_15.clients, UInt<1>(0h0)) node _view__T_63 = or(_view__T_47, _view__T_48) node _view__T_64 = or(_view__T_63, _view__T_49) node _view__T_65 = or(_view__T_64, _view__T_50) node _view__T_66 = or(_view__T_65, _view__T_51) node _view__T_67 = or(_view__T_66, _view__T_52) node _view__T_68 = or(_view__T_67, _view__T_53) node _view__T_69 = or(_view__T_68, _view__T_54) node _view__T_70 = or(_view__T_69, _view__T_55) node _view__T_71 = or(_view__T_70, _view__T_56) node _view__T_72 = or(_view__T_71, _view__T_57) node _view__T_73 = or(_view__T_72, _view__T_58) node _view__T_74 = or(_view__T_73, _view__T_59) node _view__T_75 = or(_view__T_74, _view__T_60) node _view__T_76 = or(_view__T_75, _view__T_61) node _view__T_77 = or(_view__T_76, _view__T_62) wire _view__WIRE_2 : UInt<1> connect _view__WIRE_2, _view__T_77 connect _view__WIRE.clients, _view__WIRE_2 node _view__T_78 = mux(_view__T, ways_0.state, UInt<1>(0h0)) node _view__T_79 = mux(_view__T_1, ways_1.state, UInt<1>(0h0)) node _view__T_80 = mux(_view__T_2, ways_2.state, UInt<1>(0h0)) node _view__T_81 = mux(_view__T_3, ways_3.state, UInt<1>(0h0)) node _view__T_82 = mux(_view__T_4, ways_4.state, UInt<1>(0h0)) node _view__T_83 = mux(_view__T_5, ways_5.state, UInt<1>(0h0)) node _view__T_84 = mux(_view__T_6, ways_6.state, UInt<1>(0h0)) node _view__T_85 = mux(_view__T_7, ways_7.state, UInt<1>(0h0)) node _view__T_86 = mux(_view__T_8, ways_8.state, UInt<1>(0h0)) node _view__T_87 = mux(_view__T_9, ways_9.state, UInt<1>(0h0)) node _view__T_88 = mux(_view__T_10, ways_10.state, UInt<1>(0h0)) node _view__T_89 = mux(_view__T_11, ways_11.state, UInt<1>(0h0)) node _view__T_90 = mux(_view__T_12, ways_12.state, UInt<1>(0h0)) node _view__T_91 = mux(_view__T_13, ways_13.state, UInt<1>(0h0)) node _view__T_92 = mux(_view__T_14, ways_14.state, UInt<1>(0h0)) node _view__T_93 = mux(_view__T_15, ways_15.state, UInt<1>(0h0)) node _view__T_94 = or(_view__T_78, _view__T_79) node _view__T_95 = or(_view__T_94, _view__T_80) node _view__T_96 = or(_view__T_95, _view__T_81) node _view__T_97 = or(_view__T_96, _view__T_82) node _view__T_98 = or(_view__T_97, _view__T_83) node _view__T_99 = or(_view__T_98, _view__T_84) node _view__T_100 = or(_view__T_99, _view__T_85) node _view__T_101 = or(_view__T_100, _view__T_86) node _view__T_102 = or(_view__T_101, _view__T_87) node _view__T_103 = or(_view__T_102, _view__T_88) node _view__T_104 = or(_view__T_103, _view__T_89) node _view__T_105 = or(_view__T_104, _view__T_90) node _view__T_106 = or(_view__T_105, _view__T_91) node _view__T_107 = or(_view__T_106, _view__T_92) node _view__T_108 = or(_view__T_107, _view__T_93) wire _view__WIRE_3 : UInt<2> connect _view__WIRE_3, _view__T_108 connect _view__WIRE.state, _view__WIRE_3 node _view__T_109 = mux(_view__T, ways_0.dirty, UInt<1>(0h0)) node _view__T_110 = mux(_view__T_1, ways_1.dirty, UInt<1>(0h0)) node _view__T_111 = mux(_view__T_2, ways_2.dirty, UInt<1>(0h0)) node _view__T_112 = mux(_view__T_3, ways_3.dirty, UInt<1>(0h0)) node _view__T_113 = mux(_view__T_4, ways_4.dirty, UInt<1>(0h0)) node _view__T_114 = mux(_view__T_5, ways_5.dirty, UInt<1>(0h0)) node _view__T_115 = mux(_view__T_6, ways_6.dirty, UInt<1>(0h0)) node _view__T_116 = mux(_view__T_7, ways_7.dirty, UInt<1>(0h0)) node _view__T_117 = mux(_view__T_8, ways_8.dirty, UInt<1>(0h0)) node _view__T_118 = mux(_view__T_9, ways_9.dirty, UInt<1>(0h0)) node _view__T_119 = mux(_view__T_10, ways_10.dirty, UInt<1>(0h0)) node _view__T_120 = mux(_view__T_11, ways_11.dirty, UInt<1>(0h0)) node _view__T_121 = mux(_view__T_12, ways_12.dirty, UInt<1>(0h0)) node _view__T_122 = mux(_view__T_13, ways_13.dirty, UInt<1>(0h0)) node _view__T_123 = mux(_view__T_14, ways_14.dirty, UInt<1>(0h0)) node _view__T_124 = mux(_view__T_15, ways_15.dirty, UInt<1>(0h0)) node _view__T_125 = or(_view__T_109, _view__T_110) node _view__T_126 = or(_view__T_125, _view__T_111) node _view__T_127 = or(_view__T_126, _view__T_112) node _view__T_128 = or(_view__T_127, _view__T_113) node _view__T_129 = or(_view__T_128, _view__T_114) node _view__T_130 = or(_view__T_129, _view__T_115) node _view__T_131 = or(_view__T_130, _view__T_116) node _view__T_132 = or(_view__T_131, _view__T_117) node _view__T_133 = or(_view__T_132, _view__T_118) node _view__T_134 = or(_view__T_133, _view__T_119) node _view__T_135 = or(_view__T_134, _view__T_120) node _view__T_136 = or(_view__T_135, _view__T_121) node _view__T_137 = or(_view__T_136, _view__T_122) node _view__T_138 = or(_view__T_137, _view__T_123) node _view__T_139 = or(_view__T_138, _view__T_124) wire _view__WIRE_4 : UInt<1> connect _view__WIRE_4, _view__T_139 connect _view__WIRE.dirty, _view__WIRE_4 node _view__T_140 = or(tagMatch, wayMatch) node _view__T_141 = and(setQuash, _view__T_140) node _view__T_142 = bits(victimWayOH, 0, 0) node _view__T_143 = bits(victimWayOH, 1, 1) node _view__T_144 = bits(victimWayOH, 2, 2) node _view__T_145 = bits(victimWayOH, 3, 3) node _view__T_146 = bits(victimWayOH, 4, 4) node _view__T_147 = bits(victimWayOH, 5, 5) node _view__T_148 = bits(victimWayOH, 6, 6) node _view__T_149 = bits(victimWayOH, 7, 7) node _view__T_150 = bits(victimWayOH, 8, 8) node _view__T_151 = bits(victimWayOH, 9, 9) node _view__T_152 = bits(victimWayOH, 10, 10) node _view__T_153 = bits(victimWayOH, 11, 11) node _view__T_154 = bits(victimWayOH, 12, 12) node _view__T_155 = bits(victimWayOH, 13, 13) node _view__T_156 = bits(victimWayOH, 14, 14) node _view__T_157 = bits(victimWayOH, 15, 15) wire _view__WIRE_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_158 = mux(_view__T_142, ways_0.tag, UInt<1>(0h0)) node _view__T_159 = mux(_view__T_143, ways_1.tag, UInt<1>(0h0)) node _view__T_160 = mux(_view__T_144, ways_2.tag, UInt<1>(0h0)) node _view__T_161 = mux(_view__T_145, ways_3.tag, UInt<1>(0h0)) node _view__T_162 = mux(_view__T_146, ways_4.tag, UInt<1>(0h0)) node _view__T_163 = mux(_view__T_147, ways_5.tag, UInt<1>(0h0)) node _view__T_164 = mux(_view__T_148, ways_6.tag, UInt<1>(0h0)) node _view__T_165 = mux(_view__T_149, ways_7.tag, UInt<1>(0h0)) node _view__T_166 = mux(_view__T_150, ways_8.tag, UInt<1>(0h0)) node _view__T_167 = mux(_view__T_151, ways_9.tag, UInt<1>(0h0)) node _view__T_168 = mux(_view__T_152, ways_10.tag, UInt<1>(0h0)) node _view__T_169 = mux(_view__T_153, ways_11.tag, UInt<1>(0h0)) node _view__T_170 = mux(_view__T_154, ways_12.tag, UInt<1>(0h0)) node _view__T_171 = mux(_view__T_155, ways_13.tag, UInt<1>(0h0)) node _view__T_172 = mux(_view__T_156, ways_14.tag, UInt<1>(0h0)) node _view__T_173 = mux(_view__T_157, ways_15.tag, UInt<1>(0h0)) node _view__T_174 = or(_view__T_158, _view__T_159) node _view__T_175 = or(_view__T_174, _view__T_160) node _view__T_176 = or(_view__T_175, _view__T_161) node _view__T_177 = or(_view__T_176, _view__T_162) node _view__T_178 = or(_view__T_177, _view__T_163) node _view__T_179 = or(_view__T_178, _view__T_164) node _view__T_180 = or(_view__T_179, _view__T_165) node _view__T_181 = or(_view__T_180, _view__T_166) node _view__T_182 = or(_view__T_181, _view__T_167) node _view__T_183 = or(_view__T_182, _view__T_168) node _view__T_184 = or(_view__T_183, _view__T_169) node _view__T_185 = or(_view__T_184, _view__T_170) node _view__T_186 = or(_view__T_185, _view__T_171) node _view__T_187 = or(_view__T_186, _view__T_172) node _view__T_188 = or(_view__T_187, _view__T_173) wire _view__WIRE_6 : UInt<9> connect _view__WIRE_6, _view__T_188 connect _view__WIRE_5.tag, _view__WIRE_6 node _view__T_189 = mux(_view__T_142, ways_0.clients, UInt<1>(0h0)) node _view__T_190 = mux(_view__T_143, ways_1.clients, UInt<1>(0h0)) node _view__T_191 = mux(_view__T_144, ways_2.clients, UInt<1>(0h0)) node _view__T_192 = mux(_view__T_145, ways_3.clients, UInt<1>(0h0)) node _view__T_193 = mux(_view__T_146, ways_4.clients, UInt<1>(0h0)) node _view__T_194 = mux(_view__T_147, ways_5.clients, UInt<1>(0h0)) node _view__T_195 = mux(_view__T_148, ways_6.clients, UInt<1>(0h0)) node _view__T_196 = mux(_view__T_149, ways_7.clients, UInt<1>(0h0)) node _view__T_197 = mux(_view__T_150, ways_8.clients, UInt<1>(0h0)) node _view__T_198 = mux(_view__T_151, ways_9.clients, UInt<1>(0h0)) node _view__T_199 = mux(_view__T_152, ways_10.clients, UInt<1>(0h0)) node _view__T_200 = mux(_view__T_153, ways_11.clients, UInt<1>(0h0)) node _view__T_201 = mux(_view__T_154, ways_12.clients, UInt<1>(0h0)) node _view__T_202 = mux(_view__T_155, ways_13.clients, UInt<1>(0h0)) node _view__T_203 = mux(_view__T_156, ways_14.clients, UInt<1>(0h0)) node _view__T_204 = mux(_view__T_157, ways_15.clients, UInt<1>(0h0)) node _view__T_205 = or(_view__T_189, _view__T_190) node _view__T_206 = or(_view__T_205, _view__T_191) node _view__T_207 = or(_view__T_206, _view__T_192) node _view__T_208 = or(_view__T_207, _view__T_193) node _view__T_209 = or(_view__T_208, _view__T_194) node _view__T_210 = or(_view__T_209, _view__T_195) node _view__T_211 = or(_view__T_210, _view__T_196) node _view__T_212 = or(_view__T_211, _view__T_197) node _view__T_213 = or(_view__T_212, _view__T_198) node _view__T_214 = or(_view__T_213, _view__T_199) node _view__T_215 = or(_view__T_214, _view__T_200) node _view__T_216 = or(_view__T_215, _view__T_201) node _view__T_217 = or(_view__T_216, _view__T_202) node _view__T_218 = or(_view__T_217, _view__T_203) node _view__T_219 = or(_view__T_218, _view__T_204) wire _view__WIRE_7 : UInt<1> connect _view__WIRE_7, _view__T_219 connect _view__WIRE_5.clients, _view__WIRE_7 node _view__T_220 = mux(_view__T_142, ways_0.state, UInt<1>(0h0)) node _view__T_221 = mux(_view__T_143, ways_1.state, UInt<1>(0h0)) node _view__T_222 = mux(_view__T_144, ways_2.state, UInt<1>(0h0)) node _view__T_223 = mux(_view__T_145, ways_3.state, UInt<1>(0h0)) node _view__T_224 = mux(_view__T_146, ways_4.state, UInt<1>(0h0)) node _view__T_225 = mux(_view__T_147, ways_5.state, UInt<1>(0h0)) node _view__T_226 = mux(_view__T_148, ways_6.state, UInt<1>(0h0)) node _view__T_227 = mux(_view__T_149, ways_7.state, UInt<1>(0h0)) node _view__T_228 = mux(_view__T_150, ways_8.state, UInt<1>(0h0)) node _view__T_229 = mux(_view__T_151, ways_9.state, UInt<1>(0h0)) node _view__T_230 = mux(_view__T_152, ways_10.state, UInt<1>(0h0)) node _view__T_231 = mux(_view__T_153, ways_11.state, UInt<1>(0h0)) node _view__T_232 = mux(_view__T_154, ways_12.state, UInt<1>(0h0)) node _view__T_233 = mux(_view__T_155, ways_13.state, UInt<1>(0h0)) node _view__T_234 = mux(_view__T_156, ways_14.state, UInt<1>(0h0)) node _view__T_235 = mux(_view__T_157, ways_15.state, UInt<1>(0h0)) node _view__T_236 = or(_view__T_220, _view__T_221) node _view__T_237 = or(_view__T_236, _view__T_222) node _view__T_238 = or(_view__T_237, _view__T_223) node _view__T_239 = or(_view__T_238, _view__T_224) node _view__T_240 = or(_view__T_239, _view__T_225) node _view__T_241 = or(_view__T_240, _view__T_226) node _view__T_242 = or(_view__T_241, _view__T_227) node _view__T_243 = or(_view__T_242, _view__T_228) node _view__T_244 = or(_view__T_243, _view__T_229) node _view__T_245 = or(_view__T_244, _view__T_230) node _view__T_246 = or(_view__T_245, _view__T_231) node _view__T_247 = or(_view__T_246, _view__T_232) node _view__T_248 = or(_view__T_247, _view__T_233) node _view__T_249 = or(_view__T_248, _view__T_234) node _view__T_250 = or(_view__T_249, _view__T_235) wire _view__WIRE_8 : UInt<2> connect _view__WIRE_8, _view__T_250 connect _view__WIRE_5.state, _view__WIRE_8 node _view__T_251 = mux(_view__T_142, ways_0.dirty, UInt<1>(0h0)) node _view__T_252 = mux(_view__T_143, ways_1.dirty, UInt<1>(0h0)) node _view__T_253 = mux(_view__T_144, ways_2.dirty, UInt<1>(0h0)) node _view__T_254 = mux(_view__T_145, ways_3.dirty, UInt<1>(0h0)) node _view__T_255 = mux(_view__T_146, ways_4.dirty, UInt<1>(0h0)) node _view__T_256 = mux(_view__T_147, ways_5.dirty, UInt<1>(0h0)) node _view__T_257 = mux(_view__T_148, ways_6.dirty, UInt<1>(0h0)) node _view__T_258 = mux(_view__T_149, ways_7.dirty, UInt<1>(0h0)) node _view__T_259 = mux(_view__T_150, ways_8.dirty, UInt<1>(0h0)) node _view__T_260 = mux(_view__T_151, ways_9.dirty, UInt<1>(0h0)) node _view__T_261 = mux(_view__T_152, ways_10.dirty, UInt<1>(0h0)) node _view__T_262 = mux(_view__T_153, ways_11.dirty, UInt<1>(0h0)) node _view__T_263 = mux(_view__T_154, ways_12.dirty, UInt<1>(0h0)) node _view__T_264 = mux(_view__T_155, ways_13.dirty, UInt<1>(0h0)) node _view__T_265 = mux(_view__T_156, ways_14.dirty, UInt<1>(0h0)) node _view__T_266 = mux(_view__T_157, ways_15.dirty, UInt<1>(0h0)) node _view__T_267 = or(_view__T_251, _view__T_252) node _view__T_268 = or(_view__T_267, _view__T_253) node _view__T_269 = or(_view__T_268, _view__T_254) node _view__T_270 = or(_view__T_269, _view__T_255) node _view__T_271 = or(_view__T_270, _view__T_256) node _view__T_272 = or(_view__T_271, _view__T_257) node _view__T_273 = or(_view__T_272, _view__T_258) node _view__T_274 = or(_view__T_273, _view__T_259) node _view__T_275 = or(_view__T_274, _view__T_260) node _view__T_276 = or(_view__T_275, _view__T_261) node _view__T_277 = or(_view__T_276, _view__T_262) node _view__T_278 = or(_view__T_277, _view__T_263) node _view__T_279 = or(_view__T_278, _view__T_264) node _view__T_280 = or(_view__T_279, _view__T_265) node _view__T_281 = or(_view__T_280, _view__T_266) wire _view__WIRE_9 : UInt<1> connect _view__WIRE_9, _view__T_281 connect _view__WIRE_5.dirty, _view__WIRE_9 node _view__T_282 = mux(_view__T_141, write_q.io.deq.bits.data, _view__WIRE_5) node _view__T_283 = mux(hit, _view__WIRE, _view__T_282) connect io.result.bits.tag, _view__T_283.tag connect io.result.bits.clients, _view__T_283.clients connect io.result.bits.state, _view__T_283.state connect io.result.bits.dirty, _view__T_283.dirty node _io_result_bits_hit_T = and(setQuash, tagMatch) node _io_result_bits_hit_T_1 = neq(write_q.io.deq.bits.data.state, UInt<2>(0h0)) node _io_result_bits_hit_T_2 = and(_io_result_bits_hit_T, _io_result_bits_hit_T_1) node _io_result_bits_hit_T_3 = or(hit, _io_result_bits_hit_T_2) connect io.result.bits.hit, _io_result_bits_hit_T_3 node io_result_bits_way_hi = bits(hits, 15, 8) node io_result_bits_way_lo = bits(hits, 7, 0) node _io_result_bits_way_T = orr(io_result_bits_way_hi) node _io_result_bits_way_T_1 = or(io_result_bits_way_hi, io_result_bits_way_lo) node io_result_bits_way_hi_1 = bits(_io_result_bits_way_T_1, 7, 4) node io_result_bits_way_lo_1 = bits(_io_result_bits_way_T_1, 3, 0) node _io_result_bits_way_T_2 = orr(io_result_bits_way_hi_1) node _io_result_bits_way_T_3 = or(io_result_bits_way_hi_1, io_result_bits_way_lo_1) node io_result_bits_way_hi_2 = bits(_io_result_bits_way_T_3, 3, 2) node io_result_bits_way_lo_2 = bits(_io_result_bits_way_T_3, 1, 0) node _io_result_bits_way_T_4 = orr(io_result_bits_way_hi_2) node _io_result_bits_way_T_5 = or(io_result_bits_way_hi_2, io_result_bits_way_lo_2) node _io_result_bits_way_T_6 = bits(_io_result_bits_way_T_5, 1, 1) node _io_result_bits_way_T_7 = cat(_io_result_bits_way_T_4, _io_result_bits_way_T_6) node _io_result_bits_way_T_8 = cat(_io_result_bits_way_T_2, _io_result_bits_way_T_7) node _io_result_bits_way_T_9 = cat(_io_result_bits_way_T, _io_result_bits_way_T_8) node _io_result_bits_way_T_10 = and(setQuash, tagMatch) node _io_result_bits_way_T_11 = mux(_io_result_bits_way_T_10, write_q.io.deq.bits.way, victimWay) node _io_result_bits_way_T_12 = mux(hit, _io_result_bits_way_T_9, _io_result_bits_way_T_11) connect io.result.bits.way, _io_result_bits_way_T_12 node _T_166 = and(ren1, setQuash) node _T_167 = and(_T_166, tagMatch) node _T_168 = and(ren1, setQuash) node _T_169 = eq(tagMatch, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = and(_T_170, wayMatch)	module Directory_5( // @[Directory.scala:56:7] input clock, // @[Directory.scala:56:7] input reset, // @[Directory.scala:56:7] output io_write_ready, // @[Directory.scala:58:14] input io_write_valid, // @[Directory.scala:58:14] input [10:0] io_write_bits_set, // @[Directory.scala:58:14] input [3:0] io_write_bits_way, // @[Directory.scala:58:14] input io_write_bits_data_dirty, // @[Directory.scala:58:14] input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14] input io_write_bits_data_clients, // @[Directory.scala:58:14] input [8:0] io_write_bits_data_tag, // @[Directory.scala:58:14] input io_read_valid, // @[Directory.scala:58:14] input [10:0] io_read_bits_set, // @[Directory.scala:58:14] input [8:0] io_read_bits_tag, // @[Directory.scala:58:14] output io_result_bits_dirty, // @[Directory.scala:58:14] output [1:0] io_result_bits_state, // @[Directory.scala:58:14] output io_result_bits_clients, // @[Directory.scala:58:14] output [8:0] io_result_bits_tag, // @[Directory.scala:58:14] output io_result_bits_hit, // @[Directory.scala:58:14] output [3:0] io_result_bits_way, // @[Directory.scala:58:14] output io_ready // @[Directory.scala:58:14] ); wire cc_dir_MPORT_mask_15; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_14; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_13; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_12; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_11; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_10; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_9; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_8; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65] wire [12:0] _T_47; // @[Directory.scala:99:44] wire [12:0] _T_45; // @[Directory.scala:99:44] wire [12:0] _T_43; // @[Directory.scala:99:44] wire [12:0] _T_41; // @[Directory.scala:99:44] wire [12:0] _T_39; // @[Directory.scala:99:44] wire [12:0] _T_37; // @[Directory.scala:99:44] wire [12:0] _T_35; // @[Directory.scala:99:44] wire [12:0] _T_33; // @[Directory.scala:99:44] wire [12:0] _T_31; // @[Directory.scala:99:44] wire [12:0] _T_29; // @[Directory.scala:99:44] wire [12:0] _T_27; // @[Directory.scala:99:44] wire [12:0] _T_25; // @[Directory.scala:99:44] wire [12:0] _T_23; // @[Directory.scala:99:44] wire [12:0] _T_21; // @[Directory.scala:99:44] wire [12:0] _T_19; // @[Directory.scala:99:44] wire [12:0] _T_17; // @[Directory.scala:99:44] wire [10:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10] wire cc_dir_MPORT_en; // @[Directory.scala:96:14] wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_10; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_11; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_12; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_13; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_14; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_15; // @[PRNG.scala:91:22] wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [10:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21] wire [3:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21] wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21] wire [8:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21] wire [207:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_write_valid_0 = io_write_valid; // @[Directory.scala:56:7] wire [10:0] io_write_bits_set_0 = io_write_bits_set; // @[Directory.scala:56:7] wire [3:0] io_write_bits_way_0 = io_write_bits_way; // @[Directory.scala:56:7] wire io_write_bits_data_dirty_0 = io_write_bits_data_dirty; // @[Directory.scala:56:7] wire [1:0] io_write_bits_data_state_0 = io_write_bits_data_state; // @[Directory.scala:56:7] wire io_write_bits_data_clients_0 = io_write_bits_data_clients; // @[Directory.scala:56:7] wire [8:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[Directory.scala:56:7] wire io_read_valid_0 = io_read_valid; // @[Directory.scala:56:7] wire [10:0] io_read_bits_set_0 = io_read_bits_set; // @[Directory.scala:56:7] wire [8:0] io_read_bits_tag_0 = io_read_bits_tag; // @[Directory.scala:56:7] wire _victimLTE_T = 1'h1; // @[Directory.scala:117:43] wire [10:0] _regout_WIRE = io_read_bits_set_0; // @[Directory.scala:56:7, :110:41] wire _view__T_283_dirty; // @[Directory.scala:136:67] wire [1:0] _view__T_283_state; // @[Directory.scala:136:67] wire _view__T_283_clients; // @[Directory.scala:136:67] wire [8:0] _view__T_283_tag; // @[Directory.scala:136:67] wire _io_result_bits_hit_T_3; // @[Directory.scala:137:29] wire [3:0] _io_result_bits_way_T_12; // @[Directory.scala:138:28] wire wipeDone; // @[Directory.scala:81:27] wire io_write_ready_0; // @[Directory.scala:56:7] wire io_result_bits_dirty_0; // @[Directory.scala:56:7] wire [1:0] io_result_bits_state_0; // @[Directory.scala:56:7] wire io_result_bits_clients_0; // @[Directory.scala:56:7] wire [8:0] io_result_bits_tag_0; // @[Directory.scala:56:7] wire io_result_bits_hit_0; // @[Directory.scala:56:7] wire [3:0] io_result_bits_way_0; // @[Directory.scala:56:7] wire io_result_valid; // @[Directory.scala:56:7] wire io_ready_0; // @[Directory.scala:56:7] wire [12:0] _ways_WIRE = _cc_dir_RW0_rdata[12:0]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_1 = _cc_dir_RW0_rdata[25:13]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_2 = _cc_dir_RW0_rdata[38:26]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_3 = _cc_dir_RW0_rdata[51:39]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_4 = _cc_dir_RW0_rdata[64:52]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_5 = _cc_dir_RW0_rdata[77:65]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_6 = _cc_dir_RW0_rdata[90:78]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_7 = _cc_dir_RW0_rdata[103:91]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_8 = _cc_dir_RW0_rdata[116:104]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_9 = _cc_dir_RW0_rdata[129:117]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_10 = _cc_dir_RW0_rdata[142:130]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_11 = _cc_dir_RW0_rdata[155:143]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_12 = _cc_dir_RW0_rdata[168:156]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_13 = _cc_dir_RW0_rdata[181:169]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_14 = _cc_dir_RW0_rdata[194:182]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_15 = _cc_dir_RW0_rdata[207:195]; // @[DescribedSRAM.scala:17:26] reg [11:0] wipeCount; // @[Directory.scala:79:26] reg wipeOff; // @[Directory.scala:80:24] assign wipeDone = wipeCount[11]; // @[Directory.scala:79:26, :81:27] assign io_ready_0 = wipeDone; // @[Directory.scala:56:7, :81:27] wire [10:0] wipeSet = wipeCount[10:0]; // @[Directory.scala:79:26, :82:26] wire _wen_T_1 = ~wipeOff; // @[Directory.scala:80:24, :85:22, :90:27] wire [12:0] _wipeCount_T = {1'h0, wipeCount} + 13'h1; // @[Directory.scala:79:26, :85:57] wire [11:0] _wipeCount_T_1 = _wipeCount_T[11:0]; // @[Directory.scala:85:57] wire _wen_T = ~wipeDone; // @[Directory.scala:81:27, :85:9, :90:14] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Directory.scala:90:{14,24,27}] wire wen = _wen_T_2 \| _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _q_io_deq_ready_T = ~io_read_valid_0; // @[Directory.scala:56:7, :86:23, :95:18] assign cc_dir_MPORT_en = ~io_read_valid_0 & wen; // @[Directory.scala:56:7, :86:23, :90:37, :96:14] assign cc_dir_MPORT_addr = wipeDone ? _write_q_io_deq_bits_set : wipeSet; // @[Decoupled.scala:362:21] wire [9:0] _GEN = {_write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag}; // @[Decoupled.scala:362:21] wire [9:0] lo; // @[Directory.scala:99:71] assign lo = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_1; // @[Directory.scala:99:71] assign lo_1 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_2; // @[Directory.scala:99:71] assign lo_2 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_3; // @[Directory.scala:99:71] assign lo_3 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_4; // @[Directory.scala:99:71] assign lo_4 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_5; // @[Directory.scala:99:71] assign lo_5 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_6; // @[Directory.scala:99:71] assign lo_6 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_7; // @[Directory.scala:99:71] assign lo_7 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_8; // @[Directory.scala:99:71] assign lo_8 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_9; // @[Directory.scala:99:71] assign lo_9 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_10; // @[Directory.scala:99:71] assign lo_10 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_11; // @[Directory.scala:99:71] assign lo_11 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_12; // @[Directory.scala:99:71] assign lo_12 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_13; // @[Directory.scala:99:71] assign lo_13 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_14; // @[Directory.scala:99:71] assign lo_14 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_15; // @[Directory.scala:99:71] assign lo_15 = _GEN; // @[Directory.scala:99:71] wire [2:0] _GEN_0 = {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state}; // @[Decoupled.scala:362:21] wire [2:0] hi; // @[Directory.scala:99:71] assign hi = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_1; // @[Directory.scala:99:71] assign hi_1 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_2; // @[Directory.scala:99:71] assign hi_2 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_3; // @[Directory.scala:99:71] assign hi_3 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_4; // @[Directory.scala:99:71] assign hi_4 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_5; // @[Directory.scala:99:71] assign hi_5 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_6; // @[Directory.scala:99:71] assign hi_6 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_7; // @[Directory.scala:99:71] assign hi_7 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_8; // @[Directory.scala:99:71] assign hi_8 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_9; // @[Directory.scala:99:71] assign hi_9 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_10; // @[Directory.scala:99:71] assign hi_10 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_11; // @[Directory.scala:99:71] assign hi_11 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_12; // @[Directory.scala:99:71] assign hi_12 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_13; // @[Directory.scala:99:71] assign hi_13 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_14; // @[Directory.scala:99:71] assign hi_14 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_15; // @[Directory.scala:99:71] assign hi_15 = _GEN_0; // @[Directory.scala:99:71] assign _T_17 = wipeDone ? {hi, lo} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_19 = wipeDone ? {hi_1, lo_1} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_21 = wipeDone ? {hi_2, lo_2} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_23 = wipeDone ? {hi_3, lo_3} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_25 = wipeDone ? {hi_4, lo_4} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_27 = wipeDone ? {hi_5, lo_5} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_29 = wipeDone ? {hi_6, lo_6} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_31 = wipeDone ? {hi_7, lo_7} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_33 = wipeDone ? {hi_8, lo_8} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_35 = wipeDone ? {hi_9, lo_9} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_37 = wipeDone ? {hi_10, lo_10} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_39 = wipeDone ? {hi_11, lo_11} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_41 = wipeDone ? {hi_12, lo_12} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_43 = wipeDone ? {hi_13, lo_13} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_45 = wipeDone ? {hi_14, lo_14} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_47 = wipeDone ? {hi_15, lo_15} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] wire [3:0] shiftAmount; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_0 = shiftAmount == 4'h0 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_1 = shiftAmount == 4'h1 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_2 = shiftAmount == 4'h2 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_3 = shiftAmount == 4'h3 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_4 = shiftAmount == 4'h4 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_5 = shiftAmount == 4'h5 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_6 = shiftAmount == 4'h6 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_7 = shiftAmount == 4'h7 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_8 = shiftAmount == 4'h8 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_9 = shiftAmount == 4'h9 \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_10 = shiftAmount == 4'hA \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_11 = shiftAmount == 4'hB \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_12 = shiftAmount == 4'hC \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_13 = shiftAmount == 4'hD \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_14 = shiftAmount == 4'hE \| ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_15 = (&shiftAmount) \| ~wipeDone; // @[OneHot.scala:64:49] reg ren1; // @[Directory.scala:103:21] assign io_result_valid = ren1; // @[Directory.scala:56:7, :103:21] wire _bypass_T = ren1 & _write_q_io_deq_valid; // @[Decoupled.scala:362:21] reg [8:0] tag; // @[Directory.scala:111:36] reg [10:0] set; // @[Directory.scala:112:36] wire [1:0] victimLFSR_lo_lo_lo = {_victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_lo_hi = {_victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_lo = {victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_lo_hi_lo = {_victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_hi_hi = {_victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_hi = {victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_lo = {victimLFSR_lo_hi, victimLFSR_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_lo_lo = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_lo_hi = {_victimLFSR_prng_io_out_11, _victimLFSR_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_lo = {victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_hi_lo = {_victimLFSR_prng_io_out_13, _victimLFSR_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_hi_hi = {_victimLFSR_prng_io_out_15, _victimLFSR_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_hi = {victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_hi = {victimLFSR_hi_hi, victimLFSR_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _victimLFSR_T = {victimLFSR_hi, victimLFSR_lo}; // @[PRNG.scala:95:17] wire [9:0] victimLFSR = _victimLFSR_T[9:0]; // @[PRNG.scala:95:17] wire _victimLTE_T_1 = \|(victimLFSR[9:6]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_2 = \|(victimLFSR[9:7]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_3 = victimLFSR > 10'hBF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_4 = \|(victimLFSR[9:8]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_5 = victimLFSR > 10'h13F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_6 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_7 = victimLFSR > 10'h1BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_8 = victimLFSR[9]; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_9 = victimLFSR > 10'h23F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_10 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_11 = victimLFSR > 10'h2BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_12 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_13 = victimLFSR > 10'h33F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_14 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_15 = victimLFSR > 10'h3BF; // @[Directory.scala:115:63, :117:43] wire [1:0] victimLTE_lo_lo_lo = {_victimLTE_T_1, 1'h1}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_lo_hi = {_victimLTE_T_3, _victimLTE_T_2}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_lo = {victimLTE_lo_lo_hi, victimLTE_lo_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_lo_hi_lo = {_victimLTE_T_5, _victimLTE_T_4}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_hi_hi = {_victimLTE_T_7, _victimLTE_T_6}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_hi = {victimLTE_lo_hi_hi, victimLTE_lo_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_lo = {victimLTE_lo_hi, victimLTE_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_lo_lo = {_victimLTE_T_9, _victimLTE_T_8}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_lo_hi = {_victimLTE_T_11, _victimLTE_T_10}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_lo = {victimLTE_hi_lo_hi, victimLTE_hi_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_hi_lo = {_victimLTE_T_13, _victimLTE_T_12}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_hi_hi = {_victimLTE_T_15, _victimLTE_T_14}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_hi = {victimLTE_hi_hi_hi, victimLTE_hi_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_hi = {victimLTE_hi_hi, victimLTE_hi_lo}; // @[Directory.scala:117:23] wire [15:0] victimLTE = {victimLTE_hi, victimLTE_lo}; // @[Directory.scala:117:23] wire [14:0] _victimSimp_T = victimLTE[15:1]; // @[Directory.scala:117:23, :118:43] wire [15:0] victimSimp_hi = {1'h0, _victimSimp_T}; // @[Directory.scala:118:{23,43}] wire [16:0] victimSimp = {victimSimp_hi, 1'h1}; // @[Directory.scala:118:23] wire [15:0] _victimWayOH_T = victimSimp[15:0]; // @[Directory.scala:118:23, :119:31] wire [15:0] _victimWayOH_T_1 = victimSimp[16:1]; // @[Directory.scala:118:23, :119:70] wire [15:0] _victimWayOH_T_2 = ~_victimWayOH_T_1; // @[Directory.scala:119:{57,70}] wire [15:0] victimWayOH = _victimWayOH_T & _victimWayOH_T_2; // @[Directory.scala:119:{31,55,57}] wire [7:0] victimWay_hi = victimWayOH[15:8]; // @[OneHot.scala:30:18] wire [7:0] victimWay_lo = victimWayOH[7:0]; // @[OneHot.scala:31:18] wire _victimWay_T = \|victimWay_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _victimWay_T_1 = victimWay_hi \| victimWay_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] victimWay_hi_1 = _victimWay_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] victimWay_lo_1 = _victimWay_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_2 = \|victimWay_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _victimWay_T_3 = victimWay_hi_1 \| victimWay_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] victimWay_hi_2 = _victimWay_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] victimWay_lo_2 = _victimWay_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_4 = \|victimWay_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _victimWay_T_5 = victimWay_hi_2 \| victimWay_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _victimWay_T_6 = _victimWay_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _victimWay_T_7 = {_victimWay_T_4, _victimWay_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _victimWay_T_8 = {_victimWay_T_2, _victimWay_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] victimWay = {_victimWay_T, _victimWay_T_8}; // @[OneHot.scala:32:{10,14}] wire _view__T_142 = victimWayOH[0]; // @[Mux.scala:32:36] wire _view__T_143 = victimWayOH[1]; // @[Mux.scala:32:36] wire _view__T_144 = victimWayOH[2]; // @[Mux.scala:32:36] wire _view__T_145 = victimWayOH[3]; // @[Mux.scala:32:36] wire _view__T_146 = victimWayOH[4]; // @[Mux.scala:32:36] wire _view__T_147 = victimWayOH[5]; // @[Mux.scala:32:36] wire _view__T_148 = victimWayOH[6]; // @[Mux.scala:32:36] wire _view__T_149 = victimWayOH[7]; // @[Mux.scala:32:36] wire _view__T_150 = victimWayOH[8]; // @[Mux.scala:32:36] wire _view__T_151 = victimWayOH[9]; // @[Mux.scala:32:36] wire _view__T_152 = victimWayOH[10]; // @[Mux.scala:32:36] wire _view__T_153 = victimWayOH[11]; // @[Mux.scala:32:36] wire _view__T_154 = victimWayOH[12]; // @[Mux.scala:32:36] wire _view__T_155 = victimWayOH[13]; // @[Mux.scala:32:36] wire _view__T_156 = victimWayOH[14]; // @[Mux.scala:32:36] wire _view__T_157 = victimWayOH[15]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_88 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_88( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Pipeline : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, busy : UInt<1>} reg stages : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}[4], clock wire _valids_WIRE : UInt<1>[4] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) regreset valids : UInt<1>[4], clock, reset, _valids_WIRE wire stalling : UInt<1>[4] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) connect stalling[2], UInt<1>(0h0) connect stalling[3], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(_io_busy_T, valids[2]) node _io_busy_T_2 = or(_io_busy_T_1, valids[3]) node _io_busy_T_3 = or(io.in.valid, _io_busy_T_2) connect io.busy, _io_busy_T_3 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_3_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_3_T_1 = and(valids[3], _stalling_3_T) connect stalling[3], _stalling_3_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T node _stalling_1_T = and(valids[1], stalling[2]) connect stalling[1], _stalling_1_T node _stalling_2_T = and(valids[2], stalling[3]) connect stalling[2], _stalling_2_T connect io.out.valid, valids[3] when io.out.ready : connect valids[3], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = eq(stalling[2], UInt<1>(0h0)) when _T_1 : connect valids[1], UInt<1>(0h0) node _T_2 = eq(stalling[3], UInt<1>(0h0)) when _T_2 : connect valids[2], UInt<1>(0h0) node _T_3 = and(io.in.ready, io.in.valid) when _T_3 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) when valids[1] : connect valids[2], UInt<1>(0h1) when valids[2] : connect valids[3], UInt<1>(0h1) node _T_4 = and(io.in.ready, io.in.valid) when _T_4 : connect stages[0], io.in.bits connect io.out.bits, stages[3] node _T_5 = eq(stalling[1], UInt<1>(0h0)) when _T_5 : connect stages[1], stages[0] node _T_6 = eq(stalling[2], UInt<1>(0h0)) when _T_6 : connect stages[2], stages[1] node _T_7 = eq(stalling[3], UInt<1>(0h0)) when _T_7 : connect stages[3], stages[2]	module Pipeline( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_0_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_1_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_2_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_3_bits, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_row, // @[Pipeline.scala:7:14] input io_in_bits_last, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_tag_data, // @[Pipeline.scala:7:14] input [13:0] io_in_bits_tag_addr, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_0, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_1, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_2, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_3, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_4, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_5, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_6, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_7, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_8, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_9, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_10, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_11, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_12, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_13, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_14, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_15, // @[Pipeline.scala:7:14] input io_in_bits_tag_is_acc, // @[Pipeline.scala:7:14] input io_in_bits_tag_accumulate, // @[Pipeline.scala:7:14] input io_in_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_tag_scale, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_repeats, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_len, // @[Pipeline.scala:7:14] input io_in_bits_tag_last, // @[Pipeline.scala:7:14] input [7:0] io_in_bits_tag_bytes_read, // @[Pipeline.scala:7:14] input [7:0] io_in_bits_tag_cmd_id, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_0_bits, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_1_bits, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_2_bits, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_3_bits, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_row, // @[Pipeline.scala:7:14] output io_out_bits_last, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_tag_data, // @[Pipeline.scala:7:14] output [13:0] io_out_bits_tag_addr, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_0, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_1, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_2, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_3, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_4, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_5, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_6, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_7, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_8, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_9, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_10, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_11, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_12, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_13, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_14, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_15, // @[Pipeline.scala:7:14] output io_out_bits_tag_is_acc, // @[Pipeline.scala:7:14] output io_out_bits_tag_accumulate, // @[Pipeline.scala:7:14] output io_out_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_tag_scale, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_repeats, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_len, // @[Pipeline.scala:7:14] output io_out_bits_tag_last, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_tag_bytes_read, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_tag_cmd_id // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_0_bits_0 = io_in_bits_out_0_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_1_bits_0 = io_in_bits_out_1_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_2_bits_0 = io_in_bits_out_2_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_3_bits_0 = io_in_bits_out_3_bits; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_row_0 = io_in_bits_row; // @[Pipeline.scala:6:7] wire io_in_bits_last_0 = io_in_bits_last; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_tag_data_0 = io_in_bits_tag_data; // @[Pipeline.scala:6:7] wire [13:0] io_in_bits_tag_addr_0 = io_in_bits_tag_addr; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_0_0 = io_in_bits_tag_mask_0; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_1_0 = io_in_bits_tag_mask_1; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_2_0 = io_in_bits_tag_mask_2; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_3_0 = io_in_bits_tag_mask_3; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_4_0 = io_in_bits_tag_mask_4; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_5_0 = io_in_bits_tag_mask_5; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_6_0 = io_in_bits_tag_mask_6; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_7_0 = io_in_bits_tag_mask_7; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_8_0 = io_in_bits_tag_mask_8; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_9_0 = io_in_bits_tag_mask_9; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_10_0 = io_in_bits_tag_mask_10; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_11_0 = io_in_bits_tag_mask_11; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_12_0 = io_in_bits_tag_mask_12; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_13_0 = io_in_bits_tag_mask_13; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_14_0 = io_in_bits_tag_mask_14; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_15_0 = io_in_bits_tag_mask_15; // @[Pipeline.scala:6:7] wire io_in_bits_tag_is_acc_0 = io_in_bits_tag_is_acc; // @[Pipeline.scala:6:7] wire io_in_bits_tag_accumulate_0 = io_in_bits_tag_accumulate; // @[Pipeline.scala:6:7] wire io_in_bits_tag_has_acc_bitwidth_0 = io_in_bits_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_tag_scale_0 = io_in_bits_tag_scale; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_repeats_0 = io_in_bits_tag_repeats; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_pixel_repeats_0 = io_in_bits_tag_pixel_repeats; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_len_0 = io_in_bits_tag_len; // @[Pipeline.scala:6:7] wire io_in_bits_tag_last_0 = io_in_bits_tag_last; // @[Pipeline.scala:6:7] wire [7:0] io_in_bits_tag_bytes_read_0 = io_in_bits_tag_bytes_read; // @[Pipeline.scala:6:7] wire [7:0] io_in_bits_tag_cmd_id_0 = io_in_bits_tag_cmd_id; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_3; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_0_bits_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_1_bits_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_2_bits_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_3_bits_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_tag_data_0; // @[Pipeline.scala:6:7] wire [13:0] io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_len_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_last_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_row_0; // @[Pipeline.scala:6:7] wire io_out_bits_last_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [31:0] stages_0_out_0_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_out_1_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_out_2_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_out_3_bits; // @[Pipeline.scala:21:21] reg [15:0] stages_0_row; // @[Pipeline.scala:21:21] reg stages_0_last; // @[Pipeline.scala:21:21] reg [127:0] stages_0_tag_data; // @[Pipeline.scala:21:21] reg [13:0] stages_0_tag_addr; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_0; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_1; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_2; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_3; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_4; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_5; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_6; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_7; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_8; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_9; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_10; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_11; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_12; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_13; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_14; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_15; // @[Pipeline.scala:21:21] reg stages_0_tag_is_acc; // @[Pipeline.scala:21:21] reg stages_0_tag_accumulate; // @[Pipeline.scala:21:21] reg stages_0_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] reg [31:0] stages_0_tag_scale; // @[Pipeline.scala:21:21] reg [15:0] stages_0_tag_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_0_tag_pixel_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_0_tag_len; // @[Pipeline.scala:21:21] reg stages_0_tag_last; // @[Pipeline.scala:21:21] reg [7:0] stages_0_tag_bytes_read; // @[Pipeline.scala:21:21] reg [7:0] stages_0_tag_cmd_id; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_0_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_1_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_2_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_3_bits; // @[Pipeline.scala:21:21] reg [15:0] stages_1_row; // @[Pipeline.scala:21:21] reg stages_1_last; // @[Pipeline.scala:21:21] reg [127:0] stages_1_tag_data; // @[Pipeline.scala:21:21] reg [13:0] stages_1_tag_addr; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_0; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_1; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_2; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_3; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_4; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_5; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_6; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_7; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_8; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_9; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_10; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_11; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_12; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_13; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_14; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_15; // @[Pipeline.scala:21:21] reg stages_1_tag_is_acc; // @[Pipeline.scala:21:21] reg stages_1_tag_accumulate; // @[Pipeline.scala:21:21] reg stages_1_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] reg [31:0] stages_1_tag_scale; // @[Pipeline.scala:21:21] reg [15:0] stages_1_tag_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_1_tag_pixel_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_1_tag_len; // @[Pipeline.scala:21:21] reg stages_1_tag_last; // @[Pipeline.scala:21:21] reg [7:0] stages_1_tag_bytes_read; // @[Pipeline.scala:21:21] reg [7:0] stages_1_tag_cmd_id; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_0_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_1_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_2_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_3_bits; // @[Pipeline.scala:21:21] reg [15:0] stages_2_row; // @[Pipeline.scala:21:21] reg stages_2_last; // @[Pipeline.scala:21:21] reg [127:0] stages_2_tag_data; // @[Pipeline.scala:21:21] reg [13:0] stages_2_tag_addr; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_0; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_1; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_2; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_3; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_4; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_5; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_6; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_7; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_8; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_9; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_10; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_11; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_12; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_13; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_14; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_15; // @[Pipeline.scala:21:21] reg stages_2_tag_is_acc; // @[Pipeline.scala:21:21] reg stages_2_tag_accumulate; // @[Pipeline.scala:21:21] reg stages_2_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] reg [31:0] stages_2_tag_scale; // @[Pipeline.scala:21:21] reg [15:0] stages_2_tag_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_2_tag_pixel_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_2_tag_len; // @[Pipeline.scala:21:21] reg stages_2_tag_last; // @[Pipeline.scala:21:21] reg [7:0] stages_2_tag_bytes_read; // @[Pipeline.scala:21:21] reg [7:0] stages_2_tag_cmd_id; // @[Pipeline.scala:21:21] reg [31:0] stages_3_out_0_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_0_bits_0 = stages_3_out_0_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_out_1_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_1_bits_0 = stages_3_out_1_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_out_2_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_2_bits_0 = stages_3_out_2_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_out_3_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_3_bits_0 = stages_3_out_3_bits; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_row; // @[Pipeline.scala:21:21] assign io_out_bits_row_0 = stages_3_row; // @[Pipeline.scala:6:7, :21:21] reg stages_3_last; // @[Pipeline.scala:21:21] assign io_out_bits_last_0 = stages_3_last; // @[Pipeline.scala:6:7, :21:21] reg [127:0] stages_3_tag_data; // @[Pipeline.scala:21:21] assign io_out_bits_tag_data_0 = stages_3_tag_data; // @[Pipeline.scala:6:7, :21:21] reg [13:0] stages_3_tag_addr; // @[Pipeline.scala:21:21] assign io_out_bits_tag_addr_0 = stages_3_tag_addr; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_0; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_0_0 = stages_3_tag_mask_0; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_1; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_1_0 = stages_3_tag_mask_1; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_2; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_2_0 = stages_3_tag_mask_2; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_3; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_3_0 = stages_3_tag_mask_3; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_4; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_4_0 = stages_3_tag_mask_4; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_5; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_5_0 = stages_3_tag_mask_5; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_6; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_6_0 = stages_3_tag_mask_6; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_7; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_7_0 = stages_3_tag_mask_7; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_8; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_8_0 = stages_3_tag_mask_8; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_9; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_9_0 = stages_3_tag_mask_9; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_10; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_10_0 = stages_3_tag_mask_10; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_11; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_11_0 = stages_3_tag_mask_11; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_12; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_12_0 = stages_3_tag_mask_12; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_13; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_13_0 = stages_3_tag_mask_13; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_14; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_14_0 = stages_3_tag_mask_14; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_15; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_15_0 = stages_3_tag_mask_15; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_is_acc; // @[Pipeline.scala:21:21] assign io_out_bits_tag_is_acc_0 = stages_3_tag_is_acc; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_accumulate; // @[Pipeline.scala:21:21] assign io_out_bits_tag_accumulate_0 = stages_3_tag_accumulate; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] assign io_out_bits_tag_has_acc_bitwidth_0 = stages_3_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_tag_scale; // @[Pipeline.scala:21:21] assign io_out_bits_tag_scale_0 = stages_3_tag_scale; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_tag_repeats; // @[Pipeline.scala:21:21] assign io_out_bits_tag_repeats_0 = stages_3_tag_repeats; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_tag_pixel_repeats; // @[Pipeline.scala:21:21] assign io_out_bits_tag_pixel_repeats_0 = stages_3_tag_pixel_repeats; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_tag_len; // @[Pipeline.scala:21:21] assign io_out_bits_tag_len_0 = stages_3_tag_len; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_last; // @[Pipeline.scala:21:21] assign io_out_bits_tag_last_0 = stages_3_tag_last; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_3_tag_bytes_read; // @[Pipeline.scala:21:21] assign io_out_bits_tag_bytes_read_0 = stages_3_tag_bytes_read; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_3_tag_cmd_id; // @[Pipeline.scala:21:21] assign io_out_bits_tag_cmd_id_0 = stages_3_tag_cmd_id; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 \| valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T \| valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 \| valids_3; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_3 = io_in_valid_0 \| _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_4) begin // @[Decoupled.scala:51:35] stages_0_out_0_bits <= io_in_bits_out_0_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_out_1_bits <= io_in_bits_out_1_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_out_2_bits <= io_in_bits_out_2_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_out_3_bits <= io_in_bits_out_3_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_row <= io_in_bits_row_0; // @[Pipeline.scala:6:7, :21:21] stages_0_last <= io_in_bits_last_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_data <= io_in_bits_tag_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_addr <= io_in_bits_tag_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_0 <= io_in_bits_tag_mask_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_1 <= io_in_bits_tag_mask_1_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_2 <= io_in_bits_tag_mask_2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_3 <= io_in_bits_tag_mask_3_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_4 <= io_in_bits_tag_mask_4_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_5 <= io_in_bits_tag_mask_5_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_6 <= io_in_bits_tag_mask_6_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_7 <= io_in_bits_tag_mask_7_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_8 <= io_in_bits_tag_mask_8_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_9 <= io_in_bits_tag_mask_9_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_10 <= io_in_bits_tag_mask_10_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_11 <= io_in_bits_tag_mask_11_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_12 <= io_in_bits_tag_mask_12_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_13 <= io_in_bits_tag_mask_13_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_14 <= io_in_bits_tag_mask_14_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_15 <= io_in_bits_tag_mask_15_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_is_acc <= io_in_bits_tag_is_acc_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_accumulate <= io_in_bits_tag_accumulate_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_has_acc_bitwidth <= io_in_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_scale <= io_in_bits_tag_scale_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_repeats <= io_in_bits_tag_repeats_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_pixel_repeats <= io_in_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_len <= io_in_bits_tag_len_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_last <= io_in_bits_tag_last_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_bytes_read <= io_in_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_cmd_id <= io_in_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_out_0_bits <= stages_0_out_0_bits; // @[Pipeline.scala:21:21] stages_1_out_1_bits <= stages_0_out_1_bits; // @[Pipeline.scala:21:21] stages_1_out_2_bits <= stages_0_out_2_bits; // @[Pipeline.scala:21:21] stages_1_out_3_bits <= stages_0_out_3_bits; // @[Pipeline.scala:21:21] stages_1_row <= stages_0_row; // @[Pipeline.scala:21:21] stages_1_last <= stages_0_last; // @[Pipeline.scala:21:21] stages_1_tag_data <= stages_0_tag_data; // @[Pipeline.scala:21:21] stages_1_tag_addr <= stages_0_tag_addr; // @[Pipeline.scala:21:21] stages_1_tag_mask_0 <= stages_0_tag_mask_0; // @[Pipeline.scala:21:21] stages_1_tag_mask_1 <= stages_0_tag_mask_1; // @[Pipeline.scala:21:21] stages_1_tag_mask_2 <= stages_0_tag_mask_2; // @[Pipeline.scala:21:21] stages_1_tag_mask_3 <= stages_0_tag_mask_3; // @[Pipeline.scala:21:21] stages_1_tag_mask_4 <= stages_0_tag_mask_4; // @[Pipeline.scala:21:21] stages_1_tag_mask_5 <= stages_0_tag_mask_5; // @[Pipeline.scala:21:21] stages_1_tag_mask_6 <= stages_0_tag_mask_6; // @[Pipeline.scala:21:21] stages_1_tag_mask_7 <= stages_0_tag_mask_7; // @[Pipeline.scala:21:21] stages_1_tag_mask_8 <= stages_0_tag_mask_8; // @[Pipeline.scala:21:21] stages_1_tag_mask_9 <= stages_0_tag_mask_9; // @[Pipeline.scala:21:21] stages_1_tag_mask_10 <= stages_0_tag_mask_10; // @[Pipeline.scala:21:21] stages_1_tag_mask_11 <= stages_0_tag_mask_11; // @[Pipeline.scala:21:21] stages_1_tag_mask_12 <= stages_0_tag_mask_12; // @[Pipeline.scala:21:21] stages_1_tag_mask_13 <= stages_0_tag_mask_13; // @[Pipeline.scala:21:21] stages_1_tag_mask_14 <= stages_0_tag_mask_14; // @[Pipeline.scala:21:21] stages_1_tag_mask_15 <= stages_0_tag_mask_15; // @[Pipeline.scala:21:21] stages_1_tag_is_acc <= stages_0_tag_is_acc; // @[Pipeline.scala:21:21] stages_1_tag_accumulate <= stages_0_tag_accumulate; // @[Pipeline.scala:21:21] stages_1_tag_has_acc_bitwidth <= stages_0_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] stages_1_tag_scale <= stages_0_tag_scale; // @[Pipeline.scala:21:21] stages_1_tag_repeats <= stages_0_tag_repeats; // @[Pipeline.scala:21:21] stages_1_tag_pixel_repeats <= stages_0_tag_pixel_repeats; // @[Pipeline.scala:21:21] stages_1_tag_len <= stages_0_tag_len; // @[Pipeline.scala:21:21] stages_1_tag_last <= stages_0_tag_last; // @[Pipeline.scala:21:21] stages_1_tag_bytes_read <= stages_0_tag_bytes_read; // @[Pipeline.scala:21:21] stages_1_tag_cmd_id <= stages_0_tag_cmd_id; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_out_0_bits <= stages_1_out_0_bits; // @[Pipeline.scala:21:21] stages_2_out_1_bits <= stages_1_out_1_bits; // @[Pipeline.scala:21:21] stages_2_out_2_bits <= stages_1_out_2_bits; // @[Pipeline.scala:21:21] stages_2_out_3_bits <= stages_1_out_3_bits; // @[Pipeline.scala:21:21] stages_2_row <= stages_1_row; // @[Pipeline.scala:21:21] stages_2_last <= stages_1_last; // @[Pipeline.scala:21:21] stages_2_tag_data <= stages_1_tag_data; // @[Pipeline.scala:21:21] stages_2_tag_addr <= stages_1_tag_addr; // @[Pipeline.scala:21:21] stages_2_tag_mask_0 <= stages_1_tag_mask_0; // @[Pipeline.scala:21:21] stages_2_tag_mask_1 <= stages_1_tag_mask_1; // @[Pipeline.scala:21:21] stages_2_tag_mask_2 <= stages_1_tag_mask_2; // @[Pipeline.scala:21:21] stages_2_tag_mask_3 <= stages_1_tag_mask_3; // @[Pipeline.scala:21:21] stages_2_tag_mask_4 <= stages_1_tag_mask_4; // @[Pipeline.scala:21:21] stages_2_tag_mask_5 <= stages_1_tag_mask_5; // @[Pipeline.scala:21:21] stages_2_tag_mask_6 <= stages_1_tag_mask_6; // @[Pipeline.scala:21:21] stages_2_tag_mask_7 <= stages_1_tag_mask_7; // @[Pipeline.scala:21:21] stages_2_tag_mask_8 <= stages_1_tag_mask_8; // @[Pipeline.scala:21:21] stages_2_tag_mask_9 <= stages_1_tag_mask_9; // @[Pipeline.scala:21:21] stages_2_tag_mask_10 <= stages_1_tag_mask_10; // @[Pipeline.scala:21:21] stages_2_tag_mask_11 <= stages_1_tag_mask_11; // @[Pipeline.scala:21:21] stages_2_tag_mask_12 <= stages_1_tag_mask_12; // @[Pipeline.scala:21:21] stages_2_tag_mask_13 <= stages_1_tag_mask_13; // @[Pipeline.scala:21:21] stages_2_tag_mask_14 <= stages_1_tag_mask_14; // @[Pipeline.scala:21:21] stages_2_tag_mask_15 <= stages_1_tag_mask_15; // @[Pipeline.scala:21:21] stages_2_tag_is_acc <= stages_1_tag_is_acc; // @[Pipeline.scala:21:21] stages_2_tag_accumulate <= stages_1_tag_accumulate; // @[Pipeline.scala:21:21] stages_2_tag_has_acc_bitwidth <= stages_1_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] stages_2_tag_scale <= stages_1_tag_scale; // @[Pipeline.scala:21:21] stages_2_tag_repeats <= stages_1_tag_repeats; // @[Pipeline.scala:21:21] stages_2_tag_pixel_repeats <= stages_1_tag_pixel_repeats; // @[Pipeline.scala:21:21] stages_2_tag_len <= stages_1_tag_len; // @[Pipeline.scala:21:21] stages_2_tag_last <= stages_1_tag_last; // @[Pipeline.scala:21:21] stages_2_tag_bytes_read <= stages_1_tag_bytes_read; // @[Pipeline.scala:21:21] stages_2_tag_cmd_id <= stages_1_tag_cmd_id; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_out_0_bits <= stages_2_out_0_bits; // @[Pipeline.scala:21:21] stages_3_out_1_bits <= stages_2_out_1_bits; // @[Pipeline.scala:21:21] stages_3_out_2_bits <= stages_2_out_2_bits; // @[Pipeline.scala:21:21] stages_3_out_3_bits <= stages_2_out_3_bits; // @[Pipeline.scala:21:21] stages_3_row <= stages_2_row; // @[Pipeline.scala:21:21] stages_3_last <= stages_2_last; // @[Pipeline.scala:21:21] stages_3_tag_data <= stages_2_tag_data; // @[Pipeline.scala:21:21] stages_3_tag_addr <= stages_2_tag_addr; // @[Pipeline.scala:21:21] stages_3_tag_mask_0 <= stages_2_tag_mask_0; // @[Pipeline.scala:21:21] stages_3_tag_mask_1 <= stages_2_tag_mask_1; // @[Pipeline.scala:21:21] stages_3_tag_mask_2 <= stages_2_tag_mask_2; // @[Pipeline.scala:21:21] stages_3_tag_mask_3 <= stages_2_tag_mask_3; // @[Pipeline.scala:21:21] stages_3_tag_mask_4 <= stages_2_tag_mask_4; // @[Pipeline.scala:21:21] stages_3_tag_mask_5 <= stages_2_tag_mask_5; // @[Pipeline.scala:21:21] stages_3_tag_mask_6 <= stages_2_tag_mask_6; // @[Pipeline.scala:21:21] stages_3_tag_mask_7 <= stages_2_tag_mask_7; // @[Pipeline.scala:21:21] stages_3_tag_mask_8 <= stages_2_tag_mask_8; // @[Pipeline.scala:21:21] stages_3_tag_mask_9 <= stages_2_tag_mask_9; // @[Pipeline.scala:21:21] stages_3_tag_mask_10 <= stages_2_tag_mask_10; // @[Pipeline.scala:21:21] stages_3_tag_mask_11 <= stages_2_tag_mask_11; // @[Pipeline.scala:21:21] stages_3_tag_mask_12 <= stages_2_tag_mask_12; // @[Pipeline.scala:21:21] stages_3_tag_mask_13 <= stages_2_tag_mask_13; // @[Pipeline.scala:21:21] stages_3_tag_mask_14 <= stages_2_tag_mask_14; // @[Pipeline.scala:21:21] stages_3_tag_mask_15 <= stages_2_tag_mask_15; // @[Pipeline.scala:21:21] stages_3_tag_is_acc <= stages_2_tag_is_acc; // @[Pipeline.scala:21:21] stages_3_tag_accumulate <= stages_2_tag_accumulate; // @[Pipeline.scala:21:21] stages_3_tag_has_acc_bitwidth <= stages_2_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] stages_3_tag_scale <= stages_2_tag_scale; // @[Pipeline.scala:21:21] stages_3_tag_repeats <= stages_2_tag_repeats; // @[Pipeline.scala:21:21] stages_3_tag_pixel_repeats <= stages_2_tag_pixel_repeats; // @[Pipeline.scala:21:21] stages_3_tag_len <= stages_2_tag_len; // @[Pipeline.scala:21:21] stages_3_tag_last <= stages_2_tag_last; // @[Pipeline.scala:21:21] stages_3_tag_bytes_read <= stages_2_tag_bytes_read; // @[Pipeline.scala:21:21] stages_3_tag_cmd_id <= stages_2_tag_cmd_id; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_4 \| stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 \| stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 \| stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 \| ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_0_bits = io_out_bits_out_0_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_1_bits = io_out_bits_out_1_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_2_bits = io_out_bits_out_2_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_3_bits = io_out_bits_out_3_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_row = io_out_bits_row_0; // @[Pipeline.scala:6:7] assign io_out_bits_last = io_out_bits_last_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_data = io_out_bits_tag_data_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_addr = io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_0 = io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_1 = io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_2 = io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_3 = io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_4 = io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_5 = io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_6 = io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_7 = io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_8 = io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_9 = io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_10 = io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_11 = io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_12 = io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_13 = io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_14 = io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_15 = io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_is_acc = io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_accumulate = io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_has_acc_bitwidth = io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_scale = io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_repeats = io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_pixel_repeats = io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_len = io_out_bits_tag_len_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_last = io_out_bits_tag_last_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_bytes_read = io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_cmd_id = io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_5 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_5( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_146 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_146( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_13 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 2) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_17 = shr(io.in.a.bits.source, 2) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_30 = shr(io.in.a.bits.source, 2) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_43 = shr(io.in.a.bits.source, 2) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_66 = shr(io.in.a.bits.source, 2) node _T_67 = eq(_T_66, UInt<1>(0h0)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_72 = shr(io.in.a.bits.source, 2) node _T_73 = eq(_T_72, UInt<1>(0h1)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_78 = shr(io.in.a.bits.source, 2) node _T_79 = eq(_T_78, UInt<2>(0h2)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_84 = shr(io.in.a.bits.source, 2) node _T_85 = eq(_T_84, UInt<2>(0h3)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = or(_T_100, _T_105) node _T_137 = or(_T_136, _T_110) node _T_138 = or(_T_137, _T_115) node _T_139 = or(_T_138, _T_120) node _T_140 = or(_T_139, _T_125) node _T_141 = or(_T_140, _T_130) node _T_142 = or(_T_141, _T_135) node _T_143 = and(_T_95, _T_142) node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_150, _T_155) node _T_157 = and(_T_145, _T_156) node _T_158 = or(UInt<1>(0h0), _T_143) node _T_159 = or(_T_158, _T_157) node _T_160 = and(_T_94, _T_159) node _T_161 = asUInt(reset) node _T_162 = eq(_T_161, UInt<1>(0h0)) when _T_162 : node _T_163 = eq(_T_160, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_160, UInt<1>(0h1), "") : assert_2 node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_166 = and(_T_164, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_184 = cvt(_T_183) node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000))) node _T_186 = asSInt(_T_185) node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0))) node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = or(_T_172, _T_177) node _T_219 = or(_T_218, _T_182) node _T_220 = or(_T_219, _T_187) node _T_221 = or(_T_220, _T_192) node _T_222 = or(_T_221, _T_197) node _T_223 = or(_T_222, _T_202) node _T_224 = or(_T_223, _T_207) node _T_225 = or(_T_224, _T_212) node _T_226 = or(_T_225, _T_217) node _T_227 = and(_T_167, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = and(UInt<1>(0h0), _T_228) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_229, UInt<1>(0h1), "") : assert_3 node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(source_ok, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_237 = asUInt(reset) node _T_238 = eq(_T_237, UInt<1>(0h0)) when _T_238 : node _T_239 = eq(_T_236, UInt<1>(0h0)) when _T_239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_236, UInt<1>(0h1), "") : assert_5 node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(is_aligned, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_243, UInt<1>(0h1), "") : assert_7 node _T_247 = not(io.in.a.bits.mask) node _T_248 = eq(_T_247, UInt<1>(0h0)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_248, UInt<1>(0h1), "") : assert_8 node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(_T_252, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_252, UInt<1>(0h1), "") : assert_9 node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_256 : node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_260 = shr(io.in.a.bits.source, 2) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_8) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h1)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_9) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<2>(0h2)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_10) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h3)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_11) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _T_284 = or(_T_265, _T_271) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_283) node _T_287 = and(_T_259, _T_286) node _T_288 = or(UInt<1>(0h0), _T_287) node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = or(_T_294, _T_299) node _T_331 = or(_T_330, _T_304) node _T_332 = or(_T_331, _T_309) node _T_333 = or(_T_332, _T_314) node _T_334 = or(_T_333, _T_319) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_329) node _T_337 = and(_T_289, _T_336) node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_339 = or(UInt<1>(0h0), _T_338) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = or(_T_344, _T_349) node _T_351 = and(_T_339, _T_350) node _T_352 = or(UInt<1>(0h0), _T_337) node _T_353 = or(_T_352, _T_351) node _T_354 = and(_T_288, _T_353) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_354, UInt<1>(0h1), "") : assert_10 node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_366, _T_371) node _T_413 = or(_T_412, _T_376) node _T_414 = or(_T_413, _T_381) node _T_415 = or(_T_414, _T_386) node _T_416 = or(_T_415, _T_391) node _T_417 = or(_T_416, _T_396) node _T_418 = or(_T_417, _T_401) node _T_419 = or(_T_418, _T_406) node _T_420 = or(_T_419, _T_411) node _T_421 = and(_T_361, _T_420) node _T_422 = or(UInt<1>(0h0), _T_421) node _T_423 = and(UInt<1>(0h0), _T_422) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_423, UInt<1>(0h1), "") : assert_11 node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(source_ok, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_430, UInt<1>(0h1), "") : assert_13 node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(is_aligned, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_437, UInt<1>(0h1), "") : assert_15 node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_441, UInt<1>(0h1), "") : assert_16 node _T_445 = not(io.in.a.bits.mask) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_446, UInt<1>(0h1), "") : assert_17 node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_450, UInt<1>(0h1), "") : assert_18 node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_454 : node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_12) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_464 = shr(io.in.a.bits.source, 2) node _T_465 = eq(_T_464, UInt<1>(0h1)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_13) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_469 = and(_T_467, _T_468) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_470 = shr(io.in.a.bits.source, 2) node _T_471 = eq(_T_470, UInt<2>(0h2)) node _T_472 = leq(UInt<1>(0h0), uncommonBits_14) node _T_473 = and(_T_471, _T_472) node _T_474 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_475 = and(_T_473, _T_474) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_476 = shr(io.in.a.bits.source, 2) node _T_477 = eq(_T_476, UInt<2>(0h3)) node _T_478 = leq(UInt<1>(0h0), uncommonBits_15) node _T_479 = and(_T_477, _T_478) node _T_480 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_481 = and(_T_479, _T_480) node _T_482 = or(_T_463, _T_469) node _T_483 = or(_T_482, _T_475) node _T_484 = or(_T_483, _T_481) node _T_485 = and(_T_457, _T_484) node _T_486 = or(UInt<1>(0h0), _T_485) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_486, UInt<1>(0h1), "") : assert_19 node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_492 = and(_T_490, _T_491) node _T_493 = or(UInt<1>(0h0), _T_492) node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = and(_T_493, _T_498) node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_502 = and(_T_500, _T_501) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = or(_T_508, _T_513) node _T_550 = or(_T_549, _T_518) node _T_551 = or(_T_550, _T_523) node _T_552 = or(_T_551, _T_528) node _T_553 = or(_T_552, _T_533) node _T_554 = or(_T_553, _T_538) node _T_555 = or(_T_554, _T_543) node _T_556 = or(_T_555, _T_548) node _T_557 = and(_T_503, _T_556) node _T_558 = or(UInt<1>(0h0), _T_499) node _T_559 = or(_T_558, _T_557) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_559, UInt<1>(0h1), "") : assert_20 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_569, UInt<1>(0h1), "") : assert_23 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_573, UInt<1>(0h1), "") : assert_24 node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_577, UInt<1>(0h1), "") : assert_25 node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_581 : node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_584 = and(_T_582, _T_583) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_585 = shr(io.in.a.bits.source, 2) node _T_586 = eq(_T_585, UInt<1>(0h0)) node _T_587 = leq(UInt<1>(0h0), uncommonBits_16) node _T_588 = and(_T_586, _T_587) node _T_589 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_590 = and(_T_588, _T_589) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_591 = shr(io.in.a.bits.source, 2) node _T_592 = eq(_T_591, UInt<1>(0h1)) node _T_593 = leq(UInt<1>(0h0), uncommonBits_17) node _T_594 = and(_T_592, _T_593) node _T_595 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_596 = and(_T_594, _T_595) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<2>(0h2)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_18) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<2>(0h3)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_19) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(_T_590, _T_596) node _T_610 = or(_T_609, _T_602) node _T_611 = or(_T_610, _T_608) node _T_612 = and(_T_584, _T_611) node _T_613 = or(UInt<1>(0h0), _T_612) node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = and(_T_617, _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_649 = cvt(_T_648) node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000))) node _T_651 = asSInt(_T_650) node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0))) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = or(_T_632, _T_637) node _T_669 = or(_T_668, _T_642) node _T_670 = or(_T_669, _T_647) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_657) node _T_673 = or(_T_672, _T_662) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_627, _T_674) node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = or(UInt<1>(0h0), _T_623) node _T_684 = or(_T_683, _T_675) node _T_685 = or(_T_684, _T_682) node _T_686 = and(_T_613, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_686, UInt<1>(0h1), "") : assert_26 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(source_ok, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(is_aligned, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_696, UInt<1>(0h1), "") : assert_29 node _T_700 = eq(io.in.a.bits.mask, mask) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_700, UInt<1>(0h1), "") : assert_30 node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_704 : node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_707 = and(_T_705, _T_706) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_708 = shr(io.in.a.bits.source, 2) node _T_709 = eq(_T_708, UInt<1>(0h0)) node _T_710 = leq(UInt<1>(0h0), uncommonBits_20) node _T_711 = and(_T_709, _T_710) node _T_712 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_714 = shr(io.in.a.bits.source, 2) node _T_715 = eq(_T_714, UInt<1>(0h1)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_21) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_720 = shr(io.in.a.bits.source, 2) node _T_721 = eq(_T_720, UInt<2>(0h2)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_22) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<2>(0h3)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_23) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(_T_713, _T_719) node _T_733 = or(_T_732, _T_725) node _T_734 = or(_T_733, _T_731) node _T_735 = and(_T_707, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = and(_T_740, _T_745) node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = or(_T_755, _T_760) node _T_792 = or(_T_791, _T_765) node _T_793 = or(_T_792, _T_770) node _T_794 = or(_T_793, _T_775) node _T_795 = or(_T_794, _T_780) node _T_796 = or(_T_795, _T_785) node _T_797 = or(_T_796, _T_790) node _T_798 = and(_T_750, _T_797) node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = and(_T_799, _T_804) node _T_806 = or(UInt<1>(0h0), _T_746) node _T_807 = or(_T_806, _T_798) node _T_808 = or(_T_807, _T_805) node _T_809 = and(_T_736, _T_808) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_809, UInt<1>(0h1), "") : assert_31 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(source_ok, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(is_aligned, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_819, UInt<1>(0h1), "") : assert_34 node _T_823 = not(mask) node _T_824 = and(io.in.a.bits.mask, _T_823) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_825, UInt<1>(0h1), "") : assert_35 node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_829 : node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_832 = and(_T_830, _T_831) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_24) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<1>(0h1)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_25) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<2>(0h2)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_26) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<2>(0h3)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_27) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = or(_T_838, _T_844) node _T_858 = or(_T_857, _T_850) node _T_859 = or(_T_858, _T_856) node _T_860 = and(_T_832, _T_859) node _T_861 = or(UInt<1>(0h0), _T_860) node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _T_865 = or(UInt<1>(0h0), _T_864) node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_877 = cvt(_T_876) node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000))) node _T_879 = asSInt(_T_878) node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<17>(0h10000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<27>(0h4000000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<29>(0h10000000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = or(_T_870, _T_875) node _T_912 = or(_T_911, _T_880) node _T_913 = or(_T_912, _T_885) node _T_914 = or(_T_913, _T_890) node _T_915 = or(_T_914, _T_895) node _T_916 = or(_T_915, _T_900) node _T_917 = or(_T_916, _T_905) node _T_918 = or(_T_917, _T_910) node _T_919 = and(_T_865, _T_918) node _T_920 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_921 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<17>(0h10000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = and(_T_920, _T_925) node _T_927 = or(UInt<1>(0h0), _T_919) node _T_928 = or(_T_927, _T_926) node _T_929 = and(_T_861, _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_929, UInt<1>(0h1), "") : assert_36 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(source_ok, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(is_aligned, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_939 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_939, UInt<1>(0h1), "") : assert_39 node _T_943 = eq(io.in.a.bits.mask, mask) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_943, UInt<1>(0h1), "") : assert_40 node _T_947 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_947 : node _T_948 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_949 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<1>(0h0)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_28) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_957 = shr(io.in.a.bits.source, 2) node _T_958 = eq(_T_957, UInt<1>(0h1)) node _T_959 = leq(UInt<1>(0h0), uncommonBits_29) node _T_960 = and(_T_958, _T_959) node _T_961 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_962 = and(_T_960, _T_961) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_963 = shr(io.in.a.bits.source, 2) node _T_964 = eq(_T_963, UInt<2>(0h2)) node _T_965 = leq(UInt<1>(0h0), uncommonBits_30) node _T_966 = and(_T_964, _T_965) node _T_967 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_968 = and(_T_966, _T_967) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_969 = shr(io.in.a.bits.source, 2) node _T_970 = eq(_T_969, UInt<2>(0h3)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_31) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_974 = and(_T_972, _T_973) node _T_975 = or(_T_956, _T_962) node _T_976 = or(_T_975, _T_968) node _T_977 = or(_T_976, _T_974) node _T_978 = and(_T_950, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_981 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _T_983 = or(UInt<1>(0h0), _T_982) node _T_984 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<14>(0h2000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<13>(0h1000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<18>(0h2f000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<17>(0h10000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<13>(0h1000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1010 = cvt(_T_1009) node _T_1011 = and(_T_1010, asSInt(UInt<17>(0h10000))) node _T_1012 = asSInt(_T_1011) node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0))) node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<29>(0h10000000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = or(_T_988, _T_993) node _T_1030 = or(_T_1029, _T_998) node _T_1031 = or(_T_1030, _T_1003) node _T_1032 = or(_T_1031, _T_1008) node _T_1033 = or(_T_1032, _T_1013) node _T_1034 = or(_T_1033, _T_1018) node _T_1035 = or(_T_1034, _T_1023) node _T_1036 = or(_T_1035, _T_1028) node _T_1037 = and(_T_983, _T_1036) node _T_1038 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1039 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = and(_T_1038, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_1037) node _T_1046 = or(_T_1045, _T_1044) node _T_1047 = and(_T_979, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_41 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1057 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_44 node _T_1061 = eq(io.in.a.bits.mask, mask) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_45 node _T_1065 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1065 : node _T_1066 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1067 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1068 = and(_T_1066, _T_1067) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1069 = shr(io.in.a.bits.source, 2) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) node _T_1071 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1074 = and(_T_1072, _T_1073) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1075 = shr(io.in.a.bits.source, 2) node _T_1076 = eq(_T_1075, UInt<1>(0h1)) node _T_1077 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1080 = and(_T_1078, _T_1079) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1081 = shr(io.in.a.bits.source, 2) node _T_1082 = eq(_T_1081, UInt<2>(0h2)) node _T_1083 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1086 = and(_T_1084, _T_1085) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<2>(0h3)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = or(_T_1074, _T_1080) node _T_1094 = or(_T_1093, _T_1086) node _T_1095 = or(_T_1094, _T_1092) node _T_1096 = and(_T_1068, _T_1095) node _T_1097 = or(UInt<1>(0h0), _T_1096) node _T_1098 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1099 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = or(UInt<1>(0h0), _T_1100) node _T_1102 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<13>(0h1000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = and(_T_1101, _T_1106) node _T_1108 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1109 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1110 = cvt(_T_1109) node _T_1111 = and(_T_1110, asSInt(UInt<14>(0h2000))) node _T_1112 = asSInt(_T_1111) node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0))) node _T_1114 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<17>(0h10000))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<18>(0h2f000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<13>(0h1000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<27>(0h4000000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = or(_T_1113, _T_1118) node _T_1145 = or(_T_1144, _T_1123) node _T_1146 = or(_T_1145, _T_1128) node _T_1147 = or(_T_1146, _T_1133) node _T_1148 = or(_T_1147, _T_1138) node _T_1149 = or(_T_1148, _T_1143) node _T_1150 = and(_T_1108, _T_1149) node _T_1151 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1152 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1156 = cvt(_T_1155) node _T_1157 = and(_T_1156, asSInt(UInt<17>(0h10000))) node _T_1158 = asSInt(_T_1157) node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0))) node _T_1160 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<29>(0h10000000))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1154, _T_1165) node _T_1167 = or(UInt<1>(0h0), _T_1107) node _T_1168 = or(_T_1167, _T_1150) node _T_1169 = or(_T_1168, _T_1166) node _T_1170 = and(_T_1097, _T_1169) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_46 node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(source_ok, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(is_aligned, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1180 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_49 node _T_1184 = eq(io.in.a.bits.mask, mask) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_50 node _T_1188 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1192 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 2) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 2) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 2) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1196 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1196 : node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(source_ok_1, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1200 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_54 node _T_1204 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_55 node _T_1208 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_56 node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_57 node _T_1216 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1216 : node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(source_ok_1, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(sink_ok, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1223 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_60 node _T_1227 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_61 node _T_1231 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_62 node _T_1235 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_63 node _T_1239 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1240 = or(UInt<1>(0h1), _T_1239) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_64 node _T_1244 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1244 : node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(source_ok_1, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(sink_ok, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1251 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_67 node _T_1255 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_68 node _T_1259 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_69 node _T_1263 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1264 = or(_T_1263, io.in.d.bits.corrupt) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_70 node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1269 = or(UInt<1>(0h1), _T_1268) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_71 node _T_1273 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1273 : node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(source_ok_1, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1277 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_73 node _T_1281 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_74 node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1286 = or(UInt<1>(0h1), _T_1285) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_75 node _T_1290 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1290 : node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok_1, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1294 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_77 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(_T_1298, io.in.d.bits.corrupt) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_78 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_79 node _T_1308 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_81 node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_82 node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1321 = or(UInt<1>(0h1), _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1325 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1329 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1333 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(_T_1333, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1333, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1337 = eq(a_first, UInt<1>(0h0)) node _T_1338 = and(io.in.a.valid, _T_1337) when _T_1338 : node _T_1339 = eq(io.in.a.bits.opcode, opcode) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_87 node _T_1343 = eq(io.in.a.bits.param, param) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_88 node _T_1347 = eq(io.in.a.bits.size, size) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_89 node _T_1351 = eq(io.in.a.bits.source, source) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_90 node _T_1355 = eq(io.in.a.bits.address, address) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_91 node _T_1359 = and(io.in.a.ready, io.in.a.valid) node _T_1360 = and(_T_1359, a_first) when _T_1360 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1361 = eq(d_first, UInt<1>(0h0)) node _T_1362 = and(io.in.d.valid, _T_1361) when _T_1362 : node _T_1363 = eq(io.in.d.bits.opcode, opcode_1) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_92 node _T_1367 = eq(io.in.d.bits.param, param_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_93 node _T_1371 = eq(io.in.d.bits.size, size_1) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_94 node _T_1375 = eq(io.in.d.bits.source, source_1) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_95 node _T_1379 = eq(io.in.d.bits.sink, sink) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_96 node _T_1383 = eq(io.in.d.bits.denied, denied) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_97 node _T_1387 = and(io.in.d.ready, io.in.d.valid) node _T_1388 = and(_T_1387, d_first) when _T_1388 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<16> connect a_set, UInt<16>(0h0) wire a_set_wo_ready : UInt<16> connect a_set_wo_ready, UInt<16>(0h0) wire a_opcodes_set : UInt<64> connect a_opcodes_set, UInt<64>(0h0) wire a_sizes_set : UInt<128> connect a_sizes_set, UInt<128>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1389 = and(io.in.a.valid, a_first_1) node _T_1390 = and(_T_1389, UInt<1>(0h1)) when _T_1390 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1391 = and(io.in.a.ready, io.in.a.valid) node _T_1392 = and(_T_1391, a_first_1) node _T_1393 = and(_T_1392, UInt<1>(0h1)) when _T_1393 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1394 = dshr(inflight, io.in.a.bits.source) node _T_1395 = bits(_T_1394, 0, 0) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<16> connect d_clr, UInt<16>(0h0) wire d_clr_wo_ready : UInt<16> connect d_clr_wo_ready, UInt<16>(0h0) wire d_opcodes_clr : UInt<64> connect d_opcodes_clr, UInt<64>(0h0) wire d_sizes_clr : UInt<128> connect d_sizes_clr, UInt<128>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1400 = and(io.in.d.valid, d_first_1) node _T_1401 = and(_T_1400, UInt<1>(0h1)) node _T_1402 = eq(d_release_ack, UInt<1>(0h0)) node _T_1403 = and(_T_1401, _T_1402) when _T_1403 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1404 = and(io.in.d.ready, io.in.d.valid) node _T_1405 = and(_T_1404, d_first_1) node _T_1406 = and(_T_1405, UInt<1>(0h1)) node _T_1407 = eq(d_release_ack, UInt<1>(0h0)) node _T_1408 = and(_T_1406, _T_1407) when _T_1408 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1409 = and(io.in.d.valid, d_first_1) node _T_1410 = and(_T_1409, UInt<1>(0h1)) node _T_1411 = eq(d_release_ack, UInt<1>(0h0)) node _T_1412 = and(_T_1410, _T_1411) when _T_1412 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1413 = dshr(inflight, io.in.d.bits.source) node _T_1414 = bits(_T_1413, 0, 0) node _T_1415 = or(_T_1414, same_cycle_resp) node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(_T_1415, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1415, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1419 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1420 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1421 = or(_T_1419, _T_1420) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_100 node _T_1425 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_101 else : node _T_1429 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1431 = or(_T_1429, _T_1430) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_102 node _T_1435 = eq(io.in.d.bits.size, a_size_lookup) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_103 node _T_1439 = and(io.in.d.valid, d_first_1) node _T_1440 = and(_T_1439, a_first_1) node _T_1441 = and(_T_1440, io.in.a.valid) node _T_1442 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = eq(d_release_ack, UInt<1>(0h0)) node _T_1445 = and(_T_1443, _T_1444) when _T_1445 : node _T_1446 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1447 = or(_T_1446, io.in.a.ready) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_104 node _T_1451 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1452 = orr(a_set_wo_ready) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) node _T_1454 = or(_T_1451, _T_1453) node _T_1455 = asUInt(reset) node _T_1456 = eq(_T_1455, UInt<1>(0h0)) when _T_1456 : node _T_1457 = eq(_T_1454, UInt<1>(0h0)) when _T_1457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1454, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_26 node _T_1458 = orr(inflight) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) node _T_1460 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1461 = or(_T_1459, _T_1460) node _T_1462 = lt(watchdog, plusarg_reader.out) node _T_1463 = or(_T_1461, _T_1462) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1467 = and(io.in.a.ready, io.in.a.valid) node _T_1468 = and(io.in.d.ready, io.in.d.valid) node _T_1469 = or(_T_1467, _T_1468) when _T_1469 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<16> connect c_set, UInt<16>(0h0) wire c_set_wo_ready : UInt<16> connect c_set_wo_ready, UInt<16>(0h0) wire c_opcodes_set : UInt<64> connect c_opcodes_set, UInt<64>(0h0) wire c_sizes_set : UInt<128> connect c_sizes_set, UInt<128>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1470 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1471 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1472 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1473 = and(_T_1471, _T_1472) node _T_1474 = and(_T_1470, _T_1473) when _T_1474 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1475 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1476 = and(_T_1475, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1477 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1478 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = and(_T_1476, _T_1479) when _T_1480 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1481 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1482 = bits(_T_1481, 0, 0) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(_T_1483, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1483, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<16> connect d_clr_1, UInt<16>(0h0) wire d_clr_wo_ready_1 : UInt<16> connect d_clr_wo_ready_1, UInt<16>(0h0) wire d_opcodes_clr_1 : UInt<64> connect d_opcodes_clr_1, UInt<64>(0h0) wire d_sizes_clr_1 : UInt<128> connect d_sizes_clr_1, UInt<128>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1487 = and(io.in.d.valid, d_first_2) node _T_1488 = and(_T_1487, UInt<1>(0h1)) node _T_1489 = and(_T_1488, d_release_ack_1) when _T_1489 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1490 = and(io.in.d.ready, io.in.d.valid) node _T_1491 = and(_T_1490, d_first_2) node _T_1492 = and(_T_1491, UInt<1>(0h1)) node _T_1493 = and(_T_1492, d_release_ack_1) when _T_1493 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1494 = and(io.in.d.valid, d_first_2) node _T_1495 = and(_T_1494, UInt<1>(0h1)) node _T_1496 = and(_T_1495, d_release_ack_1) when _T_1496 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1497 = dshr(inflight_1, io.in.d.bits.source) node _T_1498 = bits(_T_1497, 0, 0) node _T_1499 = or(_T_1498, same_cycle_resp_1) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1503 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_109 else : node _T_1507 = eq(io.in.d.bits.size, c_size_lookup) node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(_T_1507, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1507, UInt<1>(0h1), "") : assert_110 node _T_1511 = and(io.in.d.valid, d_first_2) node _T_1512 = and(_T_1511, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1513 = and(_T_1512, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1514 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = and(_T_1515, d_release_ack_1) node _T_1517 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1518 = and(_T_1516, _T_1517) when _T_1518 : node _T_1519 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1520 = or(_T_1519, _WIRE_23.ready) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_111 node _T_1524 = orr(c_set_wo_ready) when _T_1524 : node _T_1525 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1526 = asUInt(reset) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) when _T_1527 : node _T_1528 = eq(_T_1525, UInt<1>(0h0)) when _T_1528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1525, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_27 node _T_1529 = orr(inflight_1) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) node _T_1531 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1532 = or(_T_1530, _T_1531) node _T_1533 = lt(watchdog_1, plusarg_reader_1.out) node _T_1534 = or(_T_1532, _T_1533) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1538 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1539 = and(io.in.d.ready, io.in.d.valid) node _T_1540 = or(_T_1538, _T_1539) when _T_1540 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_13( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1467 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1467; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1467; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1540 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1540; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1467 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1393 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1393 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1393 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1393 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1393 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1439 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1439 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1408 = _T_1540 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1408 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1408 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1408 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1511 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1511 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1493 = _T_1540 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1493 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1493 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1493 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_134 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_134 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_28 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_9 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_9 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_10 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_10 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_11 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_11 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_12 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_12 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_13 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_13 : connect states[7].g, UInt<3>(0h2) node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_14 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_14 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_15 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_15 : connect states[9].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_29 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_29 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_30 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_30 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_31 = and(io.router_req.ready, io.router_req.valid) when _T_31 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_32 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_33 = or(_T_32, vcalloc_vals[2]) node _T_34 = or(_T_33, vcalloc_vals[3]) node _T_35 = or(_T_34, vcalloc_vals[4]) node _T_36 = or(_T_35, vcalloc_vals[5]) node _T_37 = or(_T_36, vcalloc_vals[6]) node _T_38 = or(_T_37, vcalloc_vals[7]) node _T_39 = or(_T_38, vcalloc_vals[8]) node _T_40 = or(_T_39, vcalloc_vals[9]) when _T_40 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>[10] node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24[0], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410) node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_24[1], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435) node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436) node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446 connect _io_vcalloc_req_bits_WIRE_24[2], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450) node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451) node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452) node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453) node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454) node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455) node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465 connect _io_vcalloc_req_bits_WIRE_24[3], _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467) node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468) node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469) node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470) node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475) wire _io_vcalloc_req_bits_WIRE_29 : UInt<1> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484 connect _io_vcalloc_req_bits_WIRE_24[4], _io_vcalloc_req_bits_WIRE_29 node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503 connect _io_vcalloc_req_bits_WIRE_24[5], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_512 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_513 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_504, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_518 = or(_io_vcalloc_req_bits_T_517, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_519 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_510) node _io_vcalloc_req_bits_T_520 = or(_io_vcalloc_req_bits_T_519, _io_vcalloc_req_bits_T_511) node _io_vcalloc_req_bits_T_521 = or(_io_vcalloc_req_bits_T_520, _io_vcalloc_req_bits_T_512) node _io_vcalloc_req_bits_T_522 = or(_io_vcalloc_req_bits_T_521, _io_vcalloc_req_bits_T_513) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_522 connect _io_vcalloc_req_bits_WIRE_24[6], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_527 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_528 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_529 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_530 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_531 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_532 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_533 = or(_io_vcalloc_req_bits_T_523, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_534 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_525) node _io_vcalloc_req_bits_T_535 = or(_io_vcalloc_req_bits_T_534, _io_vcalloc_req_bits_T_526) node _io_vcalloc_req_bits_T_536 = or(_io_vcalloc_req_bits_T_535, _io_vcalloc_req_bits_T_527) node _io_vcalloc_req_bits_T_537 = or(_io_vcalloc_req_bits_T_536, _io_vcalloc_req_bits_T_528) node _io_vcalloc_req_bits_T_538 = or(_io_vcalloc_req_bits_T_537, _io_vcalloc_req_bits_T_529) node _io_vcalloc_req_bits_T_539 = or(_io_vcalloc_req_bits_T_538, _io_vcalloc_req_bits_T_530) node _io_vcalloc_req_bits_T_540 = or(_io_vcalloc_req_bits_T_539, _io_vcalloc_req_bits_T_531) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_540, _io_vcalloc_req_bits_T_532) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_541 connect _io_vcalloc_req_bits_WIRE_24[7], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_542 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_543 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_544 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_545 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_546 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_547 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_543) node _io_vcalloc_req_bits_T_553 = or(_io_vcalloc_req_bits_T_552, _io_vcalloc_req_bits_T_544) node _io_vcalloc_req_bits_T_554 = or(_io_vcalloc_req_bits_T_553, _io_vcalloc_req_bits_T_545) node _io_vcalloc_req_bits_T_555 = or(_io_vcalloc_req_bits_T_554, _io_vcalloc_req_bits_T_546) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_555, _io_vcalloc_req_bits_T_547) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_548) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_551) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_560 connect _io_vcalloc_req_bits_WIRE_24[8], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_561 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_562 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_562) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_563) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_578 = or(_io_vcalloc_req_bits_T_577, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_579 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_579 connect _io_vcalloc_req_bits_WIRE_24[9], _io_vcalloc_req_bits_WIRE_34 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_24 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_587 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_588 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_589 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_580, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_593 = or(_io_vcalloc_req_bits_T_592, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_594 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_585) node _io_vcalloc_req_bits_T_595 = or(_io_vcalloc_req_bits_T_594, _io_vcalloc_req_bits_T_586) node _io_vcalloc_req_bits_T_596 = or(_io_vcalloc_req_bits_T_595, _io_vcalloc_req_bits_T_587) node _io_vcalloc_req_bits_T_597 = or(_io_vcalloc_req_bits_T_596, _io_vcalloc_req_bits_T_588) node _io_vcalloc_req_bits_T_598 = or(_io_vcalloc_req_bits_T_597, _io_vcalloc_req_bits_T_589) wire _io_vcalloc_req_bits_WIRE_35 : UInt<4> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_598 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_35 wire _io_vcalloc_req_bits_WIRE_36 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_602 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_603 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_604 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_605 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_606 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_607 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = or(_io_vcalloc_req_bits_T_599, _io_vcalloc_req_bits_T_600) node _io_vcalloc_req_bits_T_610 = or(_io_vcalloc_req_bits_T_609, _io_vcalloc_req_bits_T_601) node _io_vcalloc_req_bits_T_611 = or(_io_vcalloc_req_bits_T_610, _io_vcalloc_req_bits_T_602) node _io_vcalloc_req_bits_T_612 = or(_io_vcalloc_req_bits_T_611, _io_vcalloc_req_bits_T_603) node _io_vcalloc_req_bits_T_613 = or(_io_vcalloc_req_bits_T_612, _io_vcalloc_req_bits_T_604) node _io_vcalloc_req_bits_T_614 = or(_io_vcalloc_req_bits_T_613, _io_vcalloc_req_bits_T_605) node _io_vcalloc_req_bits_T_615 = or(_io_vcalloc_req_bits_T_614, _io_vcalloc_req_bits_T_606) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_615, _io_vcalloc_req_bits_T_607) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_608) wire _io_vcalloc_req_bits_WIRE_37 : UInt<3> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_617 connect _io_vcalloc_req_bits_WIRE_36.egress_node_id, _io_vcalloc_req_bits_WIRE_37 node _io_vcalloc_req_bits_T_618 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_619 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_620 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_621 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_622 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_619) node _io_vcalloc_req_bits_T_629 = or(_io_vcalloc_req_bits_T_628, _io_vcalloc_req_bits_T_620) node _io_vcalloc_req_bits_T_630 = or(_io_vcalloc_req_bits_T_629, _io_vcalloc_req_bits_T_621) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_630, _io_vcalloc_req_bits_T_622) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_623) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_627) wire _io_vcalloc_req_bits_WIRE_38 : UInt<4> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_636 connect _io_vcalloc_req_bits_WIRE_36.egress_node, _io_vcalloc_req_bits_WIRE_38 node _io_vcalloc_req_bits_T_637 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_637, _io_vcalloc_req_bits_T_638) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_653 = or(_io_vcalloc_req_bits_T_652, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_654 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_645) node _io_vcalloc_req_bits_T_655 = or(_io_vcalloc_req_bits_T_654, _io_vcalloc_req_bits_T_646) wire _io_vcalloc_req_bits_WIRE_39 : UInt<2> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_655 connect _io_vcalloc_req_bits_WIRE_36.ingress_node_id, _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_662 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_663 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_664 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_665 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_656, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_668 = or(_io_vcalloc_req_bits_T_667, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_669 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_660) node _io_vcalloc_req_bits_T_670 = or(_io_vcalloc_req_bits_T_669, _io_vcalloc_req_bits_T_661) node _io_vcalloc_req_bits_T_671 = or(_io_vcalloc_req_bits_T_670, _io_vcalloc_req_bits_T_662) node _io_vcalloc_req_bits_T_672 = or(_io_vcalloc_req_bits_T_671, _io_vcalloc_req_bits_T_663) node _io_vcalloc_req_bits_T_673 = or(_io_vcalloc_req_bits_T_672, _io_vcalloc_req_bits_T_664) node _io_vcalloc_req_bits_T_674 = or(_io_vcalloc_req_bits_T_673, _io_vcalloc_req_bits_T_665) wire _io_vcalloc_req_bits_WIRE_40 : UInt<4> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_674 connect _io_vcalloc_req_bits_WIRE_36.ingress_node, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_677 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_678 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_679 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_680 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_681 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_682 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = or(_io_vcalloc_req_bits_T_675, _io_vcalloc_req_bits_T_676) node _io_vcalloc_req_bits_T_686 = or(_io_vcalloc_req_bits_T_685, _io_vcalloc_req_bits_T_677) node _io_vcalloc_req_bits_T_687 = or(_io_vcalloc_req_bits_T_686, _io_vcalloc_req_bits_T_678) node _io_vcalloc_req_bits_T_688 = or(_io_vcalloc_req_bits_T_687, _io_vcalloc_req_bits_T_679) node _io_vcalloc_req_bits_T_689 = or(_io_vcalloc_req_bits_T_688, _io_vcalloc_req_bits_T_680) node _io_vcalloc_req_bits_T_690 = or(_io_vcalloc_req_bits_T_689, _io_vcalloc_req_bits_T_681) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_690, _io_vcalloc_req_bits_T_682) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_683) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_684) wire _io_vcalloc_req_bits_WIRE_41 : UInt<3> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_693 connect _io_vcalloc_req_bits_WIRE_36.vnet_id, _io_vcalloc_req_bits_WIRE_41 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_36 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`0`[8] invalidate vcalloc_reqs[0].vc_sel.`0`[9] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[8] invalidate vcalloc_reqs[0].vc_sel.`1`[9] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[8] invalidate vcalloc_reqs[0].vc_sel.`2`[9] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`0`[5] invalidate vcalloc_reqs[1].vc_sel.`0`[6] invalidate vcalloc_reqs[1].vc_sel.`0`[7] invalidate vcalloc_reqs[1].vc_sel.`0`[8] invalidate vcalloc_reqs[1].vc_sel.`0`[9] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[5] invalidate vcalloc_reqs[1].vc_sel.`1`[6] invalidate vcalloc_reqs[1].vc_sel.`1`[7] invalidate vcalloc_reqs[1].vc_sel.`1`[8] invalidate vcalloc_reqs[1].vc_sel.`1`[9] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[3] invalidate vcalloc_reqs[1].vc_sel.`2`[4] invalidate vcalloc_reqs[1].vc_sel.`2`[5] invalidate vcalloc_reqs[1].vc_sel.`2`[6] invalidate vcalloc_reqs[1].vc_sel.`2`[7] invalidate vcalloc_reqs[1].vc_sel.`2`[8] invalidate vcalloc_reqs[1].vc_sel.`2`[9] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`0`[5] invalidate vcalloc_reqs[2].vc_sel.`0`[6] invalidate vcalloc_reqs[2].vc_sel.`0`[7] invalidate vcalloc_reqs[2].vc_sel.`0`[8] invalidate vcalloc_reqs[2].vc_sel.`0`[9] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[5] invalidate vcalloc_reqs[2].vc_sel.`1`[6] invalidate vcalloc_reqs[2].vc_sel.`1`[7] invalidate vcalloc_reqs[2].vc_sel.`1`[8] invalidate vcalloc_reqs[2].vc_sel.`1`[9] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[3] invalidate vcalloc_reqs[2].vc_sel.`2`[4] invalidate vcalloc_reqs[2].vc_sel.`2`[5] invalidate vcalloc_reqs[2].vc_sel.`2`[6] invalidate vcalloc_reqs[2].vc_sel.`2`[7] invalidate vcalloc_reqs[2].vc_sel.`2`[8] invalidate vcalloc_reqs[2].vc_sel.`2`[9] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].flow, states[3].flow node _T_41 = bits(vcalloc_sel, 3, 3) node _T_42 = and(vcalloc_vals[3], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_44 = bits(vcalloc_sel, 4, 4) node _T_45 = and(vcalloc_vals[4], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].flow, states[5].flow node _T_47 = bits(vcalloc_sel, 5, 5) node _T_48 = and(vcalloc_vals[5], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].flow, states[6].flow node _T_50 = bits(vcalloc_sel, 6, 6) node _T_51 = and(vcalloc_vals[6], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].flow, states[7].flow node _T_53 = bits(vcalloc_sel, 7, 7) node _T_54 = and(vcalloc_vals[7], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[7].g, UInt<3>(0h3) node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].flow, states[8].flow node _T_56 = bits(vcalloc_sel, 8, 8) node _T_57 = and(vcalloc_vals[8], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].flow, states[9].flow node _T_59 = bits(vcalloc_sel, 9, 9) node _T_60 = and(vcalloc_vals[9], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_62 : node _T_63 = bits(vcalloc_sel, 0, 0) when _T_63 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_64 = eq(states[0].g, UInt<3>(0h2)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_64, UInt<1>(0h1), "") : assert_3 node _T_68 = bits(vcalloc_sel, 1, 1) when _T_68 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_69 = eq(states[1].g, UInt<3>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 node _T_73 = bits(vcalloc_sel, 2, 2) when _T_73 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_74 = eq(states[2].g, UInt<3>(0h2)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = bits(vcalloc_sel, 3, 3) when _T_78 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_79 = eq(states[3].g, UInt<3>(0h2)) node _T_80 = asUInt(reset) node _T_81 = eq(_T_80, UInt<1>(0h0)) when _T_81 : node _T_82 = eq(_T_79, UInt<1>(0h0)) when _T_82 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_79, UInt<1>(0h1), "") : assert_6 node _T_83 = bits(vcalloc_sel, 4, 4) when _T_83 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_84 = eq(states[4].g, UInt<3>(0h2)) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_84, UInt<1>(0h1), "") : assert_7 node _T_88 = bits(vcalloc_sel, 5, 5) when _T_88 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_89 = eq(states[5].g, UInt<3>(0h2)) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_89, UInt<1>(0h1), "") : assert_8 node _T_93 = bits(vcalloc_sel, 6, 6) when _T_93 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_94 = eq(states[6].g, UInt<3>(0h2)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = bits(vcalloc_sel, 7, 7) when _T_98 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_99 = eq(states[7].g, UInt<3>(0h2)) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = bits(vcalloc_sel, 8, 8) when _T_103 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].g, UInt<3>(0h3) node _T_104 = eq(states[8].g, UInt<3>(0h2)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_104, UInt<1>(0h1), "") : assert_11 node _T_108 = bits(vcalloc_sel, 9, 9) when _T_108 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].g, UInt<3>(0h3) node _T_109 = eq(states[9].g, UInt<3>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_109, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_349 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[9] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[9] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[9] node credit_available_lo_lo = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[3].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[3].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_hi_1 = cat(states[3].vc_sel.`1`[4], states[3].vc_sel.`1`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[3].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[3].vc_sel.`1`[6], states[3].vc_sel.`1`[5]) node credit_available_hi_hi_hi_1 = cat(states[3].vc_sel.`1`[9], states[3].vc_sel.`1`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[3].vc_sel.`1`[7]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_hi_2 = cat(states[3].vc_sel.`2`[4], states[3].vc_sel.`2`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[3].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[3].vc_sel.`2`[6], states[3].vc_sel.`2`[5]) node credit_available_hi_hi_hi_2 = cat(states[3].vc_sel.`2`[9], states[3].vc_sel.`2`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[3].vc_sel.`2`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, io.out_credit_available.`1`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_4 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, io.out_credit_available.`1`[7]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`2`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`2`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[8], states[3].vc_sel.`1`[8] connect salloc_arb.io.in[3].bits.vc_sel.`1`[9], states[3].vc_sel.`1`[9] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[8], states[3].vc_sel.`2`[8] connect salloc_arb.io.in[3].bits.vc_sel.`2`[9], states[3].vc_sel.`2`[9] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_113 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_114 = and(_T_113, input_buffer.io.deq[3].bits.tail) when _T_114 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_6 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, states[4].vc_sel.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, states[4].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6) node credit_available_lo_lo_7 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_hi_7 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3]) node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, states[4].vc_sel.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(states[4].vc_sel.`1`[6], states[4].vc_sel.`1`[5]) node credit_available_hi_hi_hi_7 = cat(states[4].vc_sel.`1`[9], states[4].vc_sel.`1`[8]) node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, states[4].vc_sel.`1`[7]) node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7) node credit_available_lo_lo_8 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_hi_8 = cat(states[4].vc_sel.`2`[4], states[4].vc_sel.`2`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[4].vc_sel.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[4].vc_sel.`2`[6], states[4].vc_sel.`2`[5]) node credit_available_hi_hi_hi_8 = cat(states[4].vc_sel.`2`[9], states[4].vc_sel.`2`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[4].vc_sel.`2`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8) node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10) node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9) node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_10 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, io.out_credit_available.`1`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_10 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, io.out_credit_available.`1`[7]) node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10) node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`2`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`2`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11) node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14) node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13) node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16) node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_1) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[8], states[4].vc_sel.`1`[8] connect salloc_arb.io.in[4].bits.vc_sel.`1`[9], states[4].vc_sel.`1`[9] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[8], states[4].vc_sel.`2`[8] connect salloc_arb.io.in[4].bits.vc_sel.`2`[9], states[4].vc_sel.`2`[9] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_115 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_116 = and(_T_115, input_buffer.io.deq[4].bits.tail) when _T_116 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_12 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[5].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[5].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12) node credit_available_lo_lo_13 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_hi_13 = cat(states[5].vc_sel.`1`[4], states[5].vc_sel.`1`[3]) node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, states[5].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[5].vc_sel.`1`[6], states[5].vc_sel.`1`[5]) node credit_available_hi_hi_hi_13 = cat(states[5].vc_sel.`1`[9], states[5].vc_sel.`1`[8]) node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, states[5].vc_sel.`1`[7]) node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13) node credit_available_lo_lo_14 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_hi_14 = cat(states[5].vc_sel.`2`[4], states[5].vc_sel.`2`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, states[5].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[5].vc_sel.`2`[6], states[5].vc_sel.`2`[5]) node credit_available_hi_hi_hi_14 = cat(states[5].vc_sel.`2`[9], states[5].vc_sel.`2`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, states[5].vc_sel.`2`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14) node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19) node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_16 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_16, io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_16 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_16, io.out_credit_available.`1`[7]) node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_17 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_17 = cat(credit_available_lo_hi_hi_17, io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_17 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_17 = cat(credit_available_hi_hi_hi_17, io.out_credit_available.`2`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17) node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23) node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22) node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25) node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_2) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[8], states[5].vc_sel.`1`[8] connect salloc_arb.io.in[5].bits.vc_sel.`1`[9], states[5].vc_sel.`1`[9] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[8], states[5].vc_sel.`2`[8] connect salloc_arb.io.in[5].bits.vc_sel.`2`[9], states[5].vc_sel.`2`[9] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_117 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_118 = and(_T_117, input_buffer.io.deq[5].bits.tail) when _T_118 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_18 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_hi_18 = cat(states[6].vc_sel.`0`[4], states[6].vc_sel.`0`[3]) node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_18, states[6].vc_sel.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[6].vc_sel.`0`[6], states[6].vc_sel.`0`[5]) node credit_available_hi_hi_hi_18 = cat(states[6].vc_sel.`0`[9], states[6].vc_sel.`0`[8]) node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_18, states[6].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18) node credit_available_lo_lo_19 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_hi_19 = cat(states[6].vc_sel.`1`[4], states[6].vc_sel.`1`[3]) node credit_available_lo_hi_19 = cat(credit_available_lo_hi_hi_19, states[6].vc_sel.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[6].vc_sel.`1`[6], states[6].vc_sel.`1`[5]) node credit_available_hi_hi_hi_19 = cat(states[6].vc_sel.`1`[9], states[6].vc_sel.`1`[8]) node credit_available_hi_hi_19 = cat(credit_available_hi_hi_hi_19, states[6].vc_sel.`1`[7]) node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19) node credit_available_lo_lo_20 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_hi_20 = cat(states[6].vc_sel.`2`[4], states[6].vc_sel.`2`[3]) node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_20, states[6].vc_sel.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[6].vc_sel.`2`[6], states[6].vc_sel.`2`[5]) node credit_available_hi_hi_hi_20 = cat(states[6].vc_sel.`2`[9], states[6].vc_sel.`2`[8]) node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_20, states[6].vc_sel.`2`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20) node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28) node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27) node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_21 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_21 = cat(credit_available_lo_hi_hi_21, io.out_credit_available.`0`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_21 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_21 = cat(credit_available_hi_hi_hi_21, io.out_credit_available.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21) node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_22 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_22, io.out_credit_available.`1`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_22 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_22, io.out_credit_available.`1`[7]) node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22) node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_23 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_23 = cat(credit_available_lo_hi_hi_23, io.out_credit_available.`2`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_23 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_23 = cat(credit_available_hi_hi_hi_23, io.out_credit_available.`2`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23) node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32) node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31) node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34) node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_3) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`0`[8], states[6].vc_sel.`0`[8] connect salloc_arb.io.in[6].bits.vc_sel.`0`[9], states[6].vc_sel.`0`[9] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[8], states[6].vc_sel.`1`[8] connect salloc_arb.io.in[6].bits.vc_sel.`1`[9], states[6].vc_sel.`1`[9] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[8], states[6].vc_sel.`2`[8] connect salloc_arb.io.in[6].bits.vc_sel.`2`[9], states[6].vc_sel.`2`[9] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_119 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_120 = and(_T_119, input_buffer.io.deq[6].bits.tail) when _T_120 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_24 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_hi_24 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3]) node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_24, states[7].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5]) node credit_available_hi_hi_hi_24 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8]) node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_24, states[7].vc_sel.`0`[7]) node credit_available_hi_32 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_36 = cat(credit_available_hi_32, credit_available_lo_24) node credit_available_lo_lo_25 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_hi_25 = cat(states[7].vc_sel.`1`[4], states[7].vc_sel.`1`[3]) node credit_available_lo_hi_25 = cat(credit_available_lo_hi_hi_25, states[7].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[7].vc_sel.`1`[6], states[7].vc_sel.`1`[5]) node credit_available_hi_hi_hi_25 = cat(states[7].vc_sel.`1`[9], states[7].vc_sel.`1`[8]) node credit_available_hi_hi_25 = cat(credit_available_hi_hi_hi_25, states[7].vc_sel.`1`[7]) node credit_available_hi_33 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_37 = cat(credit_available_hi_33, credit_available_lo_25) node credit_available_lo_lo_26 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_hi_26 = cat(states[7].vc_sel.`2`[4], states[7].vc_sel.`2`[3]) node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_26, states[7].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[7].vc_sel.`2`[6], states[7].vc_sel.`2`[5]) node credit_available_hi_hi_hi_26 = cat(states[7].vc_sel.`2`[9], states[7].vc_sel.`2`[8]) node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_26, states[7].vc_sel.`2`[7]) node credit_available_hi_34 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_38 = cat(credit_available_hi_34, credit_available_lo_26) node credit_available_hi_35 = cat(_credit_available_T_38, _credit_available_T_37) node _credit_available_T_39 = cat(credit_available_hi_35, _credit_available_T_36) node credit_available_lo_lo_27 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_27 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_27 = cat(credit_available_lo_hi_hi_27, io.out_credit_available.`0`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_27 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_27 = cat(credit_available_hi_hi_hi_27, io.out_credit_available.`0`[7]) node credit_available_hi_36 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_40 = cat(credit_available_hi_36, credit_available_lo_27) node credit_available_lo_lo_28 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_28 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_28, io.out_credit_available.`1`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_28 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_28, io.out_credit_available.`1`[7]) node credit_available_hi_37 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_41 = cat(credit_available_hi_37, credit_available_lo_28) node credit_available_lo_lo_29 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_29 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_29 = cat(credit_available_lo_hi_hi_29, io.out_credit_available.`2`[2]) node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_29 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_29 = cat(credit_available_hi_hi_hi_29, io.out_credit_available.`2`[7]) node credit_available_hi_38 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_42 = cat(credit_available_hi_38, credit_available_lo_29) node credit_available_hi_39 = cat(_credit_available_T_42, _credit_available_T_41) node _credit_available_T_43 = cat(credit_available_hi_39, _credit_available_T_40) node _credit_available_T_44 = and(_credit_available_T_39, _credit_available_T_43) node credit_available_4 = neq(_credit_available_T_44, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_4) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8] connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[8], states[7].vc_sel.`1`[8] connect salloc_arb.io.in[7].bits.vc_sel.`1`[9], states[7].vc_sel.`1`[9] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[8], states[7].vc_sel.`2`[8] connect salloc_arb.io.in[7].bits.vc_sel.`2`[9], states[7].vc_sel.`2`[9] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_121 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_122 = and(_T_121, input_buffer.io.deq[7].bits.tail) when _T_122 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node credit_available_lo_lo_30 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_30 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_30, states[8].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_30 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_30, states[8].vc_sel.`0`[7]) node credit_available_hi_40 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_45 = cat(credit_available_hi_40, credit_available_lo_30) node credit_available_lo_lo_31 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0]) node credit_available_lo_hi_hi_31 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3]) node credit_available_lo_hi_31 = cat(credit_available_lo_hi_hi_31, states[8].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5]) node credit_available_hi_hi_hi_31 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8]) node credit_available_hi_hi_31 = cat(credit_available_hi_hi_hi_31, states[8].vc_sel.`1`[7]) node credit_available_hi_41 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_46 = cat(credit_available_hi_41, credit_available_lo_31) node credit_available_lo_lo_32 = cat(states[8].vc_sel.`2`[1], states[8].vc_sel.`2`[0]) node credit_available_lo_hi_hi_32 = cat(states[8].vc_sel.`2`[4], states[8].vc_sel.`2`[3]) node credit_available_lo_hi_32 = cat(credit_available_lo_hi_hi_32, states[8].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[8].vc_sel.`2`[6], states[8].vc_sel.`2`[5]) node credit_available_hi_hi_hi_32 = cat(states[8].vc_sel.`2`[9], states[8].vc_sel.`2`[8]) node credit_available_hi_hi_32 = cat(credit_available_hi_hi_hi_32, states[8].vc_sel.`2`[7]) node credit_available_hi_42 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_47 = cat(credit_available_hi_42, credit_available_lo_32) node credit_available_hi_43 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_43, _credit_available_T_45) node credit_available_lo_lo_33 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_33 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_33 = cat(credit_available_lo_hi_hi_33, io.out_credit_available.`0`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_33 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_33 = cat(credit_available_hi_hi_hi_33, io.out_credit_available.`0`[7]) node credit_available_hi_44 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_49 = cat(credit_available_hi_44, credit_available_lo_33) node credit_available_lo_lo_34 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_34 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_34 = cat(credit_available_lo_hi_hi_34, io.out_credit_available.`1`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_34 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_34 = cat(credit_available_hi_hi_hi_34, io.out_credit_available.`1`[7]) node credit_available_hi_45 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_50 = cat(credit_available_hi_45, credit_available_lo_34) node credit_available_lo_lo_35 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_35 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_35 = cat(credit_available_lo_hi_hi_35, io.out_credit_available.`2`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_35 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_35 = cat(credit_available_hi_hi_hi_35, io.out_credit_available.`2`[7]) node credit_available_hi_46 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_51 = cat(credit_available_hi_46, credit_available_lo_35) node credit_available_hi_47 = cat(_credit_available_T_51, _credit_available_T_50) node _credit_available_T_52 = cat(credit_available_hi_47, _credit_available_T_49) node _credit_available_T_53 = and(_credit_available_T_48, _credit_available_T_52) node credit_available_5 = neq(_credit_available_T_53, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_5) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1] connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2] connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3] connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4] connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5] connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6] connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7] connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8] connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[1], states[8].vc_sel.`2`[1] connect salloc_arb.io.in[8].bits.vc_sel.`2`[2], states[8].vc_sel.`2`[2] connect salloc_arb.io.in[8].bits.vc_sel.`2`[3], states[8].vc_sel.`2`[3] connect salloc_arb.io.in[8].bits.vc_sel.`2`[4], states[8].vc_sel.`2`[4] connect salloc_arb.io.in[8].bits.vc_sel.`2`[5], states[8].vc_sel.`2`[5] connect salloc_arb.io.in[8].bits.vc_sel.`2`[6], states[8].vc_sel.`2`[6] connect salloc_arb.io.in[8].bits.vc_sel.`2`[7], states[8].vc_sel.`2`[7] connect salloc_arb.io.in[8].bits.vc_sel.`2`[8], states[8].vc_sel.`2`[8] connect salloc_arb.io.in[8].bits.vc_sel.`2`[9], states[8].vc_sel.`2`[9] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_123 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_124 = and(_T_123, input_buffer.io.deq[8].bits.tail) when _T_124 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_36 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_36 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_36 = cat(credit_available_lo_hi_hi_36, states[9].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_36 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_36 = cat(credit_available_hi_hi_hi_36, states[9].vc_sel.`0`[7]) node credit_available_hi_48 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_54 = cat(credit_available_hi_48, credit_available_lo_36) node credit_available_lo_lo_37 = cat(states[9].vc_sel.`1`[1], states[9].vc_sel.`1`[0]) node credit_available_lo_hi_hi_37 = cat(states[9].vc_sel.`1`[4], states[9].vc_sel.`1`[3]) node credit_available_lo_hi_37 = cat(credit_available_lo_hi_hi_37, states[9].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(states[9].vc_sel.`1`[6], states[9].vc_sel.`1`[5]) node credit_available_hi_hi_hi_37 = cat(states[9].vc_sel.`1`[9], states[9].vc_sel.`1`[8]) node credit_available_hi_hi_37 = cat(credit_available_hi_hi_hi_37, states[9].vc_sel.`1`[7]) node credit_available_hi_49 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_55 = cat(credit_available_hi_49, credit_available_lo_37) node credit_available_lo_lo_38 = cat(states[9].vc_sel.`2`[1], states[9].vc_sel.`2`[0]) node credit_available_lo_hi_hi_38 = cat(states[9].vc_sel.`2`[4], states[9].vc_sel.`2`[3]) node credit_available_lo_hi_38 = cat(credit_available_lo_hi_hi_38, states[9].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(states[9].vc_sel.`2`[6], states[9].vc_sel.`2`[5]) node credit_available_hi_hi_hi_38 = cat(states[9].vc_sel.`2`[9], states[9].vc_sel.`2`[8]) node credit_available_hi_hi_38 = cat(credit_available_hi_hi_hi_38, states[9].vc_sel.`2`[7]) node credit_available_hi_50 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_56 = cat(credit_available_hi_50, credit_available_lo_38) node credit_available_hi_51 = cat(_credit_available_T_56, _credit_available_T_55) node _credit_available_T_57 = cat(credit_available_hi_51, _credit_available_T_54) node credit_available_lo_lo_39 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_39 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_39 = cat(credit_available_lo_hi_hi_39, io.out_credit_available.`0`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_39 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_39 = cat(credit_available_hi_hi_hi_39, io.out_credit_available.`0`[7]) node credit_available_hi_52 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_58 = cat(credit_available_hi_52, credit_available_lo_39) node credit_available_lo_lo_40 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_40 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_40 = cat(credit_available_lo_hi_hi_40, io.out_credit_available.`1`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_40 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_40 = cat(credit_available_hi_hi_hi_40, io.out_credit_available.`1`[7]) node credit_available_hi_53 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_59 = cat(credit_available_hi_53, credit_available_lo_40) node credit_available_lo_lo_41 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_41 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_41 = cat(credit_available_lo_hi_hi_41, io.out_credit_available.`2`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_41 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_41 = cat(credit_available_hi_hi_hi_41, io.out_credit_available.`2`[7]) node credit_available_hi_54 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_60 = cat(credit_available_hi_54, credit_available_lo_41) node credit_available_hi_55 = cat(_credit_available_T_60, _credit_available_T_59) node _credit_available_T_61 = cat(credit_available_hi_55, _credit_available_T_58) node _credit_available_T_62 = and(_credit_available_T_57, _credit_available_T_61) node credit_available_6 = neq(_credit_available_T_62, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_6) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`1`[1], states[9].vc_sel.`1`[1] connect salloc_arb.io.in[9].bits.vc_sel.`1`[2], states[9].vc_sel.`1`[2] connect salloc_arb.io.in[9].bits.vc_sel.`1`[3], states[9].vc_sel.`1`[3] connect salloc_arb.io.in[9].bits.vc_sel.`1`[4], states[9].vc_sel.`1`[4] connect salloc_arb.io.in[9].bits.vc_sel.`1`[5], states[9].vc_sel.`1`[5] connect salloc_arb.io.in[9].bits.vc_sel.`1`[6], states[9].vc_sel.`1`[6] connect salloc_arb.io.in[9].bits.vc_sel.`1`[7], states[9].vc_sel.`1`[7] connect salloc_arb.io.in[9].bits.vc_sel.`1`[8], states[9].vc_sel.`1`[8] connect salloc_arb.io.in[9].bits.vc_sel.`1`[9], states[9].vc_sel.`1`[9] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[1], states[9].vc_sel.`2`[1] connect salloc_arb.io.in[9].bits.vc_sel.`2`[2], states[9].vc_sel.`2`[2] connect salloc_arb.io.in[9].bits.vc_sel.`2`[3], states[9].vc_sel.`2`[3] connect salloc_arb.io.in[9].bits.vc_sel.`2`[4], states[9].vc_sel.`2`[4] connect salloc_arb.io.in[9].bits.vc_sel.`2`[5], states[9].vc_sel.`2`[5] connect salloc_arb.io.in[9].bits.vc_sel.`2`[6], states[9].vc_sel.`2`[6] connect salloc_arb.io.in[9].bits.vc_sel.`2`[7], states[9].vc_sel.`2`[7] connect salloc_arb.io.in[9].bits.vc_sel.`2`[8], states[9].vc_sel.`2`[8] connect salloc_arb.io.in[9].bits.vc_sel.`2`[9], states[9].vc_sel.`2`[9] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_125 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_126 = and(_T_125, input_buffer.io.deq[9].bits.tail) when _T_126 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[10] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_237 connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13 node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_256 connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14 node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_275 connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15 node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_294 connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16 node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298) node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299) node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300) node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301) node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302) node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303) node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_313 connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17 node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315) node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316) node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317) node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318) node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319) node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320) node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321) node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_332 connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18 node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334) node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335) node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336) node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_351 connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19 node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358) node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359) node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360) node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_370 connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20 node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373) node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374) node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375) node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376) node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377) node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378) node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379) node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_389 connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_22 : UInt<1>[10] node _vc_sel_T_390 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_391 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_392 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_393 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_394 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_395 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_396 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_397 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_398 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_400 = or(_vc_sel_T_390, _vc_sel_T_391) node _vc_sel_T_401 = or(_vc_sel_T_400, _vc_sel_T_392) node _vc_sel_T_402 = or(_vc_sel_T_401, _vc_sel_T_393) node _vc_sel_T_403 = or(_vc_sel_T_402, _vc_sel_T_394) node _vc_sel_T_404 = or(_vc_sel_T_403, _vc_sel_T_395) node _vc_sel_T_405 = or(_vc_sel_T_404, _vc_sel_T_396) node _vc_sel_T_406 = or(_vc_sel_T_405, _vc_sel_T_397) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_398) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_399) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_408 connect _vc_sel_WIRE_22[0], _vc_sel_WIRE_23 node _vc_sel_T_409 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_410 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_411 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_412 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_413 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_419 = or(_vc_sel_T_409, _vc_sel_T_410) node _vc_sel_T_420 = or(_vc_sel_T_419, _vc_sel_T_411) node _vc_sel_T_421 = or(_vc_sel_T_420, _vc_sel_T_412) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_413) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_414) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_415) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_416) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_417) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_418) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_427 connect _vc_sel_WIRE_22[1], _vc_sel_WIRE_24 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_436 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_437 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_438 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_430) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_431) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_432) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_433) node _vc_sel_T_443 = or(_vc_sel_T_442, _vc_sel_T_434) node _vc_sel_T_444 = or(_vc_sel_T_443, _vc_sel_T_435) node _vc_sel_T_445 = or(_vc_sel_T_444, _vc_sel_T_436) node _vc_sel_T_446 = or(_vc_sel_T_445, _vc_sel_T_437) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_446 connect _vc_sel_WIRE_22[2], _vc_sel_WIRE_25 node _vc_sel_T_447 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_451 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_452 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_453 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_454 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_455 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_456 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_457 = or(_vc_sel_T_447, _vc_sel_T_448) node _vc_sel_T_458 = or(_vc_sel_T_457, _vc_sel_T_449) node _vc_sel_T_459 = or(_vc_sel_T_458, _vc_sel_T_450) node _vc_sel_T_460 = or(_vc_sel_T_459, _vc_sel_T_451) node _vc_sel_T_461 = or(_vc_sel_T_460, _vc_sel_T_452) node _vc_sel_T_462 = or(_vc_sel_T_461, _vc_sel_T_453) node _vc_sel_T_463 = or(_vc_sel_T_462, _vc_sel_T_454) node _vc_sel_T_464 = or(_vc_sel_T_463, _vc_sel_T_455) node _vc_sel_T_465 = or(_vc_sel_T_464, _vc_sel_T_456) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_465 connect _vc_sel_WIRE_22[3], _vc_sel_WIRE_26 node _vc_sel_T_466 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_467 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_468 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_469 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_470 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_471 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_472 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_473 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_476 = or(_vc_sel_T_466, _vc_sel_T_467) node _vc_sel_T_477 = or(_vc_sel_T_476, _vc_sel_T_468) node _vc_sel_T_478 = or(_vc_sel_T_477, _vc_sel_T_469) node _vc_sel_T_479 = or(_vc_sel_T_478, _vc_sel_T_470) node _vc_sel_T_480 = or(_vc_sel_T_479, _vc_sel_T_471) node _vc_sel_T_481 = or(_vc_sel_T_480, _vc_sel_T_472) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_473) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_474) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_475) wire _vc_sel_WIRE_27 : UInt<1> connect _vc_sel_WIRE_27, _vc_sel_T_484 connect _vc_sel_WIRE_22[4], _vc_sel_WIRE_27 node _vc_sel_T_485 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_486 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_487 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_488 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_495 = or(_vc_sel_T_485, _vc_sel_T_486) node _vc_sel_T_496 = or(_vc_sel_T_495, _vc_sel_T_487) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_488) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_489) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_490) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_491) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_492) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_493) node _vc_sel_T_503 = or(_vc_sel_T_502, _vc_sel_T_494) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_503 connect _vc_sel_WIRE_22[5], _vc_sel_WIRE_28 node _vc_sel_T_504 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_511 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_512 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_513 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_514 = or(_vc_sel_T_504, _vc_sel_T_505) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_506) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_507) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_508) node _vc_sel_T_518 = or(_vc_sel_T_517, _vc_sel_T_509) node _vc_sel_T_519 = or(_vc_sel_T_518, _vc_sel_T_510) node _vc_sel_T_520 = or(_vc_sel_T_519, _vc_sel_T_511) node _vc_sel_T_521 = or(_vc_sel_T_520, _vc_sel_T_512) node _vc_sel_T_522 = or(_vc_sel_T_521, _vc_sel_T_513) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_522 connect _vc_sel_WIRE_22[6], _vc_sel_WIRE_29 node _vc_sel_T_523 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_526 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_527 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_528 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_529 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_530 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_531 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_532 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_533 = or(_vc_sel_T_523, _vc_sel_T_524) node _vc_sel_T_534 = or(_vc_sel_T_533, _vc_sel_T_525) node _vc_sel_T_535 = or(_vc_sel_T_534, _vc_sel_T_526) node _vc_sel_T_536 = or(_vc_sel_T_535, _vc_sel_T_527) node _vc_sel_T_537 = or(_vc_sel_T_536, _vc_sel_T_528) node _vc_sel_T_538 = or(_vc_sel_T_537, _vc_sel_T_529) node _vc_sel_T_539 = or(_vc_sel_T_538, _vc_sel_T_530) node _vc_sel_T_540 = or(_vc_sel_T_539, _vc_sel_T_531) node _vc_sel_T_541 = or(_vc_sel_T_540, _vc_sel_T_532) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_541 connect _vc_sel_WIRE_22[7], _vc_sel_WIRE_30 node _vc_sel_T_542 = mux(_vc_sel_T, states[0].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_543 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_544 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_545 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_546 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_547 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_548 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_552 = or(_vc_sel_T_542, _vc_sel_T_543) node _vc_sel_T_553 = or(_vc_sel_T_552, _vc_sel_T_544) node _vc_sel_T_554 = or(_vc_sel_T_553, _vc_sel_T_545) node _vc_sel_T_555 = or(_vc_sel_T_554, _vc_sel_T_546) node _vc_sel_T_556 = or(_vc_sel_T_555, _vc_sel_T_547) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_548) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_549) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_550) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_551) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_560 connect _vc_sel_WIRE_22[8], _vc_sel_WIRE_31 node _vc_sel_T_561 = mux(_vc_sel_T, states[0].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_562 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_563 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_561, _vc_sel_T_562) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_563) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_564) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_565) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_566) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_567) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_568) node _vc_sel_T_578 = or(_vc_sel_T_577, _vc_sel_T_569) node _vc_sel_T_579 = or(_vc_sel_T_578, _vc_sel_T_570) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_579 connect _vc_sel_WIRE_22[9], _vc_sel_WIRE_32 connect vc_sel.`2`, _vc_sel_WIRE_22 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4]) node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8]) node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9]) node _channel_oh_T_16 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[2]) node _channel_oh_T_18 = or(_channel_oh_T_17, vc_sel.`2`[3]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`2`[4]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`2`[5]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`2`[6]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`2`[7]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`2`[8]) node channel_oh_2 = or(_channel_oh_T_23, vc_sel.`2`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2]) node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5]) node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8]) node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7]) node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8) node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0) node _virt_channel_T_12 = orr(virt_channel_hi_5) node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5) node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4) node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0) node _virt_channel_T_14 = orr(virt_channel_hi_6) node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2) node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19) node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_lo_hi_2 = cat(virt_channel_lo_hi_hi_2, vc_sel.`2`[2]) node virt_channel_lo_8 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[6], vc_sel.`2`[5]) node virt_channel_hi_hi_hi_2 = cat(vc_sel.`2`[9], vc_sel.`2`[8]) node virt_channel_hi_hi_2 = cat(virt_channel_hi_hi_hi_2, vc_sel.`2`[7]) node virt_channel_hi_8 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_22 = cat(virt_channel_hi_8, virt_channel_lo_8) node virt_channel_hi_9 = bits(_virt_channel_T_22, 9, 8) node virt_channel_lo_9 = bits(_virt_channel_T_22, 7, 0) node _virt_channel_T_23 = orr(virt_channel_hi_9) node _virt_channel_T_24 = or(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = cat(_virt_channel_T_23, _virt_channel_T_31) node _virt_channel_T_33 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_2, _virt_channel_T_32, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_33, _virt_channel_T_34) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_35) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_37 node _T_127 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_127 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`0`[8] invalidate states[0].vc_sel.`0`[9] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`1`[8] invalidate states[0].vc_sel.`1`[9] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`2`[8] invalidate states[0].vc_sel.`2`[9] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`0`[5] invalidate states[1].vc_sel.`0`[6] invalidate states[1].vc_sel.`0`[7] invalidate states[1].vc_sel.`0`[8] invalidate states[1].vc_sel.`0`[9] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].vc_sel.`1`[5] invalidate states[1].vc_sel.`1`[6] invalidate states[1].vc_sel.`1`[7] invalidate states[1].vc_sel.`1`[8] invalidate states[1].vc_sel.`1`[9] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`2`[3] invalidate states[1].vc_sel.`2`[4] invalidate states[1].vc_sel.`2`[5] invalidate states[1].vc_sel.`2`[6] invalidate states[1].vc_sel.`2`[7] invalidate states[1].vc_sel.`2`[8] invalidate states[1].vc_sel.`2`[9] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`0`[5] invalidate states[2].vc_sel.`0`[6] invalidate states[2].vc_sel.`0`[7] invalidate states[2].vc_sel.`0`[8] invalidate states[2].vc_sel.`0`[9] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].vc_sel.`1`[5] invalidate states[2].vc_sel.`1`[6] invalidate states[2].vc_sel.`1`[7] invalidate states[2].vc_sel.`1`[8] invalidate states[2].vc_sel.`1`[9] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`2`[3] invalidate states[2].vc_sel.`2`[4] invalidate states[2].vc_sel.`2`[5] invalidate states[2].vc_sel.`2`[6] invalidate states[2].vc_sel.`2`[7] invalidate states[2].vc_sel.`2`[8] invalidate states[2].vc_sel.`2`[9] invalidate states[2].g connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[2], UInt<1>(0h0) connect states[3].vc_sel.`0`[3], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[6], UInt<1>(0h0) connect states[3].vc_sel.`0`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[8], UInt<1>(0h0) connect states[3].vc_sel.`0`[9], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[8], UInt<1>(0h0) connect states[3].vc_sel.`1`[9], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[8], UInt<1>(0h0) connect states[3].vc_sel.`2`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[4], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[6], UInt<1>(0h0) connect states[4].vc_sel.`0`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[8], UInt<1>(0h0) connect states[4].vc_sel.`0`[9], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[8], UInt<1>(0h0) connect states[4].vc_sel.`1`[9], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[8], UInt<1>(0h0) connect states[4].vc_sel.`2`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) connect states[5].vc_sel.`0`[4], UInt<1>(0h0) connect states[5].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[6], UInt<1>(0h0) connect states[5].vc_sel.`0`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[8], UInt<1>(0h0) connect states[5].vc_sel.`0`[9], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`1`[5], UInt<1>(0h0) connect states[5].vc_sel.`1`[6], UInt<1>(0h0) connect states[5].vc_sel.`1`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[8], UInt<1>(0h0) connect states[5].vc_sel.`1`[9], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`2`[8], UInt<1>(0h0) connect states[5].vc_sel.`2`[9], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`0`[1], UInt<1>(0h0) connect states[6].vc_sel.`0`[2], UInt<1>(0h0) connect states[6].vc_sel.`0`[3], UInt<1>(0h0) connect states[6].vc_sel.`0`[4], UInt<1>(0h0) connect states[6].vc_sel.`0`[5], UInt<1>(0h0) connect states[6].vc_sel.`0`[6], UInt<1>(0h0) connect states[6].vc_sel.`0`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[8], UInt<1>(0h0) connect states[6].vc_sel.`0`[9], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`1`[5], UInt<1>(0h0) connect states[6].vc_sel.`1`[6], UInt<1>(0h0) connect states[6].vc_sel.`1`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[8], UInt<1>(0h0) connect states[6].vc_sel.`1`[9], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`2`[8], UInt<1>(0h0) connect states[6].vc_sel.`2`[9], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`0`[1], UInt<1>(0h0) connect states[7].vc_sel.`0`[2], UInt<1>(0h0) connect states[7].vc_sel.`0`[3], UInt<1>(0h0) connect states[7].vc_sel.`0`[4], UInt<1>(0h0) connect states[7].vc_sel.`0`[5], UInt<1>(0h0) connect states[7].vc_sel.`0`[6], UInt<1>(0h0) connect states[7].vc_sel.`0`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[8], UInt<1>(0h0) connect states[7].vc_sel.`0`[9], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`1`[5], UInt<1>(0h0) connect states[7].vc_sel.`1`[6], UInt<1>(0h0) connect states[7].vc_sel.`1`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[8], UInt<1>(0h0) connect states[7].vc_sel.`1`[9], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[8], UInt<1>(0h0) connect states[7].vc_sel.`2`[9], UInt<1>(0h0) connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`0`[8], UInt<1>(0h0) connect states[8].vc_sel.`0`[9], UInt<1>(0h0) connect states[8].vc_sel.`1`[0], UInt<1>(0h0) connect states[8].vc_sel.`1`[1], UInt<1>(0h0) connect states[8].vc_sel.`1`[2], UInt<1>(0h0) connect states[8].vc_sel.`1`[3], UInt<1>(0h0) connect states[8].vc_sel.`1`[4], UInt<1>(0h0) connect states[8].vc_sel.`1`[5], UInt<1>(0h0) connect states[8].vc_sel.`1`[6], UInt<1>(0h0) connect states[8].vc_sel.`1`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[8], UInt<1>(0h0) connect states[8].vc_sel.`1`[9], UInt<1>(0h0) connect states[8].vc_sel.`2`[0], UInt<1>(0h0) connect states[8].vc_sel.`2`[1], UInt<1>(0h0) connect states[8].vc_sel.`2`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`0`[2], UInt<1>(0h0) connect states[9].vc_sel.`0`[3], UInt<1>(0h0) connect states[9].vc_sel.`0`[4], UInt<1>(0h0) connect states[9].vc_sel.`0`[5], UInt<1>(0h0) connect states[9].vc_sel.`0`[6], UInt<1>(0h0) connect states[9].vc_sel.`0`[7], UInt<1>(0h0) connect states[9].vc_sel.`0`[8], UInt<1>(0h0) connect states[9].vc_sel.`0`[9], UInt<1>(0h0) connect states[9].vc_sel.`1`[0], UInt<1>(0h0) connect states[9].vc_sel.`1`[1], UInt<1>(0h0) connect states[9].vc_sel.`1`[2], UInt<1>(0h0) connect states[9].vc_sel.`1`[3], UInt<1>(0h0) connect states[9].vc_sel.`1`[4], UInt<1>(0h0) connect states[9].vc_sel.`1`[5], UInt<1>(0h0) connect states[9].vc_sel.`1`[6], UInt<1>(0h0) connect states[9].vc_sel.`1`[7], UInt<1>(0h0) connect states[9].vc_sel.`1`[8], UInt<1>(0h0) connect states[9].vc_sel.`1`[9], UInt<1>(0h0) connect states[9].vc_sel.`2`[0], UInt<1>(0h0) connect states[9].vc_sel.`2`[1], UInt<1>(0h0) node _T_128 = asUInt(reset) when _T_128 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)	module InputUnit_134( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_8, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_8; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, 3'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] \| vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7 \| vcalloc_vals_8 \| vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_24 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_228 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_229 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_24( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_228 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_229 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_12 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}} node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31) node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23) node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0) node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0) node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1) node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2) node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3) node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4) node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5) node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6) node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7) node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8) node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9) node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10) node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11) node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12) node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13) node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14) node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15) node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16) node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17) node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18) node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19) node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20) node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21) node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22) node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23) node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24) node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25) node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26) node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27) node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28) node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29) node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30) node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31) node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32) node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33) node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34) node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35) node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36) node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37) node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38) node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39) node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40) node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41) node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42) node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43) node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist) node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn) node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2) node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3) node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn) node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T) connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1 node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn) connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T) connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1 node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T) node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn) node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2) connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3 node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6) node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T) node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2) node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3) node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0) node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5) node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0) node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7) node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31) node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23) node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0) node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0) node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1) node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2) node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3) node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4) node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5) node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6) node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7) node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8) node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9) node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10) node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11) node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12) node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13) node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14) node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15) node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16) node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17) node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18) node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19) node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20) node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21) node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22) node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23) node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24) node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25) node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26) node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27) node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28) node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29) node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30) node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31) node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32) node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33) node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34) node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35) node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36) node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37) node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38) node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39) node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40) node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41) node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42) node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43) node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist) node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn) node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2) node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3) node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn) node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T) connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1 node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn) connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T) connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1 node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T) node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn) node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2) connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3 node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6) node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T) node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2) node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3) node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0) node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5) node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0) node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7) node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31) node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23) node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0) node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0) node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1) node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2) node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3) node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4) node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5) node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6) node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7) node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8) node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9) node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10) node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11) node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12) node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13) node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14) node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15) node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16) node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17) node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18) node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19) node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20) node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21) node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22) node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23) node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24) node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25) node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26) node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27) node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28) node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29) node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30) node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31) node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32) node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33) node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34) node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35) node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36) node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37) node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38) node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39) node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40) node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41) node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42) node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43) node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist) node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn) node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2) node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3) node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn) node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7) node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T) connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1 node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn) connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T) connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1 node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T) node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn) node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2) connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3 node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6) node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T) node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2) node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3) node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0) node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5) node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0) node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7) inst io_out_d_m1_resizer of RecFNToRecFN_216 connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_m2_resizer of RecFNToRecFN_217 connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_muladder of MulAddRecFN_e8_s24_76 connect io_out_d_muladder.io.op, UInt<1>(0h0) connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out connect io_out_d_muladder.io.c, io_out_d_self_rec wire io_out_d_out : { bits : UInt<32>} node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23) node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6) node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7) node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T) connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1 node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1) connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2 connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32) connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp) connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T) node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0) node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2) connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3 node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0) node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T) node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1) node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1) node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist) node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0) node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0) node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81)) node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1) node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2) node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf) node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5) node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0) node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T) node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1) node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut) node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut) connect io_out_d_out.bits, _io_out_d_out_bits_T connect io.out_d, io_out_d_out	module MacUnit_12( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [31:0] io_in_a_bits, // @[PE.scala:16:14] input [31:0] io_in_b_bits, // @[PE.scala:16:14] input [31:0] io_in_c_bits, // @[PE.scala:16:14] output [31:0] io_out_d_bits // @[PE.scala:16:14] ); wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7] wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7] wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23] wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7] wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] \| _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] \| _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] \| _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7] wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN \| io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 \| _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] RecFNToRecFN_216 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_217 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_76 io_out_d_muladder ( // @[Arithmetic.scala:376:30] .io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_muladder_io_out) ); // @[Arithmetic.scala:376:30] assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module BoomDuplicatedDataArray : input clock : Clock input reset : Reset output io : { flip read : { valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>}}[1], flip write : { valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[8][1], s1_nacks : UInt<1>[1]} node waddr = shr(io.write.bits.addr, 4) node raddr = shr(io.read[0].bits.addr, 4) smem array_0_0 : UInt<64>[2] [256] node _T = bits(io.write.bits.way_en, 0, 0) node _T_1 = and(_T, io.write.valid) when _T_1 : node _data_T = bits(io.write.bits.data, 63, 0) node _data_T_1 = bits(io.write.bits.data, 127, 64) wire data : UInt<64>[2] connect data[0], _data_T connect data[1], _data_T_1 node _T_2 = bits(io.write.bits.wmask, 0, 0) node _T_3 = bits(io.write.bits.wmask, 1, 1) write mport MPORT = array_0_0[waddr], clock when _T_2 : connect MPORT[0], data[0] when _T_3 : connect MPORT[1], data[1] wire _io_resp_0_0_WIRE : UInt<8> invalidate _io_resp_0_0_WIRE when io.read[0].valid : connect _io_resp_0_0_WIRE, raddr read mport io_resp_0_0_MPORT = array_0_0[_io_resp_0_0_WIRE], clock node _io_resp_0_0_T = cat(io_resp_0_0_MPORT[1], io_resp_0_0_MPORT[0]) reg io_resp_0_0_REG : UInt, clock connect io_resp_0_0_REG, _io_resp_0_0_T connect io.resp[0][0], io_resp_0_0_REG smem array_1_0 : UInt<64>[2] [256] node _T_4 = bits(io.write.bits.way_en, 1, 1) node _T_5 = and(_T_4, io.write.valid) when _T_5 : node _data_T_2 = bits(io.write.bits.data, 63, 0) node _data_T_3 = bits(io.write.bits.data, 127, 64) wire data_1 : UInt<64>[2] connect data_1[0], _data_T_2 connect data_1[1], _data_T_3 node _T_6 = bits(io.write.bits.wmask, 0, 0) node _T_7 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_1 = array_1_0[waddr], clock when _T_6 : connect MPORT_1[0], data_1[0] when _T_7 : connect MPORT_1[1], data_1[1] wire _io_resp_0_1_WIRE : UInt<8> invalidate _io_resp_0_1_WIRE when io.read[0].valid : connect _io_resp_0_1_WIRE, raddr read mport io_resp_0_1_MPORT = array_1_0[_io_resp_0_1_WIRE], clock node _io_resp_0_1_T = cat(io_resp_0_1_MPORT[1], io_resp_0_1_MPORT[0]) reg io_resp_0_1_REG : UInt, clock connect io_resp_0_1_REG, _io_resp_0_1_T connect io.resp[0][1], io_resp_0_1_REG smem array_2_0 : UInt<64>[2] [256] node _T_8 = bits(io.write.bits.way_en, 2, 2) node _T_9 = and(_T_8, io.write.valid) when _T_9 : node _data_T_4 = bits(io.write.bits.data, 63, 0) node _data_T_5 = bits(io.write.bits.data, 127, 64) wire data_2 : UInt<64>[2] connect data_2[0], _data_T_4 connect data_2[1], _data_T_5 node _T_10 = bits(io.write.bits.wmask, 0, 0) node _T_11 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_2 = array_2_0[waddr], clock when _T_10 : connect MPORT_2[0], data_2[0] when _T_11 : connect MPORT_2[1], data_2[1] wire _io_resp_0_2_WIRE : UInt<8> invalidate _io_resp_0_2_WIRE when io.read[0].valid : connect _io_resp_0_2_WIRE, raddr read mport io_resp_0_2_MPORT = array_2_0[_io_resp_0_2_WIRE], clock node _io_resp_0_2_T = cat(io_resp_0_2_MPORT[1], io_resp_0_2_MPORT[0]) reg io_resp_0_2_REG : UInt, clock connect io_resp_0_2_REG, _io_resp_0_2_T connect io.resp[0][2], io_resp_0_2_REG smem array_3_0 : UInt<64>[2] [256] node _T_12 = bits(io.write.bits.way_en, 3, 3) node _T_13 = and(_T_12, io.write.valid) when _T_13 : node _data_T_6 = bits(io.write.bits.data, 63, 0) node _data_T_7 = bits(io.write.bits.data, 127, 64) wire data_3 : UInt<64>[2] connect data_3[0], _data_T_6 connect data_3[1], _data_T_7 node _T_14 = bits(io.write.bits.wmask, 0, 0) node _T_15 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_3 = array_3_0[waddr], clock when _T_14 : connect MPORT_3[0], data_3[0] when _T_15 : connect MPORT_3[1], data_3[1] wire _io_resp_0_3_WIRE : UInt<8> invalidate _io_resp_0_3_WIRE when io.read[0].valid : connect _io_resp_0_3_WIRE, raddr read mport io_resp_0_3_MPORT = array_3_0[_io_resp_0_3_WIRE], clock node _io_resp_0_3_T = cat(io_resp_0_3_MPORT[1], io_resp_0_3_MPORT[0]) reg io_resp_0_3_REG : UInt, clock connect io_resp_0_3_REG, _io_resp_0_3_T connect io.resp[0][3], io_resp_0_3_REG smem array_4_0 : UInt<64>[2] [256] node _T_16 = bits(io.write.bits.way_en, 4, 4) node _T_17 = and(_T_16, io.write.valid) when _T_17 : node _data_T_8 = bits(io.write.bits.data, 63, 0) node _data_T_9 = bits(io.write.bits.data, 127, 64) wire data_4 : UInt<64>[2] connect data_4[0], _data_T_8 connect data_4[1], _data_T_9 node _T_18 = bits(io.write.bits.wmask, 0, 0) node _T_19 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_4 = array_4_0[waddr], clock when _T_18 : connect MPORT_4[0], data_4[0] when _T_19 : connect MPORT_4[1], data_4[1] wire _io_resp_0_4_WIRE : UInt<8> invalidate _io_resp_0_4_WIRE when io.read[0].valid : connect _io_resp_0_4_WIRE, raddr read mport io_resp_0_4_MPORT = array_4_0[_io_resp_0_4_WIRE], clock node _io_resp_0_4_T = cat(io_resp_0_4_MPORT[1], io_resp_0_4_MPORT[0]) reg io_resp_0_4_REG : UInt, clock connect io_resp_0_4_REG, _io_resp_0_4_T connect io.resp[0][4], io_resp_0_4_REG smem array_5_0 : UInt<64>[2] [256] node _T_20 = bits(io.write.bits.way_en, 5, 5) node _T_21 = and(_T_20, io.write.valid) when _T_21 : node _data_T_10 = bits(io.write.bits.data, 63, 0) node _data_T_11 = bits(io.write.bits.data, 127, 64) wire data_5 : UInt<64>[2] connect data_5[0], _data_T_10 connect data_5[1], _data_T_11 node _T_22 = bits(io.write.bits.wmask, 0, 0) node _T_23 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_5 = array_5_0[waddr], clock when _T_22 : connect MPORT_5[0], data_5[0] when _T_23 : connect MPORT_5[1], data_5[1] wire _io_resp_0_5_WIRE : UInt<8> invalidate _io_resp_0_5_WIRE when io.read[0].valid : connect _io_resp_0_5_WIRE, raddr read mport io_resp_0_5_MPORT = array_5_0[_io_resp_0_5_WIRE], clock node _io_resp_0_5_T = cat(io_resp_0_5_MPORT[1], io_resp_0_5_MPORT[0]) reg io_resp_0_5_REG : UInt, clock connect io_resp_0_5_REG, _io_resp_0_5_T connect io.resp[0][5], io_resp_0_5_REG smem array_6_0 : UInt<64>[2] [256] node _T_24 = bits(io.write.bits.way_en, 6, 6) node _T_25 = and(_T_24, io.write.valid) when _T_25 : node _data_T_12 = bits(io.write.bits.data, 63, 0) node _data_T_13 = bits(io.write.bits.data, 127, 64) wire data_6 : UInt<64>[2] connect data_6[0], _data_T_12 connect data_6[1], _data_T_13 node _T_26 = bits(io.write.bits.wmask, 0, 0) node _T_27 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_6 = array_6_0[waddr], clock when _T_26 : connect MPORT_6[0], data_6[0] when _T_27 : connect MPORT_6[1], data_6[1] wire _io_resp_0_6_WIRE : UInt<8> invalidate _io_resp_0_6_WIRE when io.read[0].valid : connect _io_resp_0_6_WIRE, raddr read mport io_resp_0_6_MPORT = array_6_0[_io_resp_0_6_WIRE], clock node _io_resp_0_6_T = cat(io_resp_0_6_MPORT[1], io_resp_0_6_MPORT[0]) reg io_resp_0_6_REG : UInt, clock connect io_resp_0_6_REG, _io_resp_0_6_T connect io.resp[0][6], io_resp_0_6_REG smem array_7_0 : UInt<64>[2] [256] node _T_28 = bits(io.write.bits.way_en, 7, 7) node _T_29 = and(_T_28, io.write.valid) when _T_29 : node _data_T_14 = bits(io.write.bits.data, 63, 0) node _data_T_15 = bits(io.write.bits.data, 127, 64) wire data_7 : UInt<64>[2] connect data_7[0], _data_T_14 connect data_7[1], _data_T_15 node _T_30 = bits(io.write.bits.wmask, 0, 0) node _T_31 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_7 = array_7_0[waddr], clock when _T_30 : connect MPORT_7[0], data_7[0] when _T_31 : connect MPORT_7[1], data_7[1] wire _io_resp_0_7_WIRE : UInt<8> invalidate _io_resp_0_7_WIRE when io.read[0].valid : connect _io_resp_0_7_WIRE, raddr read mport io_resp_0_7_MPORT = array_7_0[_io_resp_0_7_WIRE], clock node _io_resp_0_7_T = cat(io_resp_0_7_MPORT[1], io_resp_0_7_MPORT[0]) reg io_resp_0_7_REG : UInt, clock connect io_resp_0_7_REG, _io_resp_0_7_T connect io.resp[0][7], io_resp_0_7_REG connect io.s1_nacks[0], UInt<1>(0h0)	module BoomDuplicatedDataArray( // @[dcache.scala:281:7] input clock, // @[dcache.scala:281:7] input reset, // @[dcache.scala:281:7] input io_read_0_valid, // @[dcache.scala:270:14] input [7:0] io_read_0_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_read_0_bits_addr, // @[dcache.scala:270:14] input io_write_valid, // @[dcache.scala:270:14] input [7:0] io_write_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_write_bits_addr, // @[dcache.scala:270:14] input [1:0] io_write_bits_wmask, // @[dcache.scala:270:14] input [127:0] io_write_bits_data, // @[dcache.scala:270:14] output [127:0] io_resp_0_0, // @[dcache.scala:270:14] output [127:0] io_resp_0_1, // @[dcache.scala:270:14] output [127:0] io_resp_0_2, // @[dcache.scala:270:14] output [127:0] io_resp_0_3, // @[dcache.scala:270:14] output [127:0] io_resp_0_4, // @[dcache.scala:270:14] output [127:0] io_resp_0_5, // @[dcache.scala:270:14] output [127:0] io_resp_0_6, // @[dcache.scala:270:14] output [127:0] io_resp_0_7 // @[dcache.scala:270:14] ); wire io_read_0_valid_0 = io_read_0_valid; // @[dcache.scala:281:7] wire [7:0] io_read_0_bits_way_en_0 = io_read_0_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_read_0_bits_addr_0 = io_read_0_bits_addr; // @[dcache.scala:281:7] wire io_write_valid_0 = io_write_valid; // @[dcache.scala:281:7] wire [7:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_write_bits_addr_0 = io_write_bits_addr; // @[dcache.scala:281:7] wire [1:0] io_write_bits_wmask_0 = io_write_bits_wmask; // @[dcache.scala:281:7] wire [127:0] io_write_bits_data_0 = io_write_bits_data; // @[dcache.scala:281:7] wire io_s1_nacks_0 = 1'h0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_0_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_1_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_2_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_3_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_4_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_5_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_6_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_7_0; // @[dcache.scala:281:7] wire [7:0] waddr = io_write_bits_addr_0[11:4]; // @[dcache.scala:281:7, :284:34] wire [7:0] raddr = io_read_0_bits_addr_0[11:4]; // @[dcache.scala:281:7, :287:38] wire [7:0] _io_resp_0_0_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_1_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_2_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_3_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_4_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_5_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_6_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_7_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [63:0] data_0; // @[dcache.scala:296:27] wire [63:0] data_1; // @[dcache.scala:296:27] wire [63:0] _data_T = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_2 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_4 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_6 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_8 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_10 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_12 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_14 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] assign data_0 = _data_T; // @[dcache.scala:296:{27,75}] wire [63:0] _data_T_1 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_3 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_5 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_7 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_9 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_11 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_13 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_15 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] assign data_1 = _data_T_1; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_0_REG; // @[dcache.scala:302:33] assign io_resp_0_0_0 = io_resp_0_0_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_1_0; // @[dcache.scala:296:27] wire [63:0] data_1_1; // @[dcache.scala:296:27] assign data_1_0 = _data_T_2; // @[dcache.scala:296:{27,75}] assign data_1_1 = _data_T_3; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_1_REG; // @[dcache.scala:302:33] assign io_resp_0_1_0 = io_resp_0_1_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_2_0; // @[dcache.scala:296:27] wire [63:0] data_2_1; // @[dcache.scala:296:27] assign data_2_0 = _data_T_4; // @[dcache.scala:296:{27,75}] assign data_2_1 = _data_T_5; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_2_REG; // @[dcache.scala:302:33] assign io_resp_0_2_0 = io_resp_0_2_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_3_0; // @[dcache.scala:296:27] wire [63:0] data_3_1; // @[dcache.scala:296:27] assign data_3_0 = _data_T_6; // @[dcache.scala:296:{27,75}] assign data_3_1 = _data_T_7; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_3_REG; // @[dcache.scala:302:33] assign io_resp_0_3_0 = io_resp_0_3_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_4_0; // @[dcache.scala:296:27] wire [63:0] data_4_1; // @[dcache.scala:296:27] assign data_4_0 = _data_T_8; // @[dcache.scala:296:{27,75}] assign data_4_1 = _data_T_9; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_4_REG; // @[dcache.scala:302:33] assign io_resp_0_4_0 = io_resp_0_4_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_5_0; // @[dcache.scala:296:27] wire [63:0] data_5_1; // @[dcache.scala:296:27] assign data_5_0 = _data_T_10; // @[dcache.scala:296:{27,75}] assign data_5_1 = _data_T_11; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_5_REG; // @[dcache.scala:302:33] assign io_resp_0_5_0 = io_resp_0_5_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_6_0; // @[dcache.scala:296:27] wire [63:0] data_6_1; // @[dcache.scala:296:27] assign data_6_0 = _data_T_12; // @[dcache.scala:296:{27,75}] assign data_6_1 = _data_T_13; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_6_REG; // @[dcache.scala:302:33] assign io_resp_0_6_0 = io_resp_0_6_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_7_0; // @[dcache.scala:296:27] wire [63:0] data_7_1; // @[dcache.scala:296:27] assign data_7_0 = _data_T_14; // @[dcache.scala:296:{27,75}] assign data_7_1 = _data_T_15; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_7_REG; // @[dcache.scala:302:33] assign io_resp_0_7_0 = io_resp_0_7_REG; // @[dcache.scala:281:7, :302:33] wire [127:0] _io_resp_0_0_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_1_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_2_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_3_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_4_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_5_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_6_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_7_T; // @[dcache.scala:302:70] always @(posedge clock) begin // @[dcache.scala:281:7] io_resp_0_0_REG <= _io_resp_0_0_T; // @[dcache.scala:302:{33,70}] io_resp_0_1_REG <= _io_resp_0_1_T; // @[dcache.scala:302:{33,70}] io_resp_0_2_REG <= _io_resp_0_2_T; // @[dcache.scala:302:{33,70}] io_resp_0_3_REG <= _io_resp_0_3_T; // @[dcache.scala:302:{33,70}] io_resp_0_4_REG <= _io_resp_0_4_T; // @[dcache.scala:302:{33,70}] io_resp_0_5_REG <= _io_resp_0_5_T; // @[dcache.scala:302:{33,70}] io_resp_0_6_REG <= _io_resp_0_6_T; // @[dcache.scala:302:{33,70}] io_resp_0_7_REG <= _io_resp_0_7_T; // @[dcache.scala:302:{33,70}] always @(posedge) array_0_0 array_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_0_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_0_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[0] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_1, data_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_1_0 array_1_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_1_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_1_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[1] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_1_1, data_1_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_2_0 array_2_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_2_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_2_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[2] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_2_1, data_2_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_3_0 array_3_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_3_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_3_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[3] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_3_1, data_3_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_4_0 array_4_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_4_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_4_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[4] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_4_1, data_4_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_5_0 array_5_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_5_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_5_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[5] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_5_1, data_5_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_6_0 array_6_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_6_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_6_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[6] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_6_1, data_6_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_7_0 array_7_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_7_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_7_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[7] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_7_1, data_7_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0_0 = io_resp_0_0_0; // @[dcache.scala:281:7] assign io_resp_0_1 = io_resp_0_1_0; // @[dcache.scala:281:7] assign io_resp_0_2 = io_resp_0_2_0; // @[dcache.scala:281:7] assign io_resp_0_3 = io_resp_0_3_0; // @[dcache.scala:281:7] assign io_resp_0_4 = io_resp_0_4_0; // @[dcache.scala:281:7] assign io_resp_0_5 = io_resp_0_5_0; // @[dcache.scala:281:7] assign io_resp_0_6 = io_resp_0_6_0; // @[dcache.scala:281:7] assign io_resp_0_7 = io_resp_0_7_0; // @[dcache.scala:281:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_76 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_77 = and(_T_75, _T_76) node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_79 = and(_T_77, _T_78) node _T_80 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_81 = and(_T_79, _T_80) node _T_82 = or(_T_53, _T_60) node _T_83 = or(_T_82, _T_67) node _T_84 = or(_T_83, _T_74) node _T_85 = or(_T_84, _T_81) node _T_86 = or(_T_46, _T_85) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_86, UInt<1>(0h1), "") : assert_3	module NoCMonitor_44( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module MemReader : input clock : Clock input reset : Reset output io : { flip addr : UInt<21>, flip size : UInt<2>, flip signed : UInt<1>, data : UInt<32>, mem_addr : UInt<19>, flip mem_data : UInt<8>[4]} node s_offset = bits(io.addr, 1, 0) node _io_mem_addr_T = bits(io.addr, 20, 2) connect io.mem_addr, _io_mem_addr_T node shiftedVec_lo = cat(io.mem_data[2], io.mem_data[3]) node shiftedVec_hi = cat(io.mem_data[0], io.mem_data[1]) node _shiftedVec_T = cat(shiftedVec_hi, shiftedVec_lo) node _shiftedVec_T_1 = shl(s_offset, 3) node _shiftedVec_T_2 = dshr(_shiftedVec_T, _shiftedVec_T_1) node _shiftedVec_T_3 = bits(_shiftedVec_T_2, 31, 0) node _shiftedVec_T_4 = bits(_shiftedVec_T_3, 0, 0) node _shiftedVec_T_5 = bits(_shiftedVec_T_3, 1, 1) node _shiftedVec_T_6 = bits(_shiftedVec_T_3, 2, 2) node _shiftedVec_T_7 = bits(_shiftedVec_T_3, 3, 3) node _shiftedVec_T_8 = bits(_shiftedVec_T_3, 4, 4) node _shiftedVec_T_9 = bits(_shiftedVec_T_3, 5, 5) node _shiftedVec_T_10 = bits(_shiftedVec_T_3, 6, 6) node _shiftedVec_T_11 = bits(_shiftedVec_T_3, 7, 7) node _shiftedVec_T_12 = bits(_shiftedVec_T_3, 8, 8) node _shiftedVec_T_13 = bits(_shiftedVec_T_3, 9, 9) node _shiftedVec_T_14 = bits(_shiftedVec_T_3, 10, 10) node _shiftedVec_T_15 = bits(_shiftedVec_T_3, 11, 11) node _shiftedVec_T_16 = bits(_shiftedVec_T_3, 12, 12) node _shiftedVec_T_17 = bits(_shiftedVec_T_3, 13, 13) node _shiftedVec_T_18 = bits(_shiftedVec_T_3, 14, 14) node _shiftedVec_T_19 = bits(_shiftedVec_T_3, 15, 15) node _shiftedVec_T_20 = bits(_shiftedVec_T_3, 16, 16) node _shiftedVec_T_21 = bits(_shiftedVec_T_3, 17, 17) node _shiftedVec_T_22 = bits(_shiftedVec_T_3, 18, 18) node _shiftedVec_T_23 = bits(_shiftedVec_T_3, 19, 19) node _shiftedVec_T_24 = bits(_shiftedVec_T_3, 20, 20) node _shiftedVec_T_25 = bits(_shiftedVec_T_3, 21, 21) node _shiftedVec_T_26 = bits(_shiftedVec_T_3, 22, 22) node _shiftedVec_T_27 = bits(_shiftedVec_T_3, 23, 23) node _shiftedVec_T_28 = bits(_shiftedVec_T_3, 24, 24) node _shiftedVec_T_29 = bits(_shiftedVec_T_3, 25, 25) node _shiftedVec_T_30 = bits(_shiftedVec_T_3, 26, 26) node _shiftedVec_T_31 = bits(_shiftedVec_T_3, 27, 27) node _shiftedVec_T_32 = bits(_shiftedVec_T_3, 28, 28) node _shiftedVec_T_33 = bits(_shiftedVec_T_3, 29, 29) node _shiftedVec_T_34 = bits(_shiftedVec_T_3, 30, 30) node _shiftedVec_T_35 = bits(_shiftedVec_T_3, 31, 31) node shiftedVec_lo_lo = cat(_shiftedVec_T_29, _shiftedVec_T_28) node shiftedVec_lo_hi = cat(_shiftedVec_T_31, _shiftedVec_T_30) node shiftedVec_lo_1 = cat(shiftedVec_lo_hi, shiftedVec_lo_lo) node shiftedVec_hi_lo = cat(_shiftedVec_T_33, _shiftedVec_T_32) node shiftedVec_hi_hi = cat(_shiftedVec_T_35, _shiftedVec_T_34) node shiftedVec_hi_1 = cat(shiftedVec_hi_hi, shiftedVec_hi_lo) node _shiftedVec_T_36 = cat(shiftedVec_hi_1, shiftedVec_lo_1) node shiftedVec_lo_lo_1 = cat(_shiftedVec_T_21, _shiftedVec_T_20) node shiftedVec_lo_hi_1 = cat(_shiftedVec_T_23, _shiftedVec_T_22) node shiftedVec_lo_2 = cat(shiftedVec_lo_hi_1, shiftedVec_lo_lo_1) node shiftedVec_hi_lo_1 = cat(_shiftedVec_T_25, _shiftedVec_T_24) node shiftedVec_hi_hi_1 = cat(_shiftedVec_T_27, _shiftedVec_T_26) node shiftedVec_hi_2 = cat(shiftedVec_hi_hi_1, shiftedVec_hi_lo_1) node _shiftedVec_T_37 = cat(shiftedVec_hi_2, shiftedVec_lo_2) node shiftedVec_lo_lo_2 = cat(_shiftedVec_T_13, _shiftedVec_T_12) node shiftedVec_lo_hi_2 = cat(_shiftedVec_T_15, _shiftedVec_T_14) node shiftedVec_lo_3 = cat(shiftedVec_lo_hi_2, shiftedVec_lo_lo_2) node shiftedVec_hi_lo_2 = cat(_shiftedVec_T_17, _shiftedVec_T_16) node shiftedVec_hi_hi_2 = cat(_shiftedVec_T_19, _shiftedVec_T_18) node shiftedVec_hi_3 = cat(shiftedVec_hi_hi_2, shiftedVec_hi_lo_2) node _shiftedVec_T_38 = cat(shiftedVec_hi_3, shiftedVec_lo_3) node shiftedVec_lo_lo_3 = cat(_shiftedVec_T_5, _shiftedVec_T_4) node shiftedVec_lo_hi_3 = cat(_shiftedVec_T_7, _shiftedVec_T_6) node shiftedVec_lo_4 = cat(shiftedVec_lo_hi_3, shiftedVec_lo_lo_3) node shiftedVec_hi_lo_3 = cat(_shiftedVec_T_9, _shiftedVec_T_8) node shiftedVec_hi_hi_3 = cat(_shiftedVec_T_11, _shiftedVec_T_10) node shiftedVec_hi_4 = cat(shiftedVec_hi_hi_3, shiftedVec_hi_lo_3) node _shiftedVec_T_39 = cat(shiftedVec_hi_4, shiftedVec_lo_4) wire shiftedVec : UInt<8>[4] connect shiftedVec[0], _shiftedVec_T_36 connect shiftedVec[1], _shiftedVec_T_37 connect shiftedVec[2], _shiftedVec_T_38 connect shiftedVec[3], _shiftedVec_T_39 node _bytes_T = eq(UInt<1>(0h0), io.size) node _bytes_T_1 = mux(_bytes_T, UInt<1>(0h0), UInt<2>(0h3)) node _bytes_T_2 = eq(UInt<1>(0h1), io.size) node _bytes_T_3 = mux(_bytes_T_2, UInt<1>(0h1), _bytes_T_1) node _bytes_T_4 = eq(UInt<2>(0h2), io.size) node bytes = mux(_bytes_T_4, UInt<2>(0h3), _bytes_T_3) node _sign_T = sub(UInt<2>(0h3), bytes) node _sign_T_1 = tail(_sign_T, 1) node sign = bits(shiftedVec[_sign_T_1], 7, 7) node _masks_mask_T = dshl(UInt<8>(0h1f), bytes) node masks_mask = bits(_masks_mask_T, 7, 4) node _masks_maskWithOffset_T = dshl(masks_mask, UInt<1>(0h0)) node masks_maskWithOffset = bits(_masks_maskWithOffset_T, 3, 0) node masks_3 = bits(masks_maskWithOffset, 0, 0) node masks_2 = bits(masks_maskWithOffset, 1, 1) node masks_1 = bits(masks_maskWithOffset, 2, 2) node masks_0 = bits(masks_maskWithOffset, 3, 3) node _maskedVec_T = and(sign, io.signed) node _maskedVec_T_1 = mux(masks_0, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_2 = not(_maskedVec_T_1) node _maskedVec_T_3 = or(shiftedVec[0], _maskedVec_T_2) node _maskedVec_T_4 = mux(masks_0, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_5 = and(shiftedVec[0], _maskedVec_T_4) node maskedVec_0 = mux(_maskedVec_T, _maskedVec_T_3, _maskedVec_T_5) node _maskedVec_T_6 = and(sign, io.signed) node _maskedVec_T_7 = mux(masks_1, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_8 = not(_maskedVec_T_7) node _maskedVec_T_9 = or(shiftedVec[1], _maskedVec_T_8) node _maskedVec_T_10 = mux(masks_1, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_11 = and(shiftedVec[1], _maskedVec_T_10) node maskedVec_1 = mux(_maskedVec_T_6, _maskedVec_T_9, _maskedVec_T_11) node _maskedVec_T_12 = and(sign, io.signed) node _maskedVec_T_13 = mux(masks_2, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_14 = not(_maskedVec_T_13) node _maskedVec_T_15 = or(shiftedVec[2], _maskedVec_T_14) node _maskedVec_T_16 = mux(masks_2, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_17 = and(shiftedVec[2], _maskedVec_T_16) node maskedVec_2 = mux(_maskedVec_T_12, _maskedVec_T_15, _maskedVec_T_17) node _maskedVec_T_18 = and(sign, io.signed) node _maskedVec_T_19 = mux(masks_3, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_20 = not(_maskedVec_T_19) node _maskedVec_T_21 = or(shiftedVec[3], _maskedVec_T_20) node _maskedVec_T_22 = mux(masks_3, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_23 = and(shiftedVec[3], _maskedVec_T_22) node maskedVec_3 = mux(_maskedVec_T_18, _maskedVec_T_21, _maskedVec_T_23) node io_data_lo = cat(maskedVec_2, maskedVec_3) node io_data_hi = cat(maskedVec_0, maskedVec_1) node _io_data_T = cat(io_data_hi, io_data_lo) connect io.data, _io_data_T	module MemReader( // @[memory.scala:89:13] input clock, // @[memory.scala:89:13] input reset, // @[memory.scala:89:13] input [20:0] io_addr, // @[memory.scala:90:21] input [1:0] io_size, // @[memory.scala:90:21] input io_signed, // @[memory.scala:90:21] output [31:0] io_data, // @[memory.scala:90:21] output [18:0] io_mem_addr, // @[memory.scala:90:21] input [7:0] io_mem_data_0, // @[memory.scala:90:21] input [7:0] io_mem_data_1, // @[memory.scala:90:21] input [7:0] io_mem_data_2, // @[memory.scala:90:21] input [7:0] io_mem_data_3 // @[memory.scala:90:21] ); wire [20:0] io_addr_0 = io_addr; // @[memory.scala:89:13] wire [1:0] io_size_0 = io_size; // @[memory.scala:89:13] wire io_signed_0 = io_signed; // @[memory.scala:89:13] wire [7:0] io_mem_data_0_0 = io_mem_data_0; // @[memory.scala:89:13] wire [7:0] io_mem_data_1_0 = io_mem_data_1; // @[memory.scala:89:13] wire [7:0] io_mem_data_2_0 = io_mem_data_2; // @[memory.scala:89:13] wire [7:0] io_mem_data_3_0 = io_mem_data_3; // @[memory.scala:89:13] wire [31:0] _io_data_T; // @[memory.scala:117:24] wire [18:0] _io_mem_addr_T; // @[memory.scala:105:32] wire [31:0] io_data_0; // @[memory.scala:89:13] wire [18:0] io_mem_addr_0; // @[memory.scala:89:13] wire [1:0] s_offset = io_addr_0[1:0]; // @[memory.scala:89:13, :100:46] assign _io_mem_addr_T = io_addr_0[20:2]; // @[memory.scala:89:13, :105:32] assign io_mem_addr_0 = _io_mem_addr_T; // @[memory.scala:89:13, :105:32] wire [15:0] shiftedVec_lo = {io_mem_data_2_0, io_mem_data_3_0}; // @[memory.scala:89:13, :107:40] wire [15:0] shiftedVec_hi = {io_mem_data_0_0, io_mem_data_1_0}; // @[memory.scala:89:13, :107:40] wire [31:0] _shiftedVec_T = {shiftedVec_hi, shiftedVec_lo}; // @[memory.scala:107:40] wire [4:0] _shiftedVec_T_1 = {s_offset, 3'h0}; // @[memory.scala:100:46, :107:63] wire [31:0] _shiftedVec_T_2 = _shiftedVec_T >> _shiftedVec_T_1; // @[memory.scala:107:{40,50,63}] wire [31:0] _shiftedVec_T_3 = _shiftedVec_T_2; // @[memory.scala:84:54, :107:50] wire _shiftedVec_T_4 = _shiftedVec_T_3[0]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_5 = _shiftedVec_T_3[1]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_6 = _shiftedVec_T_3[2]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_7 = _shiftedVec_T_3[3]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_8 = _shiftedVec_T_3[4]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_9 = _shiftedVec_T_3[5]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_10 = _shiftedVec_T_3[6]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_11 = _shiftedVec_T_3[7]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_12 = _shiftedVec_T_3[8]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_13 = _shiftedVec_T_3[9]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_14 = _shiftedVec_T_3[10]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_15 = _shiftedVec_T_3[11]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_16 = _shiftedVec_T_3[12]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_17 = _shiftedVec_T_3[13]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_18 = _shiftedVec_T_3[14]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_19 = _shiftedVec_T_3[15]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_20 = _shiftedVec_T_3[16]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_21 = _shiftedVec_T_3[17]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_22 = _shiftedVec_T_3[18]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_23 = _shiftedVec_T_3[19]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_24 = _shiftedVec_T_3[20]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_25 = _shiftedVec_T_3[21]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_26 = _shiftedVec_T_3[22]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_27 = _shiftedVec_T_3[23]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_28 = _shiftedVec_T_3[24]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_29 = _shiftedVec_T_3[25]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_30 = _shiftedVec_T_3[26]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_31 = _shiftedVec_T_3[27]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_32 = _shiftedVec_T_3[28]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_33 = _shiftedVec_T_3[29]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_34 = _shiftedVec_T_3[30]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_35 = _shiftedVec_T_3[31]; // @[memory.scala:84:{54,62}] wire [1:0] shiftedVec_lo_lo = {_shiftedVec_T_29, _shiftedVec_T_28}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi = {_shiftedVec_T_31, _shiftedVec_T_30}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_1 = {shiftedVec_lo_hi, shiftedVec_lo_lo}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo = {_shiftedVec_T_33, _shiftedVec_T_32}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi = {_shiftedVec_T_35, _shiftedVec_T_34}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_1 = {shiftedVec_hi_hi, shiftedVec_hi_lo}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_36 = {shiftedVec_hi_1, shiftedVec_lo_1}; // @[memory.scala:84:106] wire [7:0] shiftedVec_0 = _shiftedVec_T_36; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_1 = {_shiftedVec_T_21, _shiftedVec_T_20}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_1 = {_shiftedVec_T_23, _shiftedVec_T_22}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_2 = {shiftedVec_lo_hi_1, shiftedVec_lo_lo_1}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_1 = {_shiftedVec_T_25, _shiftedVec_T_24}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_1 = {_shiftedVec_T_27, _shiftedVec_T_26}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_2 = {shiftedVec_hi_hi_1, shiftedVec_hi_lo_1}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_37 = {shiftedVec_hi_2, shiftedVec_lo_2}; // @[memory.scala:84:106] wire [7:0] shiftedVec_1 = _shiftedVec_T_37; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_2 = {_shiftedVec_T_13, _shiftedVec_T_12}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_2 = {_shiftedVec_T_15, _shiftedVec_T_14}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_3 = {shiftedVec_lo_hi_2, shiftedVec_lo_lo_2}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_2 = {_shiftedVec_T_17, _shiftedVec_T_16}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_2 = {_shiftedVec_T_19, _shiftedVec_T_18}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_3 = {shiftedVec_hi_hi_2, shiftedVec_hi_lo_2}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_38 = {shiftedVec_hi_3, shiftedVec_lo_3}; // @[memory.scala:84:106] wire [7:0] shiftedVec_2 = _shiftedVec_T_38; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_3 = {_shiftedVec_T_5, _shiftedVec_T_4}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_3 = {_shiftedVec_T_7, _shiftedVec_T_6}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_4 = {shiftedVec_lo_hi_3, shiftedVec_lo_lo_3}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_3 = {_shiftedVec_T_9, _shiftedVec_T_8}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_3 = {_shiftedVec_T_11, _shiftedVec_T_10}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_4 = {shiftedVec_hi_hi_3, shiftedVec_hi_lo_3}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_39 = {shiftedVec_hi_4, shiftedVec_lo_4}; // @[memory.scala:84:106] wire [7:0] shiftedVec_3 = _shiftedVec_T_39; // @[memory.scala:84:{47,106}] wire _bytes_T = io_size_0 == 2'h0; // @[memory.scala:76:62, :89:13] wire [1:0] _bytes_T_1 = _bytes_T ? 2'h0 : 2'h3; // @[memory.scala:76:62] wire _bytes_T_2 = io_size_0 == 2'h1; // @[memory.scala:76:62, :89:13] wire [1:0] _bytes_T_3 = _bytes_T_2 ? 2'h1 : _bytes_T_1; // @[memory.scala:76:62] wire _bytes_T_4 = io_size_0 == 2'h2; // @[memory.scala:76:62, :89:13] wire [1:0] bytes = _bytes_T_4 ? 2'h3 : _bytes_T_3; // @[memory.scala:76:62] wire [2:0] _sign_T = 3'h3 - {1'h0, bytes}; // @[memory.scala:76:62, :111:36] wire [1:0] _sign_T_1 = _sign_T[1:0]; // @[memory.scala:111:36] wire [3:0][7:0] _GEN = {{shiftedVec_3}, {shiftedVec_2}, {shiftedVec_1}, {shiftedVec_0}}; // @[memory.scala:84:47, :111:50] wire sign = _GEN[_sign_T_1][7]; // @[memory.scala:111:{36,50}] wire [10:0] _masks_mask_T = 11'h1F << bytes; // @[memory.scala:76:62, :79:38] wire [3:0] masks_mask = _masks_mask_T[7:4]; // @[memory.scala:79:{38,53}] wire [4:0] _masks_maskWithOffset_T = {1'h0, masks_mask}; // @[memory.scala:76:62, :79:53, :80:34] wire [3:0] masks_maskWithOffset = _masks_maskWithOffset_T[3:0]; // @[memory.scala:80:{34,55}] wire masks_3 = masks_maskWithOffset[0]; // @[memory.scala:80:55, :81:22] wire masks_2 = masks_maskWithOffset[1]; // @[memory.scala:80:55, :81:22] wire masks_1 = masks_maskWithOffset[2]; // @[memory.scala:80:55, :81:22] wire masks_0 = masks_maskWithOffset[3]; // @[memory.scala:80:55, :81:22] wire _GEN_0 = sign & io_signed_0; // @[memory.scala:89:13, :111:50, :114:22] wire _maskedVec_T; // @[memory.scala:114:22] assign _maskedVec_T = _GEN_0; // @[memory.scala:114:22] wire _maskedVec_T_6; // @[memory.scala:114:22] assign _maskedVec_T_6 = _GEN_0; // @[memory.scala:114:22] wire _maskedVec_T_12; // @[memory.scala:114:22] assign _maskedVec_T_12 = _GEN_0; // @[memory.scala:114:22] wire _maskedVec_T_18; // @[memory.scala:114:22] assign _maskedVec_T_18 = _GEN_0; // @[memory.scala:114:22] wire [7:0] _GEN_1 = {8{masks_0}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_1; // @[memory.scala:114:47] assign _maskedVec_T_1 = _GEN_1; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_4; // @[memory.scala:114:69] assign _maskedVec_T_4 = _GEN_1; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_2 = ~_maskedVec_T_1; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_3 = shiftedVec_0 \| _maskedVec_T_2; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_5 = shiftedVec_0 & _maskedVec_T_4; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_0 = _maskedVec_T ? _maskedVec_T_3 : _maskedVec_T_5; // @[memory.scala:114:{16,22,40,63}] wire [7:0] _GEN_2 = {8{masks_1}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_7; // @[memory.scala:114:47] assign _maskedVec_T_7 = _GEN_2; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_10; // @[memory.scala:114:69] assign _maskedVec_T_10 = _GEN_2; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_8 = ~_maskedVec_T_7; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_9 = shiftedVec_1 \| _maskedVec_T_8; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_11 = shiftedVec_1 & _maskedVec_T_10; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_1 = _maskedVec_T_6 ? _maskedVec_T_9 : _maskedVec_T_11; // @[memory.scala:114:{16,22,40,63}] wire [7:0] _GEN_3 = {8{masks_2}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_13; // @[memory.scala:114:47] assign _maskedVec_T_13 = _GEN_3; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_16; // @[memory.scala:114:69] assign _maskedVec_T_16 = _GEN_3; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_14 = ~_maskedVec_T_13; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_15 = shiftedVec_2 \| _maskedVec_T_14; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_17 = shiftedVec_2 & _maskedVec_T_16; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_2 = _maskedVec_T_12 ? _maskedVec_T_15 : _maskedVec_T_17; // @[memory.scala:114:{16,22,40,63}] wire [7:0] _GEN_4 = {8{masks_3}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_19; // @[memory.scala:114:47] assign _maskedVec_T_19 = _GEN_4; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_22; // @[memory.scala:114:69] assign _maskedVec_T_22 = _GEN_4; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_20 = ~_maskedVec_T_19; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_21 = shiftedVec_3 \| _maskedVec_T_20; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_23 = shiftedVec_3 & _maskedVec_T_22; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_3 = _maskedVec_T_18 ? _maskedVec_T_21 : _maskedVec_T_23; // @[memory.scala:114:{16,22,40,63}] wire [15:0] io_data_lo = {maskedVec_2, maskedVec_3}; // @[memory.scala:114:16, :117:24] wire [15:0] io_data_hi = {maskedVec_0, maskedVec_1}; // @[memory.scala:114:16, :117:24] assign _io_data_T = {io_data_hi, io_data_lo}; // @[memory.scala:117:24] assign io_data_0 = _io_data_T; // @[memory.scala:89:13, :117:24] assign io_data = io_data_0; // @[memory.scala:89:13] assign io_mem_addr = io_mem_addr_0; // @[memory.scala:89:13] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_188 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_188( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_36 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_327 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_36( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_327 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_51 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync	module IntSyncSyncCrossingSink_n1x1_51( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_31 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_85 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_11 of InputUnit_85 connect input_unit_0_from_11.clock, clock connect input_unit_0_from_11.reset, reset inst ingress_unit_1_from_12 of IngressUnit_48 connect ingress_unit_1_from_12.clock, clock connect ingress_unit_1_from_12.reset, reset inst output_unit_0_to_14 of OutputUnit_85 connect output_unit_0_to_14.clock, clock connect output_unit_0_to_14.reset, reset inst egress_unit_1_to_12 of EgressUnit_40 connect egress_unit_1_to_12.clock, clock connect egress_unit_1_to_12.reset, reset inst switch of Switch_31 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_31 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_31 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_31 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_3 connect input_unit_0_from_11.io.in, destNodesIn connect ingress_unit_1_from_12.io.in, ingressNodesIn.flit connect output_unit_0_to_14.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_14.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_14.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_12.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_12.io.out.valid connect egress_unit_1_to_12.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_11.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_12.io.router_req connect input_unit_0_from_11.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_12.io.router_resp, route_computer.io.resp.`1` connect vc_allocator.io.req.`0`, input_unit_0_from_11.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_12.io.vcalloc_req connect input_unit_0_from_11.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_12.io.vcalloc_resp, vc_allocator.io.resp.`1` connect output_unit_0_to_14.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_12.io.allocs, vc_allocator.io.out_allocs.`1` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_14.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_14.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_14.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_14.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_14.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_14.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_14.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_14.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_14.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_14.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_14.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_14.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_12.io.channel_status[0].occupied connect input_unit_0_from_11.io.out_credit_available.`0`[0], output_unit_0_to_14.io.credit_available[0] connect input_unit_0_from_11.io.out_credit_available.`0`[1], output_unit_0_to_14.io.credit_available[1] connect input_unit_0_from_11.io.out_credit_available.`1`[0], egress_unit_1_to_12.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[0], output_unit_0_to_14.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[1], output_unit_0_to_14.io.credit_available[1] connect ingress_unit_1_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_12.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_11.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_12.io.salloc_req[0] connect output_unit_0_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_14.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_14.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect egress_unit_1_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_11.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_12.io.out[0] connect output_unit_0_to_14.io.in, switch.io.out.`0` connect egress_unit_1_to_12.io.in, switch.io.out.`1` connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0] connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0] connect input_unit_0_from_11.io.block, UInt<1>(0h0) connect ingress_unit_1_from_12.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_11.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_12.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_11.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_12.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_57 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 11 15 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i12 15 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d 15 e12 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20	module Router_31( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_12_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_12_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_12_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_14_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_14_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_11_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_11_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_11_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_12_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module LCG_4 : input clock : Clock input reset : Reset output io : { out : UInt<5>, flip inc : UInt<1>} inst outs_lcg of LCG16_5 connect outs_lcg.clock, clock connect outs_lcg.reset, reset connect outs_lcg.io.inc, io.inc connect io.out, outs_lcg.io.out	module LCG_4( // @[LCG.scala:30:7] input clock, // @[LCG.scala:30:7] input reset, // @[LCG.scala:30:7] output [4:0] io_out // @[LCG.scala:31:14] ); wire [15:0] _outs_lcg_io_out; // @[LCG.scala:43:21] wire io_inc = 1'h1; // @[LCG.scala:30:7, :31:14, :43:21] wire [4:0] io_out_0; // @[LCG.scala:30:7] assign io_out_0 = _outs_lcg_io_out[4:0]; // @[LCG.scala:30:7, :38:10, :43:21] LCG16_5 outs_lcg ( // @[LCG.scala:43:21] .clock (clock), .reset (reset), .io_out (_outs_lcg_io_out) ); // @[LCG.scala:43:21] assign io_out = io_out_0; // @[LCG.scala:30:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_3 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e11_s53_3( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DatPath : input clock : Clock input reset : Reset output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip imem : { flip req : { valid : UInt<1>, bits : { pc : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<32>, inst : UInt<32>}}, debug : { if_pc : UInt<32>, if_inst : UInt<32>}, imiss : UInt<1>, flip exe_kill : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ctl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}, dat : { br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, inst_misaligned : UInt<1>, data_misaligned : UInt<1>, wb_hazard_stall : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt} invalidate io.hartid invalidate io.interrupt.meip invalidate io.interrupt.msip invalidate io.interrupt.mtip invalidate io.interrupt.debug invalidate io.dat.csr_interrupt invalidate io.dat.csr_eret invalidate io.dat.wb_hazard_stall invalidate io.dat.data_misaligned invalidate io.dat.inst_misaligned invalidate io.dat.br_ltu invalidate io.dat.br_lt invalidate io.dat.br_eq invalidate io.ctl.exception_cause invalidate io.ctl.exception invalidate io.ctl.dmem_typ invalidate io.ctl.dmem_fcn invalidate io.ctl.dmem_val invalidate io.ctl.csr_cmd invalidate io.ctl.bypassable invalidate io.ctl.rf_wen invalidate io.ctl.wb_sel invalidate io.ctl.alu_fun invalidate io.ctl.op2_sel invalidate io.ctl.op1_sel invalidate io.ctl.brjmp_sel invalidate io.ctl.pc_sel invalidate io.ctl.exe_kill invalidate io.dmem.resp.bits.data invalidate io.dmem.resp.valid invalidate io.dmem.req.bits.typ invalidate io.dmem.req.bits.fcn invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.addr invalidate io.dmem.req.valid invalidate io.dmem.req.ready invalidate io.imem.exe_kill invalidate io.imem.imiss invalidate io.imem.debug.if_inst invalidate io.imem.debug.if_pc invalidate io.imem.resp.bits.inst invalidate io.imem.resp.bits.pc invalidate io.imem.resp.valid invalidate io.imem.resp.ready invalidate io.imem.req.bits.pc invalidate io.imem.req.valid invalidate io.ddpath.resetpc invalidate io.ddpath.rdata invalidate io.ddpath.validreq invalidate io.ddpath.wdata invalidate io.ddpath.addr wire tval_data_ma : UInt<32> wire tval_inst_ma : UInt<32> regreset wb_reg_inst : UInt<32>, clock, reset, UInt<32>(0h4033) regreset wb_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg wb_reg_ctrl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}, clock reg wb_reg_pc : UInt<32>, clock reg wb_reg_alu : UInt<32>, clock reg wb_reg_csr_addr : UInt<12>, clock reg wb_reg_wbaddr : UInt<5>, clock reg wb_reg_target_pc : UInt<32>, clock regreset wb_reg_mem : UInt<1>, clock, reset, UInt<1>(0h0) wire wb_hazard_stall : UInt<1> wire wb_dmiss_stall : UInt<1> wire exe_brjmp_target : UInt<32> wire exe_jump_reg_target : UInt<32> wire exception_target : UInt<32> node _io_imem_resp_ready_T = eq(wb_hazard_stall, UInt<1>(0h0)) node _io_imem_resp_ready_T_1 = eq(wb_dmiss_stall, UInt<1>(0h0)) node _io_imem_resp_ready_T_2 = and(_io_imem_resp_ready_T, _io_imem_resp_ready_T_1) connect io.imem.resp.ready, _io_imem_resp_ready_T_2 node _take_pc_T = eq(io.ctl.pc_sel, UInt<3>(0h4)) node _take_pc_T_1 = eq(io.ctl.pc_sel, UInt<3>(0h3)) node _take_pc_T_2 = mux(_take_pc_T_1, exe_jump_reg_target, exe_brjmp_target) node take_pc = mux(_take_pc_T, exception_target, _take_pc_T_2) node _io_dat_inst_misaligned_T = bits(exe_brjmp_target, 1, 0) node _io_dat_inst_misaligned_T_1 = orr(_io_dat_inst_misaligned_T) node _io_dat_inst_misaligned_T_2 = eq(io.ctl.pc_sel, UInt<3>(0h1)) node _io_dat_inst_misaligned_T_3 = eq(io.ctl.pc_sel, UInt<3>(0h2)) node _io_dat_inst_misaligned_T_4 = or(_io_dat_inst_misaligned_T_2, _io_dat_inst_misaligned_T_3) node _io_dat_inst_misaligned_T_5 = and(_io_dat_inst_misaligned_T_1, _io_dat_inst_misaligned_T_4) node _io_dat_inst_misaligned_T_6 = bits(exe_jump_reg_target, 1, 0) node _io_dat_inst_misaligned_T_7 = orr(_io_dat_inst_misaligned_T_6) node _io_dat_inst_misaligned_T_8 = eq(io.ctl.pc_sel, UInt<3>(0h3)) node _io_dat_inst_misaligned_T_9 = and(_io_dat_inst_misaligned_T_7, _io_dat_inst_misaligned_T_8) node _io_dat_inst_misaligned_T_10 = or(_io_dat_inst_misaligned_T_5, _io_dat_inst_misaligned_T_9) node _io_dat_inst_misaligned_T_11 = and(_io_dat_inst_misaligned_T_10, io.imem.resp.valid) connect io.dat.inst_misaligned, _io_dat_inst_misaligned_T_11 node _exe_target_pc_T = eq(io.ctl.pc_sel, UInt<3>(0h3)) node exe_target_pc = mux(_exe_target_pc_T, exe_jump_reg_target, exe_brjmp_target) connect io.imem.req.bits.pc, take_pc node exe_rs1_addr = bits(io.imem.resp.bits.inst, 19, 15) node exe_rs2_addr = bits(io.imem.resp.bits.inst, 24, 20) node exe_wbaddr = bits(io.imem.resp.bits.inst, 11, 7) wire wb_wbdata : UInt<32> connect io.dat.wb_hazard_stall, wb_hazard_stall node _wb_hazard_stall_T = eq(wb_reg_wbaddr, exe_rs1_addr) node _wb_hazard_stall_T_1 = neq(exe_rs1_addr, UInt<1>(0h0)) node _wb_hazard_stall_T_2 = and(_wb_hazard_stall_T, _wb_hazard_stall_T_1) node _wb_hazard_stall_T_3 = and(_wb_hazard_stall_T_2, wb_reg_ctrl.rf_wen) node _wb_hazard_stall_T_4 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0)) node _wb_hazard_stall_T_5 = and(_wb_hazard_stall_T_3, _wb_hazard_stall_T_4) node _wb_hazard_stall_T_6 = eq(wb_reg_wbaddr, exe_rs2_addr) node _wb_hazard_stall_T_7 = neq(exe_rs2_addr, UInt<1>(0h0)) node _wb_hazard_stall_T_8 = and(_wb_hazard_stall_T_6, _wb_hazard_stall_T_7) node _wb_hazard_stall_T_9 = and(_wb_hazard_stall_T_8, wb_reg_ctrl.rf_wen) node _wb_hazard_stall_T_10 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0)) node _wb_hazard_stall_T_11 = and(_wb_hazard_stall_T_9, _wb_hazard_stall_T_10) node _wb_hazard_stall_T_12 = or(_wb_hazard_stall_T_5, _wb_hazard_stall_T_11) connect wb_hazard_stall, _wb_hazard_stall_T_12 cmem regfile : UInt<32> [32] infer mport io_ddpath_rdata_MPORT = regfile[io.ddpath.addr], clock connect io.ddpath.rdata, io_ddpath_rdata_MPORT when io.ddpath.validreq : infer mport MPORT = regfile[io.ddpath.addr], clock connect MPORT, io.ddpath.wdata node _T = neq(wb_reg_wbaddr, UInt<1>(0h0)) node _T_1 = and(wb_reg_ctrl.rf_wen, _T) node _T_2 = eq(wb_dmiss_stall, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(io.ctl.exception, UInt<1>(0h0)) node _T_5 = and(_T_3, _T_4) when _T_5 : infer mport MPORT_1 = regfile[wb_reg_wbaddr], clock connect MPORT_1, wb_wbdata node _rf_rs1_data_T = neq(exe_rs1_addr, UInt<1>(0h0)) infer mport rf_rs1_data_MPORT = regfile[exe_rs1_addr], clock node rf_rs1_data = mux(_rf_rs1_data_T, rf_rs1_data_MPORT, UInt<32>(0h0)) node _rf_rs2_data_T = neq(exe_rs2_addr, UInt<1>(0h0)) infer mport rf_rs2_data_MPORT = regfile[exe_rs2_addr], clock node rf_rs2_data = mux(_rf_rs2_data_T, rf_rs2_data_MPORT, UInt<32>(0h0)) node imm_i = bits(io.imem.resp.bits.inst, 31, 20) node _imm_s_T = bits(io.imem.resp.bits.inst, 31, 25) node _imm_s_T_1 = bits(io.imem.resp.bits.inst, 11, 7) node imm_s = cat(_imm_s_T, _imm_s_T_1) node _imm_b_T = bits(io.imem.resp.bits.inst, 31, 31) node _imm_b_T_1 = bits(io.imem.resp.bits.inst, 7, 7) node _imm_b_T_2 = bits(io.imem.resp.bits.inst, 30, 25) node _imm_b_T_3 = bits(io.imem.resp.bits.inst, 11, 8) node imm_b_lo = cat(_imm_b_T_2, _imm_b_T_3) node imm_b_hi = cat(_imm_b_T, _imm_b_T_1) node imm_b = cat(imm_b_hi, imm_b_lo) node _imm_u_T = bits(io.imem.resp.bits.inst, 31, 12) node _imm_u_T_1 = mux(UInt<1>(0h0), UInt<12>(0hfff), UInt<12>(0h0)) node imm_u = cat(_imm_u_T, _imm_u_T_1) node _imm_j_T = bits(io.imem.resp.bits.inst, 31, 31) node _imm_j_T_1 = bits(io.imem.resp.bits.inst, 19, 12) node _imm_j_T_2 = bits(io.imem.resp.bits.inst, 20, 20) node _imm_j_T_3 = bits(io.imem.resp.bits.inst, 30, 21) node imm_j_lo = cat(_imm_j_T_2, _imm_j_T_3) node imm_j_hi = cat(_imm_j_T, _imm_j_T_1) node imm_j = cat(imm_j_hi, imm_j_lo) node imm_z = bits(io.imem.resp.bits.inst, 19, 15) node _imm_i_sext_T = bits(imm_i, 11, 11) node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) node _imm_s_sext_T = bits(imm_s, 11, 11) node _imm_s_sext_T_1 = mux(_imm_s_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_s_sext = cat(_imm_s_sext_T_1, imm_s) node _imm_b_sext_T = bits(imm_b, 11, 11) node _imm_b_sext_T_1 = mux(_imm_b_sext_T, UInt<19>(0h7ffff), UInt<19>(0h0)) node imm_b_sext_hi = cat(_imm_b_sext_T_1, imm_b) node imm_b_sext = cat(imm_b_sext_hi, UInt<1>(0h0)) node _imm_j_sext_T = bits(imm_j, 19, 19) node _imm_j_sext_T_1 = mux(_imm_j_sext_T, UInt<11>(0h7ff), UInt<11>(0h0)) node imm_j_sext_hi = cat(_imm_j_sext_T_1, imm_j) node imm_j_sext = cat(imm_j_sext_hi, UInt<1>(0h0)) node _exe_rs1_data_T = eq(wb_reg_wbaddr, exe_rs1_addr) node _exe_rs1_data_T_1 = neq(exe_rs1_addr, UInt<1>(0h0)) node _exe_rs1_data_T_2 = and(_exe_rs1_data_T, _exe_rs1_data_T_1) node _exe_rs1_data_T_3 = and(_exe_rs1_data_T_2, wb_reg_ctrl.rf_wen) node _exe_rs1_data_T_4 = and(_exe_rs1_data_T_3, wb_reg_ctrl.bypassable) node exe_rs1_data = mux(_exe_rs1_data_T_4, wb_reg_alu, rf_rs1_data) node _exe_rs2_data_T = eq(wb_reg_wbaddr, exe_rs2_addr) node _exe_rs2_data_T_1 = neq(exe_rs2_addr, UInt<1>(0h0)) node _exe_rs2_data_T_2 = and(_exe_rs2_data_T, _exe_rs2_data_T_1) node _exe_rs2_data_T_3 = and(_exe_rs2_data_T_2, wb_reg_ctrl.rf_wen) node _exe_rs2_data_T_4 = and(_exe_rs2_data_T_3, wb_reg_ctrl.bypassable) node exe_rs2_data = mux(_exe_rs2_data_T_4, wb_reg_alu, rf_rs2_data) node _exe_alu_op1_T = eq(io.ctl.op1_sel, UInt<2>(0h2)) node _exe_alu_op1_T_1 = eq(io.ctl.op1_sel, UInt<2>(0h1)) node _exe_alu_op1_T_2 = mux(_exe_alu_op1_T_1, imm_u, exe_rs1_data) node exe_alu_op1 = mux(_exe_alu_op1_T, imm_z, _exe_alu_op1_T_2) node _exe_alu_op2_T = eq(io.ctl.op2_sel, UInt<2>(0h1)) node _exe_alu_op2_T_1 = eq(io.ctl.op2_sel, UInt<2>(0h3)) node _exe_alu_op2_T_2 = eq(io.ctl.op2_sel, UInt<2>(0h2)) node _exe_alu_op2_T_3 = mux(_exe_alu_op2_T_2, imm_s_sext, exe_rs2_data) node _exe_alu_op2_T_4 = mux(_exe_alu_op2_T_1, io.imem.resp.bits.pc, _exe_alu_op2_T_3) node exe_alu_op2 = mux(_exe_alu_op2_T, imm_i_sext, _exe_alu_op2_T_4) inst alu of ALU connect alu.clock, clock connect alu.reset, reset connect alu.io.in1, exe_alu_op1 connect alu.io.in2, exe_alu_op2 connect alu.io.fn, io.ctl.alu_fun node imm_brjmp = mux(io.ctl.brjmp_sel, imm_j_sext, imm_b_sext) node _exe_brjmp_target_T = add(io.imem.resp.bits.pc, imm_brjmp) node _exe_brjmp_target_T_1 = tail(_exe_brjmp_target_T, 1) connect exe_brjmp_target, _exe_brjmp_target_T_1 node _exe_jump_reg_target_T = not(UInt<32>(0h1)) node _exe_jump_reg_target_T_1 = and(alu.io.adder_out, _exe_jump_reg_target_T) connect exe_jump_reg_target, _exe_jump_reg_target_T_1 node _io_dat_br_eq_T = eq(exe_rs1_data, exe_rs2_data) connect io.dat.br_eq, _io_dat_br_eq_T node _io_dat_br_lt_T = asSInt(exe_rs1_data) node _io_dat_br_lt_T_1 = asSInt(exe_rs2_data) node _io_dat_br_lt_T_2 = lt(_io_dat_br_lt_T, _io_dat_br_lt_T_1) connect io.dat.br_lt, _io_dat_br_lt_T_2 node _io_dat_br_ltu_T = lt(exe_rs1_data, exe_rs2_data) connect io.dat.br_ltu, _io_dat_br_ltu_T node mem_address_low = bits(alu.io.out, 2, 0) wire misaligned_mask : UInt<3> node _misaligned_mask_T = sub(io.ctl.dmem_typ, UInt<1>(0h1)) node _misaligned_mask_T_1 = tail(_misaligned_mask_T, 1) node _misaligned_mask_T_2 = bits(_misaligned_mask_T_1, 1, 0) node _misaligned_mask_T_3 = dshl(UInt<3>(0h7), _misaligned_mask_T_2) node _misaligned_mask_T_4 = not(_misaligned_mask_T_3) connect misaligned_mask, _misaligned_mask_T_4 node _io_dat_data_misaligned_T = and(misaligned_mask, mem_address_low) node _io_dat_data_misaligned_T_1 = orr(_io_dat_data_misaligned_T) node _io_dat_data_misaligned_T_2 = and(_io_dat_data_misaligned_T_1, io.ctl.dmem_val) connect io.dat.data_misaligned, _io_dat_data_misaligned_T_2 node _io_dmem_req_valid_T = eq(io.dat.data_misaligned, UInt<1>(0h0)) node _io_dmem_req_valid_T_1 = and(io.ctl.dmem_val, _io_dmem_req_valid_T) node _io_dmem_req_valid_T_2 = eq(wb_hazard_stall, UInt<1>(0h0)) node _io_dmem_req_valid_T_3 = and(_io_dmem_req_valid_T_1, _io_dmem_req_valid_T_2) connect io.dmem.req.valid, _io_dmem_req_valid_T_3 node _io_dmem_req_bits_fcn_T = eq(wb_hazard_stall, UInt<1>(0h0)) node _io_dmem_req_bits_fcn_T_1 = and(io.ctl.dmem_fcn, _io_dmem_req_bits_fcn_T) node _io_dmem_req_bits_fcn_T_2 = and(_io_dmem_req_bits_fcn_T_1, io.imem.resp.valid) connect io.dmem.req.bits.fcn, _io_dmem_req_bits_fcn_T_2 connect io.dmem.req.bits.typ, io.ctl.dmem_typ connect io.dmem.req.bits.addr, alu.io.out connect io.dmem.req.bits.data, exe_rs2_data node _wb_dmiss_stall_T = eq(io.dmem.req.ready, UInt<1>(0h0)) node _wb_dmiss_stall_T_1 = and(_wb_dmiss_stall_T, io.dmem.req.valid) node _wb_dmiss_stall_T_2 = eq(io.dmem.resp.valid, UInt<1>(0h0)) node _wb_dmiss_stall_T_3 = and(wb_reg_mem, _wb_dmiss_stall_T_2) node _wb_dmiss_stall_T_4 = or(_wb_dmiss_stall_T_1, _wb_dmiss_stall_T_3) connect wb_dmiss_stall, _wb_dmiss_stall_T_4 node _T_6 = eq(wb_dmiss_stall, UInt<1>(0h0)) when _T_6 : node _T_7 = or(wb_hazard_stall, io.ctl.exe_kill) node _T_8 = eq(io.imem.resp.valid, UInt<1>(0h0)) node _T_9 = or(_T_7, _T_8) when _T_9 : connect wb_reg_inst, UInt<32>(0h4033) connect wb_reg_valid, UInt<1>(0h0) connect wb_reg_ctrl.rf_wen, UInt<1>(0h0) connect wb_reg_ctrl.csr_cmd, UInt<3>(0h0) connect wb_reg_ctrl.dmem_val, UInt<1>(0h0) connect wb_reg_ctrl.exception, UInt<1>(0h0) connect wb_reg_mem, UInt<1>(0h0) else : connect wb_reg_inst, io.imem.resp.bits.inst connect wb_reg_valid, io.imem.resp.valid connect wb_reg_ctrl, io.ctl connect wb_reg_pc, io.imem.resp.bits.pc connect wb_reg_alu, alu.io.out connect wb_reg_wbaddr, exe_wbaddr node _wb_reg_csr_addr_T = bits(io.imem.resp.bits.inst, 31, 20) connect wb_reg_csr_addr, _wb_reg_csr_addr_T connect wb_reg_target_pc, exe_target_pc connect wb_reg_mem, io.dmem.req.valid wire _hits_WIRE : UInt<1>[1] connect _hits_WIRE[0], UInt<1>(0h0) wire hits : UInt<1>[1] connect hits, _hits_WIRE inst csr of CSRFile connect csr.clock, clock connect csr.reset, reset invalidate csr.io.fiom invalidate csr.io.scontext invalidate csr.io.mcontext invalidate csr.io.trace[0].tval invalidate csr.io.trace[0].cause invalidate csr.io.trace[0].interrupt invalidate csr.io.trace[0].exception invalidate csr.io.trace[0].priv invalidate csr.io.trace[0].insn invalidate csr.io.trace[0].iaddr invalidate csr.io.trace[0].valid invalidate csr.io.inst[0] invalidate csr.io.inhibit_cycle invalidate csr.io.csrw_counter invalidate csr.io.interrupt_cause invalidate csr.io.interrupt invalidate csr.io.rocc_interrupt invalidate csr.io.fcsr_flags.bits invalidate csr.io.fcsr_flags.valid invalidate csr.io.fcsr_rm invalidate csr.io.time invalidate csr.io.gva invalidate csr.io.mhtinst_read_pseudo invalidate csr.io.htval invalidate csr.io.tval invalidate csr.io.pc invalidate csr.io.cause invalidate csr.io.retire invalidate csr.io.exception invalidate csr.io.evec invalidate csr.io.vsatp.ppn invalidate csr.io.vsatp.asid invalidate csr.io.vsatp.mode invalidate csr.io.hgatp.ppn invalidate csr.io.hgatp.asid invalidate csr.io.hgatp.mode invalidate csr.io.ptbr.ppn invalidate csr.io.ptbr.asid invalidate csr.io.ptbr.mode invalidate csr.io.gstatus.uie invalidate csr.io.gstatus.sie invalidate csr.io.gstatus.hie invalidate csr.io.gstatus.mie invalidate csr.io.gstatus.upie invalidate csr.io.gstatus.spie invalidate csr.io.gstatus.ube invalidate csr.io.gstatus.mpie invalidate csr.io.gstatus.spp invalidate csr.io.gstatus.vs invalidate csr.io.gstatus.mpp invalidate csr.io.gstatus.fs invalidate csr.io.gstatus.xs invalidate csr.io.gstatus.mprv invalidate csr.io.gstatus.sum invalidate csr.io.gstatus.mxr invalidate csr.io.gstatus.tvm invalidate csr.io.gstatus.tw invalidate csr.io.gstatus.tsr invalidate csr.io.gstatus.zero1 invalidate csr.io.gstatus.sd_rv32 invalidate csr.io.gstatus.uxl invalidate csr.io.gstatus.sxl invalidate csr.io.gstatus.sbe invalidate csr.io.gstatus.mbe invalidate csr.io.gstatus.gva invalidate csr.io.gstatus.mpv invalidate csr.io.gstatus.zero2 invalidate csr.io.gstatus.sd invalidate csr.io.gstatus.v invalidate csr.io.gstatus.prv invalidate csr.io.gstatus.dv invalidate csr.io.gstatus.dprv invalidate csr.io.gstatus.isa invalidate csr.io.gstatus.wfi invalidate csr.io.gstatus.cease invalidate csr.io.gstatus.debug invalidate csr.io.hstatus.zero1 invalidate csr.io.hstatus.vsbe invalidate csr.io.hstatus.gva invalidate csr.io.hstatus.spv invalidate csr.io.hstatus.spvp invalidate csr.io.hstatus.hu invalidate csr.io.hstatus.zero2 invalidate csr.io.hstatus.vgein invalidate csr.io.hstatus.zero3 invalidate csr.io.hstatus.vtvm invalidate csr.io.hstatus.vtw invalidate csr.io.hstatus.vtsr invalidate csr.io.hstatus.zero5 invalidate csr.io.hstatus.vsxl invalidate csr.io.hstatus.zero6 invalidate csr.io.status.uie invalidate csr.io.status.sie invalidate csr.io.status.hie invalidate csr.io.status.mie invalidate csr.io.status.upie invalidate csr.io.status.spie invalidate csr.io.status.ube invalidate csr.io.status.mpie invalidate csr.io.status.spp invalidate csr.io.status.vs invalidate csr.io.status.mpp invalidate csr.io.status.fs invalidate csr.io.status.xs invalidate csr.io.status.mprv invalidate csr.io.status.sum invalidate csr.io.status.mxr invalidate csr.io.status.tvm invalidate csr.io.status.tw invalidate csr.io.status.tsr invalidate csr.io.status.zero1 invalidate csr.io.status.sd_rv32 invalidate csr.io.status.uxl invalidate csr.io.status.sxl invalidate csr.io.status.sbe invalidate csr.io.status.mbe invalidate csr.io.status.gva invalidate csr.io.status.mpv invalidate csr.io.status.zero2 invalidate csr.io.status.sd invalidate csr.io.status.v invalidate csr.io.status.prv invalidate csr.io.status.dv invalidate csr.io.status.dprv invalidate csr.io.status.isa invalidate csr.io.status.wfi invalidate csr.io.status.cease invalidate csr.io.status.debug invalidate csr.io.singleStep invalidate csr.io.eret invalidate csr.io.rw_stall invalidate csr.io.csr_stall invalidate csr.io.decode[0].virtual_system_illegal invalidate csr.io.decode[0].virtual_access_illegal invalidate csr.io.decode[0].system_illegal invalidate csr.io.decode[0].write_flush invalidate csr.io.decode[0].write_illegal invalidate csr.io.decode[0].read_illegal invalidate csr.io.decode[0].rocc_illegal invalidate csr.io.decode[0].vector_csr invalidate csr.io.decode[0].fp_csr invalidate csr.io.decode[0].vector_illegal invalidate csr.io.decode[0].fp_illegal invalidate csr.io.decode[0].inst invalidate csr.io.rw.wdata invalidate csr.io.rw.rdata invalidate csr.io.rw.cmd invalidate csr.io.rw.addr invalidate csr.io.hartid invalidate csr.io.interrupts.meip invalidate csr.io.interrupts.msip invalidate csr.io.interrupts.mtip invalidate csr.io.interrupts.debug invalidate csr.io.ungated_clock node _csr_io_decode_0_inst_T = shl(wb_reg_csr_addr, 20) connect csr.io.decode[0].inst, _csr_io_decode_0_inst_T node _csr_io_rw_addr_T = bits(wb_reg_inst, 31, 20) connect csr.io.rw.addr, _csr_io_rw_addr_T connect csr.io.rw.wdata, wb_reg_alu node _csr_io_rw_cmd_T = mux(wb_dmiss_stall, UInt<3>(0h0), wb_reg_ctrl.csr_cmd) connect csr.io.rw.cmd, _csr_io_rw_cmd_T node _csr_io_retire_T = eq(io.ctl.exception, UInt<1>(0h0)) node _csr_io_retire_T_1 = and(wb_reg_valid, _csr_io_retire_T) connect csr.io.retire, _csr_io_retire_T_1 connect csr.io.exception, io.ctl.exception connect csr.io.pc, wb_reg_pc connect exception_target, csr.io.evec connect io.dat.csr_eret, csr.io.eret connect tval_data_ma, wb_reg_alu connect tval_inst_ma, wb_reg_target_pc node _csr_io_tval_T = eq(io.ctl.exception_cause, UInt<2>(0h2)) node _csr_io_tval_T_1 = eq(io.ctl.exception_cause, UInt<1>(0h0)) node _csr_io_tval_T_2 = eq(io.ctl.exception_cause, UInt<3>(0h6)) node _csr_io_tval_T_3 = eq(io.ctl.exception_cause, UInt<3>(0h4)) node _csr_io_tval_T_4 = mux(_csr_io_tval_T_3, tval_data_ma, UInt<1>(0h0)) node _csr_io_tval_T_5 = mux(_csr_io_tval_T_2, tval_data_ma, _csr_io_tval_T_4) node _csr_io_tval_T_6 = mux(_csr_io_tval_T_1, tval_inst_ma, _csr_io_tval_T_5) node _csr_io_tval_T_7 = mux(_csr_io_tval_T, wb_reg_inst, _csr_io_tval_T_6) connect csr.io.tval, _csr_io_tval_T_7 regreset reg_interrupt_flag : UInt<1>, clock, reset, UInt<1>(0h0) connect reg_interrupt_flag, csr.io.interrupt node _interrupt_edge_T = eq(reg_interrupt_flag, UInt<1>(0h0)) node interrupt_edge = and(csr.io.interrupt, _interrupt_edge_T) connect csr.io.interrupts.meip, io.interrupt.meip connect csr.io.interrupts.msip, io.interrupt.msip connect csr.io.interrupts.mtip, io.interrupt.mtip connect csr.io.interrupts.debug, io.interrupt.debug connect csr.io.hartid, io.hartid connect io.dat.csr_interrupt, interrupt_edge node _csr_io_cause_T = mux(io.ctl.exception, io.ctl.exception_cause, csr.io.interrupt_cause) connect csr.io.cause, _csr_io_cause_T connect csr.io.ungated_clock, clock node _wb_wbdata_T = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h0)) node _wb_wbdata_T_1 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h1)) node _wb_wbdata_T_2 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h2)) node _wb_wbdata_T_3 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h3)) node _wb_wbdata_T_4 = mux(_wb_wbdata_T_3, csr.io.rw.rdata, wb_reg_alu) node _wb_wbdata_T_5 = mux(_wb_wbdata_T_2, io.imem.resp.bits.pc, _wb_wbdata_T_4) node _wb_wbdata_T_6 = mux(_wb_wbdata_T_1, io.dmem.resp.bits.data, _wb_wbdata_T_5) node _wb_wbdata_T_7 = mux(_wb_wbdata_T, wb_reg_alu, _wb_wbdata_T_6) connect wb_wbdata, _wb_wbdata_T_7 node _debug_wb_inst_T = or(wb_hazard_stall, io.ctl.exe_kill) node _debug_wb_inst_T_1 = eq(io.imem.resp.valid, UInt<1>(0h0)) node _debug_wb_inst_T_2 = or(_debug_wb_inst_T, _debug_wb_inst_T_1) node _debug_wb_inst_T_3 = mux(_debug_wb_inst_T_2, UInt<32>(0h4033), io.imem.resp.bits.inst) reg debug_wb_inst : UInt, clock connect debug_wb_inst, _debug_wb_inst_T_3 node _T_10 = bits(csr.io.time, 31, 0) reg REG : UInt, clock connect REG, exe_rs1_addr reg REG_1 : UInt, clock connect REG_1, exe_alu_op1 reg REG_2 : UInt, clock connect REG_2, exe_rs2_addr reg REG_3 : UInt, clock connect REG_3, exe_alu_op2 node _T_11 = mux(io.ctl.exe_kill, UInt<8>(0h4b), UInt<8>(0h20)) node _T_12 = mux(wb_hazard_stall, UInt<8>(0h48), _T_11) node _T_13 = eq(UInt<3>(0h1), io.ctl.pc_sel) node _T_14 = mux(_T_13, UInt<8>(0h42), UInt<8>(0h3f)) node _T_15 = eq(UInt<3>(0h2), io.ctl.pc_sel) node _T_16 = mux(_T_15, UInt<8>(0h4a), _T_14) node _T_17 = eq(UInt<3>(0h3), io.ctl.pc_sel) node _T_18 = mux(_T_17, UInt<8>(0h52), _T_16) node _T_19 = eq(UInt<3>(0h4), io.ctl.pc_sel) node _T_20 = mux(_T_19, UInt<8>(0h45), _T_18) node _T_21 = eq(UInt<3>(0h0), io.ctl.pc_sel) node _T_22 = mux(_T_21, UInt<8>(0h20), _T_20) node _T_23 = mux(csr.io.exception, UInt<8>(0h58), UInt<8>(0h20)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Cyc= %d [%d] pc=[%x] W[r%d=%x][%d] Op1=[r%d][%x] Op2=[r%d][%x] inst=[%x] %c%c%c DASM(%x)\n", _T_10, csr.io.retire, wb_reg_pc, wb_reg_wbaddr, wb_wbdata, wb_reg_ctrl.rf_wen, REG, REG_1, REG_2, REG_3, debug_wb_inst, _T_12, _T_22, _T_23, debug_wb_inst) : printf	module DatPath( // @[dpath.scala:50:7] input clock, // @[dpath.scala:50:7] input reset, // @[dpath.scala:50:7] output [31:0] io_ddpath_rdata, // @[dpath.scala:52:15] output [31:0] io_imem_req_bits_pc, // @[dpath.scala:52:15] output io_imem_resp_ready, // @[dpath.scala:52:15] input io_imem_resp_valid, // @[dpath.scala:52:15] input [31:0] io_imem_resp_bits_pc, // @[dpath.scala:52:15] input [31:0] io_imem_resp_bits_inst, // @[dpath.scala:52:15] input [31:0] io_imem_debug_if_pc, // @[dpath.scala:52:15] input [31:0] io_imem_debug_if_inst, // @[dpath.scala:52:15] input io_dmem_req_ready, // @[dpath.scala:52:15] output io_dmem_req_valid, // @[dpath.scala:52:15] output [31:0] io_dmem_req_bits_addr, // @[dpath.scala:52:15] output [31:0] io_dmem_req_bits_data, // @[dpath.scala:52:15] output io_dmem_req_bits_fcn, // @[dpath.scala:52:15] output [2:0] io_dmem_req_bits_typ, // @[dpath.scala:52:15] input io_dmem_resp_valid, // @[dpath.scala:52:15] input [31:0] io_dmem_resp_bits_data, // @[dpath.scala:52:15] input io_ctl_exe_kill, // @[dpath.scala:52:15] input [2:0] io_ctl_pc_sel, // @[dpath.scala:52:15] input io_ctl_brjmp_sel, // @[dpath.scala:52:15] input [1:0] io_ctl_op1_sel, // @[dpath.scala:52:15] input [1:0] io_ctl_op2_sel, // @[dpath.scala:52:15] input [3:0] io_ctl_alu_fun, // @[dpath.scala:52:15] input [1:0] io_ctl_wb_sel, // @[dpath.scala:52:15] input io_ctl_rf_wen, // @[dpath.scala:52:15] input io_ctl_bypassable, // @[dpath.scala:52:15] input [2:0] io_ctl_csr_cmd, // @[dpath.scala:52:15] input io_ctl_dmem_val, // @[dpath.scala:52:15] input io_ctl_dmem_fcn, // @[dpath.scala:52:15] input [2:0] io_ctl_dmem_typ, // @[dpath.scala:52:15] input io_ctl_exception, // @[dpath.scala:52:15] input [31:0] io_ctl_exception_cause, // @[dpath.scala:52:15] output io_dat_br_eq, // @[dpath.scala:52:15] output io_dat_br_lt, // @[dpath.scala:52:15] output io_dat_br_ltu, // @[dpath.scala:52:15] output io_dat_inst_misaligned, // @[dpath.scala:52:15] output io_dat_data_misaligned, // @[dpath.scala:52:15] output io_dat_wb_hazard_stall, // @[dpath.scala:52:15] output io_dat_csr_eret, // @[dpath.scala:52:15] output io_dat_csr_interrupt, // @[dpath.scala:52:15] input io_interrupt_debug, // @[dpath.scala:52:15] input io_interrupt_mtip, // @[dpath.scala:52:15] input io_interrupt_msip, // @[dpath.scala:52:15] input io_interrupt_meip, // @[dpath.scala:52:15] input io_hartid // @[dpath.scala:52:15] ); wire [31:0] _csr_io_rw_rdata; // @[dpath.scala:259:20] wire [31:0] _csr_io_time; // @[dpath.scala:259:20] wire _csr_io_interrupt; // @[dpath.scala:259:20] wire [31:0] _csr_io_interrupt_cause; // @[dpath.scala:259:20] wire [31:0] _alu_io_out; // @[dpath.scala:190:20] wire [31:0] _alu_io_adder_out; // @[dpath.scala:190:20] wire [31:0] _regfile_ext_R0_data; // @[dpath.scala:135:21] wire [31:0] _regfile_ext_R1_data; // @[dpath.scala:135:21] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[dpath.scala:50:7] wire [31:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[dpath.scala:50:7] wire [31:0] io_imem_resp_bits_inst_0 = io_imem_resp_bits_inst; // @[dpath.scala:50:7] wire [31:0] io_imem_debug_if_pc_0 = io_imem_debug_if_pc; // @[dpath.scala:50:7] wire [31:0] io_imem_debug_if_inst_0 = io_imem_debug_if_inst; // @[dpath.scala:50:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[dpath.scala:50:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[dpath.scala:50:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[dpath.scala:50:7] wire io_ctl_exe_kill_0 = io_ctl_exe_kill; // @[dpath.scala:50:7] wire [2:0] io_ctl_pc_sel_0 = io_ctl_pc_sel; // @[dpath.scala:50:7] wire io_ctl_brjmp_sel_0 = io_ctl_brjmp_sel; // @[dpath.scala:50:7] wire [1:0] io_ctl_op1_sel_0 = io_ctl_op1_sel; // @[dpath.scala:50:7] wire [1:0] io_ctl_op2_sel_0 = io_ctl_op2_sel; // @[dpath.scala:50:7] wire [3:0] io_ctl_alu_fun_0 = io_ctl_alu_fun; // @[dpath.scala:50:7] wire [1:0] io_ctl_wb_sel_0 = io_ctl_wb_sel; // @[dpath.scala:50:7] wire io_ctl_rf_wen_0 = io_ctl_rf_wen; // @[dpath.scala:50:7] wire io_ctl_bypassable_0 = io_ctl_bypassable; // @[dpath.scala:50:7] wire [2:0] io_ctl_csr_cmd_0 = io_ctl_csr_cmd; // @[dpath.scala:50:7] wire io_ctl_dmem_val_0 = io_ctl_dmem_val; // @[dpath.scala:50:7] wire io_ctl_dmem_fcn_0 = io_ctl_dmem_fcn; // @[dpath.scala:50:7] wire [2:0] io_ctl_dmem_typ_0 = io_ctl_dmem_typ; // @[dpath.scala:50:7] wire io_ctl_exception_0 = io_ctl_exception; // @[dpath.scala:50:7] wire [31:0] io_ctl_exception_cause_0 = io_ctl_exception_cause; // @[dpath.scala:50:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[dpath.scala:50:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[dpath.scala:50:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[dpath.scala:50:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[dpath.scala:50:7] wire io_hartid_0 = io_hartid; // @[dpath.scala:50:7] wire [4:0] io_ddpath_addr = 5'h0; // @[dpath.scala:50:7] wire [31:0] io_ddpath_wdata = 32'h0; // @[dpath.scala:50:7] wire io_ddpath_validreq = 1'h0; // @[dpath.scala:50:7] wire io_ddpath_resetpc = 1'h0; // @[dpath.scala:50:7] wire io_imem_req_valid = 1'h0; // @[dpath.scala:50:7] wire io_imem_imiss = 1'h0; // @[dpath.scala:50:7] wire io_imem_exe_kill = 1'h0; // @[dpath.scala:50:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire [31:0] _exe_jump_reg_target_T = 32'hFFFFFFFE; // @[dpath.scala:201:46] wire [11:0] _imm_u_T_1 = 12'h0; // @[dpath.scala:157:42] wire [31:0] take_pc; // @[dpath.scala:83:21] wire _io_imem_resp_ready_T_2; // @[dpath.scala:80:43] wire _io_dmem_req_valid_T_3; // @[dpath.scala:217:72] wire [31:0] exe_rs2_data; // @[Mux.scala:126:16] wire _io_dmem_req_bits_fcn_T_2; // @[dpath.scala:221:67] wire [2:0] io_dmem_req_bits_typ_0 = io_ctl_dmem_typ_0; // @[dpath.scala:50:7] wire _io_dat_br_eq_T; // @[dpath.scala:205:35] wire _io_dat_br_lt_T_2; // @[dpath.scala:206:42] wire _io_dat_br_ltu_T; // @[dpath.scala:207:42] wire _io_dat_inst_misaligned_T_11; // @[dpath.scala:91:91] wire _io_dat_data_misaligned_T_2; // @[dpath.scala:214:70] wire wb_hazard_stall; // @[dpath.scala:71:31] wire interrupt_edge; // @[dpath.scala:284:42] wire [31:0] io_ddpath_rdata_0; // @[dpath.scala:50:7] wire [31:0] io_imem_req_bits_pc_0; // @[dpath.scala:50:7] wire io_imem_resp_ready_0; // @[dpath.scala:50:7] wire [31:0] io_dmem_req_bits_addr_0; // @[dpath.scala:50:7] wire [31:0] io_dmem_req_bits_data_0; // @[dpath.scala:50:7] wire io_dmem_req_bits_fcn_0; // @[dpath.scala:50:7] wire io_dmem_req_valid_0; // @[dpath.scala:50:7] wire io_dat_br_eq_0; // @[dpath.scala:50:7] wire io_dat_br_lt_0; // @[dpath.scala:50:7] wire io_dat_br_ltu_0; // @[dpath.scala:50:7] wire io_dat_inst_misaligned_0; // @[dpath.scala:50:7] wire io_dat_data_misaligned_0; // @[dpath.scala:50:7] wire io_dat_wb_hazard_stall_0; // @[dpath.scala:50:7] wire io_dat_csr_eret_0; // @[dpath.scala:50:7] wire io_dat_csr_interrupt_0; // @[dpath.scala:50:7] wire [31:0] tval_data_ma; // @[dpath.scala:56:27] wire [31:0] tval_inst_ma; // @[dpath.scala:57:27] reg [31:0] wb_reg_inst; // @[dpath.scala:61:34] reg wb_reg_valid; // @[dpath.scala:62:34] reg wb_reg_ctrl_exe_kill; // @[dpath.scala:63:30] reg [2:0] wb_reg_ctrl_pc_sel; // @[dpath.scala:63:30] reg wb_reg_ctrl_brjmp_sel; // @[dpath.scala:63:30] reg [1:0] wb_reg_ctrl_op1_sel; // @[dpath.scala:63:30] reg [1:0] wb_reg_ctrl_op2_sel; // @[dpath.scala:63:30] reg [3:0] wb_reg_ctrl_alu_fun; // @[dpath.scala:63:30] reg [1:0] wb_reg_ctrl_wb_sel; // @[dpath.scala:63:30] reg wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30] reg wb_reg_ctrl_bypassable; // @[dpath.scala:63:30] reg [2:0] wb_reg_ctrl_csr_cmd; // @[dpath.scala:63:30] reg wb_reg_ctrl_dmem_val; // @[dpath.scala:63:30] reg wb_reg_ctrl_dmem_fcn; // @[dpath.scala:63:30] reg [2:0] wb_reg_ctrl_dmem_typ; // @[dpath.scala:63:30] reg wb_reg_ctrl_exception; // @[dpath.scala:63:30] reg [31:0] wb_reg_ctrl_exception_cause; // @[dpath.scala:63:30] reg [31:0] wb_reg_pc; // @[dpath.scala:64:30] reg [31:0] wb_reg_alu; // @[dpath.scala:65:30] assign tval_data_ma = wb_reg_alu; // @[dpath.scala:56:27, :65:30] reg [11:0] wb_reg_csr_addr; // @[dpath.scala:66:30] reg [4:0] wb_reg_wbaddr; // @[dpath.scala:67:30] reg [31:0] wb_reg_target_pc; // @[dpath.scala:68:30] assign tval_inst_ma = wb_reg_target_pc; // @[dpath.scala:57:27, :68:30] reg wb_reg_mem; // @[dpath.scala:69:34] wire _wb_hazard_stall_T_12; // @[dpath.scala:128:136] assign io_dat_wb_hazard_stall_0 = wb_hazard_stall; // @[dpath.scala:50:7, :71:31] wire _wb_dmiss_stall_T_4; // @[dpath.scala:227:64] wire wb_dmiss_stall; // @[dpath.scala:72:31] wire [31:0] _exe_brjmp_target_T_1; // @[dpath.scala:200:31] wire [31:0] exe_brjmp_target; // @[dpath.scala:76:34] wire [31:0] _exe_jump_reg_target_T_1; // @[dpath.scala:201:44] wire [31:0] exe_jump_reg_target; // @[dpath.scala:77:34] wire [31:0] exception_target; // @[dpath.scala:78:34] wire _io_imem_resp_ready_T = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26] wire _io_imem_resp_ready_T_1 = ~wb_dmiss_stall; // @[dpath.scala:72:31, :80:46] assign _io_imem_resp_ready_T_2 = _io_imem_resp_ready_T & _io_imem_resp_ready_T_1; // @[dpath.scala:80:{26,43,46}] assign io_imem_resp_ready_0 = _io_imem_resp_ready_T_2; // @[dpath.scala:50:7, :80:43] wire _take_pc_T = io_ctl_pc_sel_0 == 3'h4; // @[dpath.scala:50:7, :83:36] wire _T_17 = io_ctl_pc_sel_0 == 3'h3; // @[dpath.scala:50:7, :84:36] wire _take_pc_T_1; // @[dpath.scala:84:36] assign _take_pc_T_1 = _T_17; // @[dpath.scala:84:36] wire _io_dat_inst_misaligned_T_8; // @[dpath.scala:91:79] assign _io_dat_inst_misaligned_T_8 = _T_17; // @[dpath.scala:84:36, :91:79] wire _exe_target_pc_T; // @[dpath.scala:93:43] assign _exe_target_pc_T = _T_17; // @[dpath.scala:84:36, :93:43] wire [31:0] _take_pc_T_2 = _take_pc_T_1 ? exe_jump_reg_target : exe_brjmp_target; // @[dpath.scala:76:34, :77:34, :84:{21,36}] assign take_pc = _take_pc_T ? exception_target : _take_pc_T_2; // @[dpath.scala:78:34, :83:{21,36}, :84:21] assign io_imem_req_bits_pc_0 = take_pc; // @[dpath.scala:50:7, :83:21] wire [1:0] _io_dat_inst_misaligned_T = exe_brjmp_target[1:0]; // @[dpath.scala:76:34, :90:48] wire _io_dat_inst_misaligned_T_1 = \|_io_dat_inst_misaligned_T; // @[dpath.scala:90:{48,55}] wire _io_dat_inst_misaligned_T_2 = io_ctl_pc_sel_0 == 3'h1; // @[dpath.scala:50:7, :90:80] wire _io_dat_inst_misaligned_T_3 = io_ctl_pc_sel_0 == 3'h2; // @[dpath.scala:50:7, :90:107] wire _io_dat_inst_misaligned_T_4 = _io_dat_inst_misaligned_T_2 \| _io_dat_inst_misaligned_T_3; // @[dpath.scala:90:{80,90,107}] wire _io_dat_inst_misaligned_T_5 = _io_dat_inst_misaligned_T_1 & _io_dat_inst_misaligned_T_4; // @[dpath.scala:90:{55,62,90}] wire [1:0] _io_dat_inst_misaligned_T_6 = exe_jump_reg_target[1:0]; // @[dpath.scala:77:34, :91:51] wire _io_dat_inst_misaligned_T_7 = \|_io_dat_inst_misaligned_T_6; // @[dpath.scala:91:{51,58}] wire _io_dat_inst_misaligned_T_9 = _io_dat_inst_misaligned_T_7 & _io_dat_inst_misaligned_T_8; // @[dpath.scala:91:{58,62,79}] wire _io_dat_inst_misaligned_T_10 = _io_dat_inst_misaligned_T_5 \| _io_dat_inst_misaligned_T_9; // @[dpath.scala:90:{62,118}, :91:62] assign _io_dat_inst_misaligned_T_11 = _io_dat_inst_misaligned_T_10 & io_imem_resp_valid_0; // @[dpath.scala:50:7, :90:118, :91:91] assign io_dat_inst_misaligned_0 = _io_dat_inst_misaligned_T_11; // @[dpath.scala:50:7, :91:91] wire [31:0] exe_target_pc = _exe_target_pc_T ? exe_jump_reg_target : exe_brjmp_target; // @[dpath.scala:76:34, :77:34, :93:{27,43}] wire [4:0] exe_rs1_addr = io_imem_resp_bits_inst_0[19:15]; // @[dpath.scala:50:7, :105:31] wire [4:0] imm_z = io_imem_resp_bits_inst_0[19:15]; // @[dpath.scala:50:7, :105:31, :159:24] wire [4:0] exe_rs2_addr = io_imem_resp_bits_inst_0[24:20]; // @[dpath.scala:50:7, :106:31] wire [4:0] exe_wbaddr = io_imem_resp_bits_inst_0[11:7]; // @[dpath.scala:50:7, :107:31] wire [4:0] _imm_s_T_1 = io_imem_resp_bits_inst_0[11:7]; // @[dpath.scala:50:7, :107:31, :155:46] wire [31:0] _wb_wbdata_T_7; // @[Mux.scala:126:16] wire [31:0] wb_wbdata; // @[dpath.scala:109:27] wire _GEN = wb_reg_wbaddr == exe_rs1_addr; // @[dpath.scala:67:30, :105:31, :128:42] wire _wb_hazard_stall_T; // @[dpath.scala:128:42] assign _wb_hazard_stall_T = _GEN; // @[dpath.scala:128:42] wire _exe_rs1_data_T; // @[dpath.scala:171:44] assign _exe_rs1_data_T = _GEN; // @[dpath.scala:128:42, :171:44] wire _wb_hazard_stall_T_1 = \|exe_rs1_addr; // @[dpath.scala:105:31, :128:77] wire _wb_hazard_stall_T_2 = _wb_hazard_stall_T & _wb_hazard_stall_T_1; // @[dpath.scala:128:{42,60,77}] wire _wb_hazard_stall_T_3 = _wb_hazard_stall_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :128:{60,86}] wire _wb_hazard_stall_T_4 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :128:111] wire _wb_hazard_stall_T_5 = _wb_hazard_stall_T_3 & _wb_hazard_stall_T_4; // @[dpath.scala:128:{86,108,111}] wire _GEN_0 = wb_reg_wbaddr == exe_rs2_addr; // @[dpath.scala:67:30, :106:31, :129:42] wire _wb_hazard_stall_T_6; // @[dpath.scala:129:42] assign _wb_hazard_stall_T_6 = _GEN_0; // @[dpath.scala:129:42] wire _exe_rs2_data_T; // @[dpath.scala:174:44] assign _exe_rs2_data_T = _GEN_0; // @[dpath.scala:129:42, :174:44] wire _wb_hazard_stall_T_7 = \|exe_rs2_addr; // @[dpath.scala:106:31, :129:77] wire _wb_hazard_stall_T_8 = _wb_hazard_stall_T_6 & _wb_hazard_stall_T_7; // @[dpath.scala:129:{42,60,77}] wire _wb_hazard_stall_T_9 = _wb_hazard_stall_T_8 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :129:{60,86}] wire _wb_hazard_stall_T_10 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :128:111, :129:111] wire _wb_hazard_stall_T_11 = _wb_hazard_stall_T_9 & _wb_hazard_stall_T_10; // @[dpath.scala:129:{86,108,111}] assign _wb_hazard_stall_T_12 = _wb_hazard_stall_T_5 \| _wb_hazard_stall_T_11; // @[dpath.scala:128:{108,136}, :129:108] assign wb_hazard_stall = _wb_hazard_stall_T_12; // @[dpath.scala:71:31, :128:136] wire _rf_rs1_data_T = \|exe_rs1_addr; // @[dpath.scala:105:31, :128:77, :149:40] wire [31:0] rf_rs1_data = _rf_rs1_data_T ? _regfile_ext_R1_data : 32'h0; // @[dpath.scala:135:21, :149:{25,40}] wire _rf_rs2_data_T = \|exe_rs2_addr; // @[dpath.scala:106:31, :129:77, :150:40] wire [31:0] rf_rs2_data = _rf_rs2_data_T ? _regfile_ext_R0_data : 32'h0; // @[dpath.scala:135:21, :150:{25,40}] wire [11:0] imm_i = io_imem_resp_bits_inst_0[31:20]; // @[dpath.scala:50:7, :154:24] wire [11:0] _wb_reg_csr_addr_T = io_imem_resp_bits_inst_0[31:20]; // @[dpath.scala:50:7, :154:24, :249:37] wire [6:0] _imm_s_T = io_imem_resp_bits_inst_0[31:25]; // @[dpath.scala:50:7, :155:28] wire [11:0] imm_s = {_imm_s_T, _imm_s_T_1}; // @[dpath.scala:155:{19,28,46}] wire _imm_b_T = io_imem_resp_bits_inst_0[31]; // @[dpath.scala:50:7, :156:28] wire _imm_j_T = io_imem_resp_bits_inst_0[31]; // @[dpath.scala:50:7, :156:28, :158:28] wire _imm_b_T_1 = io_imem_resp_bits_inst_0[7]; // @[dpath.scala:50:7, :156:42] wire [5:0] _imm_b_T_2 = io_imem_resp_bits_inst_0[30:25]; // @[dpath.scala:50:7, :156:55] wire [3:0] _imm_b_T_3 = io_imem_resp_bits_inst_0[11:8]; // @[dpath.scala:50:7, :156:72] wire [9:0] imm_b_lo = {_imm_b_T_2, _imm_b_T_3}; // @[dpath.scala:156:{19,55,72}] wire [1:0] imm_b_hi = {_imm_b_T, _imm_b_T_1}; // @[dpath.scala:156:{19,28,42}] wire [11:0] imm_b = {imm_b_hi, imm_b_lo}; // @[dpath.scala:156:19] wire [19:0] _imm_u_T = io_imem_resp_bits_inst_0[31:12]; // @[dpath.scala:50:7, :157:28] wire [31:0] imm_u = {_imm_u_T, 12'h0}; // @[dpath.scala:157:{19,28}] wire [7:0] _imm_j_T_1 = io_imem_resp_bits_inst_0[19:12]; // @[dpath.scala:50:7, :158:42] wire _imm_j_T_2 = io_imem_resp_bits_inst_0[20]; // @[dpath.scala:50:7, :158:59] wire [9:0] _imm_j_T_3 = io_imem_resp_bits_inst_0[30:21]; // @[dpath.scala:50:7, :158:73] wire [10:0] imm_j_lo = {_imm_j_T_2, _imm_j_T_3}; // @[dpath.scala:158:{19,59,73}] wire [8:0] imm_j_hi = {_imm_j_T, _imm_j_T_1}; // @[dpath.scala:158:{19,28,42}] wire [19:0] imm_j = {imm_j_hi, imm_j_lo}; // @[dpath.scala:158:19] wire _imm_i_sext_T = imm_i[11]; // @[dpath.scala:154:24, :162:38] wire [19:0] _imm_i_sext_T_1 = {20{_imm_i_sext_T}}; // @[dpath.scala:162:{29,38}] wire [31:0] imm_i_sext = {_imm_i_sext_T_1, imm_i}; // @[dpath.scala:154:24, :162:{24,29}] wire _imm_s_sext_T = imm_s[11]; // @[dpath.scala:155:19, :163:38] wire [19:0] _imm_s_sext_T_1 = {20{_imm_s_sext_T}}; // @[dpath.scala:163:{29,38}] wire [31:0] imm_s_sext = {_imm_s_sext_T_1, imm_s}; // @[dpath.scala:155:19, :163:{24,29}] wire _imm_b_sext_T = imm_b[11]; // @[dpath.scala:156:19, :164:38] wire [18:0] _imm_b_sext_T_1 = {19{_imm_b_sext_T}}; // @[dpath.scala:164:{29,38}] wire [30:0] imm_b_sext_hi = {_imm_b_sext_T_1, imm_b}; // @[dpath.scala:156:19, :164:{24,29}] wire [31:0] imm_b_sext = {imm_b_sext_hi, 1'h0}; // @[dpath.scala:164:24] wire _imm_j_sext_T = imm_j[19]; // @[dpath.scala:158:19, :165:38] wire [10:0] _imm_j_sext_T_1 = {11{_imm_j_sext_T}}; // @[dpath.scala:165:{29,38}] wire [30:0] imm_j_sext_hi = {_imm_j_sext_T_1, imm_j}; // @[dpath.scala:158:19, :165:{24,29}] wire [31:0] imm_j_sext = {imm_j_sext_hi, 1'h0}; // @[dpath.scala:165:24] wire _exe_rs1_data_T_1 = \|exe_rs1_addr; // @[dpath.scala:105:31, :128:77, :171:79] wire _exe_rs1_data_T_2 = _exe_rs1_data_T & _exe_rs1_data_T_1; // @[dpath.scala:171:{44,62,79}] wire _exe_rs1_data_T_3 = _exe_rs1_data_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :171:{62,88}] wire _exe_rs1_data_T_4 = _exe_rs1_data_T_3 & wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :171:{88,110}] wire [31:0] exe_rs1_data = _exe_rs1_data_T_4 ? wb_reg_alu : rf_rs1_data; // @[Mux.scala:126:16] wire [31:0] _io_dat_br_lt_T = exe_rs1_data; // @[Mux.scala:126:16] wire _exe_rs2_data_T_1 = \|exe_rs2_addr; // @[dpath.scala:106:31, :129:77, :174:79] wire _exe_rs2_data_T_2 = _exe_rs2_data_T & _exe_rs2_data_T_1; // @[dpath.scala:174:{44,62,79}] wire _exe_rs2_data_T_3 = _exe_rs2_data_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :174:{62,88}] wire _exe_rs2_data_T_4 = _exe_rs2_data_T_3 & wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :174:{88,110}] assign exe_rs2_data = _exe_rs2_data_T_4 ? wb_reg_alu : rf_rs2_data; // @[Mux.scala:126:16] assign io_dmem_req_bits_data_0 = exe_rs2_data; // @[Mux.scala:126:16] wire [31:0] _io_dat_br_lt_T_1 = exe_rs2_data; // @[Mux.scala:126:16] wire _exe_alu_op1_T = io_ctl_op1_sel_0 == 2'h2; // @[dpath.scala:50:7, :179:41] wire _exe_alu_op1_T_1 = io_ctl_op1_sel_0 == 2'h1; // @[dpath.scala:50:7, :180:41] wire [31:0] _exe_alu_op1_T_2 = _exe_alu_op1_T_1 ? imm_u : exe_rs1_data; // @[Mux.scala:126:16] wire [31:0] exe_alu_op1 = _exe_alu_op1_T ? {27'h0, imm_z} : _exe_alu_op1_T_2; // @[dpath.scala:159:24, :179:{25,41}, :180:25] wire _exe_alu_op2_T = io_ctl_op2_sel_0 == 2'h1; // @[dpath.scala:50:7, :183:41] wire _exe_alu_op2_T_1 = &io_ctl_op2_sel_0; // @[dpath.scala:50:7, :184:41] wire _exe_alu_op2_T_2 = io_ctl_op2_sel_0 == 2'h2; // @[dpath.scala:50:7, :185:41] wire [31:0] _exe_alu_op2_T_3 = _exe_alu_op2_T_2 ? imm_s_sext : exe_rs2_data; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op2_T_4 = _exe_alu_op2_T_1 ? io_imem_resp_bits_pc_0 : _exe_alu_op2_T_3; // @[dpath.scala:50:7, :184:{25,41}, :185:25] wire [31:0] exe_alu_op2 = _exe_alu_op2_T ? imm_i_sext : _exe_alu_op2_T_4; // @[dpath.scala:162:24, :183:{25,41}, :184:25] wire [31:0] imm_brjmp = io_ctl_brjmp_sel_0 ? imm_j_sext : imm_b_sext; // @[dpath.scala:50:7, :164:24, :165:24, :199:23] wire [32:0] _exe_brjmp_target_T = {1'h0, io_imem_resp_bits_pc_0} + {1'h0, imm_brjmp}; // @[dpath.scala:50:7, :199:23, :200:31] assign _exe_brjmp_target_T_1 = _exe_brjmp_target_T[31:0]; // @[dpath.scala:200:31] assign exe_brjmp_target = _exe_brjmp_target_T_1; // @[dpath.scala:76:34, :200:31] assign _exe_jump_reg_target_T_1 = _alu_io_adder_out & 32'hFFFFFFFE; // @[dpath.scala:190:20, :201:44] assign exe_jump_reg_target = _exe_jump_reg_target_T_1; // @[dpath.scala:77:34, :201:44] assign _io_dat_br_eq_T = exe_rs1_data == exe_rs2_data; // @[Mux.scala:126:16] assign io_dat_br_eq_0 = _io_dat_br_eq_T; // @[dpath.scala:50:7, :205:35] assign _io_dat_br_lt_T_2 = $signed(_io_dat_br_lt_T) < $signed(_io_dat_br_lt_T_1); // @[dpath.scala:206:{35,42,57}] assign io_dat_br_lt_0 = _io_dat_br_lt_T_2; // @[dpath.scala:50:7, :206:42] assign _io_dat_br_ltu_T = exe_rs1_data < exe_rs2_data; // @[Mux.scala:126:16] assign io_dat_br_ltu_0 = _io_dat_br_ltu_T; // @[dpath.scala:50:7, :207:42] wire [2:0] mem_address_low = _alu_io_out[2:0]; // @[dpath.scala:190:20, :211:37] wire [2:0] misaligned_mask; // @[dpath.scala:212:30] wire [3:0] _misaligned_mask_T = {1'h0, io_ctl_dmem_typ_0} - 4'h1; // @[dpath.scala:50:7, :213:54] wire [2:0] _misaligned_mask_T_1 = _misaligned_mask_T[2:0]; // @[dpath.scala:213:54] wire [1:0] _misaligned_mask_T_2 = _misaligned_mask_T_1[1:0]; // @[dpath.scala:213:{54,60}] wire [5:0] _misaligned_mask_T_3 = 6'h7 << _misaligned_mask_T_2; // @[dpath.scala:213:{34,60}] wire [5:0] _misaligned_mask_T_4 = ~_misaligned_mask_T_3; // @[dpath.scala:213:{23,34}] assign misaligned_mask = _misaligned_mask_T_4[2:0]; // @[dpath.scala:212:30, :213:{20,23}] wire [2:0] _io_dat_data_misaligned_T = misaligned_mask & mem_address_low; // @[dpath.scala:211:37, :212:30, :214:47] wire _io_dat_data_misaligned_T_1 = \|_io_dat_data_misaligned_T; // @[dpath.scala:214:{47,66}] assign _io_dat_data_misaligned_T_2 = _io_dat_data_misaligned_T_1 & io_ctl_dmem_val_0; // @[dpath.scala:50:7, :214:{66,70}] assign io_dat_data_misaligned_0 = _io_dat_data_misaligned_T_2; // @[dpath.scala:50:7, :214:70] wire _io_dmem_req_valid_T = ~io_dat_data_misaligned_0; // @[dpath.scala:50:7, :217:48] wire _io_dmem_req_valid_T_1 = io_ctl_dmem_val_0 & _io_dmem_req_valid_T; // @[dpath.scala:50:7, :217:{45,48}] wire _io_dmem_req_valid_T_2 = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26, :217:75] assign _io_dmem_req_valid_T_3 = _io_dmem_req_valid_T_1 & _io_dmem_req_valid_T_2; // @[dpath.scala:217:{45,72,75}] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T_3; // @[dpath.scala:50:7, :217:72] wire _io_dmem_req_bits_fcn_T = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26, :221:50] wire _io_dmem_req_bits_fcn_T_1 = io_ctl_dmem_fcn_0 & _io_dmem_req_bits_fcn_T; // @[dpath.scala:50:7, :221:{48,50}] assign _io_dmem_req_bits_fcn_T_2 = _io_dmem_req_bits_fcn_T_1 & io_imem_resp_valid_0; // @[dpath.scala:50:7, :221:{48,67}] assign io_dmem_req_bits_fcn_0 = _io_dmem_req_bits_fcn_T_2; // @[dpath.scala:50:7, :221:67] wire _wb_dmiss_stall_T = ~io_dmem_req_ready_0; // @[dpath.scala:50:7, :227:23] wire _wb_dmiss_stall_T_1 = _wb_dmiss_stall_T & io_dmem_req_valid_0; // @[dpath.scala:50:7, :227:{23,42}] wire _wb_dmiss_stall_T_2 = ~io_dmem_resp_valid_0; // @[dpath.scala:50:7, :227:82] wire _wb_dmiss_stall_T_3 = wb_reg_mem & _wb_dmiss_stall_T_2; // @[dpath.scala:69:34, :227:{79,82}] assign _wb_dmiss_stall_T_4 = _wb_dmiss_stall_T_1 \| _wb_dmiss_stall_T_3; // @[dpath.scala:227:{42,64,79}] assign wb_dmiss_stall = _wb_dmiss_stall_T_4; // @[dpath.scala:72:31, :227:64] wire [31:0] _csr_io_decode_0_inst_T = {wb_reg_csr_addr, 20'h0}; // @[dpath.scala:66:30, :261:47] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[dpath.scala:61:34, :262:35] wire [2:0] _csr_io_rw_cmd_T = wb_dmiss_stall ? 3'h0 : wb_reg_ctrl_csr_cmd; // @[dpath.scala:63:30, :72:31, :264:27] wire _csr_io_retire_T = ~io_ctl_exception_0; // @[dpath.scala:50:7, :144:78, :267:40] wire _csr_io_retire_T_1 = wb_reg_valid & _csr_io_retire_T; // @[dpath.scala:62:34, :267:{37,40}] wire _csr_io_tval_T = io_ctl_exception_cause_0 == 32'h2; // @[dpath.scala:50:7, :276:43] wire _csr_io_tval_T_1 = io_ctl_exception_cause_0 == 32'h0; // @[dpath.scala:50:7, :277:43] wire _csr_io_tval_T_2 = io_ctl_exception_cause_0 == 32'h6; // @[dpath.scala:50:7, :278:43] wire _csr_io_tval_T_3 = io_ctl_exception_cause_0 == 32'h4; // @[dpath.scala:50:7, :279:43] wire [31:0] _csr_io_tval_T_4 = _csr_io_tval_T_3 ? tval_data_ma : 32'h0; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_5 = _csr_io_tval_T_2 ? tval_data_ma : _csr_io_tval_T_4; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_6 = _csr_io_tval_T_1 ? tval_inst_ma : _csr_io_tval_T_5; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_7 = _csr_io_tval_T ? wb_reg_inst : _csr_io_tval_T_6; // @[Mux.scala:126:16] reg reg_interrupt_flag; // @[dpath.scala:283:36] wire _interrupt_edge_T = ~reg_interrupt_flag; // @[dpath.scala:283:36, :284:45] assign interrupt_edge = _csr_io_interrupt & _interrupt_edge_T; // @[dpath.scala:259:20, :284:{42,45}] assign io_dat_csr_interrupt_0 = interrupt_edge; // @[dpath.scala:50:7, :284:42] wire [31:0] _csr_io_cause_T = io_ctl_exception_0 ? io_ctl_exception_cause_0 : _csr_io_interrupt_cause; // @[dpath.scala:50:7, :259:20, :289:23] wire _wb_wbdata_T = wb_reg_ctrl_wb_sel == 2'h0; // @[dpath.scala:63:30, :301:39] wire _wb_wbdata_T_1 = wb_reg_ctrl_wb_sel == 2'h1; // @[dpath.scala:63:30, :302:39] wire _wb_wbdata_T_2 = wb_reg_ctrl_wb_sel == 2'h2; // @[dpath.scala:63:30, :303:39] wire _wb_wbdata_T_3 = &wb_reg_ctrl_wb_sel; // @[dpath.scala:63:30, :304:39] wire [31:0] _wb_wbdata_T_4 = _wb_wbdata_T_3 ? _csr_io_rw_rdata : wb_reg_alu; // @[Mux.scala:126:16] wire [31:0] _wb_wbdata_T_5 = _wb_wbdata_T_2 ? io_imem_resp_bits_pc_0 : _wb_wbdata_T_4; // @[Mux.scala:126:16] wire [31:0] _wb_wbdata_T_6 = _wb_wbdata_T_1 ? io_dmem_resp_bits_data_0 : _wb_wbdata_T_5; // @[Mux.scala:126:16] assign _wb_wbdata_T_7 = _wb_wbdata_T ? wb_reg_alu : _wb_wbdata_T_6; // @[Mux.scala:126:16] assign wb_wbdata = _wb_wbdata_T_7; // @[Mux.scala:126:16] wire _debug_wb_inst_T = wb_hazard_stall \| io_ctl_exe_kill_0; // @[dpath.scala:50:7, :71:31, :310:53] wire _debug_wb_inst_T_1 = ~io_imem_resp_valid_0; // @[dpath.scala:50:7, :310:75] wire _debug_wb_inst_T_2 = _debug_wb_inst_T \| _debug_wb_inst_T_1; // @[dpath.scala:310:{53,72,75}] wire [31:0] _debug_wb_inst_T_3 = _debug_wb_inst_T_2 ? 32'h4033 : io_imem_resp_bits_inst_0; // @[dpath.scala:50:7, :310:{35,72}] reg [31:0] debug_wb_inst; // @[dpath.scala:310:31] reg [4:0] REG; // @[dpath.scala:319:14] reg [31:0] REG_1; // @[dpath.scala:320:14] reg [4:0] REG_2; // @[dpath.scala:321:14] reg [31:0] REG_3; // @[dpath.scala:322:14]
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_22 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `4` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `3` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<14> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_5_1, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_2, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_lo = cat(_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = shl(UInt<4>(0hf), 4) node _decoded_T_1 = xor(UInt<8>(0hff), _decoded_T) node _decoded_T_2 = shr(decoded_plaOutput, 4) node _decoded_T_3 = and(_decoded_T_2, _decoded_T_1) node _decoded_T_4 = bits(decoded_plaOutput, 3, 0) node _decoded_T_5 = shl(_decoded_T_4, 4) node _decoded_T_6 = not(_decoded_T_1) node _decoded_T_7 = and(_decoded_T_5, _decoded_T_6) node _decoded_T_8 = or(_decoded_T_3, _decoded_T_7) node _decoded_T_9 = bits(_decoded_T_1, 5, 0) node _decoded_T_10 = shl(_decoded_T_9, 2) node _decoded_T_11 = xor(_decoded_T_1, _decoded_T_10) node _decoded_T_12 = shr(_decoded_T_8, 2) node _decoded_T_13 = and(_decoded_T_12, _decoded_T_11) node _decoded_T_14 = bits(_decoded_T_8, 5, 0) node _decoded_T_15 = shl(_decoded_T_14, 2) node _decoded_T_16 = not(_decoded_T_11) node _decoded_T_17 = and(_decoded_T_15, _decoded_T_16) node _decoded_T_18 = or(_decoded_T_13, _decoded_T_17) node _decoded_T_19 = bits(_decoded_T_11, 6, 0) node _decoded_T_20 = shl(_decoded_T_19, 1) node _decoded_T_21 = xor(_decoded_T_11, _decoded_T_20) node _decoded_T_22 = shr(_decoded_T_18, 1) node _decoded_T_23 = and(_decoded_T_22, _decoded_T_21) node _decoded_T_24 = bits(_decoded_T_18, 6, 0) node _decoded_T_25 = shl(_decoded_T_24, 1) node _decoded_T_26 = not(_decoded_T_21) node _decoded_T_27 = and(_decoded_T_25, _decoded_T_26) node decoded = or(_decoded_T_23, _decoded_T_27) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_3_0_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`3`[0], _io_resp_0_vc_sel_3_0_T node _io_resp_0_vc_sel_3_1_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`3`[1], _io_resp_0_vc_sel_3_1_T connect io.resp.`0`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<14> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_3 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_2_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 7, 7) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_9, _decoded_invMatrixOutputs_T_8) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_13, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_15, _decoded_invMatrixOutputs_T_14) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_28 = shl(UInt<4>(0hf), 4) node _decoded_T_29 = xor(UInt<8>(0hff), _decoded_T_28) node _decoded_T_30 = shr(decoded_plaOutput_1, 4) node _decoded_T_31 = and(_decoded_T_30, _decoded_T_29) node _decoded_T_32 = bits(decoded_plaOutput_1, 3, 0) node _decoded_T_33 = shl(_decoded_T_32, 4) node _decoded_T_34 = not(_decoded_T_29) node _decoded_T_35 = and(_decoded_T_33, _decoded_T_34) node _decoded_T_36 = or(_decoded_T_31, _decoded_T_35) node _decoded_T_37 = bits(_decoded_T_29, 5, 0) node _decoded_T_38 = shl(_decoded_T_37, 2) node _decoded_T_39 = xor(_decoded_T_29, _decoded_T_38) node _decoded_T_40 = shr(_decoded_T_36, 2) node _decoded_T_41 = and(_decoded_T_40, _decoded_T_39) node _decoded_T_42 = bits(_decoded_T_36, 5, 0) node _decoded_T_43 = shl(_decoded_T_42, 2) node _decoded_T_44 = not(_decoded_T_39) node _decoded_T_45 = and(_decoded_T_43, _decoded_T_44) node _decoded_T_46 = or(_decoded_T_41, _decoded_T_45) node _decoded_T_47 = bits(_decoded_T_39, 6, 0) node _decoded_T_48 = shl(_decoded_T_47, 1) node _decoded_T_49 = xor(_decoded_T_39, _decoded_T_48) node _decoded_T_50 = shr(_decoded_T_46, 1) node _decoded_T_51 = and(_decoded_T_50, _decoded_T_49) node _decoded_T_52 = bits(_decoded_T_46, 6, 0) node _decoded_T_53 = shl(_decoded_T_52, 1) node _decoded_T_54 = not(_decoded_T_49) node _decoded_T_55 = and(_decoded_T_53, _decoded_T_54) node decoded_1 = or(_decoded_T_51, _decoded_T_55) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_3_0_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`3`[0], _io_resp_1_vc_sel_3_0_T node _io_resp_1_vc_sel_3_1_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`3`[1], _io_resp_1_vc_sel_3_1_T connect io.resp.`1`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<14> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_2, 12, 12) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_plaInput_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_2, 12, 12) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_plaInput_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_2, 12, 12) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_9) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_2_2_2) node _decoded_orMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_8 = orr(_decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_lo_2 = cat(_decoded_orMatrixOutputs_T_6, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_8, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_2, 7, 7) node decoded_invMatrixOutputs_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20) node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_56 = shl(UInt<4>(0hf), 4) node _decoded_T_57 = xor(UInt<8>(0hff), _decoded_T_56) node _decoded_T_58 = shr(decoded_plaOutput_2, 4) node _decoded_T_59 = and(_decoded_T_58, _decoded_T_57) node _decoded_T_60 = bits(decoded_plaOutput_2, 3, 0) node _decoded_T_61 = shl(_decoded_T_60, 4) node _decoded_T_62 = not(_decoded_T_57) node _decoded_T_63 = and(_decoded_T_61, _decoded_T_62) node _decoded_T_64 = or(_decoded_T_59, _decoded_T_63) node _decoded_T_65 = bits(_decoded_T_57, 5, 0) node _decoded_T_66 = shl(_decoded_T_65, 2) node _decoded_T_67 = xor(_decoded_T_57, _decoded_T_66) node _decoded_T_68 = shr(_decoded_T_64, 2) node _decoded_T_69 = and(_decoded_T_68, _decoded_T_67) node _decoded_T_70 = bits(_decoded_T_64, 5, 0) node _decoded_T_71 = shl(_decoded_T_70, 2) node _decoded_T_72 = not(_decoded_T_67) node _decoded_T_73 = and(_decoded_T_71, _decoded_T_72) node _decoded_T_74 = or(_decoded_T_69, _decoded_T_73) node _decoded_T_75 = bits(_decoded_T_67, 6, 0) node _decoded_T_76 = shl(_decoded_T_75, 1) node _decoded_T_77 = xor(_decoded_T_67, _decoded_T_76) node _decoded_T_78 = shr(_decoded_T_74, 1) node _decoded_T_79 = and(_decoded_T_78, _decoded_T_77) node _decoded_T_80 = bits(_decoded_T_74, 6, 0) node _decoded_T_81 = shl(_decoded_T_80, 1) node _decoded_T_82 = not(_decoded_T_77) node _decoded_T_83 = and(_decoded_T_81, _decoded_T_82) node decoded_2 = or(_decoded_T_79, _decoded_T_83) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_3_0_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`3`[0], _io_resp_2_vc_sel_3_0_T node _io_resp_2_vc_sel_3_1_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`3`[1], _io_resp_2_vc_sel_3_1_T connect io.resp.`2`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h1) node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id) node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node) node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id) node _addr_T_3 = cat(addr_hi_3, addr_lo_3) node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3) wire decoded_plaInput_3 : UInt<14> node decoded_invInputs_3 = not(decoded_plaInput_3) wire decoded_plaOutput_3 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_plaInput_3, 12, 12) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_0_2_3) node decoded_orMatrixOutputs_lo_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_3 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3) node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_3, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_3, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_3, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_3, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_3, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_3, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_3, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_3, 7, 7) node decoded_invMatrixOutputs_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_25, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_27, _decoded_invMatrixOutputs_T_26) node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3) node decoded_invMatrixOutputs_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_31, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3) node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3) connect decoded_plaOutput_3, decoded_invMatrixOutputs_3 connect decoded_plaInput_3, addr_3 node _decoded_T_84 = shl(UInt<4>(0hf), 4) node _decoded_T_85 = xor(UInt<8>(0hff), _decoded_T_84) node _decoded_T_86 = shr(decoded_plaOutput_3, 4) node _decoded_T_87 = and(_decoded_T_86, _decoded_T_85) node _decoded_T_88 = bits(decoded_plaOutput_3, 3, 0) node _decoded_T_89 = shl(_decoded_T_88, 4) node _decoded_T_90 = not(_decoded_T_85) node _decoded_T_91 = and(_decoded_T_89, _decoded_T_90) node _decoded_T_92 = or(_decoded_T_87, _decoded_T_91) node _decoded_T_93 = bits(_decoded_T_85, 5, 0) node _decoded_T_94 = shl(_decoded_T_93, 2) node _decoded_T_95 = xor(_decoded_T_85, _decoded_T_94) node _decoded_T_96 = shr(_decoded_T_92, 2) node _decoded_T_97 = and(_decoded_T_96, _decoded_T_95) node _decoded_T_98 = bits(_decoded_T_92, 5, 0) node _decoded_T_99 = shl(_decoded_T_98, 2) node _decoded_T_100 = not(_decoded_T_95) node _decoded_T_101 = and(_decoded_T_99, _decoded_T_100) node _decoded_T_102 = or(_decoded_T_97, _decoded_T_101) node _decoded_T_103 = bits(_decoded_T_95, 6, 0) node _decoded_T_104 = shl(_decoded_T_103, 1) node _decoded_T_105 = xor(_decoded_T_95, _decoded_T_104) node _decoded_T_106 = shr(_decoded_T_102, 1) node _decoded_T_107 = and(_decoded_T_106, _decoded_T_105) node _decoded_T_108 = bits(_decoded_T_102, 6, 0) node _decoded_T_109 = shl(_decoded_T_108, 1) node _decoded_T_110 = not(_decoded_T_105) node _decoded_T_111 = and(_decoded_T_109, _decoded_T_110) node decoded_3 = or(_decoded_T_107, _decoded_T_111) node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0) connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1) connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 2, 2) connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 3, 3) connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T node _io_resp_3_vc_sel_2_0_T = bits(decoded_3, 4, 4) connect io.resp.`3`.vc_sel.`2`[0], _io_resp_3_vc_sel_2_0_T node _io_resp_3_vc_sel_2_1_T = bits(decoded_3, 5, 5) connect io.resp.`3`.vc_sel.`2`[1], _io_resp_3_vc_sel_2_1_T node _io_resp_3_vc_sel_3_0_T = bits(decoded_3, 6, 6) connect io.resp.`3`.vc_sel.`3`[0], _io_resp_3_vc_sel_3_0_T node _io_resp_3_vc_sel_3_1_T = bits(decoded_3, 7, 7) connect io.resp.`3`.vc_sel.`3`[1], _io_resp_3_vc_sel_3_1_T connect io.resp.`3`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`4`.ready, UInt<1>(0h1) node addr_lo_4 = cat(io.req.`4`.bits.flow.egress_node, io.req.`4`.bits.flow.egress_node_id) node addr_hi_hi_4 = cat(io.req.`4`.bits.flow.vnet_id, io.req.`4`.bits.flow.ingress_node) node addr_hi_4 = cat(addr_hi_hi_4, io.req.`4`.bits.flow.ingress_node_id) node _addr_T_4 = cat(addr_hi_4, addr_lo_4) node addr_4 = cat(io.req.`4`.bits.src_virt_id, _addr_T_4) wire decoded_plaInput_4 : UInt<14> node decoded_invInputs_4 = not(decoded_plaInput_4) wire decoded_plaOutput_4 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_4 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_13) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_1_2_3 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_2_2_3 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_16) node _decoded_orMatrixOutputs_T_10 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_11 = orr(decoded_andMatrixOutputs_3_2_1) node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_0_2_4, decoded_andMatrixOutputs_1_2_3) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_5, decoded_andMatrixOutputs_2_2_3) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node _decoded_orMatrixOutputs_T_14 = orr(decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_hi_hi_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_4) node decoded_orMatrixOutputs_4 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_4, 0, 0) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_4, 1, 1) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_4, 2, 2) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_4, 3, 3) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_4, 4, 4) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_4, 5, 5) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_4, 6, 6) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_4, 7, 7) node decoded_invMatrixOutputs_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_33, _decoded_invMatrixOutputs_T_32) node decoded_invMatrixOutputs_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_4, decoded_invMatrixOutputs_lo_lo_4) node decoded_invMatrixOutputs_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_37, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_39, _decoded_invMatrixOutputs_T_38) node decoded_invMatrixOutputs_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_4, decoded_invMatrixOutputs_hi_lo_4) node decoded_invMatrixOutputs_4 = cat(decoded_invMatrixOutputs_hi_4, decoded_invMatrixOutputs_lo_4) connect decoded_plaOutput_4, decoded_invMatrixOutputs_4 connect decoded_plaInput_4, addr_4 node _decoded_T_112 = shl(UInt<4>(0hf), 4) node _decoded_T_113 = xor(UInt<8>(0hff), _decoded_T_112) node _decoded_T_114 = shr(decoded_plaOutput_4, 4) node _decoded_T_115 = and(_decoded_T_114, _decoded_T_113) node _decoded_T_116 = bits(decoded_plaOutput_4, 3, 0) node _decoded_T_117 = shl(_decoded_T_116, 4) node _decoded_T_118 = not(_decoded_T_113) node _decoded_T_119 = and(_decoded_T_117, _decoded_T_118) node _decoded_T_120 = or(_decoded_T_115, _decoded_T_119) node _decoded_T_121 = bits(_decoded_T_113, 5, 0) node _decoded_T_122 = shl(_decoded_T_121, 2) node _decoded_T_123 = xor(_decoded_T_113, _decoded_T_122) node _decoded_T_124 = shr(_decoded_T_120, 2) node _decoded_T_125 = and(_decoded_T_124, _decoded_T_123) node _decoded_T_126 = bits(_decoded_T_120, 5, 0) node _decoded_T_127 = shl(_decoded_T_126, 2) node _decoded_T_128 = not(_decoded_T_123) node _decoded_T_129 = and(_decoded_T_127, _decoded_T_128) node _decoded_T_130 = or(_decoded_T_125, _decoded_T_129) node _decoded_T_131 = bits(_decoded_T_123, 6, 0) node _decoded_T_132 = shl(_decoded_T_131, 1) node _decoded_T_133 = xor(_decoded_T_123, _decoded_T_132) node _decoded_T_134 = shr(_decoded_T_130, 1) node _decoded_T_135 = and(_decoded_T_134, _decoded_T_133) node _decoded_T_136 = bits(_decoded_T_130, 6, 0) node _decoded_T_137 = shl(_decoded_T_136, 1) node _decoded_T_138 = not(_decoded_T_133) node _decoded_T_139 = and(_decoded_T_137, _decoded_T_138) node decoded_4 = or(_decoded_T_135, _decoded_T_139) node _io_resp_4_vc_sel_0_0_T = bits(decoded_4, 0, 0) connect io.resp.`4`.vc_sel.`0`[0], _io_resp_4_vc_sel_0_0_T node _io_resp_4_vc_sel_0_1_T = bits(decoded_4, 1, 1) connect io.resp.`4`.vc_sel.`0`[1], _io_resp_4_vc_sel_0_1_T node _io_resp_4_vc_sel_1_0_T = bits(decoded_4, 2, 2) connect io.resp.`4`.vc_sel.`1`[0], _io_resp_4_vc_sel_1_0_T node _io_resp_4_vc_sel_1_1_T = bits(decoded_4, 3, 3) connect io.resp.`4`.vc_sel.`1`[1], _io_resp_4_vc_sel_1_1_T node _io_resp_4_vc_sel_2_0_T = bits(decoded_4, 4, 4) connect io.resp.`4`.vc_sel.`2`[0], _io_resp_4_vc_sel_2_0_T node _io_resp_4_vc_sel_2_1_T = bits(decoded_4, 5, 5) connect io.resp.`4`.vc_sel.`2`[1], _io_resp_4_vc_sel_2_1_T node _io_resp_4_vc_sel_3_0_T = bits(decoded_4, 6, 6) connect io.resp.`4`.vc_sel.`3`[0], _io_resp_4_vc_sel_3_0_T node _io_resp_4_vc_sel_3_1_T = bits(decoded_4, 7, 7) connect io.resp.`4`.vc_sel.`3`[1], _io_resp_4_vc_sel_3_1_T connect io.resp.`4`.vc_sel.`4`[0], UInt<1>(0h0) extmodule plusarg_reader_48 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_22( // @[RouteComputer.scala:29:7] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14] ); wire [12:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [12:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [12:0] decoded_invInputs_2 = ~{io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [3:0] _GEN = ~io_req_4_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_4_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_4_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_3_1 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_1 = &{_GEN_0[0], _GEN_0[1], io_req_4_bits_flow_egress_node[0], io_req_4_bits_flow_egress_node[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_1 = \|{&{_GEN_0[1], _GEN[1], _GEN[2], _GEN[3]}, &{_GEN_0[0], _GEN[1], io_req_4_bits_flow_egress_node[2]}, &{_GEN_0[0], _GEN[1], io_req_4_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_1 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], _GEN[2], _GEN[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_3_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_1 = &{~(io_req_3_bits_flow_egress_node_id[0]), io_req_3_bits_flow_vnet_id}; // @[pla.scala:78:21, :98:{53,70}] assign io_resp_2_vc_sel_3_0 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], decoded_invInputs_2[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_0 = \|{&{decoded_invInputs_2[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], decoded_invInputs_2[12]}, &{decoded_invInputs_2[0], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], decoded_invInputs_2[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_3_0 = &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_3_1 = &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_1 = &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_3_0 = \|{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_169 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_169( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_99 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_99 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_99( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_99 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_ScratchpadBank : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_53 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a28d64s4k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full \|\| !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full \|\| in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_109 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLFragmenter_ScratchpadBank( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [3:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [27:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} \| ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {\|dFirst_size_hi, \|(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] \| _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (\|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module Tile_111 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_367 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_111( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_367 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_88 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_88( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_58 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_6 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_120 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_121 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_58 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_61 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_61( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_32 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h1), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h1), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h1), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h1), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h1), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_64 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_65 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_5 : input clock : Clock input reset : Reset output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[10]} cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [28] wire _heads_WIRE : UInt<5>[10] connect _heads_WIRE[0], UInt<5>(0h0) connect _heads_WIRE[1], UInt<5>(0h4) connect _heads_WIRE[2], UInt<5>(0h0) connect _heads_WIRE[3], UInt<5>(0h8) connect _heads_WIRE[4], UInt<5>(0hc) connect _heads_WIRE[5], UInt<5>(0h10) connect _heads_WIRE[6], UInt<5>(0h0) connect _heads_WIRE[7], UInt<5>(0h0) connect _heads_WIRE[8], UInt<5>(0h14) connect _heads_WIRE[9], UInt<5>(0h18) regreset heads : UInt<5>[10], clock, reset, _heads_WIRE wire _tails_WIRE : UInt<5>[10] connect _tails_WIRE[0], UInt<5>(0h0) connect _tails_WIRE[1], UInt<5>(0h4) connect _tails_WIRE[2], UInt<5>(0h0) connect _tails_WIRE[3], UInt<5>(0h8) connect _tails_WIRE[4], UInt<5>(0hc) connect _tails_WIRE[5], UInt<5>(0h10) connect _tails_WIRE[6], UInt<5>(0h0) connect _tails_WIRE[7], UInt<5>(0h0) connect _tails_WIRE[8], UInt<5>(0h14) connect _tails_WIRE[9], UInt<5>(0h18) regreset tails : UInt<5>[10], clock, reset, _tails_WIRE node empty_0 = eq(heads[0], tails[0]) node empty_1 = eq(heads[1], tails[1]) node empty_2 = eq(heads[2], tails[2]) node empty_3 = eq(heads[3], tails[3]) node empty_4 = eq(heads[4], tails[4]) node empty_5 = eq(heads[5], tails[5]) node empty_6 = eq(heads[6], tails[6]) node empty_7 = eq(heads[7], tails[7]) node empty_8 = eq(heads[8], tails[8]) node empty_9 = eq(heads[9], tails[9]) inst qs_0 of Queue1_BaseFlit_50 connect qs_0.clock, clock connect qs_0.reset, reset inst qs_1 of Queue1_BaseFlit_51 connect qs_1.clock, clock connect qs_1.reset, reset inst qs_2 of Queue1_BaseFlit_52 connect qs_2.clock, clock connect qs_2.reset, reset inst qs_3 of Queue1_BaseFlit_53 connect qs_3.clock, clock connect qs_3.reset, reset inst qs_4 of Queue1_BaseFlit_54 connect qs_4.clock, clock connect qs_4.reset, reset inst qs_5 of Queue1_BaseFlit_55 connect qs_5.clock, clock connect qs_5.reset, reset inst qs_6 of Queue1_BaseFlit_56 connect qs_6.clock, clock connect qs_6.reset, reset inst qs_7 of Queue1_BaseFlit_57 connect qs_7.clock, clock connect qs_7.reset, reset inst qs_8 of Queue1_BaseFlit_58 connect qs_8.clock, clock connect qs_8.reset, reset inst qs_9 of Queue1_BaseFlit_59 connect qs_9.clock, clock connect qs_9.reset, reset connect qs_0.io.enq.valid, UInt<1>(0h0) connect qs_1.io.enq.valid, UInt<1>(0h0) connect qs_2.io.enq.valid, UInt<1>(0h0) connect qs_3.io.enq.valid, UInt<1>(0h0) connect qs_4.io.enq.valid, UInt<1>(0h0) connect qs_5.io.enq.valid, UInt<1>(0h0) connect qs_6.io.enq.valid, UInt<1>(0h0) connect qs_7.io.enq.valid, UInt<1>(0h0) connect qs_8.io.enq.valid, UInt<1>(0h0) connect qs_9.io.enq.valid, UInt<1>(0h0) invalidate qs_0.io.enq.bits.payload invalidate qs_0.io.enq.bits.tail invalidate qs_0.io.enq.bits.head invalidate qs_1.io.enq.bits.payload invalidate qs_1.io.enq.bits.tail invalidate qs_1.io.enq.bits.head invalidate qs_2.io.enq.bits.payload invalidate qs_2.io.enq.bits.tail invalidate qs_2.io.enq.bits.head invalidate qs_3.io.enq.bits.payload invalidate qs_3.io.enq.bits.tail invalidate qs_3.io.enq.bits.head invalidate qs_4.io.enq.bits.payload invalidate qs_4.io.enq.bits.tail invalidate qs_4.io.enq.bits.head invalidate qs_5.io.enq.bits.payload invalidate qs_5.io.enq.bits.tail invalidate qs_5.io.enq.bits.head invalidate qs_6.io.enq.bits.payload invalidate qs_6.io.enq.bits.tail invalidate qs_6.io.enq.bits.head invalidate qs_7.io.enq.bits.payload invalidate qs_7.io.enq.bits.tail invalidate qs_7.io.enq.bits.head invalidate qs_8.io.enq.bits.payload invalidate qs_8.io.enq.bits.tail invalidate qs_8.io.enq.bits.head invalidate qs_9.io.enq.bits.payload invalidate qs_9.io.enq.bits.tail invalidate qs_9.io.enq.bits.head node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id) wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} node _direct_to_q_T = bits(vc_sel, 0, 0) node _direct_to_q_T_1 = bits(vc_sel, 1, 1) node _direct_to_q_T_2 = bits(vc_sel, 2, 2) node _direct_to_q_T_3 = bits(vc_sel, 3, 3) node _direct_to_q_T_4 = bits(vc_sel, 4, 4) node _direct_to_q_T_5 = bits(vc_sel, 5, 5) node _direct_to_q_T_6 = bits(vc_sel, 6, 6) node _direct_to_q_T_7 = bits(vc_sel, 7, 7) node _direct_to_q_T_8 = bits(vc_sel, 8, 8) node _direct_to_q_T_9 = bits(vc_sel, 9, 9) node _direct_to_q_T_10 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_11 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_12 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_13 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_14 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_15 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_16 = mux(_direct_to_q_T_6, qs_6.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_17 = mux(_direct_to_q_T_7, qs_7.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_18 = mux(_direct_to_q_T_8, qs_8.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_19 = mux(_direct_to_q_T_9, qs_9.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_20 = or(_direct_to_q_T_10, _direct_to_q_T_11) node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_12) node _direct_to_q_T_22 = or(_direct_to_q_T_21, _direct_to_q_T_13) node _direct_to_q_T_23 = or(_direct_to_q_T_22, _direct_to_q_T_14) node _direct_to_q_T_24 = or(_direct_to_q_T_23, _direct_to_q_T_15) node _direct_to_q_T_25 = or(_direct_to_q_T_24, _direct_to_q_T_16) node _direct_to_q_T_26 = or(_direct_to_q_T_25, _direct_to_q_T_17) node _direct_to_q_T_27 = or(_direct_to_q_T_26, _direct_to_q_T_18) node _direct_to_q_T_28 = or(_direct_to_q_T_27, _direct_to_q_T_19) wire _direct_to_q_WIRE : UInt<1> connect _direct_to_q_WIRE, _direct_to_q_T_28 node _direct_to_q_T_29 = bits(vc_sel, 0, 0) node _direct_to_q_T_30 = bits(vc_sel, 1, 1) node _direct_to_q_T_31 = bits(vc_sel, 2, 2) node _direct_to_q_T_32 = bits(vc_sel, 3, 3) node _direct_to_q_T_33 = bits(vc_sel, 4, 4) node _direct_to_q_T_34 = bits(vc_sel, 5, 5) node _direct_to_q_T_35 = bits(vc_sel, 6, 6) node _direct_to_q_T_36 = bits(vc_sel, 7, 7) node _direct_to_q_T_37 = bits(vc_sel, 8, 8) node _direct_to_q_T_38 = bits(vc_sel, 9, 9) node _direct_to_q_T_39 = mux(_direct_to_q_T_29, empty_0, UInt<1>(0h0)) node _direct_to_q_T_40 = mux(_direct_to_q_T_30, empty_1, UInt<1>(0h0)) node _direct_to_q_T_41 = mux(_direct_to_q_T_31, empty_2, UInt<1>(0h0)) node _direct_to_q_T_42 = mux(_direct_to_q_T_32, empty_3, UInt<1>(0h0)) node _direct_to_q_T_43 = mux(_direct_to_q_T_33, empty_4, UInt<1>(0h0)) node _direct_to_q_T_44 = mux(_direct_to_q_T_34, empty_5, UInt<1>(0h0)) node _direct_to_q_T_45 = mux(_direct_to_q_T_35, empty_6, UInt<1>(0h0)) node _direct_to_q_T_46 = mux(_direct_to_q_T_36, empty_7, UInt<1>(0h0)) node _direct_to_q_T_47 = mux(_direct_to_q_T_37, empty_8, UInt<1>(0h0)) node _direct_to_q_T_48 = mux(_direct_to_q_T_38, empty_9, UInt<1>(0h0)) node _direct_to_q_T_49 = or(_direct_to_q_T_39, _direct_to_q_T_40) node _direct_to_q_T_50 = or(_direct_to_q_T_49, _direct_to_q_T_41) node _direct_to_q_T_51 = or(_direct_to_q_T_50, _direct_to_q_T_42) node _direct_to_q_T_52 = or(_direct_to_q_T_51, _direct_to_q_T_43) node _direct_to_q_T_53 = or(_direct_to_q_T_52, _direct_to_q_T_44) node _direct_to_q_T_54 = or(_direct_to_q_T_53, _direct_to_q_T_45) node _direct_to_q_T_55 = or(_direct_to_q_T_54, _direct_to_q_T_46) node _direct_to_q_T_56 = or(_direct_to_q_T_55, _direct_to_q_T_47) node _direct_to_q_T_57 = or(_direct_to_q_T_56, _direct_to_q_T_48) wire _direct_to_q_WIRE_1 : UInt<1> connect _direct_to_q_WIRE_1, _direct_to_q_T_57 node _direct_to_q_T_58 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1) node direct_to_q = and(_direct_to_q_T_58, UInt<1>(0h1)) connect flit.head, io.enq[0].bits.head connect flit.tail, io.enq[0].bits.tail connect flit.payload, io.enq[0].bits.payload node _T = eq(direct_to_q, UInt<1>(0h0)) node _T_1 = and(io.enq[0].valid, _T) when _T_1 : write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock connect MPORT, flit node _tails_T = bits(vc_sel, 0, 0) node _tails_T_1 = bits(vc_sel, 1, 1) node _tails_T_2 = bits(vc_sel, 2, 2) node _tails_T_3 = bits(vc_sel, 3, 3) node _tails_T_4 = bits(vc_sel, 4, 4) node _tails_T_5 = bits(vc_sel, 5, 5) node _tails_T_6 = bits(vc_sel, 6, 6) node _tails_T_7 = bits(vc_sel, 7, 7) node _tails_T_8 = bits(vc_sel, 8, 8) node _tails_T_9 = bits(vc_sel, 9, 9) node _tails_T_10 = mux(_tails_T, UInt<2>(0h3), UInt<1>(0h0)) node _tails_T_11 = mux(_tails_T_1, UInt<3>(0h7), UInt<1>(0h0)) node _tails_T_12 = mux(_tails_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_13 = mux(_tails_T_3, UInt<4>(0hb), UInt<1>(0h0)) node _tails_T_14 = mux(_tails_T_4, UInt<4>(0hf), UInt<1>(0h0)) node _tails_T_15 = mux(_tails_T_5, UInt<5>(0h13), UInt<1>(0h0)) node _tails_T_16 = mux(_tails_T_6, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_17 = mux(_tails_T_7, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_18 = mux(_tails_T_8, UInt<5>(0h17), UInt<1>(0h0)) node _tails_T_19 = mux(_tails_T_9, UInt<5>(0h1b), UInt<1>(0h0)) node _tails_T_20 = or(_tails_T_10, _tails_T_11) node _tails_T_21 = or(_tails_T_20, _tails_T_12) node _tails_T_22 = or(_tails_T_21, _tails_T_13) node _tails_T_23 = or(_tails_T_22, _tails_T_14) node _tails_T_24 = or(_tails_T_23, _tails_T_15) node _tails_T_25 = or(_tails_T_24, _tails_T_16) node _tails_T_26 = or(_tails_T_25, _tails_T_17) node _tails_T_27 = or(_tails_T_26, _tails_T_18) node _tails_T_28 = or(_tails_T_27, _tails_T_19) wire _tails_WIRE_1 : UInt<5> connect _tails_WIRE_1, _tails_T_28 node _tails_T_29 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1) node _tails_T_30 = bits(vc_sel, 0, 0) node _tails_T_31 = bits(vc_sel, 1, 1) node _tails_T_32 = bits(vc_sel, 2, 2) node _tails_T_33 = bits(vc_sel, 3, 3) node _tails_T_34 = bits(vc_sel, 4, 4) node _tails_T_35 = bits(vc_sel, 5, 5) node _tails_T_36 = bits(vc_sel, 6, 6) node _tails_T_37 = bits(vc_sel, 7, 7) node _tails_T_38 = bits(vc_sel, 8, 8) node _tails_T_39 = bits(vc_sel, 9, 9) node _tails_T_40 = mux(_tails_T_30, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_41 = mux(_tails_T_31, UInt<3>(0h4), UInt<1>(0h0)) node _tails_T_42 = mux(_tails_T_32, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_43 = mux(_tails_T_33, UInt<4>(0h8), UInt<1>(0h0)) node _tails_T_44 = mux(_tails_T_34, UInt<4>(0hc), UInt<1>(0h0)) node _tails_T_45 = mux(_tails_T_35, UInt<5>(0h10), UInt<1>(0h0)) node _tails_T_46 = mux(_tails_T_36, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_47 = mux(_tails_T_37, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_48 = mux(_tails_T_38, UInt<5>(0h14), UInt<1>(0h0)) node _tails_T_49 = mux(_tails_T_39, UInt<5>(0h18), UInt<1>(0h0)) node _tails_T_50 = or(_tails_T_40, _tails_T_41) node _tails_T_51 = or(_tails_T_50, _tails_T_42) node _tails_T_52 = or(_tails_T_51, _tails_T_43) node _tails_T_53 = or(_tails_T_52, _tails_T_44) node _tails_T_54 = or(_tails_T_53, _tails_T_45) node _tails_T_55 = or(_tails_T_54, _tails_T_46) node _tails_T_56 = or(_tails_T_55, _tails_T_47) node _tails_T_57 = or(_tails_T_56, _tails_T_48) node _tails_T_58 = or(_tails_T_57, _tails_T_49) wire _tails_WIRE_2 : UInt<5> connect _tails_WIRE_2, _tails_T_58 node _tails_T_59 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1)) node _tails_T_60 = tail(_tails_T_59, 1) node _tails_T_61 = mux(_tails_T_29, _tails_WIRE_2, _tails_T_60) connect tails[io.enq[0].bits.virt_channel_id], _tails_T_61 else : node _T_2 = and(io.enq[0].valid, direct_to_q) when _T_2 : node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0)) when _T_3 : connect qs_0.io.enq.valid, UInt<1>(0h1) connect qs_0.io.enq.bits.payload, flit.payload connect qs_0.io.enq.bits.tail, flit.tail connect qs_0.io.enq.bits.head, flit.head node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1)) when _T_4 : connect qs_1.io.enq.valid, UInt<1>(0h1) connect qs_1.io.enq.bits.payload, flit.payload connect qs_1.io.enq.bits.tail, flit.tail connect qs_1.io.enq.bits.head, flit.head node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2)) when _T_5 : connect qs_2.io.enq.valid, UInt<1>(0h1) connect qs_2.io.enq.bits.payload, flit.payload connect qs_2.io.enq.bits.tail, flit.tail connect qs_2.io.enq.bits.head, flit.head node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3)) when _T_6 : connect qs_3.io.enq.valid, UInt<1>(0h1) connect qs_3.io.enq.bits.payload, flit.payload connect qs_3.io.enq.bits.tail, flit.tail connect qs_3.io.enq.bits.head, flit.head node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4)) when _T_7 : connect qs_4.io.enq.valid, UInt<1>(0h1) connect qs_4.io.enq.bits.payload, flit.payload connect qs_4.io.enq.bits.tail, flit.tail connect qs_4.io.enq.bits.head, flit.head node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5)) when _T_8 : connect qs_5.io.enq.valid, UInt<1>(0h1) connect qs_5.io.enq.bits.payload, flit.payload connect qs_5.io.enq.bits.tail, flit.tail connect qs_5.io.enq.bits.head, flit.head node _T_9 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h6)) when _T_9 : connect qs_6.io.enq.valid, UInt<1>(0h1) connect qs_6.io.enq.bits.payload, flit.payload connect qs_6.io.enq.bits.tail, flit.tail connect qs_6.io.enq.bits.head, flit.head node _T_10 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h7)) when _T_10 : connect qs_7.io.enq.valid, UInt<1>(0h1) connect qs_7.io.enq.bits.payload, flit.payload connect qs_7.io.enq.bits.tail, flit.tail connect qs_7.io.enq.bits.head, flit.head node _T_11 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h8)) when _T_11 : connect qs_8.io.enq.valid, UInt<1>(0h1) connect qs_8.io.enq.bits.payload, flit.payload connect qs_8.io.enq.bits.tail, flit.tail connect qs_8.io.enq.bits.head, flit.head node _T_12 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h9)) when _T_12 : connect qs_9.io.enq.valid, UInt<1>(0h1) connect qs_9.io.enq.bits.payload, flit.payload connect qs_9.io.enq.bits.tail, flit.tail connect qs_9.io.enq.bits.head, flit.head node _can_to_q_T = eq(empty_0, UInt<1>(0h0)) node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready) node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0)) node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready) node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0)) node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready) node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0)) node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready) node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0)) node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready) node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0)) node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready) node _can_to_q_T_6 = eq(empty_6, UInt<1>(0h0)) node can_to_q_6 = and(_can_to_q_T_6, qs_6.io.enq.ready) node _can_to_q_T_7 = eq(empty_7, UInt<1>(0h0)) node can_to_q_7 = and(_can_to_q_T_7, qs_7.io.enq.ready) node _can_to_q_T_8 = eq(empty_8, UInt<1>(0h0)) node can_to_q_8 = and(_can_to_q_T_8, qs_8.io.enq.ready) node _can_to_q_T_9 = eq(empty_9, UInt<1>(0h0)) node can_to_q_9 = and(_can_to_q_T_9, qs_9.io.enq.ready) node _to_q_oh_enc_T = mux(can_to_q_9, UInt<10>(0h200), UInt<10>(0h0)) node _to_q_oh_enc_T_1 = mux(can_to_q_8, UInt<10>(0h100), _to_q_oh_enc_T) node _to_q_oh_enc_T_2 = mux(can_to_q_7, UInt<10>(0h80), _to_q_oh_enc_T_1) node _to_q_oh_enc_T_3 = mux(can_to_q_6, UInt<10>(0h40), _to_q_oh_enc_T_2) node _to_q_oh_enc_T_4 = mux(can_to_q_5, UInt<10>(0h20), _to_q_oh_enc_T_3) node _to_q_oh_enc_T_5 = mux(can_to_q_4, UInt<10>(0h10), _to_q_oh_enc_T_4) node _to_q_oh_enc_T_6 = mux(can_to_q_3, UInt<10>(0h8), _to_q_oh_enc_T_5) node _to_q_oh_enc_T_7 = mux(can_to_q_2, UInt<10>(0h4), _to_q_oh_enc_T_6) node _to_q_oh_enc_T_8 = mux(can_to_q_1, UInt<10>(0h2), _to_q_oh_enc_T_7) node to_q_oh_enc = mux(can_to_q_0, UInt<10>(0h1), _to_q_oh_enc_T_8) node to_q_oh_0 = bits(to_q_oh_enc, 0, 0) node to_q_oh_1 = bits(to_q_oh_enc, 1, 1) node to_q_oh_2 = bits(to_q_oh_enc, 2, 2) node to_q_oh_3 = bits(to_q_oh_enc, 3, 3) node to_q_oh_4 = bits(to_q_oh_enc, 4, 4) node to_q_oh_5 = bits(to_q_oh_enc, 5, 5) node to_q_oh_6 = bits(to_q_oh_enc, 6, 6) node to_q_oh_7 = bits(to_q_oh_enc, 7, 7) node to_q_oh_8 = bits(to_q_oh_enc, 8, 8) node to_q_oh_9 = bits(to_q_oh_enc, 9, 9) node to_q_lo_lo = cat(to_q_oh_1, to_q_oh_0) node to_q_lo_hi_hi = cat(to_q_oh_4, to_q_oh_3) node to_q_lo_hi = cat(to_q_lo_hi_hi, to_q_oh_2) node to_q_lo = cat(to_q_lo_hi, to_q_lo_lo) node to_q_hi_lo = cat(to_q_oh_6, to_q_oh_5) node to_q_hi_hi_hi = cat(to_q_oh_9, to_q_oh_8) node to_q_hi_hi = cat(to_q_hi_hi_hi, to_q_oh_7) node to_q_hi = cat(to_q_hi_hi, to_q_hi_lo) node _to_q_T = cat(to_q_hi, to_q_lo) node to_q_hi_1 = bits(_to_q_T, 9, 8) node to_q_lo_1 = bits(_to_q_T, 7, 0) node _to_q_T_1 = orr(to_q_hi_1) node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1) node to_q_hi_2 = bits(_to_q_T_2, 7, 4) node to_q_lo_2 = bits(_to_q_T_2, 3, 0) node _to_q_T_3 = orr(to_q_hi_2) node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2) node to_q_hi_3 = bits(_to_q_T_4, 3, 2) node to_q_lo_3 = bits(_to_q_T_4, 1, 0) node _to_q_T_5 = orr(to_q_hi_3) node _to_q_T_6 = or(to_q_hi_3, to_q_lo_3) node _to_q_T_7 = bits(_to_q_T_6, 1, 1) node _to_q_T_8 = cat(_to_q_T_5, _to_q_T_7) node _to_q_T_9 = cat(_to_q_T_3, _to_q_T_8) node to_q = cat(_to_q_T_1, _to_q_T_9) node _T_13 = or(can_to_q_0, can_to_q_1) node _T_14 = or(_T_13, can_to_q_2) node _T_15 = or(_T_14, can_to_q_3) node _T_16 = or(_T_15, can_to_q_4) node _T_17 = or(_T_16, can_to_q_5) node _T_18 = or(_T_17, can_to_q_6) node _T_19 = or(_T_18, can_to_q_7) node _T_20 = or(_T_19, can_to_q_8) node _T_21 = or(_T_20, can_to_q_9) when _T_21 : node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0)) node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0)) node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0)) node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0)) node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0)) node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0)) node _head_T_6 = mux(to_q_oh_6, heads[6], UInt<1>(0h0)) node _head_T_7 = mux(to_q_oh_7, heads[7], UInt<1>(0h0)) node _head_T_8 = mux(to_q_oh_8, heads[8], UInt<1>(0h0)) node _head_T_9 = mux(to_q_oh_9, heads[9], UInt<1>(0h0)) node _head_T_10 = or(_head_T, _head_T_1) node _head_T_11 = or(_head_T_10, _head_T_2) node _head_T_12 = or(_head_T_11, _head_T_3) node _head_T_13 = or(_head_T_12, _head_T_4) node _head_T_14 = or(_head_T_13, _head_T_5) node _head_T_15 = or(_head_T_14, _head_T_6) node _head_T_16 = or(_head_T_15, _head_T_7) node _head_T_17 = or(_head_T_16, _head_T_8) node _head_T_18 = or(_head_T_17, _head_T_9) wire head : UInt<5> connect head, _head_T_18 node _heads_T = mux(to_q_oh_0, UInt<2>(0h3), UInt<1>(0h0)) node _heads_T_1 = mux(to_q_oh_1, UInt<3>(0h7), UInt<1>(0h0)) node _heads_T_2 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_3 = mux(to_q_oh_3, UInt<4>(0hb), UInt<1>(0h0)) node _heads_T_4 = mux(to_q_oh_4, UInt<4>(0hf), UInt<1>(0h0)) node _heads_T_5 = mux(to_q_oh_5, UInt<5>(0h13), UInt<1>(0h0)) node _heads_T_6 = mux(to_q_oh_6, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_7 = mux(to_q_oh_7, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_8 = mux(to_q_oh_8, UInt<5>(0h17), UInt<1>(0h0)) node _heads_T_9 = mux(to_q_oh_9, UInt<5>(0h1b), UInt<1>(0h0)) node _heads_T_10 = or(_heads_T, _heads_T_1) node _heads_T_11 = or(_heads_T_10, _heads_T_2) node _heads_T_12 = or(_heads_T_11, _heads_T_3) node _heads_T_13 = or(_heads_T_12, _heads_T_4) node _heads_T_14 = or(_heads_T_13, _heads_T_5) node _heads_T_15 = or(_heads_T_14, _heads_T_6) node _heads_T_16 = or(_heads_T_15, _heads_T_7) node _heads_T_17 = or(_heads_T_16, _heads_T_8) node _heads_T_18 = or(_heads_T_17, _heads_T_9) wire _heads_WIRE_1 : UInt<5> connect _heads_WIRE_1, _heads_T_18 node _heads_T_19 = eq(head, _heads_WIRE_1) node _heads_T_20 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_21 = mux(to_q_oh_1, UInt<3>(0h4), UInt<1>(0h0)) node _heads_T_22 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_23 = mux(to_q_oh_3, UInt<4>(0h8), UInt<1>(0h0)) node _heads_T_24 = mux(to_q_oh_4, UInt<4>(0hc), UInt<1>(0h0)) node _heads_T_25 = mux(to_q_oh_5, UInt<5>(0h10), UInt<1>(0h0)) node _heads_T_26 = mux(to_q_oh_6, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_27 = mux(to_q_oh_7, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_28 = mux(to_q_oh_8, UInt<5>(0h14), UInt<1>(0h0)) node _heads_T_29 = mux(to_q_oh_9, UInt<5>(0h18), UInt<1>(0h0)) node _heads_T_30 = or(_heads_T_20, _heads_T_21) node _heads_T_31 = or(_heads_T_30, _heads_T_22) node _heads_T_32 = or(_heads_T_31, _heads_T_23) node _heads_T_33 = or(_heads_T_32, _heads_T_24) node _heads_T_34 = or(_heads_T_33, _heads_T_25) node _heads_T_35 = or(_heads_T_34, _heads_T_26) node _heads_T_36 = or(_heads_T_35, _heads_T_27) node _heads_T_37 = or(_heads_T_36, _heads_T_28) node _heads_T_38 = or(_heads_T_37, _heads_T_29) wire _heads_WIRE_2 : UInt<5> connect _heads_WIRE_2, _heads_T_38 node _heads_T_39 = add(head, UInt<1>(0h1)) node _heads_T_40 = tail(_heads_T_39, 1) node _heads_T_41 = mux(_heads_T_19, _heads_WIRE_2, _heads_T_40) connect heads[to_q], _heads_T_41 when to_q_oh_0 : connect qs_0.io.enq.valid, UInt<1>(0h1) read mport qs_0_io_enq_bits_MPORT = mem[head], clock connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head when to_q_oh_1 : connect qs_1.io.enq.valid, UInt<1>(0h1) read mport qs_1_io_enq_bits_MPORT = mem[head], clock connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head when to_q_oh_2 : connect qs_2.io.enq.valid, UInt<1>(0h1) read mport qs_2_io_enq_bits_MPORT = mem[head], clock connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head when to_q_oh_3 : connect qs_3.io.enq.valid, UInt<1>(0h1) read mport qs_3_io_enq_bits_MPORT = mem[head], clock connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head when to_q_oh_4 : connect qs_4.io.enq.valid, UInt<1>(0h1) read mport qs_4_io_enq_bits_MPORT = mem[head], clock connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head when to_q_oh_5 : connect qs_5.io.enq.valid, UInt<1>(0h1) read mport qs_5_io_enq_bits_MPORT = mem[head], clock connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head when to_q_oh_6 : connect qs_6.io.enq.valid, UInt<1>(0h1) read mport qs_6_io_enq_bits_MPORT = mem[head], clock connect qs_6.io.enq.bits.payload, qs_6_io_enq_bits_MPORT.payload connect qs_6.io.enq.bits.tail, qs_6_io_enq_bits_MPORT.tail connect qs_6.io.enq.bits.head, qs_6_io_enq_bits_MPORT.head when to_q_oh_7 : connect qs_7.io.enq.valid, UInt<1>(0h1) read mport qs_7_io_enq_bits_MPORT = mem[head], clock connect qs_7.io.enq.bits.payload, qs_7_io_enq_bits_MPORT.payload connect qs_7.io.enq.bits.tail, qs_7_io_enq_bits_MPORT.tail connect qs_7.io.enq.bits.head, qs_7_io_enq_bits_MPORT.head when to_q_oh_8 : connect qs_8.io.enq.valid, UInt<1>(0h1) read mport qs_8_io_enq_bits_MPORT = mem[head], clock connect qs_8.io.enq.bits.payload, qs_8_io_enq_bits_MPORT.payload connect qs_8.io.enq.bits.tail, qs_8_io_enq_bits_MPORT.tail connect qs_8.io.enq.bits.head, qs_8_io_enq_bits_MPORT.head when to_q_oh_9 : connect qs_9.io.enq.valid, UInt<1>(0h1) read mport qs_9_io_enq_bits_MPORT = mem[head], clock connect qs_9.io.enq.bits.payload, qs_9_io_enq_bits_MPORT.payload connect qs_9.io.enq.bits.tail, qs_9_io_enq_bits_MPORT.tail connect qs_9.io.enq.bits.head, qs_9_io_enq_bits_MPORT.head connect io.deq[0].bits, qs_0.io.deq.bits connect io.deq[0].valid, qs_0.io.deq.valid connect qs_0.io.deq.ready, io.deq[0].ready connect io.deq[1].bits, qs_1.io.deq.bits connect io.deq[1].valid, qs_1.io.deq.valid connect qs_1.io.deq.ready, io.deq[1].ready connect io.deq[2].bits, qs_2.io.deq.bits connect io.deq[2].valid, qs_2.io.deq.valid connect qs_2.io.deq.ready, io.deq[2].ready connect io.deq[3].bits, qs_3.io.deq.bits connect io.deq[3].valid, qs_3.io.deq.valid connect qs_3.io.deq.ready, io.deq[3].ready connect io.deq[4].bits, qs_4.io.deq.bits connect io.deq[4].valid, qs_4.io.deq.valid connect qs_4.io.deq.ready, io.deq[4].ready connect io.deq[5].bits, qs_5.io.deq.bits connect io.deq[5].valid, qs_5.io.deq.valid connect qs_5.io.deq.ready, io.deq[5].ready connect io.deq[6].bits, qs_6.io.deq.bits connect io.deq[6].valid, qs_6.io.deq.valid connect qs_6.io.deq.ready, io.deq[6].ready connect io.deq[7].bits, qs_7.io.deq.bits connect io.deq[7].valid, qs_7.io.deq.valid connect qs_7.io.deq.ready, io.deq[7].ready connect io.deq[8].bits, qs_8.io.deq.bits connect io.deq[8].valid, qs_8.io.deq.valid connect qs_8.io.deq.ready, io.deq[8].ready connect io.deq[9].bits, qs_9.io.deq.bits connect io.deq[9].valid, qs_9.io.deq.valid connect qs_9.io.deq.ready, io.deq[9].ready	module InputBuffer_5( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [3:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] input io_deq_0_ready, // @[InputUnit.scala:51:14] output io_deq_0_valid, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] input io_deq_1_ready, // @[InputUnit.scala:51:14] output io_deq_1_valid, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] input io_deq_4_ready, // @[InputUnit.scala:51:14] output io_deq_4_valid, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] input io_deq_5_ready, // @[InputUnit.scala:51:14] output io_deq_5_valid, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] input io_deq_8_ready, // @[InputUnit.scala:51:14] output io_deq_8_valid, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] input io_deq_9_ready, // @[InputUnit.scala:51:14] output io_deq_9_valid, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] reg [4:0] heads_0; // @[InputUnit.scala:86:24] reg [4:0] heads_1; // @[InputUnit.scala:86:24] reg [4:0] heads_2; // @[InputUnit.scala:86:24] reg [4:0] heads_3; // @[InputUnit.scala:86:24] reg [4:0] heads_4; // @[InputUnit.scala:86:24] reg [4:0] heads_5; // @[InputUnit.scala:86:24] reg [4:0] heads_6; // @[InputUnit.scala:86:24] reg [4:0] heads_7; // @[InputUnit.scala:86:24] reg [4:0] heads_8; // @[InputUnit.scala:86:24] reg [4:0] heads_9; // @[InputUnit.scala:86:24] reg [4:0] tails_0; // @[InputUnit.scala:87:24] reg [4:0] tails_1; // @[InputUnit.scala:87:24] reg [4:0] tails_2; // @[InputUnit.scala:87:24] reg [4:0] tails_3; // @[InputUnit.scala:87:24] reg [4:0] tails_4; // @[InputUnit.scala:87:24] reg [4:0] tails_5; // @[InputUnit.scala:87:24] reg [4:0] tails_6; // @[InputUnit.scala:87:24] reg [4:0] tails_7; // @[InputUnit.scala:87:24] reg [4:0] tails_8; // @[InputUnit.scala:87:24] reg [4:0] tails_9; // @[InputUnit.scala:87:24] wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 4'h0; // @[Mux.scala:32:36] wire _tails_T_31 = io_enq_0_bits_virt_channel_id == 4'h1; // @[Mux.scala:32:36] wire _tails_T_32 = io_enq_0_bits_virt_channel_id == 4'h2; // @[Mux.scala:32:36] wire _tails_T_33 = io_enq_0_bits_virt_channel_id == 4'h3; // @[Mux.scala:32:36] wire _tails_T_34 = io_enq_0_bits_virt_channel_id == 4'h4; // @[Mux.scala:32:36] wire _tails_T_35 = io_enq_0_bits_virt_channel_id == 4'h5; // @[Mux.scala:32:36] wire _tails_T_36 = io_enq_0_bits_virt_channel_id == 4'h6; // @[Mux.scala:32:36] wire _tails_T_37 = io_enq_0_bits_virt_channel_id == 4'h7; // @[Mux.scala:32:36] wire _tails_T_38 = io_enq_0_bits_virt_channel_id == 4'h8; // @[Mux.scala:32:36] wire _tails_T_39 = io_enq_0_bits_virt_channel_id == 4'h9; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_30 & _qs_0_io_enq_ready \| _tails_T_31 & _qs_1_io_enq_ready \| _tails_T_32 & _qs_2_io_enq_ready \| _tails_T_33 & _qs_3_io_enq_ready \| _tails_T_34 & _qs_4_io_enq_ready \| _tails_T_35 & _qs_5_io_enq_ready \| _tails_T_36 & _qs_6_io_enq_ready \| _tails_T_37 & _qs_7_io_enq_ready \| _tails_T_38 & _qs_8_io_enq_ready \| _tails_T_39 & _qs_9_io_enq_ready) & (_tails_T_30 & heads_0 == tails_0 \| _tails_T_31 & heads_1 == tails_1 \| _tails_T_32 & heads_2 == tails_2 \| _tails_T_33 & heads_3 == tails_3 \| _tails_T_34 & heads_4 == tails_4 \| _tails_T_35 & heads_5 == tails_5 \| _tails_T_36 & heads_6 == tails_6 \| _tails_T_37 & heads_7 == tails_7 \| _tails_T_38 & heads_8 == tails_8 \| _tails_T_39 & heads_9 == tails_9); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [15:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 4'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 4'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 4'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 4'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 4'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 4'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 4'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 4'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 4'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 4'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [9:0] to_q_oh_enc = can_to_q_0 ? 10'h1 : can_to_q_1 ? 10'h2 : can_to_q_2 ? 10'h4 : can_to_q_3 ? 10'h8 : can_to_q_4 ? 10'h10 : can_to_q_5 ? 10'h20 : can_to_q_6 ? 10'h40 : can_to_q_7 ? 10'h80 : can_to_q_8 ? 10'h100 : {can_to_q_9, 9'h0}; // @[Mux.scala:50:70] wire _GEN_11 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7 \| can_to_q_8 \| can_to_q_9; // @[package.scala:81:59] wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) \| (to_q_oh_enc[1] ? heads_1 : 5'h0) \| (to_q_oh_enc[2] ? heads_2 : 5'h0) \| (to_q_oh_enc[3] ? heads_3 : 5'h0) \| (to_q_oh_enc[4] ? heads_4 : 5'h0) \| (to_q_oh_enc[5] ? heads_5 : 5'h0) \| (to_q_oh_enc[6] ? heads_6 : 5'h0) \| (to_q_oh_enc[7] ? heads_7 : 5'h0) \| (to_q_oh_enc[8] ? heads_8 : 5'h0) \| (to_q_oh_enc[9] ? heads_9 : 5'h0); // @[OneHot.scala:83:30] wire _GEN_12 = _GEN_11 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_13 = _GEN_11 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_14 = _GEN_11 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_15 = _GEN_11 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_16 = _GEN_11 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_17 = _GEN_11 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_18 = _GEN_11 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_19 = _GEN_11 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_20 = _GEN_11 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_21 = _GEN_11 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire [4:0] _tails_T_61 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_30}}} \| {3{_tails_T_31}}} \| (_tails_T_33 ? 4'hB : 4'h0) \| {4{_tails_T_34}}} \| (_tails_T_35 ? 5'h13 : 5'h0) \| (_tails_T_38 ? 5'h17 : 5'h0) \| (_tails_T_39 ? 5'h1B : 5'h0)) ? {_tails_T_35, {_tails_T_33, _tails_T_31, 2'h0} \| (_tails_T_34 ? 4'hC : 4'h0)} \| (_tails_T_38 ? 5'h14 : 5'h0) \| (_tails_T_39 ? 5'h18 : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36] wire [6:0] _to_q_T_2 = {6'h0, to_q_oh_enc[9]} \| to_q_oh_enc[7:1]; // @[OneHot.scala:31:18, :32:28] wire [2:0] _to_q_T_4 = _to_q_T_2[6:4] \| _to_q_T_2[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_6 = _to_q_T_4[2] \| _to_q_T_4[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] to_q = {\|(to_q_oh_enc[9:8]), \|(_to_q_T_2[6:3]), \|(_to_q_T_4[2:1]), _to_q_T_6}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [4:0] _heads_T_41 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[0]}}} \| {3{to_q_oh_enc[1]}}} \| (to_q_oh_enc[3] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[4]}}} \| (to_q_oh_enc[5] ? 5'h13 : 5'h0) \| (to_q_oh_enc[8] ? 5'h17 : 5'h0) \| (to_q_oh_enc[9] ? 5'h1B : 5'h0)) ? {to_q_oh_enc[5], {to_q_oh_enc[3], to_q_oh_enc[1], 2'h0} \| (to_q_oh_enc[4] ? 4'hC : 4'h0)} \| (to_q_oh_enc[8] ? 5'h14 : 5'h0) \| (to_q_oh_enc[9] ? 5'h18 : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 5'h0; // @[InputUnit.scala:86:24] heads_1 <= 5'h4; // @[InputUnit.scala:86:24] heads_2 <= 5'h0; // @[InputUnit.scala:86:24] heads_3 <= 5'h8; // @[InputUnit.scala:86:24] heads_4 <= 5'hC; // @[InputUnit.scala:86:24] heads_5 <= 5'h10; // @[InputUnit.scala:86:24] heads_6 <= 5'h0; // @[InputUnit.scala:86:24] heads_7 <= 5'h0; // @[InputUnit.scala:86:24] heads_8 <= 5'h14; // @[InputUnit.scala:86:24] heads_9 <= 5'h18; // @[InputUnit.scala:86:24] tails_0 <= 5'h0; // @[InputUnit.scala:87:24] tails_1 <= 5'h4; // @[InputUnit.scala:87:24] tails_2 <= 5'h0; // @[InputUnit.scala:87:24] tails_3 <= 5'h8; // @[InputUnit.scala:87:24] tails_4 <= 5'hC; // @[InputUnit.scala:87:24] tails_5 <= 5'h10; // @[InputUnit.scala:87:24] tails_6 <= 5'h0; // @[InputUnit.scala:87:24] tails_7 <= 5'h0; // @[InputUnit.scala:87:24] tails_8 <= 5'h14; // @[InputUnit.scala:87:24] tails_9 <= 5'h18; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_11 & {to_q_oh_enc[9:8], \|(_to_q_T_2[6:3]), \|(_to_q_T_4[2:1]), _to_q_T_6} == 5'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 12, 0) node _source_ok_T = shr(io.in.a.bits.source, 13) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<13>(0h100f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits = bits(_uncommonBits_T, 12, 0) node _T_4 = shr(io.in.a.bits.source, 13) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<13>(0h100f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 12, 0) node _T_24 = shr(io.in.a.bits.source, 13) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<13>(0h100f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 12, 0) node _T_86 = shr(io.in.a.bits.source, 13) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<13>(0h100f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 12, 0) node _T_152 = shr(io.in.a.bits.source, 13) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<13>(0h100f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 12, 0) node _T_199 = shr(io.in.a.bits.source, 13) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<13>(0h100f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 12, 0) node _T_240 = shr(io.in.a.bits.source, 13) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<13>(0h100f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 12, 0) node _T_283 = shr(io.in.a.bits.source, 13) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<13>(0h100f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 12, 0) node _T_321 = shr(io.in.a.bits.source, 13) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<13>(0h100f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 12, 0) node _T_359 = shr(io.in.a.bits.source, 13) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<13>(0h100f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<13>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 12, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 13) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<13>(0h100f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<13>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<13>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4112>, clock, reset, UInt<4112>(0h0) regreset inflight_opcodes : UInt<16448>, clock, reset, UInt<16448>(0h0) regreset inflight_sizes : UInt<16448>, clock, reset, UInt<16448>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4112> connect a_set, UInt<4112>(0h0) wire a_set_wo_ready : UInt<4112> connect a_set_wo_ready, UInt<4112>(0h0) wire a_opcodes_set : UInt<16448> connect a_opcodes_set, UInt<16448>(0h0) wire a_sizes_set : UInt<16448> connect a_sizes_set, UInt<16448>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4112> connect d_clr, UInt<4112>(0h0) wire d_clr_wo_ready : UInt<4112> connect d_clr_wo_ready, UInt<4112>(0h0) wire d_opcodes_clr : UInt<16448> connect d_opcodes_clr, UInt<16448>(0h0) wire d_sizes_clr : UInt<16448> connect d_sizes_clr, UInt<16448>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_128 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4112>, clock, reset, UInt<4112>(0h0) regreset inflight_opcodes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0) regreset inflight_sizes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<13>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<13>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4112> connect c_set, UInt<4112>(0h0) wire c_set_wo_ready : UInt<4112> connect c_set_wo_ready, UInt<4112>(0h0) wire c_opcodes_set : UInt<16448> connect c_opcodes_set, UInt<16448>(0h0) wire c_sizes_set : UInt<16448> connect c_sizes_set, UInt<16448>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<13>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<13>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<13>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<13>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4112> connect d_clr_1, UInt<4112>(0h0) wire d_clr_wo_ready_1 : UInt<4112> connect d_clr_wo_ready_1, UInt<4112>(0h0) wire d_opcodes_clr_1 : UInt<16448> connect d_opcodes_clr_1, UInt<16448>(0h0) wire d_sizes_clr_1 : UInt<16448> connect d_sizes_clr_1, UInt<16448>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<13>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<13>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<13>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<13>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_129 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<13>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_131 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52] wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79] wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77] wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35] wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35] wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34] wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34] wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34] wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [12:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [12:0] source_1; // @[Monitor.scala:541:22] reg [4111:0] inflight; // @[Monitor.scala:614:27] reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [4111:0] a_set; // @[Monitor.scala:626:34] wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [8191:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4111:0] d_clr; // @[Monitor.scala:664:34] wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4111:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [16447:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [16447:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4111:0] inflight_1; // @[Monitor.scala:726:35] wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [4111:0] d_clr_1; // @[Monitor.scala:774:34] wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113] wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_238 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_255 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_238( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_255 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_83 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_83( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_30 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_30( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_413 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_157 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_413( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_157 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain : output auto : { flip plic_int_in : UInt<1>[2], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_1 : { sync : UInt<1>[1]}, int_in_clock_xing_out_0 : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst plic of TLPLIC connect plic.clock, childClock connect plic.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_3 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x1_4 connect intsource_1.clock, childClock connect intsource_1.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[1]} invalidate intInClockXingOut.sync[0] wire intInClockXingIn : { sync : UInt<1>[1]} invalidate intInClockXingIn.sync[0] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 connect intsource.auto.in[0], plic.auto.int_out_0[0] connect intsource_1.auto.in[0], plic.auto.int_out_1[0] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect plic.auto.in, auto.plic_in connect plic.auto.int_in[0], auto.plic_int_in[0] connect plic.auto.int_in[1], auto.plic_int_in[1] connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_105 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_106 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module PLICClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25] input auto_plic_int_in_1, // @[LazyModuleImp.scala:107:25] output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46] TLPLIC plic ( // @[Plic.scala:367:46] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_int_in_0 (auto_plic_int_in_0), .auto_int_in_1 (auto_plic_int_in_1), .auto_int_out_1_0 (_plic_auto_int_out_1_0), .auto_int_out_0_0 (_plic_auto_int_out_0_0), .auto_in_a_ready (auto_plic_in_a_ready), .auto_in_a_valid (auto_plic_in_a_valid), .auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode), .auto_in_a_bits_param (auto_plic_in_a_bits_param), .auto_in_a_bits_size (auto_plic_in_a_bits_size), .auto_in_a_bits_source (auto_plic_in_a_bits_source), .auto_in_a_bits_address (auto_plic_in_a_bits_address), .auto_in_a_bits_mask (auto_plic_in_a_bits_mask), .auto_in_a_bits_data (auto_plic_in_a_bits_data), .auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt), .auto_in_d_ready (auto_plic_in_d_ready), .auto_in_d_valid (auto_plic_in_d_valid), .auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode), .auto_in_d_bits_size (auto_plic_in_d_bits_size), .auto_in_d_bits_source (auto_plic_in_d_bits_source), .auto_in_d_bits_data (auto_plic_in_d_bits_data) ); // @[Plic.scala:367:46] IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46] .auto_out_sync_0 (auto_int_in_clock_xing_out_0_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46] .auto_out_sync_0 (auto_int_in_clock_xing_out_1_sync_0) ); // @[Crossing.scala:29:31] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_90 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_181 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_182 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_183 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_184 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_90( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_240 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_240( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_15 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_15( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_113 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_114 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_9 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_9 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_9 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_19 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFN_e8_s24_9( // @[MulAddRecFN.scala:300:7] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = 48'h0; // @[MulAddRecFN.scala:327:45] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [48:0] mulAddResult = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_9 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_9 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_19 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_97 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_97( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_35 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_70 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_71 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_35( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<6>, vc_free : UInt<6>}} wire _in_flight_WIRE : UInt<1>[6] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) regreset in_flight : UInt<1>[6], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_41 = and(_T_39, _T_40) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_47 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_54 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_61 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_68 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_89 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_96 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_153 = and(_T_151, _T_152) node _T_154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_159 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_160 = and(_T_158, _T_159) node _T_161 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_166 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_167 = and(_T_165, _T_166) node _T_168 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_173 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_174 = and(_T_172, _T_173) node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_180 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_187 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_188 = and(_T_186, _T_187) node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_194 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_201 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_206 = and(_T_204, _T_205) node _T_207 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_208 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_250 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_255 = and(_T_253, _T_254) node _T_256 = or(_T_17, _T_24) node _T_257 = or(_T_256, _T_31) node _T_258 = or(_T_257, _T_38) node _T_259 = or(_T_258, _T_45) node _T_260 = or(_T_259, _T_52) node _T_261 = or(_T_260, _T_59) node _T_262 = or(_T_261, _T_66) node _T_263 = or(_T_262, _T_73) node _T_264 = or(_T_263, _T_80) node _T_265 = or(_T_264, _T_87) node _T_266 = or(_T_265, _T_94) node _T_267 = or(_T_266, _T_101) node _T_268 = or(_T_267, _T_108) node _T_269 = or(_T_268, _T_115) node _T_270 = or(_T_269, _T_122) node _T_271 = or(_T_270, _T_129) node _T_272 = or(_T_271, _T_136) node _T_273 = or(_T_272, _T_143) node _T_274 = or(_T_273, _T_150) node _T_275 = or(_T_274, _T_157) node _T_276 = or(_T_275, _T_164) node _T_277 = or(_T_276, _T_171) node _T_278 = or(_T_277, _T_178) node _T_279 = or(_T_278, _T_185) node _T_280 = or(_T_279, _T_192) node _T_281 = or(_T_280, _T_199) node _T_282 = or(_T_281, _T_206) node _T_283 = or(_T_282, _T_213) node _T_284 = or(_T_283, _T_220) node _T_285 = or(_T_284, _T_227) node _T_286 = or(_T_285, _T_234) node _T_287 = or(_T_286, _T_241) node _T_288 = or(_T_287, _T_248) node _T_289 = or(_T_288, _T_255) node _T_290 = or(_T_10, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_290, UInt<1>(0h1), "") : assert_2 node _T_294 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_295 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_296 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_303 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_310 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_313 = and(_T_311, _T_312) node _T_314 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_315 = and(_T_313, _T_314) node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_320 = and(_T_318, _T_319) node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_325 = and(_T_323, _T_324) node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_329 = and(_T_327, _T_328) node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_339 = and(_T_337, _T_338) node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_346 = and(_T_344, _T_345) node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_350 = and(_T_348, _T_349) node _T_351 = or(_T_301, _T_308) node _T_352 = or(_T_351, _T_315) node _T_353 = or(_T_352, _T_322) node _T_354 = or(_T_353, _T_329) node _T_355 = or(_T_354, _T_336) node _T_356 = or(_T_355, _T_343) node _T_357 = or(_T_356, _T_350) node _T_358 = or(_T_294, _T_357) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_358, UInt<1>(0h1), "") : assert_3 node _T_362 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_363 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_364 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_369 = and(_T_367, _T_368) node _T_370 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_371 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_376 = and(_T_374, _T_375) node _T_377 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_378 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_385 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_392 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_399 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_400 = and(_T_398, _T_399) node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_404 = and(_T_402, _T_403) node _T_405 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_406 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_411 = and(_T_409, _T_410) node _T_412 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_413 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_418 = and(_T_416, _T_417) node _T_419 = or(_T_369, _T_376) node _T_420 = or(_T_419, _T_383) node _T_421 = or(_T_420, _T_390) node _T_422 = or(_T_421, _T_397) node _T_423 = or(_T_422, _T_404) node _T_424 = or(_T_423, _T_411) node _T_425 = or(_T_424, _T_418) node _T_426 = or(_T_362, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_426, UInt<1>(0h1), "") : assert_4 node _T_430 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_461 = and(_T_459, _T_460) node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_467 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_474 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_475 = and(_T_473, _T_474) node _T_476 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_479 = and(_T_477, _T_478) node _T_480 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_481 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_484 = and(_T_482, _T_483) node _T_485 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_488 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(_T_437, _T_444) node _T_495 = or(_T_494, _T_451) node _T_496 = or(_T_495, _T_458) node _T_497 = or(_T_496, _T_465) node _T_498 = or(_T_497, _T_472) node _T_499 = or(_T_498, _T_479) node _T_500 = or(_T_499, _T_486) node _T_501 = or(_T_500, _T_493) node _T_502 = or(_T_430, _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_502, UInt<1>(0h1), "") : assert_5 node _T_506 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_508 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_509 = and(_T_507, _T_508) node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_511 = and(_T_509, _T_510) node _T_512 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_515 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_516 = and(_T_514, _T_515) node _T_517 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_522 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_523 = and(_T_521, _T_522) node _T_524 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_525 = and(_T_523, _T_524) node _T_526 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_529 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_536 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_539 = and(_T_537, _T_538) node _T_540 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_543 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _T_547 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_548 = and(_T_546, _T_547) node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_550 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_553 = and(_T_551, _T_552) node _T_554 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_557 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_560 = and(_T_558, _T_559) node _T_561 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_564 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(_T_513, _T_520) node _T_571 = or(_T_570, _T_527) node _T_572 = or(_T_571, _T_534) node _T_573 = or(_T_572, _T_541) node _T_574 = or(_T_573, _T_548) node _T_575 = or(_T_574, _T_555) node _T_576 = or(_T_575, _T_562) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_506, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_578, UInt<1>(0h1), "") : assert_6	module NoCMonitor_12( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module FetchBuffer : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<40>, next_pc : UInt<40>, next_fetch : UInt<40>, edge_inst : UInt<1>[2], insts : UInt<32>[8], exp_insts : UInt<32>[8], pcs : UInt<40>[8], sfbs : UInt<1>[8], sfb_masks : UInt<16>[8], sfb_dests : UInt<5>[8], shadowable_mask : UInt<1>[8], shadowed_mask : UInt<1>[8], cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_type : UInt<3>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ftq_idx : UInt<5>, mask : UInt<8>, br_mask : UInt<8>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[2], xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, bp_debug_if_oh : UInt<1>[8], bp_xcpt_if_oh : UInt<1>[8], end_half : { valid : UInt<1>, bits : UInt<16>}, bpd_meta : UInt[2], fsrc : UInt<3>, tsrc : UInt<3>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3]}}, flip clear : UInt<1>} reg fb_uop_ram : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[24], clock wire deq_vec : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3][8] regreset head : UInt<8>, clock, reset, UInt<8>(0h1) regreset tail : UInt<24>, clock, reset, UInt<24>(0h1) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node _might_hit_head_T = bits(tail, 22, 0) node _might_hit_head_T_1 = bits(tail, 23, 23) node _might_hit_head_T_2 = cat(_might_hit_head_T, _might_hit_head_T_1) node _might_hit_head_T_3 = bits(_might_hit_head_T_2, 0, 0) node _might_hit_head_T_4 = bits(_might_hit_head_T_2, 1, 1) node _might_hit_head_T_5 = bits(_might_hit_head_T_2, 2, 2) node _might_hit_head_T_6 = bits(_might_hit_head_T_2, 3, 3) node _might_hit_head_T_7 = bits(_might_hit_head_T_2, 4, 4) node _might_hit_head_T_8 = bits(_might_hit_head_T_2, 5, 5) node _might_hit_head_T_9 = bits(_might_hit_head_T_2, 6, 6) node _might_hit_head_T_10 = bits(_might_hit_head_T_2, 7, 7) node _might_hit_head_T_11 = bits(_might_hit_head_T_2, 8, 8) node _might_hit_head_T_12 = bits(_might_hit_head_T_2, 9, 9) node _might_hit_head_T_13 = bits(_might_hit_head_T_2, 10, 10) node _might_hit_head_T_14 = bits(_might_hit_head_T_2, 11, 11) node _might_hit_head_T_15 = bits(_might_hit_head_T_2, 12, 12) node _might_hit_head_T_16 = bits(_might_hit_head_T_2, 13, 13) node _might_hit_head_T_17 = bits(_might_hit_head_T_2, 14, 14) node _might_hit_head_T_18 = bits(_might_hit_head_T_2, 15, 15) node _might_hit_head_T_19 = bits(_might_hit_head_T_2, 16, 16) node _might_hit_head_T_20 = bits(_might_hit_head_T_2, 17, 17) node _might_hit_head_T_21 = bits(_might_hit_head_T_2, 18, 18) node _might_hit_head_T_22 = bits(_might_hit_head_T_2, 19, 19) node _might_hit_head_T_23 = bits(_might_hit_head_T_2, 20, 20) node _might_hit_head_T_24 = bits(_might_hit_head_T_2, 21, 21) node _might_hit_head_T_25 = bits(_might_hit_head_T_2, 22, 22) node _might_hit_head_T_26 = bits(_might_hit_head_T_2, 23, 23) wire _might_hit_head_WIRE : UInt<1>[8] connect _might_hit_head_WIRE[0], _might_hit_head_T_3 connect _might_hit_head_WIRE[1], _might_hit_head_T_6 connect _might_hit_head_WIRE[2], _might_hit_head_T_9 connect _might_hit_head_WIRE[3], _might_hit_head_T_12 connect _might_hit_head_WIRE[4], _might_hit_head_T_15 connect _might_hit_head_WIRE[5], _might_hit_head_T_18 connect _might_hit_head_WIRE[6], _might_hit_head_T_21 connect _might_hit_head_WIRE[7], _might_hit_head_T_24 node might_hit_head_lo_lo = cat(_might_hit_head_WIRE[1], _might_hit_head_WIRE[0]) node might_hit_head_lo_hi = cat(_might_hit_head_WIRE[3], _might_hit_head_WIRE[2]) node might_hit_head_lo = cat(might_hit_head_lo_hi, might_hit_head_lo_lo) node might_hit_head_hi_lo = cat(_might_hit_head_WIRE[5], _might_hit_head_WIRE[4]) node might_hit_head_hi_hi = cat(_might_hit_head_WIRE[7], _might_hit_head_WIRE[6]) node might_hit_head_hi = cat(might_hit_head_hi_hi, might_hit_head_hi_lo) node _might_hit_head_T_27 = cat(might_hit_head_hi, might_hit_head_lo) node _might_hit_head_T_28 = bits(tail, 21, 0) node _might_hit_head_T_29 = bits(tail, 23, 22) node _might_hit_head_T_30 = cat(_might_hit_head_T_28, _might_hit_head_T_29) node _might_hit_head_T_31 = bits(_might_hit_head_T_30, 0, 0) node _might_hit_head_T_32 = bits(_might_hit_head_T_30, 1, 1) node _might_hit_head_T_33 = bits(_might_hit_head_T_30, 2, 2) node _might_hit_head_T_34 = bits(_might_hit_head_T_30, 3, 3) node _might_hit_head_T_35 = bits(_might_hit_head_T_30, 4, 4) node _might_hit_head_T_36 = bits(_might_hit_head_T_30, 5, 5) node _might_hit_head_T_37 = bits(_might_hit_head_T_30, 6, 6) node _might_hit_head_T_38 = bits(_might_hit_head_T_30, 7, 7) node _might_hit_head_T_39 = bits(_might_hit_head_T_30, 8, 8) node _might_hit_head_T_40 = bits(_might_hit_head_T_30, 9, 9) node _might_hit_head_T_41 = bits(_might_hit_head_T_30, 10, 10) node _might_hit_head_T_42 = bits(_might_hit_head_T_30, 11, 11) node _might_hit_head_T_43 = bits(_might_hit_head_T_30, 12, 12) node _might_hit_head_T_44 = bits(_might_hit_head_T_30, 13, 13) node _might_hit_head_T_45 = bits(_might_hit_head_T_30, 14, 14) node _might_hit_head_T_46 = bits(_might_hit_head_T_30, 15, 15) node _might_hit_head_T_47 = bits(_might_hit_head_T_30, 16, 16) node _might_hit_head_T_48 = bits(_might_hit_head_T_30, 17, 17) node _might_hit_head_T_49 = bits(_might_hit_head_T_30, 18, 18) node _might_hit_head_T_50 = bits(_might_hit_head_T_30, 19, 19) node _might_hit_head_T_51 = bits(_might_hit_head_T_30, 20, 20) node _might_hit_head_T_52 = bits(_might_hit_head_T_30, 21, 21) node _might_hit_head_T_53 = bits(_might_hit_head_T_30, 22, 22) node _might_hit_head_T_54 = bits(_might_hit_head_T_30, 23, 23) wire _might_hit_head_WIRE_1 : UInt<1>[8] connect _might_hit_head_WIRE_1[0], _might_hit_head_T_31 connect _might_hit_head_WIRE_1[1], _might_hit_head_T_34 connect _might_hit_head_WIRE_1[2], _might_hit_head_T_37 connect _might_hit_head_WIRE_1[3], _might_hit_head_T_40 connect _might_hit_head_WIRE_1[4], _might_hit_head_T_43 connect _might_hit_head_WIRE_1[5], _might_hit_head_T_46 connect _might_hit_head_WIRE_1[6], _might_hit_head_T_49 connect _might_hit_head_WIRE_1[7], _might_hit_head_T_52 node might_hit_head_lo_lo_1 = cat(_might_hit_head_WIRE_1[1], _might_hit_head_WIRE_1[0]) node might_hit_head_lo_hi_1 = cat(_might_hit_head_WIRE_1[3], _might_hit_head_WIRE_1[2]) node might_hit_head_lo_1 = cat(might_hit_head_lo_hi_1, might_hit_head_lo_lo_1) node might_hit_head_hi_lo_1 = cat(_might_hit_head_WIRE_1[5], _might_hit_head_WIRE_1[4]) node might_hit_head_hi_hi_1 = cat(_might_hit_head_WIRE_1[7], _might_hit_head_WIRE_1[6]) node might_hit_head_hi_1 = cat(might_hit_head_hi_hi_1, might_hit_head_hi_lo_1) node _might_hit_head_T_55 = cat(might_hit_head_hi_1, might_hit_head_lo_1) node _might_hit_head_T_56 = bits(tail, 20, 0) node _might_hit_head_T_57 = bits(tail, 23, 21) node _might_hit_head_T_58 = cat(_might_hit_head_T_56, _might_hit_head_T_57) node _might_hit_head_T_59 = bits(_might_hit_head_T_58, 0, 0) node _might_hit_head_T_60 = bits(_might_hit_head_T_58, 1, 1) node _might_hit_head_T_61 = bits(_might_hit_head_T_58, 2, 2) node _might_hit_head_T_62 = bits(_might_hit_head_T_58, 3, 3) node _might_hit_head_T_63 = bits(_might_hit_head_T_58, 4, 4) node _might_hit_head_T_64 = bits(_might_hit_head_T_58, 5, 5) node _might_hit_head_T_65 = bits(_might_hit_head_T_58, 6, 6) node _might_hit_head_T_66 = bits(_might_hit_head_T_58, 7, 7) node _might_hit_head_T_67 = bits(_might_hit_head_T_58, 8, 8) node _might_hit_head_T_68 = bits(_might_hit_head_T_58, 9, 9) node _might_hit_head_T_69 = bits(_might_hit_head_T_58, 10, 10) node _might_hit_head_T_70 = bits(_might_hit_head_T_58, 11, 11) node _might_hit_head_T_71 = bits(_might_hit_head_T_58, 12, 12) node _might_hit_head_T_72 = bits(_might_hit_head_T_58, 13, 13) node _might_hit_head_T_73 = bits(_might_hit_head_T_58, 14, 14) node _might_hit_head_T_74 = bits(_might_hit_head_T_58, 15, 15) node _might_hit_head_T_75 = bits(_might_hit_head_T_58, 16, 16) node _might_hit_head_T_76 = bits(_might_hit_head_T_58, 17, 17) node _might_hit_head_T_77 = bits(_might_hit_head_T_58, 18, 18) node _might_hit_head_T_78 = bits(_might_hit_head_T_58, 19, 19) node _might_hit_head_T_79 = bits(_might_hit_head_T_58, 20, 20) node _might_hit_head_T_80 = bits(_might_hit_head_T_58, 21, 21) node _might_hit_head_T_81 = bits(_might_hit_head_T_58, 22, 22) node _might_hit_head_T_82 = bits(_might_hit_head_T_58, 23, 23) wire _might_hit_head_WIRE_2 : UInt<1>[8] connect _might_hit_head_WIRE_2[0], _might_hit_head_T_59 connect _might_hit_head_WIRE_2[1], _might_hit_head_T_62 connect _might_hit_head_WIRE_2[2], _might_hit_head_T_65 connect _might_hit_head_WIRE_2[3], _might_hit_head_T_68 connect _might_hit_head_WIRE_2[4], _might_hit_head_T_71 connect _might_hit_head_WIRE_2[5], _might_hit_head_T_74 connect _might_hit_head_WIRE_2[6], _might_hit_head_T_77 connect _might_hit_head_WIRE_2[7], _might_hit_head_T_80 node might_hit_head_lo_lo_2 = cat(_might_hit_head_WIRE_2[1], _might_hit_head_WIRE_2[0]) node might_hit_head_lo_hi_2 = cat(_might_hit_head_WIRE_2[3], _might_hit_head_WIRE_2[2]) node might_hit_head_lo_2 = cat(might_hit_head_lo_hi_2, might_hit_head_lo_lo_2) node might_hit_head_hi_lo_2 = cat(_might_hit_head_WIRE_2[5], _might_hit_head_WIRE_2[4]) node might_hit_head_hi_hi_2 = cat(_might_hit_head_WIRE_2[7], _might_hit_head_WIRE_2[6]) node might_hit_head_hi_2 = cat(might_hit_head_hi_hi_2, might_hit_head_hi_lo_2) node _might_hit_head_T_83 = cat(might_hit_head_hi_2, might_hit_head_lo_2) node _might_hit_head_T_84 = bits(tail, 19, 0) node _might_hit_head_T_85 = bits(tail, 23, 20) node _might_hit_head_T_86 = cat(_might_hit_head_T_84, _might_hit_head_T_85) node _might_hit_head_T_87 = bits(_might_hit_head_T_86, 0, 0) node _might_hit_head_T_88 = bits(_might_hit_head_T_86, 1, 1) node _might_hit_head_T_89 = bits(_might_hit_head_T_86, 2, 2) node _might_hit_head_T_90 = bits(_might_hit_head_T_86, 3, 3) node _might_hit_head_T_91 = bits(_might_hit_head_T_86, 4, 4) node _might_hit_head_T_92 = bits(_might_hit_head_T_86, 5, 5) node _might_hit_head_T_93 = bits(_might_hit_head_T_86, 6, 6) node _might_hit_head_T_94 = bits(_might_hit_head_T_86, 7, 7) node _might_hit_head_T_95 = bits(_might_hit_head_T_86, 8, 8) node _might_hit_head_T_96 = bits(_might_hit_head_T_86, 9, 9) node _might_hit_head_T_97 = bits(_might_hit_head_T_86, 10, 10) node _might_hit_head_T_98 = bits(_might_hit_head_T_86, 11, 11) node _might_hit_head_T_99 = bits(_might_hit_head_T_86, 12, 12) node _might_hit_head_T_100 = bits(_might_hit_head_T_86, 13, 13) node _might_hit_head_T_101 = bits(_might_hit_head_T_86, 14, 14) node _might_hit_head_T_102 = bits(_might_hit_head_T_86, 15, 15) node _might_hit_head_T_103 = bits(_might_hit_head_T_86, 16, 16) node _might_hit_head_T_104 = bits(_might_hit_head_T_86, 17, 17) node _might_hit_head_T_105 = bits(_might_hit_head_T_86, 18, 18) node _might_hit_head_T_106 = bits(_might_hit_head_T_86, 19, 19) node _might_hit_head_T_107 = bits(_might_hit_head_T_86, 20, 20) node _might_hit_head_T_108 = bits(_might_hit_head_T_86, 21, 21) node _might_hit_head_T_109 = bits(_might_hit_head_T_86, 22, 22) node _might_hit_head_T_110 = bits(_might_hit_head_T_86, 23, 23) wire _might_hit_head_WIRE_3 : UInt<1>[8] connect _might_hit_head_WIRE_3[0], _might_hit_head_T_87 connect _might_hit_head_WIRE_3[1], _might_hit_head_T_90 connect _might_hit_head_WIRE_3[2], _might_hit_head_T_93 connect _might_hit_head_WIRE_3[3], _might_hit_head_T_96 connect _might_hit_head_WIRE_3[4], _might_hit_head_T_99 connect _might_hit_head_WIRE_3[5], _might_hit_head_T_102 connect _might_hit_head_WIRE_3[6], _might_hit_head_T_105 connect _might_hit_head_WIRE_3[7], _might_hit_head_T_108 node might_hit_head_lo_lo_3 = cat(_might_hit_head_WIRE_3[1], _might_hit_head_WIRE_3[0]) node might_hit_head_lo_hi_3 = cat(_might_hit_head_WIRE_3[3], _might_hit_head_WIRE_3[2]) node might_hit_head_lo_3 = cat(might_hit_head_lo_hi_3, might_hit_head_lo_lo_3) node might_hit_head_hi_lo_3 = cat(_might_hit_head_WIRE_3[5], _might_hit_head_WIRE_3[4]) node might_hit_head_hi_hi_3 = cat(_might_hit_head_WIRE_3[7], _might_hit_head_WIRE_3[6]) node might_hit_head_hi_3 = cat(might_hit_head_hi_hi_3, might_hit_head_hi_lo_3) node _might_hit_head_T_111 = cat(might_hit_head_hi_3, might_hit_head_lo_3) node _might_hit_head_T_112 = bits(tail, 18, 0) node _might_hit_head_T_113 = bits(tail, 23, 19) node _might_hit_head_T_114 = cat(_might_hit_head_T_112, _might_hit_head_T_113) node _might_hit_head_T_115 = bits(_might_hit_head_T_114, 0, 0) node _might_hit_head_T_116 = bits(_might_hit_head_T_114, 1, 1) node _might_hit_head_T_117 = bits(_might_hit_head_T_114, 2, 2) node _might_hit_head_T_118 = bits(_might_hit_head_T_114, 3, 3) node _might_hit_head_T_119 = bits(_might_hit_head_T_114, 4, 4) node _might_hit_head_T_120 = bits(_might_hit_head_T_114, 5, 5) node _might_hit_head_T_121 = bits(_might_hit_head_T_114, 6, 6) node _might_hit_head_T_122 = bits(_might_hit_head_T_114, 7, 7) node _might_hit_head_T_123 = bits(_might_hit_head_T_114, 8, 8) node _might_hit_head_T_124 = bits(_might_hit_head_T_114, 9, 9) node _might_hit_head_T_125 = bits(_might_hit_head_T_114, 10, 10) node _might_hit_head_T_126 = bits(_might_hit_head_T_114, 11, 11) node _might_hit_head_T_127 = bits(_might_hit_head_T_114, 12, 12) node _might_hit_head_T_128 = bits(_might_hit_head_T_114, 13, 13) node _might_hit_head_T_129 = bits(_might_hit_head_T_114, 14, 14) node _might_hit_head_T_130 = bits(_might_hit_head_T_114, 15, 15) node _might_hit_head_T_131 = bits(_might_hit_head_T_114, 16, 16) node _might_hit_head_T_132 = bits(_might_hit_head_T_114, 17, 17) node _might_hit_head_T_133 = bits(_might_hit_head_T_114, 18, 18) node _might_hit_head_T_134 = bits(_might_hit_head_T_114, 19, 19) node _might_hit_head_T_135 = bits(_might_hit_head_T_114, 20, 20) node _might_hit_head_T_136 = bits(_might_hit_head_T_114, 21, 21) node _might_hit_head_T_137 = bits(_might_hit_head_T_114, 22, 22) node _might_hit_head_T_138 = bits(_might_hit_head_T_114, 23, 23) wire _might_hit_head_WIRE_4 : UInt<1>[8] connect _might_hit_head_WIRE_4[0], _might_hit_head_T_115 connect _might_hit_head_WIRE_4[1], _might_hit_head_T_118 connect _might_hit_head_WIRE_4[2], _might_hit_head_T_121 connect _might_hit_head_WIRE_4[3], _might_hit_head_T_124 connect _might_hit_head_WIRE_4[4], _might_hit_head_T_127 connect _might_hit_head_WIRE_4[5], _might_hit_head_T_130 connect _might_hit_head_WIRE_4[6], _might_hit_head_T_133 connect _might_hit_head_WIRE_4[7], _might_hit_head_T_136 node might_hit_head_lo_lo_4 = cat(_might_hit_head_WIRE_4[1], _might_hit_head_WIRE_4[0]) node might_hit_head_lo_hi_4 = cat(_might_hit_head_WIRE_4[3], _might_hit_head_WIRE_4[2]) node might_hit_head_lo_4 = cat(might_hit_head_lo_hi_4, might_hit_head_lo_lo_4) node might_hit_head_hi_lo_4 = cat(_might_hit_head_WIRE_4[5], _might_hit_head_WIRE_4[4]) node might_hit_head_hi_hi_4 = cat(_might_hit_head_WIRE_4[7], _might_hit_head_WIRE_4[6]) node might_hit_head_hi_4 = cat(might_hit_head_hi_hi_4, might_hit_head_hi_lo_4) node _might_hit_head_T_139 = cat(might_hit_head_hi_4, might_hit_head_lo_4) node _might_hit_head_T_140 = bits(tail, 17, 0) node _might_hit_head_T_141 = bits(tail, 23, 18) node _might_hit_head_T_142 = cat(_might_hit_head_T_140, _might_hit_head_T_141) node _might_hit_head_T_143 = bits(_might_hit_head_T_142, 0, 0) node _might_hit_head_T_144 = bits(_might_hit_head_T_142, 1, 1) node _might_hit_head_T_145 = bits(_might_hit_head_T_142, 2, 2) node _might_hit_head_T_146 = bits(_might_hit_head_T_142, 3, 3) node _might_hit_head_T_147 = bits(_might_hit_head_T_142, 4, 4) node _might_hit_head_T_148 = bits(_might_hit_head_T_142, 5, 5) node _might_hit_head_T_149 = bits(_might_hit_head_T_142, 6, 6) node _might_hit_head_T_150 = bits(_might_hit_head_T_142, 7, 7) node _might_hit_head_T_151 = bits(_might_hit_head_T_142, 8, 8) node _might_hit_head_T_152 = bits(_might_hit_head_T_142, 9, 9) node _might_hit_head_T_153 = bits(_might_hit_head_T_142, 10, 10) node _might_hit_head_T_154 = bits(_might_hit_head_T_142, 11, 11) node _might_hit_head_T_155 = bits(_might_hit_head_T_142, 12, 12) node _might_hit_head_T_156 = bits(_might_hit_head_T_142, 13, 13) node _might_hit_head_T_157 = bits(_might_hit_head_T_142, 14, 14) node _might_hit_head_T_158 = bits(_might_hit_head_T_142, 15, 15) node _might_hit_head_T_159 = bits(_might_hit_head_T_142, 16, 16) node _might_hit_head_T_160 = bits(_might_hit_head_T_142, 17, 17) node _might_hit_head_T_161 = bits(_might_hit_head_T_142, 18, 18) node _might_hit_head_T_162 = bits(_might_hit_head_T_142, 19, 19) node _might_hit_head_T_163 = bits(_might_hit_head_T_142, 20, 20) node _might_hit_head_T_164 = bits(_might_hit_head_T_142, 21, 21) node _might_hit_head_T_165 = bits(_might_hit_head_T_142, 22, 22) node _might_hit_head_T_166 = bits(_might_hit_head_T_142, 23, 23) wire _might_hit_head_WIRE_5 : UInt<1>[8] connect _might_hit_head_WIRE_5[0], _might_hit_head_T_143 connect _might_hit_head_WIRE_5[1], _might_hit_head_T_146 connect _might_hit_head_WIRE_5[2], _might_hit_head_T_149 connect _might_hit_head_WIRE_5[3], _might_hit_head_T_152 connect _might_hit_head_WIRE_5[4], _might_hit_head_T_155 connect _might_hit_head_WIRE_5[5], _might_hit_head_T_158 connect _might_hit_head_WIRE_5[6], _might_hit_head_T_161 connect _might_hit_head_WIRE_5[7], _might_hit_head_T_164 node might_hit_head_lo_lo_5 = cat(_might_hit_head_WIRE_5[1], _might_hit_head_WIRE_5[0]) node might_hit_head_lo_hi_5 = cat(_might_hit_head_WIRE_5[3], _might_hit_head_WIRE_5[2]) node might_hit_head_lo_5 = cat(might_hit_head_lo_hi_5, might_hit_head_lo_lo_5) node might_hit_head_hi_lo_5 = cat(_might_hit_head_WIRE_5[5], _might_hit_head_WIRE_5[4]) node might_hit_head_hi_hi_5 = cat(_might_hit_head_WIRE_5[7], _might_hit_head_WIRE_5[6]) node might_hit_head_hi_5 = cat(might_hit_head_hi_hi_5, might_hit_head_hi_lo_5) node _might_hit_head_T_167 = cat(might_hit_head_hi_5, might_hit_head_lo_5) node _might_hit_head_T_168 = bits(tail, 16, 0) node _might_hit_head_T_169 = bits(tail, 23, 17) node _might_hit_head_T_170 = cat(_might_hit_head_T_168, _might_hit_head_T_169) node _might_hit_head_T_171 = bits(_might_hit_head_T_170, 0, 0) node _might_hit_head_T_172 = bits(_might_hit_head_T_170, 1, 1) node _might_hit_head_T_173 = bits(_might_hit_head_T_170, 2, 2) node _might_hit_head_T_174 = bits(_might_hit_head_T_170, 3, 3) node _might_hit_head_T_175 = bits(_might_hit_head_T_170, 4, 4) node _might_hit_head_T_176 = bits(_might_hit_head_T_170, 5, 5) node _might_hit_head_T_177 = bits(_might_hit_head_T_170, 6, 6) node _might_hit_head_T_178 = bits(_might_hit_head_T_170, 7, 7) node _might_hit_head_T_179 = bits(_might_hit_head_T_170, 8, 8) node _might_hit_head_T_180 = bits(_might_hit_head_T_170, 9, 9) node _might_hit_head_T_181 = bits(_might_hit_head_T_170, 10, 10) node _might_hit_head_T_182 = bits(_might_hit_head_T_170, 11, 11) node _might_hit_head_T_183 = bits(_might_hit_head_T_170, 12, 12) node _might_hit_head_T_184 = bits(_might_hit_head_T_170, 13, 13) node _might_hit_head_T_185 = bits(_might_hit_head_T_170, 14, 14) node _might_hit_head_T_186 = bits(_might_hit_head_T_170, 15, 15) node _might_hit_head_T_187 = bits(_might_hit_head_T_170, 16, 16) node _might_hit_head_T_188 = bits(_might_hit_head_T_170, 17, 17) node _might_hit_head_T_189 = bits(_might_hit_head_T_170, 18, 18) node _might_hit_head_T_190 = bits(_might_hit_head_T_170, 19, 19) node _might_hit_head_T_191 = bits(_might_hit_head_T_170, 20, 20) node _might_hit_head_T_192 = bits(_might_hit_head_T_170, 21, 21) node _might_hit_head_T_193 = bits(_might_hit_head_T_170, 22, 22) node _might_hit_head_T_194 = bits(_might_hit_head_T_170, 23, 23) wire _might_hit_head_WIRE_6 : UInt<1>[8] connect _might_hit_head_WIRE_6[0], _might_hit_head_T_171 connect _might_hit_head_WIRE_6[1], _might_hit_head_T_174 connect _might_hit_head_WIRE_6[2], _might_hit_head_T_177 connect _might_hit_head_WIRE_6[3], _might_hit_head_T_180 connect _might_hit_head_WIRE_6[4], _might_hit_head_T_183 connect _might_hit_head_WIRE_6[5], _might_hit_head_T_186 connect _might_hit_head_WIRE_6[6], _might_hit_head_T_189 connect _might_hit_head_WIRE_6[7], _might_hit_head_T_192 node might_hit_head_lo_lo_6 = cat(_might_hit_head_WIRE_6[1], _might_hit_head_WIRE_6[0]) node might_hit_head_lo_hi_6 = cat(_might_hit_head_WIRE_6[3], _might_hit_head_WIRE_6[2]) node might_hit_head_lo_6 = cat(might_hit_head_lo_hi_6, might_hit_head_lo_lo_6) node might_hit_head_hi_lo_6 = cat(_might_hit_head_WIRE_6[5], _might_hit_head_WIRE_6[4]) node might_hit_head_hi_hi_6 = cat(_might_hit_head_WIRE_6[7], _might_hit_head_WIRE_6[6]) node might_hit_head_hi_6 = cat(might_hit_head_hi_hi_6, might_hit_head_hi_lo_6) node _might_hit_head_T_195 = cat(might_hit_head_hi_6, might_hit_head_lo_6) node _might_hit_head_T_196 = and(head, _might_hit_head_T_27) node _might_hit_head_T_197 = and(head, _might_hit_head_T_55) node _might_hit_head_T_198 = and(head, _might_hit_head_T_83) node _might_hit_head_T_199 = and(head, _might_hit_head_T_111) node _might_hit_head_T_200 = and(head, _might_hit_head_T_139) node _might_hit_head_T_201 = and(head, _might_hit_head_T_167) node _might_hit_head_T_202 = and(head, _might_hit_head_T_195) node _might_hit_head_T_203 = or(_might_hit_head_T_196, _might_hit_head_T_197) node _might_hit_head_T_204 = or(_might_hit_head_T_203, _might_hit_head_T_198) node _might_hit_head_T_205 = or(_might_hit_head_T_204, _might_hit_head_T_199) node _might_hit_head_T_206 = or(_might_hit_head_T_205, _might_hit_head_T_200) node _might_hit_head_T_207 = or(_might_hit_head_T_206, _might_hit_head_T_201) node _might_hit_head_T_208 = or(_might_hit_head_T_207, _might_hit_head_T_202) node might_hit_head = orr(_might_hit_head_T_208) node _at_head_T = bits(tail, 0, 0) node _at_head_T_1 = bits(tail, 1, 1) node _at_head_T_2 = bits(tail, 2, 2) node _at_head_T_3 = bits(tail, 3, 3) node _at_head_T_4 = bits(tail, 4, 4) node _at_head_T_5 = bits(tail, 5, 5) node _at_head_T_6 = bits(tail, 6, 6) node _at_head_T_7 = bits(tail, 7, 7) node _at_head_T_8 = bits(tail, 8, 8) node _at_head_T_9 = bits(tail, 9, 9) node _at_head_T_10 = bits(tail, 10, 10) node _at_head_T_11 = bits(tail, 11, 11) node _at_head_T_12 = bits(tail, 12, 12) node _at_head_T_13 = bits(tail, 13, 13) node _at_head_T_14 = bits(tail, 14, 14) node _at_head_T_15 = bits(tail, 15, 15) node _at_head_T_16 = bits(tail, 16, 16) node _at_head_T_17 = bits(tail, 17, 17) node _at_head_T_18 = bits(tail, 18, 18) node _at_head_T_19 = bits(tail, 19, 19) node _at_head_T_20 = bits(tail, 20, 20) node _at_head_T_21 = bits(tail, 21, 21) node _at_head_T_22 = bits(tail, 22, 22) node _at_head_T_23 = bits(tail, 23, 23) wire _at_head_WIRE : UInt<1>[8] connect _at_head_WIRE[0], _at_head_T connect _at_head_WIRE[1], _at_head_T_3 connect _at_head_WIRE[2], _at_head_T_6 connect _at_head_WIRE[3], _at_head_T_9 connect _at_head_WIRE[4], _at_head_T_12 connect _at_head_WIRE[5], _at_head_T_15 connect _at_head_WIRE[6], _at_head_T_18 connect _at_head_WIRE[7], _at_head_T_21 node at_head_lo_lo = cat(_at_head_WIRE[1], _at_head_WIRE[0]) node at_head_lo_hi = cat(_at_head_WIRE[3], _at_head_WIRE[2]) node at_head_lo = cat(at_head_lo_hi, at_head_lo_lo) node at_head_hi_lo = cat(_at_head_WIRE[5], _at_head_WIRE[4]) node at_head_hi_hi = cat(_at_head_WIRE[7], _at_head_WIRE[6]) node at_head_hi = cat(at_head_hi_hi, at_head_hi_lo) node _at_head_T_24 = cat(at_head_hi, at_head_lo) node _at_head_T_25 = and(_at_head_T_24, head) node at_head = orr(_at_head_T_25) node _do_enq_T = and(at_head, maybe_full) node _do_enq_T_1 = or(_do_enq_T, might_hit_head) node do_enq = eq(_do_enq_T_1, UInt<1>(0h0)) connect io.enq.ready, do_enq wire in_mask : UInt<1>[8] wire in_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[8] node _pc_T = not(io.enq.bits.pc) node _pc_T_1 = or(_pc_T, UInt<3>(0h7)) node _pc_T_2 = not(_pc_T_1) node _pc_T_3 = add(_pc_T_2, UInt<1>(0h0)) node pc = tail(_pc_T_3, 1) invalidate in_uops[0].debug_tsrc invalidate in_uops[0].debug_fsrc invalidate in_uops[0].bp_xcpt_if invalidate in_uops[0].bp_debug_if invalidate in_uops[0].xcpt_ma_if invalidate in_uops[0].xcpt_ae_if invalidate in_uops[0].xcpt_pf_if invalidate in_uops[0].fp_typ invalidate in_uops[0].fp_rm invalidate in_uops[0].fp_val invalidate in_uops[0].fcn_op invalidate in_uops[0].fcn_dw invalidate in_uops[0].frs3_en invalidate in_uops[0].lrs2_rtype invalidate in_uops[0].lrs1_rtype invalidate in_uops[0].dst_rtype invalidate in_uops[0].lrs3 invalidate in_uops[0].lrs2 invalidate in_uops[0].lrs1 invalidate in_uops[0].ldst invalidate in_uops[0].ldst_is_rs1 invalidate in_uops[0].csr_cmd invalidate in_uops[0].flush_on_commit invalidate in_uops[0].is_unique invalidate in_uops[0].uses_stq invalidate in_uops[0].uses_ldq invalidate in_uops[0].mem_signed invalidate in_uops[0].mem_size invalidate in_uops[0].mem_cmd invalidate in_uops[0].exc_cause invalidate in_uops[0].exception invalidate in_uops[0].stale_pdst invalidate in_uops[0].ppred_busy invalidate in_uops[0].prs3_busy invalidate in_uops[0].prs2_busy invalidate in_uops[0].prs1_busy invalidate in_uops[0].ppred invalidate in_uops[0].prs3 invalidate in_uops[0].prs2 invalidate in_uops[0].prs1 invalidate in_uops[0].pdst invalidate in_uops[0].rxq_idx invalidate in_uops[0].stq_idx invalidate in_uops[0].ldq_idx invalidate in_uops[0].rob_idx invalidate in_uops[0].fp_ctrl.vec invalidate in_uops[0].fp_ctrl.wflags invalidate in_uops[0].fp_ctrl.sqrt invalidate in_uops[0].fp_ctrl.div invalidate in_uops[0].fp_ctrl.fma invalidate in_uops[0].fp_ctrl.fastpipe invalidate in_uops[0].fp_ctrl.toint invalidate in_uops[0].fp_ctrl.fromint invalidate in_uops[0].fp_ctrl.typeTagOut invalidate in_uops[0].fp_ctrl.typeTagIn invalidate in_uops[0].fp_ctrl.swap23 invalidate in_uops[0].fp_ctrl.swap12 invalidate in_uops[0].fp_ctrl.ren3 invalidate in_uops[0].fp_ctrl.ren2 invalidate in_uops[0].fp_ctrl.ren1 invalidate in_uops[0].fp_ctrl.wen invalidate in_uops[0].fp_ctrl.ldst invalidate in_uops[0].op2_sel invalidate in_uops[0].op1_sel invalidate in_uops[0].imm_packed invalidate in_uops[0].pimm invalidate in_uops[0].imm_sel invalidate in_uops[0].imm_rename invalidate in_uops[0].taken invalidate in_uops[0].pc_lob invalidate in_uops[0].edge_inst invalidate in_uops[0].ftq_idx invalidate in_uops[0].is_mov invalidate in_uops[0].is_rocc invalidate in_uops[0].is_sys_pc2epc invalidate in_uops[0].is_eret invalidate in_uops[0].is_amo invalidate in_uops[0].is_sfence invalidate in_uops[0].is_fencei invalidate in_uops[0].is_fence invalidate in_uops[0].is_sfb invalidate in_uops[0].br_type invalidate in_uops[0].br_tag invalidate in_uops[0].br_mask invalidate in_uops[0].dis_col_sel invalidate in_uops[0].iw_p3_bypass_hint invalidate in_uops[0].iw_p2_bypass_hint invalidate in_uops[0].iw_p1_bypass_hint invalidate in_uops[0].iw_p2_speculative_child invalidate in_uops[0].iw_p1_speculative_child invalidate in_uops[0].iw_issued_partial_dgen invalidate in_uops[0].iw_issued_partial_agen invalidate in_uops[0].iw_issued invalidate in_uops[0].fu_code[0] invalidate in_uops[0].fu_code[1] invalidate in_uops[0].fu_code[2] invalidate in_uops[0].fu_code[3] invalidate in_uops[0].fu_code[4] invalidate in_uops[0].fu_code[5] invalidate in_uops[0].fu_code[6] invalidate in_uops[0].fu_code[7] invalidate in_uops[0].fu_code[8] invalidate in_uops[0].fu_code[9] invalidate in_uops[0].iq_type[0] invalidate in_uops[0].iq_type[1] invalidate in_uops[0].iq_type[2] invalidate in_uops[0].iq_type[3] invalidate in_uops[0].debug_pc invalidate in_uops[0].is_rvc invalidate in_uops[0].debug_inst invalidate in_uops[0].inst node _in_mask_0_T = bits(io.enq.bits.mask, 0, 0) node _in_mask_0_T_1 = and(io.enq.valid, _in_mask_0_T) connect in_mask[0], _in_mask_0_T_1 connect in_uops[0].edge_inst, UInt<1>(0h0) connect in_uops[0].debug_pc, pc connect in_uops[0].pc_lob, pc node _in_uops_0_is_sfb_T = or(io.enq.bits.sfbs[0], io.enq.bits.shadowed_mask[0]) connect in_uops[0].is_sfb, _in_uops_0_is_sfb_T when io.enq.bits.edge_inst[0] : node _in_uops_0_debug_pc_T = not(io.enq.bits.pc) node _in_uops_0_debug_pc_T_1 = or(_in_uops_0_debug_pc_T, UInt<3>(0h7)) node _in_uops_0_debug_pc_T_2 = not(_in_uops_0_debug_pc_T_1) node _in_uops_0_debug_pc_T_3 = add(_in_uops_0_debug_pc_T_2, UInt<1>(0h0)) node _in_uops_0_debug_pc_T_4 = tail(_in_uops_0_debug_pc_T_3, 1) node _in_uops_0_debug_pc_T_5 = sub(_in_uops_0_debug_pc_T_4, UInt<2>(0h2)) node _in_uops_0_debug_pc_T_6 = tail(_in_uops_0_debug_pc_T_5, 1) connect in_uops[0].debug_pc, _in_uops_0_debug_pc_T_6 node _in_uops_0_pc_lob_T = not(io.enq.bits.pc) node _in_uops_0_pc_lob_T_1 = or(_in_uops_0_pc_lob_T, UInt<3>(0h7)) node _in_uops_0_pc_lob_T_2 = not(_in_uops_0_pc_lob_T_1) node _in_uops_0_pc_lob_T_3 = add(_in_uops_0_pc_lob_T_2, UInt<1>(0h0)) node _in_uops_0_pc_lob_T_4 = tail(_in_uops_0_pc_lob_T_3, 1) connect in_uops[0].pc_lob, _in_uops_0_pc_lob_T_4 connect in_uops[0].edge_inst, UInt<1>(0h1) connect in_uops[0].ftq_idx, io.enq.bits.ftq_idx connect in_uops[0].inst, io.enq.bits.exp_insts[0] connect in_uops[0].debug_inst, io.enq.bits.insts[0] node _in_uops_0_is_rvc_T = bits(io.enq.bits.insts[0], 1, 0) node _in_uops_0_is_rvc_T_1 = neq(_in_uops_0_is_rvc_T, UInt<2>(0h3)) connect in_uops[0].is_rvc, _in_uops_0_is_rvc_T_1 node _in_uops_0_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<1>(0h0)) node _in_uops_0_taken_T_1 = and(_in_uops_0_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[0].taken, _in_uops_0_taken_T_1 connect in_uops[0].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[0].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[0].bp_debug_if, io.enq.bits.bp_debug_if_oh[0] connect in_uops[0].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[0] connect in_uops[0].debug_fsrc, io.enq.bits.fsrc node _pc_T_4 = not(io.enq.bits.pc) node _pc_T_5 = or(_pc_T_4, UInt<3>(0h7)) node _pc_T_6 = not(_pc_T_5) node _pc_T_7 = add(_pc_T_6, UInt<2>(0h2)) node pc_1 = tail(_pc_T_7, 1) invalidate in_uops[1].debug_tsrc invalidate in_uops[1].debug_fsrc invalidate in_uops[1].bp_xcpt_if invalidate in_uops[1].bp_debug_if invalidate in_uops[1].xcpt_ma_if invalidate in_uops[1].xcpt_ae_if invalidate in_uops[1].xcpt_pf_if invalidate in_uops[1].fp_typ invalidate in_uops[1].fp_rm invalidate in_uops[1].fp_val invalidate in_uops[1].fcn_op invalidate in_uops[1].fcn_dw invalidate in_uops[1].frs3_en invalidate in_uops[1].lrs2_rtype invalidate in_uops[1].lrs1_rtype invalidate in_uops[1].dst_rtype invalidate in_uops[1].lrs3 invalidate in_uops[1].lrs2 invalidate in_uops[1].lrs1 invalidate in_uops[1].ldst invalidate in_uops[1].ldst_is_rs1 invalidate in_uops[1].csr_cmd invalidate in_uops[1].flush_on_commit invalidate in_uops[1].is_unique invalidate in_uops[1].uses_stq invalidate in_uops[1].uses_ldq invalidate in_uops[1].mem_signed invalidate in_uops[1].mem_size invalidate in_uops[1].mem_cmd invalidate in_uops[1].exc_cause invalidate in_uops[1].exception invalidate in_uops[1].stale_pdst invalidate in_uops[1].ppred_busy invalidate in_uops[1].prs3_busy invalidate in_uops[1].prs2_busy invalidate in_uops[1].prs1_busy invalidate in_uops[1].ppred invalidate in_uops[1].prs3 invalidate in_uops[1].prs2 invalidate in_uops[1].prs1 invalidate in_uops[1].pdst invalidate in_uops[1].rxq_idx invalidate in_uops[1].stq_idx invalidate in_uops[1].ldq_idx invalidate in_uops[1].rob_idx invalidate in_uops[1].fp_ctrl.vec invalidate in_uops[1].fp_ctrl.wflags invalidate in_uops[1].fp_ctrl.sqrt invalidate in_uops[1].fp_ctrl.div invalidate in_uops[1].fp_ctrl.fma invalidate in_uops[1].fp_ctrl.fastpipe invalidate in_uops[1].fp_ctrl.toint invalidate in_uops[1].fp_ctrl.fromint invalidate in_uops[1].fp_ctrl.typeTagOut invalidate in_uops[1].fp_ctrl.typeTagIn invalidate in_uops[1].fp_ctrl.swap23 invalidate in_uops[1].fp_ctrl.swap12 invalidate in_uops[1].fp_ctrl.ren3 invalidate in_uops[1].fp_ctrl.ren2 invalidate in_uops[1].fp_ctrl.ren1 invalidate in_uops[1].fp_ctrl.wen invalidate in_uops[1].fp_ctrl.ldst invalidate in_uops[1].op2_sel invalidate in_uops[1].op1_sel invalidate in_uops[1].imm_packed invalidate in_uops[1].pimm invalidate in_uops[1].imm_sel invalidate in_uops[1].imm_rename invalidate in_uops[1].taken invalidate in_uops[1].pc_lob invalidate in_uops[1].edge_inst invalidate in_uops[1].ftq_idx invalidate in_uops[1].is_mov invalidate in_uops[1].is_rocc invalidate in_uops[1].is_sys_pc2epc invalidate in_uops[1].is_eret invalidate in_uops[1].is_amo invalidate in_uops[1].is_sfence invalidate in_uops[1].is_fencei invalidate in_uops[1].is_fence invalidate in_uops[1].is_sfb invalidate in_uops[1].br_type invalidate in_uops[1].br_tag invalidate in_uops[1].br_mask invalidate in_uops[1].dis_col_sel invalidate in_uops[1].iw_p3_bypass_hint invalidate in_uops[1].iw_p2_bypass_hint invalidate in_uops[1].iw_p1_bypass_hint invalidate in_uops[1].iw_p2_speculative_child invalidate in_uops[1].iw_p1_speculative_child invalidate in_uops[1].iw_issued_partial_dgen invalidate in_uops[1].iw_issued_partial_agen invalidate in_uops[1].iw_issued invalidate in_uops[1].fu_code[0] invalidate in_uops[1].fu_code[1] invalidate in_uops[1].fu_code[2] invalidate in_uops[1].fu_code[3] invalidate in_uops[1].fu_code[4] invalidate in_uops[1].fu_code[5] invalidate in_uops[1].fu_code[6] invalidate in_uops[1].fu_code[7] invalidate in_uops[1].fu_code[8] invalidate in_uops[1].fu_code[9] invalidate in_uops[1].iq_type[0] invalidate in_uops[1].iq_type[1] invalidate in_uops[1].iq_type[2] invalidate in_uops[1].iq_type[3] invalidate in_uops[1].debug_pc invalidate in_uops[1].is_rvc invalidate in_uops[1].debug_inst invalidate in_uops[1].inst node _in_mask_1_T = bits(io.enq.bits.mask, 1, 1) node _in_mask_1_T_1 = and(io.enq.valid, _in_mask_1_T) connect in_mask[1], _in_mask_1_T_1 connect in_uops[1].edge_inst, UInt<1>(0h0) connect in_uops[1].debug_pc, pc_1 connect in_uops[1].pc_lob, pc_1 node _in_uops_1_is_sfb_T = or(io.enq.bits.sfbs[1], io.enq.bits.shadowed_mask[1]) connect in_uops[1].is_sfb, _in_uops_1_is_sfb_T connect in_uops[1].ftq_idx, io.enq.bits.ftq_idx connect in_uops[1].inst, io.enq.bits.exp_insts[1] connect in_uops[1].debug_inst, io.enq.bits.insts[1] node _in_uops_1_is_rvc_T = bits(io.enq.bits.insts[1], 1, 0) node _in_uops_1_is_rvc_T_1 = neq(_in_uops_1_is_rvc_T, UInt<2>(0h3)) connect in_uops[1].is_rvc, _in_uops_1_is_rvc_T_1 node _in_uops_1_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<1>(0h1)) node _in_uops_1_taken_T_1 = and(_in_uops_1_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[1].taken, _in_uops_1_taken_T_1 connect in_uops[1].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[1].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[1].bp_debug_if, io.enq.bits.bp_debug_if_oh[1] connect in_uops[1].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[1] connect in_uops[1].debug_fsrc, io.enq.bits.fsrc node _pc_T_8 = not(io.enq.bits.pc) node _pc_T_9 = or(_pc_T_8, UInt<3>(0h7)) node _pc_T_10 = not(_pc_T_9) node _pc_T_11 = add(_pc_T_10, UInt<3>(0h4)) node pc_2 = tail(_pc_T_11, 1) invalidate in_uops[2].debug_tsrc invalidate in_uops[2].debug_fsrc invalidate in_uops[2].bp_xcpt_if invalidate in_uops[2].bp_debug_if invalidate in_uops[2].xcpt_ma_if invalidate in_uops[2].xcpt_ae_if invalidate in_uops[2].xcpt_pf_if invalidate in_uops[2].fp_typ invalidate in_uops[2].fp_rm invalidate in_uops[2].fp_val invalidate in_uops[2].fcn_op invalidate in_uops[2].fcn_dw invalidate in_uops[2].frs3_en invalidate in_uops[2].lrs2_rtype invalidate in_uops[2].lrs1_rtype invalidate in_uops[2].dst_rtype invalidate in_uops[2].lrs3 invalidate in_uops[2].lrs2 invalidate in_uops[2].lrs1 invalidate in_uops[2].ldst invalidate in_uops[2].ldst_is_rs1 invalidate in_uops[2].csr_cmd invalidate in_uops[2].flush_on_commit invalidate in_uops[2].is_unique invalidate in_uops[2].uses_stq invalidate in_uops[2].uses_ldq invalidate in_uops[2].mem_signed invalidate in_uops[2].mem_size invalidate in_uops[2].mem_cmd invalidate in_uops[2].exc_cause invalidate in_uops[2].exception invalidate in_uops[2].stale_pdst invalidate in_uops[2].ppred_busy invalidate in_uops[2].prs3_busy invalidate in_uops[2].prs2_busy invalidate in_uops[2].prs1_busy invalidate in_uops[2].ppred invalidate in_uops[2].prs3 invalidate in_uops[2].prs2 invalidate in_uops[2].prs1 invalidate in_uops[2].pdst invalidate in_uops[2].rxq_idx invalidate in_uops[2].stq_idx invalidate in_uops[2].ldq_idx invalidate in_uops[2].rob_idx invalidate in_uops[2].fp_ctrl.vec invalidate in_uops[2].fp_ctrl.wflags invalidate in_uops[2].fp_ctrl.sqrt invalidate in_uops[2].fp_ctrl.div invalidate in_uops[2].fp_ctrl.fma invalidate in_uops[2].fp_ctrl.fastpipe invalidate in_uops[2].fp_ctrl.toint invalidate in_uops[2].fp_ctrl.fromint invalidate in_uops[2].fp_ctrl.typeTagOut invalidate in_uops[2].fp_ctrl.typeTagIn invalidate in_uops[2].fp_ctrl.swap23 invalidate in_uops[2].fp_ctrl.swap12 invalidate in_uops[2].fp_ctrl.ren3 invalidate in_uops[2].fp_ctrl.ren2 invalidate in_uops[2].fp_ctrl.ren1 invalidate in_uops[2].fp_ctrl.wen invalidate in_uops[2].fp_ctrl.ldst invalidate in_uops[2].op2_sel invalidate in_uops[2].op1_sel invalidate in_uops[2].imm_packed invalidate in_uops[2].pimm invalidate in_uops[2].imm_sel invalidate in_uops[2].imm_rename invalidate in_uops[2].taken invalidate in_uops[2].pc_lob invalidate in_uops[2].edge_inst invalidate in_uops[2].ftq_idx invalidate in_uops[2].is_mov invalidate in_uops[2].is_rocc invalidate in_uops[2].is_sys_pc2epc invalidate in_uops[2].is_eret invalidate in_uops[2].is_amo invalidate in_uops[2].is_sfence invalidate in_uops[2].is_fencei invalidate in_uops[2].is_fence invalidate in_uops[2].is_sfb invalidate in_uops[2].br_type invalidate in_uops[2].br_tag invalidate in_uops[2].br_mask invalidate in_uops[2].dis_col_sel invalidate in_uops[2].iw_p3_bypass_hint invalidate in_uops[2].iw_p2_bypass_hint invalidate in_uops[2].iw_p1_bypass_hint invalidate in_uops[2].iw_p2_speculative_child invalidate in_uops[2].iw_p1_speculative_child invalidate in_uops[2].iw_issued_partial_dgen invalidate in_uops[2].iw_issued_partial_agen invalidate in_uops[2].iw_issued invalidate in_uops[2].fu_code[0] invalidate in_uops[2].fu_code[1] invalidate in_uops[2].fu_code[2] invalidate in_uops[2].fu_code[3] invalidate in_uops[2].fu_code[4] invalidate in_uops[2].fu_code[5] invalidate in_uops[2].fu_code[6] invalidate in_uops[2].fu_code[7] invalidate in_uops[2].fu_code[8] invalidate in_uops[2].fu_code[9] invalidate in_uops[2].iq_type[0] invalidate in_uops[2].iq_type[1] invalidate in_uops[2].iq_type[2] invalidate in_uops[2].iq_type[3] invalidate in_uops[2].debug_pc invalidate in_uops[2].is_rvc invalidate in_uops[2].debug_inst invalidate in_uops[2].inst node _in_mask_2_T = bits(io.enq.bits.mask, 2, 2) node _in_mask_2_T_1 = and(io.enq.valid, _in_mask_2_T) connect in_mask[2], _in_mask_2_T_1 connect in_uops[2].edge_inst, UInt<1>(0h0) connect in_uops[2].debug_pc, pc_2 connect in_uops[2].pc_lob, pc_2 node _in_uops_2_is_sfb_T = or(io.enq.bits.sfbs[2], io.enq.bits.shadowed_mask[2]) connect in_uops[2].is_sfb, _in_uops_2_is_sfb_T connect in_uops[2].ftq_idx, io.enq.bits.ftq_idx connect in_uops[2].inst, io.enq.bits.exp_insts[2] connect in_uops[2].debug_inst, io.enq.bits.insts[2] node _in_uops_2_is_rvc_T = bits(io.enq.bits.insts[2], 1, 0) node _in_uops_2_is_rvc_T_1 = neq(_in_uops_2_is_rvc_T, UInt<2>(0h3)) connect in_uops[2].is_rvc, _in_uops_2_is_rvc_T_1 node _in_uops_2_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<2>(0h2)) node _in_uops_2_taken_T_1 = and(_in_uops_2_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[2].taken, _in_uops_2_taken_T_1 connect in_uops[2].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[2].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[2].bp_debug_if, io.enq.bits.bp_debug_if_oh[2] connect in_uops[2].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[2] connect in_uops[2].debug_fsrc, io.enq.bits.fsrc node _pc_T_12 = not(io.enq.bits.pc) node _pc_T_13 = or(_pc_T_12, UInt<3>(0h7)) node _pc_T_14 = not(_pc_T_13) node _pc_T_15 = add(_pc_T_14, UInt<3>(0h6)) node pc_3 = tail(_pc_T_15, 1) invalidate in_uops[3].debug_tsrc invalidate in_uops[3].debug_fsrc invalidate in_uops[3].bp_xcpt_if invalidate in_uops[3].bp_debug_if invalidate in_uops[3].xcpt_ma_if invalidate in_uops[3].xcpt_ae_if invalidate in_uops[3].xcpt_pf_if invalidate in_uops[3].fp_typ invalidate in_uops[3].fp_rm invalidate in_uops[3].fp_val invalidate in_uops[3].fcn_op invalidate in_uops[3].fcn_dw invalidate in_uops[3].frs3_en invalidate in_uops[3].lrs2_rtype invalidate in_uops[3].lrs1_rtype invalidate in_uops[3].dst_rtype invalidate in_uops[3].lrs3 invalidate in_uops[3].lrs2 invalidate in_uops[3].lrs1 invalidate in_uops[3].ldst invalidate in_uops[3].ldst_is_rs1 invalidate in_uops[3].csr_cmd invalidate in_uops[3].flush_on_commit invalidate in_uops[3].is_unique invalidate in_uops[3].uses_stq invalidate in_uops[3].uses_ldq invalidate in_uops[3].mem_signed invalidate in_uops[3].mem_size invalidate in_uops[3].mem_cmd invalidate in_uops[3].exc_cause invalidate in_uops[3].exception invalidate in_uops[3].stale_pdst invalidate in_uops[3].ppred_busy invalidate in_uops[3].prs3_busy invalidate in_uops[3].prs2_busy invalidate in_uops[3].prs1_busy invalidate in_uops[3].ppred invalidate in_uops[3].prs3 invalidate in_uops[3].prs2 invalidate in_uops[3].prs1 invalidate in_uops[3].pdst invalidate in_uops[3].rxq_idx invalidate in_uops[3].stq_idx invalidate in_uops[3].ldq_idx invalidate in_uops[3].rob_idx invalidate in_uops[3].fp_ctrl.vec invalidate in_uops[3].fp_ctrl.wflags invalidate in_uops[3].fp_ctrl.sqrt invalidate in_uops[3].fp_ctrl.div invalidate in_uops[3].fp_ctrl.fma invalidate in_uops[3].fp_ctrl.fastpipe invalidate in_uops[3].fp_ctrl.toint invalidate in_uops[3].fp_ctrl.fromint invalidate in_uops[3].fp_ctrl.typeTagOut invalidate in_uops[3].fp_ctrl.typeTagIn invalidate in_uops[3].fp_ctrl.swap23 invalidate in_uops[3].fp_ctrl.swap12 invalidate in_uops[3].fp_ctrl.ren3 invalidate in_uops[3].fp_ctrl.ren2 invalidate in_uops[3].fp_ctrl.ren1 invalidate in_uops[3].fp_ctrl.wen invalidate in_uops[3].fp_ctrl.ldst invalidate in_uops[3].op2_sel invalidate in_uops[3].op1_sel invalidate in_uops[3].imm_packed invalidate in_uops[3].pimm invalidate in_uops[3].imm_sel invalidate in_uops[3].imm_rename invalidate in_uops[3].taken invalidate in_uops[3].pc_lob invalidate in_uops[3].edge_inst invalidate in_uops[3].ftq_idx invalidate in_uops[3].is_mov invalidate in_uops[3].is_rocc invalidate in_uops[3].is_sys_pc2epc invalidate in_uops[3].is_eret invalidate in_uops[3].is_amo invalidate in_uops[3].is_sfence invalidate in_uops[3].is_fencei invalidate in_uops[3].is_fence invalidate in_uops[3].is_sfb invalidate in_uops[3].br_type invalidate in_uops[3].br_tag invalidate in_uops[3].br_mask invalidate in_uops[3].dis_col_sel invalidate in_uops[3].iw_p3_bypass_hint invalidate in_uops[3].iw_p2_bypass_hint invalidate in_uops[3].iw_p1_bypass_hint invalidate in_uops[3].iw_p2_speculative_child invalidate in_uops[3].iw_p1_speculative_child invalidate in_uops[3].iw_issued_partial_dgen invalidate in_uops[3].iw_issued_partial_agen invalidate in_uops[3].iw_issued invalidate in_uops[3].fu_code[0] invalidate in_uops[3].fu_code[1] invalidate in_uops[3].fu_code[2] invalidate in_uops[3].fu_code[3] invalidate in_uops[3].fu_code[4] invalidate in_uops[3].fu_code[5] invalidate in_uops[3].fu_code[6] invalidate in_uops[3].fu_code[7] invalidate in_uops[3].fu_code[8] invalidate in_uops[3].fu_code[9] invalidate in_uops[3].iq_type[0] invalidate in_uops[3].iq_type[1] invalidate in_uops[3].iq_type[2] invalidate in_uops[3].iq_type[3] invalidate in_uops[3].debug_pc invalidate in_uops[3].is_rvc invalidate in_uops[3].debug_inst invalidate in_uops[3].inst node _in_mask_3_T = bits(io.enq.bits.mask, 3, 3) node _in_mask_3_T_1 = and(io.enq.valid, _in_mask_3_T) connect in_mask[3], _in_mask_3_T_1 connect in_uops[3].edge_inst, UInt<1>(0h0) connect in_uops[3].debug_pc, pc_3 connect in_uops[3].pc_lob, pc_3 node _in_uops_3_is_sfb_T = or(io.enq.bits.sfbs[3], io.enq.bits.shadowed_mask[3]) connect in_uops[3].is_sfb, _in_uops_3_is_sfb_T connect in_uops[3].ftq_idx, io.enq.bits.ftq_idx connect in_uops[3].inst, io.enq.bits.exp_insts[3] connect in_uops[3].debug_inst, io.enq.bits.insts[3] node _in_uops_3_is_rvc_T = bits(io.enq.bits.insts[3], 1, 0) node _in_uops_3_is_rvc_T_1 = neq(_in_uops_3_is_rvc_T, UInt<2>(0h3)) connect in_uops[3].is_rvc, _in_uops_3_is_rvc_T_1 node _in_uops_3_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<2>(0h3)) node _in_uops_3_taken_T_1 = and(_in_uops_3_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[3].taken, _in_uops_3_taken_T_1 connect in_uops[3].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[3].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[3].bp_debug_if, io.enq.bits.bp_debug_if_oh[3] connect in_uops[3].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[3] connect in_uops[3].debug_fsrc, io.enq.bits.fsrc node _pc_T_16 = not(io.enq.bits.pc) node _pc_T_17 = or(_pc_T_16, UInt<3>(0h7)) node _pc_T_18 = not(_pc_T_17) node _pc_T_19 = add(_pc_T_18, UInt<4>(0h8)) node pc_4 = tail(_pc_T_19, 1) invalidate in_uops[4].debug_tsrc invalidate in_uops[4].debug_fsrc invalidate in_uops[4].bp_xcpt_if invalidate in_uops[4].bp_debug_if invalidate in_uops[4].xcpt_ma_if invalidate in_uops[4].xcpt_ae_if invalidate in_uops[4].xcpt_pf_if invalidate in_uops[4].fp_typ invalidate in_uops[4].fp_rm invalidate in_uops[4].fp_val invalidate in_uops[4].fcn_op invalidate in_uops[4].fcn_dw invalidate in_uops[4].frs3_en invalidate in_uops[4].lrs2_rtype invalidate in_uops[4].lrs1_rtype invalidate in_uops[4].dst_rtype invalidate in_uops[4].lrs3 invalidate in_uops[4].lrs2 invalidate in_uops[4].lrs1 invalidate in_uops[4].ldst invalidate in_uops[4].ldst_is_rs1 invalidate in_uops[4].csr_cmd invalidate in_uops[4].flush_on_commit invalidate in_uops[4].is_unique invalidate in_uops[4].uses_stq invalidate in_uops[4].uses_ldq invalidate in_uops[4].mem_signed invalidate in_uops[4].mem_size invalidate in_uops[4].mem_cmd invalidate in_uops[4].exc_cause invalidate in_uops[4].exception invalidate in_uops[4].stale_pdst invalidate in_uops[4].ppred_busy invalidate in_uops[4].prs3_busy invalidate in_uops[4].prs2_busy invalidate in_uops[4].prs1_busy invalidate in_uops[4].ppred invalidate in_uops[4].prs3 invalidate in_uops[4].prs2 invalidate in_uops[4].prs1 invalidate in_uops[4].pdst invalidate in_uops[4].rxq_idx invalidate in_uops[4].stq_idx invalidate in_uops[4].ldq_idx invalidate in_uops[4].rob_idx invalidate in_uops[4].fp_ctrl.vec invalidate in_uops[4].fp_ctrl.wflags invalidate in_uops[4].fp_ctrl.sqrt invalidate in_uops[4].fp_ctrl.div invalidate in_uops[4].fp_ctrl.fma invalidate in_uops[4].fp_ctrl.fastpipe invalidate in_uops[4].fp_ctrl.toint invalidate in_uops[4].fp_ctrl.fromint invalidate in_uops[4].fp_ctrl.typeTagOut invalidate in_uops[4].fp_ctrl.typeTagIn invalidate in_uops[4].fp_ctrl.swap23 invalidate in_uops[4].fp_ctrl.swap12 invalidate in_uops[4].fp_ctrl.ren3 invalidate in_uops[4].fp_ctrl.ren2 invalidate in_uops[4].fp_ctrl.ren1 invalidate in_uops[4].fp_ctrl.wen invalidate in_uops[4].fp_ctrl.ldst invalidate in_uops[4].op2_sel invalidate in_uops[4].op1_sel invalidate in_uops[4].imm_packed invalidate in_uops[4].pimm invalidate in_uops[4].imm_sel invalidate in_uops[4].imm_rename invalidate in_uops[4].taken invalidate in_uops[4].pc_lob invalidate in_uops[4].edge_inst invalidate in_uops[4].ftq_idx invalidate in_uops[4].is_mov invalidate in_uops[4].is_rocc invalidate in_uops[4].is_sys_pc2epc invalidate in_uops[4].is_eret invalidate in_uops[4].is_amo invalidate in_uops[4].is_sfence invalidate in_uops[4].is_fencei invalidate in_uops[4].is_fence invalidate in_uops[4].is_sfb invalidate in_uops[4].br_type invalidate in_uops[4].br_tag invalidate in_uops[4].br_mask invalidate in_uops[4].dis_col_sel invalidate in_uops[4].iw_p3_bypass_hint invalidate in_uops[4].iw_p2_bypass_hint invalidate in_uops[4].iw_p1_bypass_hint invalidate in_uops[4].iw_p2_speculative_child invalidate in_uops[4].iw_p1_speculative_child invalidate in_uops[4].iw_issued_partial_dgen invalidate in_uops[4].iw_issued_partial_agen invalidate in_uops[4].iw_issued invalidate in_uops[4].fu_code[0] invalidate in_uops[4].fu_code[1] invalidate in_uops[4].fu_code[2] invalidate in_uops[4].fu_code[3] invalidate in_uops[4].fu_code[4] invalidate in_uops[4].fu_code[5] invalidate in_uops[4].fu_code[6] invalidate in_uops[4].fu_code[7] invalidate in_uops[4].fu_code[8] invalidate in_uops[4].fu_code[9] invalidate in_uops[4].iq_type[0] invalidate in_uops[4].iq_type[1] invalidate in_uops[4].iq_type[2] invalidate in_uops[4].iq_type[3] invalidate in_uops[4].debug_pc invalidate in_uops[4].is_rvc invalidate in_uops[4].debug_inst invalidate in_uops[4].inst node _in_mask_4_T = bits(io.enq.bits.mask, 4, 4) node _in_mask_4_T_1 = and(io.enq.valid, _in_mask_4_T) connect in_mask[4], _in_mask_4_T_1 connect in_uops[4].edge_inst, UInt<1>(0h0) connect in_uops[4].debug_pc, pc_4 connect in_uops[4].pc_lob, pc_4 node _in_uops_4_is_sfb_T = or(io.enq.bits.sfbs[4], io.enq.bits.shadowed_mask[4]) connect in_uops[4].is_sfb, _in_uops_4_is_sfb_T when io.enq.bits.edge_inst[1] : node _in_uops_4_debug_pc_T = not(io.enq.bits.pc) node _in_uops_4_debug_pc_T_1 = or(_in_uops_4_debug_pc_T, UInt<3>(0h7)) node _in_uops_4_debug_pc_T_2 = not(_in_uops_4_debug_pc_T_1) node _in_uops_4_debug_pc_T_3 = add(_in_uops_4_debug_pc_T_2, UInt<4>(0h8)) node _in_uops_4_debug_pc_T_4 = tail(_in_uops_4_debug_pc_T_3, 1) node _in_uops_4_debug_pc_T_5 = sub(_in_uops_4_debug_pc_T_4, UInt<2>(0h2)) node _in_uops_4_debug_pc_T_6 = tail(_in_uops_4_debug_pc_T_5, 1) connect in_uops[4].debug_pc, _in_uops_4_debug_pc_T_6 node _in_uops_4_pc_lob_T = not(io.enq.bits.pc) node _in_uops_4_pc_lob_T_1 = or(_in_uops_4_pc_lob_T, UInt<3>(0h7)) node _in_uops_4_pc_lob_T_2 = not(_in_uops_4_pc_lob_T_1) node _in_uops_4_pc_lob_T_3 = add(_in_uops_4_pc_lob_T_2, UInt<4>(0h8)) node _in_uops_4_pc_lob_T_4 = tail(_in_uops_4_pc_lob_T_3, 1) connect in_uops[4].pc_lob, _in_uops_4_pc_lob_T_4 connect in_uops[4].edge_inst, UInt<1>(0h1) connect in_uops[4].ftq_idx, io.enq.bits.ftq_idx connect in_uops[4].inst, io.enq.bits.exp_insts[4] connect in_uops[4].debug_inst, io.enq.bits.insts[4] node _in_uops_4_is_rvc_T = bits(io.enq.bits.insts[4], 1, 0) node _in_uops_4_is_rvc_T_1 = neq(_in_uops_4_is_rvc_T, UInt<2>(0h3)) connect in_uops[4].is_rvc, _in_uops_4_is_rvc_T_1 node _in_uops_4_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h4)) node _in_uops_4_taken_T_1 = and(_in_uops_4_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[4].taken, _in_uops_4_taken_T_1 connect in_uops[4].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[4].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[4].bp_debug_if, io.enq.bits.bp_debug_if_oh[4] connect in_uops[4].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[4] connect in_uops[4].debug_fsrc, io.enq.bits.fsrc node _pc_T_20 = not(io.enq.bits.pc) node _pc_T_21 = or(_pc_T_20, UInt<3>(0h7)) node _pc_T_22 = not(_pc_T_21) node _pc_T_23 = add(_pc_T_22, UInt<4>(0ha)) node pc_5 = tail(_pc_T_23, 1) invalidate in_uops[5].debug_tsrc invalidate in_uops[5].debug_fsrc invalidate in_uops[5].bp_xcpt_if invalidate in_uops[5].bp_debug_if invalidate in_uops[5].xcpt_ma_if invalidate in_uops[5].xcpt_ae_if invalidate in_uops[5].xcpt_pf_if invalidate in_uops[5].fp_typ invalidate in_uops[5].fp_rm invalidate in_uops[5].fp_val invalidate in_uops[5].fcn_op invalidate in_uops[5].fcn_dw invalidate in_uops[5].frs3_en invalidate in_uops[5].lrs2_rtype invalidate in_uops[5].lrs1_rtype invalidate in_uops[5].dst_rtype invalidate in_uops[5].lrs3 invalidate in_uops[5].lrs2 invalidate in_uops[5].lrs1 invalidate in_uops[5].ldst invalidate in_uops[5].ldst_is_rs1 invalidate in_uops[5].csr_cmd invalidate in_uops[5].flush_on_commit invalidate in_uops[5].is_unique invalidate in_uops[5].uses_stq invalidate in_uops[5].uses_ldq invalidate in_uops[5].mem_signed invalidate in_uops[5].mem_size invalidate in_uops[5].mem_cmd invalidate in_uops[5].exc_cause invalidate in_uops[5].exception invalidate in_uops[5].stale_pdst invalidate in_uops[5].ppred_busy invalidate in_uops[5].prs3_busy invalidate in_uops[5].prs2_busy invalidate in_uops[5].prs1_busy invalidate in_uops[5].ppred invalidate in_uops[5].prs3 invalidate in_uops[5].prs2 invalidate in_uops[5].prs1 invalidate in_uops[5].pdst invalidate in_uops[5].rxq_idx invalidate in_uops[5].stq_idx invalidate in_uops[5].ldq_idx invalidate in_uops[5].rob_idx invalidate in_uops[5].fp_ctrl.vec invalidate in_uops[5].fp_ctrl.wflags invalidate in_uops[5].fp_ctrl.sqrt invalidate in_uops[5].fp_ctrl.div invalidate in_uops[5].fp_ctrl.fma invalidate in_uops[5].fp_ctrl.fastpipe invalidate in_uops[5].fp_ctrl.toint invalidate in_uops[5].fp_ctrl.fromint invalidate in_uops[5].fp_ctrl.typeTagOut invalidate in_uops[5].fp_ctrl.typeTagIn invalidate in_uops[5].fp_ctrl.swap23 invalidate in_uops[5].fp_ctrl.swap12 invalidate in_uops[5].fp_ctrl.ren3 invalidate in_uops[5].fp_ctrl.ren2 invalidate in_uops[5].fp_ctrl.ren1 invalidate in_uops[5].fp_ctrl.wen invalidate in_uops[5].fp_ctrl.ldst invalidate in_uops[5].op2_sel invalidate in_uops[5].op1_sel invalidate in_uops[5].imm_packed invalidate in_uops[5].pimm invalidate in_uops[5].imm_sel invalidate in_uops[5].imm_rename invalidate in_uops[5].taken invalidate in_uops[5].pc_lob invalidate in_uops[5].edge_inst invalidate in_uops[5].ftq_idx invalidate in_uops[5].is_mov invalidate in_uops[5].is_rocc invalidate in_uops[5].is_sys_pc2epc invalidate in_uops[5].is_eret invalidate in_uops[5].is_amo invalidate in_uops[5].is_sfence invalidate in_uops[5].is_fencei invalidate in_uops[5].is_fence invalidate in_uops[5].is_sfb invalidate in_uops[5].br_type invalidate in_uops[5].br_tag invalidate in_uops[5].br_mask invalidate in_uops[5].dis_col_sel invalidate in_uops[5].iw_p3_bypass_hint invalidate in_uops[5].iw_p2_bypass_hint invalidate in_uops[5].iw_p1_bypass_hint invalidate in_uops[5].iw_p2_speculative_child invalidate in_uops[5].iw_p1_speculative_child invalidate in_uops[5].iw_issued_partial_dgen invalidate in_uops[5].iw_issued_partial_agen invalidate in_uops[5].iw_issued invalidate in_uops[5].fu_code[0] invalidate in_uops[5].fu_code[1] invalidate in_uops[5].fu_code[2] invalidate in_uops[5].fu_code[3] invalidate in_uops[5].fu_code[4] invalidate in_uops[5].fu_code[5] invalidate in_uops[5].fu_code[6] invalidate in_uops[5].fu_code[7] invalidate in_uops[5].fu_code[8] invalidate in_uops[5].fu_code[9] invalidate in_uops[5].iq_type[0] invalidate in_uops[5].iq_type[1] invalidate in_uops[5].iq_type[2] invalidate in_uops[5].iq_type[3] invalidate in_uops[5].debug_pc invalidate in_uops[5].is_rvc invalidate in_uops[5].debug_inst invalidate in_uops[5].inst node _in_mask_5_T = bits(io.enq.bits.mask, 5, 5) node _in_mask_5_T_1 = and(io.enq.valid, _in_mask_5_T) connect in_mask[5], _in_mask_5_T_1 connect in_uops[5].edge_inst, UInt<1>(0h0) connect in_uops[5].debug_pc, pc_5 connect in_uops[5].pc_lob, pc_5 node _in_uops_5_is_sfb_T = or(io.enq.bits.sfbs[5], io.enq.bits.shadowed_mask[5]) connect in_uops[5].is_sfb, _in_uops_5_is_sfb_T connect in_uops[5].ftq_idx, io.enq.bits.ftq_idx connect in_uops[5].inst, io.enq.bits.exp_insts[5] connect in_uops[5].debug_inst, io.enq.bits.insts[5] node _in_uops_5_is_rvc_T = bits(io.enq.bits.insts[5], 1, 0) node _in_uops_5_is_rvc_T_1 = neq(_in_uops_5_is_rvc_T, UInt<2>(0h3)) connect in_uops[5].is_rvc, _in_uops_5_is_rvc_T_1 node _in_uops_5_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h5)) node _in_uops_5_taken_T_1 = and(_in_uops_5_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[5].taken, _in_uops_5_taken_T_1 connect in_uops[5].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[5].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[5].bp_debug_if, io.enq.bits.bp_debug_if_oh[5] connect in_uops[5].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[5] connect in_uops[5].debug_fsrc, io.enq.bits.fsrc node _pc_T_24 = not(io.enq.bits.pc) node _pc_T_25 = or(_pc_T_24, UInt<3>(0h7)) node _pc_T_26 = not(_pc_T_25) node _pc_T_27 = add(_pc_T_26, UInt<4>(0hc)) node pc_6 = tail(_pc_T_27, 1) invalidate in_uops[6].debug_tsrc invalidate in_uops[6].debug_fsrc invalidate in_uops[6].bp_xcpt_if invalidate in_uops[6].bp_debug_if invalidate in_uops[6].xcpt_ma_if invalidate in_uops[6].xcpt_ae_if invalidate in_uops[6].xcpt_pf_if invalidate in_uops[6].fp_typ invalidate in_uops[6].fp_rm invalidate in_uops[6].fp_val invalidate in_uops[6].fcn_op invalidate in_uops[6].fcn_dw invalidate in_uops[6].frs3_en invalidate in_uops[6].lrs2_rtype invalidate in_uops[6].lrs1_rtype invalidate in_uops[6].dst_rtype invalidate in_uops[6].lrs3 invalidate in_uops[6].lrs2 invalidate in_uops[6].lrs1 invalidate in_uops[6].ldst invalidate in_uops[6].ldst_is_rs1 invalidate in_uops[6].csr_cmd invalidate in_uops[6].flush_on_commit invalidate in_uops[6].is_unique invalidate in_uops[6].uses_stq invalidate in_uops[6].uses_ldq invalidate in_uops[6].mem_signed invalidate in_uops[6].mem_size invalidate in_uops[6].mem_cmd invalidate in_uops[6].exc_cause invalidate in_uops[6].exception invalidate in_uops[6].stale_pdst invalidate in_uops[6].ppred_busy invalidate in_uops[6].prs3_busy invalidate in_uops[6].prs2_busy invalidate in_uops[6].prs1_busy invalidate in_uops[6].ppred invalidate in_uops[6].prs3 invalidate in_uops[6].prs2 invalidate in_uops[6].prs1 invalidate in_uops[6].pdst invalidate in_uops[6].rxq_idx invalidate in_uops[6].stq_idx invalidate in_uops[6].ldq_idx invalidate in_uops[6].rob_idx invalidate in_uops[6].fp_ctrl.vec invalidate in_uops[6].fp_ctrl.wflags invalidate in_uops[6].fp_ctrl.sqrt invalidate in_uops[6].fp_ctrl.div invalidate in_uops[6].fp_ctrl.fma invalidate in_uops[6].fp_ctrl.fastpipe invalidate in_uops[6].fp_ctrl.toint invalidate in_uops[6].fp_ctrl.fromint invalidate in_uops[6].fp_ctrl.typeTagOut invalidate in_uops[6].fp_ctrl.typeTagIn invalidate in_uops[6].fp_ctrl.swap23 invalidate in_uops[6].fp_ctrl.swap12 invalidate in_uops[6].fp_ctrl.ren3 invalidate in_uops[6].fp_ctrl.ren2 invalidate in_uops[6].fp_ctrl.ren1 invalidate in_uops[6].fp_ctrl.wen invalidate in_uops[6].fp_ctrl.ldst invalidate in_uops[6].op2_sel invalidate in_uops[6].op1_sel invalidate in_uops[6].imm_packed invalidate in_uops[6].pimm invalidate in_uops[6].imm_sel invalidate in_uops[6].imm_rename invalidate in_uops[6].taken invalidate in_uops[6].pc_lob invalidate in_uops[6].edge_inst invalidate in_uops[6].ftq_idx invalidate in_uops[6].is_mov invalidate in_uops[6].is_rocc invalidate in_uops[6].is_sys_pc2epc invalidate in_uops[6].is_eret invalidate in_uops[6].is_amo invalidate in_uops[6].is_sfence invalidate in_uops[6].is_fencei invalidate in_uops[6].is_fence invalidate in_uops[6].is_sfb invalidate in_uops[6].br_type invalidate in_uops[6].br_tag invalidate in_uops[6].br_mask invalidate in_uops[6].dis_col_sel invalidate in_uops[6].iw_p3_bypass_hint invalidate in_uops[6].iw_p2_bypass_hint invalidate in_uops[6].iw_p1_bypass_hint invalidate in_uops[6].iw_p2_speculative_child invalidate in_uops[6].iw_p1_speculative_child invalidate in_uops[6].iw_issued_partial_dgen invalidate in_uops[6].iw_issued_partial_agen invalidate in_uops[6].iw_issued invalidate in_uops[6].fu_code[0] invalidate in_uops[6].fu_code[1] invalidate in_uops[6].fu_code[2] invalidate in_uops[6].fu_code[3] invalidate in_uops[6].fu_code[4] invalidate in_uops[6].fu_code[5] invalidate in_uops[6].fu_code[6] invalidate in_uops[6].fu_code[7] invalidate in_uops[6].fu_code[8] invalidate in_uops[6].fu_code[9] invalidate in_uops[6].iq_type[0] invalidate in_uops[6].iq_type[1] invalidate in_uops[6].iq_type[2] invalidate in_uops[6].iq_type[3] invalidate in_uops[6].debug_pc invalidate in_uops[6].is_rvc invalidate in_uops[6].debug_inst invalidate in_uops[6].inst node _in_mask_6_T = bits(io.enq.bits.mask, 6, 6) node _in_mask_6_T_1 = and(io.enq.valid, _in_mask_6_T) connect in_mask[6], _in_mask_6_T_1 connect in_uops[6].edge_inst, UInt<1>(0h0) connect in_uops[6].debug_pc, pc_6 connect in_uops[6].pc_lob, pc_6 node _in_uops_6_is_sfb_T = or(io.enq.bits.sfbs[6], io.enq.bits.shadowed_mask[6]) connect in_uops[6].is_sfb, _in_uops_6_is_sfb_T connect in_uops[6].ftq_idx, io.enq.bits.ftq_idx connect in_uops[6].inst, io.enq.bits.exp_insts[6] connect in_uops[6].debug_inst, io.enq.bits.insts[6] node _in_uops_6_is_rvc_T = bits(io.enq.bits.insts[6], 1, 0) node _in_uops_6_is_rvc_T_1 = neq(_in_uops_6_is_rvc_T, UInt<2>(0h3)) connect in_uops[6].is_rvc, _in_uops_6_is_rvc_T_1 node _in_uops_6_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h6)) node _in_uops_6_taken_T_1 = and(_in_uops_6_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[6].taken, _in_uops_6_taken_T_1 connect in_uops[6].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[6].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[6].bp_debug_if, io.enq.bits.bp_debug_if_oh[6] connect in_uops[6].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[6] connect in_uops[6].debug_fsrc, io.enq.bits.fsrc node _pc_T_28 = not(io.enq.bits.pc) node _pc_T_29 = or(_pc_T_28, UInt<3>(0h7)) node _pc_T_30 = not(_pc_T_29) node _pc_T_31 = add(_pc_T_30, UInt<4>(0he)) node pc_7 = tail(_pc_T_31, 1) invalidate in_uops[7].debug_tsrc invalidate in_uops[7].debug_fsrc invalidate in_uops[7].bp_xcpt_if invalidate in_uops[7].bp_debug_if invalidate in_uops[7].xcpt_ma_if invalidate in_uops[7].xcpt_ae_if invalidate in_uops[7].xcpt_pf_if invalidate in_uops[7].fp_typ invalidate in_uops[7].fp_rm invalidate in_uops[7].fp_val invalidate in_uops[7].fcn_op invalidate in_uops[7].fcn_dw invalidate in_uops[7].frs3_en invalidate in_uops[7].lrs2_rtype invalidate in_uops[7].lrs1_rtype invalidate in_uops[7].dst_rtype invalidate in_uops[7].lrs3 invalidate in_uops[7].lrs2 invalidate in_uops[7].lrs1 invalidate in_uops[7].ldst invalidate in_uops[7].ldst_is_rs1 invalidate in_uops[7].csr_cmd invalidate in_uops[7].flush_on_commit invalidate in_uops[7].is_unique invalidate in_uops[7].uses_stq invalidate in_uops[7].uses_ldq invalidate in_uops[7].mem_signed invalidate in_uops[7].mem_size invalidate in_uops[7].mem_cmd invalidate in_uops[7].exc_cause invalidate in_uops[7].exception invalidate in_uops[7].stale_pdst invalidate in_uops[7].ppred_busy invalidate in_uops[7].prs3_busy invalidate in_uops[7].prs2_busy invalidate in_uops[7].prs1_busy invalidate in_uops[7].ppred invalidate in_uops[7].prs3 invalidate in_uops[7].prs2 invalidate in_uops[7].prs1 invalidate in_uops[7].pdst invalidate in_uops[7].rxq_idx invalidate in_uops[7].stq_idx invalidate in_uops[7].ldq_idx invalidate in_uops[7].rob_idx invalidate in_uops[7].fp_ctrl.vec invalidate in_uops[7].fp_ctrl.wflags invalidate in_uops[7].fp_ctrl.sqrt invalidate in_uops[7].fp_ctrl.div invalidate in_uops[7].fp_ctrl.fma invalidate in_uops[7].fp_ctrl.fastpipe invalidate in_uops[7].fp_ctrl.toint invalidate in_uops[7].fp_ctrl.fromint invalidate in_uops[7].fp_ctrl.typeTagOut invalidate in_uops[7].fp_ctrl.typeTagIn invalidate in_uops[7].fp_ctrl.swap23 invalidate in_uops[7].fp_ctrl.swap12 invalidate in_uops[7].fp_ctrl.ren3 invalidate in_uops[7].fp_ctrl.ren2 invalidate in_uops[7].fp_ctrl.ren1 invalidate in_uops[7].fp_ctrl.wen invalidate in_uops[7].fp_ctrl.ldst invalidate in_uops[7].op2_sel invalidate in_uops[7].op1_sel invalidate in_uops[7].imm_packed invalidate in_uops[7].pimm invalidate in_uops[7].imm_sel invalidate in_uops[7].imm_rename invalidate in_uops[7].taken invalidate in_uops[7].pc_lob invalidate in_uops[7].edge_inst invalidate in_uops[7].ftq_idx invalidate in_uops[7].is_mov invalidate in_uops[7].is_rocc invalidate in_uops[7].is_sys_pc2epc invalidate in_uops[7].is_eret invalidate in_uops[7].is_amo invalidate in_uops[7].is_sfence invalidate in_uops[7].is_fencei invalidate in_uops[7].is_fence invalidate in_uops[7].is_sfb invalidate in_uops[7].br_type invalidate in_uops[7].br_tag invalidate in_uops[7].br_mask invalidate in_uops[7].dis_col_sel invalidate in_uops[7].iw_p3_bypass_hint invalidate in_uops[7].iw_p2_bypass_hint invalidate in_uops[7].iw_p1_bypass_hint invalidate in_uops[7].iw_p2_speculative_child invalidate in_uops[7].iw_p1_speculative_child invalidate in_uops[7].iw_issued_partial_dgen invalidate in_uops[7].iw_issued_partial_agen invalidate in_uops[7].iw_issued invalidate in_uops[7].fu_code[0] invalidate in_uops[7].fu_code[1] invalidate in_uops[7].fu_code[2] invalidate in_uops[7].fu_code[3] invalidate in_uops[7].fu_code[4] invalidate in_uops[7].fu_code[5] invalidate in_uops[7].fu_code[6] invalidate in_uops[7].fu_code[7] invalidate in_uops[7].fu_code[8] invalidate in_uops[7].fu_code[9] invalidate in_uops[7].iq_type[0] invalidate in_uops[7].iq_type[1] invalidate in_uops[7].iq_type[2] invalidate in_uops[7].iq_type[3] invalidate in_uops[7].debug_pc invalidate in_uops[7].is_rvc invalidate in_uops[7].debug_inst invalidate in_uops[7].inst node _in_mask_7_T = bits(io.enq.bits.mask, 7, 7) node _in_mask_7_T_1 = and(io.enq.valid, _in_mask_7_T) connect in_mask[7], _in_mask_7_T_1 connect in_uops[7].edge_inst, UInt<1>(0h0) connect in_uops[7].debug_pc, pc_7 connect in_uops[7].pc_lob, pc_7 node _in_uops_7_is_sfb_T = or(io.enq.bits.sfbs[7], io.enq.bits.shadowed_mask[7]) connect in_uops[7].is_sfb, _in_uops_7_is_sfb_T connect in_uops[7].ftq_idx, io.enq.bits.ftq_idx connect in_uops[7].inst, io.enq.bits.exp_insts[7] connect in_uops[7].debug_inst, io.enq.bits.insts[7] node _in_uops_7_is_rvc_T = bits(io.enq.bits.insts[7], 1, 0) node _in_uops_7_is_rvc_T_1 = neq(_in_uops_7_is_rvc_T, UInt<2>(0h3)) connect in_uops[7].is_rvc, _in_uops_7_is_rvc_T_1 node _in_uops_7_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h7)) node _in_uops_7_taken_T_1 = and(_in_uops_7_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[7].taken, _in_uops_7_taken_T_1 connect in_uops[7].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[7].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[7].bp_debug_if, io.enq.bits.bp_debug_if_oh[7] connect in_uops[7].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[7] connect in_uops[7].debug_fsrc, io.enq.bits.fsrc wire enq_idxs : UInt<24>[8] connect enq_idxs[0], tail node _T = bits(tail, 22, 0) node _T_1 = bits(tail, 23, 23) node _T_2 = cat(_T, _T_1) node _T_3 = mux(in_mask[0], _T_2, tail) connect enq_idxs[1], _T_3 node _T_4 = bits(_T_3, 22, 0) node _T_5 = bits(_T_3, 23, 23) node _T_6 = cat(_T_4, _T_5) node _T_7 = mux(in_mask[1], _T_6, _T_3) connect enq_idxs[2], _T_7 node _T_8 = bits(_T_7, 22, 0) node _T_9 = bits(_T_7, 23, 23) node _T_10 = cat(_T_8, _T_9) node _T_11 = mux(in_mask[2], _T_10, _T_7) connect enq_idxs[3], _T_11 node _T_12 = bits(_T_11, 22, 0) node _T_13 = bits(_T_11, 23, 23) node _T_14 = cat(_T_12, _T_13) node _T_15 = mux(in_mask[3], _T_14, _T_11) connect enq_idxs[4], _T_15 node _T_16 = bits(_T_15, 22, 0) node _T_17 = bits(_T_15, 23, 23) node _T_18 = cat(_T_16, _T_17) node _T_19 = mux(in_mask[4], _T_18, _T_15) connect enq_idxs[5], _T_19 node _T_20 = bits(_T_19, 22, 0) node _T_21 = bits(_T_19, 23, 23) node _T_22 = cat(_T_20, _T_21) node _T_23 = mux(in_mask[5], _T_22, _T_19) connect enq_idxs[6], _T_23 node _T_24 = bits(_T_23, 22, 0) node _T_25 = bits(_T_23, 23, 23) node _T_26 = cat(_T_24, _T_25) node _T_27 = mux(in_mask[6], _T_26, _T_23) connect enq_idxs[7], _T_27 node _T_28 = bits(_T_27, 22, 0) node _T_29 = bits(_T_27, 23, 23) node _T_30 = cat(_T_28, _T_29) node _T_31 = mux(in_mask[7], _T_30, _T_27) node _T_32 = and(do_enq, in_mask[0]) node _T_33 = bits(enq_idxs[0], 0, 0) node _T_34 = and(_T_32, _T_33) when _T_34 : connect fb_uop_ram[0], in_uops[0] node _T_35 = and(do_enq, in_mask[0]) node _T_36 = bits(enq_idxs[0], 1, 1) node _T_37 = and(_T_35, _T_36) when _T_37 : connect fb_uop_ram[1], in_uops[0] node _T_38 = and(do_enq, in_mask[0]) node _T_39 = bits(enq_idxs[0], 2, 2) node _T_40 = and(_T_38, _T_39) when _T_40 : connect fb_uop_ram[2], in_uops[0] node _T_41 = and(do_enq, in_mask[0]) node _T_42 = bits(enq_idxs[0], 3, 3) node _T_43 = and(_T_41, _T_42) when _T_43 : connect fb_uop_ram[3], in_uops[0] node _T_44 = and(do_enq, in_mask[0]) node _T_45 = bits(enq_idxs[0], 4, 4) node _T_46 = and(_T_44, _T_45) when _T_46 : connect fb_uop_ram[4], in_uops[0] node _T_47 = and(do_enq, in_mask[0]) node _T_48 = bits(enq_idxs[0], 5, 5) node _T_49 = and(_T_47, _T_48) when _T_49 : connect fb_uop_ram[5], in_uops[0] node _T_50 = and(do_enq, in_mask[0]) node _T_51 = bits(enq_idxs[0], 6, 6) node _T_52 = and(_T_50, _T_51) when _T_52 : connect fb_uop_ram[6], in_uops[0] node _T_53 = and(do_enq, in_mask[0]) node _T_54 = bits(enq_idxs[0], 7, 7) node _T_55 = and(_T_53, _T_54) when _T_55 : connect fb_uop_ram[7], in_uops[0] node _T_56 = and(do_enq, in_mask[0]) node _T_57 = bits(enq_idxs[0], 8, 8) node _T_58 = and(_T_56, _T_57) when _T_58 : connect fb_uop_ram[8], in_uops[0] node _T_59 = and(do_enq, in_mask[0]) node _T_60 = bits(enq_idxs[0], 9, 9) node _T_61 = and(_T_59, _T_60) when _T_61 : connect fb_uop_ram[9], in_uops[0] node _T_62 = and(do_enq, in_mask[0]) node _T_63 = bits(enq_idxs[0], 10, 10) node _T_64 = and(_T_62, _T_63) when _T_64 : connect fb_uop_ram[10], in_uops[0] node _T_65 = and(do_enq, in_mask[0]) node _T_66 = bits(enq_idxs[0], 11, 11) node _T_67 = and(_T_65, _T_66) when _T_67 : connect fb_uop_ram[11], in_uops[0] node _T_68 = and(do_enq, in_mask[0]) node _T_69 = bits(enq_idxs[0], 12, 12) node _T_70 = and(_T_68, _T_69) when _T_70 : connect fb_uop_ram[12], in_uops[0] node _T_71 = and(do_enq, in_mask[0]) node _T_72 = bits(enq_idxs[0], 13, 13) node _T_73 = and(_T_71, _T_72) when _T_73 : connect fb_uop_ram[13], in_uops[0] node _T_74 = and(do_enq, in_mask[0]) node _T_75 = bits(enq_idxs[0], 14, 14) node _T_76 = and(_T_74, _T_75) when _T_76 : connect fb_uop_ram[14], in_uops[0] node _T_77 = and(do_enq, in_mask[0]) node _T_78 = bits(enq_idxs[0], 15, 15) node _T_79 = and(_T_77, _T_78) when _T_79 : connect fb_uop_ram[15], in_uops[0] node _T_80 = and(do_enq, in_mask[0]) node _T_81 = bits(enq_idxs[0], 16, 16) node _T_82 = and(_T_80, _T_81) when _T_82 : connect fb_uop_ram[16], in_uops[0] node _T_83 = and(do_enq, in_mask[0]) node _T_84 = bits(enq_idxs[0], 17, 17) node _T_85 = and(_T_83, _T_84) when _T_85 : connect fb_uop_ram[17], in_uops[0] node _T_86 = and(do_enq, in_mask[0]) node _T_87 = bits(enq_idxs[0], 18, 18) node _T_88 = and(_T_86, _T_87) when _T_88 : connect fb_uop_ram[18], in_uops[0] node _T_89 = and(do_enq, in_mask[0]) node _T_90 = bits(enq_idxs[0], 19, 19) node _T_91 = and(_T_89, _T_90) when _T_91 : connect fb_uop_ram[19], in_uops[0] node _T_92 = and(do_enq, in_mask[0]) node _T_93 = bits(enq_idxs[0], 20, 20) node _T_94 = and(_T_92, _T_93) when _T_94 : connect fb_uop_ram[20], in_uops[0] node _T_95 = and(do_enq, in_mask[0]) node _T_96 = bits(enq_idxs[0], 21, 21) node _T_97 = and(_T_95, _T_96) when _T_97 : connect fb_uop_ram[21], in_uops[0] node _T_98 = and(do_enq, in_mask[0]) node _T_99 = bits(enq_idxs[0], 22, 22) node _T_100 = and(_T_98, _T_99) when _T_100 : connect fb_uop_ram[22], in_uops[0] node _T_101 = and(do_enq, in_mask[0]) node _T_102 = bits(enq_idxs[0], 23, 23) node _T_103 = and(_T_101, _T_102) when _T_103 : connect fb_uop_ram[23], in_uops[0] node _T_104 = and(do_enq, in_mask[1]) node _T_105 = bits(enq_idxs[1], 0, 0) node _T_106 = and(_T_104, _T_105) when _T_106 : connect fb_uop_ram[0], in_uops[1] node _T_107 = and(do_enq, in_mask[1]) node _T_108 = bits(enq_idxs[1], 1, 1) node _T_109 = and(_T_107, _T_108) when _T_109 : connect fb_uop_ram[1], in_uops[1] node _T_110 = and(do_enq, in_mask[1]) node _T_111 = bits(enq_idxs[1], 2, 2) node _T_112 = and(_T_110, _T_111) when _T_112 : connect fb_uop_ram[2], in_uops[1] node _T_113 = and(do_enq, in_mask[1]) node _T_114 = bits(enq_idxs[1], 3, 3) node _T_115 = and(_T_113, _T_114) when _T_115 : connect fb_uop_ram[3], in_uops[1] node _T_116 = and(do_enq, in_mask[1]) node _T_117 = bits(enq_idxs[1], 4, 4) node _T_118 = and(_T_116, _T_117) when _T_118 : connect fb_uop_ram[4], in_uops[1] node _T_119 = and(do_enq, in_mask[1]) node _T_120 = bits(enq_idxs[1], 5, 5) node _T_121 = and(_T_119, _T_120) when _T_121 : connect fb_uop_ram[5], in_uops[1] node _T_122 = and(do_enq, in_mask[1]) node _T_123 = bits(enq_idxs[1], 6, 6) node _T_124 = and(_T_122, _T_123) when _T_124 : connect fb_uop_ram[6], in_uops[1] node _T_125 = and(do_enq, in_mask[1]) node _T_126 = bits(enq_idxs[1], 7, 7) node _T_127 = and(_T_125, _T_126) when _T_127 : connect fb_uop_ram[7], in_uops[1] node _T_128 = and(do_enq, in_mask[1]) node _T_129 = bits(enq_idxs[1], 8, 8) node _T_130 = and(_T_128, _T_129) when _T_130 : connect fb_uop_ram[8], in_uops[1] node _T_131 = and(do_enq, in_mask[1]) node _T_132 = bits(enq_idxs[1], 9, 9) node _T_133 = and(_T_131, _T_132) when _T_133 : connect fb_uop_ram[9], in_uops[1] node _T_134 = and(do_enq, in_mask[1]) node _T_135 = bits(enq_idxs[1], 10, 10) node _T_136 = and(_T_134, _T_135) when _T_136 : connect fb_uop_ram[10], in_uops[1] node _T_137 = and(do_enq, in_mask[1]) node _T_138 = bits(enq_idxs[1], 11, 11) node _T_139 = and(_T_137, _T_138) when _T_139 : connect fb_uop_ram[11], in_uops[1] node _T_140 = and(do_enq, in_mask[1]) node _T_141 = bits(enq_idxs[1], 12, 12) node _T_142 = and(_T_140, _T_141) when _T_142 : connect fb_uop_ram[12], in_uops[1] node _T_143 = and(do_enq, in_mask[1]) node _T_144 = bits(enq_idxs[1], 13, 13) node _T_145 = and(_T_143, _T_144) when _T_145 : connect fb_uop_ram[13], in_uops[1] node _T_146 = and(do_enq, in_mask[1]) node _T_147 = bits(enq_idxs[1], 14, 14) node _T_148 = and(_T_146, _T_147) when _T_148 : connect fb_uop_ram[14], in_uops[1] node _T_149 = and(do_enq, in_mask[1]) node _T_150 = bits(enq_idxs[1], 15, 15) node _T_151 = and(_T_149, _T_150) when _T_151 : connect fb_uop_ram[15], in_uops[1] node _T_152 = and(do_enq, in_mask[1]) node _T_153 = bits(enq_idxs[1], 16, 16) node _T_154 = and(_T_152, _T_153) when _T_154 : connect fb_uop_ram[16], in_uops[1] node _T_155 = and(do_enq, in_mask[1]) node _T_156 = bits(enq_idxs[1], 17, 17) node _T_157 = and(_T_155, _T_156) when _T_157 : connect fb_uop_ram[17], in_uops[1] node _T_158 = and(do_enq, in_mask[1]) node _T_159 = bits(enq_idxs[1], 18, 18) node _T_160 = and(_T_158, _T_159) when _T_160 : connect fb_uop_ram[18], in_uops[1] node _T_161 = and(do_enq, in_mask[1]) node _T_162 = bits(enq_idxs[1], 19, 19) node _T_163 = and(_T_161, _T_162) when _T_163 : connect fb_uop_ram[19], in_uops[1] node _T_164 = and(do_enq, in_mask[1]) node _T_165 = bits(enq_idxs[1], 20, 20) node _T_166 = and(_T_164, _T_165) when _T_166 : connect fb_uop_ram[20], in_uops[1] node _T_167 = and(do_enq, in_mask[1]) node _T_168 = bits(enq_idxs[1], 21, 21) node _T_169 = and(_T_167, _T_168) when _T_169 : connect fb_uop_ram[21], in_uops[1] node _T_170 = and(do_enq, in_mask[1]) node _T_171 = bits(enq_idxs[1], 22, 22) node _T_172 = and(_T_170, _T_171) when _T_172 : connect fb_uop_ram[22], in_uops[1] node _T_173 = and(do_enq, in_mask[1]) node _T_174 = bits(enq_idxs[1], 23, 23) node _T_175 = and(_T_173, _T_174) when _T_175 : connect fb_uop_ram[23], in_uops[1] node _T_176 = and(do_enq, in_mask[2]) node _T_177 = bits(enq_idxs[2], 0, 0) node _T_178 = and(_T_176, _T_177) when _T_178 : connect fb_uop_ram[0], in_uops[2] node _T_179 = and(do_enq, in_mask[2]) node _T_180 = bits(enq_idxs[2], 1, 1) node _T_181 = and(_T_179, _T_180) when _T_181 : connect fb_uop_ram[1], in_uops[2] node _T_182 = and(do_enq, in_mask[2]) node _T_183 = bits(enq_idxs[2], 2, 2) node _T_184 = and(_T_182, _T_183) when _T_184 : connect fb_uop_ram[2], in_uops[2] node _T_185 = and(do_enq, in_mask[2]) node _T_186 = bits(enq_idxs[2], 3, 3) node _T_187 = and(_T_185, _T_186) when _T_187 : connect fb_uop_ram[3], in_uops[2] node _T_188 = and(do_enq, in_mask[2]) node _T_189 = bits(enq_idxs[2], 4, 4) node _T_190 = and(_T_188, _T_189) when _T_190 : connect fb_uop_ram[4], in_uops[2] node _T_191 = and(do_enq, in_mask[2]) node _T_192 = bits(enq_idxs[2], 5, 5) node _T_193 = and(_T_191, _T_192) when _T_193 : connect fb_uop_ram[5], in_uops[2] node _T_194 = and(do_enq, in_mask[2]) node _T_195 = bits(enq_idxs[2], 6, 6) node _T_196 = and(_T_194, _T_195) when _T_196 : connect fb_uop_ram[6], in_uops[2] node _T_197 = and(do_enq, in_mask[2]) node _T_198 = bits(enq_idxs[2], 7, 7) node _T_199 = and(_T_197, _T_198) when _T_199 : connect fb_uop_ram[7], in_uops[2] node _T_200 = and(do_enq, in_mask[2]) node _T_201 = bits(enq_idxs[2], 8, 8) node _T_202 = and(_T_200, _T_201) when _T_202 : connect fb_uop_ram[8], in_uops[2] node _T_203 = and(do_enq, in_mask[2]) node _T_204 = bits(enq_idxs[2], 9, 9) node _T_205 = and(_T_203, _T_204) when _T_205 : connect fb_uop_ram[9], in_uops[2] node _T_206 = and(do_enq, in_mask[2]) node _T_207 = bits(enq_idxs[2], 10, 10) node _T_208 = and(_T_206, _T_207) when _T_208 : connect fb_uop_ram[10], in_uops[2] node _T_209 = and(do_enq, in_mask[2]) node _T_210 = bits(enq_idxs[2], 11, 11) node _T_211 = and(_T_209, _T_210) when _T_211 : connect fb_uop_ram[11], in_uops[2] node _T_212 = and(do_enq, in_mask[2]) node _T_213 = bits(enq_idxs[2], 12, 12) node _T_214 = and(_T_212, _T_213) when _T_214 : connect fb_uop_ram[12], in_uops[2] node _T_215 = and(do_enq, in_mask[2]) node _T_216 = bits(enq_idxs[2], 13, 13) node _T_217 = and(_T_215, _T_216) when _T_217 : connect fb_uop_ram[13], in_uops[2] node _T_218 = and(do_enq, in_mask[2]) node _T_219 = bits(enq_idxs[2], 14, 14) node _T_220 = and(_T_218, _T_219) when _T_220 : connect fb_uop_ram[14], in_uops[2] node _T_221 = and(do_enq, in_mask[2]) node _T_222 = bits(enq_idxs[2], 15, 15) node _T_223 = and(_T_221, _T_222) when _T_223 : connect fb_uop_ram[15], in_uops[2] node _T_224 = and(do_enq, in_mask[2]) node _T_225 = bits(enq_idxs[2], 16, 16) node _T_226 = and(_T_224, _T_225) when _T_226 : connect fb_uop_ram[16], in_uops[2] node _T_227 = and(do_enq, in_mask[2]) node _T_228 = bits(enq_idxs[2], 17, 17) node _T_229 = and(_T_227, _T_228) when _T_229 : connect fb_uop_ram[17], in_uops[2] node _T_230 = and(do_enq, in_mask[2]) node _T_231 = bits(enq_idxs[2], 18, 18) node _T_232 = and(_T_230, _T_231) when _T_232 : connect fb_uop_ram[18], in_uops[2] node _T_233 = and(do_enq, in_mask[2]) node _T_234 = bits(enq_idxs[2], 19, 19) node _T_235 = and(_T_233, _T_234) when _T_235 : connect fb_uop_ram[19], in_uops[2] node _T_236 = and(do_enq, in_mask[2]) node _T_237 = bits(enq_idxs[2], 20, 20) node _T_238 = and(_T_236, _T_237) when _T_238 : connect fb_uop_ram[20], in_uops[2] node _T_239 = and(do_enq, in_mask[2]) node _T_240 = bits(enq_idxs[2], 21, 21) node _T_241 = and(_T_239, _T_240) when _T_241 : connect fb_uop_ram[21], in_uops[2] node _T_242 = and(do_enq, in_mask[2]) node _T_243 = bits(enq_idxs[2], 22, 22) node _T_244 = and(_T_242, _T_243) when _T_244 : connect fb_uop_ram[22], in_uops[2] node _T_245 = and(do_enq, in_mask[2]) node _T_246 = bits(enq_idxs[2], 23, 23) node _T_247 = and(_T_245, _T_246) when _T_247 : connect fb_uop_ram[23], in_uops[2] node _T_248 = and(do_enq, in_mask[3]) node _T_249 = bits(enq_idxs[3], 0, 0) node _T_250 = and(_T_248, _T_249) when _T_250 : connect fb_uop_ram[0], in_uops[3] node _T_251 = and(do_enq, in_mask[3]) node _T_252 = bits(enq_idxs[3], 1, 1) node _T_253 = and(_T_251, _T_252) when _T_253 : connect fb_uop_ram[1], in_uops[3] node _T_254 = and(do_enq, in_mask[3]) node _T_255 = bits(enq_idxs[3], 2, 2) node _T_256 = and(_T_254, _T_255) when _T_256 : connect fb_uop_ram[2], in_uops[3] node _T_257 = and(do_enq, in_mask[3]) node _T_258 = bits(enq_idxs[3], 3, 3) node _T_259 = and(_T_257, _T_258) when _T_259 : connect fb_uop_ram[3], in_uops[3] node _T_260 = and(do_enq, in_mask[3]) node _T_261 = bits(enq_idxs[3], 4, 4) node _T_262 = and(_T_260, _T_261) when _T_262 : connect fb_uop_ram[4], in_uops[3] node _T_263 = and(do_enq, in_mask[3]) node _T_264 = bits(enq_idxs[3], 5, 5) node _T_265 = and(_T_263, _T_264) when _T_265 : connect fb_uop_ram[5], in_uops[3] node _T_266 = and(do_enq, in_mask[3]) node _T_267 = bits(enq_idxs[3], 6, 6) node _T_268 = and(_T_266, _T_267) when _T_268 : connect fb_uop_ram[6], in_uops[3] node _T_269 = and(do_enq, in_mask[3]) node _T_270 = bits(enq_idxs[3], 7, 7) node _T_271 = and(_T_269, _T_270) when _T_271 : connect fb_uop_ram[7], in_uops[3] node _T_272 = and(do_enq, in_mask[3]) node _T_273 = bits(enq_idxs[3], 8, 8) node _T_274 = and(_T_272, _T_273) when _T_274 : connect fb_uop_ram[8], in_uops[3] node _T_275 = and(do_enq, in_mask[3]) node _T_276 = bits(enq_idxs[3], 9, 9) node _T_277 = and(_T_275, _T_276) when _T_277 : connect fb_uop_ram[9], in_uops[3] node _T_278 = and(do_enq, in_mask[3]) node _T_279 = bits(enq_idxs[3], 10, 10) node _T_280 = and(_T_278, _T_279) when _T_280 : connect fb_uop_ram[10], in_uops[3] node _T_281 = and(do_enq, in_mask[3]) node _T_282 = bits(enq_idxs[3], 11, 11) node _T_283 = and(_T_281, _T_282) when _T_283 : connect fb_uop_ram[11], in_uops[3] node _T_284 = and(do_enq, in_mask[3]) node _T_285 = bits(enq_idxs[3], 12, 12) node _T_286 = and(_T_284, _T_285) when _T_286 : connect fb_uop_ram[12], in_uops[3] node _T_287 = and(do_enq, in_mask[3]) node _T_288 = bits(enq_idxs[3], 13, 13) node _T_289 = and(_T_287, _T_288) when _T_289 : connect fb_uop_ram[13], in_uops[3] node _T_290 = and(do_enq, in_mask[3]) node _T_291 = bits(enq_idxs[3], 14, 14) node _T_292 = and(_T_290, _T_291) when _T_292 : connect fb_uop_ram[14], in_uops[3] node _T_293 = and(do_enq, in_mask[3]) node _T_294 = bits(enq_idxs[3], 15, 15) node _T_295 = and(_T_293, _T_294) when _T_295 : connect fb_uop_ram[15], in_uops[3] node _T_296 = and(do_enq, in_mask[3]) node _T_297 = bits(enq_idxs[3], 16, 16) node _T_298 = and(_T_296, _T_297) when _T_298 : connect fb_uop_ram[16], in_uops[3] node _T_299 = and(do_enq, in_mask[3]) node _T_300 = bits(enq_idxs[3], 17, 17) node _T_301 = and(_T_299, _T_300) when _T_301 : connect fb_uop_ram[17], in_uops[3] node _T_302 = and(do_enq, in_mask[3]) node _T_303 = bits(enq_idxs[3], 18, 18) node _T_304 = and(_T_302, _T_303) when _T_304 : connect fb_uop_ram[18], in_uops[3] node _T_305 = and(do_enq, in_mask[3]) node _T_306 = bits(enq_idxs[3], 19, 19) node _T_307 = and(_T_305, _T_306) when _T_307 : connect fb_uop_ram[19], in_uops[3] node _T_308 = and(do_enq, in_mask[3]) node _T_309 = bits(enq_idxs[3], 20, 20) node _T_310 = and(_T_308, _T_309) when _T_310 : connect fb_uop_ram[20], in_uops[3] node _T_311 = and(do_enq, in_mask[3]) node _T_312 = bits(enq_idxs[3], 21, 21) node _T_313 = and(_T_311, _T_312) when _T_313 : connect fb_uop_ram[21], in_uops[3] node _T_314 = and(do_enq, in_mask[3]) node _T_315 = bits(enq_idxs[3], 22, 22) node _T_316 = and(_T_314, _T_315) when _T_316 : connect fb_uop_ram[22], in_uops[3] node _T_317 = and(do_enq, in_mask[3]) node _T_318 = bits(enq_idxs[3], 23, 23) node _T_319 = and(_T_317, _T_318) when _T_319 : connect fb_uop_ram[23], in_uops[3] node _T_320 = and(do_enq, in_mask[4]) node _T_321 = bits(enq_idxs[4], 0, 0) node _T_322 = and(_T_320, _T_321) when _T_322 : connect fb_uop_ram[0], in_uops[4] node _T_323 = and(do_enq, in_mask[4]) node _T_324 = bits(enq_idxs[4], 1, 1) node _T_325 = and(_T_323, _T_324) when _T_325 : connect fb_uop_ram[1], in_uops[4] node _T_326 = and(do_enq, in_mask[4]) node _T_327 = bits(enq_idxs[4], 2, 2) node _T_328 = and(_T_326, _T_327) when _T_328 : connect fb_uop_ram[2], in_uops[4] node _T_329 = and(do_enq, in_mask[4]) node _T_330 = bits(enq_idxs[4], 3, 3) node _T_331 = and(_T_329, _T_330) when _T_331 : connect fb_uop_ram[3], in_uops[4] node _T_332 = and(do_enq, in_mask[4]) node _T_333 = bits(enq_idxs[4], 4, 4) node _T_334 = and(_T_332, _T_333) when _T_334 : connect fb_uop_ram[4], in_uops[4] node _T_335 = and(do_enq, in_mask[4]) node _T_336 = bits(enq_idxs[4], 5, 5) node _T_337 = and(_T_335, _T_336) when _T_337 : connect fb_uop_ram[5], in_uops[4] node _T_338 = and(do_enq, in_mask[4]) node _T_339 = bits(enq_idxs[4], 6, 6) node _T_340 = and(_T_338, _T_339) when _T_340 : connect fb_uop_ram[6], in_uops[4] node _T_341 = and(do_enq, in_mask[4]) node _T_342 = bits(enq_idxs[4], 7, 7) node _T_343 = and(_T_341, _T_342) when _T_343 : connect fb_uop_ram[7], in_uops[4] node _T_344 = and(do_enq, in_mask[4]) node _T_345 = bits(enq_idxs[4], 8, 8) node _T_346 = and(_T_344, _T_345) when _T_346 : connect fb_uop_ram[8], in_uops[4] node _T_347 = and(do_enq, in_mask[4]) node _T_348 = bits(enq_idxs[4], 9, 9) node _T_349 = and(_T_347, _T_348) when _T_349 : connect fb_uop_ram[9], in_uops[4] node _T_350 = and(do_enq, in_mask[4]) node _T_351 = bits(enq_idxs[4], 10, 10) node _T_352 = and(_T_350, _T_351) when _T_352 : connect fb_uop_ram[10], in_uops[4] node _T_353 = and(do_enq, in_mask[4]) node _T_354 = bits(enq_idxs[4], 11, 11) node _T_355 = and(_T_353, _T_354) when _T_355 : connect fb_uop_ram[11], in_uops[4] node _T_356 = and(do_enq, in_mask[4]) node _T_357 = bits(enq_idxs[4], 12, 12) node _T_358 = and(_T_356, _T_357) when _T_358 : connect fb_uop_ram[12], in_uops[4] node _T_359 = and(do_enq, in_mask[4]) node _T_360 = bits(enq_idxs[4], 13, 13) node _T_361 = and(_T_359, _T_360) when _T_361 : connect fb_uop_ram[13], in_uops[4] node _T_362 = and(do_enq, in_mask[4]) node _T_363 = bits(enq_idxs[4], 14, 14) node _T_364 = and(_T_362, _T_363) when _T_364 : connect fb_uop_ram[14], in_uops[4] node _T_365 = and(do_enq, in_mask[4]) node _T_366 = bits(enq_idxs[4], 15, 15) node _T_367 = and(_T_365, _T_366) when _T_367 : connect fb_uop_ram[15], in_uops[4] node _T_368 = and(do_enq, in_mask[4]) node _T_369 = bits(enq_idxs[4], 16, 16) node _T_370 = and(_T_368, _T_369) when _T_370 : connect fb_uop_ram[16], in_uops[4] node _T_371 = and(do_enq, in_mask[4]) node _T_372 = bits(enq_idxs[4], 17, 17) node _T_373 = and(_T_371, _T_372) when _T_373 : connect fb_uop_ram[17], in_uops[4] node _T_374 = and(do_enq, in_mask[4]) node _T_375 = bits(enq_idxs[4], 18, 18) node _T_376 = and(_T_374, _T_375) when _T_376 : connect fb_uop_ram[18], in_uops[4] node _T_377 = and(do_enq, in_mask[4]) node _T_378 = bits(enq_idxs[4], 19, 19) node _T_379 = and(_T_377, _T_378) when _T_379 : connect fb_uop_ram[19], in_uops[4] node _T_380 = and(do_enq, in_mask[4]) node _T_381 = bits(enq_idxs[4], 20, 20) node _T_382 = and(_T_380, _T_381) when _T_382 : connect fb_uop_ram[20], in_uops[4] node _T_383 = and(do_enq, in_mask[4]) node _T_384 = bits(enq_idxs[4], 21, 21) node _T_385 = and(_T_383, _T_384) when _T_385 : connect fb_uop_ram[21], in_uops[4] node _T_386 = and(do_enq, in_mask[4]) node _T_387 = bits(enq_idxs[4], 22, 22) node _T_388 = and(_T_386, _T_387) when _T_388 : connect fb_uop_ram[22], in_uops[4] node _T_389 = and(do_enq, in_mask[4]) node _T_390 = bits(enq_idxs[4], 23, 23) node _T_391 = and(_T_389, _T_390) when _T_391 : connect fb_uop_ram[23], in_uops[4] node _T_392 = and(do_enq, in_mask[5]) node _T_393 = bits(enq_idxs[5], 0, 0) node _T_394 = and(_T_392, _T_393) when _T_394 : connect fb_uop_ram[0], in_uops[5] node _T_395 = and(do_enq, in_mask[5]) node _T_396 = bits(enq_idxs[5], 1, 1) node _T_397 = and(_T_395, _T_396) when _T_397 : connect fb_uop_ram[1], in_uops[5] node _T_398 = and(do_enq, in_mask[5]) node _T_399 = bits(enq_idxs[5], 2, 2) node _T_400 = and(_T_398, _T_399) when _T_400 : connect fb_uop_ram[2], in_uops[5] node _T_401 = and(do_enq, in_mask[5]) node _T_402 = bits(enq_idxs[5], 3, 3) node _T_403 = and(_T_401, _T_402) when _T_403 : connect fb_uop_ram[3], in_uops[5] node _T_404 = and(do_enq, in_mask[5]) node _T_405 = bits(enq_idxs[5], 4, 4) node _T_406 = and(_T_404, _T_405) when _T_406 : connect fb_uop_ram[4], in_uops[5] node _T_407 = and(do_enq, in_mask[5]) node _T_408 = bits(enq_idxs[5], 5, 5) node _T_409 = and(_T_407, _T_408) when _T_409 : connect fb_uop_ram[5], in_uops[5] node _T_410 = and(do_enq, in_mask[5]) node _T_411 = bits(enq_idxs[5], 6, 6) node _T_412 = and(_T_410, _T_411) when _T_412 : connect fb_uop_ram[6], in_uops[5] node _T_413 = and(do_enq, in_mask[5]) node _T_414 = bits(enq_idxs[5], 7, 7) node _T_415 = and(_T_413, _T_414) when _T_415 : connect fb_uop_ram[7], in_uops[5] node _T_416 = and(do_enq, in_mask[5]) node _T_417 = bits(enq_idxs[5], 8, 8) node _T_418 = and(_T_416, _T_417) when _T_418 : connect fb_uop_ram[8], in_uops[5] node _T_419 = and(do_enq, in_mask[5]) node _T_420 = bits(enq_idxs[5], 9, 9) node _T_421 = and(_T_419, _T_420) when _T_421 : connect fb_uop_ram[9], in_uops[5] node _T_422 = and(do_enq, in_mask[5]) node _T_423 = bits(enq_idxs[5], 10, 10) node _T_424 = and(_T_422, _T_423) when _T_424 : connect fb_uop_ram[10], in_uops[5] node _T_425 = and(do_enq, in_mask[5]) node _T_426 = bits(enq_idxs[5], 11, 11) node _T_427 = and(_T_425, _T_426) when _T_427 : connect fb_uop_ram[11], in_uops[5] node _T_428 = and(do_enq, in_mask[5]) node _T_429 = bits(enq_idxs[5], 12, 12) node _T_430 = and(_T_428, _T_429) when _T_430 : connect fb_uop_ram[12], in_uops[5] node _T_431 = and(do_enq, in_mask[5]) node _T_432 = bits(enq_idxs[5], 13, 13) node _T_433 = and(_T_431, _T_432) when _T_433 : connect fb_uop_ram[13], in_uops[5] node _T_434 = and(do_enq, in_mask[5]) node _T_435 = bits(enq_idxs[5], 14, 14) node _T_436 = and(_T_434, _T_435) when _T_436 : connect fb_uop_ram[14], in_uops[5] node _T_437 = and(do_enq, in_mask[5]) node _T_438 = bits(enq_idxs[5], 15, 15) node _T_439 = and(_T_437, _T_438) when _T_439 : connect fb_uop_ram[15], in_uops[5] node _T_440 = and(do_enq, in_mask[5]) node _T_441 = bits(enq_idxs[5], 16, 16) node _T_442 = and(_T_440, _T_441) when _T_442 : connect fb_uop_ram[16], in_uops[5] node _T_443 = and(do_enq, in_mask[5]) node _T_444 = bits(enq_idxs[5], 17, 17) node _T_445 = and(_T_443, _T_444) when _T_445 : connect fb_uop_ram[17], in_uops[5] node _T_446 = and(do_enq, in_mask[5]) node _T_447 = bits(enq_idxs[5], 18, 18) node _T_448 = and(_T_446, _T_447) when _T_448 : connect fb_uop_ram[18], in_uops[5] node _T_449 = and(do_enq, in_mask[5]) node _T_450 = bits(enq_idxs[5], 19, 19) node _T_451 = and(_T_449, _T_450) when _T_451 : connect fb_uop_ram[19], in_uops[5] node _T_452 = and(do_enq, in_mask[5]) node _T_453 = bits(enq_idxs[5], 20, 20) node _T_454 = and(_T_452, _T_453) when _T_454 : connect fb_uop_ram[20], in_uops[5] node _T_455 = and(do_enq, in_mask[5]) node _T_456 = bits(enq_idxs[5], 21, 21) node _T_457 = and(_T_455, _T_456) when _T_457 : connect fb_uop_ram[21], in_uops[5] node _T_458 = and(do_enq, in_mask[5]) node _T_459 = bits(enq_idxs[5], 22, 22) node _T_460 = and(_T_458, _T_459) when _T_460 : connect fb_uop_ram[22], in_uops[5] node _T_461 = and(do_enq, in_mask[5]) node _T_462 = bits(enq_idxs[5], 23, 23) node _T_463 = and(_T_461, _T_462) when _T_463 : connect fb_uop_ram[23], in_uops[5] node _T_464 = and(do_enq, in_mask[6]) node _T_465 = bits(enq_idxs[6], 0, 0) node _T_466 = and(_T_464, _T_465) when _T_466 : connect fb_uop_ram[0], in_uops[6] node _T_467 = and(do_enq, in_mask[6]) node _T_468 = bits(enq_idxs[6], 1, 1) node _T_469 = and(_T_467, _T_468) when _T_469 : connect fb_uop_ram[1], in_uops[6] node _T_470 = and(do_enq, in_mask[6]) node _T_471 = bits(enq_idxs[6], 2, 2) node _T_472 = and(_T_470, _T_471) when _T_472 : connect fb_uop_ram[2], in_uops[6] node _T_473 = and(do_enq, in_mask[6]) node _T_474 = bits(enq_idxs[6], 3, 3) node _T_475 = and(_T_473, _T_474) when _T_475 : connect fb_uop_ram[3], in_uops[6] node _T_476 = and(do_enq, in_mask[6]) node _T_477 = bits(enq_idxs[6], 4, 4) node _T_478 = and(_T_476, _T_477) when _T_478 : connect fb_uop_ram[4], in_uops[6] node _T_479 = and(do_enq, in_mask[6]) node _T_480 = bits(enq_idxs[6], 5, 5) node _T_481 = and(_T_479, _T_480) when _T_481 : connect fb_uop_ram[5], in_uops[6] node _T_482 = and(do_enq, in_mask[6]) node _T_483 = bits(enq_idxs[6], 6, 6) node _T_484 = and(_T_482, _T_483) when _T_484 : connect fb_uop_ram[6], in_uops[6] node _T_485 = and(do_enq, in_mask[6]) node _T_486 = bits(enq_idxs[6], 7, 7) node _T_487 = and(_T_485, _T_486) when _T_487 : connect fb_uop_ram[7], in_uops[6] node _T_488 = and(do_enq, in_mask[6]) node _T_489 = bits(enq_idxs[6], 8, 8) node _T_490 = and(_T_488, _T_489) when _T_490 : connect fb_uop_ram[8], in_uops[6] node _T_491 = and(do_enq, in_mask[6]) node _T_492 = bits(enq_idxs[6], 9, 9) node _T_493 = and(_T_491, _T_492) when _T_493 : connect fb_uop_ram[9], in_uops[6] node _T_494 = and(do_enq, in_mask[6]) node _T_495 = bits(enq_idxs[6], 10, 10) node _T_496 = and(_T_494, _T_495) when _T_496 : connect fb_uop_ram[10], in_uops[6] node _T_497 = and(do_enq, in_mask[6]) node _T_498 = bits(enq_idxs[6], 11, 11) node _T_499 = and(_T_497, _T_498) when _T_499 : connect fb_uop_ram[11], in_uops[6] node _T_500 = and(do_enq, in_mask[6]) node _T_501 = bits(enq_idxs[6], 12, 12) node _T_502 = and(_T_500, _T_501) when _T_502 : connect fb_uop_ram[12], in_uops[6] node _T_503 = and(do_enq, in_mask[6]) node _T_504 = bits(enq_idxs[6], 13, 13) node _T_505 = and(_T_503, _T_504) when _T_505 : connect fb_uop_ram[13], in_uops[6] node _T_506 = and(do_enq, in_mask[6]) node _T_507 = bits(enq_idxs[6], 14, 14) node _T_508 = and(_T_506, _T_507) when _T_508 : connect fb_uop_ram[14], in_uops[6] node _T_509 = and(do_enq, in_mask[6]) node _T_510 = bits(enq_idxs[6], 15, 15) node _T_511 = and(_T_509, _T_510) when _T_511 : connect fb_uop_ram[15], in_uops[6] node _T_512 = and(do_enq, in_mask[6]) node _T_513 = bits(enq_idxs[6], 16, 16) node _T_514 = and(_T_512, _T_513) when _T_514 : connect fb_uop_ram[16], in_uops[6] node _T_515 = and(do_enq, in_mask[6]) node _T_516 = bits(enq_idxs[6], 17, 17) node _T_517 = and(_T_515, _T_516) when _T_517 : connect fb_uop_ram[17], in_uops[6] node _T_518 = and(do_enq, in_mask[6]) node _T_519 = bits(enq_idxs[6], 18, 18) node _T_520 = and(_T_518, _T_519) when _T_520 : connect fb_uop_ram[18], in_uops[6] node _T_521 = and(do_enq, in_mask[6]) node _T_522 = bits(enq_idxs[6], 19, 19) node _T_523 = and(_T_521, _T_522) when _T_523 : connect fb_uop_ram[19], in_uops[6] node _T_524 = and(do_enq, in_mask[6]) node _T_525 = bits(enq_idxs[6], 20, 20) node _T_526 = and(_T_524, _T_525) when _T_526 : connect fb_uop_ram[20], in_uops[6] node _T_527 = and(do_enq, in_mask[6]) node _T_528 = bits(enq_idxs[6], 21, 21) node _T_529 = and(_T_527, _T_528) when _T_529 : connect fb_uop_ram[21], in_uops[6] node _T_530 = and(do_enq, in_mask[6]) node _T_531 = bits(enq_idxs[6], 22, 22) node _T_532 = and(_T_530, _T_531) when _T_532 : connect fb_uop_ram[22], in_uops[6] node _T_533 = and(do_enq, in_mask[6]) node _T_534 = bits(enq_idxs[6], 23, 23) node _T_535 = and(_T_533, _T_534) when _T_535 : connect fb_uop_ram[23], in_uops[6] node _T_536 = and(do_enq, in_mask[7]) node _T_537 = bits(enq_idxs[7], 0, 0) node _T_538 = and(_T_536, _T_537) when _T_538 : connect fb_uop_ram[0], in_uops[7] node _T_539 = and(do_enq, in_mask[7]) node _T_540 = bits(enq_idxs[7], 1, 1) node _T_541 = and(_T_539, _T_540) when _T_541 : connect fb_uop_ram[1], in_uops[7] node _T_542 = and(do_enq, in_mask[7]) node _T_543 = bits(enq_idxs[7], 2, 2) node _T_544 = and(_T_542, _T_543) when _T_544 : connect fb_uop_ram[2], in_uops[7] node _T_545 = and(do_enq, in_mask[7]) node _T_546 = bits(enq_idxs[7], 3, 3) node _T_547 = and(_T_545, _T_546) when _T_547 : connect fb_uop_ram[3], in_uops[7] node _T_548 = and(do_enq, in_mask[7]) node _T_549 = bits(enq_idxs[7], 4, 4) node _T_550 = and(_T_548, _T_549) when _T_550 : connect fb_uop_ram[4], in_uops[7] node _T_551 = and(do_enq, in_mask[7]) node _T_552 = bits(enq_idxs[7], 5, 5) node _T_553 = and(_T_551, _T_552) when _T_553 : connect fb_uop_ram[5], in_uops[7] node _T_554 = and(do_enq, in_mask[7]) node _T_555 = bits(enq_idxs[7], 6, 6) node _T_556 = and(_T_554, _T_555) when _T_556 : connect fb_uop_ram[6], in_uops[7] node _T_557 = and(do_enq, in_mask[7]) node _T_558 = bits(enq_idxs[7], 7, 7) node _T_559 = and(_T_557, _T_558) when _T_559 : connect fb_uop_ram[7], in_uops[7] node _T_560 = and(do_enq, in_mask[7]) node _T_561 = bits(enq_idxs[7], 8, 8) node _T_562 = and(_T_560, _T_561) when _T_562 : connect fb_uop_ram[8], in_uops[7] node _T_563 = and(do_enq, in_mask[7]) node _T_564 = bits(enq_idxs[7], 9, 9) node _T_565 = and(_T_563, _T_564) when _T_565 : connect fb_uop_ram[9], in_uops[7] node _T_566 = and(do_enq, in_mask[7]) node _T_567 = bits(enq_idxs[7], 10, 10) node _T_568 = and(_T_566, _T_567) when _T_568 : connect fb_uop_ram[10], in_uops[7] node _T_569 = and(do_enq, in_mask[7]) node _T_570 = bits(enq_idxs[7], 11, 11) node _T_571 = and(_T_569, _T_570) when _T_571 : connect fb_uop_ram[11], in_uops[7] node _T_572 = and(do_enq, in_mask[7]) node _T_573 = bits(enq_idxs[7], 12, 12) node _T_574 = and(_T_572, _T_573) when _T_574 : connect fb_uop_ram[12], in_uops[7] node _T_575 = and(do_enq, in_mask[7]) node _T_576 = bits(enq_idxs[7], 13, 13) node _T_577 = and(_T_575, _T_576) when _T_577 : connect fb_uop_ram[13], in_uops[7] node _T_578 = and(do_enq, in_mask[7]) node _T_579 = bits(enq_idxs[7], 14, 14) node _T_580 = and(_T_578, _T_579) when _T_580 : connect fb_uop_ram[14], in_uops[7] node _T_581 = and(do_enq, in_mask[7]) node _T_582 = bits(enq_idxs[7], 15, 15) node _T_583 = and(_T_581, _T_582) when _T_583 : connect fb_uop_ram[15], in_uops[7] node _T_584 = and(do_enq, in_mask[7]) node _T_585 = bits(enq_idxs[7], 16, 16) node _T_586 = and(_T_584, _T_585) when _T_586 : connect fb_uop_ram[16], in_uops[7] node _T_587 = and(do_enq, in_mask[7]) node _T_588 = bits(enq_idxs[7], 17, 17) node _T_589 = and(_T_587, _T_588) when _T_589 : connect fb_uop_ram[17], in_uops[7] node _T_590 = and(do_enq, in_mask[7]) node _T_591 = bits(enq_idxs[7], 18, 18) node _T_592 = and(_T_590, _T_591) when _T_592 : connect fb_uop_ram[18], in_uops[7] node _T_593 = and(do_enq, in_mask[7]) node _T_594 = bits(enq_idxs[7], 19, 19) node _T_595 = and(_T_593, _T_594) when _T_595 : connect fb_uop_ram[19], in_uops[7] node _T_596 = and(do_enq, in_mask[7]) node _T_597 = bits(enq_idxs[7], 20, 20) node _T_598 = and(_T_596, _T_597) when _T_598 : connect fb_uop_ram[20], in_uops[7] node _T_599 = and(do_enq, in_mask[7]) node _T_600 = bits(enq_idxs[7], 21, 21) node _T_601 = and(_T_599, _T_600) when _T_601 : connect fb_uop_ram[21], in_uops[7] node _T_602 = and(do_enq, in_mask[7]) node _T_603 = bits(enq_idxs[7], 22, 22) node _T_604 = and(_T_602, _T_603) when _T_604 : connect fb_uop_ram[22], in_uops[7] node _T_605 = and(do_enq, in_mask[7]) node _T_606 = bits(enq_idxs[7], 23, 23) node _T_607 = and(_T_605, _T_606) when _T_607 : connect fb_uop_ram[23], in_uops[7] node _tail_collisions_T = bits(head, 0, 0) node _tail_collisions_T_1 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_2 = or(_tail_collisions_T_1, UInt<1>(0h0)) node _tail_collisions_T_3 = and(_tail_collisions_T, _tail_collisions_T_2) node _tail_collisions_T_4 = bits(head, 0, 0) node _tail_collisions_T_5 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_6 = or(_tail_collisions_T_5, UInt<1>(0h1)) node _tail_collisions_T_7 = and(_tail_collisions_T_4, _tail_collisions_T_6) node _tail_collisions_T_8 = bits(head, 0, 0) node _tail_collisions_T_9 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_10 = or(_tail_collisions_T_9, UInt<1>(0h1)) node _tail_collisions_T_11 = and(_tail_collisions_T_8, _tail_collisions_T_10) node _tail_collisions_T_12 = bits(head, 1, 1) node _tail_collisions_T_13 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_14 = or(_tail_collisions_T_13, UInt<1>(0h0)) node _tail_collisions_T_15 = and(_tail_collisions_T_12, _tail_collisions_T_14) node _tail_collisions_T_16 = bits(head, 1, 1) node _tail_collisions_T_17 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_18 = or(_tail_collisions_T_17, UInt<1>(0h1)) node _tail_collisions_T_19 = and(_tail_collisions_T_16, _tail_collisions_T_18) node _tail_collisions_T_20 = bits(head, 1, 1) node _tail_collisions_T_21 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_22 = or(_tail_collisions_T_21, UInt<1>(0h1)) node _tail_collisions_T_23 = and(_tail_collisions_T_20, _tail_collisions_T_22) node _tail_collisions_T_24 = bits(head, 2, 2) node _tail_collisions_T_25 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_26 = or(_tail_collisions_T_25, UInt<1>(0h0)) node _tail_collisions_T_27 = and(_tail_collisions_T_24, _tail_collisions_T_26) node _tail_collisions_T_28 = bits(head, 2, 2) node _tail_collisions_T_29 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_30 = or(_tail_collisions_T_29, UInt<1>(0h1)) node _tail_collisions_T_31 = and(_tail_collisions_T_28, _tail_collisions_T_30) node _tail_collisions_T_32 = bits(head, 2, 2) node _tail_collisions_T_33 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_34 = or(_tail_collisions_T_33, UInt<1>(0h1)) node _tail_collisions_T_35 = and(_tail_collisions_T_32, _tail_collisions_T_34) node _tail_collisions_T_36 = bits(head, 3, 3) node _tail_collisions_T_37 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_38 = or(_tail_collisions_T_37, UInt<1>(0h0)) node _tail_collisions_T_39 = and(_tail_collisions_T_36, _tail_collisions_T_38) node _tail_collisions_T_40 = bits(head, 3, 3) node _tail_collisions_T_41 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_42 = or(_tail_collisions_T_41, UInt<1>(0h1)) node _tail_collisions_T_43 = and(_tail_collisions_T_40, _tail_collisions_T_42) node _tail_collisions_T_44 = bits(head, 3, 3) node _tail_collisions_T_45 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_46 = or(_tail_collisions_T_45, UInt<1>(0h1)) node _tail_collisions_T_47 = and(_tail_collisions_T_44, _tail_collisions_T_46) node _tail_collisions_T_48 = bits(head, 4, 4) node _tail_collisions_T_49 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_50 = or(_tail_collisions_T_49, UInt<1>(0h0)) node _tail_collisions_T_51 = and(_tail_collisions_T_48, _tail_collisions_T_50) node _tail_collisions_T_52 = bits(head, 4, 4) node _tail_collisions_T_53 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_54 = or(_tail_collisions_T_53, UInt<1>(0h1)) node _tail_collisions_T_55 = and(_tail_collisions_T_52, _tail_collisions_T_54) node _tail_collisions_T_56 = bits(head, 4, 4) node _tail_collisions_T_57 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_58 = or(_tail_collisions_T_57, UInt<1>(0h1)) node _tail_collisions_T_59 = and(_tail_collisions_T_56, _tail_collisions_T_58) node _tail_collisions_T_60 = bits(head, 5, 5) node _tail_collisions_T_61 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_62 = or(_tail_collisions_T_61, UInt<1>(0h0)) node _tail_collisions_T_63 = and(_tail_collisions_T_60, _tail_collisions_T_62) node _tail_collisions_T_64 = bits(head, 5, 5) node _tail_collisions_T_65 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_66 = or(_tail_collisions_T_65, UInt<1>(0h1)) node _tail_collisions_T_67 = and(_tail_collisions_T_64, _tail_collisions_T_66) node _tail_collisions_T_68 = bits(head, 5, 5) node _tail_collisions_T_69 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_70 = or(_tail_collisions_T_69, UInt<1>(0h1)) node _tail_collisions_T_71 = and(_tail_collisions_T_68, _tail_collisions_T_70) node _tail_collisions_T_72 = bits(head, 6, 6) node _tail_collisions_T_73 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_74 = or(_tail_collisions_T_73, UInt<1>(0h0)) node _tail_collisions_T_75 = and(_tail_collisions_T_72, _tail_collisions_T_74) node _tail_collisions_T_76 = bits(head, 6, 6) node _tail_collisions_T_77 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_78 = or(_tail_collisions_T_77, UInt<1>(0h1)) node _tail_collisions_T_79 = and(_tail_collisions_T_76, _tail_collisions_T_78) node _tail_collisions_T_80 = bits(head, 6, 6) node _tail_collisions_T_81 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_82 = or(_tail_collisions_T_81, UInt<1>(0h1)) node _tail_collisions_T_83 = and(_tail_collisions_T_80, _tail_collisions_T_82) node _tail_collisions_T_84 = bits(head, 7, 7) node _tail_collisions_T_85 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_86 = or(_tail_collisions_T_85, UInt<1>(0h0)) node _tail_collisions_T_87 = and(_tail_collisions_T_84, _tail_collisions_T_86) node _tail_collisions_T_88 = bits(head, 7, 7) node _tail_collisions_T_89 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_90 = or(_tail_collisions_T_89, UInt<1>(0h1)) node _tail_collisions_T_91 = and(_tail_collisions_T_88, _tail_collisions_T_90) node _tail_collisions_T_92 = bits(head, 7, 7) node _tail_collisions_T_93 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_94 = or(_tail_collisions_T_93, UInt<1>(0h1)) node _tail_collisions_T_95 = and(_tail_collisions_T_92, _tail_collisions_T_94) wire _tail_collisions_WIRE : UInt<1>[24] connect _tail_collisions_WIRE[0], _tail_collisions_T_3 connect _tail_collisions_WIRE[1], _tail_collisions_T_7 connect _tail_collisions_WIRE[2], _tail_collisions_T_11 connect _tail_collisions_WIRE[3], _tail_collisions_T_15 connect _tail_collisions_WIRE[4], _tail_collisions_T_19 connect _tail_collisions_WIRE[5], _tail_collisions_T_23 connect _tail_collisions_WIRE[6], _tail_collisions_T_27 connect _tail_collisions_WIRE[7], _tail_collisions_T_31 connect _tail_collisions_WIRE[8], _tail_collisions_T_35 connect _tail_collisions_WIRE[9], _tail_collisions_T_39 connect _tail_collisions_WIRE[10], _tail_collisions_T_43 connect _tail_collisions_WIRE[11], _tail_collisions_T_47 connect _tail_collisions_WIRE[12], _tail_collisions_T_51 connect _tail_collisions_WIRE[13], _tail_collisions_T_55 connect _tail_collisions_WIRE[14], _tail_collisions_T_59 connect _tail_collisions_WIRE[15], _tail_collisions_T_63 connect _tail_collisions_WIRE[16], _tail_collisions_T_67 connect _tail_collisions_WIRE[17], _tail_collisions_T_71 connect _tail_collisions_WIRE[18], _tail_collisions_T_75 connect _tail_collisions_WIRE[19], _tail_collisions_T_79 connect _tail_collisions_WIRE[20], _tail_collisions_T_83 connect _tail_collisions_WIRE[21], _tail_collisions_T_87 connect _tail_collisions_WIRE[22], _tail_collisions_T_91 connect _tail_collisions_WIRE[23], _tail_collisions_T_95 node tail_collisions_lo_lo_lo_hi = cat(_tail_collisions_WIRE[2], _tail_collisions_WIRE[1]) node tail_collisions_lo_lo_lo = cat(tail_collisions_lo_lo_lo_hi, _tail_collisions_WIRE[0]) node tail_collisions_lo_lo_hi_hi = cat(_tail_collisions_WIRE[5], _tail_collisions_WIRE[4]) node tail_collisions_lo_lo_hi = cat(tail_collisions_lo_lo_hi_hi, _tail_collisions_WIRE[3]) node tail_collisions_lo_lo = cat(tail_collisions_lo_lo_hi, tail_collisions_lo_lo_lo) node tail_collisions_lo_hi_lo_hi = cat(_tail_collisions_WIRE[8], _tail_collisions_WIRE[7]) node tail_collisions_lo_hi_lo = cat(tail_collisions_lo_hi_lo_hi, _tail_collisions_WIRE[6]) node tail_collisions_lo_hi_hi_hi = cat(_tail_collisions_WIRE[11], _tail_collisions_WIRE[10]) node tail_collisions_lo_hi_hi = cat(tail_collisions_lo_hi_hi_hi, _tail_collisions_WIRE[9]) node tail_collisions_lo_hi = cat(tail_collisions_lo_hi_hi, tail_collisions_lo_hi_lo) node tail_collisions_lo = cat(tail_collisions_lo_hi, tail_collisions_lo_lo) node tail_collisions_hi_lo_lo_hi = cat(_tail_collisions_WIRE[14], _tail_collisions_WIRE[13]) node tail_collisions_hi_lo_lo = cat(tail_collisions_hi_lo_lo_hi, _tail_collisions_WIRE[12]) node tail_collisions_hi_lo_hi_hi = cat(_tail_collisions_WIRE[17], _tail_collisions_WIRE[16]) node tail_collisions_hi_lo_hi = cat(tail_collisions_hi_lo_hi_hi, _tail_collisions_WIRE[15]) node tail_collisions_hi_lo = cat(tail_collisions_hi_lo_hi, tail_collisions_hi_lo_lo) node tail_collisions_hi_hi_lo_hi = cat(_tail_collisions_WIRE[20], _tail_collisions_WIRE[19]) node tail_collisions_hi_hi_lo = cat(tail_collisions_hi_hi_lo_hi, _tail_collisions_WIRE[18]) node tail_collisions_hi_hi_hi_hi = cat(_tail_collisions_WIRE[23], _tail_collisions_WIRE[22]) node tail_collisions_hi_hi_hi = cat(tail_collisions_hi_hi_hi_hi, _tail_collisions_WIRE[21]) node tail_collisions_hi_hi = cat(tail_collisions_hi_hi_hi, tail_collisions_hi_hi_lo) node tail_collisions_hi = cat(tail_collisions_hi_hi, tail_collisions_hi_lo) node _tail_collisions_T_96 = cat(tail_collisions_hi, tail_collisions_lo) node tail_collisions = and(_tail_collisions_T_96, tail) node _slot_will_hit_tail_T = bits(tail_collisions, 2, 0) node _slot_will_hit_tail_T_1 = bits(tail_collisions, 5, 3) node _slot_will_hit_tail_T_2 = bits(tail_collisions, 8, 6) node _slot_will_hit_tail_T_3 = bits(tail_collisions, 11, 9) node _slot_will_hit_tail_T_4 = bits(tail_collisions, 14, 12) node _slot_will_hit_tail_T_5 = bits(tail_collisions, 17, 15) node _slot_will_hit_tail_T_6 = bits(tail_collisions, 20, 18) node _slot_will_hit_tail_T_7 = bits(tail_collisions, 23, 21) node _slot_will_hit_tail_T_8 = or(_slot_will_hit_tail_T, _slot_will_hit_tail_T_1) node _slot_will_hit_tail_T_9 = or(_slot_will_hit_tail_T_8, _slot_will_hit_tail_T_2) node _slot_will_hit_tail_T_10 = or(_slot_will_hit_tail_T_9, _slot_will_hit_tail_T_3) node _slot_will_hit_tail_T_11 = or(_slot_will_hit_tail_T_10, _slot_will_hit_tail_T_4) node _slot_will_hit_tail_T_12 = or(_slot_will_hit_tail_T_11, _slot_will_hit_tail_T_5) node _slot_will_hit_tail_T_13 = or(_slot_will_hit_tail_T_12, _slot_will_hit_tail_T_6) node slot_will_hit_tail = or(_slot_will_hit_tail_T_13, _slot_will_hit_tail_T_7) node will_hit_tail = orr(slot_will_hit_tail) node _do_deq_T = eq(will_hit_tail, UInt<1>(0h0)) node do_deq = and(io.deq.ready, _do_deq_T) node _deq_valids_T = dshl(slot_will_hit_tail, UInt<1>(0h0)) node _deq_valids_T_1 = bits(_deq_valids_T, 2, 0) node _deq_valids_T_2 = dshl(slot_will_hit_tail, UInt<1>(0h1)) node _deq_valids_T_3 = bits(_deq_valids_T_2, 2, 0) node _deq_valids_T_4 = dshl(slot_will_hit_tail, UInt<2>(0h2)) node _deq_valids_T_5 = bits(_deq_valids_T_4, 2, 0) node _deq_valids_T_6 = or(_deq_valids_T_1, _deq_valids_T_3) node _deq_valids_T_7 = or(_deq_valids_T_6, _deq_valids_T_5) node _deq_valids_T_8 = not(_deq_valids_T_7) node deq_valids_0 = bits(_deq_valids_T_8, 0, 0) node deq_valids_1 = bits(_deq_valids_T_8, 1, 1) node deq_valids_2 = bits(_deq_valids_T_8, 2, 2) connect deq_vec[0][0], fb_uop_ram[0] connect deq_vec[0][1], fb_uop_ram[1] connect deq_vec[0][2], fb_uop_ram[2] connect deq_vec[1][0], fb_uop_ram[3] connect deq_vec[1][1], fb_uop_ram[4] connect deq_vec[1][2], fb_uop_ram[5] connect deq_vec[2][0], fb_uop_ram[6] connect deq_vec[2][1], fb_uop_ram[7] connect deq_vec[2][2], fb_uop_ram[8] connect deq_vec[3][0], fb_uop_ram[9] connect deq_vec[3][1], fb_uop_ram[10] connect deq_vec[3][2], fb_uop_ram[11] connect deq_vec[4][0], fb_uop_ram[12] connect deq_vec[4][1], fb_uop_ram[13] connect deq_vec[4][2], fb_uop_ram[14] connect deq_vec[5][0], fb_uop_ram[15] connect deq_vec[5][1], fb_uop_ram[16] connect deq_vec[5][2], fb_uop_ram[17] connect deq_vec[6][0], fb_uop_ram[18] connect deq_vec[6][1], fb_uop_ram[19] connect deq_vec[6][2], fb_uop_ram[20] connect deq_vec[7][0], fb_uop_ram[21] connect deq_vec[7][1], fb_uop_ram[22] connect deq_vec[7][2], fb_uop_ram[23] connect io.deq.bits.uops[0].valid, deq_valids_0 connect io.deq.bits.uops[1].valid, deq_valids_1 connect io.deq.bits.uops[2].valid, deq_valids_2 node _T_608 = bits(head, 0, 0) node _T_609 = bits(head, 1, 1) node _T_610 = bits(head, 2, 2) node _T_611 = bits(head, 3, 3) node _T_612 = bits(head, 4, 4) node _T_613 = bits(head, 5, 5) node _T_614 = bits(head, 6, 6) node _T_615 = bits(head, 7, 7) wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3] wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_616 = mux(_T_608, deq_vec[0][0].debug_tsrc, UInt<1>(0h0)) node _T_617 = mux(_T_609, deq_vec[1][0].debug_tsrc, UInt<1>(0h0)) node _T_618 = mux(_T_610, deq_vec[2][0].debug_tsrc, UInt<1>(0h0)) node _T_619 = mux(_T_611, deq_vec[3][0].debug_tsrc, UInt<1>(0h0)) node _T_620 = mux(_T_612, deq_vec[4][0].debug_tsrc, UInt<1>(0h0)) node _T_621 = mux(_T_613, deq_vec[5][0].debug_tsrc, UInt<1>(0h0)) node _T_622 = mux(_T_614, deq_vec[6][0].debug_tsrc, UInt<1>(0h0)) node _T_623 = mux(_T_615, deq_vec[7][0].debug_tsrc, UInt<1>(0h0)) node _T_624 = or(_T_616, _T_617) node _T_625 = or(_T_624, _T_618) node _T_626 = or(_T_625, _T_619) node _T_627 = or(_T_626, _T_620) node _T_628 = or(_T_627, _T_621) node _T_629 = or(_T_628, _T_622) node _T_630 = or(_T_629, _T_623) wire _WIRE_2 : UInt<3> connect _WIRE_2, _T_630 connect _WIRE_1.debug_tsrc, _WIRE_2 node _T_631 = mux(_T_608, deq_vec[0][0].debug_fsrc, UInt<1>(0h0)) node _T_632 = mux(_T_609, deq_vec[1][0].debug_fsrc, UInt<1>(0h0)) node _T_633 = mux(_T_610, deq_vec[2][0].debug_fsrc, UInt<1>(0h0)) node _T_634 = mux(_T_611, deq_vec[3][0].debug_fsrc, UInt<1>(0h0)) node _T_635 = mux(_T_612, deq_vec[4][0].debug_fsrc, UInt<1>(0h0)) node _T_636 = mux(_T_613, deq_vec[5][0].debug_fsrc, UInt<1>(0h0)) node _T_637 = mux(_T_614, deq_vec[6][0].debug_fsrc, UInt<1>(0h0)) node _T_638 = mux(_T_615, deq_vec[7][0].debug_fsrc, UInt<1>(0h0)) node _T_639 = or(_T_631, _T_632) node _T_640 = or(_T_639, _T_633) node _T_641 = or(_T_640, _T_634) node _T_642 = or(_T_641, _T_635) node _T_643 = or(_T_642, _T_636) node _T_644 = or(_T_643, _T_637) node _T_645 = or(_T_644, _T_638) wire _WIRE_3 : UInt<3> connect _WIRE_3, _T_645 connect _WIRE_1.debug_fsrc, _WIRE_3 node _T_646 = mux(_T_608, deq_vec[0][0].bp_xcpt_if, UInt<1>(0h0)) node _T_647 = mux(_T_609, deq_vec[1][0].bp_xcpt_if, UInt<1>(0h0)) node _T_648 = mux(_T_610, deq_vec[2][0].bp_xcpt_if, UInt<1>(0h0)) node _T_649 = mux(_T_611, deq_vec[3][0].bp_xcpt_if, UInt<1>(0h0)) node _T_650 = mux(_T_612, deq_vec[4][0].bp_xcpt_if, UInt<1>(0h0)) node _T_651 = mux(_T_613, deq_vec[5][0].bp_xcpt_if, UInt<1>(0h0)) node _T_652 = mux(_T_614, deq_vec[6][0].bp_xcpt_if, UInt<1>(0h0)) node _T_653 = mux(_T_615, deq_vec[7][0].bp_xcpt_if, UInt<1>(0h0)) node _T_654 = or(_T_646, _T_647) node _T_655 = or(_T_654, _T_648) node _T_656 = or(_T_655, _T_649) node _T_657 = or(_T_656, _T_650) node _T_658 = or(_T_657, _T_651) node _T_659 = or(_T_658, _T_652) node _T_660 = or(_T_659, _T_653) wire _WIRE_4 : UInt<1> connect _WIRE_4, _T_660 connect _WIRE_1.bp_xcpt_if, _WIRE_4 node _T_661 = mux(_T_608, deq_vec[0][0].bp_debug_if, UInt<1>(0h0)) node _T_662 = mux(_T_609, deq_vec[1][0].bp_debug_if, UInt<1>(0h0)) node _T_663 = mux(_T_610, deq_vec[2][0].bp_debug_if, UInt<1>(0h0)) node _T_664 = mux(_T_611, deq_vec[3][0].bp_debug_if, UInt<1>(0h0)) node _T_665 = mux(_T_612, deq_vec[4][0].bp_debug_if, UInt<1>(0h0)) node _T_666 = mux(_T_613, deq_vec[5][0].bp_debug_if, UInt<1>(0h0)) node _T_667 = mux(_T_614, deq_vec[6][0].bp_debug_if, UInt<1>(0h0)) node _T_668 = mux(_T_615, deq_vec[7][0].bp_debug_if, UInt<1>(0h0)) node _T_669 = or(_T_661, _T_662) node _T_670 = or(_T_669, _T_663) node _T_671 = or(_T_670, _T_664) node _T_672 = or(_T_671, _T_665) node _T_673 = or(_T_672, _T_666) node _T_674 = or(_T_673, _T_667) node _T_675 = or(_T_674, _T_668) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_675 connect _WIRE_1.bp_debug_if, _WIRE_5 node _T_676 = mux(_T_608, deq_vec[0][0].xcpt_ma_if, UInt<1>(0h0)) node _T_677 = mux(_T_609, deq_vec[1][0].xcpt_ma_if, UInt<1>(0h0)) node _T_678 = mux(_T_610, deq_vec[2][0].xcpt_ma_if, UInt<1>(0h0)) node _T_679 = mux(_T_611, deq_vec[3][0].xcpt_ma_if, UInt<1>(0h0)) node _T_680 = mux(_T_612, deq_vec[4][0].xcpt_ma_if, UInt<1>(0h0)) node _T_681 = mux(_T_613, deq_vec[5][0].xcpt_ma_if, UInt<1>(0h0)) node _T_682 = mux(_T_614, deq_vec[6][0].xcpt_ma_if, UInt<1>(0h0)) node _T_683 = mux(_T_615, deq_vec[7][0].xcpt_ma_if, UInt<1>(0h0)) node _T_684 = or(_T_676, _T_677) node _T_685 = or(_T_684, _T_678) node _T_686 = or(_T_685, _T_679) node _T_687 = or(_T_686, _T_680) node _T_688 = or(_T_687, _T_681) node _T_689 = or(_T_688, _T_682) node _T_690 = or(_T_689, _T_683) wire _WIRE_6 : UInt<1> connect _WIRE_6, _T_690 connect _WIRE_1.xcpt_ma_if, _WIRE_6 node _T_691 = mux(_T_608, deq_vec[0][0].xcpt_ae_if, UInt<1>(0h0)) node _T_692 = mux(_T_609, deq_vec[1][0].xcpt_ae_if, UInt<1>(0h0)) node _T_693 = mux(_T_610, deq_vec[2][0].xcpt_ae_if, UInt<1>(0h0)) node _T_694 = mux(_T_611, deq_vec[3][0].xcpt_ae_if, UInt<1>(0h0)) node _T_695 = mux(_T_612, deq_vec[4][0].xcpt_ae_if, UInt<1>(0h0)) node _T_696 = mux(_T_613, deq_vec[5][0].xcpt_ae_if, UInt<1>(0h0)) node _T_697 = mux(_T_614, deq_vec[6][0].xcpt_ae_if, UInt<1>(0h0)) node _T_698 = mux(_T_615, deq_vec[7][0].xcpt_ae_if, UInt<1>(0h0)) node _T_699 = or(_T_691, _T_692) node _T_700 = or(_T_699, _T_693) node _T_701 = or(_T_700, _T_694) node _T_702 = or(_T_701, _T_695) node _T_703 = or(_T_702, _T_696) node _T_704 = or(_T_703, _T_697) node _T_705 = or(_T_704, _T_698) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_705 connect _WIRE_1.xcpt_ae_if, _WIRE_7 node _T_706 = mux(_T_608, deq_vec[0][0].xcpt_pf_if, UInt<1>(0h0)) node _T_707 = mux(_T_609, deq_vec[1][0].xcpt_pf_if, UInt<1>(0h0)) node _T_708 = mux(_T_610, deq_vec[2][0].xcpt_pf_if, UInt<1>(0h0)) node _T_709 = mux(_T_611, deq_vec[3][0].xcpt_pf_if, UInt<1>(0h0)) node _T_710 = mux(_T_612, deq_vec[4][0].xcpt_pf_if, UInt<1>(0h0)) node _T_711 = mux(_T_613, deq_vec[5][0].xcpt_pf_if, UInt<1>(0h0)) node _T_712 = mux(_T_614, deq_vec[6][0].xcpt_pf_if, UInt<1>(0h0)) node _T_713 = mux(_T_615, deq_vec[7][0].xcpt_pf_if, UInt<1>(0h0)) node _T_714 = or(_T_706, _T_707) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = or(_T_717, _T_711) node _T_719 = or(_T_718, _T_712) node _T_720 = or(_T_719, _T_713) wire _WIRE_8 : UInt<1> connect _WIRE_8, _T_720 connect _WIRE_1.xcpt_pf_if, _WIRE_8 node _T_721 = mux(_T_608, deq_vec[0][0].fp_typ, UInt<1>(0h0)) node _T_722 = mux(_T_609, deq_vec[1][0].fp_typ, UInt<1>(0h0)) node _T_723 = mux(_T_610, deq_vec[2][0].fp_typ, UInt<1>(0h0)) node _T_724 = mux(_T_611, deq_vec[3][0].fp_typ, UInt<1>(0h0)) node _T_725 = mux(_T_612, deq_vec[4][0].fp_typ, UInt<1>(0h0)) node _T_726 = mux(_T_613, deq_vec[5][0].fp_typ, UInt<1>(0h0)) node _T_727 = mux(_T_614, deq_vec[6][0].fp_typ, UInt<1>(0h0)) node _T_728 = mux(_T_615, deq_vec[7][0].fp_typ, UInt<1>(0h0)) node _T_729 = or(_T_721, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = or(_T_732, _T_726) node _T_734 = or(_T_733, _T_727) node _T_735 = or(_T_734, _T_728) wire _WIRE_9 : UInt<2> connect _WIRE_9, _T_735 connect _WIRE_1.fp_typ, _WIRE_9 node _T_736 = mux(_T_608, deq_vec[0][0].fp_rm, UInt<1>(0h0)) node _T_737 = mux(_T_609, deq_vec[1][0].fp_rm, UInt<1>(0h0)) node _T_738 = mux(_T_610, deq_vec[2][0].fp_rm, UInt<1>(0h0)) node _T_739 = mux(_T_611, deq_vec[3][0].fp_rm, UInt<1>(0h0)) node _T_740 = mux(_T_612, deq_vec[4][0].fp_rm, UInt<1>(0h0)) node _T_741 = mux(_T_613, deq_vec[5][0].fp_rm, UInt<1>(0h0)) node _T_742 = mux(_T_614, deq_vec[6][0].fp_rm, UInt<1>(0h0)) node _T_743 = mux(_T_615, deq_vec[7][0].fp_rm, UInt<1>(0h0)) node _T_744 = or(_T_736, _T_737) node _T_745 = or(_T_744, _T_738) node _T_746 = or(_T_745, _T_739) node _T_747 = or(_T_746, _T_740) node _T_748 = or(_T_747, _T_741) node _T_749 = or(_T_748, _T_742) node _T_750 = or(_T_749, _T_743) wire _WIRE_10 : UInt<3> connect _WIRE_10, _T_750 connect _WIRE_1.fp_rm, _WIRE_10 node _T_751 = mux(_T_608, deq_vec[0][0].fp_val, UInt<1>(0h0)) node _T_752 = mux(_T_609, deq_vec[1][0].fp_val, UInt<1>(0h0)) node _T_753 = mux(_T_610, deq_vec[2][0].fp_val, UInt<1>(0h0)) node _T_754 = mux(_T_611, deq_vec[3][0].fp_val, UInt<1>(0h0)) node _T_755 = mux(_T_612, deq_vec[4][0].fp_val, UInt<1>(0h0)) node _T_756 = mux(_T_613, deq_vec[5][0].fp_val, UInt<1>(0h0)) node _T_757 = mux(_T_614, deq_vec[6][0].fp_val, UInt<1>(0h0)) node _T_758 = mux(_T_615, deq_vec[7][0].fp_val, UInt<1>(0h0)) node _T_759 = or(_T_751, _T_752) node _T_760 = or(_T_759, _T_753) node _T_761 = or(_T_760, _T_754) node _T_762 = or(_T_761, _T_755) node _T_763 = or(_T_762, _T_756) node _T_764 = or(_T_763, _T_757) node _T_765 = or(_T_764, _T_758) wire _WIRE_11 : UInt<1> connect _WIRE_11, _T_765 connect _WIRE_1.fp_val, _WIRE_11 node _T_766 = mux(_T_608, deq_vec[0][0].fcn_op, UInt<1>(0h0)) node _T_767 = mux(_T_609, deq_vec[1][0].fcn_op, UInt<1>(0h0)) node _T_768 = mux(_T_610, deq_vec[2][0].fcn_op, UInt<1>(0h0)) node _T_769 = mux(_T_611, deq_vec[3][0].fcn_op, UInt<1>(0h0)) node _T_770 = mux(_T_612, deq_vec[4][0].fcn_op, UInt<1>(0h0)) node _T_771 = mux(_T_613, deq_vec[5][0].fcn_op, UInt<1>(0h0)) node _T_772 = mux(_T_614, deq_vec[6][0].fcn_op, UInt<1>(0h0)) node _T_773 = mux(_T_615, deq_vec[7][0].fcn_op, UInt<1>(0h0)) node _T_774 = or(_T_766, _T_767) node _T_775 = or(_T_774, _T_768) node _T_776 = or(_T_775, _T_769) node _T_777 = or(_T_776, _T_770) node _T_778 = or(_T_777, _T_771) node _T_779 = or(_T_778, _T_772) node _T_780 = or(_T_779, _T_773) wire _WIRE_12 : UInt<5> connect _WIRE_12, _T_780 connect _WIRE_1.fcn_op, _WIRE_12 node _T_781 = mux(_T_608, deq_vec[0][0].fcn_dw, UInt<1>(0h0)) node _T_782 = mux(_T_609, deq_vec[1][0].fcn_dw, UInt<1>(0h0)) node _T_783 = mux(_T_610, deq_vec[2][0].fcn_dw, UInt<1>(0h0)) node _T_784 = mux(_T_611, deq_vec[3][0].fcn_dw, UInt<1>(0h0)) node _T_785 = mux(_T_612, deq_vec[4][0].fcn_dw, UInt<1>(0h0)) node _T_786 = mux(_T_613, deq_vec[5][0].fcn_dw, UInt<1>(0h0)) node _T_787 = mux(_T_614, deq_vec[6][0].fcn_dw, UInt<1>(0h0)) node _T_788 = mux(_T_615, deq_vec[7][0].fcn_dw, UInt<1>(0h0)) node _T_789 = or(_T_781, _T_782) node _T_790 = or(_T_789, _T_783) node _T_791 = or(_T_790, _T_784) node _T_792 = or(_T_791, _T_785) node _T_793 = or(_T_792, _T_786) node _T_794 = or(_T_793, _T_787) node _T_795 = or(_T_794, _T_788) wire _WIRE_13 : UInt<1> connect _WIRE_13, _T_795 connect _WIRE_1.fcn_dw, _WIRE_13 node _T_796 = mux(_T_608, deq_vec[0][0].frs3_en, UInt<1>(0h0)) node _T_797 = mux(_T_609, deq_vec[1][0].frs3_en, UInt<1>(0h0)) node _T_798 = mux(_T_610, deq_vec[2][0].frs3_en, UInt<1>(0h0)) node _T_799 = mux(_T_611, deq_vec[3][0].frs3_en, UInt<1>(0h0)) node _T_800 = mux(_T_612, deq_vec[4][0].frs3_en, UInt<1>(0h0)) node _T_801 = mux(_T_613, deq_vec[5][0].frs3_en, UInt<1>(0h0)) node _T_802 = mux(_T_614, deq_vec[6][0].frs3_en, UInt<1>(0h0)) node _T_803 = mux(_T_615, deq_vec[7][0].frs3_en, UInt<1>(0h0)) node _T_804 = or(_T_796, _T_797) node _T_805 = or(_T_804, _T_798) node _T_806 = or(_T_805, _T_799) node _T_807 = or(_T_806, _T_800) node _T_808 = or(_T_807, _T_801) node _T_809 = or(_T_808, _T_802) node _T_810 = or(_T_809, _T_803) wire _WIRE_14 : UInt<1> connect _WIRE_14, _T_810 connect _WIRE_1.frs3_en, _WIRE_14 node _T_811 = mux(_T_608, deq_vec[0][0].lrs2_rtype, UInt<1>(0h0)) node _T_812 = mux(_T_609, deq_vec[1][0].lrs2_rtype, UInt<1>(0h0)) node _T_813 = mux(_T_610, deq_vec[2][0].lrs2_rtype, UInt<1>(0h0)) node _T_814 = mux(_T_611, deq_vec[3][0].lrs2_rtype, UInt<1>(0h0)) node _T_815 = mux(_T_612, deq_vec[4][0].lrs2_rtype, UInt<1>(0h0)) node _T_816 = mux(_T_613, deq_vec[5][0].lrs2_rtype, UInt<1>(0h0)) node _T_817 = mux(_T_614, deq_vec[6][0].lrs2_rtype, UInt<1>(0h0)) node _T_818 = mux(_T_615, deq_vec[7][0].lrs2_rtype, UInt<1>(0h0)) node _T_819 = or(_T_811, _T_812) node _T_820 = or(_T_819, _T_813) node _T_821 = or(_T_820, _T_814) node _T_822 = or(_T_821, _T_815) node _T_823 = or(_T_822, _T_816) node _T_824 = or(_T_823, _T_817) node _T_825 = or(_T_824, _T_818) wire _WIRE_15 : UInt<2> connect _WIRE_15, _T_825 connect _WIRE_1.lrs2_rtype, _WIRE_15 node _T_826 = mux(_T_608, deq_vec[0][0].lrs1_rtype, UInt<1>(0h0)) node _T_827 = mux(_T_609, deq_vec[1][0].lrs1_rtype, UInt<1>(0h0)) node _T_828 = mux(_T_610, deq_vec[2][0].lrs1_rtype, UInt<1>(0h0)) node _T_829 = mux(_T_611, deq_vec[3][0].lrs1_rtype, UInt<1>(0h0)) node _T_830 = mux(_T_612, deq_vec[4][0].lrs1_rtype, UInt<1>(0h0)) node _T_831 = mux(_T_613, deq_vec[5][0].lrs1_rtype, UInt<1>(0h0)) node _T_832 = mux(_T_614, deq_vec[6][0].lrs1_rtype, UInt<1>(0h0)) node _T_833 = mux(_T_615, deq_vec[7][0].lrs1_rtype, UInt<1>(0h0)) node _T_834 = or(_T_826, _T_827) node _T_835 = or(_T_834, _T_828) node _T_836 = or(_T_835, _T_829) node _T_837 = or(_T_836, _T_830) node _T_838 = or(_T_837, _T_831) node _T_839 = or(_T_838, _T_832) node _T_840 = or(_T_839, _T_833) wire _WIRE_16 : UInt<2> connect _WIRE_16, _T_840 connect _WIRE_1.lrs1_rtype, _WIRE_16 node _T_841 = mux(_T_608, deq_vec[0][0].dst_rtype, UInt<1>(0h0)) node _T_842 = mux(_T_609, deq_vec[1][0].dst_rtype, UInt<1>(0h0)) node _T_843 = mux(_T_610, deq_vec[2][0].dst_rtype, UInt<1>(0h0)) node _T_844 = mux(_T_611, deq_vec[3][0].dst_rtype, UInt<1>(0h0)) node _T_845 = mux(_T_612, deq_vec[4][0].dst_rtype, UInt<1>(0h0)) node _T_846 = mux(_T_613, deq_vec[5][0].dst_rtype, UInt<1>(0h0)) node _T_847 = mux(_T_614, deq_vec[6][0].dst_rtype, UInt<1>(0h0)) node _T_848 = mux(_T_615, deq_vec[7][0].dst_rtype, UInt<1>(0h0)) node _T_849 = or(_T_841, _T_842) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = or(_T_853, _T_847) node _T_855 = or(_T_854, _T_848) wire _WIRE_17 : UInt<2> connect _WIRE_17, _T_855 connect _WIRE_1.dst_rtype, _WIRE_17 node _T_856 = mux(_T_608, deq_vec[0][0].lrs3, UInt<1>(0h0)) node _T_857 = mux(_T_609, deq_vec[1][0].lrs3, UInt<1>(0h0)) node _T_858 = mux(_T_610, deq_vec[2][0].lrs3, UInt<1>(0h0)) node _T_859 = mux(_T_611, deq_vec[3][0].lrs3, UInt<1>(0h0)) node _T_860 = mux(_T_612, deq_vec[4][0].lrs3, UInt<1>(0h0)) node _T_861 = mux(_T_613, deq_vec[5][0].lrs3, UInt<1>(0h0)) node _T_862 = mux(_T_614, deq_vec[6][0].lrs3, UInt<1>(0h0)) node _T_863 = mux(_T_615, deq_vec[7][0].lrs3, UInt<1>(0h0)) node _T_864 = or(_T_856, _T_857) node _T_865 = or(_T_864, _T_858) node _T_866 = or(_T_865, _T_859) node _T_867 = or(_T_866, _T_860) node _T_868 = or(_T_867, _T_861) node _T_869 = or(_T_868, _T_862) node _T_870 = or(_T_869, _T_863) wire _WIRE_18 : UInt<6> connect _WIRE_18, _T_870 connect _WIRE_1.lrs3, _WIRE_18 node _T_871 = mux(_T_608, deq_vec[0][0].lrs2, UInt<1>(0h0)) node _T_872 = mux(_T_609, deq_vec[1][0].lrs2, UInt<1>(0h0)) node _T_873 = mux(_T_610, deq_vec[2][0].lrs2, UInt<1>(0h0)) node _T_874 = mux(_T_611, deq_vec[3][0].lrs2, UInt<1>(0h0)) node _T_875 = mux(_T_612, deq_vec[4][0].lrs2, UInt<1>(0h0)) node _T_876 = mux(_T_613, deq_vec[5][0].lrs2, UInt<1>(0h0)) node _T_877 = mux(_T_614, deq_vec[6][0].lrs2, UInt<1>(0h0)) node _T_878 = mux(_T_615, deq_vec[7][0].lrs2, UInt<1>(0h0)) node _T_879 = or(_T_871, _T_872) node _T_880 = or(_T_879, _T_873) node _T_881 = or(_T_880, _T_874) node _T_882 = or(_T_881, _T_875) node _T_883 = or(_T_882, _T_876) node _T_884 = or(_T_883, _T_877) node _T_885 = or(_T_884, _T_878) wire _WIRE_19 : UInt<6> connect _WIRE_19, _T_885 connect _WIRE_1.lrs2, _WIRE_19 node _T_886 = mux(_T_608, deq_vec[0][0].lrs1, UInt<1>(0h0)) node _T_887 = mux(_T_609, deq_vec[1][0].lrs1, UInt<1>(0h0)) node _T_888 = mux(_T_610, deq_vec[2][0].lrs1, UInt<1>(0h0)) node _T_889 = mux(_T_611, deq_vec[3][0].lrs1, UInt<1>(0h0)) node _T_890 = mux(_T_612, deq_vec[4][0].lrs1, UInt<1>(0h0)) node _T_891 = mux(_T_613, deq_vec[5][0].lrs1, UInt<1>(0h0)) node _T_892 = mux(_T_614, deq_vec[6][0].lrs1, UInt<1>(0h0)) node _T_893 = mux(_T_615, deq_vec[7][0].lrs1, UInt<1>(0h0)) node _T_894 = or(_T_886, _T_887) node _T_895 = or(_T_894, _T_888) node _T_896 = or(_T_895, _T_889) node _T_897 = or(_T_896, _T_890) node _T_898 = or(_T_897, _T_891) node _T_899 = or(_T_898, _T_892) node _T_900 = or(_T_899, _T_893) wire _WIRE_20 : UInt<6> connect _WIRE_20, _T_900 connect _WIRE_1.lrs1, _WIRE_20 node _T_901 = mux(_T_608, deq_vec[0][0].ldst, UInt<1>(0h0)) node _T_902 = mux(_T_609, deq_vec[1][0].ldst, UInt<1>(0h0)) node _T_903 = mux(_T_610, deq_vec[2][0].ldst, UInt<1>(0h0)) node _T_904 = mux(_T_611, deq_vec[3][0].ldst, UInt<1>(0h0)) node _T_905 = mux(_T_612, deq_vec[4][0].ldst, UInt<1>(0h0)) node _T_906 = mux(_T_613, deq_vec[5][0].ldst, UInt<1>(0h0)) node _T_907 = mux(_T_614, deq_vec[6][0].ldst, UInt<1>(0h0)) node _T_908 = mux(_T_615, deq_vec[7][0].ldst, UInt<1>(0h0)) node _T_909 = or(_T_901, _T_902) node _T_910 = or(_T_909, _T_903) node _T_911 = or(_T_910, _T_904) node _T_912 = or(_T_911, _T_905) node _T_913 = or(_T_912, _T_906) node _T_914 = or(_T_913, _T_907) node _T_915 = or(_T_914, _T_908) wire _WIRE_21 : UInt<6> connect _WIRE_21, _T_915 connect _WIRE_1.ldst, _WIRE_21 node _T_916 = mux(_T_608, deq_vec[0][0].ldst_is_rs1, UInt<1>(0h0)) node _T_917 = mux(_T_609, deq_vec[1][0].ldst_is_rs1, UInt<1>(0h0)) node _T_918 = mux(_T_610, deq_vec[2][0].ldst_is_rs1, UInt<1>(0h0)) node _T_919 = mux(_T_611, deq_vec[3][0].ldst_is_rs1, UInt<1>(0h0)) node _T_920 = mux(_T_612, deq_vec[4][0].ldst_is_rs1, UInt<1>(0h0)) node _T_921 = mux(_T_613, deq_vec[5][0].ldst_is_rs1, UInt<1>(0h0)) node _T_922 = mux(_T_614, deq_vec[6][0].ldst_is_rs1, UInt<1>(0h0)) node _T_923 = mux(_T_615, deq_vec[7][0].ldst_is_rs1, UInt<1>(0h0)) node _T_924 = or(_T_916, _T_917) node _T_925 = or(_T_924, _T_918) node _T_926 = or(_T_925, _T_919) node _T_927 = or(_T_926, _T_920) node _T_928 = or(_T_927, _T_921) node _T_929 = or(_T_928, _T_922) node _T_930 = or(_T_929, _T_923) wire _WIRE_22 : UInt<1> connect _WIRE_22, _T_930 connect _WIRE_1.ldst_is_rs1, _WIRE_22 node _T_931 = mux(_T_608, deq_vec[0][0].csr_cmd, UInt<1>(0h0)) node _T_932 = mux(_T_609, deq_vec[1][0].csr_cmd, UInt<1>(0h0)) node _T_933 = mux(_T_610, deq_vec[2][0].csr_cmd, UInt<1>(0h0)) node _T_934 = mux(_T_611, deq_vec[3][0].csr_cmd, UInt<1>(0h0)) node _T_935 = mux(_T_612, deq_vec[4][0].csr_cmd, UInt<1>(0h0)) node _T_936 = mux(_T_613, deq_vec[5][0].csr_cmd, UInt<1>(0h0)) node _T_937 = mux(_T_614, deq_vec[6][0].csr_cmd, UInt<1>(0h0)) node _T_938 = mux(_T_615, deq_vec[7][0].csr_cmd, UInt<1>(0h0)) node _T_939 = or(_T_931, _T_932) node _T_940 = or(_T_939, _T_933) node _T_941 = or(_T_940, _T_934) node _T_942 = or(_T_941, _T_935) node _T_943 = or(_T_942, _T_936) node _T_944 = or(_T_943, _T_937) node _T_945 = or(_T_944, _T_938) wire _WIRE_23 : UInt<3> connect _WIRE_23, _T_945 connect _WIRE_1.csr_cmd, _WIRE_23 node _T_946 = mux(_T_608, deq_vec[0][0].flush_on_commit, UInt<1>(0h0)) node _T_947 = mux(_T_609, deq_vec[1][0].flush_on_commit, UInt<1>(0h0)) node _T_948 = mux(_T_610, deq_vec[2][0].flush_on_commit, UInt<1>(0h0)) node _T_949 = mux(_T_611, deq_vec[3][0].flush_on_commit, UInt<1>(0h0)) node _T_950 = mux(_T_612, deq_vec[4][0].flush_on_commit, UInt<1>(0h0)) node _T_951 = mux(_T_613, deq_vec[5][0].flush_on_commit, UInt<1>(0h0)) node _T_952 = mux(_T_614, deq_vec[6][0].flush_on_commit, UInt<1>(0h0)) node _T_953 = mux(_T_615, deq_vec[7][0].flush_on_commit, UInt<1>(0h0)) node _T_954 = or(_T_946, _T_947) node _T_955 = or(_T_954, _T_948) node _T_956 = or(_T_955, _T_949) node _T_957 = or(_T_956, _T_950) node _T_958 = or(_T_957, _T_951) node _T_959 = or(_T_958, _T_952) node _T_960 = or(_T_959, _T_953) wire _WIRE_24 : UInt<1> connect _WIRE_24, _T_960 connect _WIRE_1.flush_on_commit, _WIRE_24 node _T_961 = mux(_T_608, deq_vec[0][0].is_unique, UInt<1>(0h0)) node _T_962 = mux(_T_609, deq_vec[1][0].is_unique, UInt<1>(0h0)) node _T_963 = mux(_T_610, deq_vec[2][0].is_unique, UInt<1>(0h0)) node _T_964 = mux(_T_611, deq_vec[3][0].is_unique, UInt<1>(0h0)) node _T_965 = mux(_T_612, deq_vec[4][0].is_unique, UInt<1>(0h0)) node _T_966 = mux(_T_613, deq_vec[5][0].is_unique, UInt<1>(0h0)) node _T_967 = mux(_T_614, deq_vec[6][0].is_unique, UInt<1>(0h0)) node _T_968 = mux(_T_615, deq_vec[7][0].is_unique, UInt<1>(0h0)) node _T_969 = or(_T_961, _T_962) node _T_970 = or(_T_969, _T_963) node _T_971 = or(_T_970, _T_964) node _T_972 = or(_T_971, _T_965) node _T_973 = or(_T_972, _T_966) node _T_974 = or(_T_973, _T_967) node _T_975 = or(_T_974, _T_968) wire _WIRE_25 : UInt<1> connect _WIRE_25, _T_975 connect _WIRE_1.is_unique, _WIRE_25 node _T_976 = mux(_T_608, deq_vec[0][0].uses_stq, UInt<1>(0h0)) node _T_977 = mux(_T_609, deq_vec[1][0].uses_stq, UInt<1>(0h0)) node _T_978 = mux(_T_610, deq_vec[2][0].uses_stq, UInt<1>(0h0)) node _T_979 = mux(_T_611, deq_vec[3][0].uses_stq, UInt<1>(0h0)) node _T_980 = mux(_T_612, deq_vec[4][0].uses_stq, UInt<1>(0h0)) node _T_981 = mux(_T_613, deq_vec[5][0].uses_stq, UInt<1>(0h0)) node _T_982 = mux(_T_614, deq_vec[6][0].uses_stq, UInt<1>(0h0)) node _T_983 = mux(_T_615, deq_vec[7][0].uses_stq, UInt<1>(0h0)) node _T_984 = or(_T_976, _T_977) node _T_985 = or(_T_984, _T_978) node _T_986 = or(_T_985, _T_979) node _T_987 = or(_T_986, _T_980) node _T_988 = or(_T_987, _T_981) node _T_989 = or(_T_988, _T_982) node _T_990 = or(_T_989, _T_983) wire _WIRE_26 : UInt<1> connect _WIRE_26, _T_990 connect _WIRE_1.uses_stq, _WIRE_26 node _T_991 = mux(_T_608, deq_vec[0][0].uses_ldq, UInt<1>(0h0)) node _T_992 = mux(_T_609, deq_vec[1][0].uses_ldq, UInt<1>(0h0)) node _T_993 = mux(_T_610, deq_vec[2][0].uses_ldq, UInt<1>(0h0)) node _T_994 = mux(_T_611, deq_vec[3][0].uses_ldq, UInt<1>(0h0)) node _T_995 = mux(_T_612, deq_vec[4][0].uses_ldq, UInt<1>(0h0)) node _T_996 = mux(_T_613, deq_vec[5][0].uses_ldq, UInt<1>(0h0)) node _T_997 = mux(_T_614, deq_vec[6][0].uses_ldq, UInt<1>(0h0)) node _T_998 = mux(_T_615, deq_vec[7][0].uses_ldq, UInt<1>(0h0)) node _T_999 = or(_T_991, _T_992) node _T_1000 = or(_T_999, _T_993) node _T_1001 = or(_T_1000, _T_994) node _T_1002 = or(_T_1001, _T_995) node _T_1003 = or(_T_1002, _T_996) node _T_1004 = or(_T_1003, _T_997) node _T_1005 = or(_T_1004, _T_998) wire _WIRE_27 : UInt<1> connect _WIRE_27, _T_1005 connect _WIRE_1.uses_ldq, _WIRE_27 node _T_1006 = mux(_T_608, deq_vec[0][0].mem_signed, UInt<1>(0h0)) node _T_1007 = mux(_T_609, deq_vec[1][0].mem_signed, UInt<1>(0h0)) node _T_1008 = mux(_T_610, deq_vec[2][0].mem_signed, UInt<1>(0h0)) node _T_1009 = mux(_T_611, deq_vec[3][0].mem_signed, UInt<1>(0h0)) node _T_1010 = mux(_T_612, deq_vec[4][0].mem_signed, UInt<1>(0h0)) node _T_1011 = mux(_T_613, deq_vec[5][0].mem_signed, UInt<1>(0h0)) node _T_1012 = mux(_T_614, deq_vec[6][0].mem_signed, UInt<1>(0h0)) node _T_1013 = mux(_T_615, deq_vec[7][0].mem_signed, UInt<1>(0h0)) node _T_1014 = or(_T_1006, _T_1007) node _T_1015 = or(_T_1014, _T_1008) node _T_1016 = or(_T_1015, _T_1009) node _T_1017 = or(_T_1016, _T_1010) node _T_1018 = or(_T_1017, _T_1011) node _T_1019 = or(_T_1018, _T_1012) node _T_1020 = or(_T_1019, _T_1013) wire _WIRE_28 : UInt<1> connect _WIRE_28, _T_1020 connect _WIRE_1.mem_signed, _WIRE_28 node _T_1021 = mux(_T_608, deq_vec[0][0].mem_size, UInt<1>(0h0)) node _T_1022 = mux(_T_609, deq_vec[1][0].mem_size, UInt<1>(0h0)) node _T_1023 = mux(_T_610, deq_vec[2][0].mem_size, UInt<1>(0h0)) node _T_1024 = mux(_T_611, deq_vec[3][0].mem_size, UInt<1>(0h0)) node _T_1025 = mux(_T_612, deq_vec[4][0].mem_size, UInt<1>(0h0)) node _T_1026 = mux(_T_613, deq_vec[5][0].mem_size, UInt<1>(0h0)) node _T_1027 = mux(_T_614, deq_vec[6][0].mem_size, UInt<1>(0h0)) node _T_1028 = mux(_T_615, deq_vec[7][0].mem_size, UInt<1>(0h0)) node _T_1029 = or(_T_1021, _T_1022) node _T_1030 = or(_T_1029, _T_1023) node _T_1031 = or(_T_1030, _T_1024) node _T_1032 = or(_T_1031, _T_1025) node _T_1033 = or(_T_1032, _T_1026) node _T_1034 = or(_T_1033, _T_1027) node _T_1035 = or(_T_1034, _T_1028) wire _WIRE_29 : UInt<2> connect _WIRE_29, _T_1035 connect _WIRE_1.mem_size, _WIRE_29 node _T_1036 = mux(_T_608, deq_vec[0][0].mem_cmd, UInt<1>(0h0)) node _T_1037 = mux(_T_609, deq_vec[1][0].mem_cmd, UInt<1>(0h0)) node _T_1038 = mux(_T_610, deq_vec[2][0].mem_cmd, UInt<1>(0h0)) node _T_1039 = mux(_T_611, deq_vec[3][0].mem_cmd, UInt<1>(0h0)) node _T_1040 = mux(_T_612, deq_vec[4][0].mem_cmd, UInt<1>(0h0)) node _T_1041 = mux(_T_613, deq_vec[5][0].mem_cmd, UInt<1>(0h0)) node _T_1042 = mux(_T_614, deq_vec[6][0].mem_cmd, UInt<1>(0h0)) node _T_1043 = mux(_T_615, deq_vec[7][0].mem_cmd, UInt<1>(0h0)) node _T_1044 = or(_T_1036, _T_1037) node _T_1045 = or(_T_1044, _T_1038) node _T_1046 = or(_T_1045, _T_1039) node _T_1047 = or(_T_1046, _T_1040) node _T_1048 = or(_T_1047, _T_1041) node _T_1049 = or(_T_1048, _T_1042) node _T_1050 = or(_T_1049, _T_1043) wire _WIRE_30 : UInt<5> connect _WIRE_30, _T_1050 connect _WIRE_1.mem_cmd, _WIRE_30 node _T_1051 = mux(_T_608, deq_vec[0][0].exc_cause, UInt<1>(0h0)) node _T_1052 = mux(_T_609, deq_vec[1][0].exc_cause, UInt<1>(0h0)) node _T_1053 = mux(_T_610, deq_vec[2][0].exc_cause, UInt<1>(0h0)) node _T_1054 = mux(_T_611, deq_vec[3][0].exc_cause, UInt<1>(0h0)) node _T_1055 = mux(_T_612, deq_vec[4][0].exc_cause, UInt<1>(0h0)) node _T_1056 = mux(_T_613, deq_vec[5][0].exc_cause, UInt<1>(0h0)) node _T_1057 = mux(_T_614, deq_vec[6][0].exc_cause, UInt<1>(0h0)) node _T_1058 = mux(_T_615, deq_vec[7][0].exc_cause, UInt<1>(0h0)) node _T_1059 = or(_T_1051, _T_1052) node _T_1060 = or(_T_1059, _T_1053) node _T_1061 = or(_T_1060, _T_1054) node _T_1062 = or(_T_1061, _T_1055) node _T_1063 = or(_T_1062, _T_1056) node _T_1064 = or(_T_1063, _T_1057) node _T_1065 = or(_T_1064, _T_1058) wire _WIRE_31 : UInt<64> connect _WIRE_31, _T_1065 connect _WIRE_1.exc_cause, _WIRE_31 node _T_1066 = mux(_T_608, deq_vec[0][0].exception, UInt<1>(0h0)) node _T_1067 = mux(_T_609, deq_vec[1][0].exception, UInt<1>(0h0)) node _T_1068 = mux(_T_610, deq_vec[2][0].exception, UInt<1>(0h0)) node _T_1069 = mux(_T_611, deq_vec[3][0].exception, UInt<1>(0h0)) node _T_1070 = mux(_T_612, deq_vec[4][0].exception, UInt<1>(0h0)) node _T_1071 = mux(_T_613, deq_vec[5][0].exception, UInt<1>(0h0)) node _T_1072 = mux(_T_614, deq_vec[6][0].exception, UInt<1>(0h0)) node _T_1073 = mux(_T_615, deq_vec[7][0].exception, UInt<1>(0h0)) node _T_1074 = or(_T_1066, _T_1067) node _T_1075 = or(_T_1074, _T_1068) node _T_1076 = or(_T_1075, _T_1069) node _T_1077 = or(_T_1076, _T_1070) node _T_1078 = or(_T_1077, _T_1071) node _T_1079 = or(_T_1078, _T_1072) node _T_1080 = or(_T_1079, _T_1073) wire _WIRE_32 : UInt<1> connect _WIRE_32, _T_1080 connect _WIRE_1.exception, _WIRE_32 node _T_1081 = mux(_T_608, deq_vec[0][0].stale_pdst, UInt<1>(0h0)) node _T_1082 = mux(_T_609, deq_vec[1][0].stale_pdst, UInt<1>(0h0)) node _T_1083 = mux(_T_610, deq_vec[2][0].stale_pdst, UInt<1>(0h0)) node _T_1084 = mux(_T_611, deq_vec[3][0].stale_pdst, UInt<1>(0h0)) node _T_1085 = mux(_T_612, deq_vec[4][0].stale_pdst, UInt<1>(0h0)) node _T_1086 = mux(_T_613, deq_vec[5][0].stale_pdst, UInt<1>(0h0)) node _T_1087 = mux(_T_614, deq_vec[6][0].stale_pdst, UInt<1>(0h0)) node _T_1088 = mux(_T_615, deq_vec[7][0].stale_pdst, UInt<1>(0h0)) node _T_1089 = or(_T_1081, _T_1082) node _T_1090 = or(_T_1089, _T_1083) node _T_1091 = or(_T_1090, _T_1084) node _T_1092 = or(_T_1091, _T_1085) node _T_1093 = or(_T_1092, _T_1086) node _T_1094 = or(_T_1093, _T_1087) node _T_1095 = or(_T_1094, _T_1088) wire _WIRE_33 : UInt<7> connect _WIRE_33, _T_1095 connect _WIRE_1.stale_pdst, _WIRE_33 node _T_1096 = mux(_T_608, deq_vec[0][0].ppred_busy, UInt<1>(0h0)) node _T_1097 = mux(_T_609, deq_vec[1][0].ppred_busy, UInt<1>(0h0)) node _T_1098 = mux(_T_610, deq_vec[2][0].ppred_busy, UInt<1>(0h0)) node _T_1099 = mux(_T_611, deq_vec[3][0].ppred_busy, UInt<1>(0h0)) node _T_1100 = mux(_T_612, deq_vec[4][0].ppred_busy, UInt<1>(0h0)) node _T_1101 = mux(_T_613, deq_vec[5][0].ppred_busy, UInt<1>(0h0)) node _T_1102 = mux(_T_614, deq_vec[6][0].ppred_busy, UInt<1>(0h0)) node _T_1103 = mux(_T_615, deq_vec[7][0].ppred_busy, UInt<1>(0h0)) node _T_1104 = or(_T_1096, _T_1097) node _T_1105 = or(_T_1104, _T_1098) node _T_1106 = or(_T_1105, _T_1099) node _T_1107 = or(_T_1106, _T_1100) node _T_1108 = or(_T_1107, _T_1101) node _T_1109 = or(_T_1108, _T_1102) node _T_1110 = or(_T_1109, _T_1103) wire _WIRE_34 : UInt<1> connect _WIRE_34, _T_1110 connect _WIRE_1.ppred_busy, _WIRE_34 node _T_1111 = mux(_T_608, deq_vec[0][0].prs3_busy, UInt<1>(0h0)) node _T_1112 = mux(_T_609, deq_vec[1][0].prs3_busy, UInt<1>(0h0)) node _T_1113 = mux(_T_610, deq_vec[2][0].prs3_busy, UInt<1>(0h0)) node _T_1114 = mux(_T_611, deq_vec[3][0].prs3_busy, UInt<1>(0h0)) node _T_1115 = mux(_T_612, deq_vec[4][0].prs3_busy, UInt<1>(0h0)) node _T_1116 = mux(_T_613, deq_vec[5][0].prs3_busy, UInt<1>(0h0)) node _T_1117 = mux(_T_614, deq_vec[6][0].prs3_busy, UInt<1>(0h0)) node _T_1118 = mux(_T_615, deq_vec[7][0].prs3_busy, UInt<1>(0h0)) node _T_1119 = or(_T_1111, _T_1112) node _T_1120 = or(_T_1119, _T_1113) node _T_1121 = or(_T_1120, _T_1114) node _T_1122 = or(_T_1121, _T_1115) node _T_1123 = or(_T_1122, _T_1116) node _T_1124 = or(_T_1123, _T_1117) node _T_1125 = or(_T_1124, _T_1118) wire _WIRE_35 : UInt<1> connect _WIRE_35, _T_1125 connect _WIRE_1.prs3_busy, _WIRE_35 node _T_1126 = mux(_T_608, deq_vec[0][0].prs2_busy, UInt<1>(0h0)) node _T_1127 = mux(_T_609, deq_vec[1][0].prs2_busy, UInt<1>(0h0)) node _T_1128 = mux(_T_610, deq_vec[2][0].prs2_busy, UInt<1>(0h0)) node _T_1129 = mux(_T_611, deq_vec[3][0].prs2_busy, UInt<1>(0h0)) node _T_1130 = mux(_T_612, deq_vec[4][0].prs2_busy, UInt<1>(0h0)) node _T_1131 = mux(_T_613, deq_vec[5][0].prs2_busy, UInt<1>(0h0)) node _T_1132 = mux(_T_614, deq_vec[6][0].prs2_busy, UInt<1>(0h0)) node _T_1133 = mux(_T_615, deq_vec[7][0].prs2_busy, UInt<1>(0h0)) node _T_1134 = or(_T_1126, _T_1127) node _T_1135 = or(_T_1134, _T_1128) node _T_1136 = or(_T_1135, _T_1129) node _T_1137 = or(_T_1136, _T_1130) node _T_1138 = or(_T_1137, _T_1131) node _T_1139 = or(_T_1138, _T_1132) node _T_1140 = or(_T_1139, _T_1133) wire _WIRE_36 : UInt<1> connect _WIRE_36, _T_1140 connect _WIRE_1.prs2_busy, _WIRE_36 node _T_1141 = mux(_T_608, deq_vec[0][0].prs1_busy, UInt<1>(0h0)) node _T_1142 = mux(_T_609, deq_vec[1][0].prs1_busy, UInt<1>(0h0)) node _T_1143 = mux(_T_610, deq_vec[2][0].prs1_busy, UInt<1>(0h0)) node _T_1144 = mux(_T_611, deq_vec[3][0].prs1_busy, UInt<1>(0h0)) node _T_1145 = mux(_T_612, deq_vec[4][0].prs1_busy, UInt<1>(0h0)) node _T_1146 = mux(_T_613, deq_vec[5][0].prs1_busy, UInt<1>(0h0)) node _T_1147 = mux(_T_614, deq_vec[6][0].prs1_busy, UInt<1>(0h0)) node _T_1148 = mux(_T_615, deq_vec[7][0].prs1_busy, UInt<1>(0h0)) node _T_1149 = or(_T_1141, _T_1142) node _T_1150 = or(_T_1149, _T_1143) node _T_1151 = or(_T_1150, _T_1144) node _T_1152 = or(_T_1151, _T_1145) node _T_1153 = or(_T_1152, _T_1146) node _T_1154 = or(_T_1153, _T_1147) node _T_1155 = or(_T_1154, _T_1148) wire _WIRE_37 : UInt<1> connect _WIRE_37, _T_1155 connect _WIRE_1.prs1_busy, _WIRE_37 node _T_1156 = mux(_T_608, deq_vec[0][0].ppred, UInt<1>(0h0)) node _T_1157 = mux(_T_609, deq_vec[1][0].ppred, UInt<1>(0h0)) node _T_1158 = mux(_T_610, deq_vec[2][0].ppred, UInt<1>(0h0)) node _T_1159 = mux(_T_611, deq_vec[3][0].ppred, UInt<1>(0h0)) node _T_1160 = mux(_T_612, deq_vec[4][0].ppred, UInt<1>(0h0)) node _T_1161 = mux(_T_613, deq_vec[5][0].ppred, UInt<1>(0h0)) node _T_1162 = mux(_T_614, deq_vec[6][0].ppred, UInt<1>(0h0)) node _T_1163 = mux(_T_615, deq_vec[7][0].ppred, UInt<1>(0h0)) node _T_1164 = or(_T_1156, _T_1157) node _T_1165 = or(_T_1164, _T_1158) node _T_1166 = or(_T_1165, _T_1159) node _T_1167 = or(_T_1166, _T_1160) node _T_1168 = or(_T_1167, _T_1161) node _T_1169 = or(_T_1168, _T_1162) node _T_1170 = or(_T_1169, _T_1163) wire _WIRE_38 : UInt<5> connect _WIRE_38, _T_1170 connect _WIRE_1.ppred, _WIRE_38 node _T_1171 = mux(_T_608, deq_vec[0][0].prs3, UInt<1>(0h0)) node _T_1172 = mux(_T_609, deq_vec[1][0].prs3, UInt<1>(0h0)) node _T_1173 = mux(_T_610, deq_vec[2][0].prs3, UInt<1>(0h0)) node _T_1174 = mux(_T_611, deq_vec[3][0].prs3, UInt<1>(0h0)) node _T_1175 = mux(_T_612, deq_vec[4][0].prs3, UInt<1>(0h0)) node _T_1176 = mux(_T_613, deq_vec[5][0].prs3, UInt<1>(0h0)) node _T_1177 = mux(_T_614, deq_vec[6][0].prs3, UInt<1>(0h0)) node _T_1178 = mux(_T_615, deq_vec[7][0].prs3, UInt<1>(0h0)) node _T_1179 = or(_T_1171, _T_1172) node _T_1180 = or(_T_1179, _T_1173) node _T_1181 = or(_T_1180, _T_1174) node _T_1182 = or(_T_1181, _T_1175) node _T_1183 = or(_T_1182, _T_1176) node _T_1184 = or(_T_1183, _T_1177) node _T_1185 = or(_T_1184, _T_1178) wire _WIRE_39 : UInt<7> connect _WIRE_39, _T_1185 connect _WIRE_1.prs3, _WIRE_39 node _T_1186 = mux(_T_608, deq_vec[0][0].prs2, UInt<1>(0h0)) node _T_1187 = mux(_T_609, deq_vec[1][0].prs2, UInt<1>(0h0)) node _T_1188 = mux(_T_610, deq_vec[2][0].prs2, UInt<1>(0h0)) node _T_1189 = mux(_T_611, deq_vec[3][0].prs2, UInt<1>(0h0)) node _T_1190 = mux(_T_612, deq_vec[4][0].prs2, UInt<1>(0h0)) node _T_1191 = mux(_T_613, deq_vec[5][0].prs2, UInt<1>(0h0)) node _T_1192 = mux(_T_614, deq_vec[6][0].prs2, UInt<1>(0h0)) node _T_1193 = mux(_T_615, deq_vec[7][0].prs2, UInt<1>(0h0)) node _T_1194 = or(_T_1186, _T_1187) node _T_1195 = or(_T_1194, _T_1188) node _T_1196 = or(_T_1195, _T_1189) node _T_1197 = or(_T_1196, _T_1190) node _T_1198 = or(_T_1197, _T_1191) node _T_1199 = or(_T_1198, _T_1192) node _T_1200 = or(_T_1199, _T_1193) wire _WIRE_40 : UInt<7> connect _WIRE_40, _T_1200 connect _WIRE_1.prs2, _WIRE_40 node _T_1201 = mux(_T_608, deq_vec[0][0].prs1, UInt<1>(0h0)) node _T_1202 = mux(_T_609, deq_vec[1][0].prs1, UInt<1>(0h0)) node _T_1203 = mux(_T_610, deq_vec[2][0].prs1, UInt<1>(0h0)) node _T_1204 = mux(_T_611, deq_vec[3][0].prs1, UInt<1>(0h0)) node _T_1205 = mux(_T_612, deq_vec[4][0].prs1, UInt<1>(0h0)) node _T_1206 = mux(_T_613, deq_vec[5][0].prs1, UInt<1>(0h0)) node _T_1207 = mux(_T_614, deq_vec[6][0].prs1, UInt<1>(0h0)) node _T_1208 = mux(_T_615, deq_vec[7][0].prs1, UInt<1>(0h0)) node _T_1209 = or(_T_1201, _T_1202) node _T_1210 = or(_T_1209, _T_1203) node _T_1211 = or(_T_1210, _T_1204) node _T_1212 = or(_T_1211, _T_1205) node _T_1213 = or(_T_1212, _T_1206) node _T_1214 = or(_T_1213, _T_1207) node _T_1215 = or(_T_1214, _T_1208) wire _WIRE_41 : UInt<7> connect _WIRE_41, _T_1215 connect _WIRE_1.prs1, _WIRE_41 node _T_1216 = mux(_T_608, deq_vec[0][0].pdst, UInt<1>(0h0)) node _T_1217 = mux(_T_609, deq_vec[1][0].pdst, UInt<1>(0h0)) node _T_1218 = mux(_T_610, deq_vec[2][0].pdst, UInt<1>(0h0)) node _T_1219 = mux(_T_611, deq_vec[3][0].pdst, UInt<1>(0h0)) node _T_1220 = mux(_T_612, deq_vec[4][0].pdst, UInt<1>(0h0)) node _T_1221 = mux(_T_613, deq_vec[5][0].pdst, UInt<1>(0h0)) node _T_1222 = mux(_T_614, deq_vec[6][0].pdst, UInt<1>(0h0)) node _T_1223 = mux(_T_615, deq_vec[7][0].pdst, UInt<1>(0h0)) node _T_1224 = or(_T_1216, _T_1217) node _T_1225 = or(_T_1224, _T_1218) node _T_1226 = or(_T_1225, _T_1219) node _T_1227 = or(_T_1226, _T_1220) node _T_1228 = or(_T_1227, _T_1221) node _T_1229 = or(_T_1228, _T_1222) node _T_1230 = or(_T_1229, _T_1223) wire _WIRE_42 : UInt<7> connect _WIRE_42, _T_1230 connect _WIRE_1.pdst, _WIRE_42 node _T_1231 = mux(_T_608, deq_vec[0][0].rxq_idx, UInt<1>(0h0)) node _T_1232 = mux(_T_609, deq_vec[1][0].rxq_idx, UInt<1>(0h0)) node _T_1233 = mux(_T_610, deq_vec[2][0].rxq_idx, UInt<1>(0h0)) node _T_1234 = mux(_T_611, deq_vec[3][0].rxq_idx, UInt<1>(0h0)) node _T_1235 = mux(_T_612, deq_vec[4][0].rxq_idx, UInt<1>(0h0)) node _T_1236 = mux(_T_613, deq_vec[5][0].rxq_idx, UInt<1>(0h0)) node _T_1237 = mux(_T_614, deq_vec[6][0].rxq_idx, UInt<1>(0h0)) node _T_1238 = mux(_T_615, deq_vec[7][0].rxq_idx, UInt<1>(0h0)) node _T_1239 = or(_T_1231, _T_1232) node _T_1240 = or(_T_1239, _T_1233) node _T_1241 = or(_T_1240, _T_1234) node _T_1242 = or(_T_1241, _T_1235) node _T_1243 = or(_T_1242, _T_1236) node _T_1244 = or(_T_1243, _T_1237) node _T_1245 = or(_T_1244, _T_1238) wire _WIRE_43 : UInt<2> connect _WIRE_43, _T_1245 connect _WIRE_1.rxq_idx, _WIRE_43 node _T_1246 = mux(_T_608, deq_vec[0][0].stq_idx, UInt<1>(0h0)) node _T_1247 = mux(_T_609, deq_vec[1][0].stq_idx, UInt<1>(0h0)) node _T_1248 = mux(_T_610, deq_vec[2][0].stq_idx, UInt<1>(0h0)) node _T_1249 = mux(_T_611, deq_vec[3][0].stq_idx, UInt<1>(0h0)) node _T_1250 = mux(_T_612, deq_vec[4][0].stq_idx, UInt<1>(0h0)) node _T_1251 = mux(_T_613, deq_vec[5][0].stq_idx, UInt<1>(0h0)) node _T_1252 = mux(_T_614, deq_vec[6][0].stq_idx, UInt<1>(0h0)) node _T_1253 = mux(_T_615, deq_vec[7][0].stq_idx, UInt<1>(0h0)) node _T_1254 = or(_T_1246, _T_1247) node _T_1255 = or(_T_1254, _T_1248) node _T_1256 = or(_T_1255, _T_1249) node _T_1257 = or(_T_1256, _T_1250) node _T_1258 = or(_T_1257, _T_1251) node _T_1259 = or(_T_1258, _T_1252) node _T_1260 = or(_T_1259, _T_1253) wire _WIRE_44 : UInt<5> connect _WIRE_44, _T_1260 connect _WIRE_1.stq_idx, _WIRE_44 node _T_1261 = mux(_T_608, deq_vec[0][0].ldq_idx, UInt<1>(0h0)) node _T_1262 = mux(_T_609, deq_vec[1][0].ldq_idx, UInt<1>(0h0)) node _T_1263 = mux(_T_610, deq_vec[2][0].ldq_idx, UInt<1>(0h0)) node _T_1264 = mux(_T_611, deq_vec[3][0].ldq_idx, UInt<1>(0h0)) node _T_1265 = mux(_T_612, deq_vec[4][0].ldq_idx, UInt<1>(0h0)) node _T_1266 = mux(_T_613, deq_vec[5][0].ldq_idx, UInt<1>(0h0)) node _T_1267 = mux(_T_614, deq_vec[6][0].ldq_idx, UInt<1>(0h0)) node _T_1268 = mux(_T_615, deq_vec[7][0].ldq_idx, UInt<1>(0h0)) node _T_1269 = or(_T_1261, _T_1262) node _T_1270 = or(_T_1269, _T_1263) node _T_1271 = or(_T_1270, _T_1264) node _T_1272 = or(_T_1271, _T_1265) node _T_1273 = or(_T_1272, _T_1266) node _T_1274 = or(_T_1273, _T_1267) node _T_1275 = or(_T_1274, _T_1268) wire _WIRE_45 : UInt<5> connect _WIRE_45, _T_1275 connect _WIRE_1.ldq_idx, _WIRE_45 node _T_1276 = mux(_T_608, deq_vec[0][0].rob_idx, UInt<1>(0h0)) node _T_1277 = mux(_T_609, deq_vec[1][0].rob_idx, UInt<1>(0h0)) node _T_1278 = mux(_T_610, deq_vec[2][0].rob_idx, UInt<1>(0h0)) node _T_1279 = mux(_T_611, deq_vec[3][0].rob_idx, UInt<1>(0h0)) node _T_1280 = mux(_T_612, deq_vec[4][0].rob_idx, UInt<1>(0h0)) node _T_1281 = mux(_T_613, deq_vec[5][0].rob_idx, UInt<1>(0h0)) node _T_1282 = mux(_T_614, deq_vec[6][0].rob_idx, UInt<1>(0h0)) node _T_1283 = mux(_T_615, deq_vec[7][0].rob_idx, UInt<1>(0h0)) node _T_1284 = or(_T_1276, _T_1277) node _T_1285 = or(_T_1284, _T_1278) node _T_1286 = or(_T_1285, _T_1279) node _T_1287 = or(_T_1286, _T_1280) node _T_1288 = or(_T_1287, _T_1281) node _T_1289 = or(_T_1288, _T_1282) node _T_1290 = or(_T_1289, _T_1283) wire _WIRE_46 : UInt<7> connect _WIRE_46, _T_1290 connect _WIRE_1.rob_idx, _WIRE_46 wire _WIRE_47 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_1291 = mux(_T_608, deq_vec[0][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1292 = mux(_T_609, deq_vec[1][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1293 = mux(_T_610, deq_vec[2][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1294 = mux(_T_611, deq_vec[3][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1295 = mux(_T_612, deq_vec[4][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1296 = mux(_T_613, deq_vec[5][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1297 = mux(_T_614, deq_vec[6][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1298 = mux(_T_615, deq_vec[7][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1299 = or(_T_1291, _T_1292) node _T_1300 = or(_T_1299, _T_1293) node _T_1301 = or(_T_1300, _T_1294) node _T_1302 = or(_T_1301, _T_1295) node _T_1303 = or(_T_1302, _T_1296) node _T_1304 = or(_T_1303, _T_1297) node _T_1305 = or(_T_1304, _T_1298) wire _WIRE_48 : UInt<1> connect _WIRE_48, _T_1305 connect _WIRE_47.vec, _WIRE_48 node _T_1306 = mux(_T_608, deq_vec[0][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1307 = mux(_T_609, deq_vec[1][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1308 = mux(_T_610, deq_vec[2][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1309 = mux(_T_611, deq_vec[3][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1310 = mux(_T_612, deq_vec[4][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1311 = mux(_T_613, deq_vec[5][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1312 = mux(_T_614, deq_vec[6][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1313 = mux(_T_615, deq_vec[7][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1314 = or(_T_1306, _T_1307) node _T_1315 = or(_T_1314, _T_1308) node _T_1316 = or(_T_1315, _T_1309) node _T_1317 = or(_T_1316, _T_1310) node _T_1318 = or(_T_1317, _T_1311) node _T_1319 = or(_T_1318, _T_1312) node _T_1320 = or(_T_1319, _T_1313) wire _WIRE_49 : UInt<1> connect _WIRE_49, _T_1320 connect _WIRE_47.wflags, _WIRE_49 node _T_1321 = mux(_T_608, deq_vec[0][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1322 = mux(_T_609, deq_vec[1][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1323 = mux(_T_610, deq_vec[2][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1324 = mux(_T_611, deq_vec[3][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1325 = mux(_T_612, deq_vec[4][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1326 = mux(_T_613, deq_vec[5][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1327 = mux(_T_614, deq_vec[6][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1328 = mux(_T_615, deq_vec[7][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1329 = or(_T_1321, _T_1322) node _T_1330 = or(_T_1329, _T_1323) node _T_1331 = or(_T_1330, _T_1324) node _T_1332 = or(_T_1331, _T_1325) node _T_1333 = or(_T_1332, _T_1326) node _T_1334 = or(_T_1333, _T_1327) node _T_1335 = or(_T_1334, _T_1328) wire _WIRE_50 : UInt<1> connect _WIRE_50, _T_1335 connect _WIRE_47.sqrt, _WIRE_50 node _T_1336 = mux(_T_608, deq_vec[0][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1337 = mux(_T_609, deq_vec[1][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1338 = mux(_T_610, deq_vec[2][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1339 = mux(_T_611, deq_vec[3][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1340 = mux(_T_612, deq_vec[4][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1341 = mux(_T_613, deq_vec[5][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1342 = mux(_T_614, deq_vec[6][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1343 = mux(_T_615, deq_vec[7][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1344 = or(_T_1336, _T_1337) node _T_1345 = or(_T_1344, _T_1338) node _T_1346 = or(_T_1345, _T_1339) node _T_1347 = or(_T_1346, _T_1340) node _T_1348 = or(_T_1347, _T_1341) node _T_1349 = or(_T_1348, _T_1342) node _T_1350 = or(_T_1349, _T_1343) wire _WIRE_51 : UInt<1> connect _WIRE_51, _T_1350 connect _WIRE_47.div, _WIRE_51 node _T_1351 = mux(_T_608, deq_vec[0][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1352 = mux(_T_609, deq_vec[1][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1353 = mux(_T_610, deq_vec[2][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1354 = mux(_T_611, deq_vec[3][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1355 = mux(_T_612, deq_vec[4][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1356 = mux(_T_613, deq_vec[5][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1357 = mux(_T_614, deq_vec[6][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1358 = mux(_T_615, deq_vec[7][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1359 = or(_T_1351, _T_1352) node _T_1360 = or(_T_1359, _T_1353) node _T_1361 = or(_T_1360, _T_1354) node _T_1362 = or(_T_1361, _T_1355) node _T_1363 = or(_T_1362, _T_1356) node _T_1364 = or(_T_1363, _T_1357) node _T_1365 = or(_T_1364, _T_1358) wire _WIRE_52 : UInt<1> connect _WIRE_52, _T_1365 connect _WIRE_47.fma, _WIRE_52 node _T_1366 = mux(_T_608, deq_vec[0][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1367 = mux(_T_609, deq_vec[1][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1368 = mux(_T_610, deq_vec[2][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1369 = mux(_T_611, deq_vec[3][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1370 = mux(_T_612, deq_vec[4][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1371 = mux(_T_613, deq_vec[5][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1372 = mux(_T_614, deq_vec[6][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1373 = mux(_T_615, deq_vec[7][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1374 = or(_T_1366, _T_1367) node _T_1375 = or(_T_1374, _T_1368) node _T_1376 = or(_T_1375, _T_1369) node _T_1377 = or(_T_1376, _T_1370) node _T_1378 = or(_T_1377, _T_1371) node _T_1379 = or(_T_1378, _T_1372) node _T_1380 = or(_T_1379, _T_1373) wire _WIRE_53 : UInt<1> connect _WIRE_53, _T_1380 connect _WIRE_47.fastpipe, _WIRE_53 node _T_1381 = mux(_T_608, deq_vec[0][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1382 = mux(_T_609, deq_vec[1][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1383 = mux(_T_610, deq_vec[2][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1384 = mux(_T_611, deq_vec[3][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1385 = mux(_T_612, deq_vec[4][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1386 = mux(_T_613, deq_vec[5][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1387 = mux(_T_614, deq_vec[6][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1388 = mux(_T_615, deq_vec[7][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1389 = or(_T_1381, _T_1382) node _T_1390 = or(_T_1389, _T_1383) node _T_1391 = or(_T_1390, _T_1384) node _T_1392 = or(_T_1391, _T_1385) node _T_1393 = or(_T_1392, _T_1386) node _T_1394 = or(_T_1393, _T_1387) node _T_1395 = or(_T_1394, _T_1388) wire _WIRE_54 : UInt<1> connect _WIRE_54, _T_1395 connect _WIRE_47.toint, _WIRE_54 node _T_1396 = mux(_T_608, deq_vec[0][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1397 = mux(_T_609, deq_vec[1][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1398 = mux(_T_610, deq_vec[2][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1399 = mux(_T_611, deq_vec[3][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1400 = mux(_T_612, deq_vec[4][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1401 = mux(_T_613, deq_vec[5][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1402 = mux(_T_614, deq_vec[6][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1403 = mux(_T_615, deq_vec[7][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1404 = or(_T_1396, _T_1397) node _T_1405 = or(_T_1404, _T_1398) node _T_1406 = or(_T_1405, _T_1399) node _T_1407 = or(_T_1406, _T_1400) node _T_1408 = or(_T_1407, _T_1401) node _T_1409 = or(_T_1408, _T_1402) node _T_1410 = or(_T_1409, _T_1403) wire _WIRE_55 : UInt<1> connect _WIRE_55, _T_1410 connect _WIRE_47.fromint, _WIRE_55 node _T_1411 = mux(_T_608, deq_vec[0][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1412 = mux(_T_609, deq_vec[1][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1413 = mux(_T_610, deq_vec[2][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1414 = mux(_T_611, deq_vec[3][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1415 = mux(_T_612, deq_vec[4][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1416 = mux(_T_613, deq_vec[5][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1417 = mux(_T_614, deq_vec[6][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1418 = mux(_T_615, deq_vec[7][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1419 = or(_T_1411, _T_1412) node _T_1420 = or(_T_1419, _T_1413) node _T_1421 = or(_T_1420, _T_1414) node _T_1422 = or(_T_1421, _T_1415) node _T_1423 = or(_T_1422, _T_1416) node _T_1424 = or(_T_1423, _T_1417) node _T_1425 = or(_T_1424, _T_1418) wire _WIRE_56 : UInt<2> connect _WIRE_56, _T_1425 connect _WIRE_47.typeTagOut, _WIRE_56 node _T_1426 = mux(_T_608, deq_vec[0][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1427 = mux(_T_609, deq_vec[1][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1428 = mux(_T_610, deq_vec[2][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1429 = mux(_T_611, deq_vec[3][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1430 = mux(_T_612, deq_vec[4][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1431 = mux(_T_613, deq_vec[5][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1432 = mux(_T_614, deq_vec[6][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1433 = mux(_T_615, deq_vec[7][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1434 = or(_T_1426, _T_1427) node _T_1435 = or(_T_1434, _T_1428) node _T_1436 = or(_T_1435, _T_1429) node _T_1437 = or(_T_1436, _T_1430) node _T_1438 = or(_T_1437, _T_1431) node _T_1439 = or(_T_1438, _T_1432) node _T_1440 = or(_T_1439, _T_1433) wire _WIRE_57 : UInt<2> connect _WIRE_57, _T_1440 connect _WIRE_47.typeTagIn, _WIRE_57 node _T_1441 = mux(_T_608, deq_vec[0][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1442 = mux(_T_609, deq_vec[1][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1443 = mux(_T_610, deq_vec[2][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1444 = mux(_T_611, deq_vec[3][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1445 = mux(_T_612, deq_vec[4][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1446 = mux(_T_613, deq_vec[5][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1447 = mux(_T_614, deq_vec[6][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1448 = mux(_T_615, deq_vec[7][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1449 = or(_T_1441, _T_1442) node _T_1450 = or(_T_1449, _T_1443) node _T_1451 = or(_T_1450, _T_1444) node _T_1452 = or(_T_1451, _T_1445) node _T_1453 = or(_T_1452, _T_1446) node _T_1454 = or(_T_1453, _T_1447) node _T_1455 = or(_T_1454, _T_1448) wire _WIRE_58 : UInt<1> connect _WIRE_58, _T_1455 connect _WIRE_47.swap23, _WIRE_58 node _T_1456 = mux(_T_608, deq_vec[0][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1457 = mux(_T_609, deq_vec[1][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1458 = mux(_T_610, deq_vec[2][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1459 = mux(_T_611, deq_vec[3][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1460 = mux(_T_612, deq_vec[4][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1461 = mux(_T_613, deq_vec[5][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1462 = mux(_T_614, deq_vec[6][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1463 = mux(_T_615, deq_vec[7][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1464 = or(_T_1456, _T_1457) node _T_1465 = or(_T_1464, _T_1458) node _T_1466 = or(_T_1465, _T_1459) node _T_1467 = or(_T_1466, _T_1460) node _T_1468 = or(_T_1467, _T_1461) node _T_1469 = or(_T_1468, _T_1462) node _T_1470 = or(_T_1469, _T_1463) wire _WIRE_59 : UInt<1> connect _WIRE_59, _T_1470 connect _WIRE_47.swap12, _WIRE_59 node _T_1471 = mux(_T_608, deq_vec[0][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1472 = mux(_T_609, deq_vec[1][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1473 = mux(_T_610, deq_vec[2][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1474 = mux(_T_611, deq_vec[3][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1475 = mux(_T_612, deq_vec[4][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1476 = mux(_T_613, deq_vec[5][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1477 = mux(_T_614, deq_vec[6][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1478 = mux(_T_615, deq_vec[7][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1479 = or(_T_1471, _T_1472) node _T_1480 = or(_T_1479, _T_1473) node _T_1481 = or(_T_1480, _T_1474) node _T_1482 = or(_T_1481, _T_1475) node _T_1483 = or(_T_1482, _T_1476) node _T_1484 = or(_T_1483, _T_1477) node _T_1485 = or(_T_1484, _T_1478) wire _WIRE_60 : UInt<1> connect _WIRE_60, _T_1485 connect _WIRE_47.ren3, _WIRE_60 node _T_1486 = mux(_T_608, deq_vec[0][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1487 = mux(_T_609, deq_vec[1][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1488 = mux(_T_610, deq_vec[2][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1489 = mux(_T_611, deq_vec[3][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1490 = mux(_T_612, deq_vec[4][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1491 = mux(_T_613, deq_vec[5][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1492 = mux(_T_614, deq_vec[6][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1493 = mux(_T_615, deq_vec[7][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1494 = or(_T_1486, _T_1487) node _T_1495 = or(_T_1494, _T_1488) node _T_1496 = or(_T_1495, _T_1489) node _T_1497 = or(_T_1496, _T_1490) node _T_1498 = or(_T_1497, _T_1491) node _T_1499 = or(_T_1498, _T_1492) node _T_1500 = or(_T_1499, _T_1493) wire _WIRE_61 : UInt<1> connect _WIRE_61, _T_1500 connect _WIRE_47.ren2, _WIRE_61 node _T_1501 = mux(_T_608, deq_vec[0][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1502 = mux(_T_609, deq_vec[1][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1503 = mux(_T_610, deq_vec[2][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1504 = mux(_T_611, deq_vec[3][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1505 = mux(_T_612, deq_vec[4][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1506 = mux(_T_613, deq_vec[5][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1507 = mux(_T_614, deq_vec[6][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1508 = mux(_T_615, deq_vec[7][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1509 = or(_T_1501, _T_1502) node _T_1510 = or(_T_1509, _T_1503) node _T_1511 = or(_T_1510, _T_1504) node _T_1512 = or(_T_1511, _T_1505) node _T_1513 = or(_T_1512, _T_1506) node _T_1514 = or(_T_1513, _T_1507) node _T_1515 = or(_T_1514, _T_1508) wire _WIRE_62 : UInt<1> connect _WIRE_62, _T_1515 connect _WIRE_47.ren1, _WIRE_62 node _T_1516 = mux(_T_608, deq_vec[0][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1517 = mux(_T_609, deq_vec[1][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1518 = mux(_T_610, deq_vec[2][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1519 = mux(_T_611, deq_vec[3][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1520 = mux(_T_612, deq_vec[4][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1521 = mux(_T_613, deq_vec[5][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1522 = mux(_T_614, deq_vec[6][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1523 = mux(_T_615, deq_vec[7][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1524 = or(_T_1516, _T_1517) node _T_1525 = or(_T_1524, _T_1518) node _T_1526 = or(_T_1525, _T_1519) node _T_1527 = or(_T_1526, _T_1520) node _T_1528 = or(_T_1527, _T_1521) node _T_1529 = or(_T_1528, _T_1522) node _T_1530 = or(_T_1529, _T_1523) wire _WIRE_63 : UInt<1> connect _WIRE_63, _T_1530 connect _WIRE_47.wen, _WIRE_63 node _T_1531 = mux(_T_608, deq_vec[0][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1532 = mux(_T_609, deq_vec[1][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1533 = mux(_T_610, deq_vec[2][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1534 = mux(_T_611, deq_vec[3][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1535 = mux(_T_612, deq_vec[4][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1536 = mux(_T_613, deq_vec[5][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1537 = mux(_T_614, deq_vec[6][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1538 = mux(_T_615, deq_vec[7][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1539 = or(_T_1531, _T_1532) node _T_1540 = or(_T_1539, _T_1533) node _T_1541 = or(_T_1540, _T_1534) node _T_1542 = or(_T_1541, _T_1535) node _T_1543 = or(_T_1542, _T_1536) node _T_1544 = or(_T_1543, _T_1537) node _T_1545 = or(_T_1544, _T_1538) wire _WIRE_64 : UInt<1> connect _WIRE_64, _T_1545 connect _WIRE_47.ldst, _WIRE_64 connect _WIRE_1.fp_ctrl, _WIRE_47 node _T_1546 = mux(_T_608, deq_vec[0][0].op2_sel, UInt<1>(0h0)) node _T_1547 = mux(_T_609, deq_vec[1][0].op2_sel, UInt<1>(0h0)) node _T_1548 = mux(_T_610, deq_vec[2][0].op2_sel, UInt<1>(0h0)) node _T_1549 = mux(_T_611, deq_vec[3][0].op2_sel, UInt<1>(0h0)) node _T_1550 = mux(_T_612, deq_vec[4][0].op2_sel, UInt<1>(0h0)) node _T_1551 = mux(_T_613, deq_vec[5][0].op2_sel, UInt<1>(0h0)) node _T_1552 = mux(_T_614, deq_vec[6][0].op2_sel, UInt<1>(0h0)) node _T_1553 = mux(_T_615, deq_vec[7][0].op2_sel, UInt<1>(0h0)) node _T_1554 = or(_T_1546, _T_1547) node _T_1555 = or(_T_1554, _T_1548) node _T_1556 = or(_T_1555, _T_1549) node _T_1557 = or(_T_1556, _T_1550) node _T_1558 = or(_T_1557, _T_1551) node _T_1559 = or(_T_1558, _T_1552) node _T_1560 = or(_T_1559, _T_1553) wire _WIRE_65 : UInt<3> connect _WIRE_65, _T_1560 connect _WIRE_1.op2_sel, _WIRE_65 node _T_1561 = mux(_T_608, deq_vec[0][0].op1_sel, UInt<1>(0h0)) node _T_1562 = mux(_T_609, deq_vec[1][0].op1_sel, UInt<1>(0h0)) node _T_1563 = mux(_T_610, deq_vec[2][0].op1_sel, UInt<1>(0h0)) node _T_1564 = mux(_T_611, deq_vec[3][0].op1_sel, UInt<1>(0h0)) node _T_1565 = mux(_T_612, deq_vec[4][0].op1_sel, UInt<1>(0h0)) node _T_1566 = mux(_T_613, deq_vec[5][0].op1_sel, UInt<1>(0h0)) node _T_1567 = mux(_T_614, deq_vec[6][0].op1_sel, UInt<1>(0h0)) node _T_1568 = mux(_T_615, deq_vec[7][0].op1_sel, UInt<1>(0h0)) node _T_1569 = or(_T_1561, _T_1562) node _T_1570 = or(_T_1569, _T_1563) node _T_1571 = or(_T_1570, _T_1564) node _T_1572 = or(_T_1571, _T_1565) node _T_1573 = or(_T_1572, _T_1566) node _T_1574 = or(_T_1573, _T_1567) node _T_1575 = or(_T_1574, _T_1568) wire _WIRE_66 : UInt<2> connect _WIRE_66, _T_1575 connect _WIRE_1.op1_sel, _WIRE_66 node _T_1576 = mux(_T_608, deq_vec[0][0].imm_packed, UInt<1>(0h0)) node _T_1577 = mux(_T_609, deq_vec[1][0].imm_packed, UInt<1>(0h0)) node _T_1578 = mux(_T_610, deq_vec[2][0].imm_packed, UInt<1>(0h0)) node _T_1579 = mux(_T_611, deq_vec[3][0].imm_packed, UInt<1>(0h0)) node _T_1580 = mux(_T_612, deq_vec[4][0].imm_packed, UInt<1>(0h0)) node _T_1581 = mux(_T_613, deq_vec[5][0].imm_packed, UInt<1>(0h0)) node _T_1582 = mux(_T_614, deq_vec[6][0].imm_packed, UInt<1>(0h0)) node _T_1583 = mux(_T_615, deq_vec[7][0].imm_packed, UInt<1>(0h0)) node _T_1584 = or(_T_1576, _T_1577) node _T_1585 = or(_T_1584, _T_1578) node _T_1586 = or(_T_1585, _T_1579) node _T_1587 = or(_T_1586, _T_1580) node _T_1588 = or(_T_1587, _T_1581) node _T_1589 = or(_T_1588, _T_1582) node _T_1590 = or(_T_1589, _T_1583) wire _WIRE_67 : UInt<20> connect _WIRE_67, _T_1590 connect _WIRE_1.imm_packed, _WIRE_67 node _T_1591 = mux(_T_608, deq_vec[0][0].pimm, UInt<1>(0h0)) node _T_1592 = mux(_T_609, deq_vec[1][0].pimm, UInt<1>(0h0)) node _T_1593 = mux(_T_610, deq_vec[2][0].pimm, UInt<1>(0h0)) node _T_1594 = mux(_T_611, deq_vec[3][0].pimm, UInt<1>(0h0)) node _T_1595 = mux(_T_612, deq_vec[4][0].pimm, UInt<1>(0h0)) node _T_1596 = mux(_T_613, deq_vec[5][0].pimm, UInt<1>(0h0)) node _T_1597 = mux(_T_614, deq_vec[6][0].pimm, UInt<1>(0h0)) node _T_1598 = mux(_T_615, deq_vec[7][0].pimm, UInt<1>(0h0)) node _T_1599 = or(_T_1591, _T_1592) node _T_1600 = or(_T_1599, _T_1593) node _T_1601 = or(_T_1600, _T_1594) node _T_1602 = or(_T_1601, _T_1595) node _T_1603 = or(_T_1602, _T_1596) node _T_1604 = or(_T_1603, _T_1597) node _T_1605 = or(_T_1604, _T_1598) wire _WIRE_68 : UInt<5> connect _WIRE_68, _T_1605 connect _WIRE_1.pimm, _WIRE_68 node _T_1606 = mux(_T_608, deq_vec[0][0].imm_sel, UInt<1>(0h0)) node _T_1607 = mux(_T_609, deq_vec[1][0].imm_sel, UInt<1>(0h0)) node _T_1608 = mux(_T_610, deq_vec[2][0].imm_sel, UInt<1>(0h0)) node _T_1609 = mux(_T_611, deq_vec[3][0].imm_sel, UInt<1>(0h0)) node _T_1610 = mux(_T_612, deq_vec[4][0].imm_sel, UInt<1>(0h0)) node _T_1611 = mux(_T_613, deq_vec[5][0].imm_sel, UInt<1>(0h0)) node _T_1612 = mux(_T_614, deq_vec[6][0].imm_sel, UInt<1>(0h0)) node _T_1613 = mux(_T_615, deq_vec[7][0].imm_sel, UInt<1>(0h0)) node _T_1614 = or(_T_1606, _T_1607) node _T_1615 = or(_T_1614, _T_1608) node _T_1616 = or(_T_1615, _T_1609) node _T_1617 = or(_T_1616, _T_1610) node _T_1618 = or(_T_1617, _T_1611) node _T_1619 = or(_T_1618, _T_1612) node _T_1620 = or(_T_1619, _T_1613) wire _WIRE_69 : UInt<3> connect _WIRE_69, _T_1620 connect _WIRE_1.imm_sel, _WIRE_69 node _T_1621 = mux(_T_608, deq_vec[0][0].imm_rename, UInt<1>(0h0)) node _T_1622 = mux(_T_609, deq_vec[1][0].imm_rename, UInt<1>(0h0)) node _T_1623 = mux(_T_610, deq_vec[2][0].imm_rename, UInt<1>(0h0)) node _T_1624 = mux(_T_611, deq_vec[3][0].imm_rename, UInt<1>(0h0)) node _T_1625 = mux(_T_612, deq_vec[4][0].imm_rename, UInt<1>(0h0)) node _T_1626 = mux(_T_613, deq_vec[5][0].imm_rename, UInt<1>(0h0)) node _T_1627 = mux(_T_614, deq_vec[6][0].imm_rename, UInt<1>(0h0)) node _T_1628 = mux(_T_615, deq_vec[7][0].imm_rename, UInt<1>(0h0)) node _T_1629 = or(_T_1621, _T_1622) node _T_1630 = or(_T_1629, _T_1623) node _T_1631 = or(_T_1630, _T_1624) node _T_1632 = or(_T_1631, _T_1625) node _T_1633 = or(_T_1632, _T_1626) node _T_1634 = or(_T_1633, _T_1627) node _T_1635 = or(_T_1634, _T_1628) wire _WIRE_70 : UInt<1> connect _WIRE_70, _T_1635 connect _WIRE_1.imm_rename, _WIRE_70 node _T_1636 = mux(_T_608, deq_vec[0][0].taken, UInt<1>(0h0)) node _T_1637 = mux(_T_609, deq_vec[1][0].taken, UInt<1>(0h0)) node _T_1638 = mux(_T_610, deq_vec[2][0].taken, UInt<1>(0h0)) node _T_1639 = mux(_T_611, deq_vec[3][0].taken, UInt<1>(0h0)) node _T_1640 = mux(_T_612, deq_vec[4][0].taken, UInt<1>(0h0)) node _T_1641 = mux(_T_613, deq_vec[5][0].taken, UInt<1>(0h0)) node _T_1642 = mux(_T_614, deq_vec[6][0].taken, UInt<1>(0h0)) node _T_1643 = mux(_T_615, deq_vec[7][0].taken, UInt<1>(0h0)) node _T_1644 = or(_T_1636, _T_1637) node _T_1645 = or(_T_1644, _T_1638) node _T_1646 = or(_T_1645, _T_1639) node _T_1647 = or(_T_1646, _T_1640) node _T_1648 = or(_T_1647, _T_1641) node _T_1649 = or(_T_1648, _T_1642) node _T_1650 = or(_T_1649, _T_1643) wire _WIRE_71 : UInt<1> connect _WIRE_71, _T_1650 connect _WIRE_1.taken, _WIRE_71 node _T_1651 = mux(_T_608, deq_vec[0][0].pc_lob, UInt<1>(0h0)) node _T_1652 = mux(_T_609, deq_vec[1][0].pc_lob, UInt<1>(0h0)) node _T_1653 = mux(_T_610, deq_vec[2][0].pc_lob, UInt<1>(0h0)) node _T_1654 = mux(_T_611, deq_vec[3][0].pc_lob, UInt<1>(0h0)) node _T_1655 = mux(_T_612, deq_vec[4][0].pc_lob, UInt<1>(0h0)) node _T_1656 = mux(_T_613, deq_vec[5][0].pc_lob, UInt<1>(0h0)) node _T_1657 = mux(_T_614, deq_vec[6][0].pc_lob, UInt<1>(0h0)) node _T_1658 = mux(_T_615, deq_vec[7][0].pc_lob, UInt<1>(0h0)) node _T_1659 = or(_T_1651, _T_1652) node _T_1660 = or(_T_1659, _T_1653) node _T_1661 = or(_T_1660, _T_1654) node _T_1662 = or(_T_1661, _T_1655) node _T_1663 = or(_T_1662, _T_1656) node _T_1664 = or(_T_1663, _T_1657) node _T_1665 = or(_T_1664, _T_1658) wire _WIRE_72 : UInt<6> connect _WIRE_72, _T_1665 connect _WIRE_1.pc_lob, _WIRE_72 node _T_1666 = mux(_T_608, deq_vec[0][0].edge_inst, UInt<1>(0h0)) node _T_1667 = mux(_T_609, deq_vec[1][0].edge_inst, UInt<1>(0h0)) node _T_1668 = mux(_T_610, deq_vec[2][0].edge_inst, UInt<1>(0h0)) node _T_1669 = mux(_T_611, deq_vec[3][0].edge_inst, UInt<1>(0h0)) node _T_1670 = mux(_T_612, deq_vec[4][0].edge_inst, UInt<1>(0h0)) node _T_1671 = mux(_T_613, deq_vec[5][0].edge_inst, UInt<1>(0h0)) node _T_1672 = mux(_T_614, deq_vec[6][0].edge_inst, UInt<1>(0h0)) node _T_1673 = mux(_T_615, deq_vec[7][0].edge_inst, UInt<1>(0h0)) node _T_1674 = or(_T_1666, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = or(_T_1675, _T_1669) node _T_1677 = or(_T_1676, _T_1670) node _T_1678 = or(_T_1677, _T_1671) node _T_1679 = or(_T_1678, _T_1672) node _T_1680 = or(_T_1679, _T_1673) wire _WIRE_73 : UInt<1> connect _WIRE_73, _T_1680 connect _WIRE_1.edge_inst, _WIRE_73 node _T_1681 = mux(_T_608, deq_vec[0][0].ftq_idx, UInt<1>(0h0)) node _T_1682 = mux(_T_609, deq_vec[1][0].ftq_idx, UInt<1>(0h0)) node _T_1683 = mux(_T_610, deq_vec[2][0].ftq_idx, UInt<1>(0h0)) node _T_1684 = mux(_T_611, deq_vec[3][0].ftq_idx, UInt<1>(0h0)) node _T_1685 = mux(_T_612, deq_vec[4][0].ftq_idx, UInt<1>(0h0)) node _T_1686 = mux(_T_613, deq_vec[5][0].ftq_idx, UInt<1>(0h0)) node _T_1687 = mux(_T_614, deq_vec[6][0].ftq_idx, UInt<1>(0h0)) node _T_1688 = mux(_T_615, deq_vec[7][0].ftq_idx, UInt<1>(0h0)) node _T_1689 = or(_T_1681, _T_1682) node _T_1690 = or(_T_1689, _T_1683) node _T_1691 = or(_T_1690, _T_1684) node _T_1692 = or(_T_1691, _T_1685) node _T_1693 = or(_T_1692, _T_1686) node _T_1694 = or(_T_1693, _T_1687) node _T_1695 = or(_T_1694, _T_1688) wire _WIRE_74 : UInt<5> connect _WIRE_74, _T_1695 connect _WIRE_1.ftq_idx, _WIRE_74 node _T_1696 = mux(_T_608, deq_vec[0][0].is_mov, UInt<1>(0h0)) node _T_1697 = mux(_T_609, deq_vec[1][0].is_mov, UInt<1>(0h0)) node _T_1698 = mux(_T_610, deq_vec[2][0].is_mov, UInt<1>(0h0)) node _T_1699 = mux(_T_611, deq_vec[3][0].is_mov, UInt<1>(0h0)) node _T_1700 = mux(_T_612, deq_vec[4][0].is_mov, UInt<1>(0h0)) node _T_1701 = mux(_T_613, deq_vec[5][0].is_mov, UInt<1>(0h0)) node _T_1702 = mux(_T_614, deq_vec[6][0].is_mov, UInt<1>(0h0)) node _T_1703 = mux(_T_615, deq_vec[7][0].is_mov, UInt<1>(0h0)) node _T_1704 = or(_T_1696, _T_1697) node _T_1705 = or(_T_1704, _T_1698) node _T_1706 = or(_T_1705, _T_1699) node _T_1707 = or(_T_1706, _T_1700) node _T_1708 = or(_T_1707, _T_1701) node _T_1709 = or(_T_1708, _T_1702) node _T_1710 = or(_T_1709, _T_1703) wire _WIRE_75 : UInt<1> connect _WIRE_75, _T_1710 connect _WIRE_1.is_mov, _WIRE_75 node _T_1711 = mux(_T_608, deq_vec[0][0].is_rocc, UInt<1>(0h0)) node _T_1712 = mux(_T_609, deq_vec[1][0].is_rocc, UInt<1>(0h0)) node _T_1713 = mux(_T_610, deq_vec[2][0].is_rocc, UInt<1>(0h0)) node _T_1714 = mux(_T_611, deq_vec[3][0].is_rocc, UInt<1>(0h0)) node _T_1715 = mux(_T_612, deq_vec[4][0].is_rocc, UInt<1>(0h0)) node _T_1716 = mux(_T_613, deq_vec[5][0].is_rocc, UInt<1>(0h0)) node _T_1717 = mux(_T_614, deq_vec[6][0].is_rocc, UInt<1>(0h0)) node _T_1718 = mux(_T_615, deq_vec[7][0].is_rocc, UInt<1>(0h0)) node _T_1719 = or(_T_1711, _T_1712) node _T_1720 = or(_T_1719, _T_1713) node _T_1721 = or(_T_1720, _T_1714) node _T_1722 = or(_T_1721, _T_1715) node _T_1723 = or(_T_1722, _T_1716) node _T_1724 = or(_T_1723, _T_1717) node _T_1725 = or(_T_1724, _T_1718) wire _WIRE_76 : UInt<1> connect _WIRE_76, _T_1725 connect _WIRE_1.is_rocc, _WIRE_76 node _T_1726 = mux(_T_608, deq_vec[0][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1727 = mux(_T_609, deq_vec[1][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1728 = mux(_T_610, deq_vec[2][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1729 = mux(_T_611, deq_vec[3][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1730 = mux(_T_612, deq_vec[4][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1731 = mux(_T_613, deq_vec[5][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1732 = mux(_T_614, deq_vec[6][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1733 = mux(_T_615, deq_vec[7][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1734 = or(_T_1726, _T_1727) node _T_1735 = or(_T_1734, _T_1728) node _T_1736 = or(_T_1735, _T_1729) node _T_1737 = or(_T_1736, _T_1730) node _T_1738 = or(_T_1737, _T_1731) node _T_1739 = or(_T_1738, _T_1732) node _T_1740 = or(_T_1739, _T_1733) wire _WIRE_77 : UInt<1> connect _WIRE_77, _T_1740 connect _WIRE_1.is_sys_pc2epc, _WIRE_77 node _T_1741 = mux(_T_608, deq_vec[0][0].is_eret, UInt<1>(0h0)) node _T_1742 = mux(_T_609, deq_vec[1][0].is_eret, UInt<1>(0h0)) node _T_1743 = mux(_T_610, deq_vec[2][0].is_eret, UInt<1>(0h0)) node _T_1744 = mux(_T_611, deq_vec[3][0].is_eret, UInt<1>(0h0)) node _T_1745 = mux(_T_612, deq_vec[4][0].is_eret, UInt<1>(0h0)) node _T_1746 = mux(_T_613, deq_vec[5][0].is_eret, UInt<1>(0h0)) node _T_1747 = mux(_T_614, deq_vec[6][0].is_eret, UInt<1>(0h0)) node _T_1748 = mux(_T_615, deq_vec[7][0].is_eret, UInt<1>(0h0)) node _T_1749 = or(_T_1741, _T_1742) node _T_1750 = or(_T_1749, _T_1743) node _T_1751 = or(_T_1750, _T_1744) node _T_1752 = or(_T_1751, _T_1745) node _T_1753 = or(_T_1752, _T_1746) node _T_1754 = or(_T_1753, _T_1747) node _T_1755 = or(_T_1754, _T_1748) wire _WIRE_78 : UInt<1> connect _WIRE_78, _T_1755 connect _WIRE_1.is_eret, _WIRE_78 node _T_1756 = mux(_T_608, deq_vec[0][0].is_amo, UInt<1>(0h0)) node _T_1757 = mux(_T_609, deq_vec[1][0].is_amo, UInt<1>(0h0)) node _T_1758 = mux(_T_610, deq_vec[2][0].is_amo, UInt<1>(0h0)) node _T_1759 = mux(_T_611, deq_vec[3][0].is_amo, UInt<1>(0h0)) node _T_1760 = mux(_T_612, deq_vec[4][0].is_amo, UInt<1>(0h0)) node _T_1761 = mux(_T_613, deq_vec[5][0].is_amo, UInt<1>(0h0)) node _T_1762 = mux(_T_614, deq_vec[6][0].is_amo, UInt<1>(0h0)) node _T_1763 = mux(_T_615, deq_vec[7][0].is_amo, UInt<1>(0h0)) node _T_1764 = or(_T_1756, _T_1757) node _T_1765 = or(_T_1764, _T_1758) node _T_1766 = or(_T_1765, _T_1759) node _T_1767 = or(_T_1766, _T_1760) node _T_1768 = or(_T_1767, _T_1761) node _T_1769 = or(_T_1768, _T_1762) node _T_1770 = or(_T_1769, _T_1763) wire _WIRE_79 : UInt<1> connect _WIRE_79, _T_1770 connect _WIRE_1.is_amo, _WIRE_79 node _T_1771 = mux(_T_608, deq_vec[0][0].is_sfence, UInt<1>(0h0)) node _T_1772 = mux(_T_609, deq_vec[1][0].is_sfence, UInt<1>(0h0)) node _T_1773 = mux(_T_610, deq_vec[2][0].is_sfence, UInt<1>(0h0)) node _T_1774 = mux(_T_611, deq_vec[3][0].is_sfence, UInt<1>(0h0)) node _T_1775 = mux(_T_612, deq_vec[4][0].is_sfence, UInt<1>(0h0)) node _T_1776 = mux(_T_613, deq_vec[5][0].is_sfence, UInt<1>(0h0)) node _T_1777 = mux(_T_614, deq_vec[6][0].is_sfence, UInt<1>(0h0)) node _T_1778 = mux(_T_615, deq_vec[7][0].is_sfence, UInt<1>(0h0)) node _T_1779 = or(_T_1771, _T_1772) node _T_1780 = or(_T_1779, _T_1773) node _T_1781 = or(_T_1780, _T_1774) node _T_1782 = or(_T_1781, _T_1775) node _T_1783 = or(_T_1782, _T_1776) node _T_1784 = or(_T_1783, _T_1777) node _T_1785 = or(_T_1784, _T_1778) wire _WIRE_80 : UInt<1> connect _WIRE_80, _T_1785 connect _WIRE_1.is_sfence, _WIRE_80 node _T_1786 = mux(_T_608, deq_vec[0][0].is_fencei, UInt<1>(0h0)) node _T_1787 = mux(_T_609, deq_vec[1][0].is_fencei, UInt<1>(0h0)) node _T_1788 = mux(_T_610, deq_vec[2][0].is_fencei, UInt<1>(0h0)) node _T_1789 = mux(_T_611, deq_vec[3][0].is_fencei, UInt<1>(0h0)) node _T_1790 = mux(_T_612, deq_vec[4][0].is_fencei, UInt<1>(0h0)) node _T_1791 = mux(_T_613, deq_vec[5][0].is_fencei, UInt<1>(0h0)) node _T_1792 = mux(_T_614, deq_vec[6][0].is_fencei, UInt<1>(0h0)) node _T_1793 = mux(_T_615, deq_vec[7][0].is_fencei, UInt<1>(0h0)) node _T_1794 = or(_T_1786, _T_1787) node _T_1795 = or(_T_1794, _T_1788) node _T_1796 = or(_T_1795, _T_1789) node _T_1797 = or(_T_1796, _T_1790) node _T_1798 = or(_T_1797, _T_1791) node _T_1799 = or(_T_1798, _T_1792) node _T_1800 = or(_T_1799, _T_1793) wire _WIRE_81 : UInt<1> connect _WIRE_81, _T_1800 connect _WIRE_1.is_fencei, _WIRE_81 node _T_1801 = mux(_T_608, deq_vec[0][0].is_fence, UInt<1>(0h0)) node _T_1802 = mux(_T_609, deq_vec[1][0].is_fence, UInt<1>(0h0)) node _T_1803 = mux(_T_610, deq_vec[2][0].is_fence, UInt<1>(0h0)) node _T_1804 = mux(_T_611, deq_vec[3][0].is_fence, UInt<1>(0h0)) node _T_1805 = mux(_T_612, deq_vec[4][0].is_fence, UInt<1>(0h0)) node _T_1806 = mux(_T_613, deq_vec[5][0].is_fence, UInt<1>(0h0)) node _T_1807 = mux(_T_614, deq_vec[6][0].is_fence, UInt<1>(0h0)) node _T_1808 = mux(_T_615, deq_vec[7][0].is_fence, UInt<1>(0h0)) node _T_1809 = or(_T_1801, _T_1802) node _T_1810 = or(_T_1809, _T_1803) node _T_1811 = or(_T_1810, _T_1804) node _T_1812 = or(_T_1811, _T_1805) node _T_1813 = or(_T_1812, _T_1806) node _T_1814 = or(_T_1813, _T_1807) node _T_1815 = or(_T_1814, _T_1808) wire _WIRE_82 : UInt<1> connect _WIRE_82, _T_1815 connect _WIRE_1.is_fence, _WIRE_82 node _T_1816 = mux(_T_608, deq_vec[0][0].is_sfb, UInt<1>(0h0)) node _T_1817 = mux(_T_609, deq_vec[1][0].is_sfb, UInt<1>(0h0)) node _T_1818 = mux(_T_610, deq_vec[2][0].is_sfb, UInt<1>(0h0)) node _T_1819 = mux(_T_611, deq_vec[3][0].is_sfb, UInt<1>(0h0)) node _T_1820 = mux(_T_612, deq_vec[4][0].is_sfb, UInt<1>(0h0)) node _T_1821 = mux(_T_613, deq_vec[5][0].is_sfb, UInt<1>(0h0)) node _T_1822 = mux(_T_614, deq_vec[6][0].is_sfb, UInt<1>(0h0)) node _T_1823 = mux(_T_615, deq_vec[7][0].is_sfb, UInt<1>(0h0)) node _T_1824 = or(_T_1816, _T_1817) node _T_1825 = or(_T_1824, _T_1818) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = or(_T_1828, _T_1822) node _T_1830 = or(_T_1829, _T_1823) wire _WIRE_83 : UInt<1> connect _WIRE_83, _T_1830 connect _WIRE_1.is_sfb, _WIRE_83 node _T_1831 = mux(_T_608, deq_vec[0][0].br_type, UInt<1>(0h0)) node _T_1832 = mux(_T_609, deq_vec[1][0].br_type, UInt<1>(0h0)) node _T_1833 = mux(_T_610, deq_vec[2][0].br_type, UInt<1>(0h0)) node _T_1834 = mux(_T_611, deq_vec[3][0].br_type, UInt<1>(0h0)) node _T_1835 = mux(_T_612, deq_vec[4][0].br_type, UInt<1>(0h0)) node _T_1836 = mux(_T_613, deq_vec[5][0].br_type, UInt<1>(0h0)) node _T_1837 = mux(_T_614, deq_vec[6][0].br_type, UInt<1>(0h0)) node _T_1838 = mux(_T_615, deq_vec[7][0].br_type, UInt<1>(0h0)) node _T_1839 = or(_T_1831, _T_1832) node _T_1840 = or(_T_1839, _T_1833) node _T_1841 = or(_T_1840, _T_1834) node _T_1842 = or(_T_1841, _T_1835) node _T_1843 = or(_T_1842, _T_1836) node _T_1844 = or(_T_1843, _T_1837) node _T_1845 = or(_T_1844, _T_1838) wire _WIRE_84 : UInt<4> connect _WIRE_84, _T_1845 connect _WIRE_1.br_type, _WIRE_84 node _T_1846 = mux(_T_608, deq_vec[0][0].br_tag, UInt<1>(0h0)) node _T_1847 = mux(_T_609, deq_vec[1][0].br_tag, UInt<1>(0h0)) node _T_1848 = mux(_T_610, deq_vec[2][0].br_tag, UInt<1>(0h0)) node _T_1849 = mux(_T_611, deq_vec[3][0].br_tag, UInt<1>(0h0)) node _T_1850 = mux(_T_612, deq_vec[4][0].br_tag, UInt<1>(0h0)) node _T_1851 = mux(_T_613, deq_vec[5][0].br_tag, UInt<1>(0h0)) node _T_1852 = mux(_T_614, deq_vec[6][0].br_tag, UInt<1>(0h0)) node _T_1853 = mux(_T_615, deq_vec[7][0].br_tag, UInt<1>(0h0)) node _T_1854 = or(_T_1846, _T_1847) node _T_1855 = or(_T_1854, _T_1848) node _T_1856 = or(_T_1855, _T_1849) node _T_1857 = or(_T_1856, _T_1850) node _T_1858 = or(_T_1857, _T_1851) node _T_1859 = or(_T_1858, _T_1852) node _T_1860 = or(_T_1859, _T_1853) wire _WIRE_85 : UInt<4> connect _WIRE_85, _T_1860 connect _WIRE_1.br_tag, _WIRE_85 node _T_1861 = mux(_T_608, deq_vec[0][0].br_mask, UInt<1>(0h0)) node _T_1862 = mux(_T_609, deq_vec[1][0].br_mask, UInt<1>(0h0)) node _T_1863 = mux(_T_610, deq_vec[2][0].br_mask, UInt<1>(0h0)) node _T_1864 = mux(_T_611, deq_vec[3][0].br_mask, UInt<1>(0h0)) node _T_1865 = mux(_T_612, deq_vec[4][0].br_mask, UInt<1>(0h0)) node _T_1866 = mux(_T_613, deq_vec[5][0].br_mask, UInt<1>(0h0)) node _T_1867 = mux(_T_614, deq_vec[6][0].br_mask, UInt<1>(0h0)) node _T_1868 = mux(_T_615, deq_vec[7][0].br_mask, UInt<1>(0h0)) node _T_1869 = or(_T_1861, _T_1862) node _T_1870 = or(_T_1869, _T_1863) node _T_1871 = or(_T_1870, _T_1864) node _T_1872 = or(_T_1871, _T_1865) node _T_1873 = or(_T_1872, _T_1866) node _T_1874 = or(_T_1873, _T_1867) node _T_1875 = or(_T_1874, _T_1868) wire _WIRE_86 : UInt<16> connect _WIRE_86, _T_1875 connect _WIRE_1.br_mask, _WIRE_86 node _T_1876 = mux(_T_608, deq_vec[0][0].dis_col_sel, UInt<1>(0h0)) node _T_1877 = mux(_T_609, deq_vec[1][0].dis_col_sel, UInt<1>(0h0)) node _T_1878 = mux(_T_610, deq_vec[2][0].dis_col_sel, UInt<1>(0h0)) node _T_1879 = mux(_T_611, deq_vec[3][0].dis_col_sel, UInt<1>(0h0)) node _T_1880 = mux(_T_612, deq_vec[4][0].dis_col_sel, UInt<1>(0h0)) node _T_1881 = mux(_T_613, deq_vec[5][0].dis_col_sel, UInt<1>(0h0)) node _T_1882 = mux(_T_614, deq_vec[6][0].dis_col_sel, UInt<1>(0h0)) node _T_1883 = mux(_T_615, deq_vec[7][0].dis_col_sel, UInt<1>(0h0)) node _T_1884 = or(_T_1876, _T_1877) node _T_1885 = or(_T_1884, _T_1878) node _T_1886 = or(_T_1885, _T_1879) node _T_1887 = or(_T_1886, _T_1880) node _T_1888 = or(_T_1887, _T_1881) node _T_1889 = or(_T_1888, _T_1882) node _T_1890 = or(_T_1889, _T_1883) wire _WIRE_87 : UInt<3> connect _WIRE_87, _T_1890 connect _WIRE_1.dis_col_sel, _WIRE_87 node _T_1891 = mux(_T_608, deq_vec[0][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1892 = mux(_T_609, deq_vec[1][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1893 = mux(_T_610, deq_vec[2][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1894 = mux(_T_611, deq_vec[3][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1895 = mux(_T_612, deq_vec[4][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1896 = mux(_T_613, deq_vec[5][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1897 = mux(_T_614, deq_vec[6][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1898 = mux(_T_615, deq_vec[7][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1899 = or(_T_1891, _T_1892) node _T_1900 = or(_T_1899, _T_1893) node _T_1901 = or(_T_1900, _T_1894) node _T_1902 = or(_T_1901, _T_1895) node _T_1903 = or(_T_1902, _T_1896) node _T_1904 = or(_T_1903, _T_1897) node _T_1905 = or(_T_1904, _T_1898) wire _WIRE_88 : UInt<1> connect _WIRE_88, _T_1905 connect _WIRE_1.iw_p3_bypass_hint, _WIRE_88 node _T_1906 = mux(_T_608, deq_vec[0][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1907 = mux(_T_609, deq_vec[1][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1908 = mux(_T_610, deq_vec[2][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1909 = mux(_T_611, deq_vec[3][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1910 = mux(_T_612, deq_vec[4][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1911 = mux(_T_613, deq_vec[5][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1912 = mux(_T_614, deq_vec[6][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1913 = mux(_T_615, deq_vec[7][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1914 = or(_T_1906, _T_1907) node _T_1915 = or(_T_1914, _T_1908) node _T_1916 = or(_T_1915, _T_1909) node _T_1917 = or(_T_1916, _T_1910) node _T_1918 = or(_T_1917, _T_1911) node _T_1919 = or(_T_1918, _T_1912) node _T_1920 = or(_T_1919, _T_1913) wire _WIRE_89 : UInt<1> connect _WIRE_89, _T_1920 connect _WIRE_1.iw_p2_bypass_hint, _WIRE_89 node _T_1921 = mux(_T_608, deq_vec[0][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1922 = mux(_T_609, deq_vec[1][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1923 = mux(_T_610, deq_vec[2][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1924 = mux(_T_611, deq_vec[3][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1925 = mux(_T_612, deq_vec[4][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1926 = mux(_T_613, deq_vec[5][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1927 = mux(_T_614, deq_vec[6][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1928 = mux(_T_615, deq_vec[7][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1929 = or(_T_1921, _T_1922) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = or(_T_1930, _T_1924) node _T_1932 = or(_T_1931, _T_1925) node _T_1933 = or(_T_1932, _T_1926) node _T_1934 = or(_T_1933, _T_1927) node _T_1935 = or(_T_1934, _T_1928) wire _WIRE_90 : UInt<1> connect _WIRE_90, _T_1935 connect _WIRE_1.iw_p1_bypass_hint, _WIRE_90 node _T_1936 = mux(_T_608, deq_vec[0][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1937 = mux(_T_609, deq_vec[1][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1938 = mux(_T_610, deq_vec[2][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1939 = mux(_T_611, deq_vec[3][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1940 = mux(_T_612, deq_vec[4][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1941 = mux(_T_613, deq_vec[5][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1942 = mux(_T_614, deq_vec[6][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1943 = mux(_T_615, deq_vec[7][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1944 = or(_T_1936, _T_1937) node _T_1945 = or(_T_1944, _T_1938) node _T_1946 = or(_T_1945, _T_1939) node _T_1947 = or(_T_1946, _T_1940) node _T_1948 = or(_T_1947, _T_1941) node _T_1949 = or(_T_1948, _T_1942) node _T_1950 = or(_T_1949, _T_1943) wire _WIRE_91 : UInt<3> connect _WIRE_91, _T_1950 connect _WIRE_1.iw_p2_speculative_child, _WIRE_91 node _T_1951 = mux(_T_608, deq_vec[0][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1952 = mux(_T_609, deq_vec[1][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1953 = mux(_T_610, deq_vec[2][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1954 = mux(_T_611, deq_vec[3][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1955 = mux(_T_612, deq_vec[4][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1956 = mux(_T_613, deq_vec[5][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1957 = mux(_T_614, deq_vec[6][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1958 = mux(_T_615, deq_vec[7][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1959 = or(_T_1951, _T_1952) node _T_1960 = or(_T_1959, _T_1953) node _T_1961 = or(_T_1960, _T_1954) node _T_1962 = or(_T_1961, _T_1955) node _T_1963 = or(_T_1962, _T_1956) node _T_1964 = or(_T_1963, _T_1957) node _T_1965 = or(_T_1964, _T_1958) wire _WIRE_92 : UInt<3> connect _WIRE_92, _T_1965 connect _WIRE_1.iw_p1_speculative_child, _WIRE_92 node _T_1966 = mux(_T_608, deq_vec[0][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1967 = mux(_T_609, deq_vec[1][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1968 = mux(_T_610, deq_vec[2][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1969 = mux(_T_611, deq_vec[3][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1970 = mux(_T_612, deq_vec[4][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1971 = mux(_T_613, deq_vec[5][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1972 = mux(_T_614, deq_vec[6][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1973 = mux(_T_615, deq_vec[7][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1974 = or(_T_1966, _T_1967) node _T_1975 = or(_T_1974, _T_1968) node _T_1976 = or(_T_1975, _T_1969) node _T_1977 = or(_T_1976, _T_1970) node _T_1978 = or(_T_1977, _T_1971) node _T_1979 = or(_T_1978, _T_1972) node _T_1980 = or(_T_1979, _T_1973) wire _WIRE_93 : UInt<1> connect _WIRE_93, _T_1980 connect _WIRE_1.iw_issued_partial_dgen, _WIRE_93 node _T_1981 = mux(_T_608, deq_vec[0][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1982 = mux(_T_609, deq_vec[1][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1983 = mux(_T_610, deq_vec[2][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1984 = mux(_T_611, deq_vec[3][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1985 = mux(_T_612, deq_vec[4][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1986 = mux(_T_613, deq_vec[5][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1987 = mux(_T_614, deq_vec[6][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1988 = mux(_T_615, deq_vec[7][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1989 = or(_T_1981, _T_1982) node _T_1990 = or(_T_1989, _T_1983) node _T_1991 = or(_T_1990, _T_1984) node _T_1992 = or(_T_1991, _T_1985) node _T_1993 = or(_T_1992, _T_1986) node _T_1994 = or(_T_1993, _T_1987) node _T_1995 = or(_T_1994, _T_1988) wire _WIRE_94 : UInt<1> connect _WIRE_94, _T_1995 connect _WIRE_1.iw_issued_partial_agen, _WIRE_94 node _T_1996 = mux(_T_608, deq_vec[0][0].iw_issued, UInt<1>(0h0)) node _T_1997 = mux(_T_609, deq_vec[1][0].iw_issued, UInt<1>(0h0)) node _T_1998 = mux(_T_610, deq_vec[2][0].iw_issued, UInt<1>(0h0)) node _T_1999 = mux(_T_611, deq_vec[3][0].iw_issued, UInt<1>(0h0)) node _T_2000 = mux(_T_612, deq_vec[4][0].iw_issued, UInt<1>(0h0)) node _T_2001 = mux(_T_613, deq_vec[5][0].iw_issued, UInt<1>(0h0)) node _T_2002 = mux(_T_614, deq_vec[6][0].iw_issued, UInt<1>(0h0)) node _T_2003 = mux(_T_615, deq_vec[7][0].iw_issued, UInt<1>(0h0)) node _T_2004 = or(_T_1996, _T_1997) node _T_2005 = or(_T_2004, _T_1998) node _T_2006 = or(_T_2005, _T_1999) node _T_2007 = or(_T_2006, _T_2000) node _T_2008 = or(_T_2007, _T_2001) node _T_2009 = or(_T_2008, _T_2002) node _T_2010 = or(_T_2009, _T_2003) wire _WIRE_95 : UInt<1> connect _WIRE_95, _T_2010 connect _WIRE_1.iw_issued, _WIRE_95 wire _WIRE_96 : UInt<1>[10] node _T_2011 = mux(_T_608, deq_vec[0][0].fu_code[0], UInt<1>(0h0)) node _T_2012 = mux(_T_609, deq_vec[1][0].fu_code[0], UInt<1>(0h0)) node _T_2013 = mux(_T_610, deq_vec[2][0].fu_code[0], UInt<1>(0h0)) node _T_2014 = mux(_T_611, deq_vec[3][0].fu_code[0], UInt<1>(0h0)) node _T_2015 = mux(_T_612, deq_vec[4][0].fu_code[0], UInt<1>(0h0)) node _T_2016 = mux(_T_613, deq_vec[5][0].fu_code[0], UInt<1>(0h0)) node _T_2017 = mux(_T_614, deq_vec[6][0].fu_code[0], UInt<1>(0h0)) node _T_2018 = mux(_T_615, deq_vec[7][0].fu_code[0], UInt<1>(0h0)) node _T_2019 = or(_T_2011, _T_2012) node _T_2020 = or(_T_2019, _T_2013) node _T_2021 = or(_T_2020, _T_2014) node _T_2022 = or(_T_2021, _T_2015) node _T_2023 = or(_T_2022, _T_2016) node _T_2024 = or(_T_2023, _T_2017) node _T_2025 = or(_T_2024, _T_2018) wire _WIRE_97 : UInt<1> connect _WIRE_97, _T_2025 connect _WIRE_96[0], _WIRE_97 node _T_2026 = mux(_T_608, deq_vec[0][0].fu_code[1], UInt<1>(0h0)) node _T_2027 = mux(_T_609, deq_vec[1][0].fu_code[1], UInt<1>(0h0)) node _T_2028 = mux(_T_610, deq_vec[2][0].fu_code[1], UInt<1>(0h0)) node _T_2029 = mux(_T_611, deq_vec[3][0].fu_code[1], UInt<1>(0h0)) node _T_2030 = mux(_T_612, deq_vec[4][0].fu_code[1], UInt<1>(0h0)) node _T_2031 = mux(_T_613, deq_vec[5][0].fu_code[1], UInt<1>(0h0)) node _T_2032 = mux(_T_614, deq_vec[6][0].fu_code[1], UInt<1>(0h0)) node _T_2033 = mux(_T_615, deq_vec[7][0].fu_code[1], UInt<1>(0h0)) node _T_2034 = or(_T_2026, _T_2027) node _T_2035 = or(_T_2034, _T_2028) node _T_2036 = or(_T_2035, _T_2029) node _T_2037 = or(_T_2036, _T_2030) node _T_2038 = or(_T_2037, _T_2031) node _T_2039 = or(_T_2038, _T_2032) node _T_2040 = or(_T_2039, _T_2033) wire _WIRE_98 : UInt<1> connect _WIRE_98, _T_2040 connect _WIRE_96[1], _WIRE_98 node _T_2041 = mux(_T_608, deq_vec[0][0].fu_code[2], UInt<1>(0h0)) node _T_2042 = mux(_T_609, deq_vec[1][0].fu_code[2], UInt<1>(0h0)) node _T_2043 = mux(_T_610, deq_vec[2][0].fu_code[2], UInt<1>(0h0)) node _T_2044 = mux(_T_611, deq_vec[3][0].fu_code[2], UInt<1>(0h0)) node _T_2045 = mux(_T_612, deq_vec[4][0].fu_code[2], UInt<1>(0h0)) node _T_2046 = mux(_T_613, deq_vec[5][0].fu_code[2], UInt<1>(0h0)) node _T_2047 = mux(_T_614, deq_vec[6][0].fu_code[2], UInt<1>(0h0)) node _T_2048 = mux(_T_615, deq_vec[7][0].fu_code[2], UInt<1>(0h0)) node _T_2049 = or(_T_2041, _T_2042) node _T_2050 = or(_T_2049, _T_2043) node _T_2051 = or(_T_2050, _T_2044) node _T_2052 = or(_T_2051, _T_2045) node _T_2053 = or(_T_2052, _T_2046) node _T_2054 = or(_T_2053, _T_2047) node _T_2055 = or(_T_2054, _T_2048) wire _WIRE_99 : UInt<1> connect _WIRE_99, _T_2055 connect _WIRE_96[2], _WIRE_99 node _T_2056 = mux(_T_608, deq_vec[0][0].fu_code[3], UInt<1>(0h0)) node _T_2057 = mux(_T_609, deq_vec[1][0].fu_code[3], UInt<1>(0h0)) node _T_2058 = mux(_T_610, deq_vec[2][0].fu_code[3], UInt<1>(0h0)) node _T_2059 = mux(_T_611, deq_vec[3][0].fu_code[3], UInt<1>(0h0)) node _T_2060 = mux(_T_612, deq_vec[4][0].fu_code[3], UInt<1>(0h0)) node _T_2061 = mux(_T_613, deq_vec[5][0].fu_code[3], UInt<1>(0h0)) node _T_2062 = mux(_T_614, deq_vec[6][0].fu_code[3], UInt<1>(0h0)) node _T_2063 = mux(_T_615, deq_vec[7][0].fu_code[3], UInt<1>(0h0)) node _T_2064 = or(_T_2056, _T_2057) node _T_2065 = or(_T_2064, _T_2058) node _T_2066 = or(_T_2065, _T_2059) node _T_2067 = or(_T_2066, _T_2060) node _T_2068 = or(_T_2067, _T_2061) node _T_2069 = or(_T_2068, _T_2062) node _T_2070 = or(_T_2069, _T_2063) wire _WIRE_100 : UInt<1> connect _WIRE_100, _T_2070 connect _WIRE_96[3], _WIRE_100 node _T_2071 = mux(_T_608, deq_vec[0][0].fu_code[4], UInt<1>(0h0)) node _T_2072 = mux(_T_609, deq_vec[1][0].fu_code[4], UInt<1>(0h0)) node _T_2073 = mux(_T_610, deq_vec[2][0].fu_code[4], UInt<1>(0h0)) node _T_2074 = mux(_T_611, deq_vec[3][0].fu_code[4], UInt<1>(0h0)) node _T_2075 = mux(_T_612, deq_vec[4][0].fu_code[4], UInt<1>(0h0)) node _T_2076 = mux(_T_613, deq_vec[5][0].fu_code[4], UInt<1>(0h0)) node _T_2077 = mux(_T_614, deq_vec[6][0].fu_code[4], UInt<1>(0h0)) node _T_2078 = mux(_T_615, deq_vec[7][0].fu_code[4], UInt<1>(0h0)) node _T_2079 = or(_T_2071, _T_2072) node _T_2080 = or(_T_2079, _T_2073) node _T_2081 = or(_T_2080, _T_2074) node _T_2082 = or(_T_2081, _T_2075) node _T_2083 = or(_T_2082, _T_2076) node _T_2084 = or(_T_2083, _T_2077) node _T_2085 = or(_T_2084, _T_2078) wire _WIRE_101 : UInt<1> connect _WIRE_101, _T_2085 connect _WIRE_96[4], _WIRE_101 node _T_2086 = mux(_T_608, deq_vec[0][0].fu_code[5], UInt<1>(0h0)) node _T_2087 = mux(_T_609, deq_vec[1][0].fu_code[5], UInt<1>(0h0)) node _T_2088 = mux(_T_610, deq_vec[2][0].fu_code[5], UInt<1>(0h0)) node _T_2089 = mux(_T_611, deq_vec[3][0].fu_code[5], UInt<1>(0h0)) node _T_2090 = mux(_T_612, deq_vec[4][0].fu_code[5], UInt<1>(0h0)) node _T_2091 = mux(_T_613, deq_vec[5][0].fu_code[5], UInt<1>(0h0)) node _T_2092 = mux(_T_614, deq_vec[6][0].fu_code[5], UInt<1>(0h0)) node _T_2093 = mux(_T_615, deq_vec[7][0].fu_code[5], UInt<1>(0h0)) node _T_2094 = or(_T_2086, _T_2087) node _T_2095 = or(_T_2094, _T_2088) node _T_2096 = or(_T_2095, _T_2089) node _T_2097 = or(_T_2096, _T_2090) node _T_2098 = or(_T_2097, _T_2091) node _T_2099 = or(_T_2098, _T_2092) node _T_2100 = or(_T_2099, _T_2093) wire _WIRE_102 : UInt<1> connect _WIRE_102, _T_2100 connect _WIRE_96[5], _WIRE_102 node _T_2101 = mux(_T_608, deq_vec[0][0].fu_code[6], UInt<1>(0h0)) node _T_2102 = mux(_T_609, deq_vec[1][0].fu_code[6], UInt<1>(0h0)) node _T_2103 = mux(_T_610, deq_vec[2][0].fu_code[6], UInt<1>(0h0)) node _T_2104 = mux(_T_611, deq_vec[3][0].fu_code[6], UInt<1>(0h0)) node _T_2105 = mux(_T_612, deq_vec[4][0].fu_code[6], UInt<1>(0h0)) node _T_2106 = mux(_T_613, deq_vec[5][0].fu_code[6], UInt<1>(0h0)) node _T_2107 = mux(_T_614, deq_vec[6][0].fu_code[6], UInt<1>(0h0)) node _T_2108 = mux(_T_615, deq_vec[7][0].fu_code[6], UInt<1>(0h0)) node _T_2109 = or(_T_2101, _T_2102) node _T_2110 = or(_T_2109, _T_2103) node _T_2111 = or(_T_2110, _T_2104) node _T_2112 = or(_T_2111, _T_2105) node _T_2113 = or(_T_2112, _T_2106) node _T_2114 = or(_T_2113, _T_2107) node _T_2115 = or(_T_2114, _T_2108) wire _WIRE_103 : UInt<1> connect _WIRE_103, _T_2115 connect _WIRE_96[6], _WIRE_103 node _T_2116 = mux(_T_608, deq_vec[0][0].fu_code[7], UInt<1>(0h0)) node _T_2117 = mux(_T_609, deq_vec[1][0].fu_code[7], UInt<1>(0h0)) node _T_2118 = mux(_T_610, deq_vec[2][0].fu_code[7], UInt<1>(0h0)) node _T_2119 = mux(_T_611, deq_vec[3][0].fu_code[7], UInt<1>(0h0)) node _T_2120 = mux(_T_612, deq_vec[4][0].fu_code[7], UInt<1>(0h0)) node _T_2121 = mux(_T_613, deq_vec[5][0].fu_code[7], UInt<1>(0h0)) node _T_2122 = mux(_T_614, deq_vec[6][0].fu_code[7], UInt<1>(0h0)) node _T_2123 = mux(_T_615, deq_vec[7][0].fu_code[7], UInt<1>(0h0)) node _T_2124 = or(_T_2116, _T_2117) node _T_2125 = or(_T_2124, _T_2118) node _T_2126 = or(_T_2125, _T_2119) node _T_2127 = or(_T_2126, _T_2120) node _T_2128 = or(_T_2127, _T_2121) node _T_2129 = or(_T_2128, _T_2122) node _T_2130 = or(_T_2129, _T_2123) wire _WIRE_104 : UInt<1> connect _WIRE_104, _T_2130 connect _WIRE_96[7], _WIRE_104 node _T_2131 = mux(_T_608, deq_vec[0][0].fu_code[8], UInt<1>(0h0)) node _T_2132 = mux(_T_609, deq_vec[1][0].fu_code[8], UInt<1>(0h0)) node _T_2133 = mux(_T_610, deq_vec[2][0].fu_code[8], UInt<1>(0h0)) node _T_2134 = mux(_T_611, deq_vec[3][0].fu_code[8], UInt<1>(0h0)) node _T_2135 = mux(_T_612, deq_vec[4][0].fu_code[8], UInt<1>(0h0)) node _T_2136 = mux(_T_613, deq_vec[5][0].fu_code[8], UInt<1>(0h0)) node _T_2137 = mux(_T_614, deq_vec[6][0].fu_code[8], UInt<1>(0h0)) node _T_2138 = mux(_T_615, deq_vec[7][0].fu_code[8], UInt<1>(0h0)) node _T_2139 = or(_T_2131, _T_2132) node _T_2140 = or(_T_2139, _T_2133) node _T_2141 = or(_T_2140, _T_2134) node _T_2142 = or(_T_2141, _T_2135) node _T_2143 = or(_T_2142, _T_2136) node _T_2144 = or(_T_2143, _T_2137) node _T_2145 = or(_T_2144, _T_2138) wire _WIRE_105 : UInt<1> connect _WIRE_105, _T_2145 connect _WIRE_96[8], _WIRE_105 node _T_2146 = mux(_T_608, deq_vec[0][0].fu_code[9], UInt<1>(0h0)) node _T_2147 = mux(_T_609, deq_vec[1][0].fu_code[9], UInt<1>(0h0)) node _T_2148 = mux(_T_610, deq_vec[2][0].fu_code[9], UInt<1>(0h0)) node _T_2149 = mux(_T_611, deq_vec[3][0].fu_code[9], UInt<1>(0h0)) node _T_2150 = mux(_T_612, deq_vec[4][0].fu_code[9], UInt<1>(0h0)) node _T_2151 = mux(_T_613, deq_vec[5][0].fu_code[9], UInt<1>(0h0)) node _T_2152 = mux(_T_614, deq_vec[6][0].fu_code[9], UInt<1>(0h0)) node _T_2153 = mux(_T_615, deq_vec[7][0].fu_code[9], UInt<1>(0h0)) node _T_2154 = or(_T_2146, _T_2147) node _T_2155 = or(_T_2154, _T_2148) node _T_2156 = or(_T_2155, _T_2149) node _T_2157 = or(_T_2156, _T_2150) node _T_2158 = or(_T_2157, _T_2151) node _T_2159 = or(_T_2158, _T_2152) node _T_2160 = or(_T_2159, _T_2153) wire _WIRE_106 : UInt<1> connect _WIRE_106, _T_2160 connect _WIRE_96[9], _WIRE_106 connect _WIRE_1.fu_code, _WIRE_96 wire _WIRE_107 : UInt<1>[4] node _T_2161 = mux(_T_608, deq_vec[0][0].iq_type[0], UInt<1>(0h0)) node _T_2162 = mux(_T_609, deq_vec[1][0].iq_type[0], UInt<1>(0h0)) node _T_2163 = mux(_T_610, deq_vec[2][0].iq_type[0], UInt<1>(0h0)) node _T_2164 = mux(_T_611, deq_vec[3][0].iq_type[0], UInt<1>(0h0)) node _T_2165 = mux(_T_612, deq_vec[4][0].iq_type[0], UInt<1>(0h0)) node _T_2166 = mux(_T_613, deq_vec[5][0].iq_type[0], UInt<1>(0h0)) node _T_2167 = mux(_T_614, deq_vec[6][0].iq_type[0], UInt<1>(0h0)) node _T_2168 = mux(_T_615, deq_vec[7][0].iq_type[0], UInt<1>(0h0)) node _T_2169 = or(_T_2161, _T_2162) node _T_2170 = or(_T_2169, _T_2163) node _T_2171 = or(_T_2170, _T_2164) node _T_2172 = or(_T_2171, _T_2165) node _T_2173 = or(_T_2172, _T_2166) node _T_2174 = or(_T_2173, _T_2167) node _T_2175 = or(_T_2174, _T_2168) wire _WIRE_108 : UInt<1> connect _WIRE_108, _T_2175 connect _WIRE_107[0], _WIRE_108 node _T_2176 = mux(_T_608, deq_vec[0][0].iq_type[1], UInt<1>(0h0)) node _T_2177 = mux(_T_609, deq_vec[1][0].iq_type[1], UInt<1>(0h0)) node _T_2178 = mux(_T_610, deq_vec[2][0].iq_type[1], UInt<1>(0h0)) node _T_2179 = mux(_T_611, deq_vec[3][0].iq_type[1], UInt<1>(0h0)) node _T_2180 = mux(_T_612, deq_vec[4][0].iq_type[1], UInt<1>(0h0)) node _T_2181 = mux(_T_613, deq_vec[5][0].iq_type[1], UInt<1>(0h0)) node _T_2182 = mux(_T_614, deq_vec[6][0].iq_type[1], UInt<1>(0h0)) node _T_2183 = mux(_T_615, deq_vec[7][0].iq_type[1], UInt<1>(0h0)) node _T_2184 = or(_T_2176, _T_2177) node _T_2185 = or(_T_2184, _T_2178) node _T_2186 = or(_T_2185, _T_2179) node _T_2187 = or(_T_2186, _T_2180) node _T_2188 = or(_T_2187, _T_2181) node _T_2189 = or(_T_2188, _T_2182) node _T_2190 = or(_T_2189, _T_2183) wire _WIRE_109 : UInt<1> connect _WIRE_109, _T_2190 connect _WIRE_107[1], _WIRE_109 node _T_2191 = mux(_T_608, deq_vec[0][0].iq_type[2], UInt<1>(0h0)) node _T_2192 = mux(_T_609, deq_vec[1][0].iq_type[2], UInt<1>(0h0)) node _T_2193 = mux(_T_610, deq_vec[2][0].iq_type[2], UInt<1>(0h0)) node _T_2194 = mux(_T_611, deq_vec[3][0].iq_type[2], UInt<1>(0h0)) node _T_2195 = mux(_T_612, deq_vec[4][0].iq_type[2], UInt<1>(0h0)) node _T_2196 = mux(_T_613, deq_vec[5][0].iq_type[2], UInt<1>(0h0)) node _T_2197 = mux(_T_614, deq_vec[6][0].iq_type[2], UInt<1>(0h0)) node _T_2198 = mux(_T_615, deq_vec[7][0].iq_type[2], UInt<1>(0h0)) node _T_2199 = or(_T_2191, _T_2192) node _T_2200 = or(_T_2199, _T_2193) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = or(_T_2201, _T_2195) node _T_2203 = or(_T_2202, _T_2196) node _T_2204 = or(_T_2203, _T_2197) node _T_2205 = or(_T_2204, _T_2198) wire _WIRE_110 : UInt<1> connect _WIRE_110, _T_2205 connect _WIRE_107[2], _WIRE_110 node _T_2206 = mux(_T_608, deq_vec[0][0].iq_type[3], UInt<1>(0h0)) node _T_2207 = mux(_T_609, deq_vec[1][0].iq_type[3], UInt<1>(0h0)) node _T_2208 = mux(_T_610, deq_vec[2][0].iq_type[3], UInt<1>(0h0)) node _T_2209 = mux(_T_611, deq_vec[3][0].iq_type[3], UInt<1>(0h0)) node _T_2210 = mux(_T_612, deq_vec[4][0].iq_type[3], UInt<1>(0h0)) node _T_2211 = mux(_T_613, deq_vec[5][0].iq_type[3], UInt<1>(0h0)) node _T_2212 = mux(_T_614, deq_vec[6][0].iq_type[3], UInt<1>(0h0)) node _T_2213 = mux(_T_615, deq_vec[7][0].iq_type[3], UInt<1>(0h0)) node _T_2214 = or(_T_2206, _T_2207) node _T_2215 = or(_T_2214, _T_2208) node _T_2216 = or(_T_2215, _T_2209) node _T_2217 = or(_T_2216, _T_2210) node _T_2218 = or(_T_2217, _T_2211) node _T_2219 = or(_T_2218, _T_2212) node _T_2220 = or(_T_2219, _T_2213) wire _WIRE_111 : UInt<1> connect _WIRE_111, _T_2220 connect _WIRE_107[3], _WIRE_111 connect _WIRE_1.iq_type, _WIRE_107 node _T_2221 = mux(_T_608, deq_vec[0][0].debug_pc, UInt<1>(0h0)) node _T_2222 = mux(_T_609, deq_vec[1][0].debug_pc, UInt<1>(0h0)) node _T_2223 = mux(_T_610, deq_vec[2][0].debug_pc, UInt<1>(0h0)) node _T_2224 = mux(_T_611, deq_vec[3][0].debug_pc, UInt<1>(0h0)) node _T_2225 = mux(_T_612, deq_vec[4][0].debug_pc, UInt<1>(0h0)) node _T_2226 = mux(_T_613, deq_vec[5][0].debug_pc, UInt<1>(0h0)) node _T_2227 = mux(_T_614, deq_vec[6][0].debug_pc, UInt<1>(0h0)) node _T_2228 = mux(_T_615, deq_vec[7][0].debug_pc, UInt<1>(0h0)) node _T_2229 = or(_T_2221, _T_2222) node _T_2230 = or(_T_2229, _T_2223) node _T_2231 = or(_T_2230, _T_2224) node _T_2232 = or(_T_2231, _T_2225) node _T_2233 = or(_T_2232, _T_2226) node _T_2234 = or(_T_2233, _T_2227) node _T_2235 = or(_T_2234, _T_2228) wire _WIRE_112 : UInt<40> connect _WIRE_112, _T_2235 connect _WIRE_1.debug_pc, _WIRE_112 node _T_2236 = mux(_T_608, deq_vec[0][0].is_rvc, UInt<1>(0h0)) node _T_2237 = mux(_T_609, deq_vec[1][0].is_rvc, UInt<1>(0h0)) node _T_2238 = mux(_T_610, deq_vec[2][0].is_rvc, UInt<1>(0h0)) node _T_2239 = mux(_T_611, deq_vec[3][0].is_rvc, UInt<1>(0h0)) node _T_2240 = mux(_T_612, deq_vec[4][0].is_rvc, UInt<1>(0h0)) node _T_2241 = mux(_T_613, deq_vec[5][0].is_rvc, UInt<1>(0h0)) node _T_2242 = mux(_T_614, deq_vec[6][0].is_rvc, UInt<1>(0h0)) node _T_2243 = mux(_T_615, deq_vec[7][0].is_rvc, UInt<1>(0h0)) node _T_2244 = or(_T_2236, _T_2237) node _T_2245 = or(_T_2244, _T_2238) node _T_2246 = or(_T_2245, _T_2239) node _T_2247 = or(_T_2246, _T_2240) node _T_2248 = or(_T_2247, _T_2241) node _T_2249 = or(_T_2248, _T_2242) node _T_2250 = or(_T_2249, _T_2243) wire _WIRE_113 : UInt<1> connect _WIRE_113, _T_2250 connect _WIRE_1.is_rvc, _WIRE_113 node _T_2251 = mux(_T_608, deq_vec[0][0].debug_inst, UInt<1>(0h0)) node _T_2252 = mux(_T_609, deq_vec[1][0].debug_inst, UInt<1>(0h0)) node _T_2253 = mux(_T_610, deq_vec[2][0].debug_inst, UInt<1>(0h0)) node _T_2254 = mux(_T_611, deq_vec[3][0].debug_inst, UInt<1>(0h0)) node _T_2255 = mux(_T_612, deq_vec[4][0].debug_inst, UInt<1>(0h0)) node _T_2256 = mux(_T_613, deq_vec[5][0].debug_inst, UInt<1>(0h0)) node _T_2257 = mux(_T_614, deq_vec[6][0].debug_inst, UInt<1>(0h0)) node _T_2258 = mux(_T_615, deq_vec[7][0].debug_inst, UInt<1>(0h0)) node _T_2259 = or(_T_2251, _T_2252) node _T_2260 = or(_T_2259, _T_2253) node _T_2261 = or(_T_2260, _T_2254) node _T_2262 = or(_T_2261, _T_2255) node _T_2263 = or(_T_2262, _T_2256) node _T_2264 = or(_T_2263, _T_2257) node _T_2265 = or(_T_2264, _T_2258) wire _WIRE_114 : UInt<32> connect _WIRE_114, _T_2265 connect _WIRE_1.debug_inst, _WIRE_114 node _T_2266 = mux(_T_608, deq_vec[0][0].inst, UInt<1>(0h0)) node _T_2267 = mux(_T_609, deq_vec[1][0].inst, UInt<1>(0h0)) node _T_2268 = mux(_T_610, deq_vec[2][0].inst, UInt<1>(0h0)) node _T_2269 = mux(_T_611, deq_vec[3][0].inst, UInt<1>(0h0)) node _T_2270 = mux(_T_612, deq_vec[4][0].inst, UInt<1>(0h0)) node _T_2271 = mux(_T_613, deq_vec[5][0].inst, UInt<1>(0h0)) node _T_2272 = mux(_T_614, deq_vec[6][0].inst, UInt<1>(0h0)) node _T_2273 = mux(_T_615, deq_vec[7][0].inst, UInt<1>(0h0)) node _T_2274 = or(_T_2266, _T_2267) node _T_2275 = or(_T_2274, _T_2268) node _T_2276 = or(_T_2275, _T_2269) node _T_2277 = or(_T_2276, _T_2270) node _T_2278 = or(_T_2277, _T_2271) node _T_2279 = or(_T_2278, _T_2272) node _T_2280 = or(_T_2279, _T_2273) wire _WIRE_115 : UInt<32> connect _WIRE_115, _T_2280 connect _WIRE_1.inst, _WIRE_115 connect _WIRE[0], _WIRE_1 wire _WIRE_116 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_2281 = mux(_T_608, deq_vec[0][1].debug_tsrc, UInt<1>(0h0)) node _T_2282 = mux(_T_609, deq_vec[1][1].debug_tsrc, UInt<1>(0h0)) node _T_2283 = mux(_T_610, deq_vec[2][1].debug_tsrc, UInt<1>(0h0)) node _T_2284 = mux(_T_611, deq_vec[3][1].debug_tsrc, UInt<1>(0h0)) node _T_2285 = mux(_T_612, deq_vec[4][1].debug_tsrc, UInt<1>(0h0)) node _T_2286 = mux(_T_613, deq_vec[5][1].debug_tsrc, UInt<1>(0h0)) node _T_2287 = mux(_T_614, deq_vec[6][1].debug_tsrc, UInt<1>(0h0)) node _T_2288 = mux(_T_615, deq_vec[7][1].debug_tsrc, UInt<1>(0h0)) node _T_2289 = or(_T_2281, _T_2282) node _T_2290 = or(_T_2289, _T_2283) node _T_2291 = or(_T_2290, _T_2284) node _T_2292 = or(_T_2291, _T_2285) node _T_2293 = or(_T_2292, _T_2286) node _T_2294 = or(_T_2293, _T_2287) node _T_2295 = or(_T_2294, _T_2288) wire _WIRE_117 : UInt<3> connect _WIRE_117, _T_2295 connect _WIRE_116.debug_tsrc, _WIRE_117 node _T_2296 = mux(_T_608, deq_vec[0][1].debug_fsrc, UInt<1>(0h0)) node _T_2297 = mux(_T_609, deq_vec[1][1].debug_fsrc, UInt<1>(0h0)) node _T_2298 = mux(_T_610, deq_vec[2][1].debug_fsrc, UInt<1>(0h0)) node _T_2299 = mux(_T_611, deq_vec[3][1].debug_fsrc, UInt<1>(0h0)) node _T_2300 = mux(_T_612, deq_vec[4][1].debug_fsrc, UInt<1>(0h0)) node _T_2301 = mux(_T_613, deq_vec[5][1].debug_fsrc, UInt<1>(0h0)) node _T_2302 = mux(_T_614, deq_vec[6][1].debug_fsrc, UInt<1>(0h0)) node _T_2303 = mux(_T_615, deq_vec[7][1].debug_fsrc, UInt<1>(0h0)) node _T_2304 = or(_T_2296, _T_2297) node _T_2305 = or(_T_2304, _T_2298) node _T_2306 = or(_T_2305, _T_2299) node _T_2307 = or(_T_2306, _T_2300) node _T_2308 = or(_T_2307, _T_2301) node _T_2309 = or(_T_2308, _T_2302) node _T_2310 = or(_T_2309, _T_2303) wire _WIRE_118 : UInt<3> connect _WIRE_118, _T_2310 connect _WIRE_116.debug_fsrc, _WIRE_118 node _T_2311 = mux(_T_608, deq_vec[0][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2312 = mux(_T_609, deq_vec[1][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2313 = mux(_T_610, deq_vec[2][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2314 = mux(_T_611, deq_vec[3][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2315 = mux(_T_612, deq_vec[4][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2316 = mux(_T_613, deq_vec[5][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2317 = mux(_T_614, deq_vec[6][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2318 = mux(_T_615, deq_vec[7][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2319 = or(_T_2311, _T_2312) node _T_2320 = or(_T_2319, _T_2313) node _T_2321 = or(_T_2320, _T_2314) node _T_2322 = or(_T_2321, _T_2315) node _T_2323 = or(_T_2322, _T_2316) node _T_2324 = or(_T_2323, _T_2317) node _T_2325 = or(_T_2324, _T_2318) wire _WIRE_119 : UInt<1> connect _WIRE_119, _T_2325 connect _WIRE_116.bp_xcpt_if, _WIRE_119 node _T_2326 = mux(_T_608, deq_vec[0][1].bp_debug_if, UInt<1>(0h0)) node _T_2327 = mux(_T_609, deq_vec[1][1].bp_debug_if, UInt<1>(0h0)) node _T_2328 = mux(_T_610, deq_vec[2][1].bp_debug_if, UInt<1>(0h0)) node _T_2329 = mux(_T_611, deq_vec[3][1].bp_debug_if, UInt<1>(0h0)) node _T_2330 = mux(_T_612, deq_vec[4][1].bp_debug_if, UInt<1>(0h0)) node _T_2331 = mux(_T_613, deq_vec[5][1].bp_debug_if, UInt<1>(0h0)) node _T_2332 = mux(_T_614, deq_vec[6][1].bp_debug_if, UInt<1>(0h0)) node _T_2333 = mux(_T_615, deq_vec[7][1].bp_debug_if, UInt<1>(0h0)) node _T_2334 = or(_T_2326, _T_2327) node _T_2335 = or(_T_2334, _T_2328) node _T_2336 = or(_T_2335, _T_2329) node _T_2337 = or(_T_2336, _T_2330) node _T_2338 = or(_T_2337, _T_2331) node _T_2339 = or(_T_2338, _T_2332) node _T_2340 = or(_T_2339, _T_2333) wire _WIRE_120 : UInt<1> connect _WIRE_120, _T_2340 connect _WIRE_116.bp_debug_if, _WIRE_120 node _T_2341 = mux(_T_608, deq_vec[0][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2342 = mux(_T_609, deq_vec[1][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2343 = mux(_T_610, deq_vec[2][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2344 = mux(_T_611, deq_vec[3][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2345 = mux(_T_612, deq_vec[4][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2346 = mux(_T_613, deq_vec[5][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2347 = mux(_T_614, deq_vec[6][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2348 = mux(_T_615, deq_vec[7][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2349 = or(_T_2341, _T_2342) node _T_2350 = or(_T_2349, _T_2343) node _T_2351 = or(_T_2350, _T_2344) node _T_2352 = or(_T_2351, _T_2345) node _T_2353 = or(_T_2352, _T_2346) node _T_2354 = or(_T_2353, _T_2347) node _T_2355 = or(_T_2354, _T_2348) wire _WIRE_121 : UInt<1> connect _WIRE_121, _T_2355 connect _WIRE_116.xcpt_ma_if, _WIRE_121 node _T_2356 = mux(_T_608, deq_vec[0][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2357 = mux(_T_609, deq_vec[1][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2358 = mux(_T_610, deq_vec[2][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2359 = mux(_T_611, deq_vec[3][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2360 = mux(_T_612, deq_vec[4][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2361 = mux(_T_613, deq_vec[5][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2362 = mux(_T_614, deq_vec[6][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2363 = mux(_T_615, deq_vec[7][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2364 = or(_T_2356, _T_2357) node _T_2365 = or(_T_2364, _T_2358) node _T_2366 = or(_T_2365, _T_2359) node _T_2367 = or(_T_2366, _T_2360) node _T_2368 = or(_T_2367, _T_2361) node _T_2369 = or(_T_2368, _T_2362) node _T_2370 = or(_T_2369, _T_2363) wire _WIRE_122 : UInt<1> connect _WIRE_122, _T_2370 connect _WIRE_116.xcpt_ae_if, _WIRE_122 node _T_2371 = mux(_T_608, deq_vec[0][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2372 = mux(_T_609, deq_vec[1][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2373 = mux(_T_610, deq_vec[2][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2374 = mux(_T_611, deq_vec[3][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2375 = mux(_T_612, deq_vec[4][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2376 = mux(_T_613, deq_vec[5][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2377 = mux(_T_614, deq_vec[6][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2378 = mux(_T_615, deq_vec[7][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2379 = or(_T_2371, _T_2372) node _T_2380 = or(_T_2379, _T_2373) node _T_2381 = or(_T_2380, _T_2374) node _T_2382 = or(_T_2381, _T_2375) node _T_2383 = or(_T_2382, _T_2376) node _T_2384 = or(_T_2383, _T_2377) node _T_2385 = or(_T_2384, _T_2378) wire _WIRE_123 : UInt<1> connect _WIRE_123, _T_2385 connect _WIRE_116.xcpt_pf_if, _WIRE_123 node _T_2386 = mux(_T_608, deq_vec[0][1].fp_typ, UInt<1>(0h0)) node _T_2387 = mux(_T_609, deq_vec[1][1].fp_typ, UInt<1>(0h0)) node _T_2388 = mux(_T_610, deq_vec[2][1].fp_typ, UInt<1>(0h0)) node _T_2389 = mux(_T_611, deq_vec[3][1].fp_typ, UInt<1>(0h0)) node _T_2390 = mux(_T_612, deq_vec[4][1].fp_typ, UInt<1>(0h0)) node _T_2391 = mux(_T_613, deq_vec[5][1].fp_typ, UInt<1>(0h0)) node _T_2392 = mux(_T_614, deq_vec[6][1].fp_typ, UInt<1>(0h0)) node _T_2393 = mux(_T_615, deq_vec[7][1].fp_typ, UInt<1>(0h0)) node _T_2394 = or(_T_2386, _T_2387) node _T_2395 = or(_T_2394, _T_2388) node _T_2396 = or(_T_2395, _T_2389) node _T_2397 = or(_T_2396, _T_2390) node _T_2398 = or(_T_2397, _T_2391) node _T_2399 = or(_T_2398, _T_2392) node _T_2400 = or(_T_2399, _T_2393) wire _WIRE_124 : UInt<2> connect _WIRE_124, _T_2400 connect _WIRE_116.fp_typ, _WIRE_124 node _T_2401 = mux(_T_608, deq_vec[0][1].fp_rm, UInt<1>(0h0)) node _T_2402 = mux(_T_609, deq_vec[1][1].fp_rm, UInt<1>(0h0)) node _T_2403 = mux(_T_610, deq_vec[2][1].fp_rm, UInt<1>(0h0)) node _T_2404 = mux(_T_611, deq_vec[3][1].fp_rm, UInt<1>(0h0)) node _T_2405 = mux(_T_612, deq_vec[4][1].fp_rm, UInt<1>(0h0)) node _T_2406 = mux(_T_613, deq_vec[5][1].fp_rm, UInt<1>(0h0)) node _T_2407 = mux(_T_614, deq_vec[6][1].fp_rm, UInt<1>(0h0)) node _T_2408 = mux(_T_615, deq_vec[7][1].fp_rm, UInt<1>(0h0)) node _T_2409 = or(_T_2401, _T_2402) node _T_2410 = or(_T_2409, _T_2403) node _T_2411 = or(_T_2410, _T_2404) node _T_2412 = or(_T_2411, _T_2405) node _T_2413 = or(_T_2412, _T_2406) node _T_2414 = or(_T_2413, _T_2407) node _T_2415 = or(_T_2414, _T_2408) wire _WIRE_125 : UInt<3> connect _WIRE_125, _T_2415 connect _WIRE_116.fp_rm, _WIRE_125 node _T_2416 = mux(_T_608, deq_vec[0][1].fp_val, UInt<1>(0h0)) node _T_2417 = mux(_T_609, deq_vec[1][1].fp_val, UInt<1>(0h0)) node _T_2418 = mux(_T_610, deq_vec[2][1].fp_val, UInt<1>(0h0)) node _T_2419 = mux(_T_611, deq_vec[3][1].fp_val, UInt<1>(0h0)) node _T_2420 = mux(_T_612, deq_vec[4][1].fp_val, UInt<1>(0h0)) node _T_2421 = mux(_T_613, deq_vec[5][1].fp_val, UInt<1>(0h0)) node _T_2422 = mux(_T_614, deq_vec[6][1].fp_val, UInt<1>(0h0)) node _T_2423 = mux(_T_615, deq_vec[7][1].fp_val, UInt<1>(0h0)) node _T_2424 = or(_T_2416, _T_2417) node _T_2425 = or(_T_2424, _T_2418) node _T_2426 = or(_T_2425, _T_2419) node _T_2427 = or(_T_2426, _T_2420) node _T_2428 = or(_T_2427, _T_2421) node _T_2429 = or(_T_2428, _T_2422) node _T_2430 = or(_T_2429, _T_2423) wire _WIRE_126 : UInt<1> connect _WIRE_126, _T_2430 connect _WIRE_116.fp_val, _WIRE_126 node _T_2431 = mux(_T_608, deq_vec[0][1].fcn_op, UInt<1>(0h0)) node _T_2432 = mux(_T_609, deq_vec[1][1].fcn_op, UInt<1>(0h0)) node _T_2433 = mux(_T_610, deq_vec[2][1].fcn_op, UInt<1>(0h0)) node _T_2434 = mux(_T_611, deq_vec[3][1].fcn_op, UInt<1>(0h0)) node _T_2435 = mux(_T_612, deq_vec[4][1].fcn_op, UInt<1>(0h0)) node _T_2436 = mux(_T_613, deq_vec[5][1].fcn_op, UInt<1>(0h0)) node _T_2437 = mux(_T_614, deq_vec[6][1].fcn_op, UInt<1>(0h0)) node _T_2438 = mux(_T_615, deq_vec[7][1].fcn_op, UInt<1>(0h0)) node _T_2439 = or(_T_2431, _T_2432) node _T_2440 = or(_T_2439, _T_2433) node _T_2441 = or(_T_2440, _T_2434) node _T_2442 = or(_T_2441, _T_2435) node _T_2443 = or(_T_2442, _T_2436) node _T_2444 = or(_T_2443, _T_2437) node _T_2445 = or(_T_2444, _T_2438) wire _WIRE_127 : UInt<5> connect _WIRE_127, _T_2445 connect _WIRE_116.fcn_op, _WIRE_127 node _T_2446 = mux(_T_608, deq_vec[0][1].fcn_dw, UInt<1>(0h0)) node _T_2447 = mux(_T_609, deq_vec[1][1].fcn_dw, UInt<1>(0h0)) node _T_2448 = mux(_T_610, deq_vec[2][1].fcn_dw, UInt<1>(0h0)) node _T_2449 = mux(_T_611, deq_vec[3][1].fcn_dw, UInt<1>(0h0)) node _T_2450 = mux(_T_612, deq_vec[4][1].fcn_dw, UInt<1>(0h0)) node _T_2451 = mux(_T_613, deq_vec[5][1].fcn_dw, UInt<1>(0h0)) node _T_2452 = mux(_T_614, deq_vec[6][1].fcn_dw, UInt<1>(0h0)) node _T_2453 = mux(_T_615, deq_vec[7][1].fcn_dw, UInt<1>(0h0)) node _T_2454 = or(_T_2446, _T_2447) node _T_2455 = or(_T_2454, _T_2448) node _T_2456 = or(_T_2455, _T_2449) node _T_2457 = or(_T_2456, _T_2450) node _T_2458 = or(_T_2457, _T_2451) node _T_2459 = or(_T_2458, _T_2452) node _T_2460 = or(_T_2459, _T_2453) wire _WIRE_128 : UInt<1> connect _WIRE_128, _T_2460 connect _WIRE_116.fcn_dw, _WIRE_128 node _T_2461 = mux(_T_608, deq_vec[0][1].frs3_en, UInt<1>(0h0)) node _T_2462 = mux(_T_609, deq_vec[1][1].frs3_en, UInt<1>(0h0)) node _T_2463 = mux(_T_610, deq_vec[2][1].frs3_en, UInt<1>(0h0)) node _T_2464 = mux(_T_611, deq_vec[3][1].frs3_en, UInt<1>(0h0)) node _T_2465 = mux(_T_612, deq_vec[4][1].frs3_en, UInt<1>(0h0)) node _T_2466 = mux(_T_613, deq_vec[5][1].frs3_en, UInt<1>(0h0)) node _T_2467 = mux(_T_614, deq_vec[6][1].frs3_en, UInt<1>(0h0)) node _T_2468 = mux(_T_615, deq_vec[7][1].frs3_en, UInt<1>(0h0)) node _T_2469 = or(_T_2461, _T_2462) node _T_2470 = or(_T_2469, _T_2463) node _T_2471 = or(_T_2470, _T_2464) node _T_2472 = or(_T_2471, _T_2465) node _T_2473 = or(_T_2472, _T_2466) node _T_2474 = or(_T_2473, _T_2467) node _T_2475 = or(_T_2474, _T_2468) wire _WIRE_129 : UInt<1> connect _WIRE_129, _T_2475 connect _WIRE_116.frs3_en, _WIRE_129 node _T_2476 = mux(_T_608, deq_vec[0][1].lrs2_rtype, UInt<1>(0h0)) node _T_2477 = mux(_T_609, deq_vec[1][1].lrs2_rtype, UInt<1>(0h0)) node _T_2478 = mux(_T_610, deq_vec[2][1].lrs2_rtype, UInt<1>(0h0)) node _T_2479 = mux(_T_611, deq_vec[3][1].lrs2_rtype, UInt<1>(0h0)) node _T_2480 = mux(_T_612, deq_vec[4][1].lrs2_rtype, UInt<1>(0h0)) node _T_2481 = mux(_T_613, deq_vec[5][1].lrs2_rtype, UInt<1>(0h0)) node _T_2482 = mux(_T_614, deq_vec[6][1].lrs2_rtype, UInt<1>(0h0)) node _T_2483 = mux(_T_615, deq_vec[7][1].lrs2_rtype, UInt<1>(0h0)) node _T_2484 = or(_T_2476, _T_2477) node _T_2485 = or(_T_2484, _T_2478) node _T_2486 = or(_T_2485, _T_2479) node _T_2487 = or(_T_2486, _T_2480) node _T_2488 = or(_T_2487, _T_2481) node _T_2489 = or(_T_2488, _T_2482) node _T_2490 = or(_T_2489, _T_2483) wire _WIRE_130 : UInt<2> connect _WIRE_130, _T_2490 connect _WIRE_116.lrs2_rtype, _WIRE_130 node _T_2491 = mux(_T_608, deq_vec[0][1].lrs1_rtype, UInt<1>(0h0)) node _T_2492 = mux(_T_609, deq_vec[1][1].lrs1_rtype, UInt<1>(0h0)) node _T_2493 = mux(_T_610, deq_vec[2][1].lrs1_rtype, UInt<1>(0h0)) node _T_2494 = mux(_T_611, deq_vec[3][1].lrs1_rtype, UInt<1>(0h0)) node _T_2495 = mux(_T_612, deq_vec[4][1].lrs1_rtype, UInt<1>(0h0)) node _T_2496 = mux(_T_613, deq_vec[5][1].lrs1_rtype, UInt<1>(0h0)) node _T_2497 = mux(_T_614, deq_vec[6][1].lrs1_rtype, UInt<1>(0h0)) node _T_2498 = mux(_T_615, deq_vec[7][1].lrs1_rtype, UInt<1>(0h0)) node _T_2499 = or(_T_2491, _T_2492) node _T_2500 = or(_T_2499, _T_2493) node _T_2501 = or(_T_2500, _T_2494) node _T_2502 = or(_T_2501, _T_2495) node _T_2503 = or(_T_2502, _T_2496) node _T_2504 = or(_T_2503, _T_2497) node _T_2505 = or(_T_2504, _T_2498) wire _WIRE_131 : UInt<2> connect _WIRE_131, _T_2505 connect _WIRE_116.lrs1_rtype, _WIRE_131 node _T_2506 = mux(_T_608, deq_vec[0][1].dst_rtype, UInt<1>(0h0)) node _T_2507 = mux(_T_609, deq_vec[1][1].dst_rtype, UInt<1>(0h0)) node _T_2508 = mux(_T_610, deq_vec[2][1].dst_rtype, UInt<1>(0h0)) node _T_2509 = mux(_T_611, deq_vec[3][1].dst_rtype, UInt<1>(0h0)) node _T_2510 = mux(_T_612, deq_vec[4][1].dst_rtype, UInt<1>(0h0)) node _T_2511 = mux(_T_613, deq_vec[5][1].dst_rtype, UInt<1>(0h0)) node _T_2512 = mux(_T_614, deq_vec[6][1].dst_rtype, UInt<1>(0h0)) node _T_2513 = mux(_T_615, deq_vec[7][1].dst_rtype, UInt<1>(0h0)) node _T_2514 = or(_T_2506, _T_2507) node _T_2515 = or(_T_2514, _T_2508) node _T_2516 = or(_T_2515, _T_2509) node _T_2517 = or(_T_2516, _T_2510) node _T_2518 = or(_T_2517, _T_2511) node _T_2519 = or(_T_2518, _T_2512) node _T_2520 = or(_T_2519, _T_2513) wire _WIRE_132 : UInt<2> connect _WIRE_132, _T_2520 connect _WIRE_116.dst_rtype, _WIRE_132 node _T_2521 = mux(_T_608, deq_vec[0][1].lrs3, UInt<1>(0h0)) node _T_2522 = mux(_T_609, deq_vec[1][1].lrs3, UInt<1>(0h0)) node _T_2523 = mux(_T_610, deq_vec[2][1].lrs3, UInt<1>(0h0)) node _T_2524 = mux(_T_611, deq_vec[3][1].lrs3, UInt<1>(0h0)) node _T_2525 = mux(_T_612, deq_vec[4][1].lrs3, UInt<1>(0h0)) node _T_2526 = mux(_T_613, deq_vec[5][1].lrs3, UInt<1>(0h0)) node _T_2527 = mux(_T_614, deq_vec[6][1].lrs3, UInt<1>(0h0)) node _T_2528 = mux(_T_615, deq_vec[7][1].lrs3, UInt<1>(0h0)) node _T_2529 = or(_T_2521, _T_2522) node _T_2530 = or(_T_2529, _T_2523) node _T_2531 = or(_T_2530, _T_2524) node _T_2532 = or(_T_2531, _T_2525) node _T_2533 = or(_T_2532, _T_2526) node _T_2534 = or(_T_2533, _T_2527) node _T_2535 = or(_T_2534, _T_2528) wire _WIRE_133 : UInt<6> connect _WIRE_133, _T_2535 connect _WIRE_116.lrs3, _WIRE_133 node _T_2536 = mux(_T_608, deq_vec[0][1].lrs2, UInt<1>(0h0)) node _T_2537 = mux(_T_609, deq_vec[1][1].lrs2, UInt<1>(0h0)) node _T_2538 = mux(_T_610, deq_vec[2][1].lrs2, UInt<1>(0h0)) node _T_2539 = mux(_T_611, deq_vec[3][1].lrs2, UInt<1>(0h0)) node _T_2540 = mux(_T_612, deq_vec[4][1].lrs2, UInt<1>(0h0)) node _T_2541 = mux(_T_613, deq_vec[5][1].lrs2, UInt<1>(0h0)) node _T_2542 = mux(_T_614, deq_vec[6][1].lrs2, UInt<1>(0h0)) node _T_2543 = mux(_T_615, deq_vec[7][1].lrs2, UInt<1>(0h0)) node _T_2544 = or(_T_2536, _T_2537) node _T_2545 = or(_T_2544, _T_2538) node _T_2546 = or(_T_2545, _T_2539) node _T_2547 = or(_T_2546, _T_2540) node _T_2548 = or(_T_2547, _T_2541) node _T_2549 = or(_T_2548, _T_2542) node _T_2550 = or(_T_2549, _T_2543) wire _WIRE_134 : UInt<6> connect _WIRE_134, _T_2550 connect _WIRE_116.lrs2, _WIRE_134 node _T_2551 = mux(_T_608, deq_vec[0][1].lrs1, UInt<1>(0h0)) node _T_2552 = mux(_T_609, deq_vec[1][1].lrs1, UInt<1>(0h0)) node _T_2553 = mux(_T_610, deq_vec[2][1].lrs1, UInt<1>(0h0)) node _T_2554 = mux(_T_611, deq_vec[3][1].lrs1, UInt<1>(0h0)) node _T_2555 = mux(_T_612, deq_vec[4][1].lrs1, UInt<1>(0h0)) node _T_2556 = mux(_T_613, deq_vec[5][1].lrs1, UInt<1>(0h0)) node _T_2557 = mux(_T_614, deq_vec[6][1].lrs1, UInt<1>(0h0)) node _T_2558 = mux(_T_615, deq_vec[7][1].lrs1, UInt<1>(0h0)) node _T_2559 = or(_T_2551, _T_2552) node _T_2560 = or(_T_2559, _T_2553) node _T_2561 = or(_T_2560, _T_2554) node _T_2562 = or(_T_2561, _T_2555) node _T_2563 = or(_T_2562, _T_2556) node _T_2564 = or(_T_2563, _T_2557) node _T_2565 = or(_T_2564, _T_2558) wire _WIRE_135 : UInt<6> connect _WIRE_135, _T_2565 connect _WIRE_116.lrs1, _WIRE_135 node _T_2566 = mux(_T_608, deq_vec[0][1].ldst, UInt<1>(0h0)) node _T_2567 = mux(_T_609, deq_vec[1][1].ldst, UInt<1>(0h0)) node _T_2568 = mux(_T_610, deq_vec[2][1].ldst, UInt<1>(0h0)) node _T_2569 = mux(_T_611, deq_vec[3][1].ldst, UInt<1>(0h0)) node _T_2570 = mux(_T_612, deq_vec[4][1].ldst, UInt<1>(0h0)) node _T_2571 = mux(_T_613, deq_vec[5][1].ldst, UInt<1>(0h0)) node _T_2572 = mux(_T_614, deq_vec[6][1].ldst, UInt<1>(0h0)) node _T_2573 = mux(_T_615, deq_vec[7][1].ldst, UInt<1>(0h0)) node _T_2574 = or(_T_2566, _T_2567) node _T_2575 = or(_T_2574, _T_2568) node _T_2576 = or(_T_2575, _T_2569) node _T_2577 = or(_T_2576, _T_2570) node _T_2578 = or(_T_2577, _T_2571) node _T_2579 = or(_T_2578, _T_2572) node _T_2580 = or(_T_2579, _T_2573) wire _WIRE_136 : UInt<6> connect _WIRE_136, _T_2580 connect _WIRE_116.ldst, _WIRE_136 node _T_2581 = mux(_T_608, deq_vec[0][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2582 = mux(_T_609, deq_vec[1][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2583 = mux(_T_610, deq_vec[2][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2584 = mux(_T_611, deq_vec[3][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2585 = mux(_T_612, deq_vec[4][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2586 = mux(_T_613, deq_vec[5][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2587 = mux(_T_614, deq_vec[6][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2588 = mux(_T_615, deq_vec[7][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2589 = or(_T_2581, _T_2582) node _T_2590 = or(_T_2589, _T_2583) node _T_2591 = or(_T_2590, _T_2584) node _T_2592 = or(_T_2591, _T_2585) node _T_2593 = or(_T_2592, _T_2586) node _T_2594 = or(_T_2593, _T_2587) node _T_2595 = or(_T_2594, _T_2588) wire _WIRE_137 : UInt<1> connect _WIRE_137, _T_2595 connect _WIRE_116.ldst_is_rs1, _WIRE_137 node _T_2596 = mux(_T_608, deq_vec[0][1].csr_cmd, UInt<1>(0h0)) node _T_2597 = mux(_T_609, deq_vec[1][1].csr_cmd, UInt<1>(0h0)) node _T_2598 = mux(_T_610, deq_vec[2][1].csr_cmd, UInt<1>(0h0)) node _T_2599 = mux(_T_611, deq_vec[3][1].csr_cmd, UInt<1>(0h0)) node _T_2600 = mux(_T_612, deq_vec[4][1].csr_cmd, UInt<1>(0h0)) node _T_2601 = mux(_T_613, deq_vec[5][1].csr_cmd, UInt<1>(0h0)) node _T_2602 = mux(_T_614, deq_vec[6][1].csr_cmd, UInt<1>(0h0)) node _T_2603 = mux(_T_615, deq_vec[7][1].csr_cmd, UInt<1>(0h0)) node _T_2604 = or(_T_2596, _T_2597) node _T_2605 = or(_T_2604, _T_2598) node _T_2606 = or(_T_2605, _T_2599) node _T_2607 = or(_T_2606, _T_2600) node _T_2608 = or(_T_2607, _T_2601) node _T_2609 = or(_T_2608, _T_2602) node _T_2610 = or(_T_2609, _T_2603) wire _WIRE_138 : UInt<3> connect _WIRE_138, _T_2610 connect _WIRE_116.csr_cmd, _WIRE_138 node _T_2611 = mux(_T_608, deq_vec[0][1].flush_on_commit, UInt<1>(0h0)) node _T_2612 = mux(_T_609, deq_vec[1][1].flush_on_commit, UInt<1>(0h0)) node _T_2613 = mux(_T_610, deq_vec[2][1].flush_on_commit, UInt<1>(0h0)) node _T_2614 = mux(_T_611, deq_vec[3][1].flush_on_commit, UInt<1>(0h0)) node _T_2615 = mux(_T_612, deq_vec[4][1].flush_on_commit, UInt<1>(0h0)) node _T_2616 = mux(_T_613, deq_vec[5][1].flush_on_commit, UInt<1>(0h0)) node _T_2617 = mux(_T_614, deq_vec[6][1].flush_on_commit, UInt<1>(0h0)) node _T_2618 = mux(_T_615, deq_vec[7][1].flush_on_commit, UInt<1>(0h0)) node _T_2619 = or(_T_2611, _T_2612) node _T_2620 = or(_T_2619, _T_2613) node _T_2621 = or(_T_2620, _T_2614) node _T_2622 = or(_T_2621, _T_2615) node _T_2623 = or(_T_2622, _T_2616) node _T_2624 = or(_T_2623, _T_2617) node _T_2625 = or(_T_2624, _T_2618) wire _WIRE_139 : UInt<1> connect _WIRE_139, _T_2625 connect _WIRE_116.flush_on_commit, _WIRE_139 node _T_2626 = mux(_T_608, deq_vec[0][1].is_unique, UInt<1>(0h0)) node _T_2627 = mux(_T_609, deq_vec[1][1].is_unique, UInt<1>(0h0)) node _T_2628 = mux(_T_610, deq_vec[2][1].is_unique, UInt<1>(0h0)) node _T_2629 = mux(_T_611, deq_vec[3][1].is_unique, UInt<1>(0h0)) node _T_2630 = mux(_T_612, deq_vec[4][1].is_unique, UInt<1>(0h0)) node _T_2631 = mux(_T_613, deq_vec[5][1].is_unique, UInt<1>(0h0)) node _T_2632 = mux(_T_614, deq_vec[6][1].is_unique, UInt<1>(0h0)) node _T_2633 = mux(_T_615, deq_vec[7][1].is_unique, UInt<1>(0h0)) node _T_2634 = or(_T_2626, _T_2627) node _T_2635 = or(_T_2634, _T_2628) node _T_2636 = or(_T_2635, _T_2629) node _T_2637 = or(_T_2636, _T_2630) node _T_2638 = or(_T_2637, _T_2631) node _T_2639 = or(_T_2638, _T_2632) node _T_2640 = or(_T_2639, _T_2633) wire _WIRE_140 : UInt<1> connect _WIRE_140, _T_2640 connect _WIRE_116.is_unique, _WIRE_140 node _T_2641 = mux(_T_608, deq_vec[0][1].uses_stq, UInt<1>(0h0)) node _T_2642 = mux(_T_609, deq_vec[1][1].uses_stq, UInt<1>(0h0)) node _T_2643 = mux(_T_610, deq_vec[2][1].uses_stq, UInt<1>(0h0)) node _T_2644 = mux(_T_611, deq_vec[3][1].uses_stq, UInt<1>(0h0)) node _T_2645 = mux(_T_612, deq_vec[4][1].uses_stq, UInt<1>(0h0)) node _T_2646 = mux(_T_613, deq_vec[5][1].uses_stq, UInt<1>(0h0)) node _T_2647 = mux(_T_614, deq_vec[6][1].uses_stq, UInt<1>(0h0)) node _T_2648 = mux(_T_615, deq_vec[7][1].uses_stq, UInt<1>(0h0)) node _T_2649 = or(_T_2641, _T_2642) node _T_2650 = or(_T_2649, _T_2643) node _T_2651 = or(_T_2650, _T_2644) node _T_2652 = or(_T_2651, _T_2645) node _T_2653 = or(_T_2652, _T_2646) node _T_2654 = or(_T_2653, _T_2647) node _T_2655 = or(_T_2654, _T_2648) wire _WIRE_141 : UInt<1> connect _WIRE_141, _T_2655 connect _WIRE_116.uses_stq, _WIRE_141 node _T_2656 = mux(_T_608, deq_vec[0][1].uses_ldq, UInt<1>(0h0)) node _T_2657 = mux(_T_609, deq_vec[1][1].uses_ldq, UInt<1>(0h0)) node _T_2658 = mux(_T_610, deq_vec[2][1].uses_ldq, UInt<1>(0h0)) node _T_2659 = mux(_T_611, deq_vec[3][1].uses_ldq, UInt<1>(0h0)) node _T_2660 = mux(_T_612, deq_vec[4][1].uses_ldq, UInt<1>(0h0)) node _T_2661 = mux(_T_613, deq_vec[5][1].uses_ldq, UInt<1>(0h0)) node _T_2662 = mux(_T_614, deq_vec[6][1].uses_ldq, UInt<1>(0h0)) node _T_2663 = mux(_T_615, deq_vec[7][1].uses_ldq, UInt<1>(0h0)) node _T_2664 = or(_T_2656, _T_2657) node _T_2665 = or(_T_2664, _T_2658) node _T_2666 = or(_T_2665, _T_2659) node _T_2667 = or(_T_2666, _T_2660) node _T_2668 = or(_T_2667, _T_2661) node _T_2669 = or(_T_2668, _T_2662) node _T_2670 = or(_T_2669, _T_2663) wire _WIRE_142 : UInt<1> connect _WIRE_142, _T_2670 connect _WIRE_116.uses_ldq, _WIRE_142 node _T_2671 = mux(_T_608, deq_vec[0][1].mem_signed, UInt<1>(0h0)) node _T_2672 = mux(_T_609, deq_vec[1][1].mem_signed, UInt<1>(0h0)) node _T_2673 = mux(_T_610, deq_vec[2][1].mem_signed, UInt<1>(0h0)) node _T_2674 = mux(_T_611, deq_vec[3][1].mem_signed, UInt<1>(0h0)) node _T_2675 = mux(_T_612, deq_vec[4][1].mem_signed, UInt<1>(0h0)) node _T_2676 = mux(_T_613, deq_vec[5][1].mem_signed, UInt<1>(0h0)) node _T_2677 = mux(_T_614, deq_vec[6][1].mem_signed, UInt<1>(0h0)) node _T_2678 = mux(_T_615, deq_vec[7][1].mem_signed, UInt<1>(0h0)) node _T_2679 = or(_T_2671, _T_2672) node _T_2680 = or(_T_2679, _T_2673) node _T_2681 = or(_T_2680, _T_2674) node _T_2682 = or(_T_2681, _T_2675) node _T_2683 = or(_T_2682, _T_2676) node _T_2684 = or(_T_2683, _T_2677) node _T_2685 = or(_T_2684, _T_2678) wire _WIRE_143 : UInt<1> connect _WIRE_143, _T_2685 connect _WIRE_116.mem_signed, _WIRE_143 node _T_2686 = mux(_T_608, deq_vec[0][1].mem_size, UInt<1>(0h0)) node _T_2687 = mux(_T_609, deq_vec[1][1].mem_size, UInt<1>(0h0)) node _T_2688 = mux(_T_610, deq_vec[2][1].mem_size, UInt<1>(0h0)) node _T_2689 = mux(_T_611, deq_vec[3][1].mem_size, UInt<1>(0h0)) node _T_2690 = mux(_T_612, deq_vec[4][1].mem_size, UInt<1>(0h0)) node _T_2691 = mux(_T_613, deq_vec[5][1].mem_size, UInt<1>(0h0)) node _T_2692 = mux(_T_614, deq_vec[6][1].mem_size, UInt<1>(0h0)) node _T_2693 = mux(_T_615, deq_vec[7][1].mem_size, UInt<1>(0h0)) node _T_2694 = or(_T_2686, _T_2687) node _T_2695 = or(_T_2694, _T_2688) node _T_2696 = or(_T_2695, _T_2689) node _T_2697 = or(_T_2696, _T_2690) node _T_2698 = or(_T_2697, _T_2691) node _T_2699 = or(_T_2698, _T_2692) node _T_2700 = or(_T_2699, _T_2693) wire _WIRE_144 : UInt<2> connect _WIRE_144, _T_2700 connect _WIRE_116.mem_size, _WIRE_144 node _T_2701 = mux(_T_608, deq_vec[0][1].mem_cmd, UInt<1>(0h0)) node _T_2702 = mux(_T_609, deq_vec[1][1].mem_cmd, UInt<1>(0h0)) node _T_2703 = mux(_T_610, deq_vec[2][1].mem_cmd, UInt<1>(0h0)) node _T_2704 = mux(_T_611, deq_vec[3][1].mem_cmd, UInt<1>(0h0)) node _T_2705 = mux(_T_612, deq_vec[4][1].mem_cmd, UInt<1>(0h0)) node _T_2706 = mux(_T_613, deq_vec[5][1].mem_cmd, UInt<1>(0h0)) node _T_2707 = mux(_T_614, deq_vec[6][1].mem_cmd, UInt<1>(0h0)) node _T_2708 = mux(_T_615, deq_vec[7][1].mem_cmd, UInt<1>(0h0)) node _T_2709 = or(_T_2701, _T_2702) node _T_2710 = or(_T_2709, _T_2703) node _T_2711 = or(_T_2710, _T_2704) node _T_2712 = or(_T_2711, _T_2705) node _T_2713 = or(_T_2712, _T_2706) node _T_2714 = or(_T_2713, _T_2707) node _T_2715 = or(_T_2714, _T_2708) wire _WIRE_145 : UInt<5> connect _WIRE_145, _T_2715 connect _WIRE_116.mem_cmd, _WIRE_145 node _T_2716 = mux(_T_608, deq_vec[0][1].exc_cause, UInt<1>(0h0)) node _T_2717 = mux(_T_609, deq_vec[1][1].exc_cause, UInt<1>(0h0)) node _T_2718 = mux(_T_610, deq_vec[2][1].exc_cause, UInt<1>(0h0)) node _T_2719 = mux(_T_611, deq_vec[3][1].exc_cause, UInt<1>(0h0)) node _T_2720 = mux(_T_612, deq_vec[4][1].exc_cause, UInt<1>(0h0)) node _T_2721 = mux(_T_613, deq_vec[5][1].exc_cause, UInt<1>(0h0)) node _T_2722 = mux(_T_614, deq_vec[6][1].exc_cause, UInt<1>(0h0)) node _T_2723 = mux(_T_615, deq_vec[7][1].exc_cause, UInt<1>(0h0)) node _T_2724 = or(_T_2716, _T_2717) node _T_2725 = or(_T_2724, _T_2718) node _T_2726 = or(_T_2725, _T_2719) node _T_2727 = or(_T_2726, _T_2720) node _T_2728 = or(_T_2727, _T_2721) node _T_2729 = or(_T_2728, _T_2722) node _T_2730 = or(_T_2729, _T_2723) wire _WIRE_146 : UInt<64> connect _WIRE_146, _T_2730 connect _WIRE_116.exc_cause, _WIRE_146 node _T_2731 = mux(_T_608, deq_vec[0][1].exception, UInt<1>(0h0)) node _T_2732 = mux(_T_609, deq_vec[1][1].exception, UInt<1>(0h0)) node _T_2733 = mux(_T_610, deq_vec[2][1].exception, UInt<1>(0h0)) node _T_2734 = mux(_T_611, deq_vec[3][1].exception, UInt<1>(0h0)) node _T_2735 = mux(_T_612, deq_vec[4][1].exception, UInt<1>(0h0)) node _T_2736 = mux(_T_613, deq_vec[5][1].exception, UInt<1>(0h0)) node _T_2737 = mux(_T_614, deq_vec[6][1].exception, UInt<1>(0h0)) node _T_2738 = mux(_T_615, deq_vec[7][1].exception, UInt<1>(0h0)) node _T_2739 = or(_T_2731, _T_2732) node _T_2740 = or(_T_2739, _T_2733) node _T_2741 = or(_T_2740, _T_2734) node _T_2742 = or(_T_2741, _T_2735) node _T_2743 = or(_T_2742, _T_2736) node _T_2744 = or(_T_2743, _T_2737) node _T_2745 = or(_T_2744, _T_2738) wire _WIRE_147 : UInt<1> connect _WIRE_147, _T_2745 connect _WIRE_116.exception, _WIRE_147 node _T_2746 = mux(_T_608, deq_vec[0][1].stale_pdst, UInt<1>(0h0)) node _T_2747 = mux(_T_609, deq_vec[1][1].stale_pdst, UInt<1>(0h0)) node _T_2748 = mux(_T_610, deq_vec[2][1].stale_pdst, UInt<1>(0h0)) node _T_2749 = mux(_T_611, deq_vec[3][1].stale_pdst, UInt<1>(0h0)) node _T_2750 = mux(_T_612, deq_vec[4][1].stale_pdst, UInt<1>(0h0)) node _T_2751 = mux(_T_613, deq_vec[5][1].stale_pdst, UInt<1>(0h0)) node _T_2752 = mux(_T_614, deq_vec[6][1].stale_pdst, UInt<1>(0h0)) node _T_2753 = mux(_T_615, deq_vec[7][1].stale_pdst, UInt<1>(0h0)) node _T_2754 = or(_T_2746, _T_2747) node _T_2755 = or(_T_2754, _T_2748) node _T_2756 = or(_T_2755, _T_2749) node _T_2757 = or(_T_2756, _T_2750) node _T_2758 = or(_T_2757, _T_2751) node _T_2759 = or(_T_2758, _T_2752) node _T_2760 = or(_T_2759, _T_2753) wire _WIRE_148 : UInt<7> connect _WIRE_148, _T_2760 connect _WIRE_116.stale_pdst, _WIRE_148 node _T_2761 = mux(_T_608, deq_vec[0][1].ppred_busy, UInt<1>(0h0)) node _T_2762 = mux(_T_609, deq_vec[1][1].ppred_busy, UInt<1>(0h0)) node _T_2763 = mux(_T_610, deq_vec[2][1].ppred_busy, UInt<1>(0h0)) node _T_2764 = mux(_T_611, deq_vec[3][1].ppred_busy, UInt<1>(0h0)) node _T_2765 = mux(_T_612, deq_vec[4][1].ppred_busy, UInt<1>(0h0)) node _T_2766 = mux(_T_613, deq_vec[5][1].ppred_busy, UInt<1>(0h0)) node _T_2767 = mux(_T_614, deq_vec[6][1].ppred_busy, UInt<1>(0h0)) node _T_2768 = mux(_T_615, deq_vec[7][1].ppred_busy, UInt<1>(0h0)) node _T_2769 = or(_T_2761, _T_2762) node _T_2770 = or(_T_2769, _T_2763) node _T_2771 = or(_T_2770, _T_2764) node _T_2772 = or(_T_2771, _T_2765) node _T_2773 = or(_T_2772, _T_2766) node _T_2774 = or(_T_2773, _T_2767) node _T_2775 = or(_T_2774, _T_2768) wire _WIRE_149 : UInt<1> connect _WIRE_149, _T_2775 connect _WIRE_116.ppred_busy, _WIRE_149 node _T_2776 = mux(_T_608, deq_vec[0][1].prs3_busy, UInt<1>(0h0)) node _T_2777 = mux(_T_609, deq_vec[1][1].prs3_busy, UInt<1>(0h0)) node _T_2778 = mux(_T_610, deq_vec[2][1].prs3_busy, UInt<1>(0h0)) node _T_2779 = mux(_T_611, deq_vec[3][1].prs3_busy, UInt<1>(0h0)) node _T_2780 = mux(_T_612, deq_vec[4][1].prs3_busy, UInt<1>(0h0)) node _T_2781 = mux(_T_613, deq_vec[5][1].prs3_busy, UInt<1>(0h0)) node _T_2782 = mux(_T_614, deq_vec[6][1].prs3_busy, UInt<1>(0h0)) node _T_2783 = mux(_T_615, deq_vec[7][1].prs3_busy, UInt<1>(0h0)) node _T_2784 = or(_T_2776, _T_2777) node _T_2785 = or(_T_2784, _T_2778) node _T_2786 = or(_T_2785, _T_2779) node _T_2787 = or(_T_2786, _T_2780) node _T_2788 = or(_T_2787, _T_2781) node _T_2789 = or(_T_2788, _T_2782) node _T_2790 = or(_T_2789, _T_2783) wire _WIRE_150 : UInt<1> connect _WIRE_150, _T_2790 connect _WIRE_116.prs3_busy, _WIRE_150 node _T_2791 = mux(_T_608, deq_vec[0][1].prs2_busy, UInt<1>(0h0)) node _T_2792 = mux(_T_609, deq_vec[1][1].prs2_busy, UInt<1>(0h0)) node _T_2793 = mux(_T_610, deq_vec[2][1].prs2_busy, UInt<1>(0h0)) node _T_2794 = mux(_T_611, deq_vec[3][1].prs2_busy, UInt<1>(0h0)) node _T_2795 = mux(_T_612, deq_vec[4][1].prs2_busy, UInt<1>(0h0)) node _T_2796 = mux(_T_613, deq_vec[5][1].prs2_busy, UInt<1>(0h0)) node _T_2797 = mux(_T_614, deq_vec[6][1].prs2_busy, UInt<1>(0h0)) node _T_2798 = mux(_T_615, deq_vec[7][1].prs2_busy, UInt<1>(0h0)) node _T_2799 = or(_T_2791, _T_2792) node _T_2800 = or(_T_2799, _T_2793) node _T_2801 = or(_T_2800, _T_2794) node _T_2802 = or(_T_2801, _T_2795) node _T_2803 = or(_T_2802, _T_2796) node _T_2804 = or(_T_2803, _T_2797) node _T_2805 = or(_T_2804, _T_2798) wire _WIRE_151 : UInt<1> connect _WIRE_151, _T_2805 connect _WIRE_116.prs2_busy, _WIRE_151 node _T_2806 = mux(_T_608, deq_vec[0][1].prs1_busy, UInt<1>(0h0)) node _T_2807 = mux(_T_609, deq_vec[1][1].prs1_busy, UInt<1>(0h0)) node _T_2808 = mux(_T_610, deq_vec[2][1].prs1_busy, UInt<1>(0h0)) node _T_2809 = mux(_T_611, deq_vec[3][1].prs1_busy, UInt<1>(0h0)) node _T_2810 = mux(_T_612, deq_vec[4][1].prs1_busy, UInt<1>(0h0)) node _T_2811 = mux(_T_613, deq_vec[5][1].prs1_busy, UInt<1>(0h0)) node _T_2812 = mux(_T_614, deq_vec[6][1].prs1_busy, UInt<1>(0h0)) node _T_2813 = mux(_T_615, deq_vec[7][1].prs1_busy, UInt<1>(0h0)) node _T_2814 = or(_T_2806, _T_2807) node _T_2815 = or(_T_2814, _T_2808) node _T_2816 = or(_T_2815, _T_2809) node _T_2817 = or(_T_2816, _T_2810) node _T_2818 = or(_T_2817, _T_2811) node _T_2819 = or(_T_2818, _T_2812) node _T_2820 = or(_T_2819, _T_2813) wire _WIRE_152 : UInt<1> connect _WIRE_152, _T_2820 connect _WIRE_116.prs1_busy, _WIRE_152 node _T_2821 = mux(_T_608, deq_vec[0][1].ppred, UInt<1>(0h0)) node _T_2822 = mux(_T_609, deq_vec[1][1].ppred, UInt<1>(0h0)) node _T_2823 = mux(_T_610, deq_vec[2][1].ppred, UInt<1>(0h0)) node _T_2824 = mux(_T_611, deq_vec[3][1].ppred, UInt<1>(0h0)) node _T_2825 = mux(_T_612, deq_vec[4][1].ppred, UInt<1>(0h0)) node _T_2826 = mux(_T_613, deq_vec[5][1].ppred, UInt<1>(0h0)) node _T_2827 = mux(_T_614, deq_vec[6][1].ppred, UInt<1>(0h0)) node _T_2828 = mux(_T_615, deq_vec[7][1].ppred, UInt<1>(0h0)) node _T_2829 = or(_T_2821, _T_2822) node _T_2830 = or(_T_2829, _T_2823) node _T_2831 = or(_T_2830, _T_2824) node _T_2832 = or(_T_2831, _T_2825) node _T_2833 = or(_T_2832, _T_2826) node _T_2834 = or(_T_2833, _T_2827) node _T_2835 = or(_T_2834, _T_2828) wire _WIRE_153 : UInt<5> connect _WIRE_153, _T_2835 connect _WIRE_116.ppred, _WIRE_153 node _T_2836 = mux(_T_608, deq_vec[0][1].prs3, UInt<1>(0h0)) node _T_2837 = mux(_T_609, deq_vec[1][1].prs3, UInt<1>(0h0)) node _T_2838 = mux(_T_610, deq_vec[2][1].prs3, UInt<1>(0h0)) node _T_2839 = mux(_T_611, deq_vec[3][1].prs3, UInt<1>(0h0)) node _T_2840 = mux(_T_612, deq_vec[4][1].prs3, UInt<1>(0h0)) node _T_2841 = mux(_T_613, deq_vec[5][1].prs3, UInt<1>(0h0)) node _T_2842 = mux(_T_614, deq_vec[6][1].prs3, UInt<1>(0h0)) node _T_2843 = mux(_T_615, deq_vec[7][1].prs3, UInt<1>(0h0)) node _T_2844 = or(_T_2836, _T_2837) node _T_2845 = or(_T_2844, _T_2838) node _T_2846 = or(_T_2845, _T_2839) node _T_2847 = or(_T_2846, _T_2840) node _T_2848 = or(_T_2847, _T_2841) node _T_2849 = or(_T_2848, _T_2842) node _T_2850 = or(_T_2849, _T_2843) wire _WIRE_154 : UInt<7> connect _WIRE_154, _T_2850 connect _WIRE_116.prs3, _WIRE_154 node _T_2851 = mux(_T_608, deq_vec[0][1].prs2, UInt<1>(0h0)) node _T_2852 = mux(_T_609, deq_vec[1][1].prs2, UInt<1>(0h0)) node _T_2853 = mux(_T_610, deq_vec[2][1].prs2, UInt<1>(0h0)) node _T_2854 = mux(_T_611, deq_vec[3][1].prs2, UInt<1>(0h0)) node _T_2855 = mux(_T_612, deq_vec[4][1].prs2, UInt<1>(0h0)) node _T_2856 = mux(_T_613, deq_vec[5][1].prs2, UInt<1>(0h0)) node _T_2857 = mux(_T_614, deq_vec[6][1].prs2, UInt<1>(0h0)) node _T_2858 = mux(_T_615, deq_vec[7][1].prs2, UInt<1>(0h0)) node _T_2859 = or(_T_2851, _T_2852) node _T_2860 = or(_T_2859, _T_2853) node _T_2861 = or(_T_2860, _T_2854) node _T_2862 = or(_T_2861, _T_2855) node _T_2863 = or(_T_2862, _T_2856) node _T_2864 = or(_T_2863, _T_2857) node _T_2865 = or(_T_2864, _T_2858) wire _WIRE_155 : UInt<7> connect _WIRE_155, _T_2865 connect _WIRE_116.prs2, _WIRE_155 node _T_2866 = mux(_T_608, deq_vec[0][1].prs1, UInt<1>(0h0)) node _T_2867 = mux(_T_609, deq_vec[1][1].prs1, UInt<1>(0h0)) node _T_2868 = mux(_T_610, deq_vec[2][1].prs1, UInt<1>(0h0)) node _T_2869 = mux(_T_611, deq_vec[3][1].prs1, UInt<1>(0h0)) node _T_2870 = mux(_T_612, deq_vec[4][1].prs1, UInt<1>(0h0)) node _T_2871 = mux(_T_613, deq_vec[5][1].prs1, UInt<1>(0h0)) node _T_2872 = mux(_T_614, deq_vec[6][1].prs1, UInt<1>(0h0)) node _T_2873 = mux(_T_615, deq_vec[7][1].prs1, UInt<1>(0h0)) node _T_2874 = or(_T_2866, _T_2867) node _T_2875 = or(_T_2874, _T_2868) node _T_2876 = or(_T_2875, _T_2869) node _T_2877 = or(_T_2876, _T_2870) node _T_2878 = or(_T_2877, _T_2871) node _T_2879 = or(_T_2878, _T_2872) node _T_2880 = or(_T_2879, _T_2873) wire _WIRE_156 : UInt<7> connect _WIRE_156, _T_2880 connect _WIRE_116.prs1, _WIRE_156 node _T_2881 = mux(_T_608, deq_vec[0][1].pdst, UInt<1>(0h0)) node _T_2882 = mux(_T_609, deq_vec[1][1].pdst, UInt<1>(0h0)) node _T_2883 = mux(_T_610, deq_vec[2][1].pdst, UInt<1>(0h0)) node _T_2884 = mux(_T_611, deq_vec[3][1].pdst, UInt<1>(0h0)) node _T_2885 = mux(_T_612, deq_vec[4][1].pdst, UInt<1>(0h0)) node _T_2886 = mux(_T_613, deq_vec[5][1].pdst, UInt<1>(0h0)) node _T_2887 = mux(_T_614, deq_vec[6][1].pdst, UInt<1>(0h0)) node _T_2888 = mux(_T_615, deq_vec[7][1].pdst, UInt<1>(0h0)) node _T_2889 = or(_T_2881, _T_2882) node _T_2890 = or(_T_2889, _T_2883) node _T_2891 = or(_T_2890, _T_2884) node _T_2892 = or(_T_2891, _T_2885) node _T_2893 = or(_T_2892, _T_2886) node _T_2894 = or(_T_2893, _T_2887) node _T_2895 = or(_T_2894, _T_2888) wire _WIRE_157 : UInt<7> connect _WIRE_157, _T_2895 connect _WIRE_116.pdst, _WIRE_157 node _T_2896 = mux(_T_608, deq_vec[0][1].rxq_idx, UInt<1>(0h0)) node _T_2897 = mux(_T_609, deq_vec[1][1].rxq_idx, UInt<1>(0h0)) node _T_2898 = mux(_T_610, deq_vec[2][1].rxq_idx, UInt<1>(0h0)) node _T_2899 = mux(_T_611, deq_vec[3][1].rxq_idx, UInt<1>(0h0)) node _T_2900 = mux(_T_612, deq_vec[4][1].rxq_idx, UInt<1>(0h0)) node _T_2901 = mux(_T_613, deq_vec[5][1].rxq_idx, UInt<1>(0h0)) node _T_2902 = mux(_T_614, deq_vec[6][1].rxq_idx, UInt<1>(0h0)) node _T_2903 = mux(_T_615, deq_vec[7][1].rxq_idx, UInt<1>(0h0)) node _T_2904 = or(_T_2896, _T_2897) node _T_2905 = or(_T_2904, _T_2898) node _T_2906 = or(_T_2905, _T_2899) node _T_2907 = or(_T_2906, _T_2900) node _T_2908 = or(_T_2907, _T_2901) node _T_2909 = or(_T_2908, _T_2902) node _T_2910 = or(_T_2909, _T_2903) wire _WIRE_158 : UInt<2> connect _WIRE_158, _T_2910 connect _WIRE_116.rxq_idx, _WIRE_158 node _T_2911 = mux(_T_608, deq_vec[0][1].stq_idx, UInt<1>(0h0)) node _T_2912 = mux(_T_609, deq_vec[1][1].stq_idx, UInt<1>(0h0)) node _T_2913 = mux(_T_610, deq_vec[2][1].stq_idx, UInt<1>(0h0)) node _T_2914 = mux(_T_611, deq_vec[3][1].stq_idx, UInt<1>(0h0)) node _T_2915 = mux(_T_612, deq_vec[4][1].stq_idx, UInt<1>(0h0)) node _T_2916 = mux(_T_613, deq_vec[5][1].stq_idx, UInt<1>(0h0)) node _T_2917 = mux(_T_614, deq_vec[6][1].stq_idx, UInt<1>(0h0)) node _T_2918 = mux(_T_615, deq_vec[7][1].stq_idx, UInt<1>(0h0)) node _T_2919 = or(_T_2911, _T_2912) node _T_2920 = or(_T_2919, _T_2913) node _T_2921 = or(_T_2920, _T_2914) node _T_2922 = or(_T_2921, _T_2915) node _T_2923 = or(_T_2922, _T_2916) node _T_2924 = or(_T_2923, _T_2917) node _T_2925 = or(_T_2924, _T_2918) wire _WIRE_159 : UInt<5> connect _WIRE_159, _T_2925 connect _WIRE_116.stq_idx, _WIRE_159 node _T_2926 = mux(_T_608, deq_vec[0][1].ldq_idx, UInt<1>(0h0)) node _T_2927 = mux(_T_609, deq_vec[1][1].ldq_idx, UInt<1>(0h0)) node _T_2928 = mux(_T_610, deq_vec[2][1].ldq_idx, UInt<1>(0h0)) node _T_2929 = mux(_T_611, deq_vec[3][1].ldq_idx, UInt<1>(0h0)) node _T_2930 = mux(_T_612, deq_vec[4][1].ldq_idx, UInt<1>(0h0)) node _T_2931 = mux(_T_613, deq_vec[5][1].ldq_idx, UInt<1>(0h0)) node _T_2932 = mux(_T_614, deq_vec[6][1].ldq_idx, UInt<1>(0h0)) node _T_2933 = mux(_T_615, deq_vec[7][1].ldq_idx, UInt<1>(0h0)) node _T_2934 = or(_T_2926, _T_2927) node _T_2935 = or(_T_2934, _T_2928) node _T_2936 = or(_T_2935, _T_2929) node _T_2937 = or(_T_2936, _T_2930) node _T_2938 = or(_T_2937, _T_2931) node _T_2939 = or(_T_2938, _T_2932) node _T_2940 = or(_T_2939, _T_2933) wire _WIRE_160 : UInt<5> connect _WIRE_160, _T_2940 connect _WIRE_116.ldq_idx, _WIRE_160 node _T_2941 = mux(_T_608, deq_vec[0][1].rob_idx, UInt<1>(0h0)) node _T_2942 = mux(_T_609, deq_vec[1][1].rob_idx, UInt<1>(0h0)) node _T_2943 = mux(_T_610, deq_vec[2][1].rob_idx, UInt<1>(0h0)) node _T_2944 = mux(_T_611, deq_vec[3][1].rob_idx, UInt<1>(0h0)) node _T_2945 = mux(_T_612, deq_vec[4][1].rob_idx, UInt<1>(0h0)) node _T_2946 = mux(_T_613, deq_vec[5][1].rob_idx, UInt<1>(0h0)) node _T_2947 = mux(_T_614, deq_vec[6][1].rob_idx, UInt<1>(0h0)) node _T_2948 = mux(_T_615, deq_vec[7][1].rob_idx, UInt<1>(0h0)) node _T_2949 = or(_T_2941, _T_2942) node _T_2950 = or(_T_2949, _T_2943) node _T_2951 = or(_T_2950, _T_2944) node _T_2952 = or(_T_2951, _T_2945) node _T_2953 = or(_T_2952, _T_2946) node _T_2954 = or(_T_2953, _T_2947) node _T_2955 = or(_T_2954, _T_2948) wire _WIRE_161 : UInt<7> connect _WIRE_161, _T_2955 connect _WIRE_116.rob_idx, _WIRE_161 wire _WIRE_162 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_2956 = mux(_T_608, deq_vec[0][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2957 = mux(_T_609, deq_vec[1][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2958 = mux(_T_610, deq_vec[2][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2959 = mux(_T_611, deq_vec[3][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2960 = mux(_T_612, deq_vec[4][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2961 = mux(_T_613, deq_vec[5][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2962 = mux(_T_614, deq_vec[6][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2963 = mux(_T_615, deq_vec[7][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2964 = or(_T_2956, _T_2957) node _T_2965 = or(_T_2964, _T_2958) node _T_2966 = or(_T_2965, _T_2959) node _T_2967 = or(_T_2966, _T_2960) node _T_2968 = or(_T_2967, _T_2961) node _T_2969 = or(_T_2968, _T_2962) node _T_2970 = or(_T_2969, _T_2963) wire _WIRE_163 : UInt<1> connect _WIRE_163, _T_2970 connect _WIRE_162.vec, _WIRE_163 node _T_2971 = mux(_T_608, deq_vec[0][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2972 = mux(_T_609, deq_vec[1][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2973 = mux(_T_610, deq_vec[2][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2974 = mux(_T_611, deq_vec[3][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2975 = mux(_T_612, deq_vec[4][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2976 = mux(_T_613, deq_vec[5][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2977 = mux(_T_614, deq_vec[6][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2978 = mux(_T_615, deq_vec[7][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2979 = or(_T_2971, _T_2972) node _T_2980 = or(_T_2979, _T_2973) node _T_2981 = or(_T_2980, _T_2974) node _T_2982 = or(_T_2981, _T_2975) node _T_2983 = or(_T_2982, _T_2976) node _T_2984 = or(_T_2983, _T_2977) node _T_2985 = or(_T_2984, _T_2978) wire _WIRE_164 : UInt<1> connect _WIRE_164, _T_2985 connect _WIRE_162.wflags, _WIRE_164 node _T_2986 = mux(_T_608, deq_vec[0][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2987 = mux(_T_609, deq_vec[1][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2988 = mux(_T_610, deq_vec[2][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2989 = mux(_T_611, deq_vec[3][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2990 = mux(_T_612, deq_vec[4][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2991 = mux(_T_613, deq_vec[5][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2992 = mux(_T_614, deq_vec[6][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2993 = mux(_T_615, deq_vec[7][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2994 = or(_T_2986, _T_2987) node _T_2995 = or(_T_2994, _T_2988) node _T_2996 = or(_T_2995, _T_2989) node _T_2997 = or(_T_2996, _T_2990) node _T_2998 = or(_T_2997, _T_2991) node _T_2999 = or(_T_2998, _T_2992) node _T_3000 = or(_T_2999, _T_2993) wire _WIRE_165 : UInt<1> connect _WIRE_165, _T_3000 connect _WIRE_162.sqrt, _WIRE_165 node _T_3001 = mux(_T_608, deq_vec[0][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3002 = mux(_T_609, deq_vec[1][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3003 = mux(_T_610, deq_vec[2][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3004 = mux(_T_611, deq_vec[3][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3005 = mux(_T_612, deq_vec[4][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3006 = mux(_T_613, deq_vec[5][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3007 = mux(_T_614, deq_vec[6][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3008 = mux(_T_615, deq_vec[7][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3009 = or(_T_3001, _T_3002) node _T_3010 = or(_T_3009, _T_3003) node _T_3011 = or(_T_3010, _T_3004) node _T_3012 = or(_T_3011, _T_3005) node _T_3013 = or(_T_3012, _T_3006) node _T_3014 = or(_T_3013, _T_3007) node _T_3015 = or(_T_3014, _T_3008) wire _WIRE_166 : UInt<1> connect _WIRE_166, _T_3015 connect _WIRE_162.div, _WIRE_166 node _T_3016 = mux(_T_608, deq_vec[0][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3017 = mux(_T_609, deq_vec[1][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3018 = mux(_T_610, deq_vec[2][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3019 = mux(_T_611, deq_vec[3][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3020 = mux(_T_612, deq_vec[4][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3021 = mux(_T_613, deq_vec[5][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3022 = mux(_T_614, deq_vec[6][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3023 = mux(_T_615, deq_vec[7][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3024 = or(_T_3016, _T_3017) node _T_3025 = or(_T_3024, _T_3018) node _T_3026 = or(_T_3025, _T_3019) node _T_3027 = or(_T_3026, _T_3020) node _T_3028 = or(_T_3027, _T_3021) node _T_3029 = or(_T_3028, _T_3022) node _T_3030 = or(_T_3029, _T_3023) wire _WIRE_167 : UInt<1> connect _WIRE_167, _T_3030 connect _WIRE_162.fma, _WIRE_167 node _T_3031 = mux(_T_608, deq_vec[0][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3032 = mux(_T_609, deq_vec[1][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3033 = mux(_T_610, deq_vec[2][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3034 = mux(_T_611, deq_vec[3][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3035 = mux(_T_612, deq_vec[4][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3036 = mux(_T_613, deq_vec[5][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3037 = mux(_T_614, deq_vec[6][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3038 = mux(_T_615, deq_vec[7][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3039 = or(_T_3031, _T_3032) node _T_3040 = or(_T_3039, _T_3033) node _T_3041 = or(_T_3040, _T_3034) node _T_3042 = or(_T_3041, _T_3035) node _T_3043 = or(_T_3042, _T_3036) node _T_3044 = or(_T_3043, _T_3037) node _T_3045 = or(_T_3044, _T_3038) wire _WIRE_168 : UInt<1> connect _WIRE_168, _T_3045 connect _WIRE_162.fastpipe, _WIRE_168 node _T_3046 = mux(_T_608, deq_vec[0][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3047 = mux(_T_609, deq_vec[1][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3048 = mux(_T_610, deq_vec[2][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3049 = mux(_T_611, deq_vec[3][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3050 = mux(_T_612, deq_vec[4][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3051 = mux(_T_613, deq_vec[5][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3052 = mux(_T_614, deq_vec[6][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3053 = mux(_T_615, deq_vec[7][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3054 = or(_T_3046, _T_3047) node _T_3055 = or(_T_3054, _T_3048) node _T_3056 = or(_T_3055, _T_3049) node _T_3057 = or(_T_3056, _T_3050) node _T_3058 = or(_T_3057, _T_3051) node _T_3059 = or(_T_3058, _T_3052) node _T_3060 = or(_T_3059, _T_3053) wire _WIRE_169 : UInt<1> connect _WIRE_169, _T_3060 connect _WIRE_162.toint, _WIRE_169 node _T_3061 = mux(_T_608, deq_vec[0][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3062 = mux(_T_609, deq_vec[1][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3063 = mux(_T_610, deq_vec[2][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3064 = mux(_T_611, deq_vec[3][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3065 = mux(_T_612, deq_vec[4][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3066 = mux(_T_613, deq_vec[5][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3067 = mux(_T_614, deq_vec[6][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3068 = mux(_T_615, deq_vec[7][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3069 = or(_T_3061, _T_3062) node _T_3070 = or(_T_3069, _T_3063) node _T_3071 = or(_T_3070, _T_3064) node _T_3072 = or(_T_3071, _T_3065) node _T_3073 = or(_T_3072, _T_3066) node _T_3074 = or(_T_3073, _T_3067) node _T_3075 = or(_T_3074, _T_3068) wire _WIRE_170 : UInt<1> connect _WIRE_170, _T_3075 connect _WIRE_162.fromint, _WIRE_170 node _T_3076 = mux(_T_608, deq_vec[0][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3077 = mux(_T_609, deq_vec[1][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3078 = mux(_T_610, deq_vec[2][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3079 = mux(_T_611, deq_vec[3][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3080 = mux(_T_612, deq_vec[4][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3081 = mux(_T_613, deq_vec[5][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3082 = mux(_T_614, deq_vec[6][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3083 = mux(_T_615, deq_vec[7][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3084 = or(_T_3076, _T_3077) node _T_3085 = or(_T_3084, _T_3078) node _T_3086 = or(_T_3085, _T_3079) node _T_3087 = or(_T_3086, _T_3080) node _T_3088 = or(_T_3087, _T_3081) node _T_3089 = or(_T_3088, _T_3082) node _T_3090 = or(_T_3089, _T_3083) wire _WIRE_171 : UInt<2> connect _WIRE_171, _T_3090 connect _WIRE_162.typeTagOut, _WIRE_171 node _T_3091 = mux(_T_608, deq_vec[0][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3092 = mux(_T_609, deq_vec[1][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3093 = mux(_T_610, deq_vec[2][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3094 = mux(_T_611, deq_vec[3][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3095 = mux(_T_612, deq_vec[4][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3096 = mux(_T_613, deq_vec[5][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3097 = mux(_T_614, deq_vec[6][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3098 = mux(_T_615, deq_vec[7][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3099 = or(_T_3091, _T_3092) node _T_3100 = or(_T_3099, _T_3093) node _T_3101 = or(_T_3100, _T_3094) node _T_3102 = or(_T_3101, _T_3095) node _T_3103 = or(_T_3102, _T_3096) node _T_3104 = or(_T_3103, _T_3097) node _T_3105 = or(_T_3104, _T_3098) wire _WIRE_172 : UInt<2> connect _WIRE_172, _T_3105 connect _WIRE_162.typeTagIn, _WIRE_172 node _T_3106 = mux(_T_608, deq_vec[0][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3107 = mux(_T_609, deq_vec[1][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3108 = mux(_T_610, deq_vec[2][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3109 = mux(_T_611, deq_vec[3][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3110 = mux(_T_612, deq_vec[4][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3111 = mux(_T_613, deq_vec[5][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3112 = mux(_T_614, deq_vec[6][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3113 = mux(_T_615, deq_vec[7][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3114 = or(_T_3106, _T_3107) node _T_3115 = or(_T_3114, _T_3108) node _T_3116 = or(_T_3115, _T_3109) node _T_3117 = or(_T_3116, _T_3110) node _T_3118 = or(_T_3117, _T_3111) node _T_3119 = or(_T_3118, _T_3112) node _T_3120 = or(_T_3119, _T_3113) wire _WIRE_173 : UInt<1> connect _WIRE_173, _T_3120 connect _WIRE_162.swap23, _WIRE_173 node _T_3121 = mux(_T_608, deq_vec[0][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3122 = mux(_T_609, deq_vec[1][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3123 = mux(_T_610, deq_vec[2][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3124 = mux(_T_611, deq_vec[3][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3125 = mux(_T_612, deq_vec[4][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3126 = mux(_T_613, deq_vec[5][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3127 = mux(_T_614, deq_vec[6][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3128 = mux(_T_615, deq_vec[7][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3129 = or(_T_3121, _T_3122) node _T_3130 = or(_T_3129, _T_3123) node _T_3131 = or(_T_3130, _T_3124) node _T_3132 = or(_T_3131, _T_3125) node _T_3133 = or(_T_3132, _T_3126) node _T_3134 = or(_T_3133, _T_3127) node _T_3135 = or(_T_3134, _T_3128) wire _WIRE_174 : UInt<1> connect _WIRE_174, _T_3135 connect _WIRE_162.swap12, _WIRE_174 node _T_3136 = mux(_T_608, deq_vec[0][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3137 = mux(_T_609, deq_vec[1][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3138 = mux(_T_610, deq_vec[2][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3139 = mux(_T_611, deq_vec[3][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3140 = mux(_T_612, deq_vec[4][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3141 = mux(_T_613, deq_vec[5][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3142 = mux(_T_614, deq_vec[6][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3143 = mux(_T_615, deq_vec[7][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3144 = or(_T_3136, _T_3137) node _T_3145 = or(_T_3144, _T_3138) node _T_3146 = or(_T_3145, _T_3139) node _T_3147 = or(_T_3146, _T_3140) node _T_3148 = or(_T_3147, _T_3141) node _T_3149 = or(_T_3148, _T_3142) node _T_3150 = or(_T_3149, _T_3143) wire _WIRE_175 : UInt<1> connect _WIRE_175, _T_3150 connect _WIRE_162.ren3, _WIRE_175 node _T_3151 = mux(_T_608, deq_vec[0][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3152 = mux(_T_609, deq_vec[1][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3153 = mux(_T_610, deq_vec[2][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3154 = mux(_T_611, deq_vec[3][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3155 = mux(_T_612, deq_vec[4][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3156 = mux(_T_613, deq_vec[5][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3157 = mux(_T_614, deq_vec[6][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3158 = mux(_T_615, deq_vec[7][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3159 = or(_T_3151, _T_3152) node _T_3160 = or(_T_3159, _T_3153) node _T_3161 = or(_T_3160, _T_3154) node _T_3162 = or(_T_3161, _T_3155) node _T_3163 = or(_T_3162, _T_3156) node _T_3164 = or(_T_3163, _T_3157) node _T_3165 = or(_T_3164, _T_3158) wire _WIRE_176 : UInt<1> connect _WIRE_176, _T_3165 connect _WIRE_162.ren2, _WIRE_176 node _T_3166 = mux(_T_608, deq_vec[0][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3167 = mux(_T_609, deq_vec[1][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3168 = mux(_T_610, deq_vec[2][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3169 = mux(_T_611, deq_vec[3][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3170 = mux(_T_612, deq_vec[4][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3171 = mux(_T_613, deq_vec[5][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3172 = mux(_T_614, deq_vec[6][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3173 = mux(_T_615, deq_vec[7][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3174 = or(_T_3166, _T_3167) node _T_3175 = or(_T_3174, _T_3168) node _T_3176 = or(_T_3175, _T_3169) node _T_3177 = or(_T_3176, _T_3170) node _T_3178 = or(_T_3177, _T_3171) node _T_3179 = or(_T_3178, _T_3172) node _T_3180 = or(_T_3179, _T_3173) wire _WIRE_177 : UInt<1> connect _WIRE_177, _T_3180 connect _WIRE_162.ren1, _WIRE_177 node _T_3181 = mux(_T_608, deq_vec[0][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3182 = mux(_T_609, deq_vec[1][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3183 = mux(_T_610, deq_vec[2][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3184 = mux(_T_611, deq_vec[3][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3185 = mux(_T_612, deq_vec[4][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3186 = mux(_T_613, deq_vec[5][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3187 = mux(_T_614, deq_vec[6][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3188 = mux(_T_615, deq_vec[7][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3189 = or(_T_3181, _T_3182) node _T_3190 = or(_T_3189, _T_3183) node _T_3191 = or(_T_3190, _T_3184) node _T_3192 = or(_T_3191, _T_3185) node _T_3193 = or(_T_3192, _T_3186) node _T_3194 = or(_T_3193, _T_3187) node _T_3195 = or(_T_3194, _T_3188) wire _WIRE_178 : UInt<1> connect _WIRE_178, _T_3195 connect _WIRE_162.wen, _WIRE_178 node _T_3196 = mux(_T_608, deq_vec[0][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3197 = mux(_T_609, deq_vec[1][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3198 = mux(_T_610, deq_vec[2][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3199 = mux(_T_611, deq_vec[3][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3200 = mux(_T_612, deq_vec[4][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3201 = mux(_T_613, deq_vec[5][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3202 = mux(_T_614, deq_vec[6][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3203 = mux(_T_615, deq_vec[7][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3204 = or(_T_3196, _T_3197) node _T_3205 = or(_T_3204, _T_3198) node _T_3206 = or(_T_3205, _T_3199) node _T_3207 = or(_T_3206, _T_3200) node _T_3208 = or(_T_3207, _T_3201) node _T_3209 = or(_T_3208, _T_3202) node _T_3210 = or(_T_3209, _T_3203) wire _WIRE_179 : UInt<1> connect _WIRE_179, _T_3210 connect _WIRE_162.ldst, _WIRE_179 connect _WIRE_116.fp_ctrl, _WIRE_162 node _T_3211 = mux(_T_608, deq_vec[0][1].op2_sel, UInt<1>(0h0)) node _T_3212 = mux(_T_609, deq_vec[1][1].op2_sel, UInt<1>(0h0)) node _T_3213 = mux(_T_610, deq_vec[2][1].op2_sel, UInt<1>(0h0)) node _T_3214 = mux(_T_611, deq_vec[3][1].op2_sel, UInt<1>(0h0)) node _T_3215 = mux(_T_612, deq_vec[4][1].op2_sel, UInt<1>(0h0)) node _T_3216 = mux(_T_613, deq_vec[5][1].op2_sel, UInt<1>(0h0)) node _T_3217 = mux(_T_614, deq_vec[6][1].op2_sel, UInt<1>(0h0)) node _T_3218 = mux(_T_615, deq_vec[7][1].op2_sel, UInt<1>(0h0)) node _T_3219 = or(_T_3211, _T_3212) node _T_3220 = or(_T_3219, _T_3213) node _T_3221 = or(_T_3220, _T_3214) node _T_3222 = or(_T_3221, _T_3215) node _T_3223 = or(_T_3222, _T_3216) node _T_3224 = or(_T_3223, _T_3217) node _T_3225 = or(_T_3224, _T_3218) wire _WIRE_180 : UInt<3> connect _WIRE_180, _T_3225 connect _WIRE_116.op2_sel, _WIRE_180 node _T_3226 = mux(_T_608, deq_vec[0][1].op1_sel, UInt<1>(0h0)) node _T_3227 = mux(_T_609, deq_vec[1][1].op1_sel, UInt<1>(0h0)) node _T_3228 = mux(_T_610, deq_vec[2][1].op1_sel, UInt<1>(0h0)) node _T_3229 = mux(_T_611, deq_vec[3][1].op1_sel, UInt<1>(0h0)) node _T_3230 = mux(_T_612, deq_vec[4][1].op1_sel, UInt<1>(0h0)) node _T_3231 = mux(_T_613, deq_vec[5][1].op1_sel, UInt<1>(0h0)) node _T_3232 = mux(_T_614, deq_vec[6][1].op1_sel, UInt<1>(0h0)) node _T_3233 = mux(_T_615, deq_vec[7][1].op1_sel, UInt<1>(0h0)) node _T_3234 = or(_T_3226, _T_3227) node _T_3235 = or(_T_3234, _T_3228) node _T_3236 = or(_T_3235, _T_3229) node _T_3237 = or(_T_3236, _T_3230) node _T_3238 = or(_T_3237, _T_3231) node _T_3239 = or(_T_3238, _T_3232) node _T_3240 = or(_T_3239, _T_3233) wire _WIRE_181 : UInt<2> connect _WIRE_181, _T_3240 connect _WIRE_116.op1_sel, _WIRE_181 node _T_3241 = mux(_T_608, deq_vec[0][1].imm_packed, UInt<1>(0h0)) node _T_3242 = mux(_T_609, deq_vec[1][1].imm_packed, UInt<1>(0h0)) node _T_3243 = mux(_T_610, deq_vec[2][1].imm_packed, UInt<1>(0h0)) node _T_3244 = mux(_T_611, deq_vec[3][1].imm_packed, UInt<1>(0h0)) node _T_3245 = mux(_T_612, deq_vec[4][1].imm_packed, UInt<1>(0h0)) node _T_3246 = mux(_T_613, deq_vec[5][1].imm_packed, UInt<1>(0h0)) node _T_3247 = mux(_T_614, deq_vec[6][1].imm_packed, UInt<1>(0h0)) node _T_3248 = mux(_T_615, deq_vec[7][1].imm_packed, UInt<1>(0h0)) node _T_3249 = or(_T_3241, _T_3242) node _T_3250 = or(_T_3249, _T_3243) node _T_3251 = or(_T_3250, _T_3244) node _T_3252 = or(_T_3251, _T_3245) node _T_3253 = or(_T_3252, _T_3246) node _T_3254 = or(_T_3253, _T_3247) node _T_3255 = or(_T_3254, _T_3248) wire _WIRE_182 : UInt<20> connect _WIRE_182, _T_3255 connect _WIRE_116.imm_packed, _WIRE_182 node _T_3256 = mux(_T_608, deq_vec[0][1].pimm, UInt<1>(0h0)) node _T_3257 = mux(_T_609, deq_vec[1][1].pimm, UInt<1>(0h0)) node _T_3258 = mux(_T_610, deq_vec[2][1].pimm, UInt<1>(0h0)) node _T_3259 = mux(_T_611, deq_vec[3][1].pimm, UInt<1>(0h0)) node _T_3260 = mux(_T_612, deq_vec[4][1].pimm, UInt<1>(0h0)) node _T_3261 = mux(_T_613, deq_vec[5][1].pimm, UInt<1>(0h0)) node _T_3262 = mux(_T_614, deq_vec[6][1].pimm, UInt<1>(0h0)) node _T_3263 = mux(_T_615, deq_vec[7][1].pimm, UInt<1>(0h0)) node _T_3264 = or(_T_3256, _T_3257) node _T_3265 = or(_T_3264, _T_3258) node _T_3266 = or(_T_3265, _T_3259) node _T_3267 = or(_T_3266, _T_3260) node _T_3268 = or(_T_3267, _T_3261) node _T_3269 = or(_T_3268, _T_3262) node _T_3270 = or(_T_3269, _T_3263) wire _WIRE_183 : UInt<5> connect _WIRE_183, _T_3270 connect _WIRE_116.pimm, _WIRE_183 node _T_3271 = mux(_T_608, deq_vec[0][1].imm_sel, UInt<1>(0h0)) node _T_3272 = mux(_T_609, deq_vec[1][1].imm_sel, UInt<1>(0h0)) node _T_3273 = mux(_T_610, deq_vec[2][1].imm_sel, UInt<1>(0h0)) node _T_3274 = mux(_T_611, deq_vec[3][1].imm_sel, UInt<1>(0h0)) node _T_3275 = mux(_T_612, deq_vec[4][1].imm_sel, UInt<1>(0h0)) node _T_3276 = mux(_T_613, deq_vec[5][1].imm_sel, UInt<1>(0h0)) node _T_3277 = mux(_T_614, deq_vec[6][1].imm_sel, UInt<1>(0h0)) node _T_3278 = mux(_T_615, deq_vec[7][1].imm_sel, UInt<1>(0h0)) node _T_3279 = or(_T_3271, _T_3272) node _T_3280 = or(_T_3279, _T_3273) node _T_3281 = or(_T_3280, _T_3274) node _T_3282 = or(_T_3281, _T_3275) node _T_3283 = or(_T_3282, _T_3276) node _T_3284 = or(_T_3283, _T_3277) node _T_3285 = or(_T_3284, _T_3278) wire _WIRE_184 : UInt<3> connect _WIRE_184, _T_3285 connect _WIRE_116.imm_sel, _WIRE_184 node _T_3286 = mux(_T_608, deq_vec[0][1].imm_rename, UInt<1>(0h0)) node _T_3287 = mux(_T_609, deq_vec[1][1].imm_rename, UInt<1>(0h0)) node _T_3288 = mux(_T_610, deq_vec[2][1].imm_rename, UInt<1>(0h0)) node _T_3289 = mux(_T_611, deq_vec[3][1].imm_rename, UInt<1>(0h0)) node _T_3290 = mux(_T_612, deq_vec[4][1].imm_rename, UInt<1>(0h0)) node _T_3291 = mux(_T_613, deq_vec[5][1].imm_rename, UInt<1>(0h0)) node _T_3292 = mux(_T_614, deq_vec[6][1].imm_rename, UInt<1>(0h0)) node _T_3293 = mux(_T_615, deq_vec[7][1].imm_rename, UInt<1>(0h0)) node _T_3294 = or(_T_3286, _T_3287) node _T_3295 = or(_T_3294, _T_3288) node _T_3296 = or(_T_3295, _T_3289) node _T_3297 = or(_T_3296, _T_3290) node _T_3298 = or(_T_3297, _T_3291) node _T_3299 = or(_T_3298, _T_3292) node _T_3300 = or(_T_3299, _T_3293) wire _WIRE_185 : UInt<1> connect _WIRE_185, _T_3300 connect _WIRE_116.imm_rename, _WIRE_185 node _T_3301 = mux(_T_608, deq_vec[0][1].taken, UInt<1>(0h0)) node _T_3302 = mux(_T_609, deq_vec[1][1].taken, UInt<1>(0h0)) node _T_3303 = mux(_T_610, deq_vec[2][1].taken, UInt<1>(0h0)) node _T_3304 = mux(_T_611, deq_vec[3][1].taken, UInt<1>(0h0)) node _T_3305 = mux(_T_612, deq_vec[4][1].taken, UInt<1>(0h0)) node _T_3306 = mux(_T_613, deq_vec[5][1].taken, UInt<1>(0h0)) node _T_3307 = mux(_T_614, deq_vec[6][1].taken, UInt<1>(0h0)) node _T_3308 = mux(_T_615, deq_vec[7][1].taken, UInt<1>(0h0)) node _T_3309 = or(_T_3301, _T_3302) node _T_3310 = or(_T_3309, _T_3303) node _T_3311 = or(_T_3310, _T_3304) node _T_3312 = or(_T_3311, _T_3305) node _T_3313 = or(_T_3312, _T_3306) node _T_3314 = or(_T_3313, _T_3307) node _T_3315 = or(_T_3314, _T_3308) wire _WIRE_186 : UInt<1> connect _WIRE_186, _T_3315 connect _WIRE_116.taken, _WIRE_186 node _T_3316 = mux(_T_608, deq_vec[0][1].pc_lob, UInt<1>(0h0)) node _T_3317 = mux(_T_609, deq_vec[1][1].pc_lob, UInt<1>(0h0)) node _T_3318 = mux(_T_610, deq_vec[2][1].pc_lob, UInt<1>(0h0)) node _T_3319 = mux(_T_611, deq_vec[3][1].pc_lob, UInt<1>(0h0)) node _T_3320 = mux(_T_612, deq_vec[4][1].pc_lob, UInt<1>(0h0)) node _T_3321 = mux(_T_613, deq_vec[5][1].pc_lob, UInt<1>(0h0)) node _T_3322 = mux(_T_614, deq_vec[6][1].pc_lob, UInt<1>(0h0)) node _T_3323 = mux(_T_615, deq_vec[7][1].pc_lob, UInt<1>(0h0)) node _T_3324 = or(_T_3316, _T_3317) node _T_3325 = or(_T_3324, _T_3318) node _T_3326 = or(_T_3325, _T_3319) node _T_3327 = or(_T_3326, _T_3320) node _T_3328 = or(_T_3327, _T_3321) node _T_3329 = or(_T_3328, _T_3322) node _T_3330 = or(_T_3329, _T_3323) wire _WIRE_187 : UInt<6> connect _WIRE_187, _T_3330 connect _WIRE_116.pc_lob, _WIRE_187 node _T_3331 = mux(_T_608, deq_vec[0][1].edge_inst, UInt<1>(0h0)) node _T_3332 = mux(_T_609, deq_vec[1][1].edge_inst, UInt<1>(0h0)) node _T_3333 = mux(_T_610, deq_vec[2][1].edge_inst, UInt<1>(0h0)) node _T_3334 = mux(_T_611, deq_vec[3][1].edge_inst, UInt<1>(0h0)) node _T_3335 = mux(_T_612, deq_vec[4][1].edge_inst, UInt<1>(0h0)) node _T_3336 = mux(_T_613, deq_vec[5][1].edge_inst, UInt<1>(0h0)) node _T_3337 = mux(_T_614, deq_vec[6][1].edge_inst, UInt<1>(0h0)) node _T_3338 = mux(_T_615, deq_vec[7][1].edge_inst, UInt<1>(0h0)) node _T_3339 = or(_T_3331, _T_3332) node _T_3340 = or(_T_3339, _T_3333) node _T_3341 = or(_T_3340, _T_3334) node _T_3342 = or(_T_3341, _T_3335) node _T_3343 = or(_T_3342, _T_3336) node _T_3344 = or(_T_3343, _T_3337) node _T_3345 = or(_T_3344, _T_3338) wire _WIRE_188 : UInt<1> connect _WIRE_188, _T_3345 connect _WIRE_116.edge_inst, _WIRE_188 node _T_3346 = mux(_T_608, deq_vec[0][1].ftq_idx, UInt<1>(0h0)) node _T_3347 = mux(_T_609, deq_vec[1][1].ftq_idx, UInt<1>(0h0)) node _T_3348 = mux(_T_610, deq_vec[2][1].ftq_idx, UInt<1>(0h0)) node _T_3349 = mux(_T_611, deq_vec[3][1].ftq_idx, UInt<1>(0h0)) node _T_3350 = mux(_T_612, deq_vec[4][1].ftq_idx, UInt<1>(0h0)) node _T_3351 = mux(_T_613, deq_vec[5][1].ftq_idx, UInt<1>(0h0)) node _T_3352 = mux(_T_614, deq_vec[6][1].ftq_idx, UInt<1>(0h0)) node _T_3353 = mux(_T_615, deq_vec[7][1].ftq_idx, UInt<1>(0h0)) node _T_3354 = or(_T_3346, _T_3347) node _T_3355 = or(_T_3354, _T_3348) node _T_3356 = or(_T_3355, _T_3349) node _T_3357 = or(_T_3356, _T_3350) node _T_3358 = or(_T_3357, _T_3351) node _T_3359 = or(_T_3358, _T_3352) node _T_3360 = or(_T_3359, _T_3353) wire _WIRE_189 : UInt<5> connect _WIRE_189, _T_3360 connect _WIRE_116.ftq_idx, _WIRE_189 node _T_3361 = mux(_T_608, deq_vec[0][1].is_mov, UInt<1>(0h0)) node _T_3362 = mux(_T_609, deq_vec[1][1].is_mov, UInt<1>(0h0)) node _T_3363 = mux(_T_610, deq_vec[2][1].is_mov, UInt<1>(0h0)) node _T_3364 = mux(_T_611, deq_vec[3][1].is_mov, UInt<1>(0h0)) node _T_3365 = mux(_T_612, deq_vec[4][1].is_mov, UInt<1>(0h0)) node _T_3366 = mux(_T_613, deq_vec[5][1].is_mov, UInt<1>(0h0)) node _T_3367 = mux(_T_614, deq_vec[6][1].is_mov, UInt<1>(0h0)) node _T_3368 = mux(_T_615, deq_vec[7][1].is_mov, UInt<1>(0h0)) node _T_3369 = or(_T_3361, _T_3362) node _T_3370 = or(_T_3369, _T_3363) node _T_3371 = or(_T_3370, _T_3364) node _T_3372 = or(_T_3371, _T_3365) node _T_3373 = or(_T_3372, _T_3366) node _T_3374 = or(_T_3373, _T_3367) node _T_3375 = or(_T_3374, _T_3368) wire _WIRE_190 : UInt<1> connect _WIRE_190, _T_3375 connect _WIRE_116.is_mov, _WIRE_190 node _T_3376 = mux(_T_608, deq_vec[0][1].is_rocc, UInt<1>(0h0)) node _T_3377 = mux(_T_609, deq_vec[1][1].is_rocc, UInt<1>(0h0)) node _T_3378 = mux(_T_610, deq_vec[2][1].is_rocc, UInt<1>(0h0)) node _T_3379 = mux(_T_611, deq_vec[3][1].is_rocc, UInt<1>(0h0)) node _T_3380 = mux(_T_612, deq_vec[4][1].is_rocc, UInt<1>(0h0)) node _T_3381 = mux(_T_613, deq_vec[5][1].is_rocc, UInt<1>(0h0)) node _T_3382 = mux(_T_614, deq_vec[6][1].is_rocc, UInt<1>(0h0)) node _T_3383 = mux(_T_615, deq_vec[7][1].is_rocc, UInt<1>(0h0)) node _T_3384 = or(_T_3376, _T_3377) node _T_3385 = or(_T_3384, _T_3378) node _T_3386 = or(_T_3385, _T_3379) node _T_3387 = or(_T_3386, _T_3380) node _T_3388 = or(_T_3387, _T_3381) node _T_3389 = or(_T_3388, _T_3382) node _T_3390 = or(_T_3389, _T_3383) wire _WIRE_191 : UInt<1> connect _WIRE_191, _T_3390 connect _WIRE_116.is_rocc, _WIRE_191 node _T_3391 = mux(_T_608, deq_vec[0][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3392 = mux(_T_609, deq_vec[1][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3393 = mux(_T_610, deq_vec[2][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3394 = mux(_T_611, deq_vec[3][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3395 = mux(_T_612, deq_vec[4][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3396 = mux(_T_613, deq_vec[5][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3397 = mux(_T_614, deq_vec[6][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3398 = mux(_T_615, deq_vec[7][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3399 = or(_T_3391, _T_3392) node _T_3400 = or(_T_3399, _T_3393) node _T_3401 = or(_T_3400, _T_3394) node _T_3402 = or(_T_3401, _T_3395) node _T_3403 = or(_T_3402, _T_3396) node _T_3404 = or(_T_3403, _T_3397) node _T_3405 = or(_T_3404, _T_3398) wire _WIRE_192 : UInt<1> connect _WIRE_192, _T_3405 connect _WIRE_116.is_sys_pc2epc, _WIRE_192 node _T_3406 = mux(_T_608, deq_vec[0][1].is_eret, UInt<1>(0h0)) node _T_3407 = mux(_T_609, deq_vec[1][1].is_eret, UInt<1>(0h0)) node _T_3408 = mux(_T_610, deq_vec[2][1].is_eret, UInt<1>(0h0)) node _T_3409 = mux(_T_611, deq_vec[3][1].is_eret, UInt<1>(0h0)) node _T_3410 = mux(_T_612, deq_vec[4][1].is_eret, UInt<1>(0h0)) node _T_3411 = mux(_T_613, deq_vec[5][1].is_eret, UInt<1>(0h0)) node _T_3412 = mux(_T_614, deq_vec[6][1].is_eret, UInt<1>(0h0)) node _T_3413 = mux(_T_615, deq_vec[7][1].is_eret, UInt<1>(0h0)) node _T_3414 = or(_T_3406, _T_3407) node _T_3415 = or(_T_3414, _T_3408) node _T_3416 = or(_T_3415, _T_3409) node _T_3417 = or(_T_3416, _T_3410) node _T_3418 = or(_T_3417, _T_3411) node _T_3419 = or(_T_3418, _T_3412) node _T_3420 = or(_T_3419, _T_3413) wire _WIRE_193 : UInt<1> connect _WIRE_193, _T_3420 connect _WIRE_116.is_eret, _WIRE_193 node _T_3421 = mux(_T_608, deq_vec[0][1].is_amo, UInt<1>(0h0)) node _T_3422 = mux(_T_609, deq_vec[1][1].is_amo, UInt<1>(0h0)) node _T_3423 = mux(_T_610, deq_vec[2][1].is_amo, UInt<1>(0h0)) node _T_3424 = mux(_T_611, deq_vec[3][1].is_amo, UInt<1>(0h0)) node _T_3425 = mux(_T_612, deq_vec[4][1].is_amo, UInt<1>(0h0)) node _T_3426 = mux(_T_613, deq_vec[5][1].is_amo, UInt<1>(0h0)) node _T_3427 = mux(_T_614, deq_vec[6][1].is_amo, UInt<1>(0h0)) node _T_3428 = mux(_T_615, deq_vec[7][1].is_amo, UInt<1>(0h0)) node _T_3429 = or(_T_3421, _T_3422) node _T_3430 = or(_T_3429, _T_3423) node _T_3431 = or(_T_3430, _T_3424) node _T_3432 = or(_T_3431, _T_3425) node _T_3433 = or(_T_3432, _T_3426) node _T_3434 = or(_T_3433, _T_3427) node _T_3435 = or(_T_3434, _T_3428) wire _WIRE_194 : UInt<1> connect _WIRE_194, _T_3435 connect _WIRE_116.is_amo, _WIRE_194 node _T_3436 = mux(_T_608, deq_vec[0][1].is_sfence, UInt<1>(0h0)) node _T_3437 = mux(_T_609, deq_vec[1][1].is_sfence, UInt<1>(0h0)) node _T_3438 = mux(_T_610, deq_vec[2][1].is_sfence, UInt<1>(0h0)) node _T_3439 = mux(_T_611, deq_vec[3][1].is_sfence, UInt<1>(0h0)) node _T_3440 = mux(_T_612, deq_vec[4][1].is_sfence, UInt<1>(0h0)) node _T_3441 = mux(_T_613, deq_vec[5][1].is_sfence, UInt<1>(0h0)) node _T_3442 = mux(_T_614, deq_vec[6][1].is_sfence, UInt<1>(0h0)) node _T_3443 = mux(_T_615, deq_vec[7][1].is_sfence, UInt<1>(0h0)) node _T_3444 = or(_T_3436, _T_3437) node _T_3445 = or(_T_3444, _T_3438) node _T_3446 = or(_T_3445, _T_3439) node _T_3447 = or(_T_3446, _T_3440) node _T_3448 = or(_T_3447, _T_3441) node _T_3449 = or(_T_3448, _T_3442) node _T_3450 = or(_T_3449, _T_3443) wire _WIRE_195 : UInt<1> connect _WIRE_195, _T_3450 connect _WIRE_116.is_sfence, _WIRE_195 node _T_3451 = mux(_T_608, deq_vec[0][1].is_fencei, UInt<1>(0h0)) node _T_3452 = mux(_T_609, deq_vec[1][1].is_fencei, UInt<1>(0h0)) node _T_3453 = mux(_T_610, deq_vec[2][1].is_fencei, UInt<1>(0h0)) node _T_3454 = mux(_T_611, deq_vec[3][1].is_fencei, UInt<1>(0h0)) node _T_3455 = mux(_T_612, deq_vec[4][1].is_fencei, UInt<1>(0h0)) node _T_3456 = mux(_T_613, deq_vec[5][1].is_fencei, UInt<1>(0h0)) node _T_3457 = mux(_T_614, deq_vec[6][1].is_fencei, UInt<1>(0h0)) node _T_3458 = mux(_T_615, deq_vec[7][1].is_fencei, UInt<1>(0h0)) node _T_3459 = or(_T_3451, _T_3452) node _T_3460 = or(_T_3459, _T_3453) node _T_3461 = or(_T_3460, _T_3454) node _T_3462 = or(_T_3461, _T_3455) node _T_3463 = or(_T_3462, _T_3456) node _T_3464 = or(_T_3463, _T_3457) node _T_3465 = or(_T_3464, _T_3458) wire _WIRE_196 : UInt<1> connect _WIRE_196, _T_3465 connect _WIRE_116.is_fencei, _WIRE_196 node _T_3466 = mux(_T_608, deq_vec[0][1].is_fence, UInt<1>(0h0)) node _T_3467 = mux(_T_609, deq_vec[1][1].is_fence, UInt<1>(0h0)) node _T_3468 = mux(_T_610, deq_vec[2][1].is_fence, UInt<1>(0h0)) node _T_3469 = mux(_T_611, deq_vec[3][1].is_fence, UInt<1>(0h0)) node _T_3470 = mux(_T_612, deq_vec[4][1].is_fence, UInt<1>(0h0)) node _T_3471 = mux(_T_613, deq_vec[5][1].is_fence, UInt<1>(0h0)) node _T_3472 = mux(_T_614, deq_vec[6][1].is_fence, UInt<1>(0h0)) node _T_3473 = mux(_T_615, deq_vec[7][1].is_fence, UInt<1>(0h0)) node _T_3474 = or(_T_3466, _T_3467) node _T_3475 = or(_T_3474, _T_3468) node _T_3476 = or(_T_3475, _T_3469) node _T_3477 = or(_T_3476, _T_3470) node _T_3478 = or(_T_3477, _T_3471) node _T_3479 = or(_T_3478, _T_3472) node _T_3480 = or(_T_3479, _T_3473) wire _WIRE_197 : UInt<1> connect _WIRE_197, _T_3480 connect _WIRE_116.is_fence, _WIRE_197 node _T_3481 = mux(_T_608, deq_vec[0][1].is_sfb, UInt<1>(0h0)) node _T_3482 = mux(_T_609, deq_vec[1][1].is_sfb, UInt<1>(0h0)) node _T_3483 = mux(_T_610, deq_vec[2][1].is_sfb, UInt<1>(0h0)) node _T_3484 = mux(_T_611, deq_vec[3][1].is_sfb, UInt<1>(0h0)) node _T_3485 = mux(_T_612, deq_vec[4][1].is_sfb, UInt<1>(0h0)) node _T_3486 = mux(_T_613, deq_vec[5][1].is_sfb, UInt<1>(0h0)) node _T_3487 = mux(_T_614, deq_vec[6][1].is_sfb, UInt<1>(0h0)) node _T_3488 = mux(_T_615, deq_vec[7][1].is_sfb, UInt<1>(0h0)) node _T_3489 = or(_T_3481, _T_3482) node _T_3490 = or(_T_3489, _T_3483) node _T_3491 = or(_T_3490, _T_3484) node _T_3492 = or(_T_3491, _T_3485) node _T_3493 = or(_T_3492, _T_3486) node _T_3494 = or(_T_3493, _T_3487) node _T_3495 = or(_T_3494, _T_3488) wire _WIRE_198 : UInt<1> connect _WIRE_198, _T_3495 connect _WIRE_116.is_sfb, _WIRE_198 node _T_3496 = mux(_T_608, deq_vec[0][1].br_type, UInt<1>(0h0)) node _T_3497 = mux(_T_609, deq_vec[1][1].br_type, UInt<1>(0h0)) node _T_3498 = mux(_T_610, deq_vec[2][1].br_type, UInt<1>(0h0)) node _T_3499 = mux(_T_611, deq_vec[3][1].br_type, UInt<1>(0h0)) node _T_3500 = mux(_T_612, deq_vec[4][1].br_type, UInt<1>(0h0)) node _T_3501 = mux(_T_613, deq_vec[5][1].br_type, UInt<1>(0h0)) node _T_3502 = mux(_T_614, deq_vec[6][1].br_type, UInt<1>(0h0)) node _T_3503 = mux(_T_615, deq_vec[7][1].br_type, UInt<1>(0h0)) node _T_3504 = or(_T_3496, _T_3497) node _T_3505 = or(_T_3504, _T_3498) node _T_3506 = or(_T_3505, _T_3499) node _T_3507 = or(_T_3506, _T_3500) node _T_3508 = or(_T_3507, _T_3501) node _T_3509 = or(_T_3508, _T_3502) node _T_3510 = or(_T_3509, _T_3503) wire _WIRE_199 : UInt<4> connect _WIRE_199, _T_3510 connect _WIRE_116.br_type, _WIRE_199 node _T_3511 = mux(_T_608, deq_vec[0][1].br_tag, UInt<1>(0h0)) node _T_3512 = mux(_T_609, deq_vec[1][1].br_tag, UInt<1>(0h0)) node _T_3513 = mux(_T_610, deq_vec[2][1].br_tag, UInt<1>(0h0)) node _T_3514 = mux(_T_611, deq_vec[3][1].br_tag, UInt<1>(0h0)) node _T_3515 = mux(_T_612, deq_vec[4][1].br_tag, UInt<1>(0h0)) node _T_3516 = mux(_T_613, deq_vec[5][1].br_tag, UInt<1>(0h0)) node _T_3517 = mux(_T_614, deq_vec[6][1].br_tag, UInt<1>(0h0)) node _T_3518 = mux(_T_615, deq_vec[7][1].br_tag, UInt<1>(0h0)) node _T_3519 = or(_T_3511, _T_3512) node _T_3520 = or(_T_3519, _T_3513) node _T_3521 = or(_T_3520, _T_3514) node _T_3522 = or(_T_3521, _T_3515) node _T_3523 = or(_T_3522, _T_3516) node _T_3524 = or(_T_3523, _T_3517) node _T_3525 = or(_T_3524, _T_3518) wire _WIRE_200 : UInt<4> connect _WIRE_200, _T_3525 connect _WIRE_116.br_tag, _WIRE_200 node _T_3526 = mux(_T_608, deq_vec[0][1].br_mask, UInt<1>(0h0)) node _T_3527 = mux(_T_609, deq_vec[1][1].br_mask, UInt<1>(0h0)) node _T_3528 = mux(_T_610, deq_vec[2][1].br_mask, UInt<1>(0h0)) node _T_3529 = mux(_T_611, deq_vec[3][1].br_mask, UInt<1>(0h0)) node _T_3530 = mux(_T_612, deq_vec[4][1].br_mask, UInt<1>(0h0)) node _T_3531 = mux(_T_613, deq_vec[5][1].br_mask, UInt<1>(0h0)) node _T_3532 = mux(_T_614, deq_vec[6][1].br_mask, UInt<1>(0h0)) node _T_3533 = mux(_T_615, deq_vec[7][1].br_mask, UInt<1>(0h0)) node _T_3534 = or(_T_3526, _T_3527) node _T_3535 = or(_T_3534, _T_3528) node _T_3536 = or(_T_3535, _T_3529) node _T_3537 = or(_T_3536, _T_3530) node _T_3538 = or(_T_3537, _T_3531) node _T_3539 = or(_T_3538, _T_3532) node _T_3540 = or(_T_3539, _T_3533) wire _WIRE_201 : UInt<16> connect _WIRE_201, _T_3540 connect _WIRE_116.br_mask, _WIRE_201 node _T_3541 = mux(_T_608, deq_vec[0][1].dis_col_sel, UInt<1>(0h0)) node _T_3542 = mux(_T_609, deq_vec[1][1].dis_col_sel, UInt<1>(0h0)) node _T_3543 = mux(_T_610, deq_vec[2][1].dis_col_sel, UInt<1>(0h0)) node _T_3544 = mux(_T_611, deq_vec[3][1].dis_col_sel, UInt<1>(0h0)) node _T_3545 = mux(_T_612, deq_vec[4][1].dis_col_sel, UInt<1>(0h0)) node _T_3546 = mux(_T_613, deq_vec[5][1].dis_col_sel, UInt<1>(0h0)) node _T_3547 = mux(_T_614, deq_vec[6][1].dis_col_sel, UInt<1>(0h0)) node _T_3548 = mux(_T_615, deq_vec[7][1].dis_col_sel, UInt<1>(0h0)) node _T_3549 = or(_T_3541, _T_3542) node _T_3550 = or(_T_3549, _T_3543) node _T_3551 = or(_T_3550, _T_3544) node _T_3552 = or(_T_3551, _T_3545) node _T_3553 = or(_T_3552, _T_3546) node _T_3554 = or(_T_3553, _T_3547) node _T_3555 = or(_T_3554, _T_3548) wire _WIRE_202 : UInt<3> connect _WIRE_202, _T_3555 connect _WIRE_116.dis_col_sel, _WIRE_202 node _T_3556 = mux(_T_608, deq_vec[0][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3557 = mux(_T_609, deq_vec[1][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3558 = mux(_T_610, deq_vec[2][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3559 = mux(_T_611, deq_vec[3][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3560 = mux(_T_612, deq_vec[4][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3561 = mux(_T_613, deq_vec[5][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3562 = mux(_T_614, deq_vec[6][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3563 = mux(_T_615, deq_vec[7][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3564 = or(_T_3556, _T_3557) node _T_3565 = or(_T_3564, _T_3558) node _T_3566 = or(_T_3565, _T_3559) node _T_3567 = or(_T_3566, _T_3560) node _T_3568 = or(_T_3567, _T_3561) node _T_3569 = or(_T_3568, _T_3562) node _T_3570 = or(_T_3569, _T_3563) wire _WIRE_203 : UInt<1> connect _WIRE_203, _T_3570 connect _WIRE_116.iw_p3_bypass_hint, _WIRE_203 node _T_3571 = mux(_T_608, deq_vec[0][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3572 = mux(_T_609, deq_vec[1][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3573 = mux(_T_610, deq_vec[2][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3574 = mux(_T_611, deq_vec[3][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3575 = mux(_T_612, deq_vec[4][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3576 = mux(_T_613, deq_vec[5][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3577 = mux(_T_614, deq_vec[6][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3578 = mux(_T_615, deq_vec[7][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3579 = or(_T_3571, _T_3572) node _T_3580 = or(_T_3579, _T_3573) node _T_3581 = or(_T_3580, _T_3574) node _T_3582 = or(_T_3581, _T_3575) node _T_3583 = or(_T_3582, _T_3576) node _T_3584 = or(_T_3583, _T_3577) node _T_3585 = or(_T_3584, _T_3578) wire _WIRE_204 : UInt<1> connect _WIRE_204, _T_3585 connect _WIRE_116.iw_p2_bypass_hint, _WIRE_204 node _T_3586 = mux(_T_608, deq_vec[0][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3587 = mux(_T_609, deq_vec[1][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3588 = mux(_T_610, deq_vec[2][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3589 = mux(_T_611, deq_vec[3][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3590 = mux(_T_612, deq_vec[4][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3591 = mux(_T_613, deq_vec[5][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3592 = mux(_T_614, deq_vec[6][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3593 = mux(_T_615, deq_vec[7][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3594 = or(_T_3586, _T_3587) node _T_3595 = or(_T_3594, _T_3588) node _T_3596 = or(_T_3595, _T_3589) node _T_3597 = or(_T_3596, _T_3590) node _T_3598 = or(_T_3597, _T_3591) node _T_3599 = or(_T_3598, _T_3592) node _T_3600 = or(_T_3599, _T_3593) wire _WIRE_205 : UInt<1> connect _WIRE_205, _T_3600 connect _WIRE_116.iw_p1_bypass_hint, _WIRE_205 node _T_3601 = mux(_T_608, deq_vec[0][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3602 = mux(_T_609, deq_vec[1][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3603 = mux(_T_610, deq_vec[2][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3604 = mux(_T_611, deq_vec[3][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3605 = mux(_T_612, deq_vec[4][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3606 = mux(_T_613, deq_vec[5][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3607 = mux(_T_614, deq_vec[6][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3608 = mux(_T_615, deq_vec[7][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3609 = or(_T_3601, _T_3602) node _T_3610 = or(_T_3609, _T_3603) node _T_3611 = or(_T_3610, _T_3604) node _T_3612 = or(_T_3611, _T_3605) node _T_3613 = or(_T_3612, _T_3606) node _T_3614 = or(_T_3613, _T_3607) node _T_3615 = or(_T_3614, _T_3608) wire _WIRE_206 : UInt<3> connect _WIRE_206, _T_3615 connect _WIRE_116.iw_p2_speculative_child, _WIRE_206 node _T_3616 = mux(_T_608, deq_vec[0][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3617 = mux(_T_609, deq_vec[1][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3618 = mux(_T_610, deq_vec[2][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3619 = mux(_T_611, deq_vec[3][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3620 = mux(_T_612, deq_vec[4][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3621 = mux(_T_613, deq_vec[5][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3622 = mux(_T_614, deq_vec[6][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3623 = mux(_T_615, deq_vec[7][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3624 = or(_T_3616, _T_3617) node _T_3625 = or(_T_3624, _T_3618) node _T_3626 = or(_T_3625, _T_3619) node _T_3627 = or(_T_3626, _T_3620) node _T_3628 = or(_T_3627, _T_3621) node _T_3629 = or(_T_3628, _T_3622) node _T_3630 = or(_T_3629, _T_3623) wire _WIRE_207 : UInt<3> connect _WIRE_207, _T_3630 connect _WIRE_116.iw_p1_speculative_child, _WIRE_207 node _T_3631 = mux(_T_608, deq_vec[0][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3632 = mux(_T_609, deq_vec[1][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3633 = mux(_T_610, deq_vec[2][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3634 = mux(_T_611, deq_vec[3][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3635 = mux(_T_612, deq_vec[4][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3636 = mux(_T_613, deq_vec[5][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3637 = mux(_T_614, deq_vec[6][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3638 = mux(_T_615, deq_vec[7][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3639 = or(_T_3631, _T_3632) node _T_3640 = or(_T_3639, _T_3633) node _T_3641 = or(_T_3640, _T_3634) node _T_3642 = or(_T_3641, _T_3635) node _T_3643 = or(_T_3642, _T_3636) node _T_3644 = or(_T_3643, _T_3637) node _T_3645 = or(_T_3644, _T_3638) wire _WIRE_208 : UInt<1> connect _WIRE_208, _T_3645 connect _WIRE_116.iw_issued_partial_dgen, _WIRE_208 node _T_3646 = mux(_T_608, deq_vec[0][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3647 = mux(_T_609, deq_vec[1][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3648 = mux(_T_610, deq_vec[2][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3649 = mux(_T_611, deq_vec[3][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3650 = mux(_T_612, deq_vec[4][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3651 = mux(_T_613, deq_vec[5][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3652 = mux(_T_614, deq_vec[6][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3653 = mux(_T_615, deq_vec[7][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3654 = or(_T_3646, _T_3647) node _T_3655 = or(_T_3654, _T_3648) node _T_3656 = or(_T_3655, _T_3649) node _T_3657 = or(_T_3656, _T_3650) node _T_3658 = or(_T_3657, _T_3651) node _T_3659 = or(_T_3658, _T_3652) node _T_3660 = or(_T_3659, _T_3653) wire _WIRE_209 : UInt<1> connect _WIRE_209, _T_3660 connect _WIRE_116.iw_issued_partial_agen, _WIRE_209 node _T_3661 = mux(_T_608, deq_vec[0][1].iw_issued, UInt<1>(0h0)) node _T_3662 = mux(_T_609, deq_vec[1][1].iw_issued, UInt<1>(0h0)) node _T_3663 = mux(_T_610, deq_vec[2][1].iw_issued, UInt<1>(0h0)) node _T_3664 = mux(_T_611, deq_vec[3][1].iw_issued, UInt<1>(0h0)) node _T_3665 = mux(_T_612, deq_vec[4][1].iw_issued, UInt<1>(0h0)) node _T_3666 = mux(_T_613, deq_vec[5][1].iw_issued, UInt<1>(0h0)) node _T_3667 = mux(_T_614, deq_vec[6][1].iw_issued, UInt<1>(0h0)) node _T_3668 = mux(_T_615, deq_vec[7][1].iw_issued, UInt<1>(0h0)) node _T_3669 = or(_T_3661, _T_3662) node _T_3670 = or(_T_3669, _T_3663) node _T_3671 = or(_T_3670, _T_3664) node _T_3672 = or(_T_3671, _T_3665) node _T_3673 = or(_T_3672, _T_3666) node _T_3674 = or(_T_3673, _T_3667) node _T_3675 = or(_T_3674, _T_3668) wire _WIRE_210 : UInt<1> connect _WIRE_210, _T_3675 connect _WIRE_116.iw_issued, _WIRE_210 wire _WIRE_211 : UInt<1>[10] node _T_3676 = mux(_T_608, deq_vec[0][1].fu_code[0], UInt<1>(0h0)) node _T_3677 = mux(_T_609, deq_vec[1][1].fu_code[0], UInt<1>(0h0)) node _T_3678 = mux(_T_610, deq_vec[2][1].fu_code[0], UInt<1>(0h0)) node _T_3679 = mux(_T_611, deq_vec[3][1].fu_code[0], UInt<1>(0h0)) node _T_3680 = mux(_T_612, deq_vec[4][1].fu_code[0], UInt<1>(0h0)) node _T_3681 = mux(_T_613, deq_vec[5][1].fu_code[0], UInt<1>(0h0)) node _T_3682 = mux(_T_614, deq_vec[6][1].fu_code[0], UInt<1>(0h0)) node _T_3683 = mux(_T_615, deq_vec[7][1].fu_code[0], UInt<1>(0h0)) node _T_3684 = or(_T_3676, _T_3677) node _T_3685 = or(_T_3684, _T_3678) node _T_3686 = or(_T_3685, _T_3679) node _T_3687 = or(_T_3686, _T_3680) node _T_3688 = or(_T_3687, _T_3681) node _T_3689 = or(_T_3688, _T_3682) node _T_3690 = or(_T_3689, _T_3683) wire _WIRE_212 : UInt<1> connect _WIRE_212, _T_3690 connect _WIRE_211[0], _WIRE_212 node _T_3691 = mux(_T_608, deq_vec[0][1].fu_code[1], UInt<1>(0h0)) node _T_3692 = mux(_T_609, deq_vec[1][1].fu_code[1], UInt<1>(0h0)) node _T_3693 = mux(_T_610, deq_vec[2][1].fu_code[1], UInt<1>(0h0)) node _T_3694 = mux(_T_611, deq_vec[3][1].fu_code[1], UInt<1>(0h0)) node _T_3695 = mux(_T_612, deq_vec[4][1].fu_code[1], UInt<1>(0h0)) node _T_3696 = mux(_T_613, deq_vec[5][1].fu_code[1], UInt<1>(0h0)) node _T_3697 = mux(_T_614, deq_vec[6][1].fu_code[1], UInt<1>(0h0)) node _T_3698 = mux(_T_615, deq_vec[7][1].fu_code[1], UInt<1>(0h0)) node _T_3699 = or(_T_3691, _T_3692) node _T_3700 = or(_T_3699, _T_3693) node _T_3701 = or(_T_3700, _T_3694) node _T_3702 = or(_T_3701, _T_3695) node _T_3703 = or(_T_3702, _T_3696) node _T_3704 = or(_T_3703, _T_3697) node _T_3705 = or(_T_3704, _T_3698) wire _WIRE_213 : UInt<1> connect _WIRE_213, _T_3705 connect _WIRE_211[1], _WIRE_213 node _T_3706 = mux(_T_608, deq_vec[0][1].fu_code[2], UInt<1>(0h0)) node _T_3707 = mux(_T_609, deq_vec[1][1].fu_code[2], UInt<1>(0h0)) node _T_3708 = mux(_T_610, deq_vec[2][1].fu_code[2], UInt<1>(0h0)) node _T_3709 = mux(_T_611, deq_vec[3][1].fu_code[2], UInt<1>(0h0)) node _T_3710 = mux(_T_612, deq_vec[4][1].fu_code[2], UInt<1>(0h0)) node _T_3711 = mux(_T_613, deq_vec[5][1].fu_code[2], UInt<1>(0h0)) node _T_3712 = mux(_T_614, deq_vec[6][1].fu_code[2], UInt<1>(0h0)) node _T_3713 = mux(_T_615, deq_vec[7][1].fu_code[2], UInt<1>(0h0)) node _T_3714 = or(_T_3706, _T_3707) node _T_3715 = or(_T_3714, _T_3708) node _T_3716 = or(_T_3715, _T_3709) node _T_3717 = or(_T_3716, _T_3710) node _T_3718 = or(_T_3717, _T_3711) node _T_3719 = or(_T_3718, _T_3712) node _T_3720 = or(_T_3719, _T_3713) wire _WIRE_214 : UInt<1> connect _WIRE_214, _T_3720 connect _WIRE_211[2], _WIRE_214 node _T_3721 = mux(_T_608, deq_vec[0][1].fu_code[3], UInt<1>(0h0)) node _T_3722 = mux(_T_609, deq_vec[1][1].fu_code[3], UInt<1>(0h0)) node _T_3723 = mux(_T_610, deq_vec[2][1].fu_code[3], UInt<1>(0h0)) node _T_3724 = mux(_T_611, deq_vec[3][1].fu_code[3], UInt<1>(0h0)) node _T_3725 = mux(_T_612, deq_vec[4][1].fu_code[3], UInt<1>(0h0)) node _T_3726 = mux(_T_613, deq_vec[5][1].fu_code[3], UInt<1>(0h0)) node _T_3727 = mux(_T_614, deq_vec[6][1].fu_code[3], UInt<1>(0h0)) node _T_3728 = mux(_T_615, deq_vec[7][1].fu_code[3], UInt<1>(0h0)) node _T_3729 = or(_T_3721, _T_3722) node _T_3730 = or(_T_3729, _T_3723) node _T_3731 = or(_T_3730, _T_3724) node _T_3732 = or(_T_3731, _T_3725) node _T_3733 = or(_T_3732, _T_3726) node _T_3734 = or(_T_3733, _T_3727) node _T_3735 = or(_T_3734, _T_3728) wire _WIRE_215 : UInt<1> connect _WIRE_215, _T_3735 connect _WIRE_211[3], _WIRE_215 node _T_3736 = mux(_T_608, deq_vec[0][1].fu_code[4], UInt<1>(0h0)) node _T_3737 = mux(_T_609, deq_vec[1][1].fu_code[4], UInt<1>(0h0)) node _T_3738 = mux(_T_610, deq_vec[2][1].fu_code[4], UInt<1>(0h0)) node _T_3739 = mux(_T_611, deq_vec[3][1].fu_code[4], UInt<1>(0h0)) node _T_3740 = mux(_T_612, deq_vec[4][1].fu_code[4], UInt<1>(0h0)) node _T_3741 = mux(_T_613, deq_vec[5][1].fu_code[4], UInt<1>(0h0)) node _T_3742 = mux(_T_614, deq_vec[6][1].fu_code[4], UInt<1>(0h0)) node _T_3743 = mux(_T_615, deq_vec[7][1].fu_code[4], UInt<1>(0h0)) node _T_3744 = or(_T_3736, _T_3737) node _T_3745 = or(_T_3744, _T_3738) node _T_3746 = or(_T_3745, _T_3739) node _T_3747 = or(_T_3746, _T_3740) node _T_3748 = or(_T_3747, _T_3741) node _T_3749 = or(_T_3748, _T_3742) node _T_3750 = or(_T_3749, _T_3743) wire _WIRE_216 : UInt<1> connect _WIRE_216, _T_3750 connect _WIRE_211[4], _WIRE_216 node _T_3751 = mux(_T_608, deq_vec[0][1].fu_code[5], UInt<1>(0h0)) node _T_3752 = mux(_T_609, deq_vec[1][1].fu_code[5], UInt<1>(0h0)) node _T_3753 = mux(_T_610, deq_vec[2][1].fu_code[5], UInt<1>(0h0)) node _T_3754 = mux(_T_611, deq_vec[3][1].fu_code[5], UInt<1>(0h0)) node _T_3755 = mux(_T_612, deq_vec[4][1].fu_code[5], UInt<1>(0h0)) node _T_3756 = mux(_T_613, deq_vec[5][1].fu_code[5], UInt<1>(0h0)) node _T_3757 = mux(_T_614, deq_vec[6][1].fu_code[5], UInt<1>(0h0)) node _T_3758 = mux(_T_615, deq_vec[7][1].fu_code[5], UInt<1>(0h0)) node _T_3759 = or(_T_3751, _T_3752) node _T_3760 = or(_T_3759, _T_3753) node _T_3761 = or(_T_3760, _T_3754) node _T_3762 = or(_T_3761, _T_3755) node _T_3763 = or(_T_3762, _T_3756) node _T_3764 = or(_T_3763, _T_3757) node _T_3765 = or(_T_3764, _T_3758) wire _WIRE_217 : UInt<1> connect _WIRE_217, _T_3765 connect _WIRE_211[5], _WIRE_217 node _T_3766 = mux(_T_608, deq_vec[0][1].fu_code[6], UInt<1>(0h0)) node _T_3767 = mux(_T_609, deq_vec[1][1].fu_code[6], UInt<1>(0h0)) node _T_3768 = mux(_T_610, deq_vec[2][1].fu_code[6], UInt<1>(0h0)) node _T_3769 = mux(_T_611, deq_vec[3][1].fu_code[6], UInt<1>(0h0)) node _T_3770 = mux(_T_612, deq_vec[4][1].fu_code[6], UInt<1>(0h0)) node _T_3771 = mux(_T_613, deq_vec[5][1].fu_code[6], UInt<1>(0h0)) node _T_3772 = mux(_T_614, deq_vec[6][1].fu_code[6], UInt<1>(0h0)) node _T_3773 = mux(_T_615, deq_vec[7][1].fu_code[6], UInt<1>(0h0)) node _T_3774 = or(_T_3766, _T_3767) node _T_3775 = or(_T_3774, _T_3768) node _T_3776 = or(_T_3775, _T_3769) node _T_3777 = or(_T_3776, _T_3770) node _T_3778 = or(_T_3777, _T_3771) node _T_3779 = or(_T_3778, _T_3772) node _T_3780 = or(_T_3779, _T_3773) wire _WIRE_218 : UInt<1> connect _WIRE_218, _T_3780 connect _WIRE_211[6], _WIRE_218 node _T_3781 = mux(_T_608, deq_vec[0][1].fu_code[7], UInt<1>(0h0)) node _T_3782 = mux(_T_609, deq_vec[1][1].fu_code[7], UInt<1>(0h0)) node _T_3783 = mux(_T_610, deq_vec[2][1].fu_code[7], UInt<1>(0h0)) node _T_3784 = mux(_T_611, deq_vec[3][1].fu_code[7], UInt<1>(0h0)) node _T_3785 = mux(_T_612, deq_vec[4][1].fu_code[7], UInt<1>(0h0)) node _T_3786 = mux(_T_613, deq_vec[5][1].fu_code[7], UInt<1>(0h0)) node _T_3787 = mux(_T_614, deq_vec[6][1].fu_code[7], UInt<1>(0h0)) node _T_3788 = mux(_T_615, deq_vec[7][1].fu_code[7], UInt<1>(0h0)) node _T_3789 = or(_T_3781, _T_3782) node _T_3790 = or(_T_3789, _T_3783) node _T_3791 = or(_T_3790, _T_3784) node _T_3792 = or(_T_3791, _T_3785) node _T_3793 = or(_T_3792, _T_3786) node _T_3794 = or(_T_3793, _T_3787) node _T_3795 = or(_T_3794, _T_3788) wire _WIRE_219 : UInt<1> connect _WIRE_219, _T_3795 connect _WIRE_211[7], _WIRE_219 node _T_3796 = mux(_T_608, deq_vec[0][1].fu_code[8], UInt<1>(0h0)) node _T_3797 = mux(_T_609, deq_vec[1][1].fu_code[8], UInt<1>(0h0)) node _T_3798 = mux(_T_610, deq_vec[2][1].fu_code[8], UInt<1>(0h0)) node _T_3799 = mux(_T_611, deq_vec[3][1].fu_code[8], UInt<1>(0h0)) node _T_3800 = mux(_T_612, deq_vec[4][1].fu_code[8], UInt<1>(0h0)) node _T_3801 = mux(_T_613, deq_vec[5][1].fu_code[8], UInt<1>(0h0)) node _T_3802 = mux(_T_614, deq_vec[6][1].fu_code[8], UInt<1>(0h0)) node _T_3803 = mux(_T_615, deq_vec[7][1].fu_code[8], UInt<1>(0h0)) node _T_3804 = or(_T_3796, _T_3797) node _T_3805 = or(_T_3804, _T_3798) node _T_3806 = or(_T_3805, _T_3799) node _T_3807 = or(_T_3806, _T_3800) node _T_3808 = or(_T_3807, _T_3801) node _T_3809 = or(_T_3808, _T_3802) node _T_3810 = or(_T_3809, _T_3803) wire _WIRE_220 : UInt<1> connect _WIRE_220, _T_3810 connect _WIRE_211[8], _WIRE_220 node _T_3811 = mux(_T_608, deq_vec[0][1].fu_code[9], UInt<1>(0h0)) node _T_3812 = mux(_T_609, deq_vec[1][1].fu_code[9], UInt<1>(0h0)) node _T_3813 = mux(_T_610, deq_vec[2][1].fu_code[9], UInt<1>(0h0)) node _T_3814 = mux(_T_611, deq_vec[3][1].fu_code[9], UInt<1>(0h0)) node _T_3815 = mux(_T_612, deq_vec[4][1].fu_code[9], UInt<1>(0h0)) node _T_3816 = mux(_T_613, deq_vec[5][1].fu_code[9], UInt<1>(0h0)) node _T_3817 = mux(_T_614, deq_vec[6][1].fu_code[9], UInt<1>(0h0)) node _T_3818 = mux(_T_615, deq_vec[7][1].fu_code[9], UInt<1>(0h0)) node _T_3819 = or(_T_3811, _T_3812) node _T_3820 = or(_T_3819, _T_3813) node _T_3821 = or(_T_3820, _T_3814) node _T_3822 = or(_T_3821, _T_3815) node _T_3823 = or(_T_3822, _T_3816) node _T_3824 = or(_T_3823, _T_3817) node _T_3825 = or(_T_3824, _T_3818) wire _WIRE_221 : UInt<1> connect _WIRE_221, _T_3825 connect _WIRE_211[9], _WIRE_221 connect _WIRE_116.fu_code, _WIRE_211 wire _WIRE_222 : UInt<1>[4] node _T_3826 = mux(_T_608, deq_vec[0][1].iq_type[0], UInt<1>(0h0)) node _T_3827 = mux(_T_609, deq_vec[1][1].iq_type[0], UInt<1>(0h0)) node _T_3828 = mux(_T_610, deq_vec[2][1].iq_type[0], UInt<1>(0h0)) node _T_3829 = mux(_T_611, deq_vec[3][1].iq_type[0], UInt<1>(0h0)) node _T_3830 = mux(_T_612, deq_vec[4][1].iq_type[0], UInt<1>(0h0)) node _T_3831 = mux(_T_613, deq_vec[5][1].iq_type[0], UInt<1>(0h0)) node _T_3832 = mux(_T_614, deq_vec[6][1].iq_type[0], UInt<1>(0h0)) node _T_3833 = mux(_T_615, deq_vec[7][1].iq_type[0], UInt<1>(0h0)) node _T_3834 = or(_T_3826, _T_3827) node _T_3835 = or(_T_3834, _T_3828) node _T_3836 = or(_T_3835, _T_3829) node _T_3837 = or(_T_3836, _T_3830) node _T_3838 = or(_T_3837, _T_3831) node _T_3839 = or(_T_3838, _T_3832) node _T_3840 = or(_T_3839, _T_3833) wire _WIRE_223 : UInt<1> connect _WIRE_223, _T_3840 connect _WIRE_222[0], _WIRE_223 node _T_3841 = mux(_T_608, deq_vec[0][1].iq_type[1], UInt<1>(0h0)) node _T_3842 = mux(_T_609, deq_vec[1][1].iq_type[1], UInt<1>(0h0)) node _T_3843 = mux(_T_610, deq_vec[2][1].iq_type[1], UInt<1>(0h0)) node _T_3844 = mux(_T_611, deq_vec[3][1].iq_type[1], UInt<1>(0h0)) node _T_3845 = mux(_T_612, deq_vec[4][1].iq_type[1], UInt<1>(0h0)) node _T_3846 = mux(_T_613, deq_vec[5][1].iq_type[1], UInt<1>(0h0)) node _T_3847 = mux(_T_614, deq_vec[6][1].iq_type[1], UInt<1>(0h0)) node _T_3848 = mux(_T_615, deq_vec[7][1].iq_type[1], UInt<1>(0h0)) node _T_3849 = or(_T_3841, _T_3842) node _T_3850 = or(_T_3849, _T_3843) node _T_3851 = or(_T_3850, _T_3844) node _T_3852 = or(_T_3851, _T_3845) node _T_3853 = or(_T_3852, _T_3846) node _T_3854 = or(_T_3853, _T_3847) node _T_3855 = or(_T_3854, _T_3848) wire _WIRE_224 : UInt<1> connect _WIRE_224, _T_3855 connect _WIRE_222[1], _WIRE_224 node _T_3856 = mux(_T_608, deq_vec[0][1].iq_type[2], UInt<1>(0h0)) node _T_3857 = mux(_T_609, deq_vec[1][1].iq_type[2], UInt<1>(0h0)) node _T_3858 = mux(_T_610, deq_vec[2][1].iq_type[2], UInt<1>(0h0)) node _T_3859 = mux(_T_611, deq_vec[3][1].iq_type[2], UInt<1>(0h0)) node _T_3860 = mux(_T_612, deq_vec[4][1].iq_type[2], UInt<1>(0h0)) node _T_3861 = mux(_T_613, deq_vec[5][1].iq_type[2], UInt<1>(0h0)) node _T_3862 = mux(_T_614, deq_vec[6][1].iq_type[2], UInt<1>(0h0)) node _T_3863 = mux(_T_615, deq_vec[7][1].iq_type[2], UInt<1>(0h0)) node _T_3864 = or(_T_3856, _T_3857) node _T_3865 = or(_T_3864, _T_3858) node _T_3866 = or(_T_3865, _T_3859) node _T_3867 = or(_T_3866, _T_3860) node _T_3868 = or(_T_3867, _T_3861) node _T_3869 = or(_T_3868, _T_3862) node _T_3870 = or(_T_3869, _T_3863) wire _WIRE_225 : UInt<1> connect _WIRE_225, _T_3870 connect _WIRE_222[2], _WIRE_225 node _T_3871 = mux(_T_608, deq_vec[0][1].iq_type[3], UInt<1>(0h0)) node _T_3872 = mux(_T_609, deq_vec[1][1].iq_type[3], UInt<1>(0h0)) node _T_3873 = mux(_T_610, deq_vec[2][1].iq_type[3], UInt<1>(0h0)) node _T_3874 = mux(_T_611, deq_vec[3][1].iq_type[3], UInt<1>(0h0)) node _T_3875 = mux(_T_612, deq_vec[4][1].iq_type[3], UInt<1>(0h0)) node _T_3876 = mux(_T_613, deq_vec[5][1].iq_type[3], UInt<1>(0h0)) node _T_3877 = mux(_T_614, deq_vec[6][1].iq_type[3], UInt<1>(0h0)) node _T_3878 = mux(_T_615, deq_vec[7][1].iq_type[3], UInt<1>(0h0)) node _T_3879 = or(_T_3871, _T_3872) node _T_3880 = or(_T_3879, _T_3873) node _T_3881 = or(_T_3880, _T_3874) node _T_3882 = or(_T_3881, _T_3875) node _T_3883 = or(_T_3882, _T_3876) node _T_3884 = or(_T_3883, _T_3877) node _T_3885 = or(_T_3884, _T_3878) wire _WIRE_226 : UInt<1> connect _WIRE_226, _T_3885 connect _WIRE_222[3], _WIRE_226 connect _WIRE_116.iq_type, _WIRE_222 node _T_3886 = mux(_T_608, deq_vec[0][1].debug_pc, UInt<1>(0h0)) node _T_3887 = mux(_T_609, deq_vec[1][1].debug_pc, UInt<1>(0h0)) node _T_3888 = mux(_T_610, deq_vec[2][1].debug_pc, UInt<1>(0h0)) node _T_3889 = mux(_T_611, deq_vec[3][1].debug_pc, UInt<1>(0h0)) node _T_3890 = mux(_T_612, deq_vec[4][1].debug_pc, UInt<1>(0h0)) node _T_3891 = mux(_T_613, deq_vec[5][1].debug_pc, UInt<1>(0h0)) node _T_3892 = mux(_T_614, deq_vec[6][1].debug_pc, UInt<1>(0h0)) node _T_3893 = mux(_T_615, deq_vec[7][1].debug_pc, UInt<1>(0h0)) node _T_3894 = or(_T_3886, _T_3887) node _T_3895 = or(_T_3894, _T_3888) node _T_3896 = or(_T_3895, _T_3889) node _T_3897 = or(_T_3896, _T_3890) node _T_3898 = or(_T_3897, _T_3891) node _T_3899 = or(_T_3898, _T_3892) node _T_3900 = or(_T_3899, _T_3893) wire _WIRE_227 : UInt<40> connect _WIRE_227, _T_3900 connect _WIRE_116.debug_pc, _WIRE_227 node _T_3901 = mux(_T_608, deq_vec[0][1].is_rvc, UInt<1>(0h0)) node _T_3902 = mux(_T_609, deq_vec[1][1].is_rvc, UInt<1>(0h0)) node _T_3903 = mux(_T_610, deq_vec[2][1].is_rvc, UInt<1>(0h0)) node _T_3904 = mux(_T_611, deq_vec[3][1].is_rvc, UInt<1>(0h0)) node _T_3905 = mux(_T_612, deq_vec[4][1].is_rvc, UInt<1>(0h0)) node _T_3906 = mux(_T_613, deq_vec[5][1].is_rvc, UInt<1>(0h0)) node _T_3907 = mux(_T_614, deq_vec[6][1].is_rvc, UInt<1>(0h0)) node _T_3908 = mux(_T_615, deq_vec[7][1].is_rvc, UInt<1>(0h0)) node _T_3909 = or(_T_3901, _T_3902) node _T_3910 = or(_T_3909, _T_3903) node _T_3911 = or(_T_3910, _T_3904) node _T_3912 = or(_T_3911, _T_3905) node _T_3913 = or(_T_3912, _T_3906) node _T_3914 = or(_T_3913, _T_3907) node _T_3915 = or(_T_3914, _T_3908) wire _WIRE_228 : UInt<1> connect _WIRE_228, _T_3915 connect _WIRE_116.is_rvc, _WIRE_228 node _T_3916 = mux(_T_608, deq_vec[0][1].debug_inst, UInt<1>(0h0)) node _T_3917 = mux(_T_609, deq_vec[1][1].debug_inst, UInt<1>(0h0)) node _T_3918 = mux(_T_610, deq_vec[2][1].debug_inst, UInt<1>(0h0)) node _T_3919 = mux(_T_611, deq_vec[3][1].debug_inst, UInt<1>(0h0)) node _T_3920 = mux(_T_612, deq_vec[4][1].debug_inst, UInt<1>(0h0)) node _T_3921 = mux(_T_613, deq_vec[5][1].debug_inst, UInt<1>(0h0)) node _T_3922 = mux(_T_614, deq_vec[6][1].debug_inst, UInt<1>(0h0)) node _T_3923 = mux(_T_615, deq_vec[7][1].debug_inst, UInt<1>(0h0)) node _T_3924 = or(_T_3916, _T_3917) node _T_3925 = or(_T_3924, _T_3918) node _T_3926 = or(_T_3925, _T_3919) node _T_3927 = or(_T_3926, _T_3920) node _T_3928 = or(_T_3927, _T_3921) node _T_3929 = or(_T_3928, _T_3922) node _T_3930 = or(_T_3929, _T_3923) wire _WIRE_229 : UInt<32> connect _WIRE_229, _T_3930 connect _WIRE_116.debug_inst, _WIRE_229 node _T_3931 = mux(_T_608, deq_vec[0][1].inst, UInt<1>(0h0)) node _T_3932 = mux(_T_609, deq_vec[1][1].inst, UInt<1>(0h0)) node _T_3933 = mux(_T_610, deq_vec[2][1].inst, UInt<1>(0h0)) node _T_3934 = mux(_T_611, deq_vec[3][1].inst, UInt<1>(0h0)) node _T_3935 = mux(_T_612, deq_vec[4][1].inst, UInt<1>(0h0)) node _T_3936 = mux(_T_613, deq_vec[5][1].inst, UInt<1>(0h0)) node _T_3937 = mux(_T_614, deq_vec[6][1].inst, UInt<1>(0h0)) node _T_3938 = mux(_T_615, deq_vec[7][1].inst, UInt<1>(0h0)) node _T_3939 = or(_T_3931, _T_3932) node _T_3940 = or(_T_3939, _T_3933) node _T_3941 = or(_T_3940, _T_3934) node _T_3942 = or(_T_3941, _T_3935) node _T_3943 = or(_T_3942, _T_3936) node _T_3944 = or(_T_3943, _T_3937) node _T_3945 = or(_T_3944, _T_3938) wire _WIRE_230 : UInt<32> connect _WIRE_230, _T_3945 connect _WIRE_116.inst, _WIRE_230 connect _WIRE[1], _WIRE_116 wire _WIRE_231 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_3946 = mux(_T_608, deq_vec[0][2].debug_tsrc, UInt<1>(0h0)) node _T_3947 = mux(_T_609, deq_vec[1][2].debug_tsrc, UInt<1>(0h0)) node _T_3948 = mux(_T_610, deq_vec[2][2].debug_tsrc, UInt<1>(0h0)) node _T_3949 = mux(_T_611, deq_vec[3][2].debug_tsrc, UInt<1>(0h0)) node _T_3950 = mux(_T_612, deq_vec[4][2].debug_tsrc, UInt<1>(0h0)) node _T_3951 = mux(_T_613, deq_vec[5][2].debug_tsrc, UInt<1>(0h0)) node _T_3952 = mux(_T_614, deq_vec[6][2].debug_tsrc, UInt<1>(0h0)) node _T_3953 = mux(_T_615, deq_vec[7][2].debug_tsrc, UInt<1>(0h0)) node _T_3954 = or(_T_3946, _T_3947) node _T_3955 = or(_T_3954, _T_3948) node _T_3956 = or(_T_3955, _T_3949) node _T_3957 = or(_T_3956, _T_3950) node _T_3958 = or(_T_3957, _T_3951) node _T_3959 = or(_T_3958, _T_3952) node _T_3960 = or(_T_3959, _T_3953) wire _WIRE_232 : UInt<3> connect _WIRE_232, _T_3960 connect _WIRE_231.debug_tsrc, _WIRE_232 node _T_3961 = mux(_T_608, deq_vec[0][2].debug_fsrc, UInt<1>(0h0)) node _T_3962 = mux(_T_609, deq_vec[1][2].debug_fsrc, UInt<1>(0h0)) node _T_3963 = mux(_T_610, deq_vec[2][2].debug_fsrc, UInt<1>(0h0)) node _T_3964 = mux(_T_611, deq_vec[3][2].debug_fsrc, UInt<1>(0h0)) node _T_3965 = mux(_T_612, deq_vec[4][2].debug_fsrc, UInt<1>(0h0)) node _T_3966 = mux(_T_613, deq_vec[5][2].debug_fsrc, UInt<1>(0h0)) node _T_3967 = mux(_T_614, deq_vec[6][2].debug_fsrc, UInt<1>(0h0)) node _T_3968 = mux(_T_615, deq_vec[7][2].debug_fsrc, UInt<1>(0h0)) node _T_3969 = or(_T_3961, _T_3962) node _T_3970 = or(_T_3969, _T_3963) node _T_3971 = or(_T_3970, _T_3964) node _T_3972 = or(_T_3971, _T_3965) node _T_3973 = or(_T_3972, _T_3966) node _T_3974 = or(_T_3973, _T_3967) node _T_3975 = or(_T_3974, _T_3968) wire _WIRE_233 : UInt<3> connect _WIRE_233, _T_3975 connect _WIRE_231.debug_fsrc, _WIRE_233 node _T_3976 = mux(_T_608, deq_vec[0][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3977 = mux(_T_609, deq_vec[1][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3978 = mux(_T_610, deq_vec[2][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3979 = mux(_T_611, deq_vec[3][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3980 = mux(_T_612, deq_vec[4][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3981 = mux(_T_613, deq_vec[5][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3982 = mux(_T_614, deq_vec[6][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3983 = mux(_T_615, deq_vec[7][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3984 = or(_T_3976, _T_3977) node _T_3985 = or(_T_3984, _T_3978) node _T_3986 = or(_T_3985, _T_3979) node _T_3987 = or(_T_3986, _T_3980) node _T_3988 = or(_T_3987, _T_3981) node _T_3989 = or(_T_3988, _T_3982) node _T_3990 = or(_T_3989, _T_3983) wire _WIRE_234 : UInt<1> connect _WIRE_234, _T_3990 connect _WIRE_231.bp_xcpt_if, _WIRE_234 node _T_3991 = mux(_T_608, deq_vec[0][2].bp_debug_if, UInt<1>(0h0)) node _T_3992 = mux(_T_609, deq_vec[1][2].bp_debug_if, UInt<1>(0h0)) node _T_3993 = mux(_T_610, deq_vec[2][2].bp_debug_if, UInt<1>(0h0)) node _T_3994 = mux(_T_611, deq_vec[3][2].bp_debug_if, UInt<1>(0h0)) node _T_3995 = mux(_T_612, deq_vec[4][2].bp_debug_if, UInt<1>(0h0)) node _T_3996 = mux(_T_613, deq_vec[5][2].bp_debug_if, UInt<1>(0h0)) node _T_3997 = mux(_T_614, deq_vec[6][2].bp_debug_if, UInt<1>(0h0)) node _T_3998 = mux(_T_615, deq_vec[7][2].bp_debug_if, UInt<1>(0h0)) node _T_3999 = or(_T_3991, _T_3992) node _T_4000 = or(_T_3999, _T_3993) node _T_4001 = or(_T_4000, _T_3994) node _T_4002 = or(_T_4001, _T_3995) node _T_4003 = or(_T_4002, _T_3996) node _T_4004 = or(_T_4003, _T_3997) node _T_4005 = or(_T_4004, _T_3998) wire _WIRE_235 : UInt<1> connect _WIRE_235, _T_4005 connect _WIRE_231.bp_debug_if, _WIRE_235 node _T_4006 = mux(_T_608, deq_vec[0][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4007 = mux(_T_609, deq_vec[1][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4008 = mux(_T_610, deq_vec[2][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4009 = mux(_T_611, deq_vec[3][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4010 = mux(_T_612, deq_vec[4][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4011 = mux(_T_613, deq_vec[5][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4012 = mux(_T_614, deq_vec[6][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4013 = mux(_T_615, deq_vec[7][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4014 = or(_T_4006, _T_4007) node _T_4015 = or(_T_4014, _T_4008) node _T_4016 = or(_T_4015, _T_4009) node _T_4017 = or(_T_4016, _T_4010) node _T_4018 = or(_T_4017, _T_4011) node _T_4019 = or(_T_4018, _T_4012) node _T_4020 = or(_T_4019, _T_4013) wire _WIRE_236 : UInt<1> connect _WIRE_236, _T_4020 connect _WIRE_231.xcpt_ma_if, _WIRE_236 node _T_4021 = mux(_T_608, deq_vec[0][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4022 = mux(_T_609, deq_vec[1][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4023 = mux(_T_610, deq_vec[2][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4024 = mux(_T_611, deq_vec[3][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4025 = mux(_T_612, deq_vec[4][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4026 = mux(_T_613, deq_vec[5][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4027 = mux(_T_614, deq_vec[6][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4028 = mux(_T_615, deq_vec[7][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4029 = or(_T_4021, _T_4022) node _T_4030 = or(_T_4029, _T_4023) node _T_4031 = or(_T_4030, _T_4024) node _T_4032 = or(_T_4031, _T_4025) node _T_4033 = or(_T_4032, _T_4026) node _T_4034 = or(_T_4033, _T_4027) node _T_4035 = or(_T_4034, _T_4028) wire _WIRE_237 : UInt<1> connect _WIRE_237, _T_4035 connect _WIRE_231.xcpt_ae_if, _WIRE_237 node _T_4036 = mux(_T_608, deq_vec[0][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4037 = mux(_T_609, deq_vec[1][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4038 = mux(_T_610, deq_vec[2][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4039 = mux(_T_611, deq_vec[3][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4040 = mux(_T_612, deq_vec[4][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4041 = mux(_T_613, deq_vec[5][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4042 = mux(_T_614, deq_vec[6][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4043 = mux(_T_615, deq_vec[7][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4044 = or(_T_4036, _T_4037) node _T_4045 = or(_T_4044, _T_4038) node _T_4046 = or(_T_4045, _T_4039) node _T_4047 = or(_T_4046, _T_4040) node _T_4048 = or(_T_4047, _T_4041) node _T_4049 = or(_T_4048, _T_4042) node _T_4050 = or(_T_4049, _T_4043) wire _WIRE_238 : UInt<1> connect _WIRE_238, _T_4050 connect _WIRE_231.xcpt_pf_if, _WIRE_238 node _T_4051 = mux(_T_608, deq_vec[0][2].fp_typ, UInt<1>(0h0)) node _T_4052 = mux(_T_609, deq_vec[1][2].fp_typ, UInt<1>(0h0)) node _T_4053 = mux(_T_610, deq_vec[2][2].fp_typ, UInt<1>(0h0)) node _T_4054 = mux(_T_611, deq_vec[3][2].fp_typ, UInt<1>(0h0)) node _T_4055 = mux(_T_612, deq_vec[4][2].fp_typ, UInt<1>(0h0)) node _T_4056 = mux(_T_613, deq_vec[5][2].fp_typ, UInt<1>(0h0)) node _T_4057 = mux(_T_614, deq_vec[6][2].fp_typ, UInt<1>(0h0)) node _T_4058 = mux(_T_615, deq_vec[7][2].fp_typ, UInt<1>(0h0)) node _T_4059 = or(_T_4051, _T_4052) node _T_4060 = or(_T_4059, _T_4053) node _T_4061 = or(_T_4060, _T_4054) node _T_4062 = or(_T_4061, _T_4055) node _T_4063 = or(_T_4062, _T_4056) node _T_4064 = or(_T_4063, _T_4057) node _T_4065 = or(_T_4064, _T_4058) wire _WIRE_239 : UInt<2> connect _WIRE_239, _T_4065 connect _WIRE_231.fp_typ, _WIRE_239 node _T_4066 = mux(_T_608, deq_vec[0][2].fp_rm, UInt<1>(0h0)) node _T_4067 = mux(_T_609, deq_vec[1][2].fp_rm, UInt<1>(0h0)) node _T_4068 = mux(_T_610, deq_vec[2][2].fp_rm, UInt<1>(0h0)) node _T_4069 = mux(_T_611, deq_vec[3][2].fp_rm, UInt<1>(0h0)) node _T_4070 = mux(_T_612, deq_vec[4][2].fp_rm, UInt<1>(0h0)) node _T_4071 = mux(_T_613, deq_vec[5][2].fp_rm, UInt<1>(0h0)) node _T_4072 = mux(_T_614, deq_vec[6][2].fp_rm, UInt<1>(0h0)) node _T_4073 = mux(_T_615, deq_vec[7][2].fp_rm, UInt<1>(0h0)) node _T_4074 = or(_T_4066, _T_4067) node _T_4075 = or(_T_4074, _T_4068) node _T_4076 = or(_T_4075, _T_4069) node _T_4077 = or(_T_4076, _T_4070) node _T_4078 = or(_T_4077, _T_4071) node _T_4079 = or(_T_4078, _T_4072) node _T_4080 = or(_T_4079, _T_4073) wire _WIRE_240 : UInt<3> connect _WIRE_240, _T_4080 connect _WIRE_231.fp_rm, _WIRE_240 node _T_4081 = mux(_T_608, deq_vec[0][2].fp_val, UInt<1>(0h0)) node _T_4082 = mux(_T_609, deq_vec[1][2].fp_val, UInt<1>(0h0)) node _T_4083 = mux(_T_610, deq_vec[2][2].fp_val, UInt<1>(0h0)) node _T_4084 = mux(_T_611, deq_vec[3][2].fp_val, UInt<1>(0h0)) node _T_4085 = mux(_T_612, deq_vec[4][2].fp_val, UInt<1>(0h0)) node _T_4086 = mux(_T_613, deq_vec[5][2].fp_val, UInt<1>(0h0)) node _T_4087 = mux(_T_614, deq_vec[6][2].fp_val, UInt<1>(0h0)) node _T_4088 = mux(_T_615, deq_vec[7][2].fp_val, UInt<1>(0h0)) node _T_4089 = or(_T_4081, _T_4082) node _T_4090 = or(_T_4089, _T_4083) node _T_4091 = or(_T_4090, _T_4084) node _T_4092 = or(_T_4091, _T_4085) node _T_4093 = or(_T_4092, _T_4086) node _T_4094 = or(_T_4093, _T_4087) node _T_4095 = or(_T_4094, _T_4088) wire _WIRE_241 : UInt<1> connect _WIRE_241, _T_4095 connect _WIRE_231.fp_val, _WIRE_241 node _T_4096 = mux(_T_608, deq_vec[0][2].fcn_op, UInt<1>(0h0)) node _T_4097 = mux(_T_609, deq_vec[1][2].fcn_op, UInt<1>(0h0)) node _T_4098 = mux(_T_610, deq_vec[2][2].fcn_op, UInt<1>(0h0)) node _T_4099 = mux(_T_611, deq_vec[3][2].fcn_op, UInt<1>(0h0)) node _T_4100 = mux(_T_612, deq_vec[4][2].fcn_op, UInt<1>(0h0)) node _T_4101 = mux(_T_613, deq_vec[5][2].fcn_op, UInt<1>(0h0)) node _T_4102 = mux(_T_614, deq_vec[6][2].fcn_op, UInt<1>(0h0)) node _T_4103 = mux(_T_615, deq_vec[7][2].fcn_op, UInt<1>(0h0)) node _T_4104 = or(_T_4096, _T_4097) node _T_4105 = or(_T_4104, _T_4098) node _T_4106 = or(_T_4105, _T_4099) node _T_4107 = or(_T_4106, _T_4100) node _T_4108 = or(_T_4107, _T_4101) node _T_4109 = or(_T_4108, _T_4102) node _T_4110 = or(_T_4109, _T_4103) wire _WIRE_242 : UInt<5> connect _WIRE_242, _T_4110 connect _WIRE_231.fcn_op, _WIRE_242 node _T_4111 = mux(_T_608, deq_vec[0][2].fcn_dw, UInt<1>(0h0)) node _T_4112 = mux(_T_609, deq_vec[1][2].fcn_dw, UInt<1>(0h0)) node _T_4113 = mux(_T_610, deq_vec[2][2].fcn_dw, UInt<1>(0h0)) node _T_4114 = mux(_T_611, deq_vec[3][2].fcn_dw, UInt<1>(0h0)) node _T_4115 = mux(_T_612, deq_vec[4][2].fcn_dw, UInt<1>(0h0)) node _T_4116 = mux(_T_613, deq_vec[5][2].fcn_dw, UInt<1>(0h0)) node _T_4117 = mux(_T_614, deq_vec[6][2].fcn_dw, UInt<1>(0h0)) node _T_4118 = mux(_T_615, deq_vec[7][2].fcn_dw, UInt<1>(0h0)) node _T_4119 = or(_T_4111, _T_4112) node _T_4120 = or(_T_4119, _T_4113) node _T_4121 = or(_T_4120, _T_4114) node _T_4122 = or(_T_4121, _T_4115) node _T_4123 = or(_T_4122, _T_4116) node _T_4124 = or(_T_4123, _T_4117) node _T_4125 = or(_T_4124, _T_4118) wire _WIRE_243 : UInt<1> connect _WIRE_243, _T_4125 connect _WIRE_231.fcn_dw, _WIRE_243 node _T_4126 = mux(_T_608, deq_vec[0][2].frs3_en, UInt<1>(0h0)) node _T_4127 = mux(_T_609, deq_vec[1][2].frs3_en, UInt<1>(0h0)) node _T_4128 = mux(_T_610, deq_vec[2][2].frs3_en, UInt<1>(0h0)) node _T_4129 = mux(_T_611, deq_vec[3][2].frs3_en, UInt<1>(0h0)) node _T_4130 = mux(_T_612, deq_vec[4][2].frs3_en, UInt<1>(0h0)) node _T_4131 = mux(_T_613, deq_vec[5][2].frs3_en, UInt<1>(0h0)) node _T_4132 = mux(_T_614, deq_vec[6][2].frs3_en, UInt<1>(0h0)) node _T_4133 = mux(_T_615, deq_vec[7][2].frs3_en, UInt<1>(0h0)) node _T_4134 = or(_T_4126, _T_4127) node _T_4135 = or(_T_4134, _T_4128) node _T_4136 = or(_T_4135, _T_4129) node _T_4137 = or(_T_4136, _T_4130) node _T_4138 = or(_T_4137, _T_4131) node _T_4139 = or(_T_4138, _T_4132) node _T_4140 = or(_T_4139, _T_4133) wire _WIRE_244 : UInt<1> connect _WIRE_244, _T_4140 connect _WIRE_231.frs3_en, _WIRE_244 node _T_4141 = mux(_T_608, deq_vec[0][2].lrs2_rtype, UInt<1>(0h0)) node _T_4142 = mux(_T_609, deq_vec[1][2].lrs2_rtype, UInt<1>(0h0)) node _T_4143 = mux(_T_610, deq_vec[2][2].lrs2_rtype, UInt<1>(0h0)) node _T_4144 = mux(_T_611, deq_vec[3][2].lrs2_rtype, UInt<1>(0h0)) node _T_4145 = mux(_T_612, deq_vec[4][2].lrs2_rtype, UInt<1>(0h0)) node _T_4146 = mux(_T_613, deq_vec[5][2].lrs2_rtype, UInt<1>(0h0)) node _T_4147 = mux(_T_614, deq_vec[6][2].lrs2_rtype, UInt<1>(0h0)) node _T_4148 = mux(_T_615, deq_vec[7][2].lrs2_rtype, UInt<1>(0h0)) node _T_4149 = or(_T_4141, _T_4142) node _T_4150 = or(_T_4149, _T_4143) node _T_4151 = or(_T_4150, _T_4144) node _T_4152 = or(_T_4151, _T_4145) node _T_4153 = or(_T_4152, _T_4146) node _T_4154 = or(_T_4153, _T_4147) node _T_4155 = or(_T_4154, _T_4148) wire _WIRE_245 : UInt<2> connect _WIRE_245, _T_4155 connect _WIRE_231.lrs2_rtype, _WIRE_245 node _T_4156 = mux(_T_608, deq_vec[0][2].lrs1_rtype, UInt<1>(0h0)) node _T_4157 = mux(_T_609, deq_vec[1][2].lrs1_rtype, UInt<1>(0h0)) node _T_4158 = mux(_T_610, deq_vec[2][2].lrs1_rtype, UInt<1>(0h0)) node _T_4159 = mux(_T_611, deq_vec[3][2].lrs1_rtype, UInt<1>(0h0)) node _T_4160 = mux(_T_612, deq_vec[4][2].lrs1_rtype, UInt<1>(0h0)) node _T_4161 = mux(_T_613, deq_vec[5][2].lrs1_rtype, UInt<1>(0h0)) node _T_4162 = mux(_T_614, deq_vec[6][2].lrs1_rtype, UInt<1>(0h0)) node _T_4163 = mux(_T_615, deq_vec[7][2].lrs1_rtype, UInt<1>(0h0)) node _T_4164 = or(_T_4156, _T_4157) node _T_4165 = or(_T_4164, _T_4158) node _T_4166 = or(_T_4165, _T_4159) node _T_4167 = or(_T_4166, _T_4160) node _T_4168 = or(_T_4167, _T_4161) node _T_4169 = or(_T_4168, _T_4162) node _T_4170 = or(_T_4169, _T_4163) wire _WIRE_246 : UInt<2> connect _WIRE_246, _T_4170 connect _WIRE_231.lrs1_rtype, _WIRE_246 node _T_4171 = mux(_T_608, deq_vec[0][2].dst_rtype, UInt<1>(0h0)) node _T_4172 = mux(_T_609, deq_vec[1][2].dst_rtype, UInt<1>(0h0)) node _T_4173 = mux(_T_610, deq_vec[2][2].dst_rtype, UInt<1>(0h0)) node _T_4174 = mux(_T_611, deq_vec[3][2].dst_rtype, UInt<1>(0h0)) node _T_4175 = mux(_T_612, deq_vec[4][2].dst_rtype, UInt<1>(0h0)) node _T_4176 = mux(_T_613, deq_vec[5][2].dst_rtype, UInt<1>(0h0)) node _T_4177 = mux(_T_614, deq_vec[6][2].dst_rtype, UInt<1>(0h0)) node _T_4178 = mux(_T_615, deq_vec[7][2].dst_rtype, UInt<1>(0h0)) node _T_4179 = or(_T_4171, _T_4172) node _T_4180 = or(_T_4179, _T_4173) node _T_4181 = or(_T_4180, _T_4174) node _T_4182 = or(_T_4181, _T_4175) node _T_4183 = or(_T_4182, _T_4176) node _T_4184 = or(_T_4183, _T_4177) node _T_4185 = or(_T_4184, _T_4178) wire _WIRE_247 : UInt<2> connect _WIRE_247, _T_4185 connect _WIRE_231.dst_rtype, _WIRE_247 node _T_4186 = mux(_T_608, deq_vec[0][2].lrs3, UInt<1>(0h0)) node _T_4187 = mux(_T_609, deq_vec[1][2].lrs3, UInt<1>(0h0)) node _T_4188 = mux(_T_610, deq_vec[2][2].lrs3, UInt<1>(0h0)) node _T_4189 = mux(_T_611, deq_vec[3][2].lrs3, UInt<1>(0h0)) node _T_4190 = mux(_T_612, deq_vec[4][2].lrs3, UInt<1>(0h0)) node _T_4191 = mux(_T_613, deq_vec[5][2].lrs3, UInt<1>(0h0)) node _T_4192 = mux(_T_614, deq_vec[6][2].lrs3, UInt<1>(0h0)) node _T_4193 = mux(_T_615, deq_vec[7][2].lrs3, UInt<1>(0h0)) node _T_4194 = or(_T_4186, _T_4187) node _T_4195 = or(_T_4194, _T_4188) node _T_4196 = or(_T_4195, _T_4189) node _T_4197 = or(_T_4196, _T_4190) node _T_4198 = or(_T_4197, _T_4191) node _T_4199 = or(_T_4198, _T_4192) node _T_4200 = or(_T_4199, _T_4193) wire _WIRE_248 : UInt<6> connect _WIRE_248, _T_4200 connect _WIRE_231.lrs3, _WIRE_248 node _T_4201 = mux(_T_608, deq_vec[0][2].lrs2, UInt<1>(0h0)) node _T_4202 = mux(_T_609, deq_vec[1][2].lrs2, UInt<1>(0h0)) node _T_4203 = mux(_T_610, deq_vec[2][2].lrs2, UInt<1>(0h0)) node _T_4204 = mux(_T_611, deq_vec[3][2].lrs2, UInt<1>(0h0)) node _T_4205 = mux(_T_612, deq_vec[4][2].lrs2, UInt<1>(0h0)) node _T_4206 = mux(_T_613, deq_vec[5][2].lrs2, UInt<1>(0h0)) node _T_4207 = mux(_T_614, deq_vec[6][2].lrs2, UInt<1>(0h0)) node _T_4208 = mux(_T_615, deq_vec[7][2].lrs2, UInt<1>(0h0)) node _T_4209 = or(_T_4201, _T_4202) node _T_4210 = or(_T_4209, _T_4203) node _T_4211 = or(_T_4210, _T_4204) node _T_4212 = or(_T_4211, _T_4205) node _T_4213 = or(_T_4212, _T_4206) node _T_4214 = or(_T_4213, _T_4207) node _T_4215 = or(_T_4214, _T_4208) wire _WIRE_249 : UInt<6> connect _WIRE_249, _T_4215 connect _WIRE_231.lrs2, _WIRE_249 node _T_4216 = mux(_T_608, deq_vec[0][2].lrs1, UInt<1>(0h0)) node _T_4217 = mux(_T_609, deq_vec[1][2].lrs1, UInt<1>(0h0)) node _T_4218 = mux(_T_610, deq_vec[2][2].lrs1, UInt<1>(0h0)) node _T_4219 = mux(_T_611, deq_vec[3][2].lrs1, UInt<1>(0h0)) node _T_4220 = mux(_T_612, deq_vec[4][2].lrs1, UInt<1>(0h0)) node _T_4221 = mux(_T_613, deq_vec[5][2].lrs1, UInt<1>(0h0)) node _T_4222 = mux(_T_614, deq_vec[6][2].lrs1, UInt<1>(0h0)) node _T_4223 = mux(_T_615, deq_vec[7][2].lrs1, UInt<1>(0h0)) node _T_4224 = or(_T_4216, _T_4217) node _T_4225 = or(_T_4224, _T_4218) node _T_4226 = or(_T_4225, _T_4219) node _T_4227 = or(_T_4226, _T_4220) node _T_4228 = or(_T_4227, _T_4221) node _T_4229 = or(_T_4228, _T_4222) node _T_4230 = or(_T_4229, _T_4223) wire _WIRE_250 : UInt<6> connect _WIRE_250, _T_4230 connect _WIRE_231.lrs1, _WIRE_250 node _T_4231 = mux(_T_608, deq_vec[0][2].ldst, UInt<1>(0h0)) node _T_4232 = mux(_T_609, deq_vec[1][2].ldst, UInt<1>(0h0)) node _T_4233 = mux(_T_610, deq_vec[2][2].ldst, UInt<1>(0h0)) node _T_4234 = mux(_T_611, deq_vec[3][2].ldst, UInt<1>(0h0)) node _T_4235 = mux(_T_612, deq_vec[4][2].ldst, UInt<1>(0h0)) node _T_4236 = mux(_T_613, deq_vec[5][2].ldst, UInt<1>(0h0)) node _T_4237 = mux(_T_614, deq_vec[6][2].ldst, UInt<1>(0h0)) node _T_4238 = mux(_T_615, deq_vec[7][2].ldst, UInt<1>(0h0)) node _T_4239 = or(_T_4231, _T_4232) node _T_4240 = or(_T_4239, _T_4233) node _T_4241 = or(_T_4240, _T_4234) node _T_4242 = or(_T_4241, _T_4235) node _T_4243 = or(_T_4242, _T_4236) node _T_4244 = or(_T_4243, _T_4237) node _T_4245 = or(_T_4244, _T_4238) wire _WIRE_251 : UInt<6> connect _WIRE_251, _T_4245 connect _WIRE_231.ldst, _WIRE_251 node _T_4246 = mux(_T_608, deq_vec[0][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4247 = mux(_T_609, deq_vec[1][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4248 = mux(_T_610, deq_vec[2][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4249 = mux(_T_611, deq_vec[3][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4250 = mux(_T_612, deq_vec[4][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4251 = mux(_T_613, deq_vec[5][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4252 = mux(_T_614, deq_vec[6][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4253 = mux(_T_615, deq_vec[7][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4254 = or(_T_4246, _T_4247) node _T_4255 = or(_T_4254, _T_4248) node _T_4256 = or(_T_4255, _T_4249) node _T_4257 = or(_T_4256, _T_4250) node _T_4258 = or(_T_4257, _T_4251) node _T_4259 = or(_T_4258, _T_4252) node _T_4260 = or(_T_4259, _T_4253) wire _WIRE_252 : UInt<1> connect _WIRE_252, _T_4260 connect _WIRE_231.ldst_is_rs1, _WIRE_252 node _T_4261 = mux(_T_608, deq_vec[0][2].csr_cmd, UInt<1>(0h0)) node _T_4262 = mux(_T_609, deq_vec[1][2].csr_cmd, UInt<1>(0h0)) node _T_4263 = mux(_T_610, deq_vec[2][2].csr_cmd, UInt<1>(0h0)) node _T_4264 = mux(_T_611, deq_vec[3][2].csr_cmd, UInt<1>(0h0)) node _T_4265 = mux(_T_612, deq_vec[4][2].csr_cmd, UInt<1>(0h0)) node _T_4266 = mux(_T_613, deq_vec[5][2].csr_cmd, UInt<1>(0h0)) node _T_4267 = mux(_T_614, deq_vec[6][2].csr_cmd, UInt<1>(0h0)) node _T_4268 = mux(_T_615, deq_vec[7][2].csr_cmd, UInt<1>(0h0)) node _T_4269 = or(_T_4261, _T_4262) node _T_4270 = or(_T_4269, _T_4263) node _T_4271 = or(_T_4270, _T_4264) node _T_4272 = or(_T_4271, _T_4265) node _T_4273 = or(_T_4272, _T_4266) node _T_4274 = or(_T_4273, _T_4267) node _T_4275 = or(_T_4274, _T_4268) wire _WIRE_253 : UInt<3> connect _WIRE_253, _T_4275 connect _WIRE_231.csr_cmd, _WIRE_253 node _T_4276 = mux(_T_608, deq_vec[0][2].flush_on_commit, UInt<1>(0h0)) node _T_4277 = mux(_T_609, deq_vec[1][2].flush_on_commit, UInt<1>(0h0)) node _T_4278 = mux(_T_610, deq_vec[2][2].flush_on_commit, UInt<1>(0h0)) node _T_4279 = mux(_T_611, deq_vec[3][2].flush_on_commit, UInt<1>(0h0)) node _T_4280 = mux(_T_612, deq_vec[4][2].flush_on_commit, UInt<1>(0h0)) node _T_4281 = mux(_T_613, deq_vec[5][2].flush_on_commit, UInt<1>(0h0)) node _T_4282 = mux(_T_614, deq_vec[6][2].flush_on_commit, UInt<1>(0h0)) node _T_4283 = mux(_T_615, deq_vec[7][2].flush_on_commit, UInt<1>(0h0)) node _T_4284 = or(_T_4276, _T_4277) node _T_4285 = or(_T_4284, _T_4278) node _T_4286 = or(_T_4285, _T_4279) node _T_4287 = or(_T_4286, _T_4280) node _T_4288 = or(_T_4287, _T_4281) node _T_4289 = or(_T_4288, _T_4282) node _T_4290 = or(_T_4289, _T_4283) wire _WIRE_254 : UInt<1> connect _WIRE_254, _T_4290 connect _WIRE_231.flush_on_commit, _WIRE_254 node _T_4291 = mux(_T_608, deq_vec[0][2].is_unique, UInt<1>(0h0)) node _T_4292 = mux(_T_609, deq_vec[1][2].is_unique, UInt<1>(0h0)) node _T_4293 = mux(_T_610, deq_vec[2][2].is_unique, UInt<1>(0h0)) node _T_4294 = mux(_T_611, deq_vec[3][2].is_unique, UInt<1>(0h0)) node _T_4295 = mux(_T_612, deq_vec[4][2].is_unique, UInt<1>(0h0)) node _T_4296 = mux(_T_613, deq_vec[5][2].is_unique, UInt<1>(0h0)) node _T_4297 = mux(_T_614, deq_vec[6][2].is_unique, UInt<1>(0h0)) node _T_4298 = mux(_T_615, deq_vec[7][2].is_unique, UInt<1>(0h0)) node _T_4299 = or(_T_4291, _T_4292) node _T_4300 = or(_T_4299, _T_4293) node _T_4301 = or(_T_4300, _T_4294) node _T_4302 = or(_T_4301, _T_4295) node _T_4303 = or(_T_4302, _T_4296) node _T_4304 = or(_T_4303, _T_4297) node _T_4305 = or(_T_4304, _T_4298) wire _WIRE_255 : UInt<1> connect _WIRE_255, _T_4305 connect _WIRE_231.is_unique, _WIRE_255 node _T_4306 = mux(_T_608, deq_vec[0][2].uses_stq, UInt<1>(0h0)) node _T_4307 = mux(_T_609, deq_vec[1][2].uses_stq, UInt<1>(0h0)) node _T_4308 = mux(_T_610, deq_vec[2][2].uses_stq, UInt<1>(0h0)) node _T_4309 = mux(_T_611, deq_vec[3][2].uses_stq, UInt<1>(0h0)) node _T_4310 = mux(_T_612, deq_vec[4][2].uses_stq, UInt<1>(0h0)) node _T_4311 = mux(_T_613, deq_vec[5][2].uses_stq, UInt<1>(0h0)) node _T_4312 = mux(_T_614, deq_vec[6][2].uses_stq, UInt<1>(0h0)) node _T_4313 = mux(_T_615, deq_vec[7][2].uses_stq, UInt<1>(0h0)) node _T_4314 = or(_T_4306, _T_4307) node _T_4315 = or(_T_4314, _T_4308) node _T_4316 = or(_T_4315, _T_4309) node _T_4317 = or(_T_4316, _T_4310) node _T_4318 = or(_T_4317, _T_4311) node _T_4319 = or(_T_4318, _T_4312) node _T_4320 = or(_T_4319, _T_4313) wire _WIRE_256 : UInt<1> connect _WIRE_256, _T_4320 connect _WIRE_231.uses_stq, _WIRE_256 node _T_4321 = mux(_T_608, deq_vec[0][2].uses_ldq, UInt<1>(0h0)) node _T_4322 = mux(_T_609, deq_vec[1][2].uses_ldq, UInt<1>(0h0)) node _T_4323 = mux(_T_610, deq_vec[2][2].uses_ldq, UInt<1>(0h0)) node _T_4324 = mux(_T_611, deq_vec[3][2].uses_ldq, UInt<1>(0h0)) node _T_4325 = mux(_T_612, deq_vec[4][2].uses_ldq, UInt<1>(0h0)) node _T_4326 = mux(_T_613, deq_vec[5][2].uses_ldq, UInt<1>(0h0)) node _T_4327 = mux(_T_614, deq_vec[6][2].uses_ldq, UInt<1>(0h0)) node _T_4328 = mux(_T_615, deq_vec[7][2].uses_ldq, UInt<1>(0h0)) node _T_4329 = or(_T_4321, _T_4322) node _T_4330 = or(_T_4329, _T_4323) node _T_4331 = or(_T_4330, _T_4324) node _T_4332 = or(_T_4331, _T_4325) node _T_4333 = or(_T_4332, _T_4326) node _T_4334 = or(_T_4333, _T_4327) node _T_4335 = or(_T_4334, _T_4328) wire _WIRE_257 : UInt<1> connect _WIRE_257, _T_4335 connect _WIRE_231.uses_ldq, _WIRE_257 node _T_4336 = mux(_T_608, deq_vec[0][2].mem_signed, UInt<1>(0h0)) node _T_4337 = mux(_T_609, deq_vec[1][2].mem_signed, UInt<1>(0h0)) node _T_4338 = mux(_T_610, deq_vec[2][2].mem_signed, UInt<1>(0h0)) node _T_4339 = mux(_T_611, deq_vec[3][2].mem_signed, UInt<1>(0h0)) node _T_4340 = mux(_T_612, deq_vec[4][2].mem_signed, UInt<1>(0h0)) node _T_4341 = mux(_T_613, deq_vec[5][2].mem_signed, UInt<1>(0h0)) node _T_4342 = mux(_T_614, deq_vec[6][2].mem_signed, UInt<1>(0h0)) node _T_4343 = mux(_T_615, deq_vec[7][2].mem_signed, UInt<1>(0h0)) node _T_4344 = or(_T_4336, _T_4337) node _T_4345 = or(_T_4344, _T_4338) node _T_4346 = or(_T_4345, _T_4339) node _T_4347 = or(_T_4346, _T_4340) node _T_4348 = or(_T_4347, _T_4341) node _T_4349 = or(_T_4348, _T_4342) node _T_4350 = or(_T_4349, _T_4343) wire _WIRE_258 : UInt<1> connect _WIRE_258, _T_4350 connect _WIRE_231.mem_signed, _WIRE_258 node _T_4351 = mux(_T_608, deq_vec[0][2].mem_size, UInt<1>(0h0)) node _T_4352 = mux(_T_609, deq_vec[1][2].mem_size, UInt<1>(0h0)) node _T_4353 = mux(_T_610, deq_vec[2][2].mem_size, UInt<1>(0h0)) node _T_4354 = mux(_T_611, deq_vec[3][2].mem_size, UInt<1>(0h0)) node _T_4355 = mux(_T_612, deq_vec[4][2].mem_size, UInt<1>(0h0)) node _T_4356 = mux(_T_613, deq_vec[5][2].mem_size, UInt<1>(0h0)) node _T_4357 = mux(_T_614, deq_vec[6][2].mem_size, UInt<1>(0h0)) node _T_4358 = mux(_T_615, deq_vec[7][2].mem_size, UInt<1>(0h0)) node _T_4359 = or(_T_4351, _T_4352) node _T_4360 = or(_T_4359, _T_4353) node _T_4361 = or(_T_4360, _T_4354) node _T_4362 = or(_T_4361, _T_4355) node _T_4363 = or(_T_4362, _T_4356) node _T_4364 = or(_T_4363, _T_4357) node _T_4365 = or(_T_4364, _T_4358) wire _WIRE_259 : UInt<2> connect _WIRE_259, _T_4365 connect _WIRE_231.mem_size, _WIRE_259 node _T_4366 = mux(_T_608, deq_vec[0][2].mem_cmd, UInt<1>(0h0)) node _T_4367 = mux(_T_609, deq_vec[1][2].mem_cmd, UInt<1>(0h0)) node _T_4368 = mux(_T_610, deq_vec[2][2].mem_cmd, UInt<1>(0h0)) node _T_4369 = mux(_T_611, deq_vec[3][2].mem_cmd, UInt<1>(0h0)) node _T_4370 = mux(_T_612, deq_vec[4][2].mem_cmd, UInt<1>(0h0)) node _T_4371 = mux(_T_613, deq_vec[5][2].mem_cmd, UInt<1>(0h0)) node _T_4372 = mux(_T_614, deq_vec[6][2].mem_cmd, UInt<1>(0h0)) node _T_4373 = mux(_T_615, deq_vec[7][2].mem_cmd, UInt<1>(0h0)) node _T_4374 = or(_T_4366, _T_4367) node _T_4375 = or(_T_4374, _T_4368) node _T_4376 = or(_T_4375, _T_4369) node _T_4377 = or(_T_4376, _T_4370) node _T_4378 = or(_T_4377, _T_4371) node _T_4379 = or(_T_4378, _T_4372) node _T_4380 = or(_T_4379, _T_4373) wire _WIRE_260 : UInt<5> connect _WIRE_260, _T_4380 connect _WIRE_231.mem_cmd, _WIRE_260 node _T_4381 = mux(_T_608, deq_vec[0][2].exc_cause, UInt<1>(0h0)) node _T_4382 = mux(_T_609, deq_vec[1][2].exc_cause, UInt<1>(0h0)) node _T_4383 = mux(_T_610, deq_vec[2][2].exc_cause, UInt<1>(0h0)) node _T_4384 = mux(_T_611, deq_vec[3][2].exc_cause, UInt<1>(0h0)) node _T_4385 = mux(_T_612, deq_vec[4][2].exc_cause, UInt<1>(0h0)) node _T_4386 = mux(_T_613, deq_vec[5][2].exc_cause, UInt<1>(0h0)) node _T_4387 = mux(_T_614, deq_vec[6][2].exc_cause, UInt<1>(0h0)) node _T_4388 = mux(_T_615, deq_vec[7][2].exc_cause, UInt<1>(0h0)) node _T_4389 = or(_T_4381, _T_4382) node _T_4390 = or(_T_4389, _T_4383) node _T_4391 = or(_T_4390, _T_4384) node _T_4392 = or(_T_4391, _T_4385) node _T_4393 = or(_T_4392, _T_4386) node _T_4394 = or(_T_4393, _T_4387) node _T_4395 = or(_T_4394, _T_4388) wire _WIRE_261 : UInt<64> connect _WIRE_261, _T_4395 connect _WIRE_231.exc_cause, _WIRE_261 node _T_4396 = mux(_T_608, deq_vec[0][2].exception, UInt<1>(0h0)) node _T_4397 = mux(_T_609, deq_vec[1][2].exception, UInt<1>(0h0)) node _T_4398 = mux(_T_610, deq_vec[2][2].exception, UInt<1>(0h0)) node _T_4399 = mux(_T_611, deq_vec[3][2].exception, UInt<1>(0h0)) node _T_4400 = mux(_T_612, deq_vec[4][2].exception, UInt<1>(0h0)) node _T_4401 = mux(_T_613, deq_vec[5][2].exception, UInt<1>(0h0)) node _T_4402 = mux(_T_614, deq_vec[6][2].exception, UInt<1>(0h0)) node _T_4403 = mux(_T_615, deq_vec[7][2].exception, UInt<1>(0h0)) node _T_4404 = or(_T_4396, _T_4397) node _T_4405 = or(_T_4404, _T_4398) node _T_4406 = or(_T_4405, _T_4399) node _T_4407 = or(_T_4406, _T_4400) node _T_4408 = or(_T_4407, _T_4401) node _T_4409 = or(_T_4408, _T_4402) node _T_4410 = or(_T_4409, _T_4403) wire _WIRE_262 : UInt<1> connect _WIRE_262, _T_4410 connect _WIRE_231.exception, _WIRE_262 node _T_4411 = mux(_T_608, deq_vec[0][2].stale_pdst, UInt<1>(0h0)) node _T_4412 = mux(_T_609, deq_vec[1][2].stale_pdst, UInt<1>(0h0)) node _T_4413 = mux(_T_610, deq_vec[2][2].stale_pdst, UInt<1>(0h0)) node _T_4414 = mux(_T_611, deq_vec[3][2].stale_pdst, UInt<1>(0h0)) node _T_4415 = mux(_T_612, deq_vec[4][2].stale_pdst, UInt<1>(0h0)) node _T_4416 = mux(_T_613, deq_vec[5][2].stale_pdst, UInt<1>(0h0)) node _T_4417 = mux(_T_614, deq_vec[6][2].stale_pdst, UInt<1>(0h0)) node _T_4418 = mux(_T_615, deq_vec[7][2].stale_pdst, UInt<1>(0h0)) node _T_4419 = or(_T_4411, _T_4412) node _T_4420 = or(_T_4419, _T_4413) node _T_4421 = or(_T_4420, _T_4414) node _T_4422 = or(_T_4421, _T_4415) node _T_4423 = or(_T_4422, _T_4416) node _T_4424 = or(_T_4423, _T_4417) node _T_4425 = or(_T_4424, _T_4418) wire _WIRE_263 : UInt<7> connect _WIRE_263, _T_4425 connect _WIRE_231.stale_pdst, _WIRE_263 node _T_4426 = mux(_T_608, deq_vec[0][2].ppred_busy, UInt<1>(0h0)) node _T_4427 = mux(_T_609, deq_vec[1][2].ppred_busy, UInt<1>(0h0)) node _T_4428 = mux(_T_610, deq_vec[2][2].ppred_busy, UInt<1>(0h0)) node _T_4429 = mux(_T_611, deq_vec[3][2].ppred_busy, UInt<1>(0h0)) node _T_4430 = mux(_T_612, deq_vec[4][2].ppred_busy, UInt<1>(0h0)) node _T_4431 = mux(_T_613, deq_vec[5][2].ppred_busy, UInt<1>(0h0)) node _T_4432 = mux(_T_614, deq_vec[6][2].ppred_busy, UInt<1>(0h0)) node _T_4433 = mux(_T_615, deq_vec[7][2].ppred_busy, UInt<1>(0h0)) node _T_4434 = or(_T_4426, _T_4427) node _T_4435 = or(_T_4434, _T_4428) node _T_4436 = or(_T_4435, _T_4429) node _T_4437 = or(_T_4436, _T_4430) node _T_4438 = or(_T_4437, _T_4431) node _T_4439 = or(_T_4438, _T_4432) node _T_4440 = or(_T_4439, _T_4433) wire _WIRE_264 : UInt<1> connect _WIRE_264, _T_4440 connect _WIRE_231.ppred_busy, _WIRE_264 node _T_4441 = mux(_T_608, deq_vec[0][2].prs3_busy, UInt<1>(0h0)) node _T_4442 = mux(_T_609, deq_vec[1][2].prs3_busy, UInt<1>(0h0)) node _T_4443 = mux(_T_610, deq_vec[2][2].prs3_busy, UInt<1>(0h0)) node _T_4444 = mux(_T_611, deq_vec[3][2].prs3_busy, UInt<1>(0h0)) node _T_4445 = mux(_T_612, deq_vec[4][2].prs3_busy, UInt<1>(0h0)) node _T_4446 = mux(_T_613, deq_vec[5][2].prs3_busy, UInt<1>(0h0)) node _T_4447 = mux(_T_614, deq_vec[6][2].prs3_busy, UInt<1>(0h0)) node _T_4448 = mux(_T_615, deq_vec[7][2].prs3_busy, UInt<1>(0h0)) node _T_4449 = or(_T_4441, _T_4442) node _T_4450 = or(_T_4449, _T_4443) node _T_4451 = or(_T_4450, _T_4444) node _T_4452 = or(_T_4451, _T_4445) node _T_4453 = or(_T_4452, _T_4446) node _T_4454 = or(_T_4453, _T_4447) node _T_4455 = or(_T_4454, _T_4448) wire _WIRE_265 : UInt<1> connect _WIRE_265, _T_4455 connect _WIRE_231.prs3_busy, _WIRE_265 node _T_4456 = mux(_T_608, deq_vec[0][2].prs2_busy, UInt<1>(0h0)) node _T_4457 = mux(_T_609, deq_vec[1][2].prs2_busy, UInt<1>(0h0)) node _T_4458 = mux(_T_610, deq_vec[2][2].prs2_busy, UInt<1>(0h0)) node _T_4459 = mux(_T_611, deq_vec[3][2].prs2_busy, UInt<1>(0h0)) node _T_4460 = mux(_T_612, deq_vec[4][2].prs2_busy, UInt<1>(0h0)) node _T_4461 = mux(_T_613, deq_vec[5][2].prs2_busy, UInt<1>(0h0)) node _T_4462 = mux(_T_614, deq_vec[6][2].prs2_busy, UInt<1>(0h0)) node _T_4463 = mux(_T_615, deq_vec[7][2].prs2_busy, UInt<1>(0h0)) node _T_4464 = or(_T_4456, _T_4457) node _T_4465 = or(_T_4464, _T_4458) node _T_4466 = or(_T_4465, _T_4459) node _T_4467 = or(_T_4466, _T_4460) node _T_4468 = or(_T_4467, _T_4461) node _T_4469 = or(_T_4468, _T_4462) node _T_4470 = or(_T_4469, _T_4463) wire _WIRE_266 : UInt<1> connect _WIRE_266, _T_4470 connect _WIRE_231.prs2_busy, _WIRE_266 node _T_4471 = mux(_T_608, deq_vec[0][2].prs1_busy, UInt<1>(0h0)) node _T_4472 = mux(_T_609, deq_vec[1][2].prs1_busy, UInt<1>(0h0)) node _T_4473 = mux(_T_610, deq_vec[2][2].prs1_busy, UInt<1>(0h0)) node _T_4474 = mux(_T_611, deq_vec[3][2].prs1_busy, UInt<1>(0h0)) node _T_4475 = mux(_T_612, deq_vec[4][2].prs1_busy, UInt<1>(0h0)) node _T_4476 = mux(_T_613, deq_vec[5][2].prs1_busy, UInt<1>(0h0)) node _T_4477 = mux(_T_614, deq_vec[6][2].prs1_busy, UInt<1>(0h0)) node _T_4478 = mux(_T_615, deq_vec[7][2].prs1_busy, UInt<1>(0h0)) node _T_4479 = or(_T_4471, _T_4472) node _T_4480 = or(_T_4479, _T_4473) node _T_4481 = or(_T_4480, _T_4474) node _T_4482 = or(_T_4481, _T_4475) node _T_4483 = or(_T_4482, _T_4476) node _T_4484 = or(_T_4483, _T_4477) node _T_4485 = or(_T_4484, _T_4478) wire _WIRE_267 : UInt<1> connect _WIRE_267, _T_4485 connect _WIRE_231.prs1_busy, _WIRE_267 node _T_4486 = mux(_T_608, deq_vec[0][2].ppred, UInt<1>(0h0)) node _T_4487 = mux(_T_609, deq_vec[1][2].ppred, UInt<1>(0h0)) node _T_4488 = mux(_T_610, deq_vec[2][2].ppred, UInt<1>(0h0)) node _T_4489 = mux(_T_611, deq_vec[3][2].ppred, UInt<1>(0h0)) node _T_4490 = mux(_T_612, deq_vec[4][2].ppred, UInt<1>(0h0)) node _T_4491 = mux(_T_613, deq_vec[5][2].ppred, UInt<1>(0h0)) node _T_4492 = mux(_T_614, deq_vec[6][2].ppred, UInt<1>(0h0)) node _T_4493 = mux(_T_615, deq_vec[7][2].ppred, UInt<1>(0h0)) node _T_4494 = or(_T_4486, _T_4487) node _T_4495 = or(_T_4494, _T_4488) node _T_4496 = or(_T_4495, _T_4489) node _T_4497 = or(_T_4496, _T_4490) node _T_4498 = or(_T_4497, _T_4491) node _T_4499 = or(_T_4498, _T_4492) node _T_4500 = or(_T_4499, _T_4493) wire _WIRE_268 : UInt<5> connect _WIRE_268, _T_4500 connect _WIRE_231.ppred, _WIRE_268 node _T_4501 = mux(_T_608, deq_vec[0][2].prs3, UInt<1>(0h0)) node _T_4502 = mux(_T_609, deq_vec[1][2].prs3, UInt<1>(0h0)) node _T_4503 = mux(_T_610, deq_vec[2][2].prs3, UInt<1>(0h0)) node _T_4504 = mux(_T_611, deq_vec[3][2].prs3, UInt<1>(0h0)) node _T_4505 = mux(_T_612, deq_vec[4][2].prs3, UInt<1>(0h0)) node _T_4506 = mux(_T_613, deq_vec[5][2].prs3, UInt<1>(0h0)) node _T_4507 = mux(_T_614, deq_vec[6][2].prs3, UInt<1>(0h0)) node _T_4508 = mux(_T_615, deq_vec[7][2].prs3, UInt<1>(0h0)) node _T_4509 = or(_T_4501, _T_4502) node _T_4510 = or(_T_4509, _T_4503) node _T_4511 = or(_T_4510, _T_4504) node _T_4512 = or(_T_4511, _T_4505) node _T_4513 = or(_T_4512, _T_4506) node _T_4514 = or(_T_4513, _T_4507) node _T_4515 = or(_T_4514, _T_4508) wire _WIRE_269 : UInt<7> connect _WIRE_269, _T_4515 connect _WIRE_231.prs3, _WIRE_269 node _T_4516 = mux(_T_608, deq_vec[0][2].prs2, UInt<1>(0h0)) node _T_4517 = mux(_T_609, deq_vec[1][2].prs2, UInt<1>(0h0)) node _T_4518 = mux(_T_610, deq_vec[2][2].prs2, UInt<1>(0h0)) node _T_4519 = mux(_T_611, deq_vec[3][2].prs2, UInt<1>(0h0)) node _T_4520 = mux(_T_612, deq_vec[4][2].prs2, UInt<1>(0h0)) node _T_4521 = mux(_T_613, deq_vec[5][2].prs2, UInt<1>(0h0)) node _T_4522 = mux(_T_614, deq_vec[6][2].prs2, UInt<1>(0h0)) node _T_4523 = mux(_T_615, deq_vec[7][2].prs2, UInt<1>(0h0)) node _T_4524 = or(_T_4516, _T_4517) node _T_4525 = or(_T_4524, _T_4518) node _T_4526 = or(_T_4525, _T_4519) node _T_4527 = or(_T_4526, _T_4520) node _T_4528 = or(_T_4527, _T_4521) node _T_4529 = or(_T_4528, _T_4522) node _T_4530 = or(_T_4529, _T_4523) wire _WIRE_270 : UInt<7> connect _WIRE_270, _T_4530 connect _WIRE_231.prs2, _WIRE_270 node _T_4531 = mux(_T_608, deq_vec[0][2].prs1, UInt<1>(0h0)) node _T_4532 = mux(_T_609, deq_vec[1][2].prs1, UInt<1>(0h0)) node _T_4533 = mux(_T_610, deq_vec[2][2].prs1, UInt<1>(0h0)) node _T_4534 = mux(_T_611, deq_vec[3][2].prs1, UInt<1>(0h0)) node _T_4535 = mux(_T_612, deq_vec[4][2].prs1, UInt<1>(0h0)) node _T_4536 = mux(_T_613, deq_vec[5][2].prs1, UInt<1>(0h0)) node _T_4537 = mux(_T_614, deq_vec[6][2].prs1, UInt<1>(0h0)) node _T_4538 = mux(_T_615, deq_vec[7][2].prs1, UInt<1>(0h0)) node _T_4539 = or(_T_4531, _T_4532) node _T_4540 = or(_T_4539, _T_4533) node _T_4541 = or(_T_4540, _T_4534) node _T_4542 = or(_T_4541, _T_4535) node _T_4543 = or(_T_4542, _T_4536) node _T_4544 = or(_T_4543, _T_4537) node _T_4545 = or(_T_4544, _T_4538) wire _WIRE_271 : UInt<7> connect _WIRE_271, _T_4545 connect _WIRE_231.prs1, _WIRE_271 node _T_4546 = mux(_T_608, deq_vec[0][2].pdst, UInt<1>(0h0)) node _T_4547 = mux(_T_609, deq_vec[1][2].pdst, UInt<1>(0h0)) node _T_4548 = mux(_T_610, deq_vec[2][2].pdst, UInt<1>(0h0)) node _T_4549 = mux(_T_611, deq_vec[3][2].pdst, UInt<1>(0h0)) node _T_4550 = mux(_T_612, deq_vec[4][2].pdst, UInt<1>(0h0)) node _T_4551 = mux(_T_613, deq_vec[5][2].pdst, UInt<1>(0h0)) node _T_4552 = mux(_T_614, deq_vec[6][2].pdst, UInt<1>(0h0)) node _T_4553 = mux(_T_615, deq_vec[7][2].pdst, UInt<1>(0h0)) node _T_4554 = or(_T_4546, _T_4547) node _T_4555 = or(_T_4554, _T_4548) node _T_4556 = or(_T_4555, _T_4549) node _T_4557 = or(_T_4556, _T_4550) node _T_4558 = or(_T_4557, _T_4551) node _T_4559 = or(_T_4558, _T_4552) node _T_4560 = or(_T_4559, _T_4553) wire _WIRE_272 : UInt<7> connect _WIRE_272, _T_4560 connect _WIRE_231.pdst, _WIRE_272 node _T_4561 = mux(_T_608, deq_vec[0][2].rxq_idx, UInt<1>(0h0)) node _T_4562 = mux(_T_609, deq_vec[1][2].rxq_idx, UInt<1>(0h0)) node _T_4563 = mux(_T_610, deq_vec[2][2].rxq_idx, UInt<1>(0h0)) node _T_4564 = mux(_T_611, deq_vec[3][2].rxq_idx, UInt<1>(0h0)) node _T_4565 = mux(_T_612, deq_vec[4][2].rxq_idx, UInt<1>(0h0)) node _T_4566 = mux(_T_613, deq_vec[5][2].rxq_idx, UInt<1>(0h0)) node _T_4567 = mux(_T_614, deq_vec[6][2].rxq_idx, UInt<1>(0h0)) node _T_4568 = mux(_T_615, deq_vec[7][2].rxq_idx, UInt<1>(0h0)) node _T_4569 = or(_T_4561, _T_4562) node _T_4570 = or(_T_4569, _T_4563) node _T_4571 = or(_T_4570, _T_4564) node _T_4572 = or(_T_4571, _T_4565) node _T_4573 = or(_T_4572, _T_4566) node _T_4574 = or(_T_4573, _T_4567) node _T_4575 = or(_T_4574, _T_4568) wire _WIRE_273 : UInt<2> connect _WIRE_273, _T_4575 connect _WIRE_231.rxq_idx, _WIRE_273 node _T_4576 = mux(_T_608, deq_vec[0][2].stq_idx, UInt<1>(0h0)) node _T_4577 = mux(_T_609, deq_vec[1][2].stq_idx, UInt<1>(0h0)) node _T_4578 = mux(_T_610, deq_vec[2][2].stq_idx, UInt<1>(0h0)) node _T_4579 = mux(_T_611, deq_vec[3][2].stq_idx, UInt<1>(0h0)) node _T_4580 = mux(_T_612, deq_vec[4][2].stq_idx, UInt<1>(0h0)) node _T_4581 = mux(_T_613, deq_vec[5][2].stq_idx, UInt<1>(0h0)) node _T_4582 = mux(_T_614, deq_vec[6][2].stq_idx, UInt<1>(0h0)) node _T_4583 = mux(_T_615, deq_vec[7][2].stq_idx, UInt<1>(0h0)) node _T_4584 = or(_T_4576, _T_4577) node _T_4585 = or(_T_4584, _T_4578) node _T_4586 = or(_T_4585, _T_4579) node _T_4587 = or(_T_4586, _T_4580) node _T_4588 = or(_T_4587, _T_4581) node _T_4589 = or(_T_4588, _T_4582) node _T_4590 = or(_T_4589, _T_4583) wire _WIRE_274 : UInt<5> connect _WIRE_274, _T_4590 connect _WIRE_231.stq_idx, _WIRE_274 node _T_4591 = mux(_T_608, deq_vec[0][2].ldq_idx, UInt<1>(0h0)) node _T_4592 = mux(_T_609, deq_vec[1][2].ldq_idx, UInt<1>(0h0)) node _T_4593 = mux(_T_610, deq_vec[2][2].ldq_idx, UInt<1>(0h0)) node _T_4594 = mux(_T_611, deq_vec[3][2].ldq_idx, UInt<1>(0h0)) node _T_4595 = mux(_T_612, deq_vec[4][2].ldq_idx, UInt<1>(0h0)) node _T_4596 = mux(_T_613, deq_vec[5][2].ldq_idx, UInt<1>(0h0)) node _T_4597 = mux(_T_614, deq_vec[6][2].ldq_idx, UInt<1>(0h0)) node _T_4598 = mux(_T_615, deq_vec[7][2].ldq_idx, UInt<1>(0h0)) node _T_4599 = or(_T_4591, _T_4592) node _T_4600 = or(_T_4599, _T_4593) node _T_4601 = or(_T_4600, _T_4594) node _T_4602 = or(_T_4601, _T_4595) node _T_4603 = or(_T_4602, _T_4596) node _T_4604 = or(_T_4603, _T_4597) node _T_4605 = or(_T_4604, _T_4598) wire _WIRE_275 : UInt<5> connect _WIRE_275, _T_4605 connect _WIRE_231.ldq_idx, _WIRE_275 node _T_4606 = mux(_T_608, deq_vec[0][2].rob_idx, UInt<1>(0h0)) node _T_4607 = mux(_T_609, deq_vec[1][2].rob_idx, UInt<1>(0h0)) node _T_4608 = mux(_T_610, deq_vec[2][2].rob_idx, UInt<1>(0h0)) node _T_4609 = mux(_T_611, deq_vec[3][2].rob_idx, UInt<1>(0h0)) node _T_4610 = mux(_T_612, deq_vec[4][2].rob_idx, UInt<1>(0h0)) node _T_4611 = mux(_T_613, deq_vec[5][2].rob_idx, UInt<1>(0h0)) node _T_4612 = mux(_T_614, deq_vec[6][2].rob_idx, UInt<1>(0h0)) node _T_4613 = mux(_T_615, deq_vec[7][2].rob_idx, UInt<1>(0h0)) node _T_4614 = or(_T_4606, _T_4607) node _T_4615 = or(_T_4614, _T_4608) node _T_4616 = or(_T_4615, _T_4609) node _T_4617 = or(_T_4616, _T_4610) node _T_4618 = or(_T_4617, _T_4611) node _T_4619 = or(_T_4618, _T_4612) node _T_4620 = or(_T_4619, _T_4613) wire _WIRE_276 : UInt<7> connect _WIRE_276, _T_4620 connect _WIRE_231.rob_idx, _WIRE_276 wire _WIRE_277 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_4621 = mux(_T_608, deq_vec[0][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4622 = mux(_T_609, deq_vec[1][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4623 = mux(_T_610, deq_vec[2][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4624 = mux(_T_611, deq_vec[3][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4625 = mux(_T_612, deq_vec[4][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4626 = mux(_T_613, deq_vec[5][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4627 = mux(_T_614, deq_vec[6][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4628 = mux(_T_615, deq_vec[7][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4629 = or(_T_4621, _T_4622) node _T_4630 = or(_T_4629, _T_4623) node _T_4631 = or(_T_4630, _T_4624) node _T_4632 = or(_T_4631, _T_4625) node _T_4633 = or(_T_4632, _T_4626) node _T_4634 = or(_T_4633, _T_4627) node _T_4635 = or(_T_4634, _T_4628) wire _WIRE_278 : UInt<1> connect _WIRE_278, _T_4635 connect _WIRE_277.vec, _WIRE_278 node _T_4636 = mux(_T_608, deq_vec[0][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4637 = mux(_T_609, deq_vec[1][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4638 = mux(_T_610, deq_vec[2][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4639 = mux(_T_611, deq_vec[3][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4640 = mux(_T_612, deq_vec[4][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4641 = mux(_T_613, deq_vec[5][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4642 = mux(_T_614, deq_vec[6][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4643 = mux(_T_615, deq_vec[7][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4644 = or(_T_4636, _T_4637) node _T_4645 = or(_T_4644, _T_4638) node _T_4646 = or(_T_4645, _T_4639) node _T_4647 = or(_T_4646, _T_4640) node _T_4648 = or(_T_4647, _T_4641) node _T_4649 = or(_T_4648, _T_4642) node _T_4650 = or(_T_4649, _T_4643) wire _WIRE_279 : UInt<1> connect _WIRE_279, _T_4650 connect _WIRE_277.wflags, _WIRE_279 node _T_4651 = mux(_T_608, deq_vec[0][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4652 = mux(_T_609, deq_vec[1][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4653 = mux(_T_610, deq_vec[2][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4654 = mux(_T_611, deq_vec[3][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4655 = mux(_T_612, deq_vec[4][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4656 = mux(_T_613, deq_vec[5][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4657 = mux(_T_614, deq_vec[6][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4658 = mux(_T_615, deq_vec[7][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4659 = or(_T_4651, _T_4652) node _T_4660 = or(_T_4659, _T_4653) node _T_4661 = or(_T_4660, _T_4654) node _T_4662 = or(_T_4661, _T_4655) node _T_4663 = or(_T_4662, _T_4656) node _T_4664 = or(_T_4663, _T_4657) node _T_4665 = or(_T_4664, _T_4658) wire _WIRE_280 : UInt<1> connect _WIRE_280, _T_4665 connect _WIRE_277.sqrt, _WIRE_280 node _T_4666 = mux(_T_608, deq_vec[0][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4667 = mux(_T_609, deq_vec[1][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4668 = mux(_T_610, deq_vec[2][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4669 = mux(_T_611, deq_vec[3][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4670 = mux(_T_612, deq_vec[4][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4671 = mux(_T_613, deq_vec[5][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4672 = mux(_T_614, deq_vec[6][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4673 = mux(_T_615, deq_vec[7][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4674 = or(_T_4666, _T_4667) node _T_4675 = or(_T_4674, _T_4668) node _T_4676 = or(_T_4675, _T_4669) node _T_4677 = or(_T_4676, _T_4670) node _T_4678 = or(_T_4677, _T_4671) node _T_4679 = or(_T_4678, _T_4672) node _T_4680 = or(_T_4679, _T_4673) wire _WIRE_281 : UInt<1> connect _WIRE_281, _T_4680 connect _WIRE_277.div, _WIRE_281 node _T_4681 = mux(_T_608, deq_vec[0][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4682 = mux(_T_609, deq_vec[1][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4683 = mux(_T_610, deq_vec[2][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4684 = mux(_T_611, deq_vec[3][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4685 = mux(_T_612, deq_vec[4][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4686 = mux(_T_613, deq_vec[5][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4687 = mux(_T_614, deq_vec[6][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4688 = mux(_T_615, deq_vec[7][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4689 = or(_T_4681, _T_4682) node _T_4690 = or(_T_4689, _T_4683) node _T_4691 = or(_T_4690, _T_4684) node _T_4692 = or(_T_4691, _T_4685) node _T_4693 = or(_T_4692, _T_4686) node _T_4694 = or(_T_4693, _T_4687) node _T_4695 = or(_T_4694, _T_4688) wire _WIRE_282 : UInt<1> connect _WIRE_282, _T_4695 connect _WIRE_277.fma, _WIRE_282 node _T_4696 = mux(_T_608, deq_vec[0][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4697 = mux(_T_609, deq_vec[1][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4698 = mux(_T_610, deq_vec[2][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4699 = mux(_T_611, deq_vec[3][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4700 = mux(_T_612, deq_vec[4][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4701 = mux(_T_613, deq_vec[5][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4702 = mux(_T_614, deq_vec[6][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4703 = mux(_T_615, deq_vec[7][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4704 = or(_T_4696, _T_4697) node _T_4705 = or(_T_4704, _T_4698) node _T_4706 = or(_T_4705, _T_4699) node _T_4707 = or(_T_4706, _T_4700) node _T_4708 = or(_T_4707, _T_4701) node _T_4709 = or(_T_4708, _T_4702) node _T_4710 = or(_T_4709, _T_4703) wire _WIRE_283 : UInt<1> connect _WIRE_283, _T_4710 connect _WIRE_277.fastpipe, _WIRE_283 node _T_4711 = mux(_T_608, deq_vec[0][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4712 = mux(_T_609, deq_vec[1][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4713 = mux(_T_610, deq_vec[2][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4714 = mux(_T_611, deq_vec[3][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4715 = mux(_T_612, deq_vec[4][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4716 = mux(_T_613, deq_vec[5][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4717 = mux(_T_614, deq_vec[6][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4718 = mux(_T_615, deq_vec[7][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4719 = or(_T_4711, _T_4712) node _T_4720 = or(_T_4719, _T_4713) node _T_4721 = or(_T_4720, _T_4714) node _T_4722 = or(_T_4721, _T_4715) node _T_4723 = or(_T_4722, _T_4716) node _T_4724 = or(_T_4723, _T_4717) node _T_4725 = or(_T_4724, _T_4718) wire _WIRE_284 : UInt<1> connect _WIRE_284, _T_4725 connect _WIRE_277.toint, _WIRE_284 node _T_4726 = mux(_T_608, deq_vec[0][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4727 = mux(_T_609, deq_vec[1][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4728 = mux(_T_610, deq_vec[2][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4729 = mux(_T_611, deq_vec[3][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4730 = mux(_T_612, deq_vec[4][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4731 = mux(_T_613, deq_vec[5][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4732 = mux(_T_614, deq_vec[6][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4733 = mux(_T_615, deq_vec[7][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4734 = or(_T_4726, _T_4727) node _T_4735 = or(_T_4734, _T_4728) node _T_4736 = or(_T_4735, _T_4729) node _T_4737 = or(_T_4736, _T_4730) node _T_4738 = or(_T_4737, _T_4731) node _T_4739 = or(_T_4738, _T_4732) node _T_4740 = or(_T_4739, _T_4733) wire _WIRE_285 : UInt<1> connect _WIRE_285, _T_4740 connect _WIRE_277.fromint, _WIRE_285 node _T_4741 = mux(_T_608, deq_vec[0][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4742 = mux(_T_609, deq_vec[1][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4743 = mux(_T_610, deq_vec[2][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4744 = mux(_T_611, deq_vec[3][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4745 = mux(_T_612, deq_vec[4][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4746 = mux(_T_613, deq_vec[5][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4747 = mux(_T_614, deq_vec[6][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4748 = mux(_T_615, deq_vec[7][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4749 = or(_T_4741, _T_4742) node _T_4750 = or(_T_4749, _T_4743) node _T_4751 = or(_T_4750, _T_4744) node _T_4752 = or(_T_4751, _T_4745) node _T_4753 = or(_T_4752, _T_4746) node _T_4754 = or(_T_4753, _T_4747) node _T_4755 = or(_T_4754, _T_4748) wire _WIRE_286 : UInt<2> connect _WIRE_286, _T_4755 connect _WIRE_277.typeTagOut, _WIRE_286 node _T_4756 = mux(_T_608, deq_vec[0][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4757 = mux(_T_609, deq_vec[1][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4758 = mux(_T_610, deq_vec[2][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4759 = mux(_T_611, deq_vec[3][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4760 = mux(_T_612, deq_vec[4][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4761 = mux(_T_613, deq_vec[5][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4762 = mux(_T_614, deq_vec[6][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4763 = mux(_T_615, deq_vec[7][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4764 = or(_T_4756, _T_4757) node _T_4765 = or(_T_4764, _T_4758) node _T_4766 = or(_T_4765, _T_4759) node _T_4767 = or(_T_4766, _T_4760) node _T_4768 = or(_T_4767, _T_4761) node _T_4769 = or(_T_4768, _T_4762) node _T_4770 = or(_T_4769, _T_4763) wire _WIRE_287 : UInt<2> connect _WIRE_287, _T_4770 connect _WIRE_277.typeTagIn, _WIRE_287 node _T_4771 = mux(_T_608, deq_vec[0][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4772 = mux(_T_609, deq_vec[1][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4773 = mux(_T_610, deq_vec[2][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4774 = mux(_T_611, deq_vec[3][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4775 = mux(_T_612, deq_vec[4][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4776 = mux(_T_613, deq_vec[5][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4777 = mux(_T_614, deq_vec[6][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4778 = mux(_T_615, deq_vec[7][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4779 = or(_T_4771, _T_4772) node _T_4780 = or(_T_4779, _T_4773) node _T_4781 = or(_T_4780, _T_4774) node _T_4782 = or(_T_4781, _T_4775) node _T_4783 = or(_T_4782, _T_4776) node _T_4784 = or(_T_4783, _T_4777) node _T_4785 = or(_T_4784, _T_4778) wire _WIRE_288 : UInt<1> connect _WIRE_288, _T_4785 connect _WIRE_277.swap23, _WIRE_288 node _T_4786 = mux(_T_608, deq_vec[0][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4787 = mux(_T_609, deq_vec[1][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4788 = mux(_T_610, deq_vec[2][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4789 = mux(_T_611, deq_vec[3][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4790 = mux(_T_612, deq_vec[4][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4791 = mux(_T_613, deq_vec[5][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4792 = mux(_T_614, deq_vec[6][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4793 = mux(_T_615, deq_vec[7][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4794 = or(_T_4786, _T_4787) node _T_4795 = or(_T_4794, _T_4788) node _T_4796 = or(_T_4795, _T_4789) node _T_4797 = or(_T_4796, _T_4790) node _T_4798 = or(_T_4797, _T_4791) node _T_4799 = or(_T_4798, _T_4792) node _T_4800 = or(_T_4799, _T_4793) wire _WIRE_289 : UInt<1> connect _WIRE_289, _T_4800 connect _WIRE_277.swap12, _WIRE_289 node _T_4801 = mux(_T_608, deq_vec[0][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4802 = mux(_T_609, deq_vec[1][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4803 = mux(_T_610, deq_vec[2][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4804 = mux(_T_611, deq_vec[3][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4805 = mux(_T_612, deq_vec[4][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4806 = mux(_T_613, deq_vec[5][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4807 = mux(_T_614, deq_vec[6][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4808 = mux(_T_615, deq_vec[7][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4809 = or(_T_4801, _T_4802) node _T_4810 = or(_T_4809, _T_4803) node _T_4811 = or(_T_4810, _T_4804) node _T_4812 = or(_T_4811, _T_4805) node _T_4813 = or(_T_4812, _T_4806) node _T_4814 = or(_T_4813, _T_4807) node _T_4815 = or(_T_4814, _T_4808) wire _WIRE_290 : UInt<1> connect _WIRE_290, _T_4815 connect _WIRE_277.ren3, _WIRE_290 node _T_4816 = mux(_T_608, deq_vec[0][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4817 = mux(_T_609, deq_vec[1][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4818 = mux(_T_610, deq_vec[2][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4819 = mux(_T_611, deq_vec[3][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4820 = mux(_T_612, deq_vec[4][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4821 = mux(_T_613, deq_vec[5][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4822 = mux(_T_614, deq_vec[6][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4823 = mux(_T_615, deq_vec[7][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4824 = or(_T_4816, _T_4817) node _T_4825 = or(_T_4824, _T_4818) node _T_4826 = or(_T_4825, _T_4819) node _T_4827 = or(_T_4826, _T_4820) node _T_4828 = or(_T_4827, _T_4821) node _T_4829 = or(_T_4828, _T_4822) node _T_4830 = or(_T_4829, _T_4823) wire _WIRE_291 : UInt<1> connect _WIRE_291, _T_4830 connect _WIRE_277.ren2, _WIRE_291 node _T_4831 = mux(_T_608, deq_vec[0][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4832 = mux(_T_609, deq_vec[1][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4833 = mux(_T_610, deq_vec[2][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4834 = mux(_T_611, deq_vec[3][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4835 = mux(_T_612, deq_vec[4][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4836 = mux(_T_613, deq_vec[5][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4837 = mux(_T_614, deq_vec[6][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4838 = mux(_T_615, deq_vec[7][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4839 = or(_T_4831, _T_4832) node _T_4840 = or(_T_4839, _T_4833) node _T_4841 = or(_T_4840, _T_4834) node _T_4842 = or(_T_4841, _T_4835) node _T_4843 = or(_T_4842, _T_4836) node _T_4844 = or(_T_4843, _T_4837) node _T_4845 = or(_T_4844, _T_4838) wire _WIRE_292 : UInt<1> connect _WIRE_292, _T_4845 connect _WIRE_277.ren1, _WIRE_292 node _T_4846 = mux(_T_608, deq_vec[0][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4847 = mux(_T_609, deq_vec[1][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4848 = mux(_T_610, deq_vec[2][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4849 = mux(_T_611, deq_vec[3][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4850 = mux(_T_612, deq_vec[4][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4851 = mux(_T_613, deq_vec[5][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4852 = mux(_T_614, deq_vec[6][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4853 = mux(_T_615, deq_vec[7][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4854 = or(_T_4846, _T_4847) node _T_4855 = or(_T_4854, _T_4848) node _T_4856 = or(_T_4855, _T_4849) node _T_4857 = or(_T_4856, _T_4850) node _T_4858 = or(_T_4857, _T_4851) node _T_4859 = or(_T_4858, _T_4852) node _T_4860 = or(_T_4859, _T_4853) wire _WIRE_293 : UInt<1> connect _WIRE_293, _T_4860 connect _WIRE_277.wen, _WIRE_293 node _T_4861 = mux(_T_608, deq_vec[0][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4862 = mux(_T_609, deq_vec[1][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4863 = mux(_T_610, deq_vec[2][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4864 = mux(_T_611, deq_vec[3][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4865 = mux(_T_612, deq_vec[4][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4866 = mux(_T_613, deq_vec[5][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4867 = mux(_T_614, deq_vec[6][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4868 = mux(_T_615, deq_vec[7][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4869 = or(_T_4861, _T_4862) node _T_4870 = or(_T_4869, _T_4863) node _T_4871 = or(_T_4870, _T_4864) node _T_4872 = or(_T_4871, _T_4865) node _T_4873 = or(_T_4872, _T_4866) node _T_4874 = or(_T_4873, _T_4867) node _T_4875 = or(_T_4874, _T_4868) wire _WIRE_294 : UInt<1> connect _WIRE_294, _T_4875 connect _WIRE_277.ldst, _WIRE_294 connect _WIRE_231.fp_ctrl, _WIRE_277 node _T_4876 = mux(_T_608, deq_vec[0][2].op2_sel, UInt<1>(0h0)) node _T_4877 = mux(_T_609, deq_vec[1][2].op2_sel, UInt<1>(0h0)) node _T_4878 = mux(_T_610, deq_vec[2][2].op2_sel, UInt<1>(0h0)) node _T_4879 = mux(_T_611, deq_vec[3][2].op2_sel, UInt<1>(0h0)) node _T_4880 = mux(_T_612, deq_vec[4][2].op2_sel, UInt<1>(0h0)) node _T_4881 = mux(_T_613, deq_vec[5][2].op2_sel, UInt<1>(0h0)) node _T_4882 = mux(_T_614, deq_vec[6][2].op2_sel, UInt<1>(0h0)) node _T_4883 = mux(_T_615, deq_vec[7][2].op2_sel, UInt<1>(0h0)) node _T_4884 = or(_T_4876, _T_4877) node _T_4885 = or(_T_4884, _T_4878) node _T_4886 = or(_T_4885, _T_4879) node _T_4887 = or(_T_4886, _T_4880) node _T_4888 = or(_T_4887, _T_4881) node _T_4889 = or(_T_4888, _T_4882) node _T_4890 = or(_T_4889, _T_4883) wire _WIRE_295 : UInt<3> connect _WIRE_295, _T_4890 connect _WIRE_231.op2_sel, _WIRE_295 node _T_4891 = mux(_T_608, deq_vec[0][2].op1_sel, UInt<1>(0h0)) node _T_4892 = mux(_T_609, deq_vec[1][2].op1_sel, UInt<1>(0h0)) node _T_4893 = mux(_T_610, deq_vec[2][2].op1_sel, UInt<1>(0h0)) node _T_4894 = mux(_T_611, deq_vec[3][2].op1_sel, UInt<1>(0h0)) node _T_4895 = mux(_T_612, deq_vec[4][2].op1_sel, UInt<1>(0h0)) node _T_4896 = mux(_T_613, deq_vec[5][2].op1_sel, UInt<1>(0h0)) node _T_4897 = mux(_T_614, deq_vec[6][2].op1_sel, UInt<1>(0h0)) node _T_4898 = mux(_T_615, deq_vec[7][2].op1_sel, UInt<1>(0h0)) node _T_4899 = or(_T_4891, _T_4892) node _T_4900 = or(_T_4899, _T_4893) node _T_4901 = or(_T_4900, _T_4894) node _T_4902 = or(_T_4901, _T_4895) node _T_4903 = or(_T_4902, _T_4896) node _T_4904 = or(_T_4903, _T_4897) node _T_4905 = or(_T_4904, _T_4898) wire _WIRE_296 : UInt<2> connect _WIRE_296, _T_4905 connect _WIRE_231.op1_sel, _WIRE_296 node _T_4906 = mux(_T_608, deq_vec[0][2].imm_packed, UInt<1>(0h0)) node _T_4907 = mux(_T_609, deq_vec[1][2].imm_packed, UInt<1>(0h0)) node _T_4908 = mux(_T_610, deq_vec[2][2].imm_packed, UInt<1>(0h0)) node _T_4909 = mux(_T_611, deq_vec[3][2].imm_packed, UInt<1>(0h0)) node _T_4910 = mux(_T_612, deq_vec[4][2].imm_packed, UInt<1>(0h0)) node _T_4911 = mux(_T_613, deq_vec[5][2].imm_packed, UInt<1>(0h0)) node _T_4912 = mux(_T_614, deq_vec[6][2].imm_packed, UInt<1>(0h0)) node _T_4913 = mux(_T_615, deq_vec[7][2].imm_packed, UInt<1>(0h0)) node _T_4914 = or(_T_4906, _T_4907) node _T_4915 = or(_T_4914, _T_4908) node _T_4916 = or(_T_4915, _T_4909) node _T_4917 = or(_T_4916, _T_4910) node _T_4918 = or(_T_4917, _T_4911) node _T_4919 = or(_T_4918, _T_4912) node _T_4920 = or(_T_4919, _T_4913) wire _WIRE_297 : UInt<20> connect _WIRE_297, _T_4920 connect _WIRE_231.imm_packed, _WIRE_297 node _T_4921 = mux(_T_608, deq_vec[0][2].pimm, UInt<1>(0h0)) node _T_4922 = mux(_T_609, deq_vec[1][2].pimm, UInt<1>(0h0)) node _T_4923 = mux(_T_610, deq_vec[2][2].pimm, UInt<1>(0h0)) node _T_4924 = mux(_T_611, deq_vec[3][2].pimm, UInt<1>(0h0)) node _T_4925 = mux(_T_612, deq_vec[4][2].pimm, UInt<1>(0h0)) node _T_4926 = mux(_T_613, deq_vec[5][2].pimm, UInt<1>(0h0)) node _T_4927 = mux(_T_614, deq_vec[6][2].pimm, UInt<1>(0h0)) node _T_4928 = mux(_T_615, deq_vec[7][2].pimm, UInt<1>(0h0)) node _T_4929 = or(_T_4921, _T_4922) node _T_4930 = or(_T_4929, _T_4923) node _T_4931 = or(_T_4930, _T_4924) node _T_4932 = or(_T_4931, _T_4925) node _T_4933 = or(_T_4932, _T_4926) node _T_4934 = or(_T_4933, _T_4927) node _T_4935 = or(_T_4934, _T_4928) wire _WIRE_298 : UInt<5> connect _WIRE_298, _T_4935 connect _WIRE_231.pimm, _WIRE_298 node _T_4936 = mux(_T_608, deq_vec[0][2].imm_sel, UInt<1>(0h0)) node _T_4937 = mux(_T_609, deq_vec[1][2].imm_sel, UInt<1>(0h0)) node _T_4938 = mux(_T_610, deq_vec[2][2].imm_sel, UInt<1>(0h0)) node _T_4939 = mux(_T_611, deq_vec[3][2].imm_sel, UInt<1>(0h0)) node _T_4940 = mux(_T_612, deq_vec[4][2].imm_sel, UInt<1>(0h0)) node _T_4941 = mux(_T_613, deq_vec[5][2].imm_sel, UInt<1>(0h0)) node _T_4942 = mux(_T_614, deq_vec[6][2].imm_sel, UInt<1>(0h0)) node _T_4943 = mux(_T_615, deq_vec[7][2].imm_sel, UInt<1>(0h0)) node _T_4944 = or(_T_4936, _T_4937) node _T_4945 = or(_T_4944, _T_4938) node _T_4946 = or(_T_4945, _T_4939) node _T_4947 = or(_T_4946, _T_4940) node _T_4948 = or(_T_4947, _T_4941) node _T_4949 = or(_T_4948, _T_4942) node _T_4950 = or(_T_4949, _T_4943) wire _WIRE_299 : UInt<3> connect _WIRE_299, _T_4950 connect _WIRE_231.imm_sel, _WIRE_299 node _T_4951 = mux(_T_608, deq_vec[0][2].imm_rename, UInt<1>(0h0)) node _T_4952 = mux(_T_609, deq_vec[1][2].imm_rename, UInt<1>(0h0)) node _T_4953 = mux(_T_610, deq_vec[2][2].imm_rename, UInt<1>(0h0)) node _T_4954 = mux(_T_611, deq_vec[3][2].imm_rename, UInt<1>(0h0)) node _T_4955 = mux(_T_612, deq_vec[4][2].imm_rename, UInt<1>(0h0)) node _T_4956 = mux(_T_613, deq_vec[5][2].imm_rename, UInt<1>(0h0)) node _T_4957 = mux(_T_614, deq_vec[6][2].imm_rename, UInt<1>(0h0)) node _T_4958 = mux(_T_615, deq_vec[7][2].imm_rename, UInt<1>(0h0)) node _T_4959 = or(_T_4951, _T_4952) node _T_4960 = or(_T_4959, _T_4953) node _T_4961 = or(_T_4960, _T_4954) node _T_4962 = or(_T_4961, _T_4955) node _T_4963 = or(_T_4962, _T_4956) node _T_4964 = or(_T_4963, _T_4957) node _T_4965 = or(_T_4964, _T_4958) wire _WIRE_300 : UInt<1> connect _WIRE_300, _T_4965 connect _WIRE_231.imm_rename, _WIRE_300 node _T_4966 = mux(_T_608, deq_vec[0][2].taken, UInt<1>(0h0)) node _T_4967 = mux(_T_609, deq_vec[1][2].taken, UInt<1>(0h0)) node _T_4968 = mux(_T_610, deq_vec[2][2].taken, UInt<1>(0h0)) node _T_4969 = mux(_T_611, deq_vec[3][2].taken, UInt<1>(0h0)) node _T_4970 = mux(_T_612, deq_vec[4][2].taken, UInt<1>(0h0)) node _T_4971 = mux(_T_613, deq_vec[5][2].taken, UInt<1>(0h0)) node _T_4972 = mux(_T_614, deq_vec[6][2].taken, UInt<1>(0h0)) node _T_4973 = mux(_T_615, deq_vec[7][2].taken, UInt<1>(0h0)) node _T_4974 = or(_T_4966, _T_4967) node _T_4975 = or(_T_4974, _T_4968) node _T_4976 = or(_T_4975, _T_4969) node _T_4977 = or(_T_4976, _T_4970) node _T_4978 = or(_T_4977, _T_4971) node _T_4979 = or(_T_4978, _T_4972) node _T_4980 = or(_T_4979, _T_4973) wire _WIRE_301 : UInt<1> connect _WIRE_301, _T_4980 connect _WIRE_231.taken, _WIRE_301 node _T_4981 = mux(_T_608, deq_vec[0][2].pc_lob, UInt<1>(0h0)) node _T_4982 = mux(_T_609, deq_vec[1][2].pc_lob, UInt<1>(0h0)) node _T_4983 = mux(_T_610, deq_vec[2][2].pc_lob, UInt<1>(0h0)) node _T_4984 = mux(_T_611, deq_vec[3][2].pc_lob, UInt<1>(0h0)) node _T_4985 = mux(_T_612, deq_vec[4][2].pc_lob, UInt<1>(0h0)) node _T_4986 = mux(_T_613, deq_vec[5][2].pc_lob, UInt<1>(0h0)) node _T_4987 = mux(_T_614, deq_vec[6][2].pc_lob, UInt<1>(0h0)) node _T_4988 = mux(_T_615, deq_vec[7][2].pc_lob, UInt<1>(0h0)) node _T_4989 = or(_T_4981, _T_4982) node _T_4990 = or(_T_4989, _T_4983) node _T_4991 = or(_T_4990, _T_4984) node _T_4992 = or(_T_4991, _T_4985) node _T_4993 = or(_T_4992, _T_4986) node _T_4994 = or(_T_4993, _T_4987) node _T_4995 = or(_T_4994, _T_4988) wire _WIRE_302 : UInt<6> connect _WIRE_302, _T_4995 connect _WIRE_231.pc_lob, _WIRE_302 node _T_4996 = mux(_T_608, deq_vec[0][2].edge_inst, UInt<1>(0h0)) node _T_4997 = mux(_T_609, deq_vec[1][2].edge_inst, UInt<1>(0h0)) node _T_4998 = mux(_T_610, deq_vec[2][2].edge_inst, UInt<1>(0h0)) node _T_4999 = mux(_T_611, deq_vec[3][2].edge_inst, UInt<1>(0h0)) node _T_5000 = mux(_T_612, deq_vec[4][2].edge_inst, UInt<1>(0h0)) node _T_5001 = mux(_T_613, deq_vec[5][2].edge_inst, UInt<1>(0h0)) node _T_5002 = mux(_T_614, deq_vec[6][2].edge_inst, UInt<1>(0h0)) node _T_5003 = mux(_T_615, deq_vec[7][2].edge_inst, UInt<1>(0h0)) node _T_5004 = or(_T_4996, _T_4997) node _T_5005 = or(_T_5004, _T_4998) node _T_5006 = or(_T_5005, _T_4999) node _T_5007 = or(_T_5006, _T_5000) node _T_5008 = or(_T_5007, _T_5001) node _T_5009 = or(_T_5008, _T_5002) node _T_5010 = or(_T_5009, _T_5003) wire _WIRE_303 : UInt<1> connect _WIRE_303, _T_5010 connect _WIRE_231.edge_inst, _WIRE_303 node _T_5011 = mux(_T_608, deq_vec[0][2].ftq_idx, UInt<1>(0h0)) node _T_5012 = mux(_T_609, deq_vec[1][2].ftq_idx, UInt<1>(0h0)) node _T_5013 = mux(_T_610, deq_vec[2][2].ftq_idx, UInt<1>(0h0)) node _T_5014 = mux(_T_611, deq_vec[3][2].ftq_idx, UInt<1>(0h0)) node _T_5015 = mux(_T_612, deq_vec[4][2].ftq_idx, UInt<1>(0h0)) node _T_5016 = mux(_T_613, deq_vec[5][2].ftq_idx, UInt<1>(0h0)) node _T_5017 = mux(_T_614, deq_vec[6][2].ftq_idx, UInt<1>(0h0)) node _T_5018 = mux(_T_615, deq_vec[7][2].ftq_idx, UInt<1>(0h0)) node _T_5019 = or(_T_5011, _T_5012) node _T_5020 = or(_T_5019, _T_5013) node _T_5021 = or(_T_5020, _T_5014) node _T_5022 = or(_T_5021, _T_5015) node _T_5023 = or(_T_5022, _T_5016) node _T_5024 = or(_T_5023, _T_5017) node _T_5025 = or(_T_5024, _T_5018) wire _WIRE_304 : UInt<5> connect _WIRE_304, _T_5025 connect _WIRE_231.ftq_idx, _WIRE_304 node _T_5026 = mux(_T_608, deq_vec[0][2].is_mov, UInt<1>(0h0)) node _T_5027 = mux(_T_609, deq_vec[1][2].is_mov, UInt<1>(0h0)) node _T_5028 = mux(_T_610, deq_vec[2][2].is_mov, UInt<1>(0h0)) node _T_5029 = mux(_T_611, deq_vec[3][2].is_mov, UInt<1>(0h0)) node _T_5030 = mux(_T_612, deq_vec[4][2].is_mov, UInt<1>(0h0)) node _T_5031 = mux(_T_613, deq_vec[5][2].is_mov, UInt<1>(0h0)) node _T_5032 = mux(_T_614, deq_vec[6][2].is_mov, UInt<1>(0h0)) node _T_5033 = mux(_T_615, deq_vec[7][2].is_mov, UInt<1>(0h0)) node _T_5034 = or(_T_5026, _T_5027) node _T_5035 = or(_T_5034, _T_5028) node _T_5036 = or(_T_5035, _T_5029) node _T_5037 = or(_T_5036, _T_5030) node _T_5038 = or(_T_5037, _T_5031) node _T_5039 = or(_T_5038, _T_5032) node _T_5040 = or(_T_5039, _T_5033) wire _WIRE_305 : UInt<1> connect _WIRE_305, _T_5040 connect _WIRE_231.is_mov, _WIRE_305 node _T_5041 = mux(_T_608, deq_vec[0][2].is_rocc, UInt<1>(0h0)) node _T_5042 = mux(_T_609, deq_vec[1][2].is_rocc, UInt<1>(0h0)) node _T_5043 = mux(_T_610, deq_vec[2][2].is_rocc, UInt<1>(0h0)) node _T_5044 = mux(_T_611, deq_vec[3][2].is_rocc, UInt<1>(0h0)) node _T_5045 = mux(_T_612, deq_vec[4][2].is_rocc, UInt<1>(0h0)) node _T_5046 = mux(_T_613, deq_vec[5][2].is_rocc, UInt<1>(0h0)) node _T_5047 = mux(_T_614, deq_vec[6][2].is_rocc, UInt<1>(0h0)) node _T_5048 = mux(_T_615, deq_vec[7][2].is_rocc, UInt<1>(0h0)) node _T_5049 = or(_T_5041, _T_5042) node _T_5050 = or(_T_5049, _T_5043) node _T_5051 = or(_T_5050, _T_5044) node _T_5052 = or(_T_5051, _T_5045) node _T_5053 = or(_T_5052, _T_5046) node _T_5054 = or(_T_5053, _T_5047) node _T_5055 = or(_T_5054, _T_5048) wire _WIRE_306 : UInt<1> connect _WIRE_306, _T_5055 connect _WIRE_231.is_rocc, _WIRE_306 node _T_5056 = mux(_T_608, deq_vec[0][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5057 = mux(_T_609, deq_vec[1][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5058 = mux(_T_610, deq_vec[2][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5059 = mux(_T_611, deq_vec[3][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5060 = mux(_T_612, deq_vec[4][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5061 = mux(_T_613, deq_vec[5][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5062 = mux(_T_614, deq_vec[6][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5063 = mux(_T_615, deq_vec[7][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5064 = or(_T_5056, _T_5057) node _T_5065 = or(_T_5064, _T_5058) node _T_5066 = or(_T_5065, _T_5059) node _T_5067 = or(_T_5066, _T_5060) node _T_5068 = or(_T_5067, _T_5061) node _T_5069 = or(_T_5068, _T_5062) node _T_5070 = or(_T_5069, _T_5063) wire _WIRE_307 : UInt<1> connect _WIRE_307, _T_5070 connect _WIRE_231.is_sys_pc2epc, _WIRE_307 node _T_5071 = mux(_T_608, deq_vec[0][2].is_eret, UInt<1>(0h0)) node _T_5072 = mux(_T_609, deq_vec[1][2].is_eret, UInt<1>(0h0)) node _T_5073 = mux(_T_610, deq_vec[2][2].is_eret, UInt<1>(0h0)) node _T_5074 = mux(_T_611, deq_vec[3][2].is_eret, UInt<1>(0h0)) node _T_5075 = mux(_T_612, deq_vec[4][2].is_eret, UInt<1>(0h0)) node _T_5076 = mux(_T_613, deq_vec[5][2].is_eret, UInt<1>(0h0)) node _T_5077 = mux(_T_614, deq_vec[6][2].is_eret, UInt<1>(0h0)) node _T_5078 = mux(_T_615, deq_vec[7][2].is_eret, UInt<1>(0h0)) node _T_5079 = or(_T_5071, _T_5072) node _T_5080 = or(_T_5079, _T_5073) node _T_5081 = or(_T_5080, _T_5074) node _T_5082 = or(_T_5081, _T_5075) node _T_5083 = or(_T_5082, _T_5076) node _T_5084 = or(_T_5083, _T_5077) node _T_5085 = or(_T_5084, _T_5078) wire _WIRE_308 : UInt<1> connect _WIRE_308, _T_5085 connect _WIRE_231.is_eret, _WIRE_308 node _T_5086 = mux(_T_608, deq_vec[0][2].is_amo, UInt<1>(0h0)) node _T_5087 = mux(_T_609, deq_vec[1][2].is_amo, UInt<1>(0h0)) node _T_5088 = mux(_T_610, deq_vec[2][2].is_amo, UInt<1>(0h0)) node _T_5089 = mux(_T_611, deq_vec[3][2].is_amo, UInt<1>(0h0)) node _T_5090 = mux(_T_612, deq_vec[4][2].is_amo, UInt<1>(0h0)) node _T_5091 = mux(_T_613, deq_vec[5][2].is_amo, UInt<1>(0h0)) node _T_5092 = mux(_T_614, deq_vec[6][2].is_amo, UInt<1>(0h0)) node _T_5093 = mux(_T_615, deq_vec[7][2].is_amo, UInt<1>(0h0)) node _T_5094 = or(_T_5086, _T_5087) node _T_5095 = or(_T_5094, _T_5088) node _T_5096 = or(_T_5095, _T_5089) node _T_5097 = or(_T_5096, _T_5090) node _T_5098 = or(_T_5097, _T_5091) node _T_5099 = or(_T_5098, _T_5092) node _T_5100 = or(_T_5099, _T_5093) wire _WIRE_309 : UInt<1> connect _WIRE_309, _T_5100 connect _WIRE_231.is_amo, _WIRE_309 node _T_5101 = mux(_T_608, deq_vec[0][2].is_sfence, UInt<1>(0h0)) node _T_5102 = mux(_T_609, deq_vec[1][2].is_sfence, UInt<1>(0h0)) node _T_5103 = mux(_T_610, deq_vec[2][2].is_sfence, UInt<1>(0h0)) node _T_5104 = mux(_T_611, deq_vec[3][2].is_sfence, UInt<1>(0h0)) node _T_5105 = mux(_T_612, deq_vec[4][2].is_sfence, UInt<1>(0h0)) node _T_5106 = mux(_T_613, deq_vec[5][2].is_sfence, UInt<1>(0h0)) node _T_5107 = mux(_T_614, deq_vec[6][2].is_sfence, UInt<1>(0h0)) node _T_5108 = mux(_T_615, deq_vec[7][2].is_sfence, UInt<1>(0h0)) node _T_5109 = or(_T_5101, _T_5102) node _T_5110 = or(_T_5109, _T_5103) node _T_5111 = or(_T_5110, _T_5104) node _T_5112 = or(_T_5111, _T_5105) node _T_5113 = or(_T_5112, _T_5106) node _T_5114 = or(_T_5113, _T_5107) node _T_5115 = or(_T_5114, _T_5108) wire _WIRE_310 : UInt<1> connect _WIRE_310, _T_5115 connect _WIRE_231.is_sfence, _WIRE_310 node _T_5116 = mux(_T_608, deq_vec[0][2].is_fencei, UInt<1>(0h0)) node _T_5117 = mux(_T_609, deq_vec[1][2].is_fencei, UInt<1>(0h0)) node _T_5118 = mux(_T_610, deq_vec[2][2].is_fencei, UInt<1>(0h0)) node _T_5119 = mux(_T_611, deq_vec[3][2].is_fencei, UInt<1>(0h0)) node _T_5120 = mux(_T_612, deq_vec[4][2].is_fencei, UInt<1>(0h0)) node _T_5121 = mux(_T_613, deq_vec[5][2].is_fencei, UInt<1>(0h0)) node _T_5122 = mux(_T_614, deq_vec[6][2].is_fencei, UInt<1>(0h0)) node _T_5123 = mux(_T_615, deq_vec[7][2].is_fencei, UInt<1>(0h0)) node _T_5124 = or(_T_5116, _T_5117) node _T_5125 = or(_T_5124, _T_5118) node _T_5126 = or(_T_5125, _T_5119) node _T_5127 = or(_T_5126, _T_5120) node _T_5128 = or(_T_5127, _T_5121) node _T_5129 = or(_T_5128, _T_5122) node _T_5130 = or(_T_5129, _T_5123) wire _WIRE_311 : UInt<1> connect _WIRE_311, _T_5130 connect _WIRE_231.is_fencei, _WIRE_311 node _T_5131 = mux(_T_608, deq_vec[0][2].is_fence, UInt<1>(0h0)) node _T_5132 = mux(_T_609, deq_vec[1][2].is_fence, UInt<1>(0h0)) node _T_5133 = mux(_T_610, deq_vec[2][2].is_fence, UInt<1>(0h0)) node _T_5134 = mux(_T_611, deq_vec[3][2].is_fence, UInt<1>(0h0)) node _T_5135 = mux(_T_612, deq_vec[4][2].is_fence, UInt<1>(0h0)) node _T_5136 = mux(_T_613, deq_vec[5][2].is_fence, UInt<1>(0h0)) node _T_5137 = mux(_T_614, deq_vec[6][2].is_fence, UInt<1>(0h0)) node _T_5138 = mux(_T_615, deq_vec[7][2].is_fence, UInt<1>(0h0)) node _T_5139 = or(_T_5131, _T_5132) node _T_5140 = or(_T_5139, _T_5133) node _T_5141 = or(_T_5140, _T_5134) node _T_5142 = or(_T_5141, _T_5135) node _T_5143 = or(_T_5142, _T_5136) node _T_5144 = or(_T_5143, _T_5137) node _T_5145 = or(_T_5144, _T_5138) wire _WIRE_312 : UInt<1> connect _WIRE_312, _T_5145 connect _WIRE_231.is_fence, _WIRE_312 node _T_5146 = mux(_T_608, deq_vec[0][2].is_sfb, UInt<1>(0h0)) node _T_5147 = mux(_T_609, deq_vec[1][2].is_sfb, UInt<1>(0h0)) node _T_5148 = mux(_T_610, deq_vec[2][2].is_sfb, UInt<1>(0h0)) node _T_5149 = mux(_T_611, deq_vec[3][2].is_sfb, UInt<1>(0h0)) node _T_5150 = mux(_T_612, deq_vec[4][2].is_sfb, UInt<1>(0h0)) node _T_5151 = mux(_T_613, deq_vec[5][2].is_sfb, UInt<1>(0h0)) node _T_5152 = mux(_T_614, deq_vec[6][2].is_sfb, UInt<1>(0h0)) node _T_5153 = mux(_T_615, deq_vec[7][2].is_sfb, UInt<1>(0h0)) node _T_5154 = or(_T_5146, _T_5147) node _T_5155 = or(_T_5154, _T_5148) node _T_5156 = or(_T_5155, _T_5149) node _T_5157 = or(_T_5156, _T_5150) node _T_5158 = or(_T_5157, _T_5151) node _T_5159 = or(_T_5158, _T_5152) node _T_5160 = or(_T_5159, _T_5153) wire _WIRE_313 : UInt<1> connect _WIRE_313, _T_5160 connect _WIRE_231.is_sfb, _WIRE_313 node _T_5161 = mux(_T_608, deq_vec[0][2].br_type, UInt<1>(0h0)) node _T_5162 = mux(_T_609, deq_vec[1][2].br_type, UInt<1>(0h0)) node _T_5163 = mux(_T_610, deq_vec[2][2].br_type, UInt<1>(0h0)) node _T_5164 = mux(_T_611, deq_vec[3][2].br_type, UInt<1>(0h0)) node _T_5165 = mux(_T_612, deq_vec[4][2].br_type, UInt<1>(0h0)) node _T_5166 = mux(_T_613, deq_vec[5][2].br_type, UInt<1>(0h0)) node _T_5167 = mux(_T_614, deq_vec[6][2].br_type, UInt<1>(0h0)) node _T_5168 = mux(_T_615, deq_vec[7][2].br_type, UInt<1>(0h0)) node _T_5169 = or(_T_5161, _T_5162) node _T_5170 = or(_T_5169, _T_5163) node _T_5171 = or(_T_5170, _T_5164) node _T_5172 = or(_T_5171, _T_5165) node _T_5173 = or(_T_5172, _T_5166) node _T_5174 = or(_T_5173, _T_5167) node _T_5175 = or(_T_5174, _T_5168) wire _WIRE_314 : UInt<4> connect _WIRE_314, _T_5175 connect _WIRE_231.br_type, _WIRE_314 node _T_5176 = mux(_T_608, deq_vec[0][2].br_tag, UInt<1>(0h0)) node _T_5177 = mux(_T_609, deq_vec[1][2].br_tag, UInt<1>(0h0)) node _T_5178 = mux(_T_610, deq_vec[2][2].br_tag, UInt<1>(0h0)) node _T_5179 = mux(_T_611, deq_vec[3][2].br_tag, UInt<1>(0h0)) node _T_5180 = mux(_T_612, deq_vec[4][2].br_tag, UInt<1>(0h0)) node _T_5181 = mux(_T_613, deq_vec[5][2].br_tag, UInt<1>(0h0)) node _T_5182 = mux(_T_614, deq_vec[6][2].br_tag, UInt<1>(0h0)) node _T_5183 = mux(_T_615, deq_vec[7][2].br_tag, UInt<1>(0h0)) node _T_5184 = or(_T_5176, _T_5177) node _T_5185 = or(_T_5184, _T_5178) node _T_5186 = or(_T_5185, _T_5179) node _T_5187 = or(_T_5186, _T_5180) node _T_5188 = or(_T_5187, _T_5181) node _T_5189 = or(_T_5188, _T_5182) node _T_5190 = or(_T_5189, _T_5183) wire _WIRE_315 : UInt<4> connect _WIRE_315, _T_5190 connect _WIRE_231.br_tag, _WIRE_315 node _T_5191 = mux(_T_608, deq_vec[0][2].br_mask, UInt<1>(0h0)) node _T_5192 = mux(_T_609, deq_vec[1][2].br_mask, UInt<1>(0h0)) node _T_5193 = mux(_T_610, deq_vec[2][2].br_mask, UInt<1>(0h0)) node _T_5194 = mux(_T_611, deq_vec[3][2].br_mask, UInt<1>(0h0)) node _T_5195 = mux(_T_612, deq_vec[4][2].br_mask, UInt<1>(0h0)) node _T_5196 = mux(_T_613, deq_vec[5][2].br_mask, UInt<1>(0h0)) node _T_5197 = mux(_T_614, deq_vec[6][2].br_mask, UInt<1>(0h0)) node _T_5198 = mux(_T_615, deq_vec[7][2].br_mask, UInt<1>(0h0)) node _T_5199 = or(_T_5191, _T_5192) node _T_5200 = or(_T_5199, _T_5193) node _T_5201 = or(_T_5200, _T_5194) node _T_5202 = or(_T_5201, _T_5195) node _T_5203 = or(_T_5202, _T_5196) node _T_5204 = or(_T_5203, _T_5197) node _T_5205 = or(_T_5204, _T_5198) wire _WIRE_316 : UInt<16> connect _WIRE_316, _T_5205 connect _WIRE_231.br_mask, _WIRE_316 node _T_5206 = mux(_T_608, deq_vec[0][2].dis_col_sel, UInt<1>(0h0)) node _T_5207 = mux(_T_609, deq_vec[1][2].dis_col_sel, UInt<1>(0h0)) node _T_5208 = mux(_T_610, deq_vec[2][2].dis_col_sel, UInt<1>(0h0)) node _T_5209 = mux(_T_611, deq_vec[3][2].dis_col_sel, UInt<1>(0h0)) node _T_5210 = mux(_T_612, deq_vec[4][2].dis_col_sel, UInt<1>(0h0)) node _T_5211 = mux(_T_613, deq_vec[5][2].dis_col_sel, UInt<1>(0h0)) node _T_5212 = mux(_T_614, deq_vec[6][2].dis_col_sel, UInt<1>(0h0)) node _T_5213 = mux(_T_615, deq_vec[7][2].dis_col_sel, UInt<1>(0h0)) node _T_5214 = or(_T_5206, _T_5207) node _T_5215 = or(_T_5214, _T_5208) node _T_5216 = or(_T_5215, _T_5209) node _T_5217 = or(_T_5216, _T_5210) node _T_5218 = or(_T_5217, _T_5211) node _T_5219 = or(_T_5218, _T_5212) node _T_5220 = or(_T_5219, _T_5213) wire _WIRE_317 : UInt<3> connect _WIRE_317, _T_5220 connect _WIRE_231.dis_col_sel, _WIRE_317 node _T_5221 = mux(_T_608, deq_vec[0][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5222 = mux(_T_609, deq_vec[1][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5223 = mux(_T_610, deq_vec[2][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5224 = mux(_T_611, deq_vec[3][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5225 = mux(_T_612, deq_vec[4][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5226 = mux(_T_613, deq_vec[5][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5227 = mux(_T_614, deq_vec[6][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5228 = mux(_T_615, deq_vec[7][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5229 = or(_T_5221, _T_5222) node _T_5230 = or(_T_5229, _T_5223) node _T_5231 = or(_T_5230, _T_5224) node _T_5232 = or(_T_5231, _T_5225) node _T_5233 = or(_T_5232, _T_5226) node _T_5234 = or(_T_5233, _T_5227) node _T_5235 = or(_T_5234, _T_5228) wire _WIRE_318 : UInt<1> connect _WIRE_318, _T_5235 connect _WIRE_231.iw_p3_bypass_hint, _WIRE_318 node _T_5236 = mux(_T_608, deq_vec[0][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5237 = mux(_T_609, deq_vec[1][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5238 = mux(_T_610, deq_vec[2][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5239 = mux(_T_611, deq_vec[3][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5240 = mux(_T_612, deq_vec[4][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5241 = mux(_T_613, deq_vec[5][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5242 = mux(_T_614, deq_vec[6][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5243 = mux(_T_615, deq_vec[7][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5244 = or(_T_5236, _T_5237) node _T_5245 = or(_T_5244, _T_5238) node _T_5246 = or(_T_5245, _T_5239) node _T_5247 = or(_T_5246, _T_5240) node _T_5248 = or(_T_5247, _T_5241) node _T_5249 = or(_T_5248, _T_5242) node _T_5250 = or(_T_5249, _T_5243) wire _WIRE_319 : UInt<1> connect _WIRE_319, _T_5250 connect _WIRE_231.iw_p2_bypass_hint, _WIRE_319 node _T_5251 = mux(_T_608, deq_vec[0][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5252 = mux(_T_609, deq_vec[1][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5253 = mux(_T_610, deq_vec[2][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5254 = mux(_T_611, deq_vec[3][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5255 = mux(_T_612, deq_vec[4][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5256 = mux(_T_613, deq_vec[5][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5257 = mux(_T_614, deq_vec[6][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5258 = mux(_T_615, deq_vec[7][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5259 = or(_T_5251, _T_5252) node _T_5260 = or(_T_5259, _T_5253) node _T_5261 = or(_T_5260, _T_5254) node _T_5262 = or(_T_5261, _T_5255) node _T_5263 = or(_T_5262, _T_5256) node _T_5264 = or(_T_5263, _T_5257) node _T_5265 = or(_T_5264, _T_5258) wire _WIRE_320 : UInt<1> connect _WIRE_320, _T_5265 connect _WIRE_231.iw_p1_bypass_hint, _WIRE_320 node _T_5266 = mux(_T_608, deq_vec[0][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5267 = mux(_T_609, deq_vec[1][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5268 = mux(_T_610, deq_vec[2][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5269 = mux(_T_611, deq_vec[3][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5270 = mux(_T_612, deq_vec[4][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5271 = mux(_T_613, deq_vec[5][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5272 = mux(_T_614, deq_vec[6][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5273 = mux(_T_615, deq_vec[7][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5274 = or(_T_5266, _T_5267) node _T_5275 = or(_T_5274, _T_5268) node _T_5276 = or(_T_5275, _T_5269) node _T_5277 = or(_T_5276, _T_5270) node _T_5278 = or(_T_5277, _T_5271) node _T_5279 = or(_T_5278, _T_5272) node _T_5280 = or(_T_5279, _T_5273) wire _WIRE_321 : UInt<3> connect _WIRE_321, _T_5280 connect _WIRE_231.iw_p2_speculative_child, _WIRE_321 node _T_5281 = mux(_T_608, deq_vec[0][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5282 = mux(_T_609, deq_vec[1][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5283 = mux(_T_610, deq_vec[2][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5284 = mux(_T_611, deq_vec[3][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5285 = mux(_T_612, deq_vec[4][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5286 = mux(_T_613, deq_vec[5][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5287 = mux(_T_614, deq_vec[6][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5288 = mux(_T_615, deq_vec[7][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5289 = or(_T_5281, _T_5282) node _T_5290 = or(_T_5289, _T_5283) node _T_5291 = or(_T_5290, _T_5284) node _T_5292 = or(_T_5291, _T_5285) node _T_5293 = or(_T_5292, _T_5286) node _T_5294 = or(_T_5293, _T_5287) node _T_5295 = or(_T_5294, _T_5288) wire _WIRE_322 : UInt<3> connect _WIRE_322, _T_5295 connect _WIRE_231.iw_p1_speculative_child, _WIRE_322 node _T_5296 = mux(_T_608, deq_vec[0][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5297 = mux(_T_609, deq_vec[1][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5298 = mux(_T_610, deq_vec[2][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5299 = mux(_T_611, deq_vec[3][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5300 = mux(_T_612, deq_vec[4][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5301 = mux(_T_613, deq_vec[5][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5302 = mux(_T_614, deq_vec[6][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5303 = mux(_T_615, deq_vec[7][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5304 = or(_T_5296, _T_5297) node _T_5305 = or(_T_5304, _T_5298) node _T_5306 = or(_T_5305, _T_5299) node _T_5307 = or(_T_5306, _T_5300) node _T_5308 = or(_T_5307, _T_5301) node _T_5309 = or(_T_5308, _T_5302) node _T_5310 = or(_T_5309, _T_5303) wire _WIRE_323 : UInt<1> connect _WIRE_323, _T_5310 connect _WIRE_231.iw_issued_partial_dgen, _WIRE_323 node _T_5311 = mux(_T_608, deq_vec[0][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5312 = mux(_T_609, deq_vec[1][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5313 = mux(_T_610, deq_vec[2][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5314 = mux(_T_611, deq_vec[3][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5315 = mux(_T_612, deq_vec[4][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5316 = mux(_T_613, deq_vec[5][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5317 = mux(_T_614, deq_vec[6][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5318 = mux(_T_615, deq_vec[7][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5319 = or(_T_5311, _T_5312) node _T_5320 = or(_T_5319, _T_5313) node _T_5321 = or(_T_5320, _T_5314) node _T_5322 = or(_T_5321, _T_5315) node _T_5323 = or(_T_5322, _T_5316) node _T_5324 = or(_T_5323, _T_5317) node _T_5325 = or(_T_5324, _T_5318) wire _WIRE_324 : UInt<1> connect _WIRE_324, _T_5325 connect _WIRE_231.iw_issued_partial_agen, _WIRE_324 node _T_5326 = mux(_T_608, deq_vec[0][2].iw_issued, UInt<1>(0h0)) node _T_5327 = mux(_T_609, deq_vec[1][2].iw_issued, UInt<1>(0h0)) node _T_5328 = mux(_T_610, deq_vec[2][2].iw_issued, UInt<1>(0h0)) node _T_5329 = mux(_T_611, deq_vec[3][2].iw_issued, UInt<1>(0h0)) node _T_5330 = mux(_T_612, deq_vec[4][2].iw_issued, UInt<1>(0h0)) node _T_5331 = mux(_T_613, deq_vec[5][2].iw_issued, UInt<1>(0h0)) node _T_5332 = mux(_T_614, deq_vec[6][2].iw_issued, UInt<1>(0h0)) node _T_5333 = mux(_T_615, deq_vec[7][2].iw_issued, UInt<1>(0h0)) node _T_5334 = or(_T_5326, _T_5327) node _T_5335 = or(_T_5334, _T_5328) node _T_5336 = or(_T_5335, _T_5329) node _T_5337 = or(_T_5336, _T_5330) node _T_5338 = or(_T_5337, _T_5331) node _T_5339 = or(_T_5338, _T_5332) node _T_5340 = or(_T_5339, _T_5333) wire _WIRE_325 : UInt<1> connect _WIRE_325, _T_5340 connect _WIRE_231.iw_issued, _WIRE_325 wire _WIRE_326 : UInt<1>[10] node _T_5341 = mux(_T_608, deq_vec[0][2].fu_code[0], UInt<1>(0h0)) node _T_5342 = mux(_T_609, deq_vec[1][2].fu_code[0], UInt<1>(0h0)) node _T_5343 = mux(_T_610, deq_vec[2][2].fu_code[0], UInt<1>(0h0)) node _T_5344 = mux(_T_611, deq_vec[3][2].fu_code[0], UInt<1>(0h0)) node _T_5345 = mux(_T_612, deq_vec[4][2].fu_code[0], UInt<1>(0h0)) node _T_5346 = mux(_T_613, deq_vec[5][2].fu_code[0], UInt<1>(0h0)) node _T_5347 = mux(_T_614, deq_vec[6][2].fu_code[0], UInt<1>(0h0)) node _T_5348 = mux(_T_615, deq_vec[7][2].fu_code[0], UInt<1>(0h0)) node _T_5349 = or(_T_5341, _T_5342) node _T_5350 = or(_T_5349, _T_5343) node _T_5351 = or(_T_5350, _T_5344) node _T_5352 = or(_T_5351, _T_5345) node _T_5353 = or(_T_5352, _T_5346) node _T_5354 = or(_T_5353, _T_5347) node _T_5355 = or(_T_5354, _T_5348) wire _WIRE_327 : UInt<1> connect _WIRE_327, _T_5355 connect _WIRE_326[0], _WIRE_327 node _T_5356 = mux(_T_608, deq_vec[0][2].fu_code[1], UInt<1>(0h0)) node _T_5357 = mux(_T_609, deq_vec[1][2].fu_code[1], UInt<1>(0h0)) node _T_5358 = mux(_T_610, deq_vec[2][2].fu_code[1], UInt<1>(0h0)) node _T_5359 = mux(_T_611, deq_vec[3][2].fu_code[1], UInt<1>(0h0)) node _T_5360 = mux(_T_612, deq_vec[4][2].fu_code[1], UInt<1>(0h0)) node _T_5361 = mux(_T_613, deq_vec[5][2].fu_code[1], UInt<1>(0h0)) node _T_5362 = mux(_T_614, deq_vec[6][2].fu_code[1], UInt<1>(0h0)) node _T_5363 = mux(_T_615, deq_vec[7][2].fu_code[1], UInt<1>(0h0)) node _T_5364 = or(_T_5356, _T_5357) node _T_5365 = or(_T_5364, _T_5358) node _T_5366 = or(_T_5365, _T_5359) node _T_5367 = or(_T_5366, _T_5360) node _T_5368 = or(_T_5367, _T_5361) node _T_5369 = or(_T_5368, _T_5362) node _T_5370 = or(_T_5369, _T_5363) wire _WIRE_328 : UInt<1> connect _WIRE_328, _T_5370 connect _WIRE_326[1], _WIRE_328 node _T_5371 = mux(_T_608, deq_vec[0][2].fu_code[2], UInt<1>(0h0)) node _T_5372 = mux(_T_609, deq_vec[1][2].fu_code[2], UInt<1>(0h0)) node _T_5373 = mux(_T_610, deq_vec[2][2].fu_code[2], UInt<1>(0h0)) node _T_5374 = mux(_T_611, deq_vec[3][2].fu_code[2], UInt<1>(0h0)) node _T_5375 = mux(_T_612, deq_vec[4][2].fu_code[2], UInt<1>(0h0)) node _T_5376 = mux(_T_613, deq_vec[5][2].fu_code[2], UInt<1>(0h0)) node _T_5377 = mux(_T_614, deq_vec[6][2].fu_code[2], UInt<1>(0h0)) node _T_5378 = mux(_T_615, deq_vec[7][2].fu_code[2], UInt<1>(0h0)) node _T_5379 = or(_T_5371, _T_5372) node _T_5380 = or(_T_5379, _T_5373) node _T_5381 = or(_T_5380, _T_5374) node _T_5382 = or(_T_5381, _T_5375) node _T_5383 = or(_T_5382, _T_5376) node _T_5384 = or(_T_5383, _T_5377) node _T_5385 = or(_T_5384, _T_5378) wire _WIRE_329 : UInt<1> connect _WIRE_329, _T_5385 connect _WIRE_326[2], _WIRE_329 node _T_5386 = mux(_T_608, deq_vec[0][2].fu_code[3], UInt<1>(0h0)) node _T_5387 = mux(_T_609, deq_vec[1][2].fu_code[3], UInt<1>(0h0)) node _T_5388 = mux(_T_610, deq_vec[2][2].fu_code[3], UInt<1>(0h0)) node _T_5389 = mux(_T_611, deq_vec[3][2].fu_code[3], UInt<1>(0h0)) node _T_5390 = mux(_T_612, deq_vec[4][2].fu_code[3], UInt<1>(0h0)) node _T_5391 = mux(_T_613, deq_vec[5][2].fu_code[3], UInt<1>(0h0)) node _T_5392 = mux(_T_614, deq_vec[6][2].fu_code[3], UInt<1>(0h0)) node _T_5393 = mux(_T_615, deq_vec[7][2].fu_code[3], UInt<1>(0h0)) node _T_5394 = or(_T_5386, _T_5387) node _T_5395 = or(_T_5394, _T_5388) node _T_5396 = or(_T_5395, _T_5389) node _T_5397 = or(_T_5396, _T_5390) node _T_5398 = or(_T_5397, _T_5391) node _T_5399 = or(_T_5398, _T_5392) node _T_5400 = or(_T_5399, _T_5393) wire _WIRE_330 : UInt<1> connect _WIRE_330, _T_5400 connect _WIRE_326[3], _WIRE_330 node _T_5401 = mux(_T_608, deq_vec[0][2].fu_code[4], UInt<1>(0h0)) node _T_5402 = mux(_T_609, deq_vec[1][2].fu_code[4], UInt<1>(0h0)) node _T_5403 = mux(_T_610, deq_vec[2][2].fu_code[4], UInt<1>(0h0)) node _T_5404 = mux(_T_611, deq_vec[3][2].fu_code[4], UInt<1>(0h0)) node _T_5405 = mux(_T_612, deq_vec[4][2].fu_code[4], UInt<1>(0h0)) node _T_5406 = mux(_T_613, deq_vec[5][2].fu_code[4], UInt<1>(0h0)) node _T_5407 = mux(_T_614, deq_vec[6][2].fu_code[4], UInt<1>(0h0)) node _T_5408 = mux(_T_615, deq_vec[7][2].fu_code[4], UInt<1>(0h0)) node _T_5409 = or(_T_5401, _T_5402) node _T_5410 = or(_T_5409, _T_5403) node _T_5411 = or(_T_5410, _T_5404) node _T_5412 = or(_T_5411, _T_5405) node _T_5413 = or(_T_5412, _T_5406) node _T_5414 = or(_T_5413, _T_5407) node _T_5415 = or(_T_5414, _T_5408) wire _WIRE_331 : UInt<1> connect _WIRE_331, _T_5415 connect _WIRE_326[4], _WIRE_331 node _T_5416 = mux(_T_608, deq_vec[0][2].fu_code[5], UInt<1>(0h0)) node _T_5417 = mux(_T_609, deq_vec[1][2].fu_code[5], UInt<1>(0h0)) node _T_5418 = mux(_T_610, deq_vec[2][2].fu_code[5], UInt<1>(0h0)) node _T_5419 = mux(_T_611, deq_vec[3][2].fu_code[5], UInt<1>(0h0)) node _T_5420 = mux(_T_612, deq_vec[4][2].fu_code[5], UInt<1>(0h0)) node _T_5421 = mux(_T_613, deq_vec[5][2].fu_code[5], UInt<1>(0h0)) node _T_5422 = mux(_T_614, deq_vec[6][2].fu_code[5], UInt<1>(0h0)) node _T_5423 = mux(_T_615, deq_vec[7][2].fu_code[5], UInt<1>(0h0)) node _T_5424 = or(_T_5416, _T_5417) node _T_5425 = or(_T_5424, _T_5418) node _T_5426 = or(_T_5425, _T_5419) node _T_5427 = or(_T_5426, _T_5420) node _T_5428 = or(_T_5427, _T_5421) node _T_5429 = or(_T_5428, _T_5422) node _T_5430 = or(_T_5429, _T_5423) wire _WIRE_332 : UInt<1> connect _WIRE_332, _T_5430 connect _WIRE_326[5], _WIRE_332 node _T_5431 = mux(_T_608, deq_vec[0][2].fu_code[6], UInt<1>(0h0)) node _T_5432 = mux(_T_609, deq_vec[1][2].fu_code[6], UInt<1>(0h0)) node _T_5433 = mux(_T_610, deq_vec[2][2].fu_code[6], UInt<1>(0h0)) node _T_5434 = mux(_T_611, deq_vec[3][2].fu_code[6], UInt<1>(0h0)) node _T_5435 = mux(_T_612, deq_vec[4][2].fu_code[6], UInt<1>(0h0)) node _T_5436 = mux(_T_613, deq_vec[5][2].fu_code[6], UInt<1>(0h0)) node _T_5437 = mux(_T_614, deq_vec[6][2].fu_code[6], UInt<1>(0h0)) node _T_5438 = mux(_T_615, deq_vec[7][2].fu_code[6], UInt<1>(0h0)) node _T_5439 = or(_T_5431, _T_5432) node _T_5440 = or(_T_5439, _T_5433) node _T_5441 = or(_T_5440, _T_5434) node _T_5442 = or(_T_5441, _T_5435) node _T_5443 = or(_T_5442, _T_5436) node _T_5444 = or(_T_5443, _T_5437) node _T_5445 = or(_T_5444, _T_5438) wire _WIRE_333 : UInt<1> connect _WIRE_333, _T_5445 connect _WIRE_326[6], _WIRE_333 node _T_5446 = mux(_T_608, deq_vec[0][2].fu_code[7], UInt<1>(0h0)) node _T_5447 = mux(_T_609, deq_vec[1][2].fu_code[7], UInt<1>(0h0)) node _T_5448 = mux(_T_610, deq_vec[2][2].fu_code[7], UInt<1>(0h0)) node _T_5449 = mux(_T_611, deq_vec[3][2].fu_code[7], UInt<1>(0h0)) node _T_5450 = mux(_T_612, deq_vec[4][2].fu_code[7], UInt<1>(0h0)) node _T_5451 = mux(_T_613, deq_vec[5][2].fu_code[7], UInt<1>(0h0)) node _T_5452 = mux(_T_614, deq_vec[6][2].fu_code[7], UInt<1>(0h0)) node _T_5453 = mux(_T_615, deq_vec[7][2].fu_code[7], UInt<1>(0h0)) node _T_5454 = or(_T_5446, _T_5447) node _T_5455 = or(_T_5454, _T_5448) node _T_5456 = or(_T_5455, _T_5449) node _T_5457 = or(_T_5456, _T_5450) node _T_5458 = or(_T_5457, _T_5451) node _T_5459 = or(_T_5458, _T_5452) node _T_5460 = or(_T_5459, _T_5453) wire _WIRE_334 : UInt<1> connect _WIRE_334, _T_5460 connect _WIRE_326[7], _WIRE_334 node _T_5461 = mux(_T_608, deq_vec[0][2].fu_code[8], UInt<1>(0h0)) node _T_5462 = mux(_T_609, deq_vec[1][2].fu_code[8], UInt<1>(0h0)) node _T_5463 = mux(_T_610, deq_vec[2][2].fu_code[8], UInt<1>(0h0)) node _T_5464 = mux(_T_611, deq_vec[3][2].fu_code[8], UInt<1>(0h0)) node _T_5465 = mux(_T_612, deq_vec[4][2].fu_code[8], UInt<1>(0h0)) node _T_5466 = mux(_T_613, deq_vec[5][2].fu_code[8], UInt<1>(0h0)) node _T_5467 = mux(_T_614, deq_vec[6][2].fu_code[8], UInt<1>(0h0)) node _T_5468 = mux(_T_615, deq_vec[7][2].fu_code[8], UInt<1>(0h0)) node _T_5469 = or(_T_5461, _T_5462) node _T_5470 = or(_T_5469, _T_5463) node _T_5471 = or(_T_5470, _T_5464) node _T_5472 = or(_T_5471, _T_5465) node _T_5473 = or(_T_5472, _T_5466) node _T_5474 = or(_T_5473, _T_5467) node _T_5475 = or(_T_5474, _T_5468) wire _WIRE_335 : UInt<1> connect _WIRE_335, _T_5475 connect _WIRE_326[8], _WIRE_335 node _T_5476 = mux(_T_608, deq_vec[0][2].fu_code[9], UInt<1>(0h0)) node _T_5477 = mux(_T_609, deq_vec[1][2].fu_code[9], UInt<1>(0h0)) node _T_5478 = mux(_T_610, deq_vec[2][2].fu_code[9], UInt<1>(0h0)) node _T_5479 = mux(_T_611, deq_vec[3][2].fu_code[9], UInt<1>(0h0)) node _T_5480 = mux(_T_612, deq_vec[4][2].fu_code[9], UInt<1>(0h0)) node _T_5481 = mux(_T_613, deq_vec[5][2].fu_code[9], UInt<1>(0h0)) node _T_5482 = mux(_T_614, deq_vec[6][2].fu_code[9], UInt<1>(0h0)) node _T_5483 = mux(_T_615, deq_vec[7][2].fu_code[9], UInt<1>(0h0)) node _T_5484 = or(_T_5476, _T_5477) node _T_5485 = or(_T_5484, _T_5478) node _T_5486 = or(_T_5485, _T_5479) node _T_5487 = or(_T_5486, _T_5480) node _T_5488 = or(_T_5487, _T_5481) node _T_5489 = or(_T_5488, _T_5482) node _T_5490 = or(_T_5489, _T_5483) wire _WIRE_336 : UInt<1> connect _WIRE_336, _T_5490 connect _WIRE_326[9], _WIRE_336 connect _WIRE_231.fu_code, _WIRE_326 wire _WIRE_337 : UInt<1>[4] node _T_5491 = mux(_T_608, deq_vec[0][2].iq_type[0], UInt<1>(0h0)) node _T_5492 = mux(_T_609, deq_vec[1][2].iq_type[0], UInt<1>(0h0)) node _T_5493 = mux(_T_610, deq_vec[2][2].iq_type[0], UInt<1>(0h0)) node _T_5494 = mux(_T_611, deq_vec[3][2].iq_type[0], UInt<1>(0h0)) node _T_5495 = mux(_T_612, deq_vec[4][2].iq_type[0], UInt<1>(0h0)) node _T_5496 = mux(_T_613, deq_vec[5][2].iq_type[0], UInt<1>(0h0)) node _T_5497 = mux(_T_614, deq_vec[6][2].iq_type[0], UInt<1>(0h0)) node _T_5498 = mux(_T_615, deq_vec[7][2].iq_type[0], UInt<1>(0h0)) node _T_5499 = or(_T_5491, _T_5492) node _T_5500 = or(_T_5499, _T_5493) node _T_5501 = or(_T_5500, _T_5494) node _T_5502 = or(_T_5501, _T_5495) node _T_5503 = or(_T_5502, _T_5496) node _T_5504 = or(_T_5503, _T_5497) node _T_5505 = or(_T_5504, _T_5498) wire _WIRE_338 : UInt<1> connect _WIRE_338, _T_5505 connect _WIRE_337[0], _WIRE_338 node _T_5506 = mux(_T_608, deq_vec[0][2].iq_type[1], UInt<1>(0h0)) node _T_5507 = mux(_T_609, deq_vec[1][2].iq_type[1], UInt<1>(0h0)) node _T_5508 = mux(_T_610, deq_vec[2][2].iq_type[1], UInt<1>(0h0)) node _T_5509 = mux(_T_611, deq_vec[3][2].iq_type[1], UInt<1>(0h0)) node _T_5510 = mux(_T_612, deq_vec[4][2].iq_type[1], UInt<1>(0h0)) node _T_5511 = mux(_T_613, deq_vec[5][2].iq_type[1], UInt<1>(0h0)) node _T_5512 = mux(_T_614, deq_vec[6][2].iq_type[1], UInt<1>(0h0)) node _T_5513 = mux(_T_615, deq_vec[7][2].iq_type[1], UInt<1>(0h0)) node _T_5514 = or(_T_5506, _T_5507) node _T_5515 = or(_T_5514, _T_5508) node _T_5516 = or(_T_5515, _T_5509) node _T_5517 = or(_T_5516, _T_5510) node _T_5518 = or(_T_5517, _T_5511) node _T_5519 = or(_T_5518, _T_5512) node _T_5520 = or(_T_5519, _T_5513) wire _WIRE_339 : UInt<1> connect _WIRE_339, _T_5520 connect _WIRE_337[1], _WIRE_339 node _T_5521 = mux(_T_608, deq_vec[0][2].iq_type[2], UInt<1>(0h0)) node _T_5522 = mux(_T_609, deq_vec[1][2].iq_type[2], UInt<1>(0h0)) node _T_5523 = mux(_T_610, deq_vec[2][2].iq_type[2], UInt<1>(0h0)) node _T_5524 = mux(_T_611, deq_vec[3][2].iq_type[2], UInt<1>(0h0)) node _T_5525 = mux(_T_612, deq_vec[4][2].iq_type[2], UInt<1>(0h0)) node _T_5526 = mux(_T_613, deq_vec[5][2].iq_type[2], UInt<1>(0h0)) node _T_5527 = mux(_T_614, deq_vec[6][2].iq_type[2], UInt<1>(0h0)) node _T_5528 = mux(_T_615, deq_vec[7][2].iq_type[2], UInt<1>(0h0)) node _T_5529 = or(_T_5521, _T_5522) node _T_5530 = or(_T_5529, _T_5523) node _T_5531 = or(_T_5530, _T_5524) node _T_5532 = or(_T_5531, _T_5525) node _T_5533 = or(_T_5532, _T_5526) node _T_5534 = or(_T_5533, _T_5527) node _T_5535 = or(_T_5534, _T_5528) wire _WIRE_340 : UInt<1> connect _WIRE_340, _T_5535 connect _WIRE_337[2], _WIRE_340 node _T_5536 = mux(_T_608, deq_vec[0][2].iq_type[3], UInt<1>(0h0)) node _T_5537 = mux(_T_609, deq_vec[1][2].iq_type[3], UInt<1>(0h0)) node _T_5538 = mux(_T_610, deq_vec[2][2].iq_type[3], UInt<1>(0h0)) node _T_5539 = mux(_T_611, deq_vec[3][2].iq_type[3], UInt<1>(0h0)) node _T_5540 = mux(_T_612, deq_vec[4][2].iq_type[3], UInt<1>(0h0)) node _T_5541 = mux(_T_613, deq_vec[5][2].iq_type[3], UInt<1>(0h0)) node _T_5542 = mux(_T_614, deq_vec[6][2].iq_type[3], UInt<1>(0h0)) node _T_5543 = mux(_T_615, deq_vec[7][2].iq_type[3], UInt<1>(0h0)) node _T_5544 = or(_T_5536, _T_5537) node _T_5545 = or(_T_5544, _T_5538) node _T_5546 = or(_T_5545, _T_5539) node _T_5547 = or(_T_5546, _T_5540) node _T_5548 = or(_T_5547, _T_5541) node _T_5549 = or(_T_5548, _T_5542) node _T_5550 = or(_T_5549, _T_5543) wire _WIRE_341 : UInt<1> connect _WIRE_341, _T_5550 connect _WIRE_337[3], _WIRE_341 connect _WIRE_231.iq_type, _WIRE_337 node _T_5551 = mux(_T_608, deq_vec[0][2].debug_pc, UInt<1>(0h0)) node _T_5552 = mux(_T_609, deq_vec[1][2].debug_pc, UInt<1>(0h0)) node _T_5553 = mux(_T_610, deq_vec[2][2].debug_pc, UInt<1>(0h0)) node _T_5554 = mux(_T_611, deq_vec[3][2].debug_pc, UInt<1>(0h0)) node _T_5555 = mux(_T_612, deq_vec[4][2].debug_pc, UInt<1>(0h0)) node _T_5556 = mux(_T_613, deq_vec[5][2].debug_pc, UInt<1>(0h0)) node _T_5557 = mux(_T_614, deq_vec[6][2].debug_pc, UInt<1>(0h0)) node _T_5558 = mux(_T_615, deq_vec[7][2].debug_pc, UInt<1>(0h0)) node _T_5559 = or(_T_5551, _T_5552) node _T_5560 = or(_T_5559, _T_5553) node _T_5561 = or(_T_5560, _T_5554) node _T_5562 = or(_T_5561, _T_5555) node _T_5563 = or(_T_5562, _T_5556) node _T_5564 = or(_T_5563, _T_5557) node _T_5565 = or(_T_5564, _T_5558) wire _WIRE_342 : UInt<40> connect _WIRE_342, _T_5565 connect _WIRE_231.debug_pc, _WIRE_342 node _T_5566 = mux(_T_608, deq_vec[0][2].is_rvc, UInt<1>(0h0)) node _T_5567 = mux(_T_609, deq_vec[1][2].is_rvc, UInt<1>(0h0)) node _T_5568 = mux(_T_610, deq_vec[2][2].is_rvc, UInt<1>(0h0)) node _T_5569 = mux(_T_611, deq_vec[3][2].is_rvc, UInt<1>(0h0)) node _T_5570 = mux(_T_612, deq_vec[4][2].is_rvc, UInt<1>(0h0)) node _T_5571 = mux(_T_613, deq_vec[5][2].is_rvc, UInt<1>(0h0)) node _T_5572 = mux(_T_614, deq_vec[6][2].is_rvc, UInt<1>(0h0)) node _T_5573 = mux(_T_615, deq_vec[7][2].is_rvc, UInt<1>(0h0)) node _T_5574 = or(_T_5566, _T_5567) node _T_5575 = or(_T_5574, _T_5568) node _T_5576 = or(_T_5575, _T_5569) node _T_5577 = or(_T_5576, _T_5570) node _T_5578 = or(_T_5577, _T_5571) node _T_5579 = or(_T_5578, _T_5572) node _T_5580 = or(_T_5579, _T_5573) wire _WIRE_343 : UInt<1> connect _WIRE_343, _T_5580 connect _WIRE_231.is_rvc, _WIRE_343 node _T_5581 = mux(_T_608, deq_vec[0][2].debug_inst, UInt<1>(0h0)) node _T_5582 = mux(_T_609, deq_vec[1][2].debug_inst, UInt<1>(0h0)) node _T_5583 = mux(_T_610, deq_vec[2][2].debug_inst, UInt<1>(0h0)) node _T_5584 = mux(_T_611, deq_vec[3][2].debug_inst, UInt<1>(0h0)) node _T_5585 = mux(_T_612, deq_vec[4][2].debug_inst, UInt<1>(0h0)) node _T_5586 = mux(_T_613, deq_vec[5][2].debug_inst, UInt<1>(0h0)) node _T_5587 = mux(_T_614, deq_vec[6][2].debug_inst, UInt<1>(0h0)) node _T_5588 = mux(_T_615, deq_vec[7][2].debug_inst, UInt<1>(0h0)) node _T_5589 = or(_T_5581, _T_5582) node _T_5590 = or(_T_5589, _T_5583) node _T_5591 = or(_T_5590, _T_5584) node _T_5592 = or(_T_5591, _T_5585) node _T_5593 = or(_T_5592, _T_5586) node _T_5594 = or(_T_5593, _T_5587) node _T_5595 = or(_T_5594, _T_5588) wire _WIRE_344 : UInt<32> connect _WIRE_344, _T_5595 connect _WIRE_231.debug_inst, _WIRE_344 node _T_5596 = mux(_T_608, deq_vec[0][2].inst, UInt<1>(0h0)) node _T_5597 = mux(_T_609, deq_vec[1][2].inst, UInt<1>(0h0)) node _T_5598 = mux(_T_610, deq_vec[2][2].inst, UInt<1>(0h0)) node _T_5599 = mux(_T_611, deq_vec[3][2].inst, UInt<1>(0h0)) node _T_5600 = mux(_T_612, deq_vec[4][2].inst, UInt<1>(0h0)) node _T_5601 = mux(_T_613, deq_vec[5][2].inst, UInt<1>(0h0)) node _T_5602 = mux(_T_614, deq_vec[6][2].inst, UInt<1>(0h0)) node _T_5603 = mux(_T_615, deq_vec[7][2].inst, UInt<1>(0h0)) node _T_5604 = or(_T_5596, _T_5597) node _T_5605 = or(_T_5604, _T_5598) node _T_5606 = or(_T_5605, _T_5599) node _T_5607 = or(_T_5606, _T_5600) node _T_5608 = or(_T_5607, _T_5601) node _T_5609 = or(_T_5608, _T_5602) node _T_5610 = or(_T_5609, _T_5603) wire _WIRE_345 : UInt<32> connect _WIRE_345, _T_5610 connect _WIRE_231.inst, _WIRE_345 connect _WIRE[2], _WIRE_231 connect io.deq.bits.uops[0].bits, _WIRE[0] connect io.deq.bits.uops[1].bits, _WIRE[1] connect io.deq.bits.uops[2].bits, _WIRE[2] node _io_deq_valid_T = or(deq_valids_0, deq_valids_1) node _io_deq_valid_T_1 = or(_io_deq_valid_T, deq_valids_2) connect io.deq.valid, _io_deq_valid_T_1 when do_enq : connect tail, _T_31 node _T_5611 = or(in_mask[0], in_mask[1]) node _T_5612 = or(_T_5611, in_mask[2]) node _T_5613 = or(_T_5612, in_mask[3]) node _T_5614 = or(_T_5613, in_mask[4]) node _T_5615 = or(_T_5614, in_mask[5]) node _T_5616 = or(_T_5615, in_mask[6]) node _T_5617 = or(_T_5616, in_mask[7]) when _T_5617 : connect maybe_full, UInt<1>(0h1) when do_deq : node _head_T = bits(head, 6, 0) node _head_T_1 = bits(head, 7, 7) node _head_T_2 = cat(_head_T, _head_T_1) connect head, _head_T_2 connect maybe_full, UInt<1>(0h0) when io.clear : connect head, UInt<1>(0h1) connect tail, UInt<1>(0h1) connect maybe_full, UInt<1>(0h0) node _T_5618 = asUInt(reset) when _T_5618 : connect io.deq.bits.uops[0].valid, UInt<1>(0h0) connect io.deq.bits.uops[1].valid, UInt<1>(0h0) connect io.deq.bits.uops[2].valid, UInt<1>(0h0)	module FetchBuffer( // @[fetch-buffer.scala:40:7] input clock, // @[fetch-buffer.scala:40:7] input reset, // @[fetch-buffer.scala:40:7] output io_enq_ready, // @[fetch-buffer.scala:45:14] input io_enq_valid, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pc, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_next_pc, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_next_fetch, // @[fetch-buffer.scala:45:14] input io_enq_bits_edge_inst_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_edge_inst_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_2, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_3, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_4, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_5, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_6, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_7, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_2, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_3, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_4, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_5, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_6, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_7, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_0, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_1, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_2, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_3, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_4, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_5, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_6, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_7, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_0, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_1, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_2, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_3, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_4, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_5, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_6, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_7, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_0, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_1, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_2, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_3, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_4, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_5, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_6, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_idx_valid, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_cfi_idx_bits, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_cfi_type, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_is_call, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_is_ret, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_npc_plus4, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_ras_top, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_ftq_idx, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_mask, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_br_mask, // @[fetch-buffer.scala:45:14] input [63:0] io_enq_bits_ghist_old_history, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_current_saw_branch_not_taken, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_new_saw_branch_not_taken, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_new_saw_branch_taken, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_ghist_ras_idx, // @[fetch-buffer.scala:45:14] input io_enq_bits_lhist_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_lhist_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] input io_enq_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_end_half_valid, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_end_half_bits, // @[fetch-buffer.scala:45:14] input [119:0] io_enq_bits_bpd_meta_0, // @[fetch-buffer.scala:45:14] input [119:0] io_enq_bits_bpd_meta_1, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_fsrc, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_tsrc, // @[fetch-buffer.scala:45:14] input io_deq_ready, // @[fetch-buffer.scala:45:14] output io_deq_valid, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_0_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_0_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_0_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_0_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_0_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_0_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_1_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_1_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_1_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_1_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_1_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_1_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_2_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_2_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_2_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_2_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_2_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_2_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] input io_clear // @[fetch-buffer.scala:45:14] ); wire io_enq_valid_0 = io_enq_valid; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_next_pc_0 = io_enq_bits_next_pc; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_next_fetch_0 = io_enq_bits_next_fetch; // @[fetch-buffer.scala:40:7] wire io_enq_bits_edge_inst_0_0 = io_enq_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_edge_inst_1_0 = io_enq_bits_edge_inst_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_0_0 = io_enq_bits_insts_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_1_0 = io_enq_bits_insts_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_2_0 = io_enq_bits_insts_2; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_3_0 = io_enq_bits_insts_3; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_4_0 = io_enq_bits_insts_4; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_5_0 = io_enq_bits_insts_5; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_6_0 = io_enq_bits_insts_6; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_7_0 = io_enq_bits_insts_7; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_0_0 = io_enq_bits_exp_insts_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_1_0 = io_enq_bits_exp_insts_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_2_0 = io_enq_bits_exp_insts_2; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_3_0 = io_enq_bits_exp_insts_3; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_4_0 = io_enq_bits_exp_insts_4; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_5_0 = io_enq_bits_exp_insts_5; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_6_0 = io_enq_bits_exp_insts_6; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_7_0 = io_enq_bits_exp_insts_7; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_0_0 = io_enq_bits_pcs_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_1_0 = io_enq_bits_pcs_1; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_2_0 = io_enq_bits_pcs_2; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_3_0 = io_enq_bits_pcs_3; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_4_0 = io_enq_bits_pcs_4; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_5_0 = io_enq_bits_pcs_5; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_6_0 = io_enq_bits_pcs_6; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_7_0 = io_enq_bits_pcs_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_0_0 = io_enq_bits_sfbs_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_1_0 = io_enq_bits_sfbs_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_2_0 = io_enq_bits_sfbs_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_3_0 = io_enq_bits_sfbs_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_4_0 = io_enq_bits_sfbs_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_5_0 = io_enq_bits_sfbs_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_6_0 = io_enq_bits_sfbs_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_7_0 = io_enq_bits_sfbs_7; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_0_0 = io_enq_bits_sfb_masks_0; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_1_0 = io_enq_bits_sfb_masks_1; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_2_0 = io_enq_bits_sfb_masks_2; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_3_0 = io_enq_bits_sfb_masks_3; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_4_0 = io_enq_bits_sfb_masks_4; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_5_0 = io_enq_bits_sfb_masks_5; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_6_0 = io_enq_bits_sfb_masks_6; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_7_0 = io_enq_bits_sfb_masks_7; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_0_0 = io_enq_bits_sfb_dests_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_1_0 = io_enq_bits_sfb_dests_1; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_2_0 = io_enq_bits_sfb_dests_2; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_3_0 = io_enq_bits_sfb_dests_3; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_4_0 = io_enq_bits_sfb_dests_4; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_5_0 = io_enq_bits_sfb_dests_5; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_6_0 = io_enq_bits_sfb_dests_6; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_7_0 = io_enq_bits_sfb_dests_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_0_0 = io_enq_bits_shadowable_mask_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_1_0 = io_enq_bits_shadowable_mask_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_2_0 = io_enq_bits_shadowable_mask_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_3_0 = io_enq_bits_shadowable_mask_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_4_0 = io_enq_bits_shadowable_mask_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_5_0 = io_enq_bits_shadowable_mask_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_6_0 = io_enq_bits_shadowable_mask_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_7_0 = io_enq_bits_shadowable_mask_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_0_0 = io_enq_bits_shadowed_mask_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_1_0 = io_enq_bits_shadowed_mask_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_2_0 = io_enq_bits_shadowed_mask_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_3_0 = io_enq_bits_shadowed_mask_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_4_0 = io_enq_bits_shadowed_mask_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_5_0 = io_enq_bits_shadowed_mask_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_6_0 = io_enq_bits_shadowed_mask_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_7_0 = io_enq_bits_shadowed_mask_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_idx_valid_0 = io_enq_bits_cfi_idx_valid; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_cfi_idx_bits_0 = io_enq_bits_cfi_idx_bits; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_cfi_type_0 = io_enq_bits_cfi_type; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_is_call_0 = io_enq_bits_cfi_is_call; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_is_ret_0 = io_enq_bits_cfi_is_ret; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_npc_plus4_0 = io_enq_bits_cfi_npc_plus4; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_ras_top_0 = io_enq_bits_ras_top; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_ftq_idx_0 = io_enq_bits_ftq_idx; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_br_mask_0 = io_enq_bits_br_mask; // @[fetch-buffer.scala:40:7] wire [63:0] io_enq_bits_ghist_old_history_0 = io_enq_bits_ghist_old_history; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_current_saw_branch_not_taken_0 = io_enq_bits_ghist_current_saw_branch_not_taken; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_new_saw_branch_not_taken_0 = io_enq_bits_ghist_new_saw_branch_not_taken; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_new_saw_branch_taken_0 = io_enq_bits_ghist_new_saw_branch_taken; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_ghist_ras_idx_0 = io_enq_bits_ghist_ras_idx; // @[fetch-buffer.scala:40:7] wire io_enq_bits_lhist_0_0 = io_enq_bits_lhist_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_lhist_1_0 = io_enq_bits_lhist_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_xcpt_pf_if_0 = io_enq_bits_xcpt_pf_if; // @[fetch-buffer.scala:40:7] wire io_enq_bits_xcpt_ae_if_0 = io_enq_bits_xcpt_ae_if; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_0_0 = io_enq_bits_bp_debug_if_oh_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_1_0 = io_enq_bits_bp_debug_if_oh_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_2_0 = io_enq_bits_bp_debug_if_oh_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_3_0 = io_enq_bits_bp_debug_if_oh_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_4_0 = io_enq_bits_bp_debug_if_oh_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_5_0 = io_enq_bits_bp_debug_if_oh_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_6_0 = io_enq_bits_bp_debug_if_oh_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_7_0 = io_enq_bits_bp_debug_if_oh_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_0_0 = io_enq_bits_bp_xcpt_if_oh_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_1_0 = io_enq_bits_bp_xcpt_if_oh_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_2_0 = io_enq_bits_bp_xcpt_if_oh_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_3_0 = io_enq_bits_bp_xcpt_if_oh_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_4_0 = io_enq_bits_bp_xcpt_if_oh_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_5_0 = io_enq_bits_bp_xcpt_if_oh_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_6_0 = io_enq_bits_bp_xcpt_if_oh_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_7_0 = io_enq_bits_bp_xcpt_if_oh_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_end_half_valid_0 = io_enq_bits_end_half_valid; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_end_half_bits_0 = io_enq_bits_end_half_bits; // @[fetch-buffer.scala:40:7] wire [119:0] io_enq_bits_bpd_meta_0_0 = io_enq_bits_bpd_meta_0; // @[fetch-buffer.scala:40:7] wire [119:0] io_enq_bits_bpd_meta_1_0 = io_enq_bits_bpd_meta_1; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_fsrc_0 = io_enq_bits_fsrc; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_tsrc_0 = io_enq_bits_tsrc; // @[fetch-buffer.scala:40:7] wire io_deq_ready_0 = io_deq_ready; // @[fetch-buffer.scala:40:7] wire io_clear_0 = io_clear; // @[fetch-buffer.scala:40:7] wire _tail_collisions_T_6 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_10 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_18 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_22 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_30 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_34 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_42 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_46 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_54 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_58 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_66 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_70 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_78 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_82 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_90 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_94 = 1'h1; // @[fetch-buffer.scala:155:61] wire [5:0] io_deq_bits_uops_0_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] deq_vec_0_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] in_uops_0_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [63:0] io_deq_bits_uops_0_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] io_deq_bits_uops_1_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] io_deq_bits_uops_2_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] deq_vec_0_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_0_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_0_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] in_uops_0_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_1_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_2_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_3_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_4_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_5_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_6_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_7_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [6:0] io_deq_bits_uops_0_bits_rob_idx = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_rob_idx = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_rob_idx = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] deq_vec_0_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] in_uops_0_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [1:0] io_deq_bits_uops_0_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] deq_vec_0_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] in_uops_0_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [19:0] io_deq_bits_uops_0_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] io_deq_bits_uops_1_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] io_deq_bits_uops_2_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] deq_vec_0_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_0_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_0_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] in_uops_0_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_1_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_2_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_3_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_4_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_5_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_6_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_7_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [4:0] io_deq_bits_uops_0_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ldq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_stq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ldq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_stq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_ldq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_stq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] deq_vec_0_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] in_uops_0_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [3:0] io_deq_bits_uops_0_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_0_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_2_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_2_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] deq_vec_0_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] in_uops_0_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_0_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_4_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_4_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_5_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_5_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_6_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_6_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_7_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_7_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [15:0] io_deq_bits_uops_0_bits_br_mask = 16'h0; // @[fetch-buffer.scala:40:7] wire [15:0] io_deq_bits_uops_1_bits_br_mask = 16'h0; // @[fetch-buffer.scala:40:7] wire [15:0] io_deq_bits_uops_2_bits_br_mask = 16'h0; // @[fetch-buffer.scala:40:7] wire [15:0] deq_vec_0_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_0_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_0_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_1_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_1_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_1_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_2_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_2_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_2_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_3_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_3_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_3_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_4_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_4_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_4_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_5_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_5_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_5_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_6_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_6_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_6_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_7_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_7_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_7_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] in_uops_0_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_1_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_2_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_3_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_4_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_5_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_6_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_7_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [2:0] io_deq_bits_uops_0_bits_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_dis_col_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_dis_col_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_dis_col_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] deq_vec_0_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] in_uops_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire io_deq_bits_uops_0_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire deq_vec_0_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire do_enq; // @[fetch-buffer.scala:82:16] wire in_uops_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_edge_inst = io_enq_bits_edge_inst_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_edge_inst = io_enq_bits_edge_inst_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_0_debug_inst = io_enq_bits_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_1_debug_inst = io_enq_bits_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_2_debug_inst = io_enq_bits_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_3_debug_inst = io_enq_bits_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_4_debug_inst = io_enq_bits_insts_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_5_debug_inst = io_enq_bits_insts_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_6_debug_inst = io_enq_bits_insts_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_7_debug_inst = io_enq_bits_insts_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_0_inst = io_enq_bits_exp_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_1_inst = io_enq_bits_exp_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_2_inst = io_enq_bits_exp_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_3_inst = io_enq_bits_exp_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_4_inst = io_enq_bits_exp_insts_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_5_inst = io_enq_bits_exp_insts_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_6_inst = io_enq_bits_exp_insts_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_7_inst = io_enq_bits_exp_insts_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_0_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_1_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_2_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_3_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_4_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_5_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_6_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_7_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_bp_debug_if = io_enq_bits_bp_debug_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_bp_debug_if = io_enq_bits_bp_debug_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_bp_debug_if = io_enq_bits_bp_debug_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_bp_debug_if = io_enq_bits_bp_debug_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_bp_debug_if = io_enq_bits_bp_debug_if_oh_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_bp_debug_if = io_enq_bits_bp_debug_if_oh_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_bp_debug_if = io_enq_bits_bp_debug_if_oh_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_bp_debug_if = io_enq_bits_bp_debug_if_oh_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_0_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_1_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_2_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_3_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_4_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_5_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_6_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_7_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire _io_deq_valid_T_1; // @[fetch-buffer.scala:170:38] wire io_enq_ready_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_1_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_1_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_1_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_valid_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_2_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_2_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_2_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_valid_0; // @[fetch-buffer.scala:40:7] wire io_deq_valid_0; // @[fetch-buffer.scala:40:7] reg [31:0] fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_0_inst = fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_0_debug_inst = fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_is_rvc = fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_0_debug_pc = fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_is_sfb = fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_0_ftq_idx = fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_edge_inst = fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_0_pc_lob = fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_taken = fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_xcpt_pf_if = fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_xcpt_ae_if = fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_bp_debug_if = fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_bp_xcpt_if = fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_0_debug_fsrc = fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_1_inst = fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_1_debug_inst = fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_is_rvc = fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_1_debug_pc = fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_is_sfb = fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_1_ftq_idx = fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_edge_inst = fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_1_pc_lob = fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_taken = fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_xcpt_pf_if = fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_xcpt_ae_if = fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_bp_debug_if = fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_bp_xcpt_if = fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_1_debug_fsrc = fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_2_inst = fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_2_debug_inst = fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_is_rvc = fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_2_debug_pc = fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_is_sfb = fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_2_ftq_idx = fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_edge_inst = fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_2_pc_lob = fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_taken = fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_xcpt_pf_if = fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_xcpt_ae_if = fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_bp_debug_if = fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_bp_xcpt_if = fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_2_debug_fsrc = fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_0_inst = fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_0_debug_inst = fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_is_rvc = fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_0_debug_pc = fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_is_sfb = fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_0_ftq_idx = fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_edge_inst = fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_0_pc_lob = fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_taken = fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_xcpt_pf_if = fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_xcpt_ae_if = fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_bp_debug_if = fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_bp_xcpt_if = fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_0_debug_fsrc = fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_1_inst = fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_1_debug_inst = fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_is_rvc = fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_1_debug_pc = fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_is_sfb = fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_1_ftq_idx = fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_edge_inst = fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_1_pc_lob = fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_taken = fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_xcpt_pf_if = fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_xcpt_ae_if = fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_bp_debug_if = fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_bp_xcpt_if = fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_1_debug_fsrc = fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_2_inst = fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_2_debug_inst = fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_is_rvc = fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_2_debug_pc = fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_is_sfb = fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_2_ftq_idx = fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_edge_inst = fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_2_pc_lob = fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_taken = fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_xcpt_pf_if = fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_xcpt_ae_if = fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_bp_debug_if = fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_bp_xcpt_if = fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_2_debug_fsrc = fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_0_inst = fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_0_debug_inst = fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_is_rvc = fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_0_debug_pc = fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_is_sfb = fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_0_ftq_idx = fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_edge_inst = fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_0_pc_lob = fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_taken = fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_xcpt_pf_if = fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_xcpt_ae_if = fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_bp_debug_if = fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_bp_xcpt_if = fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_0_debug_fsrc = fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_1_inst = fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_1_debug_inst = fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_is_rvc = fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_1_debug_pc = fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_is_sfb = fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_1_ftq_idx = fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_edge_inst = fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_1_pc_lob = fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_taken = fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_xcpt_pf_if = fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_xcpt_ae_if = fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_bp_debug_if = fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_bp_xcpt_if = fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_1_debug_fsrc = fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_8_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_2_inst = fb_uop_ram_8_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_8_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_2_debug_inst = fb_uop_ram_8_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_is_rvc = fb_uop_ram_8_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_8_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_2_debug_pc = fb_uop_ram_8_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_is_sfb = fb_uop_ram_8_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_8_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_2_ftq_idx = fb_uop_ram_8_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_edge_inst = fb_uop_ram_8_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_8_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_2_pc_lob = fb_uop_ram_8_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_taken = fb_uop_ram_8_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_xcpt_pf_if = fb_uop_ram_8_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_xcpt_ae_if = fb_uop_ram_8_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_bp_debug_if = fb_uop_ram_8_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_bp_xcpt_if = fb_uop_ram_8_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_8_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_2_debug_fsrc = fb_uop_ram_8_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_9_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_0_inst = fb_uop_ram_9_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_9_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_0_debug_inst = fb_uop_ram_9_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_is_rvc = fb_uop_ram_9_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_9_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_0_debug_pc = fb_uop_ram_9_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_is_sfb = fb_uop_ram_9_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_9_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_0_ftq_idx = fb_uop_ram_9_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_edge_inst = fb_uop_ram_9_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_9_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_0_pc_lob = fb_uop_ram_9_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_taken = fb_uop_ram_9_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_xcpt_pf_if = fb_uop_ram_9_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_xcpt_ae_if = fb_uop_ram_9_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_bp_debug_if = fb_uop_ram_9_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_bp_xcpt_if = fb_uop_ram_9_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_9_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_0_debug_fsrc = fb_uop_ram_9_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_10_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_1_inst = fb_uop_ram_10_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_10_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_1_debug_inst = fb_uop_ram_10_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_is_rvc = fb_uop_ram_10_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_10_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_1_debug_pc = fb_uop_ram_10_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_is_sfb = fb_uop_ram_10_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_10_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_1_ftq_idx = fb_uop_ram_10_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_edge_inst = fb_uop_ram_10_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_10_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_1_pc_lob = fb_uop_ram_10_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_taken = fb_uop_ram_10_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_xcpt_pf_if = fb_uop_ram_10_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_xcpt_ae_if = fb_uop_ram_10_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_bp_debug_if = fb_uop_ram_10_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_bp_xcpt_if = fb_uop_ram_10_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_10_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_1_debug_fsrc = fb_uop_ram_10_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_11_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_2_inst = fb_uop_ram_11_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_11_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_2_debug_inst = fb_uop_ram_11_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_is_rvc = fb_uop_ram_11_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_11_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_2_debug_pc = fb_uop_ram_11_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_is_sfb = fb_uop_ram_11_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_11_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_2_ftq_idx = fb_uop_ram_11_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_edge_inst = fb_uop_ram_11_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_11_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_2_pc_lob = fb_uop_ram_11_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_taken = fb_uop_ram_11_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_xcpt_pf_if = fb_uop_ram_11_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_xcpt_ae_if = fb_uop_ram_11_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_bp_debug_if = fb_uop_ram_11_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_bp_xcpt_if = fb_uop_ram_11_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_11_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_2_debug_fsrc = fb_uop_ram_11_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_12_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_0_inst = fb_uop_ram_12_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_12_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_0_debug_inst = fb_uop_ram_12_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_is_rvc = fb_uop_ram_12_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_12_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_0_debug_pc = fb_uop_ram_12_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_is_sfb = fb_uop_ram_12_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_12_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_0_ftq_idx = fb_uop_ram_12_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_edge_inst = fb_uop_ram_12_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_12_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_0_pc_lob = fb_uop_ram_12_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_taken = fb_uop_ram_12_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_xcpt_pf_if = fb_uop_ram_12_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_xcpt_ae_if = fb_uop_ram_12_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_bp_debug_if = fb_uop_ram_12_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_bp_xcpt_if = fb_uop_ram_12_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_12_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_0_debug_fsrc = fb_uop_ram_12_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_13_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_1_inst = fb_uop_ram_13_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_13_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_1_debug_inst = fb_uop_ram_13_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_is_rvc = fb_uop_ram_13_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_13_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_1_debug_pc = fb_uop_ram_13_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_is_sfb = fb_uop_ram_13_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_13_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_1_ftq_idx = fb_uop_ram_13_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_edge_inst = fb_uop_ram_13_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_13_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_1_pc_lob = fb_uop_ram_13_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_taken = fb_uop_ram_13_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_xcpt_pf_if = fb_uop_ram_13_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_xcpt_ae_if = fb_uop_ram_13_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_bp_debug_if = fb_uop_ram_13_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_bp_xcpt_if = fb_uop_ram_13_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_13_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_1_debug_fsrc = fb_uop_ram_13_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_14_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_2_inst = fb_uop_ram_14_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_14_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_2_debug_inst = fb_uop_ram_14_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_is_rvc = fb_uop_ram_14_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_14_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_2_debug_pc = fb_uop_ram_14_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_is_sfb = fb_uop_ram_14_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_14_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_2_ftq_idx = fb_uop_ram_14_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_edge_inst = fb_uop_ram_14_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_14_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_2_pc_lob = fb_uop_ram_14_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_taken = fb_uop_ram_14_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_xcpt_pf_if = fb_uop_ram_14_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_xcpt_ae_if = fb_uop_ram_14_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_bp_debug_if = fb_uop_ram_14_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_bp_xcpt_if = fb_uop_ram_14_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_14_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_2_debug_fsrc = fb_uop_ram_14_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_15_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_0_inst = fb_uop_ram_15_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_15_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_0_debug_inst = fb_uop_ram_15_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_is_rvc = fb_uop_ram_15_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_15_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_0_debug_pc = fb_uop_ram_15_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_is_sfb = fb_uop_ram_15_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_15_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_0_ftq_idx = fb_uop_ram_15_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_edge_inst = fb_uop_ram_15_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_15_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_0_pc_lob = fb_uop_ram_15_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_taken = fb_uop_ram_15_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_xcpt_pf_if = fb_uop_ram_15_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_xcpt_ae_if = fb_uop_ram_15_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_bp_debug_if = fb_uop_ram_15_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_bp_xcpt_if = fb_uop_ram_15_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_15_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_0_debug_fsrc = fb_uop_ram_15_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_16_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_1_inst = fb_uop_ram_16_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_16_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_1_debug_inst = fb_uop_ram_16_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_is_rvc = fb_uop_ram_16_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_16_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_1_debug_pc = fb_uop_ram_16_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_is_sfb = fb_uop_ram_16_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_16_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_1_ftq_idx = fb_uop_ram_16_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_edge_inst = fb_uop_ram_16_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_16_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_1_pc_lob = fb_uop_ram_16_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_taken = fb_uop_ram_16_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_xcpt_pf_if = fb_uop_ram_16_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_xcpt_ae_if = fb_uop_ram_16_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_bp_debug_if = fb_uop_ram_16_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_bp_xcpt_if = fb_uop_ram_16_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_16_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_1_debug_fsrc = fb_uop_ram_16_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_17_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_2_inst = fb_uop_ram_17_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_17_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_2_debug_inst = fb_uop_ram_17_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_is_rvc = fb_uop_ram_17_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_17_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_2_debug_pc = fb_uop_ram_17_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_is_sfb = fb_uop_ram_17_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_17_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_2_ftq_idx = fb_uop_ram_17_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_edge_inst = fb_uop_ram_17_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_17_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_2_pc_lob = fb_uop_ram_17_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_taken = fb_uop_ram_17_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_xcpt_pf_if = fb_uop_ram_17_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_xcpt_ae_if = fb_uop_ram_17_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_bp_debug_if = fb_uop_ram_17_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_bp_xcpt_if = fb_uop_ram_17_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_17_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_2_debug_fsrc = fb_uop_ram_17_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_18_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_0_inst = fb_uop_ram_18_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_18_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_0_debug_inst = fb_uop_ram_18_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_is_rvc = fb_uop_ram_18_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_18_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_0_debug_pc = fb_uop_ram_18_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_is_sfb = fb_uop_ram_18_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_18_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_0_ftq_idx = fb_uop_ram_18_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_edge_inst = fb_uop_ram_18_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_18_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_0_pc_lob = fb_uop_ram_18_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_taken = fb_uop_ram_18_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_xcpt_pf_if = fb_uop_ram_18_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_xcpt_ae_if = fb_uop_ram_18_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_bp_debug_if = fb_uop_ram_18_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_bp_xcpt_if = fb_uop_ram_18_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_18_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_0_debug_fsrc = fb_uop_ram_18_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_19_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_1_inst = fb_uop_ram_19_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_19_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_1_debug_inst = fb_uop_ram_19_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_is_rvc = fb_uop_ram_19_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_19_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_1_debug_pc = fb_uop_ram_19_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_is_sfb = fb_uop_ram_19_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_19_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_1_ftq_idx = fb_uop_ram_19_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_edge_inst = fb_uop_ram_19_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_19_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_1_pc_lob = fb_uop_ram_19_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_taken = fb_uop_ram_19_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_xcpt_pf_if = fb_uop_ram_19_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_xcpt_ae_if = fb_uop_ram_19_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_bp_debug_if = fb_uop_ram_19_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_bp_xcpt_if = fb_uop_ram_19_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_19_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_1_debug_fsrc = fb_uop_ram_19_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_20_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_2_inst = fb_uop_ram_20_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_20_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_2_debug_inst = fb_uop_ram_20_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_is_rvc = fb_uop_ram_20_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_20_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_2_debug_pc = fb_uop_ram_20_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_is_sfb = fb_uop_ram_20_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_20_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_2_ftq_idx = fb_uop_ram_20_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_edge_inst = fb_uop_ram_20_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_20_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_2_pc_lob = fb_uop_ram_20_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_taken = fb_uop_ram_20_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_xcpt_pf_if = fb_uop_ram_20_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_xcpt_ae_if = fb_uop_ram_20_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_bp_debug_if = fb_uop_ram_20_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_bp_xcpt_if = fb_uop_ram_20_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_20_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_2_debug_fsrc = fb_uop_ram_20_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_21_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_0_inst = fb_uop_ram_21_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_21_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_0_debug_inst = fb_uop_ram_21_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_is_rvc = fb_uop_ram_21_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_21_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_0_debug_pc = fb_uop_ram_21_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_is_sfb = fb_uop_ram_21_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_21_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_0_ftq_idx = fb_uop_ram_21_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_edge_inst = fb_uop_ram_21_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_21_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_0_pc_lob = fb_uop_ram_21_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_taken = fb_uop_ram_21_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_xcpt_pf_if = fb_uop_ram_21_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_xcpt_ae_if = fb_uop_ram_21_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_bp_debug_if = fb_uop_ram_21_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_bp_xcpt_if = fb_uop_ram_21_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_21_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_0_debug_fsrc = fb_uop_ram_21_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_22_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_1_inst = fb_uop_ram_22_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_22_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_1_debug_inst = fb_uop_ram_22_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_is_rvc = fb_uop_ram_22_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_22_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_1_debug_pc = fb_uop_ram_22_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_is_sfb = fb_uop_ram_22_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_22_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_1_ftq_idx = fb_uop_ram_22_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_edge_inst = fb_uop_ram_22_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_22_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_1_pc_lob = fb_uop_ram_22_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_taken = fb_uop_ram_22_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_xcpt_pf_if = fb_uop_ram_22_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_xcpt_ae_if = fb_uop_ram_22_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_bp_debug_if = fb_uop_ram_22_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_bp_xcpt_if = fb_uop_ram_22_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_22_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_1_debug_fsrc = fb_uop_ram_22_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_23_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_2_inst = fb_uop_ram_23_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_23_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_2_debug_inst = fb_uop_ram_23_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_is_rvc = fb_uop_ram_23_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_23_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_2_debug_pc = fb_uop_ram_23_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_is_sfb = fb_uop_ram_23_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_23_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_2_ftq_idx = fb_uop_ram_23_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_edge_inst = fb_uop_ram_23_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_23_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_2_pc_lob = fb_uop_ram_23_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_taken = fb_uop_ram_23_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_xcpt_pf_if = fb_uop_ram_23_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_xcpt_ae_if = fb_uop_ram_23_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_bp_debug_if = fb_uop_ram_23_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_bp_xcpt_if = fb_uop_ram_23_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_23_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_2_debug_fsrc = fb_uop_ram_23_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [7:0] head; // @[fetch-buffer.scala:61:21] reg [23:0] tail; // @[fetch-buffer.scala:62:21] wire [23:0] enq_idxs_0 = tail; // @[fetch-buffer.scala:62:21, :128:22] reg maybe_full; // @[fetch-buffer.scala:64:27] wire [22:0] _might_hit_head_T = tail[22:0]; // @[fetch-buffer.scala:62:21, :75:11] wire _might_hit_head_T_1 = tail[23]; // @[fetch-buffer.scala:62:21, :75:24] wire _at_head_T_23 = tail[23]; // @[fetch-buffer.scala:62:21, :75:24, :80:31] wire [23:0] _might_hit_head_T_2 = {_might_hit_head_T, _might_hit_head_T_1}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_3 = _might_hit_head_T_2[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_0 = _might_hit_head_T_3; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_4 = _might_hit_head_T_2[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_5 = _might_hit_head_T_2[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_6 = _might_hit_head_T_2[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1 = _might_hit_head_T_6; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_7 = _might_hit_head_T_2[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_8 = _might_hit_head_T_2[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_9 = _might_hit_head_T_2[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2 = _might_hit_head_T_9; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_10 = _might_hit_head_T_2[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_11 = _might_hit_head_T_2[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_12 = _might_hit_head_T_2[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3 = _might_hit_head_T_12; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_13 = _might_hit_head_T_2[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_14 = _might_hit_head_T_2[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_15 = _might_hit_head_T_2[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4 = _might_hit_head_T_15; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_16 = _might_hit_head_T_2[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_17 = _might_hit_head_T_2[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_18 = _might_hit_head_T_2[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5 = _might_hit_head_T_18; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_19 = _might_hit_head_T_2[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_20 = _might_hit_head_T_2[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_21 = _might_hit_head_T_2[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6 = _might_hit_head_T_21; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_22 = _might_hit_head_T_2[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_23 = _might_hit_head_T_2[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_24 = _might_hit_head_T_2[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_7 = _might_hit_head_T_24; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_25 = _might_hit_head_T_2[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_26 = _might_hit_head_T_2[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo = {_might_hit_head_WIRE_1, _might_hit_head_WIRE_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi = {_might_hit_head_WIRE_3, _might_hit_head_WIRE_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo = {might_hit_head_lo_hi, might_hit_head_lo_lo}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo = {_might_hit_head_WIRE_5, _might_hit_head_WIRE_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi = {_might_hit_head_WIRE_7, _might_hit_head_WIRE_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi = {might_hit_head_hi_hi, might_hit_head_hi_lo}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_27 = {might_hit_head_hi, might_hit_head_lo}; // @[fetch-buffer.scala:79:63] wire [21:0] _might_hit_head_T_28 = tail[21:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [1:0] _might_hit_head_T_29 = tail[23:22]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_30 = {_might_hit_head_T_28, _might_hit_head_T_29}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_31 = _might_hit_head_T_30[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_0 = _might_hit_head_T_31; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_32 = _might_hit_head_T_30[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_33 = _might_hit_head_T_30[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_34 = _might_hit_head_T_30[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_1 = _might_hit_head_T_34; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_35 = _might_hit_head_T_30[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_36 = _might_hit_head_T_30[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_37 = _might_hit_head_T_30[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_2 = _might_hit_head_T_37; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_38 = _might_hit_head_T_30[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_39 = _might_hit_head_T_30[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_40 = _might_hit_head_T_30[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_3 = _might_hit_head_T_40; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_41 = _might_hit_head_T_30[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_42 = _might_hit_head_T_30[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_43 = _might_hit_head_T_30[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_4 = _might_hit_head_T_43; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_44 = _might_hit_head_T_30[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_45 = _might_hit_head_T_30[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_46 = _might_hit_head_T_30[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_5 = _might_hit_head_T_46; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_47 = _might_hit_head_T_30[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_48 = _might_hit_head_T_30[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_49 = _might_hit_head_T_30[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_6 = _might_hit_head_T_49; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_50 = _might_hit_head_T_30[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_51 = _might_hit_head_T_30[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_52 = _might_hit_head_T_30[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_7 = _might_hit_head_T_52; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_53 = _might_hit_head_T_30[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_54 = _might_hit_head_T_30[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_1 = {_might_hit_head_WIRE_1_1, _might_hit_head_WIRE_1_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_1 = {_might_hit_head_WIRE_1_3, _might_hit_head_WIRE_1_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_1 = {might_hit_head_lo_hi_1, might_hit_head_lo_lo_1}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_1 = {_might_hit_head_WIRE_1_5, _might_hit_head_WIRE_1_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_1 = {_might_hit_head_WIRE_1_7, _might_hit_head_WIRE_1_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_1 = {might_hit_head_hi_hi_1, might_hit_head_hi_lo_1}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_55 = {might_hit_head_hi_1, might_hit_head_lo_1}; // @[fetch-buffer.scala:79:63] wire [20:0] _might_hit_head_T_56 = tail[20:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [2:0] _might_hit_head_T_57 = tail[23:21]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_58 = {_might_hit_head_T_56, _might_hit_head_T_57}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_59 = _might_hit_head_T_58[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_0 = _might_hit_head_T_59; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_60 = _might_hit_head_T_58[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_61 = _might_hit_head_T_58[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_62 = _might_hit_head_T_58[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_1 = _might_hit_head_T_62; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_63 = _might_hit_head_T_58[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_64 = _might_hit_head_T_58[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_65 = _might_hit_head_T_58[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_2 = _might_hit_head_T_65; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_66 = _might_hit_head_T_58[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_67 = _might_hit_head_T_58[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_68 = _might_hit_head_T_58[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_3 = _might_hit_head_T_68; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_69 = _might_hit_head_T_58[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_70 = _might_hit_head_T_58[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_71 = _might_hit_head_T_58[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_4 = _might_hit_head_T_71; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_72 = _might_hit_head_T_58[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_73 = _might_hit_head_T_58[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_74 = _might_hit_head_T_58[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_5 = _might_hit_head_T_74; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_75 = _might_hit_head_T_58[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_76 = _might_hit_head_T_58[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_77 = _might_hit_head_T_58[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_6 = _might_hit_head_T_77; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_78 = _might_hit_head_T_58[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_79 = _might_hit_head_T_58[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_80 = _might_hit_head_T_58[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_7 = _might_hit_head_T_80; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_81 = _might_hit_head_T_58[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_82 = _might_hit_head_T_58[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_2 = {_might_hit_head_WIRE_2_1, _might_hit_head_WIRE_2_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_2 = {_might_hit_head_WIRE_2_3, _might_hit_head_WIRE_2_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_2 = {might_hit_head_lo_hi_2, might_hit_head_lo_lo_2}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_2 = {_might_hit_head_WIRE_2_5, _might_hit_head_WIRE_2_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_2 = {_might_hit_head_WIRE_2_7, _might_hit_head_WIRE_2_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_2 = {might_hit_head_hi_hi_2, might_hit_head_hi_lo_2}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_83 = {might_hit_head_hi_2, might_hit_head_lo_2}; // @[fetch-buffer.scala:79:63] wire [19:0] _might_hit_head_T_84 = tail[19:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [3:0] _might_hit_head_T_85 = tail[23:20]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_86 = {_might_hit_head_T_84, _might_hit_head_T_85}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_87 = _might_hit_head_T_86[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_0 = _might_hit_head_T_87; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_88 = _might_hit_head_T_86[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_89 = _might_hit_head_T_86[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_90 = _might_hit_head_T_86[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_1 = _might_hit_head_T_90; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_91 = _might_hit_head_T_86[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_92 = _might_hit_head_T_86[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_93 = _might_hit_head_T_86[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_2 = _might_hit_head_T_93; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_94 = _might_hit_head_T_86[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_95 = _might_hit_head_T_86[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_96 = _might_hit_head_T_86[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_3 = _might_hit_head_T_96; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_97 = _might_hit_head_T_86[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_98 = _might_hit_head_T_86[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_99 = _might_hit_head_T_86[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_4 = _might_hit_head_T_99; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_100 = _might_hit_head_T_86[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_101 = _might_hit_head_T_86[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_102 = _might_hit_head_T_86[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_5 = _might_hit_head_T_102; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_103 = _might_hit_head_T_86[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_104 = _might_hit_head_T_86[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_105 = _might_hit_head_T_86[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_6 = _might_hit_head_T_105; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_106 = _might_hit_head_T_86[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_107 = _might_hit_head_T_86[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_108 = _might_hit_head_T_86[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_7 = _might_hit_head_T_108; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_109 = _might_hit_head_T_86[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_110 = _might_hit_head_T_86[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_3 = {_might_hit_head_WIRE_3_1, _might_hit_head_WIRE_3_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_3 = {_might_hit_head_WIRE_3_3, _might_hit_head_WIRE_3_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_3 = {might_hit_head_lo_hi_3, might_hit_head_lo_lo_3}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_3 = {_might_hit_head_WIRE_3_5, _might_hit_head_WIRE_3_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_3 = {_might_hit_head_WIRE_3_7, _might_hit_head_WIRE_3_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_3 = {might_hit_head_hi_hi_3, might_hit_head_hi_lo_3}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_111 = {might_hit_head_hi_3, might_hit_head_lo_3}; // @[fetch-buffer.scala:79:63] wire [18:0] _might_hit_head_T_112 = tail[18:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [4:0] _might_hit_head_T_113 = tail[23:19]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_114 = {_might_hit_head_T_112, _might_hit_head_T_113}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_115 = _might_hit_head_T_114[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_0 = _might_hit_head_T_115; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_116 = _might_hit_head_T_114[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_117 = _might_hit_head_T_114[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_118 = _might_hit_head_T_114[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_1 = _might_hit_head_T_118; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_119 = _might_hit_head_T_114[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_120 = _might_hit_head_T_114[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_121 = _might_hit_head_T_114[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_2 = _might_hit_head_T_121; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_122 = _might_hit_head_T_114[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_123 = _might_hit_head_T_114[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_124 = _might_hit_head_T_114[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_3 = _might_hit_head_T_124; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_125 = _might_hit_head_T_114[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_126 = _might_hit_head_T_114[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_127 = _might_hit_head_T_114[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_4 = _might_hit_head_T_127; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_128 = _might_hit_head_T_114[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_129 = _might_hit_head_T_114[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_130 = _might_hit_head_T_114[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_5 = _might_hit_head_T_130; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_131 = _might_hit_head_T_114[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_132 = _might_hit_head_T_114[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_133 = _might_hit_head_T_114[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_6 = _might_hit_head_T_133; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_134 = _might_hit_head_T_114[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_135 = _might_hit_head_T_114[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_136 = _might_hit_head_T_114[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_7 = _might_hit_head_T_136; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_137 = _might_hit_head_T_114[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_138 = _might_hit_head_T_114[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_4 = {_might_hit_head_WIRE_4_1, _might_hit_head_WIRE_4_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_4 = {_might_hit_head_WIRE_4_3, _might_hit_head_WIRE_4_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_4 = {might_hit_head_lo_hi_4, might_hit_head_lo_lo_4}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_4 = {_might_hit_head_WIRE_4_5, _might_hit_head_WIRE_4_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_4 = {_might_hit_head_WIRE_4_7, _might_hit_head_WIRE_4_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_4 = {might_hit_head_hi_hi_4, might_hit_head_hi_lo_4}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_139 = {might_hit_head_hi_4, might_hit_head_lo_4}; // @[fetch-buffer.scala:79:63] wire [17:0] _might_hit_head_T_140 = tail[17:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [5:0] _might_hit_head_T_141 = tail[23:18]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_142 = {_might_hit_head_T_140, _might_hit_head_T_141}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_143 = _might_hit_head_T_142[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_0 = _might_hit_head_T_143; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_144 = _might_hit_head_T_142[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_145 = _might_hit_head_T_142[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_146 = _might_hit_head_T_142[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_1 = _might_hit_head_T_146; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_147 = _might_hit_head_T_142[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_148 = _might_hit_head_T_142[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_149 = _might_hit_head_T_142[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_2 = _might_hit_head_T_149; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_150 = _might_hit_head_T_142[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_151 = _might_hit_head_T_142[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_152 = _might_hit_head_T_142[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_3 = _might_hit_head_T_152; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_153 = _might_hit_head_T_142[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_154 = _might_hit_head_T_142[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_155 = _might_hit_head_T_142[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_4 = _might_hit_head_T_155; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_156 = _might_hit_head_T_142[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_157 = _might_hit_head_T_142[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_158 = _might_hit_head_T_142[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_5 = _might_hit_head_T_158; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_159 = _might_hit_head_T_142[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_160 = _might_hit_head_T_142[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_161 = _might_hit_head_T_142[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_6 = _might_hit_head_T_161; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_162 = _might_hit_head_T_142[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_163 = _might_hit_head_T_142[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_164 = _might_hit_head_T_142[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_7 = _might_hit_head_T_164; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_165 = _might_hit_head_T_142[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_166 = _might_hit_head_T_142[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_5 = {_might_hit_head_WIRE_5_1, _might_hit_head_WIRE_5_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_5 = {_might_hit_head_WIRE_5_3, _might_hit_head_WIRE_5_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_5 = {might_hit_head_lo_hi_5, might_hit_head_lo_lo_5}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_5 = {_might_hit_head_WIRE_5_5, _might_hit_head_WIRE_5_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_5 = {_might_hit_head_WIRE_5_7, _might_hit_head_WIRE_5_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_5 = {might_hit_head_hi_hi_5, might_hit_head_hi_lo_5}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_167 = {might_hit_head_hi_5, might_hit_head_lo_5}; // @[fetch-buffer.scala:79:63] wire [16:0] _might_hit_head_T_168 = tail[16:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [6:0] _might_hit_head_T_169 = tail[23:17]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_170 = {_might_hit_head_T_168, _might_hit_head_T_169}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_171 = _might_hit_head_T_170[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_0 = _might_hit_head_T_171; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_172 = _might_hit_head_T_170[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_173 = _might_hit_head_T_170[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_174 = _might_hit_head_T_170[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_1 = _might_hit_head_T_174; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_175 = _might_hit_head_T_170[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_176 = _might_hit_head_T_170[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_177 = _might_hit_head_T_170[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_2 = _might_hit_head_T_177; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_178 = _might_hit_head_T_170[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_179 = _might_hit_head_T_170[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_180 = _might_hit_head_T_170[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_3 = _might_hit_head_T_180; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_181 = _might_hit_head_T_170[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_182 = _might_hit_head_T_170[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_183 = _might_hit_head_T_170[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_4 = _might_hit_head_T_183; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_184 = _might_hit_head_T_170[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_185 = _might_hit_head_T_170[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_186 = _might_hit_head_T_170[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_5 = _might_hit_head_T_186; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_187 = _might_hit_head_T_170[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_188 = _might_hit_head_T_170[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_189 = _might_hit_head_T_170[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_6 = _might_hit_head_T_189; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_190 = _might_hit_head_T_170[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_191 = _might_hit_head_T_170[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_192 = _might_hit_head_T_170[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_7 = _might_hit_head_T_192; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_193 = _might_hit_head_T_170[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_194 = _might_hit_head_T_170[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_6 = {_might_hit_head_WIRE_6_1, _might_hit_head_WIRE_6_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_6 = {_might_hit_head_WIRE_6_3, _might_hit_head_WIRE_6_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_6 = {might_hit_head_lo_hi_6, might_hit_head_lo_lo_6}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_6 = {_might_hit_head_WIRE_6_5, _might_hit_head_WIRE_6_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_6 = {_might_hit_head_WIRE_6_7, _might_hit_head_WIRE_6_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_6 = {might_hit_head_hi_hi_6, might_hit_head_hi_lo_6}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_195 = {might_hit_head_hi_6, might_hit_head_lo_6}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_196 = head & _might_hit_head_T_27; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_197 = head & _might_hit_head_T_55; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_198 = head & _might_hit_head_T_83; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_199 = head & _might_hit_head_T_111; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_200 = head & _might_hit_head_T_139; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_201 = head & _might_hit_head_T_167; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_202 = head & _might_hit_head_T_195; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_203 = _might_hit_head_T_196 \| _might_hit_head_T_197; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_204 = _might_hit_head_T_203 \| _might_hit_head_T_198; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_205 = _might_hit_head_T_204 \| _might_hit_head_T_199; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_206 = _might_hit_head_T_205 \| _might_hit_head_T_200; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_207 = _might_hit_head_T_206 \| _might_hit_head_T_201; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_208 = _might_hit_head_T_207 \| _might_hit_head_T_202; // @[fetch-buffer.scala:79:{88,104}] wire might_hit_head = \|_might_hit_head_T_208; // @[fetch-buffer.scala:79:{104,108}] wire _at_head_T = tail[0]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_0 = _at_head_T; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_1 = tail[1]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_2 = tail[2]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_3 = tail[3]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_1 = _at_head_T_3; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_4 = tail[4]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_5 = tail[5]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_6 = tail[6]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_2 = _at_head_T_6; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_7 = tail[7]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_8 = tail[8]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_9 = tail[9]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_3 = _at_head_T_9; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_10 = tail[10]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_11 = tail[11]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_12 = tail[12]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_4 = _at_head_T_12; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_13 = tail[13]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_14 = tail[14]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_15 = tail[15]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_5 = _at_head_T_15; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_16 = tail[16]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_17 = tail[17]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_18 = tail[18]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_6 = _at_head_T_18; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_19 = tail[19]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_20 = tail[20]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_21 = tail[21]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_7 = _at_head_T_21; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_22 = tail[22]; // @[fetch-buffer.scala:62:21, :80:31] wire [1:0] at_head_lo_lo = {_at_head_WIRE_1, _at_head_WIRE_0}; // @[fetch-buffer.scala:80:25, :81:29] wire [1:0] at_head_lo_hi = {_at_head_WIRE_3, _at_head_WIRE_2}; // @[fetch-buffer.scala:80:25, :81:29] wire [3:0] at_head_lo = {at_head_lo_hi, at_head_lo_lo}; // @[fetch-buffer.scala:81:29] wire [1:0] at_head_hi_lo = {_at_head_WIRE_5, _at_head_WIRE_4}; // @[fetch-buffer.scala:80:25, :81:29] wire [1:0] at_head_hi_hi = {_at_head_WIRE_7, _at_head_WIRE_6}; // @[fetch-buffer.scala:80:25, :81:29] wire [3:0] at_head_hi = {at_head_hi_hi, at_head_hi_lo}; // @[fetch-buffer.scala:81:29] wire [7:0] _at_head_T_24 = {at_head_hi, at_head_lo}; // @[fetch-buffer.scala:81:29] wire [7:0] _at_head_T_25 = _at_head_T_24 & head; // @[fetch-buffer.scala:61:21, :81:{29,36}] wire at_head = \|_at_head_T_25; // @[fetch-buffer.scala:81:{36,44}] wire _do_enq_T = at_head & maybe_full; // @[fetch-buffer.scala:64:27, :81:44, :82:26] wire _do_enq_T_1 = _do_enq_T \| might_hit_head; // @[fetch-buffer.scala:79:108, :82:{26,40}] assign do_enq = ~_do_enq_T_1; // @[fetch-buffer.scala:82:{16,40}] assign io_enq_ready_0 = do_enq; // @[fetch-buffer.scala:40:7, :82:16] wire _in_mask_0_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_1_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_2_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_3_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_4_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_5_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_6_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_7_T_1; // @[fetch-buffer.scala:98:49] wire in_mask_0; // @[fetch-buffer.scala:87:21] wire in_mask_1; // @[fetch-buffer.scala:87:21] wire in_mask_2; // @[fetch-buffer.scala:87:21] wire in_mask_3; // @[fetch-buffer.scala:87:21] wire in_mask_4; // @[fetch-buffer.scala:87:21] wire in_mask_5; // @[fetch-buffer.scala:87:21] wire in_mask_6; // @[fetch-buffer.scala:87:21] wire in_mask_7; // @[fetch-buffer.scala:87:21] wire _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_0_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_1; // @[fetch-buffer.scala:95:43] wire _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_1_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_2; // @[fetch-buffer.scala:95:43] wire _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_2_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_3; // @[fetch-buffer.scala:95:43] wire _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_3_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_4_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire _in_uops_4_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_4_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_5_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_5; // @[fetch-buffer.scala:95:43] wire _in_uops_5_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_5_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_6_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_6; // @[fetch-buffer.scala:95:43] wire _in_uops_6_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_6_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_7_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_7; // @[fetch-buffer.scala:95:43] wire _in_uops_7_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_7_taken_T_1; // @[fetch-buffer.scala:116:69] wire in_uops_0_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_0_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_0_taken; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_1_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_1_taken; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_2_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_2_taken; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_3_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_3_taken; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_4_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_4_taken; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_5_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_5_taken; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_6_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_6_taken; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_7_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_7_taken; // @[fetch-buffer.scala:88:21] wire [39:0] _pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_1 = {_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_2 = ~_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_3 = {1'h0, _pc_T_2}; // @[frontend.scala:147:31] wire [39:0] pc = _pc_T_3[39:0]; // @[fetch-buffer.scala:95:43] wire _in_mask_0_T = io_enq_bits_mask_0[0]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_0_T_1 = io_enq_valid_0 & _in_mask_0_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_0 = _in_mask_0_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign _in_uops_0_is_sfb_T = io_enq_bits_sfbs_0_0 \| io_enq_bits_shadowed_mask_0_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_0_is_sfb = _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [39:0] _in_uops_0_debug_pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_0_debug_pc_T_1 = {_in_uops_0_debug_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_0_debug_pc_T_2 = ~_in_uops_0_debug_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_0_debug_pc_T_3 = {1'h0, _in_uops_0_debug_pc_T_2}; // @[frontend.scala:147:31] wire [39:0] _in_uops_0_debug_pc_T_4 = _in_uops_0_debug_pc_T_3[39:0]; // @[fetch-buffer.scala:107:61] wire [40:0] _in_uops_0_debug_pc_T_5 = {1'h0, _in_uops_0_debug_pc_T_4} - 41'h2; // @[fetch-buffer.scala:107:{61,81}] wire [39:0] _in_uops_0_debug_pc_T_6 = _in_uops_0_debug_pc_T_5[39:0]; // @[fetch-buffer.scala:107:81] assign in_uops_0_debug_pc = io_enq_bits_edge_inst_0_0 ? _in_uops_0_debug_pc_T_6 : pc; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :100:33, :106:41, :107:{32,81}] wire [39:0] _in_uops_0_pc_lob_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_0_pc_lob_T_1 = {_in_uops_0_pc_lob_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_0_pc_lob_T_2 = ~_in_uops_0_pc_lob_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_0_pc_lob_T_3 = {1'h0, _in_uops_0_pc_lob_T_2}; // @[frontend.scala:147:31] wire [39:0] _in_uops_0_pc_lob_T_4 = _in_uops_0_pc_lob_T_3[39:0]; // @[fetch-buffer.scala:108:61] assign in_uops_0_pc_lob = io_enq_bits_edge_inst_0_0 ? _in_uops_0_pc_lob_T_4[5:0] : pc[5:0]; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :101:33, :106:41, :108:{32,61}] wire [1:0] _in_uops_0_is_rvc_T = io_enq_bits_insts_0_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_0_is_rvc_T_1 = _in_uops_0_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_0_is_rvc = _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_0_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h0; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_0_taken_T_1 = _in_uops_0_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_0_taken = _in_uops_0_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_4 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_5 = {_pc_T_4[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_6 = ~_pc_T_5; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_7 = {1'h0, _pc_T_6} + 41'h2; // @[frontend.scala:147:31] assign pc_1 = _pc_T_7[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_1_debug_pc = pc_1; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_1_T = io_enq_bits_mask_0[1]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_1_T_1 = io_enq_valid_0 & _in_mask_1_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_1 = _in_mask_1_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_1_pc_lob = pc_1[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_1_is_sfb_T = io_enq_bits_sfbs_1_0 \| io_enq_bits_shadowed_mask_1_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_1_is_sfb = _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_1_is_rvc_T = io_enq_bits_insts_1_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_1_is_rvc_T_1 = _in_uops_1_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_1_is_rvc = _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_1_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h1; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_1_taken_T_1 = _in_uops_1_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_1_taken = _in_uops_1_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_8 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_9 = {_pc_T_8[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_10 = ~_pc_T_9; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_11 = {1'h0, _pc_T_10} + 41'h4; // @[frontend.scala:147:31] assign pc_2 = _pc_T_11[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_2_debug_pc = pc_2; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_2_T = io_enq_bits_mask_0[2]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_2_T_1 = io_enq_valid_0 & _in_mask_2_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_2 = _in_mask_2_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_2_pc_lob = pc_2[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_2_is_sfb_T = io_enq_bits_sfbs_2_0 \| io_enq_bits_shadowed_mask_2_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_2_is_sfb = _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_2_is_rvc_T = io_enq_bits_insts_2_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_2_is_rvc_T_1 = _in_uops_2_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_2_is_rvc = _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_2_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h2; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_2_taken_T_1 = _in_uops_2_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_2_taken = _in_uops_2_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_12 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_13 = {_pc_T_12[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_14 = ~_pc_T_13; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_15 = {1'h0, _pc_T_14} + 41'h6; // @[frontend.scala:147:31] assign pc_3 = _pc_T_15[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_3_debug_pc = pc_3; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_3_T = io_enq_bits_mask_0[3]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_3_T_1 = io_enq_valid_0 & _in_mask_3_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_3 = _in_mask_3_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_3_pc_lob = pc_3[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_3_is_sfb_T = io_enq_bits_sfbs_3_0 \| io_enq_bits_shadowed_mask_3_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_3_is_sfb = _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_3_is_rvc_T = io_enq_bits_insts_3_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_3_is_rvc_T_1 = _in_uops_3_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_3_is_rvc = _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_3_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h3; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_3_taken_T_1 = _in_uops_3_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_3_taken = _in_uops_3_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_16 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_17 = {_pc_T_16[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_18 = ~_pc_T_17; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_19 = {1'h0, _pc_T_18} + 41'h8; // @[frontend.scala:147:31] wire [39:0] pc_4 = _pc_T_19[39:0]; // @[fetch-buffer.scala:95:43] wire _in_mask_4_T = io_enq_bits_mask_0[4]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_4_T_1 = io_enq_valid_0 & _in_mask_4_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_4 = _in_mask_4_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign _in_uops_4_is_sfb_T = io_enq_bits_sfbs_4_0 \| io_enq_bits_shadowed_mask_4_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_4_is_sfb = _in_uops_4_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [39:0] _in_uops_4_debug_pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_4_debug_pc_T_1 = {_in_uops_4_debug_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_4_debug_pc_T_2 = ~_in_uops_4_debug_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_4_debug_pc_T_3 = {1'h0, _in_uops_4_debug_pc_T_2} + 41'h8; // @[frontend.scala:147:31] wire [39:0] _in_uops_4_debug_pc_T_4 = _in_uops_4_debug_pc_T_3[39:0]; // @[fetch-buffer.scala:107:61] wire [40:0] _in_uops_4_debug_pc_T_5 = {1'h0, _in_uops_4_debug_pc_T_4} - 41'h2; // @[fetch-buffer.scala:107:{61,81}] wire [39:0] _in_uops_4_debug_pc_T_6 = _in_uops_4_debug_pc_T_5[39:0]; // @[fetch-buffer.scala:107:81] assign in_uops_4_debug_pc = io_enq_bits_edge_inst_1_0 ? _in_uops_4_debug_pc_T_6 : pc_4; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :100:33, :106:41, :107:{32,81}] wire [39:0] _in_uops_4_pc_lob_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_4_pc_lob_T_1 = {_in_uops_4_pc_lob_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_4_pc_lob_T_2 = ~_in_uops_4_pc_lob_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_4_pc_lob_T_3 = {1'h0, _in_uops_4_pc_lob_T_2} + 41'h8; // @[frontend.scala:147:31] wire [39:0] _in_uops_4_pc_lob_T_4 = _in_uops_4_pc_lob_T_3[39:0]; // @[fetch-buffer.scala:108:61] assign in_uops_4_pc_lob = io_enq_bits_edge_inst_1_0 ? _in_uops_4_pc_lob_T_4[5:0] : pc_4[5:0]; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :101:33, :106:41, :108:{32,61}] wire [1:0] _in_uops_4_is_rvc_T = io_enq_bits_insts_4_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_4_is_rvc_T_1 = _in_uops_4_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_4_is_rvc = _in_uops_4_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_4_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h4; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_4_taken_T_1 = _in_uops_4_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_4_taken = _in_uops_4_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_20 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_21 = {_pc_T_20[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_22 = ~_pc_T_21; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_23 = {1'h0, _pc_T_22} + 41'hA; // @[frontend.scala:147:31] assign pc_5 = _pc_T_23[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_5_debug_pc = pc_5; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_5_T = io_enq_bits_mask_0[5]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_5_T_1 = io_enq_valid_0 & _in_mask_5_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_5 = _in_mask_5_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_5_pc_lob = pc_5[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_5_is_sfb_T = io_enq_bits_sfbs_5_0 \| io_enq_bits_shadowed_mask_5_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_5_is_sfb = _in_uops_5_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_5_is_rvc_T = io_enq_bits_insts_5_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_5_is_rvc_T_1 = _in_uops_5_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_5_is_rvc = _in_uops_5_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_5_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h5; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_5_taken_T_1 = _in_uops_5_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_5_taken = _in_uops_5_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_24 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_25 = {_pc_T_24[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_26 = ~_pc_T_25; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_27 = {1'h0, _pc_T_26} + 41'hC; // @[frontend.scala:147:31] assign pc_6 = _pc_T_27[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_6_debug_pc = pc_6; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_6_T = io_enq_bits_mask_0[6]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_6_T_1 = io_enq_valid_0 & _in_mask_6_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_6 = _in_mask_6_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_6_pc_lob = pc_6[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_6_is_sfb_T = io_enq_bits_sfbs_6_0 \| io_enq_bits_shadowed_mask_6_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_6_is_sfb = _in_uops_6_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_6_is_rvc_T = io_enq_bits_insts_6_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_6_is_rvc_T_1 = _in_uops_6_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_6_is_rvc = _in_uops_6_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_6_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h6; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_6_taken_T_1 = _in_uops_6_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_6_taken = _in_uops_6_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_28 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_29 = {_pc_T_28[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_30 = ~_pc_T_29; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_31 = {1'h0, _pc_T_30} + 41'hE; // @[frontend.scala:147:31] assign pc_7 = _pc_T_31[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_7_debug_pc = pc_7; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_7_T = io_enq_bits_mask_0[7]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_7_T_1 = io_enq_valid_0 & _in_mask_7_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_7 = _in_mask_7_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_7_pc_lob = pc_7[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_7_is_sfb_T = io_enq_bits_sfbs_7_0 \| io_enq_bits_shadowed_mask_7_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_7_is_sfb = _in_uops_7_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_7_is_rvc_T = io_enq_bits_insts_7_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_7_is_rvc_T_1 = _in_uops_7_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_7_is_rvc = _in_uops_7_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_7_taken_T = &io_enq_bits_cfi_idx_bits_0; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_7_taken_T_1 = _in_uops_7_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_7_taken = _in_uops_7_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [23:0] enq_idxs_1; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_2; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_3; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_4; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_5; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_6; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_7; // @[fetch-buffer.scala:128:22] wire [23:0] _T_2 = {_might_hit_head_T, tail[23]}; // @[fetch-buffer.scala:62:21, :75:{11,24}, :132:8] assign enq_idxs_1 = in_mask_0 ? _T_2 : tail; // @[fetch-buffer.scala:62:21, :87:21, :128:22, :132:8, :138:18] wire [23:0] _T_6 = {enq_idxs_1[22:0], enq_idxs_1[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_2 = in_mask_1 ? _T_6 : enq_idxs_1; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_10 = {enq_idxs_2[22:0], enq_idxs_2[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_3 = in_mask_2 ? _T_10 : enq_idxs_2; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_14 = {enq_idxs_3[22:0], enq_idxs_3[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_4 = in_mask_3 ? _T_14 : enq_idxs_3; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_18 = {enq_idxs_4[22:0], enq_idxs_4[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_5 = in_mask_4 ? _T_18 : enq_idxs_4; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_22 = {enq_idxs_5[22:0], enq_idxs_5[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_6 = in_mask_5 ? _T_22 : enq_idxs_5; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_26 = {enq_idxs_6[22:0], enq_idxs_6[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_7 = in_mask_6 ? _T_26 : enq_idxs_6; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire _tail_collisions_T = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_4 = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_8 = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_1 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_2 = _tail_collisions_T_1; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_3 = _tail_collisions_T & _tail_collisions_T_2; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_0 = _tail_collisions_T_3; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_7 = _tail_collisions_T_4; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_5 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_1 = _tail_collisions_T_7; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_11 = _tail_collisions_T_8; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_9 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_2 = _tail_collisions_T_11; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_12 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_16 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_20 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_13 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_14 = _tail_collisions_T_13; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_15 = _tail_collisions_T_12 & _tail_collisions_T_14; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_3 = _tail_collisions_T_15; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_19 = _tail_collisions_T_16; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_17 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_4 = _tail_collisions_T_19; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_23 = _tail_collisions_T_20; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_21 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_5 = _tail_collisions_T_23; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_24 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_28 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_32 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_25 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_26 = _tail_collisions_T_25; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_27 = _tail_collisions_T_24 & _tail_collisions_T_26; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_6 = _tail_collisions_T_27; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_31 = _tail_collisions_T_28; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_29 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_7 = _tail_collisions_T_31; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_35 = _tail_collisions_T_32; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_33 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_8 = _tail_collisions_T_35; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_36 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_40 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_44 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_37 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_38 = _tail_collisions_T_37; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_39 = _tail_collisions_T_36 & _tail_collisions_T_38; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_9 = _tail_collisions_T_39; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_43 = _tail_collisions_T_40; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_41 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_10 = _tail_collisions_T_43; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_47 = _tail_collisions_T_44; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_45 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_11 = _tail_collisions_T_47; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_48 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_52 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_56 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_49 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_50 = _tail_collisions_T_49; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_51 = _tail_collisions_T_48 & _tail_collisions_T_50; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_12 = _tail_collisions_T_51; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_55 = _tail_collisions_T_52; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_53 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_13 = _tail_collisions_T_55; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_59 = _tail_collisions_T_56; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_57 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_14 = _tail_collisions_T_59; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_60 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_64 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_68 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_61 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_62 = _tail_collisions_T_61; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_63 = _tail_collisions_T_60 & _tail_collisions_T_62; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_15 = _tail_collisions_T_63; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_67 = _tail_collisions_T_64; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_65 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_16 = _tail_collisions_T_67; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_71 = _tail_collisions_T_68; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_69 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_17 = _tail_collisions_T_71; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_72 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_76 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_80 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_73 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_74 = _tail_collisions_T_73; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_75 = _tail_collisions_T_72 & _tail_collisions_T_74; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_18 = _tail_collisions_T_75; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_79 = _tail_collisions_T_76; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_77 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_19 = _tail_collisions_T_79; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_83 = _tail_collisions_T_80; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_81 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_20 = _tail_collisions_T_83; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_84 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_88 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_92 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _head_T_1 = head[7]; // @[fetch-buffer.scala:61:21, :132:24, :155:31] wire _tail_collisions_T_85 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_86 = _tail_collisions_T_85; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_87 = _tail_collisions_T_84 & _tail_collisions_T_86; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_21 = _tail_collisions_T_87; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_91 = _tail_collisions_T_88; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_89 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_22 = _tail_collisions_T_91; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_95 = _tail_collisions_T_92; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_93 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_23 = _tail_collisions_T_95; // @[fetch-buffer.scala:154:32, :155:45] wire [1:0] tail_collisions_lo_lo_lo_hi = {_tail_collisions_WIRE_2, _tail_collisions_WIRE_1}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_lo_lo = {tail_collisions_lo_lo_lo_hi, _tail_collisions_WIRE_0}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_lo_lo_hi_hi = {_tail_collisions_WIRE_5, _tail_collisions_WIRE_4}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_lo_hi = {tail_collisions_lo_lo_hi_hi, _tail_collisions_WIRE_3}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_lo_lo = {tail_collisions_lo_lo_hi, tail_collisions_lo_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_lo_hi_lo_hi = {_tail_collisions_WIRE_8, _tail_collisions_WIRE_7}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_hi_lo = {tail_collisions_lo_hi_lo_hi, _tail_collisions_WIRE_6}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_lo_hi_hi_hi = {_tail_collisions_WIRE_11, _tail_collisions_WIRE_10}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_hi_hi = {tail_collisions_lo_hi_hi_hi, _tail_collisions_WIRE_9}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_lo_hi = {tail_collisions_lo_hi_hi, tail_collisions_lo_hi_lo}; // @[fetch-buffer.scala:155:90] wire [11:0] tail_collisions_lo = {tail_collisions_lo_hi, tail_collisions_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_hi_lo_lo_hi = {_tail_collisions_WIRE_14, _tail_collisions_WIRE_13}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_lo_lo = {tail_collisions_hi_lo_lo_hi, _tail_collisions_WIRE_12}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_hi_lo_hi_hi = {_tail_collisions_WIRE_17, _tail_collisions_WIRE_16}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_lo_hi = {tail_collisions_hi_lo_hi_hi, _tail_collisions_WIRE_15}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_hi_lo = {tail_collisions_hi_lo_hi, tail_collisions_hi_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_hi_hi_lo_hi = {_tail_collisions_WIRE_20, _tail_collisions_WIRE_19}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_hi_lo = {tail_collisions_hi_hi_lo_hi, _tail_collisions_WIRE_18}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_hi_hi_hi_hi = {_tail_collisions_WIRE_23, _tail_collisions_WIRE_22}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_hi_hi = {tail_collisions_hi_hi_hi_hi, _tail_collisions_WIRE_21}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_hi_hi = {tail_collisions_hi_hi_hi, tail_collisions_hi_hi_lo}; // @[fetch-buffer.scala:155:90] wire [11:0] tail_collisions_hi = {tail_collisions_hi_hi, tail_collisions_hi_lo}; // @[fetch-buffer.scala:155:90] wire [23:0] _tail_collisions_T_96 = {tail_collisions_hi, tail_collisions_lo}; // @[fetch-buffer.scala:155:90] wire [23:0] tail_collisions = _tail_collisions_T_96 & tail; // @[fetch-buffer.scala:62:21, :155:{90,97}] wire [2:0] _slot_will_hit_tail_T = tail_collisions[2:0]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_1 = tail_collisions[5:3]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_2 = tail_collisions[8:6]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_3 = tail_collisions[11:9]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_4 = tail_collisions[14:12]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_5 = tail_collisions[17:15]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_6 = tail_collisions[20:18]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_7 = tail_collisions[23:21]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_8 = _slot_will_hit_tail_T \| _slot_will_hit_tail_T_1; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_9 = _slot_will_hit_tail_T_8 \| _slot_will_hit_tail_T_2; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_10 = _slot_will_hit_tail_T_9 \| _slot_will_hit_tail_T_3; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_11 = _slot_will_hit_tail_T_10 \| _slot_will_hit_tail_T_4; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_12 = _slot_will_hit_tail_T_11 \| _slot_will_hit_tail_T_5; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_13 = _slot_will_hit_tail_T_12 \| _slot_will_hit_tail_T_6; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] slot_will_hit_tail = _slot_will_hit_tail_T_13 \| _slot_will_hit_tail_T_7; // @[fetch-buffer.scala:156:{70,112}] wire will_hit_tail = \|slot_will_hit_tail; // @[fetch-buffer.scala:156:112, :157:42] wire _do_deq_T = ~will_hit_tail; // @[fetch-buffer.scala:157:42, :159:32] wire do_deq = io_deq_ready_0 & _do_deq_T; // @[fetch-buffer.scala:40:7, :159:{29,32}] wire [3:0] _deq_valids_T = {1'h0, slot_will_hit_tail}; // @[util.scala:394:30] wire [2:0] _deq_valids_T_1 = _deq_valids_T[2:0]; // @[util.scala:394:{30,37}] wire [3:0] _deq_valids_T_2 = {slot_will_hit_tail, 1'h0}; // @[util.scala:394:30] wire [2:0] _deq_valids_T_3 = _deq_valids_T_2[2:0]; // @[util.scala:394:{30,37}] wire [5:0] _deq_valids_T_4 = {1'h0, slot_will_hit_tail, 2'h0}; // @[util.scala:394:30] wire [2:0] _deq_valids_T_5 = _deq_valids_T_4[2:0]; // @[util.scala:394:{30,37}] wire [2:0] _deq_valids_T_6 = _deq_valids_T_1 \| _deq_valids_T_3; // @[util.scala:394:{37,54}] wire [2:0] _deq_valids_T_7 = _deq_valids_T_6 \| _deq_valids_T_5; // @[util.scala:394:{37,54}] wire [2:0] _deq_valids_T_8 = ~_deq_valids_T_7; // @[util.scala:394:54] wire deq_valids_0 = _deq_valids_T_8[0]; // @[fetch-buffer.scala:161:{21,53}] wire deq_valids_1 = _deq_valids_T_8[1]; // @[fetch-buffer.scala:161:{21,53}] wire deq_valids_2 = _deq_valids_T_8[2]; // @[fetch-buffer.scala:161:{21,53}] assign io_deq_bits_uops_0_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_0_debug_fsrc : 3'h0) \| (head[1] ? deq_vec_1_0_debug_fsrc : 3'h0) \| (head[2] ? deq_vec_2_0_debug_fsrc : 3'h0) \| (head[3] ? deq_vec_3_0_debug_fsrc : 3'h0) \| (head[4] ? deq_vec_4_0_debug_fsrc : 3'h0) \| (head[5] ? deq_vec_5_0_debug_fsrc : 3'h0) \| (head[6] ? deq_vec_6_0_debug_fsrc : 3'h0) \| (head[7] ? deq_vec_7_0_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_0_bp_xcpt_if \| head[1] & deq_vec_1_0_bp_xcpt_if \| head[2] & deq_vec_2_0_bp_xcpt_if \| head[3] & deq_vec_3_0_bp_xcpt_if \| head[4] & deq_vec_4_0_bp_xcpt_if \| head[5] & deq_vec_5_0_bp_xcpt_if \| head[6] & deq_vec_6_0_bp_xcpt_if \| head[7] & deq_vec_7_0_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_bp_debug_if_0 = head[0] & deq_vec_0_0_bp_debug_if \| head[1] & deq_vec_1_0_bp_debug_if \| head[2] & deq_vec_2_0_bp_debug_if \| head[3] & deq_vec_3_0_bp_debug_if \| head[4] & deq_vec_4_0_bp_debug_if \| head[5] & deq_vec_5_0_bp_debug_if \| head[6] & deq_vec_6_0_bp_debug_if \| head[7] & deq_vec_7_0_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_0_xcpt_ae_if \| head[1] & deq_vec_1_0_xcpt_ae_if \| head[2] & deq_vec_2_0_xcpt_ae_if \| head[3] & deq_vec_3_0_xcpt_ae_if \| head[4] & deq_vec_4_0_xcpt_ae_if \| head[5] & deq_vec_5_0_xcpt_ae_if \| head[6] & deq_vec_6_0_xcpt_ae_if \| head[7] & deq_vec_7_0_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_0_xcpt_pf_if \| head[1] & deq_vec_1_0_xcpt_pf_if \| head[2] & deq_vec_2_0_xcpt_pf_if \| head[3] & deq_vec_3_0_xcpt_pf_if \| head[4] & deq_vec_4_0_xcpt_pf_if \| head[5] & deq_vec_5_0_xcpt_pf_if \| head[6] & deq_vec_6_0_xcpt_pf_if \| head[7] & deq_vec_7_0_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_taken_0 = head[0] & deq_vec_0_0_taken \| head[1] & deq_vec_1_0_taken \| head[2] & deq_vec_2_0_taken \| head[3] & deq_vec_3_0_taken \| head[4] & deq_vec_4_0_taken \| head[5] & deq_vec_5_0_taken \| head[6] & deq_vec_6_0_taken \| head[7] & deq_vec_7_0_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_pc_lob_0 = (head[0] ? deq_vec_0_0_pc_lob : 6'h0) \| (head[1] ? deq_vec_1_0_pc_lob : 6'h0) \| (head[2] ? deq_vec_2_0_pc_lob : 6'h0) \| (head[3] ? deq_vec_3_0_pc_lob : 6'h0) \| (head[4] ? deq_vec_4_0_pc_lob : 6'h0) \| (head[5] ? deq_vec_5_0_pc_lob : 6'h0) \| (head[6] ? deq_vec_6_0_pc_lob : 6'h0) \| (head[7] ? deq_vec_7_0_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_edge_inst_0 = head[0] & deq_vec_0_0_edge_inst \| head[1] & deq_vec_1_0_edge_inst \| head[2] & deq_vec_2_0_edge_inst \| head[3] & deq_vec_3_0_edge_inst \| head[4] & deq_vec_4_0_edge_inst \| head[5] & deq_vec_5_0_edge_inst \| head[6] & deq_vec_6_0_edge_inst \| head[7] & deq_vec_7_0_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_ftq_idx_0 = (head[0] ? deq_vec_0_0_ftq_idx : 5'h0) \| (head[1] ? deq_vec_1_0_ftq_idx : 5'h0) \| (head[2] ? deq_vec_2_0_ftq_idx : 5'h0) \| (head[3] ? deq_vec_3_0_ftq_idx : 5'h0) \| (head[4] ? deq_vec_4_0_ftq_idx : 5'h0) \| (head[5] ? deq_vec_5_0_ftq_idx : 5'h0) \| (head[6] ? deq_vec_6_0_ftq_idx : 5'h0) \| (head[7] ? deq_vec_7_0_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_is_sfb_0 = head[0] & deq_vec_0_0_is_sfb \| head[1] & deq_vec_1_0_is_sfb \| head[2] & deq_vec_2_0_is_sfb \| head[3] & deq_vec_3_0_is_sfb \| head[4] & deq_vec_4_0_is_sfb \| head[5] & deq_vec_5_0_is_sfb \| head[6] & deq_vec_6_0_is_sfb \| head[7] & deq_vec_7_0_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_debug_pc_0 = (head[0] ? deq_vec_0_0_debug_pc : 40'h0) \| (head[1] ? deq_vec_1_0_debug_pc : 40'h0) \| (head[2] ? deq_vec_2_0_debug_pc : 40'h0) \| (head[3] ? deq_vec_3_0_debug_pc : 40'h0) \| (head[4] ? deq_vec_4_0_debug_pc : 40'h0) \| (head[5] ? deq_vec_5_0_debug_pc : 40'h0) \| (head[6] ? deq_vec_6_0_debug_pc : 40'h0) \| (head[7] ? deq_vec_7_0_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_is_rvc_0 = head[0] & deq_vec_0_0_is_rvc \| head[1] & deq_vec_1_0_is_rvc \| head[2] & deq_vec_2_0_is_rvc \| head[3] & deq_vec_3_0_is_rvc \| head[4] & deq_vec_4_0_is_rvc \| head[5] & deq_vec_5_0_is_rvc \| head[6] & deq_vec_6_0_is_rvc \| head[7] & deq_vec_7_0_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_debug_inst_0 = (head[0] ? deq_vec_0_0_debug_inst : 32'h0) \| (head[1] ? deq_vec_1_0_debug_inst : 32'h0) \| (head[2] ? deq_vec_2_0_debug_inst : 32'h0) \| (head[3] ? deq_vec_3_0_debug_inst : 32'h0) \| (head[4] ? deq_vec_4_0_debug_inst : 32'h0) \| (head[5] ? deq_vec_5_0_debug_inst : 32'h0) \| (head[6] ? deq_vec_6_0_debug_inst : 32'h0) \| (head[7] ? deq_vec_7_0_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_inst_0 = (head[0] ? deq_vec_0_0_inst : 32'h0) \| (head[1] ? deq_vec_1_0_inst : 32'h0) \| (head[2] ? deq_vec_2_0_inst : 32'h0) \| (head[3] ? deq_vec_3_0_inst : 32'h0) \| (head[4] ? deq_vec_4_0_inst : 32'h0) \| (head[5] ? deq_vec_5_0_inst : 32'h0) \| (head[6] ? deq_vec_6_0_inst : 32'h0) \| (head[7] ? deq_vec_7_0_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_1_debug_fsrc : 3'h0) \| (head[1] ? deq_vec_1_1_debug_fsrc : 3'h0) \| (head[2] ? deq_vec_2_1_debug_fsrc : 3'h0) \| (head[3] ? deq_vec_3_1_debug_fsrc : 3'h0) \| (head[4] ? deq_vec_4_1_debug_fsrc : 3'h0) \| (head[5] ? deq_vec_5_1_debug_fsrc : 3'h0) \| (head[6] ? deq_vec_6_1_debug_fsrc : 3'h0) \| (head[7] ? deq_vec_7_1_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_1_bp_xcpt_if \| head[1] & deq_vec_1_1_bp_xcpt_if \| head[2] & deq_vec_2_1_bp_xcpt_if \| head[3] & deq_vec_3_1_bp_xcpt_if \| head[4] & deq_vec_4_1_bp_xcpt_if \| head[5] & deq_vec_5_1_bp_xcpt_if \| head[6] & deq_vec_6_1_bp_xcpt_if \| head[7] & deq_vec_7_1_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_bp_debug_if_0 = head[0] & deq_vec_0_1_bp_debug_if \| head[1] & deq_vec_1_1_bp_debug_if \| head[2] & deq_vec_2_1_bp_debug_if \| head[3] & deq_vec_3_1_bp_debug_if \| head[4] & deq_vec_4_1_bp_debug_if \| head[5] & deq_vec_5_1_bp_debug_if \| head[6] & deq_vec_6_1_bp_debug_if \| head[7] & deq_vec_7_1_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_1_xcpt_ae_if \| head[1] & deq_vec_1_1_xcpt_ae_if \| head[2] & deq_vec_2_1_xcpt_ae_if \| head[3] & deq_vec_3_1_xcpt_ae_if \| head[4] & deq_vec_4_1_xcpt_ae_if \| head[5] & deq_vec_5_1_xcpt_ae_if \| head[6] & deq_vec_6_1_xcpt_ae_if \| head[7] & deq_vec_7_1_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_1_xcpt_pf_if \| head[1] & deq_vec_1_1_xcpt_pf_if \| head[2] & deq_vec_2_1_xcpt_pf_if \| head[3] & deq_vec_3_1_xcpt_pf_if \| head[4] & deq_vec_4_1_xcpt_pf_if \| head[5] & deq_vec_5_1_xcpt_pf_if \| head[6] & deq_vec_6_1_xcpt_pf_if \| head[7] & deq_vec_7_1_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_taken_0 = head[0] & deq_vec_0_1_taken \| head[1] & deq_vec_1_1_taken \| head[2] & deq_vec_2_1_taken \| head[3] & deq_vec_3_1_taken \| head[4] & deq_vec_4_1_taken \| head[5] & deq_vec_5_1_taken \| head[6] & deq_vec_6_1_taken \| head[7] & deq_vec_7_1_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_pc_lob_0 = (head[0] ? deq_vec_0_1_pc_lob : 6'h0) \| (head[1] ? deq_vec_1_1_pc_lob : 6'h0) \| (head[2] ? deq_vec_2_1_pc_lob : 6'h0) \| (head[3] ? deq_vec_3_1_pc_lob : 6'h0) \| (head[4] ? deq_vec_4_1_pc_lob : 6'h0) \| (head[5] ? deq_vec_5_1_pc_lob : 6'h0) \| (head[6] ? deq_vec_6_1_pc_lob : 6'h0) \| (head[7] ? deq_vec_7_1_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_edge_inst_0 = head[0] & deq_vec_0_1_edge_inst \| head[1] & deq_vec_1_1_edge_inst \| head[2] & deq_vec_2_1_edge_inst \| head[3] & deq_vec_3_1_edge_inst \| head[4] & deq_vec_4_1_edge_inst \| head[5] & deq_vec_5_1_edge_inst \| head[6] & deq_vec_6_1_edge_inst \| head[7] & deq_vec_7_1_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_ftq_idx_0 = (head[0] ? deq_vec_0_1_ftq_idx : 5'h0) \| (head[1] ? deq_vec_1_1_ftq_idx : 5'h0) \| (head[2] ? deq_vec_2_1_ftq_idx : 5'h0) \| (head[3] ? deq_vec_3_1_ftq_idx : 5'h0) \| (head[4] ? deq_vec_4_1_ftq_idx : 5'h0) \| (head[5] ? deq_vec_5_1_ftq_idx : 5'h0) \| (head[6] ? deq_vec_6_1_ftq_idx : 5'h0) \| (head[7] ? deq_vec_7_1_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_is_sfb_0 = head[0] & deq_vec_0_1_is_sfb \| head[1] & deq_vec_1_1_is_sfb \| head[2] & deq_vec_2_1_is_sfb \| head[3] & deq_vec_3_1_is_sfb \| head[4] & deq_vec_4_1_is_sfb \| head[5] & deq_vec_5_1_is_sfb \| head[6] & deq_vec_6_1_is_sfb \| head[7] & deq_vec_7_1_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_pc_0 = (head[0] ? deq_vec_0_1_debug_pc : 40'h0) \| (head[1] ? deq_vec_1_1_debug_pc : 40'h0) \| (head[2] ? deq_vec_2_1_debug_pc : 40'h0) \| (head[3] ? deq_vec_3_1_debug_pc : 40'h0) \| (head[4] ? deq_vec_4_1_debug_pc : 40'h0) \| (head[5] ? deq_vec_5_1_debug_pc : 40'h0) \| (head[6] ? deq_vec_6_1_debug_pc : 40'h0) \| (head[7] ? deq_vec_7_1_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_is_rvc_0 = head[0] & deq_vec_0_1_is_rvc \| head[1] & deq_vec_1_1_is_rvc \| head[2] & deq_vec_2_1_is_rvc \| head[3] & deq_vec_3_1_is_rvc \| head[4] & deq_vec_4_1_is_rvc \| head[5] & deq_vec_5_1_is_rvc \| head[6] & deq_vec_6_1_is_rvc \| head[7] & deq_vec_7_1_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_inst_0 = (head[0] ? deq_vec_0_1_debug_inst : 32'h0) \| (head[1] ? deq_vec_1_1_debug_inst : 32'h0) \| (head[2] ? deq_vec_2_1_debug_inst : 32'h0) \| (head[3] ? deq_vec_3_1_debug_inst : 32'h0) \| (head[4] ? deq_vec_4_1_debug_inst : 32'h0) \| (head[5] ? deq_vec_5_1_debug_inst : 32'h0) \| (head[6] ? deq_vec_6_1_debug_inst : 32'h0) \| (head[7] ? deq_vec_7_1_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_inst_0 = (head[0] ? deq_vec_0_1_inst : 32'h0) \| (head[1] ? deq_vec_1_1_inst : 32'h0) \| (head[2] ? deq_vec_2_1_inst : 32'h0) \| (head[3] ? deq_vec_3_1_inst : 32'h0) \| (head[4] ? deq_vec_4_1_inst : 32'h0) \| (head[5] ? deq_vec_5_1_inst : 32'h0) \| (head[6] ? deq_vec_6_1_inst : 32'h0) \| (head[7] ? deq_vec_7_1_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_2_debug_fsrc : 3'h0) \| (head[1] ? deq_vec_1_2_debug_fsrc : 3'h0) \| (head[2] ? deq_vec_2_2_debug_fsrc : 3'h0) \| (head[3] ? deq_vec_3_2_debug_fsrc : 3'h0) \| (head[4] ? deq_vec_4_2_debug_fsrc : 3'h0) \| (head[5] ? deq_vec_5_2_debug_fsrc : 3'h0) \| (head[6] ? deq_vec_6_2_debug_fsrc : 3'h0) \| (head[7] ? deq_vec_7_2_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_2_bp_xcpt_if \| head[1] & deq_vec_1_2_bp_xcpt_if \| head[2] & deq_vec_2_2_bp_xcpt_if \| head[3] & deq_vec_3_2_bp_xcpt_if \| head[4] & deq_vec_4_2_bp_xcpt_if \| head[5] & deq_vec_5_2_bp_xcpt_if \| head[6] & deq_vec_6_2_bp_xcpt_if \| head[7] & deq_vec_7_2_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_bp_debug_if_0 = head[0] & deq_vec_0_2_bp_debug_if \| head[1] & deq_vec_1_2_bp_debug_if \| head[2] & deq_vec_2_2_bp_debug_if \| head[3] & deq_vec_3_2_bp_debug_if \| head[4] & deq_vec_4_2_bp_debug_if \| head[5] & deq_vec_5_2_bp_debug_if \| head[6] & deq_vec_6_2_bp_debug_if \| head[7] & deq_vec_7_2_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_2_xcpt_ae_if \| head[1] & deq_vec_1_2_xcpt_ae_if \| head[2] & deq_vec_2_2_xcpt_ae_if \| head[3] & deq_vec_3_2_xcpt_ae_if \| head[4] & deq_vec_4_2_xcpt_ae_if \| head[5] & deq_vec_5_2_xcpt_ae_if \| head[6] & deq_vec_6_2_xcpt_ae_if \| head[7] & deq_vec_7_2_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_2_xcpt_pf_if \| head[1] & deq_vec_1_2_xcpt_pf_if \| head[2] & deq_vec_2_2_xcpt_pf_if \| head[3] & deq_vec_3_2_xcpt_pf_if \| head[4] & deq_vec_4_2_xcpt_pf_if \| head[5] & deq_vec_5_2_xcpt_pf_if \| head[6] & deq_vec_6_2_xcpt_pf_if \| head[7] & deq_vec_7_2_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_taken_0 = head[0] & deq_vec_0_2_taken \| head[1] & deq_vec_1_2_taken \| head[2] & deq_vec_2_2_taken \| head[3] & deq_vec_3_2_taken \| head[4] & deq_vec_4_2_taken \| head[5] & deq_vec_5_2_taken \| head[6] & deq_vec_6_2_taken \| head[7] & deq_vec_7_2_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_pc_lob_0 = (head[0] ? deq_vec_0_2_pc_lob : 6'h0) \| (head[1] ? deq_vec_1_2_pc_lob : 6'h0) \| (head[2] ? deq_vec_2_2_pc_lob : 6'h0) \| (head[3] ? deq_vec_3_2_pc_lob : 6'h0) \| (head[4] ? deq_vec_4_2_pc_lob : 6'h0) \| (head[5] ? deq_vec_5_2_pc_lob : 6'h0) \| (head[6] ? deq_vec_6_2_pc_lob : 6'h0) \| (head[7] ? deq_vec_7_2_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_edge_inst_0 = head[0] & deq_vec_0_2_edge_inst \| head[1] & deq_vec_1_2_edge_inst \| head[2] & deq_vec_2_2_edge_inst \| head[3] & deq_vec_3_2_edge_inst \| head[4] & deq_vec_4_2_edge_inst \| head[5] & deq_vec_5_2_edge_inst \| head[6] & deq_vec_6_2_edge_inst \| head[7] & deq_vec_7_2_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_ftq_idx_0 = (head[0] ? deq_vec_0_2_ftq_idx : 5'h0) \| (head[1] ? deq_vec_1_2_ftq_idx : 5'h0) \| (head[2] ? deq_vec_2_2_ftq_idx : 5'h0) \| (head[3] ? deq_vec_3_2_ftq_idx : 5'h0) \| (head[4] ? deq_vec_4_2_ftq_idx : 5'h0) \| (head[5] ? deq_vec_5_2_ftq_idx : 5'h0) \| (head[6] ? deq_vec_6_2_ftq_idx : 5'h0) \| (head[7] ? deq_vec_7_2_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_is_sfb_0 = head[0] & deq_vec_0_2_is_sfb \| head[1] & deq_vec_1_2_is_sfb \| head[2] & deq_vec_2_2_is_sfb \| head[3] & deq_vec_3_2_is_sfb \| head[4] & deq_vec_4_2_is_sfb \| head[5] & deq_vec_5_2_is_sfb \| head[6] & deq_vec_6_2_is_sfb \| head[7] & deq_vec_7_2_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_debug_pc_0 = (head[0] ? deq_vec_0_2_debug_pc : 40'h0) \| (head[1] ? deq_vec_1_2_debug_pc : 40'h0) \| (head[2] ? deq_vec_2_2_debug_pc : 40'h0) \| (head[3] ? deq_vec_3_2_debug_pc : 40'h0) \| (head[4] ? deq_vec_4_2_debug_pc : 40'h0) \| (head[5] ? deq_vec_5_2_debug_pc : 40'h0) \| (head[6] ? deq_vec_6_2_debug_pc : 40'h0) \| (head[7] ? deq_vec_7_2_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_is_rvc_0 = head[0] & deq_vec_0_2_is_rvc \| head[1] & deq_vec_1_2_is_rvc \| head[2] & deq_vec_2_2_is_rvc \| head[3] & deq_vec_3_2_is_rvc \| head[4] & deq_vec_4_2_is_rvc \| head[5] & deq_vec_5_2_is_rvc \| head[6] & deq_vec_6_2_is_rvc \| head[7] & deq_vec_7_2_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_debug_inst_0 = (head[0] ? deq_vec_0_2_debug_inst : 32'h0) \| (head[1] ? deq_vec_1_2_debug_inst : 32'h0) \| (head[2] ? deq_vec_2_2_debug_inst : 32'h0) \| (head[3] ? deq_vec_3_2_debug_inst : 32'h0) \| (head[4] ? deq_vec_4_2_debug_inst : 32'h0) \| (head[5] ? deq_vec_5_2_debug_inst : 32'h0) \| (head[6] ? deq_vec_6_2_debug_inst : 32'h0) \| (head[7] ? deq_vec_7_2_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_inst_0 = (head[0] ? deq_vec_0_2_inst : 32'h0) \| (head[1] ? deq_vec_1_2_inst : 32'h0) \| (head[2] ? deq_vec_2_2_inst : 32'h0) \| (head[3] ? deq_vec_3_2_inst : 32'h0) \| (head[4] ? deq_vec_4_2_inst : 32'h0) \| (head[5] ? deq_vec_5_2_inst : 32'h0) \| (head[6] ? deq_vec_6_2_inst : 32'h0) \| (head[7] ? deq_vec_7_2_inst : 32'h0); // @[Mux.scala:30:73] wire _io_deq_valid_T = deq_valids_0 \| deq_valids_1; // @[fetch-buffer.scala:161:53, :170:38] assign _io_deq_valid_T_1 = _io_deq_valid_T \| deq_valids_2; // @[fetch-buffer.scala:161:53, :170:38] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[fetch-buffer.scala:40:7, :170:38] wire [6:0] _head_T = head[6:0]; // @[fetch-buffer.scala:61:21, :132:12] wire [7:0] _head_T_2 = {_head_T, _head_T_1}; // @[fetch-buffer.scala:132:{8,12,24}] assign io_deq_bits_uops_0_valid_0 = ~reset & deq_valids_0; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] assign io_deq_bits_uops_1_valid_0 = ~reset & deq_valids_1; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] assign io_deq_bits_uops_2_valid_0 = ~reset & deq_valids_2; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] wire _T_101 = do_enq & in_mask_0; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_34 = _T_101 & enq_idxs_0[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_37 = _T_101 & enq_idxs_0[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_40 = _T_101 & enq_idxs_0[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_43 = _T_101 & enq_idxs_0[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_46 = _T_101 & enq_idxs_0[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_49 = _T_101 & enq_idxs_0[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_52 = _T_101 & enq_idxs_0[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_55 = _T_101 & enq_idxs_0[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_58 = _T_101 & enq_idxs_0[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_61 = _T_101 & enq_idxs_0[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_64 = _T_101 & enq_idxs_0[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_67 = _T_101 & enq_idxs_0[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_70 = _T_101 & enq_idxs_0[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_73 = _T_101 & enq_idxs_0[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_76 = _T_101 & enq_idxs_0[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_79 = _T_101 & enq_idxs_0[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_82 = _T_101 & enq_idxs_0[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_85 = _T_101 & enq_idxs_0[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_88 = _T_101 & enq_idxs_0[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_91 = _T_101 & enq_idxs_0[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_94 = _T_101 & enq_idxs_0[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_97 = _T_101 & enq_idxs_0[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_100 = _T_101 & enq_idxs_0[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_103 = _T_101 & enq_idxs_0[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_173 = do_enq & in_mask_1; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_106 = _T_173 & enq_idxs_1[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_109 = _T_173 & enq_idxs_1[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_112 = _T_173 & enq_idxs_1[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_115 = _T_173 & enq_idxs_1[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_118 = _T_173 & enq_idxs_1[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_121 = _T_173 & enq_idxs_1[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_124 = _T_173 & enq_idxs_1[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_127 = _T_173 & enq_idxs_1[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_130 = _T_173 & enq_idxs_1[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_133 = _T_173 & enq_idxs_1[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_136 = _T_173 & enq_idxs_1[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_139 = _T_173 & enq_idxs_1[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_142 = _T_173 & enq_idxs_1[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_145 = _T_173 & enq_idxs_1[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_148 = _T_173 & enq_idxs_1[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_151 = _T_173 & enq_idxs_1[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_154 = _T_173 & enq_idxs_1[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_157 = _T_173 & enq_idxs_1[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_160 = _T_173 & enq_idxs_1[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_163 = _T_173 & enq_idxs_1[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_166 = _T_173 & enq_idxs_1[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_169 = _T_173 & enq_idxs_1[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_172 = _T_173 & enq_idxs_1[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_175 = _T_173 & enq_idxs_1[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_245 = do_enq & in_mask_2; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_178 = _T_245 & enq_idxs_2[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_181 = _T_245 & enq_idxs_2[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_184 = _T_245 & enq_idxs_2[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_187 = _T_245 & enq_idxs_2[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_190 = _T_245 & enq_idxs_2[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_193 = _T_245 & enq_idxs_2[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_196 = _T_245 & enq_idxs_2[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_199 = _T_245 & enq_idxs_2[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_202 = _T_245 & enq_idxs_2[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_205 = _T_245 & enq_idxs_2[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_208 = _T_245 & enq_idxs_2[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_211 = _T_245 & enq_idxs_2[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_214 = _T_245 & enq_idxs_2[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_217 = _T_245 & enq_idxs_2[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_220 = _T_245 & enq_idxs_2[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_223 = _T_245 & enq_idxs_2[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_226 = _T_245 & enq_idxs_2[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_229 = _T_245 & enq_idxs_2[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_232 = _T_245 & enq_idxs_2[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_235 = _T_245 & enq_idxs_2[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_238 = _T_245 & enq_idxs_2[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_241 = _T_245 & enq_idxs_2[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_244 = _T_245 & enq_idxs_2[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_247 = _T_245 & enq_idxs_2[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_317 = do_enq & in_mask_3; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_250 = _T_317 & enq_idxs_3[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_253 = _T_317 & enq_idxs_3[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_256 = _T_317 & enq_idxs_3[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_259 = _T_317 & enq_idxs_3[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_262 = _T_317 & enq_idxs_3[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_265 = _T_317 & enq_idxs_3[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_268 = _T_317 & enq_idxs_3[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_271 = _T_317 & enq_idxs_3[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_274 = _T_317 & enq_idxs_3[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_277 = _T_317 & enq_idxs_3[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_280 = _T_317 & enq_idxs_3[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_283 = _T_317 & enq_idxs_3[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_286 = _T_317 & enq_idxs_3[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_289 = _T_317 & enq_idxs_3[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_292 = _T_317 & enq_idxs_3[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_295 = _T_317 & enq_idxs_3[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_298 = _T_317 & enq_idxs_3[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_301 = _T_317 & enq_idxs_3[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_304 = _T_317 & enq_idxs_3[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_307 = _T_317 & enq_idxs_3[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_310 = _T_317 & enq_idxs_3[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_313 = _T_317 & enq_idxs_3[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_316 = _T_317 & enq_idxs_3[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_319 = _T_317 & enq_idxs_3[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_389 = do_enq & in_mask_4; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_322 = _T_389 & enq_idxs_4[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_325 = _T_389 & enq_idxs_4[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_328 = _T_389 & enq_idxs_4[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_331 = _T_389 & enq_idxs_4[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_334 = _T_389 & enq_idxs_4[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_337 = _T_389 & enq_idxs_4[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_340 = _T_389 & enq_idxs_4[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_343 = _T_389 & enq_idxs_4[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_346 = _T_389 & enq_idxs_4[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_349 = _T_389 & enq_idxs_4[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_352 = _T_389 & enq_idxs_4[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_355 = _T_389 & enq_idxs_4[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_358 = _T_389 & enq_idxs_4[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_361 = _T_389 & enq_idxs_4[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_364 = _T_389 & enq_idxs_4[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_367 = _T_389 & enq_idxs_4[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_370 = _T_389 & enq_idxs_4[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_373 = _T_389 & enq_idxs_4[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_376 = _T_389 & enq_idxs_4[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_379 = _T_389 & enq_idxs_4[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_382 = _T_389 & enq_idxs_4[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_385 = _T_389 & enq_idxs_4[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_388 = _T_389 & enq_idxs_4[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_391 = _T_389 & enq_idxs_4[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_461 = do_enq & in_mask_5; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_394 = _T_461 & enq_idxs_5[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_397 = _T_461 & enq_idxs_5[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_400 = _T_461 & enq_idxs_5[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_403 = _T_461 & enq_idxs_5[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_406 = _T_461 & enq_idxs_5[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_409 = _T_461 & enq_idxs_5[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_412 = _T_461 & enq_idxs_5[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_415 = _T_461 & enq_idxs_5[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_418 = _T_461 & enq_idxs_5[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_421 = _T_461 & enq_idxs_5[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_424 = _T_461 & enq_idxs_5[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_427 = _T_461 & enq_idxs_5[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_430 = _T_461 & enq_idxs_5[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_433 = _T_461 & enq_idxs_5[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_436 = _T_461 & enq_idxs_5[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_439 = _T_461 & enq_idxs_5[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_442 = _T_461 & enq_idxs_5[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_445 = _T_461 & enq_idxs_5[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_448 = _T_461 & enq_idxs_5[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_451 = _T_461 & enq_idxs_5[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_454 = _T_461 & enq_idxs_5[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_457 = _T_461 & enq_idxs_5[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_460 = _T_461 & enq_idxs_5[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_463 = _T_461 & enq_idxs_5[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_533 = do_enq & in_mask_6; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_466 = _T_533 & enq_idxs_6[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_469 = _T_533 & enq_idxs_6[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_472 = _T_533 & enq_idxs_6[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_475 = _T_533 & enq_idxs_6[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_478 = _T_533 & enq_idxs_6[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_481 = _T_533 & enq_idxs_6[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_484 = _T_533 & enq_idxs_6[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_487 = _T_533 & enq_idxs_6[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_490 = _T_533 & enq_idxs_6[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_493 = _T_533 & enq_idxs_6[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_496 = _T_533 & enq_idxs_6[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_499 = _T_533 & enq_idxs_6[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_502 = _T_533 & enq_idxs_6[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_505 = _T_533 & enq_idxs_6[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_508 = _T_533 & enq_idxs_6[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_511 = _T_533 & enq_idxs_6[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_514 = _T_533 & enq_idxs_6[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_517 = _T_533 & enq_idxs_6[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_520 = _T_533 & enq_idxs_6[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_523 = _T_533 & enq_idxs_6[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_526 = _T_533 & enq_idxs_6[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_529 = _T_533 & enq_idxs_6[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_532 = _T_533 & enq_idxs_6[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_535 = _T_533 & enq_idxs_6[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_605 = do_enq & in_mask_7; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_538 = _T_605 & enq_idxs_7[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_541 = _T_605 & enq_idxs_7[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_544 = _T_605 & enq_idxs_7[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_547 = _T_605 & enq_idxs_7[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_550 = _T_605 & enq_idxs_7[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_553 = _T_605 & enq_idxs_7[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_556 = _T_605 & enq_idxs_7[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_559 = _T_605 & enq_idxs_7[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_562 = _T_605 & enq_idxs_7[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_565 = _T_605 & enq_idxs_7[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_568 = _T_605 & enq_idxs_7[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_571 = _T_605 & enq_idxs_7[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_574 = _T_605 & enq_idxs_7[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_577 = _T_605 & enq_idxs_7[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_580 = _T_605 & enq_idxs_7[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_583 = _T_605 & enq_idxs_7[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_586 = _T_605 & enq_idxs_7[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_589 = _T_605 & enq_idxs_7[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_592 = _T_605 & enq_idxs_7[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_595 = _T_605 & enq_idxs_7[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_598 = _T_605 & enq_idxs_7[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_601 = _T_605 & enq_idxs_7[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_604 = _T_605 & enq_idxs_7[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_607 = _T_605 & enq_idxs_7[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] always @(posedge clock) begin // @[fetch-buffer.scala:40:7] if (_T_538) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_466) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_394) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_322) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_250) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_178) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_106) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_34) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_0_edge_inst <= ~(_T_538 \| _T_466 \| _T_394) & (_T_322 ? in_uops_4_edge_inst : ~(_T_250 \| _T_178 \| _T_106) & (_T_34 ? in_uops_0_edge_inst : fb_uop_ram_0_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_541) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_469) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_397) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_325) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_253) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_181) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_109) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_37) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_1_edge_inst <= ~(_T_541 \| _T_469 \| _T_397) & (_T_325 ? in_uops_4_edge_inst : ~(_T_253 \| _T_181 \| _T_109) & (_T_37 ? in_uops_0_edge_inst : fb_uop_ram_1_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_544) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_472) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_400) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_328) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_256) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_184) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_112) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_40) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_2_edge_inst <= ~(_T_544 \| _T_472 \| _T_400) & (_T_328 ? in_uops_4_edge_inst : ~(_T_256 \| _T_184 \| _T_112) & (_T_40 ? in_uops_0_edge_inst : fb_uop_ram_2_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_547) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_475) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_403) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_331) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_259) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_187) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_115) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_43) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_3_edge_inst <= ~(_T_547 \| _T_475 \| _T_403) & (_T_331 ? in_uops_4_edge_inst : ~(_T_259 \| _T_187 \| _T_115) & (_T_43 ? in_uops_0_edge_inst : fb_uop_ram_3_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_550) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_478) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_406) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_334) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_262) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_190) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_118) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_46) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_4_edge_inst <= ~(_T_550 \| _T_478 \| _T_406) & (_T_334 ? in_uops_4_edge_inst : ~(_T_262 \| _T_190 \| _T_118) & (_T_46 ? in_uops_0_edge_inst : fb_uop_ram_4_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_553) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_481) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_409) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_337) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_265) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_193) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_121) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_49) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_5_edge_inst <= ~(_T_553 \| _T_481 \| _T_409) & (_T_337 ? in_uops_4_edge_inst : ~(_T_265 \| _T_193 \| _T_121) & (_T_49 ? in_uops_0_edge_inst : fb_uop_ram_5_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_556) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_484) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_412) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_340) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_268) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_196) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_124) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_52) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_6_edge_inst <= ~(_T_556 \| _T_484 \| _T_412) & (_T_340 ? in_uops_4_edge_inst : ~(_T_268 \| _T_196 \| _T_124) & (_T_52 ? in_uops_0_edge_inst : fb_uop_ram_6_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_559) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_487) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_415) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_343) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_271) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_199) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_127) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_55) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_7_edge_inst <= ~(_T_559 \| _T_487 \| _T_415) & (_T_343 ? in_uops_4_edge_inst : ~(_T_271 \| _T_199 \| _T_127) & (_T_55 ? in_uops_0_edge_inst : fb_uop_ram_7_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_562) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_490) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_418) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_346) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_274) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_202) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_130) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_58) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_8_edge_inst <= ~(_T_562 \| _T_490 \| _T_418) & (_T_346 ? in_uops_4_edge_inst : ~(_T_274 \| _T_202 \| _T_130) & (_T_58 ? in_uops_0_edge_inst : fb_uop_ram_8_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_565) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_493) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_421) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_349) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_277) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_205) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_133) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_61) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_9_edge_inst <= ~(_T_565 \| _T_493 \| _T_421) & (_T_349 ? in_uops_4_edge_inst : ~(_T_277 \| _T_205 \| _T_133) & (_T_61 ? in_uops_0_edge_inst : fb_uop_ram_9_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_568) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_496) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_424) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_352) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_280) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_208) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_136) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_64) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_10_edge_inst <= ~(_T_568 \| _T_496 \| _T_424) & (_T_352 ? in_uops_4_edge_inst : ~(_T_280 \| _T_208 \| _T_136) & (_T_64 ? in_uops_0_edge_inst : fb_uop_ram_10_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_571) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_499) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_427) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_355) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_283) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_211) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_139) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_67) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_11_edge_inst <= ~(_T_571 \| _T_499 \| _T_427) & (_T_355 ? in_uops_4_edge_inst : ~(_T_283 \| _T_211 \| _T_139) & (_T_67 ? in_uops_0_edge_inst : fb_uop_ram_11_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_574) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_502) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_430) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_358) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_286) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_214) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_142) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_70) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_12_edge_inst <= ~(_T_574 \| _T_502 \| _T_430) & (_T_358 ? in_uops_4_edge_inst : ~(_T_286 \| _T_214 \| _T_142) & (_T_70 ? in_uops_0_edge_inst : fb_uop_ram_12_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_577) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_505) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_433) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_361) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_289) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_217) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_145) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_73) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_13_edge_inst <= ~(_T_577 \| _T_505 \| _T_433) & (_T_361 ? in_uops_4_edge_inst : ~(_T_289 \| _T_217 \| _T_145) & (_T_73 ? in_uops_0_edge_inst : fb_uop_ram_13_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_580) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_508) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_436) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_364) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_292) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_220) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_148) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_76) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_14_edge_inst <= ~(_T_580 \| _T_508 \| _T_436) & (_T_364 ? in_uops_4_edge_inst : ~(_T_292 \| _T_220 \| _T_148) & (_T_76 ? in_uops_0_edge_inst : fb_uop_ram_14_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_583) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_511) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_439) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_367) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_295) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_223) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_151) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_79) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_15_edge_inst <= ~(_T_583 \| _T_511 \| _T_439) & (_T_367 ? in_uops_4_edge_inst : ~(_T_295 \| _T_223 \| _T_151) & (_T_79 ? in_uops_0_edge_inst : fb_uop_ram_15_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_586) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_514) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_442) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_370) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_298) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_226) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_154) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_82) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_16_edge_inst <= ~(_T_586 \| _T_514 \| _T_442) & (_T_370 ? in_uops_4_edge_inst : ~(_T_298 \| _T_226 \| _T_154) & (_T_82 ? in_uops_0_edge_inst : fb_uop_ram_16_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_589) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_517) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_445) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_373) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_301) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_229) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_157) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_85) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_17_edge_inst <= ~(_T_589 \| _T_517 \| _T_445) & (_T_373 ? in_uops_4_edge_inst : ~(_T_301 \| _T_229 \| _T_157) & (_T_85 ? in_uops_0_edge_inst : fb_uop_ram_17_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_592) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_520) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_448) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_376) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_304) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_232) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_160) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_88) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_18_edge_inst <= ~(_T_592 \| _T_520 \| _T_448) & (_T_376 ? in_uops_4_edge_inst : ~(_T_304 \| _T_232 \| _T_160) & (_T_88 ? in_uops_0_edge_inst : fb_uop_ram_18_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_595) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_523) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_451) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_379) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_307) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_235) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_163) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_91) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_19_edge_inst <= ~(_T_595 \| _T_523 \| _T_451) & (_T_379 ? in_uops_4_edge_inst : ~(_T_307 \| _T_235 \| _T_163) & (_T_91 ? in_uops_0_edge_inst : fb_uop_ram_19_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_598) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_526) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_454) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_382) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_310) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_238) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_166) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_94) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_20_edge_inst <= ~(_T_598 \| _T_526 \| _T_454) & (_T_382 ? in_uops_4_edge_inst : ~(_T_310 \| _T_238 \| _T_166) & (_T_94 ? in_uops_0_edge_inst : fb_uop_ram_20_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_601) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_529) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_457) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_385) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_313) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_241) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_169) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_97) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_21_edge_inst <= ~(_T_601 \| _T_529 \| _T_457) & (_T_385 ? in_uops_4_edge_inst : ~(_T_313 \| _T_241 \| _T_169) & (_T_97 ? in_uops_0_edge_inst : fb_uop_ram_21_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_604) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_532) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_460) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_388) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_316) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_244) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_172) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_100) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_22_edge_inst <= ~(_T_604 \| _T_532 \| _T_460) & (_T_388 ? in_uops_4_edge_inst : ~(_T_316 \| _T_244 \| _T_172) & (_T_100 ? in_uops_0_edge_inst : fb_uop_ram_22_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_607) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_535) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_463) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_391) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_319) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_247) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_175) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_103) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_23_edge_inst <= ~(_T_607 \| _T_535 \| _T_463) & (_T_391 ? in_uops_4_edge_inst : ~(_T_319 \| _T_247 \| _T_175) & (_T_103 ? in_uops_0_edge_inst : fb_uop_ram_23_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (reset) begin // @[fetch-buffer.scala:40:7] head <= 8'h1; // @[fetch-buffer.scala:61:21] tail <= 24'h1; // @[fetch-buffer.scala:62:21] maybe_full <= 1'h0; // @[fetch-buffer.scala:64:27] end else begin // @[fetch-buffer.scala:40:7] if (io_clear_0) begin // @[fetch-buffer.scala:40:7] head <= 8'h1; // @[fetch-buffer.scala:61:21] tail <= 24'h1; // @[fetch-buffer.scala:62:21] end else begin // @[fetch-buffer.scala:40:7] if (do_deq) // @[fetch-buffer.scala:159:29] head <= _head_T_2; // @[fetch-buffer.scala:61:21, :132:8] if (do_enq) begin // @[fetch-buffer.scala:82:16] if (in_mask_7) // @[fetch-buffer.scala:87:21] tail <= {enq_idxs_7[22:0], enq_idxs_7[23]}; // @[fetch-buffer.scala:62:21, :128:22, :132:{8,12,24}] else if (in_mask_6) // @[fetch-buffer.scala:87:21] tail <= _T_26; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_5) // @[fetch-buffer.scala:87:21] tail <= _T_22; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_4) // @[fetch-buffer.scala:87:21] tail <= _T_18; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_3) // @[fetch-buffer.scala:87:21] tail <= _T_14; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_2) // @[fetch-buffer.scala:87:21] tail <= _T_10; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_1) // @[fetch-buffer.scala:87:21] tail <= _T_6; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_0) // @[fetch-buffer.scala:87:21] tail <= _T_2; // @[fetch-buffer.scala:62:21, :132:8] end end maybe_full <= ~(io_clear_0 \| do_deq) & (do_enq & (in_mask_0 \| in_mask_1 \| in_mask_2 \| in_mask_3 \| in_mask_4 \| in_mask_5 \| in_mask_6 \| in_mask_7) \| maybe_full); // @[fetch-buffer.scala:40:7, :64:27, :82:16, :87:21, :159:29, :176:17, :178:{27,33}, :179:18, :183:17, :185:16, :188:19, :191:16] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[fetch-buffer.scala:40:7] assign io_deq_valid = io_deq_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_valid = io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_inst = io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_inst = io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_is_rvc = io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_pc = io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_is_sfb = io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_ftq_idx = io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_edge_inst = io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_pc_lob = io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_taken = io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_xcpt_pf_if = io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_xcpt_ae_if = io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_bp_debug_if = io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_bp_xcpt_if = io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_fsrc = io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_valid = io_deq_bits_uops_1_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_inst = io_deq_bits_uops_1_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_inst = io_deq_bits_uops_1_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_is_rvc = io_deq_bits_uops_1_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_pc = io_deq_bits_uops_1_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_is_sfb = io_deq_bits_uops_1_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_ftq_idx = io_deq_bits_uops_1_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_edge_inst = io_deq_bits_uops_1_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_pc_lob = io_deq_bits_uops_1_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_taken = io_deq_bits_uops_1_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_xcpt_pf_if = io_deq_bits_uops_1_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_xcpt_ae_if = io_deq_bits_uops_1_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_bp_debug_if = io_deq_bits_uops_1_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_bp_xcpt_if = io_deq_bits_uops_1_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_fsrc = io_deq_bits_uops_1_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_valid = io_deq_bits_uops_2_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_inst = io_deq_bits_uops_2_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_debug_inst = io_deq_bits_uops_2_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_is_rvc = io_deq_bits_uops_2_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_debug_pc = io_deq_bits_uops_2_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_is_sfb = io_deq_bits_uops_2_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_ftq_idx = io_deq_bits_uops_2_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_edge_inst = io_deq_bits_uops_2_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_pc_lob = io_deq_bits_uops_2_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_taken = io_deq_bits_uops_2_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_xcpt_pf_if = io_deq_bits_uops_2_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_xcpt_ae_if = io_deq_bits_uops_2_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_bp_debug_if = io_deq_bits_uops_2_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_bp_xcpt_if = io_deq_bits_uops_2_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_debug_fsrc = io_deq_bits_uops_2_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_81 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_81( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_8 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_8 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_16 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulRecFN_8( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_8 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_16 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_267 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_267( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_151 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_151( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_116 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_116 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_10 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id connect route_arbiter.io.in[4].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[4].bits.flow.egress_node_id invalidate route_arbiter.io.in[4].bits.flow.egress_node invalidate route_arbiter.io.in[4].bits.flow.ingress_node_id invalidate route_arbiter.io.in[4].bits.flow.ingress_node invalidate route_arbiter.io.in[4].bits.flow.vnet_id invalidate route_arbiter.io.in[4].bits.src_virt_id connect route_arbiter.io.in[5].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[5].bits.flow.egress_node_id invalidate route_arbiter.io.in[5].bits.flow.egress_node invalidate route_arbiter.io.in[5].bits.flow.ingress_node_id invalidate route_arbiter.io.in[5].bits.flow.ingress_node invalidate route_arbiter.io.in[5].bits.flow.vnet_id invalidate route_arbiter.io.in[5].bits.src_virt_id connect route_arbiter.io.in[6].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[6].bits.flow.egress_node_id invalidate route_arbiter.io.in[6].bits.flow.egress_node invalidate route_arbiter.io.in[6].bits.flow.ingress_node_id invalidate route_arbiter.io.in[6].bits.flow.ingress_node invalidate route_arbiter.io.in[6].bits.flow.vnet_id invalidate route_arbiter.io.in[6].bits.src_virt_id connect route_arbiter.io.in[7].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[7].bits.flow.egress_node_id invalidate route_arbiter.io.in[7].bits.flow.egress_node invalidate route_arbiter.io.in[7].bits.flow.ingress_node_id invalidate route_arbiter.io.in[7].bits.flow.ingress_node invalidate route_arbiter.io.in[7].bits.flow.vnet_id invalidate route_arbiter.io.in[7].bits.src_virt_id node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_9 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_9 : connect states[8].g, UInt<3>(0h2) connect route_arbiter.io.in[9].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[9].bits.flow.egress_node_id invalidate route_arbiter.io.in[9].bits.flow.egress_node invalidate route_arbiter.io.in[9].bits.flow.ingress_node_id invalidate route_arbiter.io.in[9].bits.flow.ingress_node invalidate route_arbiter.io.in[9].bits.flow.vnet_id invalidate route_arbiter.io.in[9].bits.src_virt_id node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_20 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_20 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_21 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_21 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_22 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_22 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_23 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_24 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_25 = and(io.router_req.ready, io.router_req.valid) when _T_25 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_26 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_27 = or(_T_26, vcalloc_vals[2]) node _T_28 = or(_T_27, vcalloc_vals[3]) node _T_29 = or(_T_28, vcalloc_vals[4]) node _T_30 = or(_T_29, vcalloc_vals[5]) node _T_31 = or(_T_30, vcalloc_vals[6]) node _T_32 = or(_T_31, vcalloc_vals[7]) node _T_33 = or(_T_32, vcalloc_vals[8]) node _T_34 = or(_T_33, vcalloc_vals[9]) when _T_34 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>[10] node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24[0], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410) node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_24[1], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435) node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436) node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446 connect _io_vcalloc_req_bits_WIRE_24[2], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450) node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451) node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452) node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453) node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454) node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455) node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465 connect _io_vcalloc_req_bits_WIRE_24[3], _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467) node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468) node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469) node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470) node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475) wire _io_vcalloc_req_bits_WIRE_29 : UInt<1> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484 connect _io_vcalloc_req_bits_WIRE_24[4], _io_vcalloc_req_bits_WIRE_29 node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503 connect _io_vcalloc_req_bits_WIRE_24[5], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_512 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_513 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_504, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_518 = or(_io_vcalloc_req_bits_T_517, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_519 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_510) node _io_vcalloc_req_bits_T_520 = or(_io_vcalloc_req_bits_T_519, _io_vcalloc_req_bits_T_511) node _io_vcalloc_req_bits_T_521 = or(_io_vcalloc_req_bits_T_520, _io_vcalloc_req_bits_T_512) node _io_vcalloc_req_bits_T_522 = or(_io_vcalloc_req_bits_T_521, _io_vcalloc_req_bits_T_513) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_522 connect _io_vcalloc_req_bits_WIRE_24[6], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_527 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_528 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_529 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_530 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_531 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_532 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_533 = or(_io_vcalloc_req_bits_T_523, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_534 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_525) node _io_vcalloc_req_bits_T_535 = or(_io_vcalloc_req_bits_T_534, _io_vcalloc_req_bits_T_526) node _io_vcalloc_req_bits_T_536 = or(_io_vcalloc_req_bits_T_535, _io_vcalloc_req_bits_T_527) node _io_vcalloc_req_bits_T_537 = or(_io_vcalloc_req_bits_T_536, _io_vcalloc_req_bits_T_528) node _io_vcalloc_req_bits_T_538 = or(_io_vcalloc_req_bits_T_537, _io_vcalloc_req_bits_T_529) node _io_vcalloc_req_bits_T_539 = or(_io_vcalloc_req_bits_T_538, _io_vcalloc_req_bits_T_530) node _io_vcalloc_req_bits_T_540 = or(_io_vcalloc_req_bits_T_539, _io_vcalloc_req_bits_T_531) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_540, _io_vcalloc_req_bits_T_532) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_541 connect _io_vcalloc_req_bits_WIRE_24[7], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_542 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_543 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_544 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_545 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_546 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_547 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_543) node _io_vcalloc_req_bits_T_553 = or(_io_vcalloc_req_bits_T_552, _io_vcalloc_req_bits_T_544) node _io_vcalloc_req_bits_T_554 = or(_io_vcalloc_req_bits_T_553, _io_vcalloc_req_bits_T_545) node _io_vcalloc_req_bits_T_555 = or(_io_vcalloc_req_bits_T_554, _io_vcalloc_req_bits_T_546) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_555, _io_vcalloc_req_bits_T_547) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_548) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_551) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_560 connect _io_vcalloc_req_bits_WIRE_24[8], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_561 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_562 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_562) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_563) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_578 = or(_io_vcalloc_req_bits_T_577, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_579 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_579 connect _io_vcalloc_req_bits_WIRE_24[9], _io_vcalloc_req_bits_WIRE_34 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_24 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_587 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_588 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_589 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_580, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_593 = or(_io_vcalloc_req_bits_T_592, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_594 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_585) node _io_vcalloc_req_bits_T_595 = or(_io_vcalloc_req_bits_T_594, _io_vcalloc_req_bits_T_586) node _io_vcalloc_req_bits_T_596 = or(_io_vcalloc_req_bits_T_595, _io_vcalloc_req_bits_T_587) node _io_vcalloc_req_bits_T_597 = or(_io_vcalloc_req_bits_T_596, _io_vcalloc_req_bits_T_588) node _io_vcalloc_req_bits_T_598 = or(_io_vcalloc_req_bits_T_597, _io_vcalloc_req_bits_T_589) wire _io_vcalloc_req_bits_WIRE_35 : UInt<4> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_598 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_35 wire _io_vcalloc_req_bits_WIRE_36 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_602 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_603 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_604 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_605 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_606 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_607 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = or(_io_vcalloc_req_bits_T_599, _io_vcalloc_req_bits_T_600) node _io_vcalloc_req_bits_T_610 = or(_io_vcalloc_req_bits_T_609, _io_vcalloc_req_bits_T_601) node _io_vcalloc_req_bits_T_611 = or(_io_vcalloc_req_bits_T_610, _io_vcalloc_req_bits_T_602) node _io_vcalloc_req_bits_T_612 = or(_io_vcalloc_req_bits_T_611, _io_vcalloc_req_bits_T_603) node _io_vcalloc_req_bits_T_613 = or(_io_vcalloc_req_bits_T_612, _io_vcalloc_req_bits_T_604) node _io_vcalloc_req_bits_T_614 = or(_io_vcalloc_req_bits_T_613, _io_vcalloc_req_bits_T_605) node _io_vcalloc_req_bits_T_615 = or(_io_vcalloc_req_bits_T_614, _io_vcalloc_req_bits_T_606) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_615, _io_vcalloc_req_bits_T_607) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_608) wire _io_vcalloc_req_bits_WIRE_37 : UInt<3> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_617 connect _io_vcalloc_req_bits_WIRE_36.egress_node_id, _io_vcalloc_req_bits_WIRE_37 node _io_vcalloc_req_bits_T_618 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_619 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_620 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_621 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_622 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_619) node _io_vcalloc_req_bits_T_629 = or(_io_vcalloc_req_bits_T_628, _io_vcalloc_req_bits_T_620) node _io_vcalloc_req_bits_T_630 = or(_io_vcalloc_req_bits_T_629, _io_vcalloc_req_bits_T_621) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_630, _io_vcalloc_req_bits_T_622) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_623) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_627) wire _io_vcalloc_req_bits_WIRE_38 : UInt<4> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_636 connect _io_vcalloc_req_bits_WIRE_36.egress_node, _io_vcalloc_req_bits_WIRE_38 node _io_vcalloc_req_bits_T_637 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_637, _io_vcalloc_req_bits_T_638) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_653 = or(_io_vcalloc_req_bits_T_652, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_654 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_645) node _io_vcalloc_req_bits_T_655 = or(_io_vcalloc_req_bits_T_654, _io_vcalloc_req_bits_T_646) wire _io_vcalloc_req_bits_WIRE_39 : UInt<2> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_655 connect _io_vcalloc_req_bits_WIRE_36.ingress_node_id, _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_662 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_663 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_664 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_665 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_656, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_668 = or(_io_vcalloc_req_bits_T_667, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_669 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_660) node _io_vcalloc_req_bits_T_670 = or(_io_vcalloc_req_bits_T_669, _io_vcalloc_req_bits_T_661) node _io_vcalloc_req_bits_T_671 = or(_io_vcalloc_req_bits_T_670, _io_vcalloc_req_bits_T_662) node _io_vcalloc_req_bits_T_672 = or(_io_vcalloc_req_bits_T_671, _io_vcalloc_req_bits_T_663) node _io_vcalloc_req_bits_T_673 = or(_io_vcalloc_req_bits_T_672, _io_vcalloc_req_bits_T_664) node _io_vcalloc_req_bits_T_674 = or(_io_vcalloc_req_bits_T_673, _io_vcalloc_req_bits_T_665) wire _io_vcalloc_req_bits_WIRE_40 : UInt<4> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_674 connect _io_vcalloc_req_bits_WIRE_36.ingress_node, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_677 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_678 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_679 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_680 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_681 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_682 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = or(_io_vcalloc_req_bits_T_675, _io_vcalloc_req_bits_T_676) node _io_vcalloc_req_bits_T_686 = or(_io_vcalloc_req_bits_T_685, _io_vcalloc_req_bits_T_677) node _io_vcalloc_req_bits_T_687 = or(_io_vcalloc_req_bits_T_686, _io_vcalloc_req_bits_T_678) node _io_vcalloc_req_bits_T_688 = or(_io_vcalloc_req_bits_T_687, _io_vcalloc_req_bits_T_679) node _io_vcalloc_req_bits_T_689 = or(_io_vcalloc_req_bits_T_688, _io_vcalloc_req_bits_T_680) node _io_vcalloc_req_bits_T_690 = or(_io_vcalloc_req_bits_T_689, _io_vcalloc_req_bits_T_681) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_690, _io_vcalloc_req_bits_T_682) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_683) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_684) wire _io_vcalloc_req_bits_WIRE_41 : UInt<3> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_693 connect _io_vcalloc_req_bits_WIRE_36.vnet_id, _io_vcalloc_req_bits_WIRE_41 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_36 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`0`[8] invalidate vcalloc_reqs[0].vc_sel.`0`[9] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[8] invalidate vcalloc_reqs[0].vc_sel.`1`[9] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[8] invalidate vcalloc_reqs[0].vc_sel.`2`[9] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`0`[5] invalidate vcalloc_reqs[1].vc_sel.`0`[6] invalidate vcalloc_reqs[1].vc_sel.`0`[7] invalidate vcalloc_reqs[1].vc_sel.`0`[8] invalidate vcalloc_reqs[1].vc_sel.`0`[9] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[5] invalidate vcalloc_reqs[1].vc_sel.`1`[6] invalidate vcalloc_reqs[1].vc_sel.`1`[7] invalidate vcalloc_reqs[1].vc_sel.`1`[8] invalidate vcalloc_reqs[1].vc_sel.`1`[9] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[3] invalidate vcalloc_reqs[1].vc_sel.`2`[4] invalidate vcalloc_reqs[1].vc_sel.`2`[5] invalidate vcalloc_reqs[1].vc_sel.`2`[6] invalidate vcalloc_reqs[1].vc_sel.`2`[7] invalidate vcalloc_reqs[1].vc_sel.`2`[8] invalidate vcalloc_reqs[1].vc_sel.`2`[9] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`0`[5] invalidate vcalloc_reqs[2].vc_sel.`0`[6] invalidate vcalloc_reqs[2].vc_sel.`0`[7] invalidate vcalloc_reqs[2].vc_sel.`0`[8] invalidate vcalloc_reqs[2].vc_sel.`0`[9] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[5] invalidate vcalloc_reqs[2].vc_sel.`1`[6] invalidate vcalloc_reqs[2].vc_sel.`1`[7] invalidate vcalloc_reqs[2].vc_sel.`1`[8] invalidate vcalloc_reqs[2].vc_sel.`1`[9] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[3] invalidate vcalloc_reqs[2].vc_sel.`2`[4] invalidate vcalloc_reqs[2].vc_sel.`2`[5] invalidate vcalloc_reqs[2].vc_sel.`2`[6] invalidate vcalloc_reqs[2].vc_sel.`2`[7] invalidate vcalloc_reqs[2].vc_sel.`2`[8] invalidate vcalloc_reqs[2].vc_sel.`2`[9] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`0`[5] invalidate vcalloc_reqs[3].vc_sel.`0`[6] invalidate vcalloc_reqs[3].vc_sel.`0`[7] invalidate vcalloc_reqs[3].vc_sel.`0`[8] invalidate vcalloc_reqs[3].vc_sel.`0`[9] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[5] invalidate vcalloc_reqs[3].vc_sel.`1`[6] invalidate vcalloc_reqs[3].vc_sel.`1`[7] invalidate vcalloc_reqs[3].vc_sel.`1`[8] invalidate vcalloc_reqs[3].vc_sel.`1`[9] invalidate vcalloc_reqs[3].vc_sel.`2`[0] invalidate vcalloc_reqs[3].vc_sel.`2`[1] invalidate vcalloc_reqs[3].vc_sel.`2`[2] invalidate vcalloc_reqs[3].vc_sel.`2`[3] invalidate vcalloc_reqs[3].vc_sel.`2`[4] invalidate vcalloc_reqs[3].vc_sel.`2`[5] invalidate vcalloc_reqs[3].vc_sel.`2`[6] invalidate vcalloc_reqs[3].vc_sel.`2`[7] invalidate vcalloc_reqs[3].vc_sel.`2`[8] invalidate vcalloc_reqs[3].vc_sel.`2`[9] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id connect vcalloc_vals[4], UInt<1>(0h0) invalidate vcalloc_reqs[4].vc_sel.`0`[0] invalidate vcalloc_reqs[4].vc_sel.`0`[1] invalidate vcalloc_reqs[4].vc_sel.`0`[2] invalidate vcalloc_reqs[4].vc_sel.`0`[3] invalidate vcalloc_reqs[4].vc_sel.`0`[4] invalidate vcalloc_reqs[4].vc_sel.`0`[5] invalidate vcalloc_reqs[4].vc_sel.`0`[6] invalidate vcalloc_reqs[4].vc_sel.`0`[7] invalidate vcalloc_reqs[4].vc_sel.`0`[8] invalidate vcalloc_reqs[4].vc_sel.`0`[9] invalidate vcalloc_reqs[4].vc_sel.`1`[0] invalidate vcalloc_reqs[4].vc_sel.`1`[1] invalidate vcalloc_reqs[4].vc_sel.`1`[2] invalidate vcalloc_reqs[4].vc_sel.`1`[3] invalidate vcalloc_reqs[4].vc_sel.`1`[4] invalidate vcalloc_reqs[4].vc_sel.`1`[5] invalidate vcalloc_reqs[4].vc_sel.`1`[6] invalidate vcalloc_reqs[4].vc_sel.`1`[7] invalidate vcalloc_reqs[4].vc_sel.`1`[8] invalidate vcalloc_reqs[4].vc_sel.`1`[9] invalidate vcalloc_reqs[4].vc_sel.`2`[0] invalidate vcalloc_reqs[4].vc_sel.`2`[1] invalidate vcalloc_reqs[4].vc_sel.`2`[2] invalidate vcalloc_reqs[4].vc_sel.`2`[3] invalidate vcalloc_reqs[4].vc_sel.`2`[4] invalidate vcalloc_reqs[4].vc_sel.`2`[5] invalidate vcalloc_reqs[4].vc_sel.`2`[6] invalidate vcalloc_reqs[4].vc_sel.`2`[7] invalidate vcalloc_reqs[4].vc_sel.`2`[8] invalidate vcalloc_reqs[4].vc_sel.`2`[9] invalidate vcalloc_reqs[4].in_vc invalidate vcalloc_reqs[4].flow.egress_node_id invalidate vcalloc_reqs[4].flow.egress_node invalidate vcalloc_reqs[4].flow.ingress_node_id invalidate vcalloc_reqs[4].flow.ingress_node invalidate vcalloc_reqs[4].flow.vnet_id connect vcalloc_vals[5], UInt<1>(0h0) invalidate vcalloc_reqs[5].vc_sel.`0`[0] invalidate vcalloc_reqs[5].vc_sel.`0`[1] invalidate vcalloc_reqs[5].vc_sel.`0`[2] invalidate vcalloc_reqs[5].vc_sel.`0`[3] invalidate vcalloc_reqs[5].vc_sel.`0`[4] invalidate vcalloc_reqs[5].vc_sel.`0`[5] invalidate vcalloc_reqs[5].vc_sel.`0`[6] invalidate vcalloc_reqs[5].vc_sel.`0`[7] invalidate vcalloc_reqs[5].vc_sel.`0`[8] invalidate vcalloc_reqs[5].vc_sel.`0`[9] invalidate vcalloc_reqs[5].vc_sel.`1`[0] invalidate vcalloc_reqs[5].vc_sel.`1`[1] invalidate vcalloc_reqs[5].vc_sel.`1`[2] invalidate vcalloc_reqs[5].vc_sel.`1`[3] invalidate vcalloc_reqs[5].vc_sel.`1`[4] invalidate vcalloc_reqs[5].vc_sel.`1`[5] invalidate vcalloc_reqs[5].vc_sel.`1`[6] invalidate vcalloc_reqs[5].vc_sel.`1`[7] invalidate vcalloc_reqs[5].vc_sel.`1`[8] invalidate vcalloc_reqs[5].vc_sel.`1`[9] invalidate vcalloc_reqs[5].vc_sel.`2`[0] invalidate vcalloc_reqs[5].vc_sel.`2`[1] invalidate vcalloc_reqs[5].vc_sel.`2`[2] invalidate vcalloc_reqs[5].vc_sel.`2`[3] invalidate vcalloc_reqs[5].vc_sel.`2`[4] invalidate vcalloc_reqs[5].vc_sel.`2`[5] invalidate vcalloc_reqs[5].vc_sel.`2`[6] invalidate vcalloc_reqs[5].vc_sel.`2`[7] invalidate vcalloc_reqs[5].vc_sel.`2`[8] invalidate vcalloc_reqs[5].vc_sel.`2`[9] invalidate vcalloc_reqs[5].in_vc invalidate vcalloc_reqs[5].flow.egress_node_id invalidate vcalloc_reqs[5].flow.egress_node invalidate vcalloc_reqs[5].flow.ingress_node_id invalidate vcalloc_reqs[5].flow.ingress_node invalidate vcalloc_reqs[5].flow.vnet_id connect vcalloc_vals[6], UInt<1>(0h0) invalidate vcalloc_reqs[6].vc_sel.`0`[0] invalidate vcalloc_reqs[6].vc_sel.`0`[1] invalidate vcalloc_reqs[6].vc_sel.`0`[2] invalidate vcalloc_reqs[6].vc_sel.`0`[3] invalidate vcalloc_reqs[6].vc_sel.`0`[4] invalidate vcalloc_reqs[6].vc_sel.`0`[5] invalidate vcalloc_reqs[6].vc_sel.`0`[6] invalidate vcalloc_reqs[6].vc_sel.`0`[7] invalidate vcalloc_reqs[6].vc_sel.`0`[8] invalidate vcalloc_reqs[6].vc_sel.`0`[9] invalidate vcalloc_reqs[6].vc_sel.`1`[0] invalidate vcalloc_reqs[6].vc_sel.`1`[1] invalidate vcalloc_reqs[6].vc_sel.`1`[2] invalidate vcalloc_reqs[6].vc_sel.`1`[3] invalidate vcalloc_reqs[6].vc_sel.`1`[4] invalidate vcalloc_reqs[6].vc_sel.`1`[5] invalidate vcalloc_reqs[6].vc_sel.`1`[6] invalidate vcalloc_reqs[6].vc_sel.`1`[7] invalidate vcalloc_reqs[6].vc_sel.`1`[8] invalidate vcalloc_reqs[6].vc_sel.`1`[9] invalidate vcalloc_reqs[6].vc_sel.`2`[0] invalidate vcalloc_reqs[6].vc_sel.`2`[1] invalidate vcalloc_reqs[6].vc_sel.`2`[2] invalidate vcalloc_reqs[6].vc_sel.`2`[3] invalidate vcalloc_reqs[6].vc_sel.`2`[4] invalidate vcalloc_reqs[6].vc_sel.`2`[5] invalidate vcalloc_reqs[6].vc_sel.`2`[6] invalidate vcalloc_reqs[6].vc_sel.`2`[7] invalidate vcalloc_reqs[6].vc_sel.`2`[8] invalidate vcalloc_reqs[6].vc_sel.`2`[9] invalidate vcalloc_reqs[6].in_vc invalidate vcalloc_reqs[6].flow.egress_node_id invalidate vcalloc_reqs[6].flow.egress_node invalidate vcalloc_reqs[6].flow.ingress_node_id invalidate vcalloc_reqs[6].flow.ingress_node invalidate vcalloc_reqs[6].flow.vnet_id connect vcalloc_vals[7], UInt<1>(0h0) invalidate vcalloc_reqs[7].vc_sel.`0`[0] invalidate vcalloc_reqs[7].vc_sel.`0`[1] invalidate vcalloc_reqs[7].vc_sel.`0`[2] invalidate vcalloc_reqs[7].vc_sel.`0`[3] invalidate vcalloc_reqs[7].vc_sel.`0`[4] invalidate vcalloc_reqs[7].vc_sel.`0`[5] invalidate vcalloc_reqs[7].vc_sel.`0`[6] invalidate vcalloc_reqs[7].vc_sel.`0`[7] invalidate vcalloc_reqs[7].vc_sel.`0`[8] invalidate vcalloc_reqs[7].vc_sel.`0`[9] invalidate vcalloc_reqs[7].vc_sel.`1`[0] invalidate vcalloc_reqs[7].vc_sel.`1`[1] invalidate vcalloc_reqs[7].vc_sel.`1`[2] invalidate vcalloc_reqs[7].vc_sel.`1`[3] invalidate vcalloc_reqs[7].vc_sel.`1`[4] invalidate vcalloc_reqs[7].vc_sel.`1`[5] invalidate vcalloc_reqs[7].vc_sel.`1`[6] invalidate vcalloc_reqs[7].vc_sel.`1`[7] invalidate vcalloc_reqs[7].vc_sel.`1`[8] invalidate vcalloc_reqs[7].vc_sel.`1`[9] invalidate vcalloc_reqs[7].vc_sel.`2`[0] invalidate vcalloc_reqs[7].vc_sel.`2`[1] invalidate vcalloc_reqs[7].vc_sel.`2`[2] invalidate vcalloc_reqs[7].vc_sel.`2`[3] invalidate vcalloc_reqs[7].vc_sel.`2`[4] invalidate vcalloc_reqs[7].vc_sel.`2`[5] invalidate vcalloc_reqs[7].vc_sel.`2`[6] invalidate vcalloc_reqs[7].vc_sel.`2`[7] invalidate vcalloc_reqs[7].vc_sel.`2`[8] invalidate vcalloc_reqs[7].vc_sel.`2`[9] invalidate vcalloc_reqs[7].in_vc invalidate vcalloc_reqs[7].flow.egress_node_id invalidate vcalloc_reqs[7].flow.egress_node invalidate vcalloc_reqs[7].flow.ingress_node_id invalidate vcalloc_reqs[7].flow.ingress_node invalidate vcalloc_reqs[7].flow.vnet_id node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].flow, states[8].flow node _T_35 = bits(vcalloc_sel, 8, 8) node _T_36 = and(vcalloc_vals[8], _T_35) node _T_37 = and(_T_36, io.vcalloc_req.ready) when _T_37 : connect states[8].g, UInt<3>(0h3) connect vcalloc_vals[9], UInt<1>(0h0) invalidate vcalloc_reqs[9].vc_sel.`0`[0] invalidate vcalloc_reqs[9].vc_sel.`0`[1] invalidate vcalloc_reqs[9].vc_sel.`0`[2] invalidate vcalloc_reqs[9].vc_sel.`0`[3] invalidate vcalloc_reqs[9].vc_sel.`0`[4] invalidate vcalloc_reqs[9].vc_sel.`0`[5] invalidate vcalloc_reqs[9].vc_sel.`0`[6] invalidate vcalloc_reqs[9].vc_sel.`0`[7] invalidate vcalloc_reqs[9].vc_sel.`0`[8] invalidate vcalloc_reqs[9].vc_sel.`0`[9] invalidate vcalloc_reqs[9].vc_sel.`1`[0] invalidate vcalloc_reqs[9].vc_sel.`1`[1] invalidate vcalloc_reqs[9].vc_sel.`1`[2] invalidate vcalloc_reqs[9].vc_sel.`1`[3] invalidate vcalloc_reqs[9].vc_sel.`1`[4] invalidate vcalloc_reqs[9].vc_sel.`1`[5] invalidate vcalloc_reqs[9].vc_sel.`1`[6] invalidate vcalloc_reqs[9].vc_sel.`1`[7] invalidate vcalloc_reqs[9].vc_sel.`1`[8] invalidate vcalloc_reqs[9].vc_sel.`1`[9] invalidate vcalloc_reqs[9].vc_sel.`2`[0] invalidate vcalloc_reqs[9].vc_sel.`2`[1] invalidate vcalloc_reqs[9].vc_sel.`2`[2] invalidate vcalloc_reqs[9].vc_sel.`2`[3] invalidate vcalloc_reqs[9].vc_sel.`2`[4] invalidate vcalloc_reqs[9].vc_sel.`2`[5] invalidate vcalloc_reqs[9].vc_sel.`2`[6] invalidate vcalloc_reqs[9].vc_sel.`2`[7] invalidate vcalloc_reqs[9].vc_sel.`2`[8] invalidate vcalloc_reqs[9].vc_sel.`2`[9] invalidate vcalloc_reqs[9].in_vc invalidate vcalloc_reqs[9].flow.egress_node_id invalidate vcalloc_reqs[9].flow.egress_node invalidate vcalloc_reqs[9].flow.ingress_node_id invalidate vcalloc_reqs[9].flow.ingress_node invalidate vcalloc_reqs[9].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_38 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_38 : node _T_39 = bits(vcalloc_sel, 0, 0) when _T_39 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_40 = eq(states[0].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_40, UInt<1>(0h1), "") : assert_3 node _T_44 = bits(vcalloc_sel, 1, 1) when _T_44 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_45 = eq(states[1].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_45, UInt<1>(0h1), "") : assert_4 node _T_49 = bits(vcalloc_sel, 2, 2) when _T_49 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_50 = eq(states[2].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_50, UInt<1>(0h1), "") : assert_5 node _T_54 = bits(vcalloc_sel, 3, 3) when _T_54 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_55 = eq(states[3].g, UInt<3>(0h2)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_55, UInt<1>(0h1), "") : assert_6 node _T_59 = bits(vcalloc_sel, 4, 4) when _T_59 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_60 = eq(states[4].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_60, UInt<1>(0h1), "") : assert_7 node _T_64 = bits(vcalloc_sel, 5, 5) when _T_64 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_65 = eq(states[5].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_65, UInt<1>(0h1), "") : assert_8 node _T_69 = bits(vcalloc_sel, 6, 6) when _T_69 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_70 = eq(states[6].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_70, UInt<1>(0h1), "") : assert_9 node _T_74 = bits(vcalloc_sel, 7, 7) when _T_74 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_75 = eq(states[7].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_75, UInt<1>(0h1), "") : assert_10 node _T_79 = bits(vcalloc_sel, 8, 8) when _T_79 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].g, UInt<3>(0h3) node _T_80 = eq(states[8].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_80, UInt<1>(0h1), "") : assert_11 node _T_84 = bits(vcalloc_sel, 9, 9) when _T_84 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].g, UInt<3>(0h3) node _T_85 = eq(states[9].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_85, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_312 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[9] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[9] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[9] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[9] connect salloc_arb.io.in[4].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[4].bits.tail invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[9] connect salloc_arb.io.in[5].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[5].bits.tail invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[9] connect salloc_arb.io.in[6].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[6].bits.tail invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[9] connect salloc_arb.io.in[7].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[7].bits.tail invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[9] node credit_available_lo_lo = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[8].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[8].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0]) node credit_available_lo_hi_hi_1 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[8].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5]) node credit_available_hi_hi_hi_1 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[8].vc_sel.`1`[7]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[8].vc_sel.`2`[1], states[8].vc_sel.`2`[0]) node credit_available_lo_hi_hi_2 = cat(states[8].vc_sel.`2`[4], states[8].vc_sel.`2`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[8].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[8].vc_sel.`2`[6], states[8].vc_sel.`2`[5]) node credit_available_hi_hi_hi_2 = cat(states[8].vc_sel.`2`[9], states[8].vc_sel.`2`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[8].vc_sel.`2`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, io.out_credit_available.`1`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_4 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, io.out_credit_available.`1`[7]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`2`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`2`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1] connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2] connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3] connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4] connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5] connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6] connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7] connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8] connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[1], states[8].vc_sel.`2`[1] connect salloc_arb.io.in[8].bits.vc_sel.`2`[2], states[8].vc_sel.`2`[2] connect salloc_arb.io.in[8].bits.vc_sel.`2`[3], states[8].vc_sel.`2`[3] connect salloc_arb.io.in[8].bits.vc_sel.`2`[4], states[8].vc_sel.`2`[4] connect salloc_arb.io.in[8].bits.vc_sel.`2`[5], states[8].vc_sel.`2`[5] connect salloc_arb.io.in[8].bits.vc_sel.`2`[6], states[8].vc_sel.`2`[6] connect salloc_arb.io.in[8].bits.vc_sel.`2`[7], states[8].vc_sel.`2`[7] connect salloc_arb.io.in[8].bits.vc_sel.`2`[8], states[8].vc_sel.`2`[8] connect salloc_arb.io.in[8].bits.vc_sel.`2`[9], states[8].vc_sel.`2`[9] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_89 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_90 = and(_T_89, input_buffer.io.deq[8].bits.tail) when _T_90 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready connect salloc_arb.io.in[9].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[9].bits.tail invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[9] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[10] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_237 connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13 node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_256 connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14 node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_275 connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15 node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_294 connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16 node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298) node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299) node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300) node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301) node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302) node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303) node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_313 connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17 node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315) node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316) node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317) node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318) node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319) node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320) node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321) node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_332 connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18 node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334) node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335) node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336) node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_351 connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19 node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358) node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359) node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360) node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_370 connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20 node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373) node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374) node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375) node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376) node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377) node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378) node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379) node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_389 connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_22 : UInt<1>[10] node _vc_sel_T_390 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_391 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_392 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_393 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_394 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_395 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_396 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_397 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_398 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_400 = or(_vc_sel_T_390, _vc_sel_T_391) node _vc_sel_T_401 = or(_vc_sel_T_400, _vc_sel_T_392) node _vc_sel_T_402 = or(_vc_sel_T_401, _vc_sel_T_393) node _vc_sel_T_403 = or(_vc_sel_T_402, _vc_sel_T_394) node _vc_sel_T_404 = or(_vc_sel_T_403, _vc_sel_T_395) node _vc_sel_T_405 = or(_vc_sel_T_404, _vc_sel_T_396) node _vc_sel_T_406 = or(_vc_sel_T_405, _vc_sel_T_397) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_398) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_399) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_408 connect _vc_sel_WIRE_22[0], _vc_sel_WIRE_23 node _vc_sel_T_409 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_410 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_411 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_412 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_413 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_419 = or(_vc_sel_T_409, _vc_sel_T_410) node _vc_sel_T_420 = or(_vc_sel_T_419, _vc_sel_T_411) node _vc_sel_T_421 = or(_vc_sel_T_420, _vc_sel_T_412) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_413) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_414) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_415) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_416) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_417) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_418) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_427 connect _vc_sel_WIRE_22[1], _vc_sel_WIRE_24 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_436 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_437 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_438 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_430) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_431) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_432) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_433) node _vc_sel_T_443 = or(_vc_sel_T_442, _vc_sel_T_434) node _vc_sel_T_444 = or(_vc_sel_T_443, _vc_sel_T_435) node _vc_sel_T_445 = or(_vc_sel_T_444, _vc_sel_T_436) node _vc_sel_T_446 = or(_vc_sel_T_445, _vc_sel_T_437) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_446 connect _vc_sel_WIRE_22[2], _vc_sel_WIRE_25 node _vc_sel_T_447 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_451 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_452 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_453 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_454 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_455 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_456 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_457 = or(_vc_sel_T_447, _vc_sel_T_448) node _vc_sel_T_458 = or(_vc_sel_T_457, _vc_sel_T_449) node _vc_sel_T_459 = or(_vc_sel_T_458, _vc_sel_T_450) node _vc_sel_T_460 = or(_vc_sel_T_459, _vc_sel_T_451) node _vc_sel_T_461 = or(_vc_sel_T_460, _vc_sel_T_452) node _vc_sel_T_462 = or(_vc_sel_T_461, _vc_sel_T_453) node _vc_sel_T_463 = or(_vc_sel_T_462, _vc_sel_T_454) node _vc_sel_T_464 = or(_vc_sel_T_463, _vc_sel_T_455) node _vc_sel_T_465 = or(_vc_sel_T_464, _vc_sel_T_456) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_465 connect _vc_sel_WIRE_22[3], _vc_sel_WIRE_26 node _vc_sel_T_466 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_467 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_468 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_469 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_470 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_471 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_472 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_473 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_476 = or(_vc_sel_T_466, _vc_sel_T_467) node _vc_sel_T_477 = or(_vc_sel_T_476, _vc_sel_T_468) node _vc_sel_T_478 = or(_vc_sel_T_477, _vc_sel_T_469) node _vc_sel_T_479 = or(_vc_sel_T_478, _vc_sel_T_470) node _vc_sel_T_480 = or(_vc_sel_T_479, _vc_sel_T_471) node _vc_sel_T_481 = or(_vc_sel_T_480, _vc_sel_T_472) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_473) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_474) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_475) wire _vc_sel_WIRE_27 : UInt<1> connect _vc_sel_WIRE_27, _vc_sel_T_484 connect _vc_sel_WIRE_22[4], _vc_sel_WIRE_27 node _vc_sel_T_485 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_486 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_487 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_488 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_495 = or(_vc_sel_T_485, _vc_sel_T_486) node _vc_sel_T_496 = or(_vc_sel_T_495, _vc_sel_T_487) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_488) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_489) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_490) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_491) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_492) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_493) node _vc_sel_T_503 = or(_vc_sel_T_502, _vc_sel_T_494) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_503 connect _vc_sel_WIRE_22[5], _vc_sel_WIRE_28 node _vc_sel_T_504 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_511 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_512 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_513 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_514 = or(_vc_sel_T_504, _vc_sel_T_505) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_506) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_507) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_508) node _vc_sel_T_518 = or(_vc_sel_T_517, _vc_sel_T_509) node _vc_sel_T_519 = or(_vc_sel_T_518, _vc_sel_T_510) node _vc_sel_T_520 = or(_vc_sel_T_519, _vc_sel_T_511) node _vc_sel_T_521 = or(_vc_sel_T_520, _vc_sel_T_512) node _vc_sel_T_522 = or(_vc_sel_T_521, _vc_sel_T_513) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_522 connect _vc_sel_WIRE_22[6], _vc_sel_WIRE_29 node _vc_sel_T_523 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_526 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_527 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_528 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_529 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_530 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_531 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_532 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_533 = or(_vc_sel_T_523, _vc_sel_T_524) node _vc_sel_T_534 = or(_vc_sel_T_533, _vc_sel_T_525) node _vc_sel_T_535 = or(_vc_sel_T_534, _vc_sel_T_526) node _vc_sel_T_536 = or(_vc_sel_T_535, _vc_sel_T_527) node _vc_sel_T_537 = or(_vc_sel_T_536, _vc_sel_T_528) node _vc_sel_T_538 = or(_vc_sel_T_537, _vc_sel_T_529) node _vc_sel_T_539 = or(_vc_sel_T_538, _vc_sel_T_530) node _vc_sel_T_540 = or(_vc_sel_T_539, _vc_sel_T_531) node _vc_sel_T_541 = or(_vc_sel_T_540, _vc_sel_T_532) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_541 connect _vc_sel_WIRE_22[7], _vc_sel_WIRE_30 node _vc_sel_T_542 = mux(_vc_sel_T, states[0].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_543 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_544 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_545 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_546 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_547 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_548 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_552 = or(_vc_sel_T_542, _vc_sel_T_543) node _vc_sel_T_553 = or(_vc_sel_T_552, _vc_sel_T_544) node _vc_sel_T_554 = or(_vc_sel_T_553, _vc_sel_T_545) node _vc_sel_T_555 = or(_vc_sel_T_554, _vc_sel_T_546) node _vc_sel_T_556 = or(_vc_sel_T_555, _vc_sel_T_547) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_548) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_549) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_550) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_551) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_560 connect _vc_sel_WIRE_22[8], _vc_sel_WIRE_31 node _vc_sel_T_561 = mux(_vc_sel_T, states[0].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_562 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_563 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_561, _vc_sel_T_562) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_563) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_564) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_565) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_566) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_567) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_568) node _vc_sel_T_578 = or(_vc_sel_T_577, _vc_sel_T_569) node _vc_sel_T_579 = or(_vc_sel_T_578, _vc_sel_T_570) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_579 connect _vc_sel_WIRE_22[9], _vc_sel_WIRE_32 connect vc_sel.`2`, _vc_sel_WIRE_22 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4]) node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8]) node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9]) node _channel_oh_T_16 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[2]) node _channel_oh_T_18 = or(_channel_oh_T_17, vc_sel.`2`[3]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`2`[4]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`2`[5]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`2`[6]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`2`[7]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`2`[8]) node channel_oh_2 = or(_channel_oh_T_23, vc_sel.`2`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2]) node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5]) node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8]) node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7]) node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8) node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0) node _virt_channel_T_12 = orr(virt_channel_hi_5) node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5) node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4) node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0) node _virt_channel_T_14 = orr(virt_channel_hi_6) node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2) node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19) node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_lo_hi_2 = cat(virt_channel_lo_hi_hi_2, vc_sel.`2`[2]) node virt_channel_lo_8 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[6], vc_sel.`2`[5]) node virt_channel_hi_hi_hi_2 = cat(vc_sel.`2`[9], vc_sel.`2`[8]) node virt_channel_hi_hi_2 = cat(virt_channel_hi_hi_hi_2, vc_sel.`2`[7]) node virt_channel_hi_8 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_22 = cat(virt_channel_hi_8, virt_channel_lo_8) node virt_channel_hi_9 = bits(_virt_channel_T_22, 9, 8) node virt_channel_lo_9 = bits(_virt_channel_T_22, 7, 0) node _virt_channel_T_23 = orr(virt_channel_hi_9) node _virt_channel_T_24 = or(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = cat(_virt_channel_T_23, _virt_channel_T_31) node _virt_channel_T_33 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_2, _virt_channel_T_32, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_33, _virt_channel_T_34) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_35) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_37 node _T_91 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_91 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`0`[8] invalidate states[0].vc_sel.`0`[9] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`1`[8] invalidate states[0].vc_sel.`1`[9] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`2`[8] invalidate states[0].vc_sel.`2`[9] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`0`[5] invalidate states[1].vc_sel.`0`[6] invalidate states[1].vc_sel.`0`[7] invalidate states[1].vc_sel.`0`[8] invalidate states[1].vc_sel.`0`[9] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].vc_sel.`1`[5] invalidate states[1].vc_sel.`1`[6] invalidate states[1].vc_sel.`1`[7] invalidate states[1].vc_sel.`1`[8] invalidate states[1].vc_sel.`1`[9] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`2`[3] invalidate states[1].vc_sel.`2`[4] invalidate states[1].vc_sel.`2`[5] invalidate states[1].vc_sel.`2`[6] invalidate states[1].vc_sel.`2`[7] invalidate states[1].vc_sel.`2`[8] invalidate states[1].vc_sel.`2`[9] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`0`[5] invalidate states[2].vc_sel.`0`[6] invalidate states[2].vc_sel.`0`[7] invalidate states[2].vc_sel.`0`[8] invalidate states[2].vc_sel.`0`[9] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].vc_sel.`1`[5] invalidate states[2].vc_sel.`1`[6] invalidate states[2].vc_sel.`1`[7] invalidate states[2].vc_sel.`1`[8] invalidate states[2].vc_sel.`1`[9] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`2`[3] invalidate states[2].vc_sel.`2`[4] invalidate states[2].vc_sel.`2`[5] invalidate states[2].vc_sel.`2`[6] invalidate states[2].vc_sel.`2`[7] invalidate states[2].vc_sel.`2`[8] invalidate states[2].vc_sel.`2`[9] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`0`[5] invalidate states[3].vc_sel.`0`[6] invalidate states[3].vc_sel.`0`[7] invalidate states[3].vc_sel.`0`[8] invalidate states[3].vc_sel.`0`[9] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].vc_sel.`1`[5] invalidate states[3].vc_sel.`1`[6] invalidate states[3].vc_sel.`1`[7] invalidate states[3].vc_sel.`1`[8] invalidate states[3].vc_sel.`1`[9] invalidate states[3].vc_sel.`2`[0] invalidate states[3].vc_sel.`2`[1] invalidate states[3].vc_sel.`2`[2] invalidate states[3].vc_sel.`2`[3] invalidate states[3].vc_sel.`2`[4] invalidate states[3].vc_sel.`2`[5] invalidate states[3].vc_sel.`2`[6] invalidate states[3].vc_sel.`2`[7] invalidate states[3].vc_sel.`2`[8] invalidate states[3].vc_sel.`2`[9] invalidate states[3].g invalidate states[4].fifo_deps invalidate states[4].flow.egress_node_id invalidate states[4].flow.egress_node invalidate states[4].flow.ingress_node_id invalidate states[4].flow.ingress_node invalidate states[4].flow.vnet_id invalidate states[4].vc_sel.`0`[0] invalidate states[4].vc_sel.`0`[1] invalidate states[4].vc_sel.`0`[2] invalidate states[4].vc_sel.`0`[3] invalidate states[4].vc_sel.`0`[4] invalidate states[4].vc_sel.`0`[5] invalidate states[4].vc_sel.`0`[6] invalidate states[4].vc_sel.`0`[7] invalidate states[4].vc_sel.`0`[8] invalidate states[4].vc_sel.`0`[9] invalidate states[4].vc_sel.`1`[0] invalidate states[4].vc_sel.`1`[1] invalidate states[4].vc_sel.`1`[2] invalidate states[4].vc_sel.`1`[3] invalidate states[4].vc_sel.`1`[4] invalidate states[4].vc_sel.`1`[5] invalidate states[4].vc_sel.`1`[6] invalidate states[4].vc_sel.`1`[7] invalidate states[4].vc_sel.`1`[8] invalidate states[4].vc_sel.`1`[9] invalidate states[4].vc_sel.`2`[0] invalidate states[4].vc_sel.`2`[1] invalidate states[4].vc_sel.`2`[2] invalidate states[4].vc_sel.`2`[3] invalidate states[4].vc_sel.`2`[4] invalidate states[4].vc_sel.`2`[5] invalidate states[4].vc_sel.`2`[6] invalidate states[4].vc_sel.`2`[7] invalidate states[4].vc_sel.`2`[8] invalidate states[4].vc_sel.`2`[9] invalidate states[4].g invalidate states[5].fifo_deps invalidate states[5].flow.egress_node_id invalidate states[5].flow.egress_node invalidate states[5].flow.ingress_node_id invalidate states[5].flow.ingress_node invalidate states[5].flow.vnet_id invalidate states[5].vc_sel.`0`[0] invalidate states[5].vc_sel.`0`[1] invalidate states[5].vc_sel.`0`[2] invalidate states[5].vc_sel.`0`[3] invalidate states[5].vc_sel.`0`[4] invalidate states[5].vc_sel.`0`[5] invalidate states[5].vc_sel.`0`[6] invalidate states[5].vc_sel.`0`[7] invalidate states[5].vc_sel.`0`[8] invalidate states[5].vc_sel.`0`[9] invalidate states[5].vc_sel.`1`[0] invalidate states[5].vc_sel.`1`[1] invalidate states[5].vc_sel.`1`[2] invalidate states[5].vc_sel.`1`[3] invalidate states[5].vc_sel.`1`[4] invalidate states[5].vc_sel.`1`[5] invalidate states[5].vc_sel.`1`[6] invalidate states[5].vc_sel.`1`[7] invalidate states[5].vc_sel.`1`[8] invalidate states[5].vc_sel.`1`[9] invalidate states[5].vc_sel.`2`[0] invalidate states[5].vc_sel.`2`[1] invalidate states[5].vc_sel.`2`[2] invalidate states[5].vc_sel.`2`[3] invalidate states[5].vc_sel.`2`[4] invalidate states[5].vc_sel.`2`[5] invalidate states[5].vc_sel.`2`[6] invalidate states[5].vc_sel.`2`[7] invalidate states[5].vc_sel.`2`[8] invalidate states[5].vc_sel.`2`[9] invalidate states[5].g invalidate states[6].fifo_deps invalidate states[6].flow.egress_node_id invalidate states[6].flow.egress_node invalidate states[6].flow.ingress_node_id invalidate states[6].flow.ingress_node invalidate states[6].flow.vnet_id invalidate states[6].vc_sel.`0`[0] invalidate states[6].vc_sel.`0`[1] invalidate states[6].vc_sel.`0`[2] invalidate states[6].vc_sel.`0`[3] invalidate states[6].vc_sel.`0`[4] invalidate states[6].vc_sel.`0`[5] invalidate states[6].vc_sel.`0`[6] invalidate states[6].vc_sel.`0`[7] invalidate states[6].vc_sel.`0`[8] invalidate states[6].vc_sel.`0`[9] invalidate states[6].vc_sel.`1`[0] invalidate states[6].vc_sel.`1`[1] invalidate states[6].vc_sel.`1`[2] invalidate states[6].vc_sel.`1`[3] invalidate states[6].vc_sel.`1`[4] invalidate states[6].vc_sel.`1`[5] invalidate states[6].vc_sel.`1`[6] invalidate states[6].vc_sel.`1`[7] invalidate states[6].vc_sel.`1`[8] invalidate states[6].vc_sel.`1`[9] invalidate states[6].vc_sel.`2`[0] invalidate states[6].vc_sel.`2`[1] invalidate states[6].vc_sel.`2`[2] invalidate states[6].vc_sel.`2`[3] invalidate states[6].vc_sel.`2`[4] invalidate states[6].vc_sel.`2`[5] invalidate states[6].vc_sel.`2`[6] invalidate states[6].vc_sel.`2`[7] invalidate states[6].vc_sel.`2`[8] invalidate states[6].vc_sel.`2`[9] invalidate states[6].g invalidate states[7].fifo_deps invalidate states[7].flow.egress_node_id invalidate states[7].flow.egress_node invalidate states[7].flow.ingress_node_id invalidate states[7].flow.ingress_node invalidate states[7].flow.vnet_id invalidate states[7].vc_sel.`0`[0] invalidate states[7].vc_sel.`0`[1] invalidate states[7].vc_sel.`0`[2] invalidate states[7].vc_sel.`0`[3] invalidate states[7].vc_sel.`0`[4] invalidate states[7].vc_sel.`0`[5] invalidate states[7].vc_sel.`0`[6] invalidate states[7].vc_sel.`0`[7] invalidate states[7].vc_sel.`0`[8] invalidate states[7].vc_sel.`0`[9] invalidate states[7].vc_sel.`1`[0] invalidate states[7].vc_sel.`1`[1] invalidate states[7].vc_sel.`1`[2] invalidate states[7].vc_sel.`1`[3] invalidate states[7].vc_sel.`1`[4] invalidate states[7].vc_sel.`1`[5] invalidate states[7].vc_sel.`1`[6] invalidate states[7].vc_sel.`1`[7] invalidate states[7].vc_sel.`1`[8] invalidate states[7].vc_sel.`1`[9] invalidate states[7].vc_sel.`2`[0] invalidate states[7].vc_sel.`2`[1] invalidate states[7].vc_sel.`2`[2] invalidate states[7].vc_sel.`2`[3] invalidate states[7].vc_sel.`2`[4] invalidate states[7].vc_sel.`2`[5] invalidate states[7].vc_sel.`2`[6] invalidate states[7].vc_sel.`2`[7] invalidate states[7].vc_sel.`2`[8] invalidate states[7].vc_sel.`2`[9] invalidate states[7].g connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[0], UInt<1>(0h0) connect states[8].vc_sel.`1`[1], UInt<1>(0h0) connect states[8].vc_sel.`1`[2], UInt<1>(0h0) connect states[8].vc_sel.`1`[3], UInt<1>(0h0) connect states[8].vc_sel.`1`[4], UInt<1>(0h0) connect states[8].vc_sel.`1`[5], UInt<1>(0h0) connect states[8].vc_sel.`1`[6], UInt<1>(0h0) connect states[8].vc_sel.`1`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[8], UInt<1>(0h0) connect states[8].vc_sel.`1`[9], UInt<1>(0h0) connect states[8].vc_sel.`2`[0], UInt<1>(0h0) connect states[8].vc_sel.`2`[1], UInt<1>(0h0) connect states[8].vc_sel.`2`[2], UInt<1>(0h0) connect states[8].vc_sel.`2`[3], UInt<1>(0h0) connect states[8].vc_sel.`2`[4], UInt<1>(0h0) connect states[8].vc_sel.`2`[5], UInt<1>(0h0) connect states[8].vc_sel.`2`[6], UInt<1>(0h0) connect states[8].vc_sel.`2`[7], UInt<1>(0h0) connect states[8].vc_sel.`2`[8], UInt<1>(0h0) connect states[8].vc_sel.`2`[9], UInt<1>(0h0) invalidate states[9].fifo_deps invalidate states[9].flow.egress_node_id invalidate states[9].flow.egress_node invalidate states[9].flow.ingress_node_id invalidate states[9].flow.ingress_node invalidate states[9].flow.vnet_id invalidate states[9].vc_sel.`0`[0] invalidate states[9].vc_sel.`0`[1] invalidate states[9].vc_sel.`0`[2] invalidate states[9].vc_sel.`0`[3] invalidate states[9].vc_sel.`0`[4] invalidate states[9].vc_sel.`0`[5] invalidate states[9].vc_sel.`0`[6] invalidate states[9].vc_sel.`0`[7] invalidate states[9].vc_sel.`0`[8] invalidate states[9].vc_sel.`0`[9] invalidate states[9].vc_sel.`1`[0] invalidate states[9].vc_sel.`1`[1] invalidate states[9].vc_sel.`1`[2] invalidate states[9].vc_sel.`1`[3] invalidate states[9].vc_sel.`1`[4] invalidate states[9].vc_sel.`1`[5] invalidate states[9].vc_sel.`1`[6] invalidate states[9].vc_sel.`1`[7] invalidate states[9].vc_sel.`1`[8] invalidate states[9].vc_sel.`1`[9] invalidate states[9].vc_sel.`2`[0] invalidate states[9].vc_sel.`2`[1] invalidate states[9].vc_sel.`2`[2] invalidate states[9].vc_sel.`2`[3] invalidate states[9].vc_sel.`2`[4] invalidate states[9].vc_sel.`2`[5] invalidate states[9].vc_sel.`2`[6] invalidate states[9].vc_sel.`2`[7] invalidate states[9].vc_sel.`2`[8] invalidate states[9].vc_sel.`2`[9] invalidate states[9].g node _T_92 = asUInt(reset) when _T_92 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)	module InputUnit_116( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_8, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_1_9, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {1'h0, vcalloc_vals_8, 8'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : {1'h0, vcalloc_vals_8, 18'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] \| vcalloc_filter[19:10]; // @[Mux.scala:50:70] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_8; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_135 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_135( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h8)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h8)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = and(_T_16, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 node _T_29 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_29 : node _T_30 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_31 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_32 = and(_T_30, _T_31) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_33 = shr(io.in.a.bits.source, 4) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = leq(UInt<1>(0h0), uncommonBits_1) node _T_36 = and(_T_34, _T_35) node _T_37 = leq(uncommonBits_1, UInt<4>(0h8)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_40 = or(_T_38, _T_39) node _T_41 = and(_T_32, _T_40) node _T_42 = or(UInt<1>(0h0), _T_41) node _T_43 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<13>(0h1000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = or(_T_48, _T_53) node _T_60 = or(_T_59, _T_58) node _T_61 = and(_T_43, _T_60) node _T_62 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_63 = or(UInt<1>(0h0), _T_62) node _T_64 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<29>(0h10000000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = and(_T_63, _T_68) node _T_70 = or(UInt<1>(0h0), _T_61) node _T_71 = or(_T_70, _T_69) node _T_72 = and(_T_42, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_76 = shr(io.in.a.bits.source, 4) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_2) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_2, UInt<4>(0h8)) node _T_81 = and(_T_79, _T_80) node _T_82 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_81 connect _WIRE[1], _T_82 node _T_83 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_84 = mux(_WIRE[0], _T_83, UInt<1>(0h0)) node _T_85 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = or(_T_84, _T_85) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_86 node _T_87 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_88 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(UInt<1>(0h0), _T_89) node _T_91 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<13>(0h1000))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<18>(0h2f000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<29>(0h10000000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_95, _T_100) node _T_112 = or(_T_111, _T_105) node _T_113 = or(_T_112, _T_110) node _T_114 = and(_T_90, _T_113) node _T_115 = or(UInt<1>(0h0), _T_114) node _T_116 = and(_WIRE_1, _T_115) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_116, UInt<1>(0h1), "") : assert_3 node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(source_ok, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_123 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_123, UInt<1>(0h1), "") : assert_5 node _T_127 = asUInt(reset) node _T_128 = eq(_T_127, UInt<1>(0h0)) when _T_128 : node _T_129 = eq(is_aligned, UInt<1>(0h0)) when _T_129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_130 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_130, UInt<1>(0h1), "") : assert_7 node _T_134 = not(io.in.a.bits.mask) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_135, UInt<1>(0h1), "") : assert_8 node _T_139 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_139, UInt<1>(0h1), "") : assert_9 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_147 = shr(io.in.a.bits.source, 4) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = leq(UInt<1>(0h0), uncommonBits_3) node _T_150 = and(_T_148, _T_149) node _T_151 = leq(uncommonBits_3, UInt<4>(0h8)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_154 = or(_T_152, _T_153) node _T_155 = and(_T_146, _T_154) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_158 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_159 = cvt(_T_158) node _T_160 = and(_T_159, asSInt(UInt<13>(0h1000))) node _T_161 = asSInt(_T_160) node _T_162 = eq(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<18>(0h2f000))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<13>(0h1000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_162, _T_167) node _T_174 = or(_T_173, _T_172) node _T_175 = and(_T_157, _T_174) node _T_176 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<29>(0h10000000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = and(_T_177, _T_182) node _T_184 = or(UInt<1>(0h0), _T_175) node _T_185 = or(_T_184, _T_183) node _T_186 = and(_T_156, _T_185) node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_T_186, UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_186, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_190 = shr(io.in.a.bits.source, 4) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = leq(UInt<1>(0h0), uncommonBits_4) node _T_193 = and(_T_191, _T_192) node _T_194 = leq(uncommonBits_4, UInt<4>(0h8)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_195 connect _WIRE_2[1], _T_196 node _T_197 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_198 = mux(_WIRE_2[0], _T_197, UInt<1>(0h0)) node _T_199 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = or(_T_198, _T_199) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_200 node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_203 = and(_T_201, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<18>(0h2f000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<29>(0h10000000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = or(_T_209, _T_214) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_224) node _T_228 = and(_T_204, _T_227) node _T_229 = or(UInt<1>(0h0), _T_228) node _T_230 = and(_WIRE_3, _T_229) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_230, UInt<1>(0h1), "") : assert_11 node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(source_ok, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_237 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(_T_237, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_237, UInt<1>(0h1), "") : assert_13 node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(is_aligned, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_244 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(_T_244, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_244, UInt<1>(0h1), "") : assert_15 node _T_248 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_248, UInt<1>(0h1), "") : assert_16 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_253, UInt<1>(0h1), "") : assert_17 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_257, UInt<1>(0h1), "") : assert_18 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_265 = shr(io.in.a.bits.source, 4) node _T_266 = eq(_T_265, UInt<1>(0h0)) node _T_267 = leq(UInt<1>(0h0), uncommonBits_5) node _T_268 = and(_T_266, _T_267) node _T_269 = leq(uncommonBits_5, UInt<4>(0h8)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_272 = or(_T_270, _T_271) node _T_273 = and(_T_264, _T_272) node _T_274 = or(UInt<1>(0h0), _T_273) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_274, UInt<1>(0h1), "") : assert_19 node _T_278 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_279 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_280 = and(_T_278, _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<13>(0h1000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = and(_T_281, _T_286) node _T_288 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_289 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_290 = and(_T_288, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<18>(0h2f000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_298 = cvt(_T_297) node _T_299 = and(_T_298, asSInt(UInt<13>(0h1000))) node _T_300 = asSInt(_T_299) node _T_301 = eq(_T_300, asSInt(UInt<1>(0h0))) node _T_302 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_303 = cvt(_T_302) node _T_304 = and(_T_303, asSInt(UInt<29>(0h10000000))) node _T_305 = asSInt(_T_304) node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0))) node _T_307 = or(_T_296, _T_301) node _T_308 = or(_T_307, _T_306) node _T_309 = and(_T_291, _T_308) node _T_310 = or(UInt<1>(0h0), _T_287) node _T_311 = or(_T_310, _T_309) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_311, UInt<1>(0h1), "") : assert_20 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(source_ok, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(is_aligned, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_321 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : node _T_324 = eq(_T_321, UInt<1>(0h0)) when _T_324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_321, UInt<1>(0h1), "") : assert_23 node _T_325 = eq(io.in.a.bits.mask, mask) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_325, UInt<1>(0h1), "") : assert_24 node _T_329 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_330 = asUInt(reset) node _T_331 = eq(_T_330, UInt<1>(0h0)) when _T_331 : node _T_332 = eq(_T_329, UInt<1>(0h0)) when _T_332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_329, UInt<1>(0h1), "") : assert_25 node _T_333 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_333 : node _T_334 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_335 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_337 = shr(io.in.a.bits.source, 4) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_6) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_6, UInt<4>(0h8)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_344 = or(_T_342, _T_343) node _T_345 = and(_T_336, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_348 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_349 = and(_T_347, _T_348) node _T_350 = or(UInt<1>(0h0), _T_349) node _T_351 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<13>(0h1000))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = and(_T_350, _T_355) node _T_357 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_358 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_359 = and(_T_357, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_362 = cvt(_T_361) node _T_363 = and(_T_362, asSInt(UInt<18>(0h2f000))) node _T_364 = asSInt(_T_363) node _T_365 = eq(_T_364, asSInt(UInt<1>(0h0))) node _T_366 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_367 = cvt(_T_366) node _T_368 = and(_T_367, asSInt(UInt<13>(0h1000))) node _T_369 = asSInt(_T_368) node _T_370 = eq(_T_369, asSInt(UInt<1>(0h0))) node _T_371 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_372 = cvt(_T_371) node _T_373 = and(_T_372, asSInt(UInt<29>(0h10000000))) node _T_374 = asSInt(_T_373) node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0))) node _T_376 = or(_T_365, _T_370) node _T_377 = or(_T_376, _T_375) node _T_378 = and(_T_360, _T_377) node _T_379 = or(UInt<1>(0h0), _T_356) node _T_380 = or(_T_379, _T_378) node _T_381 = and(_T_346, _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_381, UInt<1>(0h1), "") : assert_26 node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(source_ok, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(is_aligned, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_391 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_391, UInt<1>(0h1), "") : assert_29 node _T_395 = eq(io.in.a.bits.mask, mask) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_395, UInt<1>(0h1), "") : assert_30 node _T_399 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_403 = shr(io.in.a.bits.source, 4) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = leq(UInt<1>(0h0), uncommonBits_7) node _T_406 = and(_T_404, _T_405) node _T_407 = leq(uncommonBits_7, UInt<4>(0h8)) node _T_408 = and(_T_406, _T_407) node _T_409 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_410 = or(_T_408, _T_409) node _T_411 = and(_T_402, _T_410) node _T_412 = or(UInt<1>(0h0), _T_411) node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<18>(0h2f000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<13>(0h1000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<29>(0h10000000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = or(_T_431, _T_436) node _T_443 = or(_T_442, _T_441) node _T_444 = and(_T_426, _T_443) node _T_445 = or(UInt<1>(0h0), _T_422) node _T_446 = or(_T_445, _T_444) node _T_447 = and(_T_412, _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_447, UInt<1>(0h1), "") : assert_31 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_457, UInt<1>(0h1), "") : assert_34 node _T_461 = not(mask) node _T_462 = and(io.in.a.bits.mask, _T_461) node _T_463 = eq(_T_462, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_463, UInt<1>(0h1), "") : assert_35 node _T_467 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_471 = shr(io.in.a.bits.source, 4) node _T_472 = eq(_T_471, UInt<1>(0h0)) node _T_473 = leq(UInt<1>(0h0), uncommonBits_8) node _T_474 = and(_T_472, _T_473) node _T_475 = leq(uncommonBits_8, UInt<4>(0h8)) node _T_476 = and(_T_474, _T_475) node _T_477 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_478 = or(_T_476, _T_477) node _T_479 = and(_T_470, _T_478) node _T_480 = or(UInt<1>(0h0), _T_479) node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_482 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_491 = cvt(_T_490) node _T_492 = and(_T_491, asSInt(UInt<18>(0h2f000))) node _T_493 = asSInt(_T_492) node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0))) node _T_495 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<13>(0h1000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<29>(0h10000000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = or(_T_489, _T_494) node _T_506 = or(_T_505, _T_499) node _T_507 = or(_T_506, _T_504) node _T_508 = and(_T_484, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = and(_T_480, _T_509) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_510, UInt<1>(0h1), "") : assert_36 node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(source_ok, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(is_aligned, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_520 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_520, UInt<1>(0h1), "") : assert_39 node _T_524 = eq(io.in.a.bits.mask, mask) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_524, UInt<1>(0h1), "") : assert_40 node _T_528 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_528 : node _T_529 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_530 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_532 = shr(io.in.a.bits.source, 4) node _T_533 = eq(_T_532, UInt<1>(0h0)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<4>(0h8)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_539 = or(_T_537, _T_538) node _T_540 = and(_T_531, _T_539) node _T_541 = or(UInt<1>(0h0), _T_540) node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_544 = and(_T_542, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<18>(0h2f000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<13>(0h1000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<29>(0h10000000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = or(_T_550, _T_555) node _T_567 = or(_T_566, _T_560) node _T_568 = or(_T_567, _T_565) node _T_569 = and(_T_545, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = and(_T_541, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_571, UInt<1>(0h1), "") : assert_41 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(source_ok, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_581 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_581, UInt<1>(0h1), "") : assert_44 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_585, UInt<1>(0h1), "") : assert_45 node _T_589 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_593 = shr(io.in.a.bits.source, 4) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_10) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_10, UInt<4>(0h8)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_600 = or(_T_598, _T_599) node _T_601 = and(_T_592, _T_600) node _T_602 = or(UInt<1>(0h0), _T_601) node _T_603 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_604 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_605 = and(_T_603, _T_604) node _T_606 = or(UInt<1>(0h0), _T_605) node _T_607 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_608 = cvt(_T_607) node _T_609 = and(_T_608, asSInt(UInt<13>(0h1000))) node _T_610 = asSInt(_T_609) node _T_611 = eq(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = and(_T_606, _T_611) node _T_613 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_614 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<18>(0h2f000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = or(_T_618, _T_623) node _T_625 = and(_T_613, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<29>(0h10000000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = and(_T_629, _T_634) node _T_636 = or(UInt<1>(0h0), _T_612) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_635) node _T_639 = and(_T_602, _T_638) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_639, UInt<1>(0h1), "") : assert_46 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(source_ok, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(is_aligned, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_649 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_649, UInt<1>(0h1), "") : assert_49 node _T_653 = eq(io.in.a.bits.mask, mask) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_653, UInt<1>(0h1), "") : assert_50 node _T_657 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(_T_657, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_657, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_661 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_661, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_7 = shr(io.in.d.bits.source, 4) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<4>(0h8)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.d.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_12 connect _source_ok_WIRE_1[1], _source_ok_T_13 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_665 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_665 : node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(source_ok_1, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_669 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_669, UInt<1>(0h1), "") : assert_54 node _T_673 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_673, UInt<1>(0h1), "") : assert_55 node _T_677 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_T_677, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_677, UInt<1>(0h1), "") : assert_56 node _T_681 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_681, UInt<1>(0h1), "") : assert_57 node _T_685 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_685 : node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(source_ok_1, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(sink_ok, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_692 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_692, UInt<1>(0h1), "") : assert_60 node _T_696 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_696, UInt<1>(0h1), "") : assert_61 node _T_700 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_700, UInt<1>(0h1), "") : assert_62 node _T_704 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_704, UInt<1>(0h1), "") : assert_63 node _T_708 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_709 = or(UInt<1>(0h1), _T_708) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_709, UInt<1>(0h1), "") : assert_64 node _T_713 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_713 : node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(source_ok_1, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(sink_ok, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_720 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_720, UInt<1>(0h1), "") : assert_67 node _T_724 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_724, UInt<1>(0h1), "") : assert_68 node _T_728 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_728, UInt<1>(0h1), "") : assert_69 node _T_732 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_733 = or(_T_732, io.in.d.bits.corrupt) node _T_734 = asUInt(reset) node _T_735 = eq(_T_734, UInt<1>(0h0)) when _T_735 : node _T_736 = eq(_T_733, UInt<1>(0h0)) when _T_736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_733, UInt<1>(0h1), "") : assert_70 node _T_737 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_738 = or(UInt<1>(0h1), _T_737) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_738, UInt<1>(0h1), "") : assert_71 node _T_742 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_742 : node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(source_ok_1, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_746 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_746, UInt<1>(0h1), "") : assert_73 node _T_750 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_750, UInt<1>(0h1), "") : assert_74 node _T_754 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_755 = or(UInt<1>(0h1), _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_755, UInt<1>(0h1), "") : assert_75 node _T_759 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_759 : node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(source_ok_1, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_763 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_763, UInt<1>(0h1), "") : assert_77 node _T_767 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_768 = or(_T_767, io.in.d.bits.corrupt) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_768, UInt<1>(0h1), "") : assert_78 node _T_772 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_773 = or(UInt<1>(0h1), _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_773, UInt<1>(0h1), "") : assert_79 node _T_777 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_777 : node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(source_ok_1, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_781 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_781, UInt<1>(0h1), "") : assert_81 node _T_785 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_785, UInt<1>(0h1), "") : assert_82 node _T_789 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_790 = or(UInt<1>(0h1), _T_789) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_790, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_794 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_794, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_798 = shr(io.in.b.bits.source, 4) node _T_799 = eq(_T_798, UInt<1>(0h0)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_11) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_11, UInt<4>(0h8)) node _T_803 = and(_T_801, _T_802) node _T_804 = eq(_T_803, UInt<1>(0h0)) node _T_805 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_804, _T_809) node _T_811 = eq(io.in.b.bits.source, UInt<4>(0h9)) node _T_812 = eq(_T_811, UInt<1>(0h0)) node _T_813 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = or(_T_812, _T_817) node _T_819 = and(_T_810, _T_818) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_819, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<13>(0h1000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<29>(0h10000000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[5] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 node _address_ok_T_25 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_26 = or(_address_ok_T_25, _address_ok_WIRE[2]) node _address_ok_T_27 = or(_address_ok_T_26, _address_ok_WIRE[3]) node address_ok = or(_address_ok_T_27, _address_ok_WIRE[4]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0) node _legal_source_T = shr(io.in.b.bits.source, 4) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h8)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<4>(0h9)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 node _legal_source_T_7 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_8 = mux(_legal_source_WIRE[1], UInt<4>(0h9), UInt<1>(0h0)) node _legal_source_T_9 = or(_legal_source_T_7, _legal_source_T_8) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_9 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_823 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_823 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_824 = shr(io.in.b.bits.source, 4) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_12) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_12, UInt<4>(0h8)) node _T_829 = and(_T_827, _T_828) node _T_830 = eq(io.in.b.bits.source, UInt<4>(0h9)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_829 connect _WIRE_4[1], _T_830 node _T_831 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_832 = mux(_WIRE_4[0], _T_831, UInt<1>(0h0)) node _T_833 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_834 = or(_T_832, _T_833) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_834 node _T_835 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_836 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_837 = and(_T_835, _T_836) node _T_838 = or(UInt<1>(0h0), _T_837) node _T_839 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<18>(0h2f000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<29>(0h10000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = or(_T_843, _T_848) node _T_860 = or(_T_859, _T_853) node _T_861 = or(_T_860, _T_858) node _T_862 = and(_T_838, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = and(_WIRE_5, _T_863) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_864, UInt<1>(0h1), "") : assert_86 node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(address_ok, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(legal_source, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(is_aligned_1, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_877 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_877, UInt<1>(0h1), "") : assert_90 node _T_881 = eq(io.in.b.bits.mask, mask_1) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_881, UInt<1>(0h1), "") : assert_91 node _T_885 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_885, UInt<1>(0h1), "") : assert_92 node _T_889 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_889 : node _T_890 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_891 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_892 = and(_T_890, _T_891) node _T_893 = or(UInt<1>(0h0), _T_892) node _T_894 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<18>(0h2f000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = or(_T_898, _T_903) node _T_915 = or(_T_914, _T_908) node _T_916 = or(_T_915, _T_913) node _T_917 = and(_T_893, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(UInt<1>(0h0), _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_919, UInt<1>(0h1), "") : assert_93 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(legal_source, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(is_aligned_1, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_932 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_932, UInt<1>(0h1), "") : assert_97 node _T_936 = eq(io.in.b.bits.mask, mask_1) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_936, UInt<1>(0h1), "") : assert_98 node _T_940 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_940, UInt<1>(0h1), "") : assert_99 node _T_944 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_944 : node _T_945 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_946 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_947 = and(_T_945, _T_946) node _T_948 = or(UInt<1>(0h0), _T_947) node _T_949 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_950 = cvt(_T_949) node _T_951 = and(_T_950, asSInt(UInt<13>(0h1000))) node _T_952 = asSInt(_T_951) node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0))) node _T_954 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_955 = cvt(_T_954) node _T_956 = and(_T_955, asSInt(UInt<18>(0h2f000))) node _T_957 = asSInt(_T_956) node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0))) node _T_959 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_960 = cvt(_T_959) node _T_961 = and(_T_960, asSInt(UInt<13>(0h1000))) node _T_962 = asSInt(_T_961) node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0))) node _T_964 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_965 = cvt(_T_964) node _T_966 = and(_T_965, asSInt(UInt<29>(0h10000000))) node _T_967 = asSInt(_T_966) node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0))) node _T_969 = or(_T_953, _T_958) node _T_970 = or(_T_969, _T_963) node _T_971 = or(_T_970, _T_968) node _T_972 = and(_T_948, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = and(UInt<1>(0h0), _T_973) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_974, UInt<1>(0h1), "") : assert_100 node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(address_ok, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(legal_source, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(is_aligned_1, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_987 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_987, UInt<1>(0h1), "") : assert_104 node _T_991 = eq(io.in.b.bits.mask, mask_1) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_991, UInt<1>(0h1), "") : assert_105 node _T_995 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_995 : node _T_996 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_997 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<13>(0h1000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<18>(0h2f000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<13>(0h1000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1016 = cvt(_T_1015) node _T_1017 = and(_T_1016, asSInt(UInt<29>(0h10000000))) node _T_1018 = asSInt(_T_1017) node _T_1019 = eq(_T_1018, asSInt(UInt<1>(0h0))) node _T_1020 = or(_T_1004, _T_1009) node _T_1021 = or(_T_1020, _T_1014) node _T_1022 = or(_T_1021, _T_1019) node _T_1023 = and(_T_999, _T_1022) node _T_1024 = or(UInt<1>(0h0), _T_1023) node _T_1025 = and(UInt<1>(0h0), _T_1024) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_106 node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(address_ok, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(legal_source, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1038 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_110 node _T_1042 = not(mask_1) node _T_1043 = and(io.in.b.bits.mask, _T_1042) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_111 node _T_1048 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1048 : node _T_1049 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1050 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = or(UInt<1>(0h0), _T_1051) node _T_1053 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1054 = cvt(_T_1053) node _T_1055 = and(_T_1054, asSInt(UInt<13>(0h1000))) node _T_1056 = asSInt(_T_1055) node _T_1057 = eq(_T_1056, asSInt(UInt<1>(0h0))) node _T_1058 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1059 = cvt(_T_1058) node _T_1060 = and(_T_1059, asSInt(UInt<18>(0h2f000))) node _T_1061 = asSInt(_T_1060) node _T_1062 = eq(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1069 = cvt(_T_1068) node _T_1070 = and(_T_1069, asSInt(UInt<29>(0h10000000))) node _T_1071 = asSInt(_T_1070) node _T_1072 = eq(_T_1071, asSInt(UInt<1>(0h0))) node _T_1073 = or(_T_1057, _T_1062) node _T_1074 = or(_T_1073, _T_1067) node _T_1075 = or(_T_1074, _T_1072) node _T_1076 = and(_T_1052, _T_1075) node _T_1077 = or(UInt<1>(0h0), _T_1076) node _T_1078 = and(UInt<1>(0h0), _T_1077) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_112 node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(address_ok, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(legal_source, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1091 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_116 node _T_1095 = eq(io.in.b.bits.mask, mask_1) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_117 node _T_1099 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1099 : node _T_1100 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1101 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = or(UInt<1>(0h0), _T_1102) node _T_1104 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1105 = cvt(_T_1104) node _T_1106 = and(_T_1105, asSInt(UInt<13>(0h1000))) node _T_1107 = asSInt(_T_1106) node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0))) node _T_1109 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1110 = cvt(_T_1109) node _T_1111 = and(_T_1110, asSInt(UInt<18>(0h2f000))) node _T_1112 = asSInt(_T_1111) node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0))) node _T_1114 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<13>(0h1000))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<29>(0h10000000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = or(_T_1108, _T_1113) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = or(_T_1125, _T_1123) node _T_1127 = and(_T_1103, _T_1126) node _T_1128 = or(UInt<1>(0h0), _T_1127) node _T_1129 = and(UInt<1>(0h0), _T_1128) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_118 node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(address_ok, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(legal_source, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1142 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_122 node _T_1146 = eq(io.in.b.bits.mask, mask_1) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_123 node _T_1150 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1150 : node _T_1151 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1152 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1156 = cvt(_T_1155) node _T_1157 = and(_T_1156, asSInt(UInt<13>(0h1000))) node _T_1158 = asSInt(_T_1157) node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0))) node _T_1160 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<18>(0h2f000))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1166 = cvt(_T_1165) node _T_1167 = and(_T_1166, asSInt(UInt<13>(0h1000))) node _T_1168 = asSInt(_T_1167) node _T_1169 = eq(_T_1168, asSInt(UInt<1>(0h0))) node _T_1170 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<29>(0h10000000))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1159, _T_1164) node _T_1176 = or(_T_1175, _T_1169) node _T_1177 = or(_T_1176, _T_1174) node _T_1178 = and(_T_1154, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = and(UInt<1>(0h0), _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_124 node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(address_ok, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(legal_source, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1193 = eq(io.in.b.bits.mask, mask_1) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_128 node _T_1197 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1201 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_14 = shr(io.in.c.bits.source, 4) node _source_ok_T_15 = eq(_source_ok_T_14, UInt<1>(0h0)) node _source_ok_T_16 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_T_18 = leq(source_ok_uncommonBits_2, UInt<4>(0h8)) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = eq(io.in.c.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_19 connect _source_ok_WIRE_2[1], _source_ok_T_20 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_28 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_29 = cvt(_address_ok_T_28) node _address_ok_T_30 = and(_address_ok_T_29, asSInt(UInt<13>(0h1000))) node _address_ok_T_31 = asSInt(_address_ok_T_30) node _address_ok_T_32 = eq(_address_ok_T_31, asSInt(UInt<1>(0h0))) node _address_ok_T_33 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_34 = cvt(_address_ok_T_33) node _address_ok_T_35 = and(_address_ok_T_34, asSInt(UInt<13>(0h1000))) node _address_ok_T_36 = asSInt(_address_ok_T_35) node _address_ok_T_37 = eq(_address_ok_T_36, asSInt(UInt<1>(0h0))) node _address_ok_T_38 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_39 = cvt(_address_ok_T_38) node _address_ok_T_40 = and(_address_ok_T_39, asSInt(UInt<13>(0h1000))) node _address_ok_T_41 = asSInt(_address_ok_T_40) node _address_ok_T_42 = eq(_address_ok_T_41, asSInt(UInt<1>(0h0))) node _address_ok_T_43 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_44 = cvt(_address_ok_T_43) node _address_ok_T_45 = and(_address_ok_T_44, asSInt(UInt<13>(0h1000))) node _address_ok_T_46 = asSInt(_address_ok_T_45) node _address_ok_T_47 = eq(_address_ok_T_46, asSInt(UInt<1>(0h0))) node _address_ok_T_48 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_49 = cvt(_address_ok_T_48) node _address_ok_T_50 = and(_address_ok_T_49, asSInt(UInt<29>(0h10000000))) node _address_ok_T_51 = asSInt(_address_ok_T_50) node _address_ok_T_52 = eq(_address_ok_T_51, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[5] connect _address_ok_WIRE_1[0], _address_ok_T_32 connect _address_ok_WIRE_1[1], _address_ok_T_37 connect _address_ok_WIRE_1[2], _address_ok_T_42 connect _address_ok_WIRE_1[3], _address_ok_T_47 connect _address_ok_WIRE_1[4], _address_ok_T_52 node _address_ok_T_53 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_54 = or(_address_ok_T_53, _address_ok_WIRE_1[2]) node _address_ok_T_55 = or(_address_ok_T_54, _address_ok_WIRE_1[3]) node address_ok_1 = or(_address_ok_T_55, _address_ok_WIRE_1[4]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_1205 = shr(io.in.c.bits.source, 4) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) node _T_1207 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1208 = and(_T_1206, _T_1207) node _T_1209 = leq(uncommonBits_13, UInt<4>(0h8)) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = or(_T_1211, _T_1216) node _T_1218 = eq(io.in.c.bits.source, UInt<4>(0h9)) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = or(_T_1219, _T_1224) node _T_1226 = and(_T_1217, _T_1225) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_131 node _T_1230 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1230 : node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(address_ok_1, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(source_ok_2, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1237 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_134 node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_136 node _T_1248 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_137 node _T_1252 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1252 : node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(address_ok_1, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(source_ok_2, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1259 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_140 node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1266 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_142 node _T_1270 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1270 : node _T_1271 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1272 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1273 = and(_T_1271, _T_1272) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_1274 = shr(io.in.c.bits.source, 4) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = leq(uncommonBits_14, UInt<4>(0h8)) node _T_1279 = and(_T_1277, _T_1278) node _T_1280 = eq(io.in.c.bits.source, UInt<4>(0h9)) node _T_1281 = or(_T_1279, _T_1280) node _T_1282 = and(_T_1273, _T_1281) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1285 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<18>(0h2f000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<13>(0h1000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = or(_T_1289, _T_1294) node _T_1301 = or(_T_1300, _T_1299) node _T_1302 = and(_T_1284, _T_1301) node _T_1303 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1304 = or(UInt<1>(0h0), _T_1303) node _T_1305 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = and(_T_1304, _T_1309) node _T_1311 = or(UInt<1>(0h0), _T_1302) node _T_1312 = or(_T_1311, _T_1310) node _T_1313 = and(_T_1283, _T_1312) node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(_T_1313, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1313, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_1317 = shr(io.in.c.bits.source, 4) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = leq(UInt<1>(0h0), uncommonBits_15) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = leq(uncommonBits_15, UInt<4>(0h8)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = eq(io.in.c.bits.source, UInt<4>(0h9)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1322 connect _WIRE_6[1], _T_1323 node _T_1324 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1325 = mux(_WIRE_6[0], _T_1324, UInt<1>(0h0)) node _T_1326 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1327 = or(_T_1325, _T_1326) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1327 node _T_1328 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1329 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = or(UInt<1>(0h0), _T_1330) node _T_1332 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<13>(0h1000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1338 = cvt(_T_1337) node _T_1339 = and(_T_1338, asSInt(UInt<18>(0h2f000))) node _T_1340 = asSInt(_T_1339) node _T_1341 = eq(_T_1340, asSInt(UInt<1>(0h0))) node _T_1342 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1343 = cvt(_T_1342) node _T_1344 = and(_T_1343, asSInt(UInt<13>(0h1000))) node _T_1345 = asSInt(_T_1344) node _T_1346 = eq(_T_1345, asSInt(UInt<1>(0h0))) node _T_1347 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1348 = cvt(_T_1347) node _T_1349 = and(_T_1348, asSInt(UInt<29>(0h10000000))) node _T_1350 = asSInt(_T_1349) node _T_1351 = eq(_T_1350, asSInt(UInt<1>(0h0))) node _T_1352 = or(_T_1336, _T_1341) node _T_1353 = or(_T_1352, _T_1346) node _T_1354 = or(_T_1353, _T_1351) node _T_1355 = and(_T_1331, _T_1354) node _T_1356 = or(UInt<1>(0h0), _T_1355) node _T_1357 = and(_WIRE_7, _T_1356) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_144 node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(source_ok_2, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1364 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_146 node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1371 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_148 node _T_1375 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_149 node _T_1379 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1379 : node _T_1380 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1381 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1382 = and(_T_1380, _T_1381) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_1383 = shr(io.in.c.bits.source, 4) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) node _T_1385 = leq(UInt<1>(0h0), uncommonBits_16) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = leq(uncommonBits_16, UInt<4>(0h8)) node _T_1388 = and(_T_1386, _T_1387) node _T_1389 = eq(io.in.c.bits.source, UInt<4>(0h9)) node _T_1390 = or(_T_1388, _T_1389) node _T_1391 = and(_T_1382, _T_1390) node _T_1392 = or(UInt<1>(0h0), _T_1391) node _T_1393 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1394 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1395 = cvt(_T_1394) node _T_1396 = and(_T_1395, asSInt(UInt<13>(0h1000))) node _T_1397 = asSInt(_T_1396) node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0))) node _T_1399 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1400 = cvt(_T_1399) node _T_1401 = and(_T_1400, asSInt(UInt<18>(0h2f000))) node _T_1402 = asSInt(_T_1401) node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0))) node _T_1404 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1405 = cvt(_T_1404) node _T_1406 = and(_T_1405, asSInt(UInt<13>(0h1000))) node _T_1407 = asSInt(_T_1406) node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0))) node _T_1409 = or(_T_1398, _T_1403) node _T_1410 = or(_T_1409, _T_1408) node _T_1411 = and(_T_1393, _T_1410) node _T_1412 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1413 = or(UInt<1>(0h0), _T_1412) node _T_1414 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1415 = cvt(_T_1414) node _T_1416 = and(_T_1415, asSInt(UInt<29>(0h10000000))) node _T_1417 = asSInt(_T_1416) node _T_1418 = eq(_T_1417, asSInt(UInt<1>(0h0))) node _T_1419 = and(_T_1413, _T_1418) node _T_1420 = or(UInt<1>(0h0), _T_1411) node _T_1421 = or(_T_1420, _T_1419) node _T_1422 = and(_T_1392, _T_1421) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_1426 = shr(io.in.c.bits.source, 4) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) node _T_1428 = leq(UInt<1>(0h0), uncommonBits_17) node _T_1429 = and(_T_1427, _T_1428) node _T_1430 = leq(uncommonBits_17, UInt<4>(0h8)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = eq(io.in.c.bits.source, UInt<4>(0h9)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_1431 connect _WIRE_8[1], _T_1432 node _T_1433 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1434 = mux(_WIRE_8[0], _T_1433, UInt<1>(0h0)) node _T_1435 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1436 = or(_T_1434, _T_1435) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1436 node _T_1437 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1438 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = or(UInt<1>(0h0), _T_1439) node _T_1441 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<13>(0h1000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1447 = cvt(_T_1446) node _T_1448 = and(_T_1447, asSInt(UInt<18>(0h2f000))) node _T_1449 = asSInt(_T_1448) node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1452 = cvt(_T_1451) node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000))) node _T_1454 = asSInt(_T_1453) node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0))) node _T_1456 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = or(_T_1445, _T_1450) node _T_1462 = or(_T_1461, _T_1455) node _T_1463 = or(_T_1462, _T_1460) node _T_1464 = and(_T_1440, _T_1463) node _T_1465 = or(UInt<1>(0h0), _T_1464) node _T_1466 = and(_WIRE_9, _T_1465) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_151 node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(source_ok_2, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1473 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_153 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1480 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_155 node _T_1484 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1484 : node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(address_ok_1, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(source_ok_2, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1494 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_159 node _T_1498 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_160 node _T_1502 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1502 : node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(address_ok_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(source_ok_2, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1512 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_164 node _T_1516 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1516 : node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(address_ok_1, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(source_ok_2, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1523 = asUInt(reset) node _T_1524 = eq(_T_1523, UInt<1>(0h0)) when _T_1524 : node _T_1525 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1526 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1527 = asUInt(reset) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = eq(_T_1526, UInt<1>(0h0)) when _T_1529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1526, UInt<1>(0h1), "") : assert_168 node _T_1530 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(_T_1530, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1530, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1537 = eq(a_first, UInt<1>(0h0)) node _T_1538 = and(io.in.a.valid, _T_1537) when _T_1538 : node _T_1539 = eq(io.in.a.bits.opcode, opcode) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_171 node _T_1543 = eq(io.in.a.bits.param, param) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_172 node _T_1547 = eq(io.in.a.bits.size, size) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_173 node _T_1551 = eq(io.in.a.bits.source, source) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_174 node _T_1555 = eq(io.in.a.bits.address, address) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_175 node _T_1559 = and(io.in.a.ready, io.in.a.valid) node _T_1560 = and(_T_1559, a_first) when _T_1560 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1561 = eq(d_first, UInt<1>(0h0)) node _T_1562 = and(io.in.d.valid, _T_1561) when _T_1562 : node _T_1563 = eq(io.in.d.bits.opcode, opcode_1) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_176 node _T_1567 = eq(io.in.d.bits.param, param_1) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_177 node _T_1571 = eq(io.in.d.bits.size, size_1) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_178 node _T_1575 = eq(io.in.d.bits.source, source_1) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_179 node _T_1579 = eq(io.in.d.bits.sink, sink) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_180 node _T_1583 = eq(io.in.d.bits.denied, denied) node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(_T_1583, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1583, UInt<1>(0h1), "") : assert_181 node _T_1587 = and(io.in.d.ready, io.in.d.valid) node _T_1588 = and(_T_1587, d_first) when _T_1588 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1589 = eq(b_first, UInt<1>(0h0)) node _T_1590 = and(io.in.b.valid, _T_1589) when _T_1590 : node _T_1591 = eq(io.in.b.bits.opcode, opcode_2) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_182 node _T_1595 = eq(io.in.b.bits.param, param_2) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_183 node _T_1599 = eq(io.in.b.bits.size, size_2) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_184 node _T_1603 = eq(io.in.b.bits.source, source_2) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_185 node _T_1607 = eq(io.in.b.bits.address, address_1) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_186 node _T_1611 = and(io.in.b.ready, io.in.b.valid) node _T_1612 = and(_T_1611, b_first) when _T_1612 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1613 = eq(c_first, UInt<1>(0h0)) node _T_1614 = and(io.in.c.valid, _T_1613) when _T_1614 : node _T_1615 = eq(io.in.c.bits.opcode, opcode_3) node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(_T_1615, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1615, UInt<1>(0h1), "") : assert_187 node _T_1619 = eq(io.in.c.bits.param, param_3) node _T_1620 = asUInt(reset) node _T_1621 = eq(_T_1620, UInt<1>(0h0)) when _T_1621 : node _T_1622 = eq(_T_1619, UInt<1>(0h0)) when _T_1622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1619, UInt<1>(0h1), "") : assert_188 node _T_1623 = eq(io.in.c.bits.size, size_3) node _T_1624 = asUInt(reset) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(_T_1623, UInt<1>(0h0)) when _T_1626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1623, UInt<1>(0h1), "") : assert_189 node _T_1627 = eq(io.in.c.bits.source, source_3) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_190 node _T_1631 = eq(io.in.c.bits.address, address_2) node _T_1632 = asUInt(reset) node _T_1633 = eq(_T_1632, UInt<1>(0h0)) when _T_1633 : node _T_1634 = eq(_T_1631, UInt<1>(0h0)) when _T_1634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1631, UInt<1>(0h1), "") : assert_191 node _T_1635 = and(io.in.c.ready, io.in.c.valid) node _T_1636 = and(_T_1635, c_first) when _T_1636 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1637 = and(io.in.a.valid, a_first_1) node _T_1638 = and(_T_1637, UInt<1>(0h1)) when _T_1638 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1639 = and(io.in.a.ready, io.in.a.valid) node _T_1640 = and(_T_1639, a_first_1) node _T_1641 = and(_T_1640, UInt<1>(0h1)) when _T_1641 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1642 = dshr(inflight, io.in.a.bits.source) node _T_1643 = bits(_T_1642, 0, 0) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1648 = and(io.in.d.valid, d_first_1) node _T_1649 = and(_T_1648, UInt<1>(0h1)) node _T_1650 = eq(d_release_ack, UInt<1>(0h0)) node _T_1651 = and(_T_1649, _T_1650) when _T_1651 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1652 = and(io.in.d.ready, io.in.d.valid) node _T_1653 = and(_T_1652, d_first_1) node _T_1654 = and(_T_1653, UInt<1>(0h1)) node _T_1655 = eq(d_release_ack, UInt<1>(0h0)) node _T_1656 = and(_T_1654, _T_1655) when _T_1656 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1657 = and(io.in.d.valid, d_first_1) node _T_1658 = and(_T_1657, UInt<1>(0h1)) node _T_1659 = eq(d_release_ack, UInt<1>(0h0)) node _T_1660 = and(_T_1658, _T_1659) when _T_1660 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1661 = dshr(inflight, io.in.d.bits.source) node _T_1662 = bits(_T_1661, 0, 0) node _T_1663 = or(_T_1662, same_cycle_resp) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1667 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1668 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1669 = or(_T_1667, _T_1668) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_194 node _T_1673 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_195 else : node _T_1677 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1678 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1679 = or(_T_1677, _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_196 node _T_1683 = eq(io.in.d.bits.size, a_size_lookup) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_197 node _T_1687 = and(io.in.d.valid, d_first_1) node _T_1688 = and(_T_1687, a_first_1) node _T_1689 = and(_T_1688, io.in.a.valid) node _T_1690 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1691 = and(_T_1689, _T_1690) node _T_1692 = eq(d_release_ack, UInt<1>(0h0)) node _T_1693 = and(_T_1691, _T_1692) when _T_1693 : node _T_1694 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1695 = or(_T_1694, io.in.a.ready) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_198 node _T_1699 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1700 = orr(a_set_wo_ready) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) node _T_1702 = or(_T_1699, _T_1701) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_1706 = orr(inflight) node _T_1707 = eq(_T_1706, UInt<1>(0h0)) node _T_1708 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1709 = or(_T_1707, _T_1708) node _T_1710 = lt(watchdog, plusarg_reader.out) node _T_1711 = or(_T_1709, _T_1710) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1715 = and(io.in.a.ready, io.in.a.valid) node _T_1716 = and(io.in.d.ready, io.in.d.valid) node _T_1717 = or(_T_1715, _T_1716) when _T_1717 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_1718 = and(io.in.c.valid, c_first_1) node _T_1719 = bits(io.in.c.bits.opcode, 2, 2) node _T_1720 = bits(io.in.c.bits.opcode, 1, 1) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = and(_T_1718, _T_1721) when _T_1722 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1723 = and(io.in.c.ready, io.in.c.valid) node _T_1724 = and(_T_1723, c_first_1) node _T_1725 = bits(io.in.c.bits.opcode, 2, 2) node _T_1726 = bits(io.in.c.bits.opcode, 1, 1) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = and(_T_1724, _T_1727) when _T_1728 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1729 = dshr(inflight_1, io.in.c.bits.source) node _T_1730 = bits(_T_1729, 0, 0) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) node _T_1732 = asUInt(reset) node _T_1733 = eq(_T_1732, UInt<1>(0h0)) when _T_1733 : node _T_1734 = eq(_T_1731, UInt<1>(0h0)) when _T_1734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1731, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1735 = and(io.in.d.valid, d_first_2) node _T_1736 = and(_T_1735, UInt<1>(0h1)) node _T_1737 = and(_T_1736, d_release_ack_1) when _T_1737 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1738 = and(io.in.d.ready, io.in.d.valid) node _T_1739 = and(_T_1738, d_first_2) node _T_1740 = and(_T_1739, UInt<1>(0h1)) node _T_1741 = and(_T_1740, d_release_ack_1) when _T_1741 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1742 = and(io.in.d.valid, d_first_2) node _T_1743 = and(_T_1742, UInt<1>(0h1)) node _T_1744 = and(_T_1743, d_release_ack_1) when _T_1744 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1745 = dshr(inflight_1, io.in.d.bits.source) node _T_1746 = bits(_T_1745, 0, 0) node _T_1747 = or(_T_1746, same_cycle_resp_1) node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(_T_1747, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1747, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1751 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1752 = asUInt(reset) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) when _T_1753 : node _T_1754 = eq(_T_1751, UInt<1>(0h0)) when _T_1754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1751, UInt<1>(0h1), "") : assert_203 else : node _T_1755 = eq(io.in.d.bits.size, c_size_lookup) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_204 node _T_1759 = and(io.in.d.valid, d_first_2) node _T_1760 = and(_T_1759, c_first_1) node _T_1761 = and(_T_1760, io.in.c.valid) node _T_1762 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1763 = and(_T_1761, _T_1762) node _T_1764 = and(_T_1763, d_release_ack_1) node _T_1765 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1766 = and(_T_1764, _T_1765) when _T_1766 : node _T_1767 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1768 = or(_T_1767, io.in.c.ready) node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(_T_1768, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1768, UInt<1>(0h1), "") : assert_205 node _T_1772 = orr(c_set_wo_ready) when _T_1772 : node _T_1773 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_1777 = orr(inflight_1) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) node _T_1779 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1780 = or(_T_1778, _T_1779) node _T_1781 = lt(watchdog_1, plusarg_reader_1.out) node _T_1782 = or(_T_1780, _T_1781) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1786 = and(io.in.c.ready, io.in.c.valid) node _T_1787 = and(io.in.d.ready, io.in.d.valid) node _T_1788 = or(_T_1786, _T_1787) when _T_1788 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1789 = and(io.in.d.ready, io.in.d.valid) node _T_1790 = and(_T_1789, d_first_3) node _T_1791 = bits(io.in.d.bits.opcode, 2, 2) node _T_1792 = bits(io.in.d.bits.opcode, 1, 1) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = and(_T_1791, _T_1793) node _T_1795 = and(_T_1790, _T_1794) when _T_1795 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1796 = dshr(inflight_2, io.in.d.bits.sink) node _T_1797 = bits(_T_1796, 0, 0) node _T_1798 = eq(_T_1797, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1802 = and(io.in.e.ready, io.in.e.valid) node _T_1803 = and(_T_1802, UInt<1>(0h1)) node _T_1804 = and(_T_1803, UInt<1>(0h1)) when _T_1804 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1805 = or(d_set, inflight_2) node _T_1806 = dshr(_T_1805, io.in.e.bits.sink) node _T_1807 = bits(_T_1806, 0, 0) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_d_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [20:0] _GEN_1 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:21], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [25:0] _GEN_2 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:26], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_20 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire _address_ok_T_25 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_26 = _address_ok_T_25 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_27 = _address_ok_T_26 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_27 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [3:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [3:0] _legal_source_T_8 = _legal_source_WIRE_1 ? 4'h9 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = io_in_c_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_3 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_3; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [13:0] _GEN_4 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_28 = {io_in_c_bits_address_0[31:14], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_29 = {1'h0, _address_ok_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_30 = _address_ok_T_29 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_31 = _address_ok_T_30; // @[Parameters.scala:137:46] wire _address_ok_T_32 = _address_ok_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_32; // @[Parameters.scala:612:40] wire [20:0] _GEN_5 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_33 = {io_in_c_bits_address_0[31:21], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_34 = {1'h0, _address_ok_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_35 = _address_ok_T_34 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_36 = _address_ok_T_35; // @[Parameters.scala:137:46] wire _address_ok_T_37 = _address_ok_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_37; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_38 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_39 = {1'h0, _address_ok_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_40 = _address_ok_T_39 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_41 = _address_ok_T_40; // @[Parameters.scala:137:46] wire _address_ok_T_42 = _address_ok_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_42; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_43 = {io_in_c_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_44 = {1'h0, _address_ok_T_43}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_45 = _address_ok_T_44 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_46 = _address_ok_T_45; // @[Parameters.scala:137:46] wire _address_ok_T_47 = _address_ok_T_46 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_47; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_48 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_49 = {1'h0, _address_ok_T_48}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_50 = _address_ok_T_49 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_51 = _address_ok_T_50; // @[Parameters.scala:137:46] wire _address_ok_T_52 = _address_ok_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_52; // @[Parameters.scala:612:40] wire _address_ok_T_53 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_54 = _address_ok_T_53 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_55 = _address_ok_T_54 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_55 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire [3:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_1715 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1715; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1715; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1789 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1789; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1789; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1789; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1789; // @[Decoupled.scala:51:35] wire [26:0] _GEN_7 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_7; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_7; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_7; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_7; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_1786 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1786; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1786; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_8 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_8; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_8; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_8; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_8; // @[Monitor.scala:637:69, :790:101] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_9 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_9; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_9; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_9; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_9; // @[Monitor.scala:641:65, :791:99] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {72'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_10 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_10; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_10; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1641 = _T_1715 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1641 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1641 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1641 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1641 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1641 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_11 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_11; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_11; // @[Monitor.scala:673:46, :783:46] wire _T_1687 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_12 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_12; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_12; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_12; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_12; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1687 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1656 = _T_1789 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1656 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1656 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1656 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] c_set; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {72'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_13 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_13; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_13; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1728 = _T_1786 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1728 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1728 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1728 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1728 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1728 ? _c_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1759 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1759 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1741 = _T_1789 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1741 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1741 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1741 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [9:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_1795 = _T_1789 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_14 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_14; // @[OneHot.scala:58:35] assign d_set = _T_1795 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_1804 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_15 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_15; // @[OneHot.scala:58:35] assign e_clr = _T_1804 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module PlusArgTimeout_6 : input clock : Clock input reset : Reset output io : { flip count : UInt<32>} inst plusarg_reader of plusarg_reader_142 node _T = gt(plusarg_reader.out, UInt<1>(0h0)) when _T : node _T_1 = lt(io.count, plusarg_reader.out) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert	module PlusArgTimeout_6( // @[PlusArg.scala:58:7] input clock, // @[PlusArg.scala:58:7] input reset, // @[PlusArg.scala:58:7] input [31:0] io_count // @[PlusArg.scala:59:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19] wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7]
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s8k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s8k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s8k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s8k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_13 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [7:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] in_xbar__addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] in_xbar__requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29] wire [7:0] in_xbar_requestBOI_uncommonBits = 8'h0; // @[Parameters.scala:52:56] wire [7:0] in_xbar__beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] in_xbar__beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] in_xbar__portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] in_xbar_portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [128:0] fixer__allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} \| fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] reg fixer_flight_65; // @[FIFOFixer.scala:79:27] reg fixer_flight_66; // @[FIFOFixer.scala:79:27] reg fixer_flight_67; // @[FIFOFixer.scala:79:27] reg fixer_flight_68; // @[FIFOFixer.scala:79:27] reg fixer_flight_69; // @[FIFOFixer.scala:79:27] reg fixer_flight_70; // @[FIFOFixer.scala:79:27] reg fixer_flight_71; // @[FIFOFixer.scala:79:27] reg fixer_flight_72; // @[FIFOFixer.scala:79:27] reg fixer_flight_73; // @[FIFOFixer.scala:79:27] reg fixer_flight_74; // @[FIFOFixer.scala:79:27] reg fixer_flight_75; // @[FIFOFixer.scala:79:27] reg fixer_flight_76; // @[FIFOFixer.scala:79:27] reg fixer_flight_77; // @[FIFOFixer.scala:79:27] reg fixer_flight_78; // @[FIFOFixer.scala:79:27] reg fixer_flight_79; // @[FIFOFixer.scala:79:27] reg fixer_flight_80; // @[FIFOFixer.scala:79:27] reg fixer_flight_81; // @[FIFOFixer.scala:79:27] reg fixer_flight_82; // @[FIFOFixer.scala:79:27] reg fixer_flight_83; // @[FIFOFixer.scala:79:27] reg fixer_flight_84; // @[FIFOFixer.scala:79:27] reg fixer_flight_85; // @[FIFOFixer.scala:79:27] reg fixer_flight_86; // @[FIFOFixer.scala:79:27] reg fixer_flight_87; // @[FIFOFixer.scala:79:27] reg fixer_flight_88; // @[FIFOFixer.scala:79:27] reg fixer_flight_89; // @[FIFOFixer.scala:79:27] reg fixer_flight_90; // @[FIFOFixer.scala:79:27] reg fixer_flight_91; // @[FIFOFixer.scala:79:27] reg fixer_flight_92; // @[FIFOFixer.scala:79:27] reg fixer_flight_93; // @[FIFOFixer.scala:79:27] reg fixer_flight_94; // @[FIFOFixer.scala:79:27] reg fixer_flight_95; // @[FIFOFixer.scala:79:27] reg fixer_flight_96; // @[FIFOFixer.scala:79:27] reg fixer_flight_97; // @[FIFOFixer.scala:79:27] reg fixer_flight_98; // @[FIFOFixer.scala:79:27] reg fixer_flight_99; // @[FIFOFixer.scala:79:27] reg fixer_flight_100; // @[FIFOFixer.scala:79:27] reg fixer_flight_101; // @[FIFOFixer.scala:79:27] reg fixer_flight_102; // @[FIFOFixer.scala:79:27] reg fixer_flight_103; // @[FIFOFixer.scala:79:27] reg fixer_flight_104; // @[FIFOFixer.scala:79:27] reg fixer_flight_105; // @[FIFOFixer.scala:79:27] reg fixer_flight_106; // @[FIFOFixer.scala:79:27] reg fixer_flight_107; // @[FIFOFixer.scala:79:27] reg fixer_flight_108; // @[FIFOFixer.scala:79:27] reg fixer_flight_109; // @[FIFOFixer.scala:79:27] reg fixer_flight_110; // @[FIFOFixer.scala:79:27] reg fixer_flight_111; // @[FIFOFixer.scala:79:27] reg fixer_flight_112; // @[FIFOFixer.scala:79:27] reg fixer_flight_113; // @[FIFOFixer.scala:79:27] reg fixer_flight_114; // @[FIFOFixer.scala:79:27] reg fixer_flight_115; // @[FIFOFixer.scala:79:27] reg fixer_flight_116; // @[FIFOFixer.scala:79:27] reg fixer_flight_117; // @[FIFOFixer.scala:79:27] reg fixer_flight_118; // @[FIFOFixer.scala:79:27] reg fixer_flight_119; // @[FIFOFixer.scala:79:27] reg fixer_flight_120; // @[FIFOFixer.scala:79:27] reg fixer_flight_121; // @[FIFOFixer.scala:79:27] reg fixer_flight_122; // @[FIFOFixer.scala:79:27] reg fixer_flight_123; // @[FIFOFixer.scala:79:27] reg fixer_flight_124; // @[FIFOFixer.scala:79:27] reg fixer_flight_125; // @[FIFOFixer.scala:79:27] reg fixer_flight_126; // @[FIFOFixer.scala:79:27] reg fixer_flight_127; // @[FIFOFixer.scala:79:27] reg fixer_flight_128; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [128:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [128:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [128:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [255:0] fixer__SourceIdSet_T = 256'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [255:0] fixer__SourceIdClear_T = 256'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [128:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [7:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [7:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [7:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [7:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [7:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire in_ready; // @[RegisterRouter.scala:73:18] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34] wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52] wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 129'h0; // @[FIFOFixer.scala:115:35] bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h0 \| fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1 \| fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2 \| fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3 \| fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4 \| fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5 \| fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6 \| fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7 \| fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h8 \| fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h9 \| fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hA \| fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hB \| fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hC \| fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hD \| fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hE \| fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hF \| fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h10 \| fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h11 \| fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h12 \| fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h13 \| fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h14 \| fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h15 \| fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h16 \| fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h17 \| fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h18 \| fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h19 \| fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1A \| fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1B \| fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1C \| fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1D \| fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1E \| fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1F \| fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h20 \| fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h21 \| fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h22 \| fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h23 \| fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h24 \| fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h25 \| fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h26 \| fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h27 \| fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h28 \| fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h29 \| fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2A \| fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2B \| fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2C \| fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2D \| fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2E \| fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2F \| fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h30 \| fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h31 \| fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h32 \| fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h33 \| fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h34 \| fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h35 \| fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h36 \| fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h37 \| fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h38 \| fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h39 \| fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3A \| fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3B \| fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3C \| fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3D \| fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3E \| fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3F \| fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h40 \| fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_65 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h41) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h41 \| fixer_flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_66 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h42) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h42 \| fixer_flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_67 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h43) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h43 \| fixer_flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_68 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h44) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h44 \| fixer_flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_69 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h45) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h45 \| fixer_flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_70 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h46) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h46 \| fixer_flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_71 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h47) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h47 \| fixer_flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_72 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h48) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h48 \| fixer_flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_73 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h49) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h49 \| fixer_flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_74 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4A \| fixer_flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_75 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4B \| fixer_flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_76 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4C \| fixer_flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_77 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4D \| fixer_flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_78 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4E \| fixer_flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_79 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4F \| fixer_flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_80 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h50) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h50 \| fixer_flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_81 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h51) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h51 \| fixer_flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_82 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h52) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h52 \| fixer_flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_83 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h53) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h53 \| fixer_flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_84 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h54) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h54 \| fixer_flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_85 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h55) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h55 \| fixer_flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_86 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h56) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h56 \| fixer_flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_87 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h57) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h57 \| fixer_flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_88 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h58) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h58 \| fixer_flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_89 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h59) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h59 \| fixer_flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_90 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5A \| fixer_flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_91 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5B \| fixer_flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_92 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5C \| fixer_flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_93 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5D \| fixer_flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_94 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5E \| fixer_flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_95 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5F \| fixer_flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_96 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h60) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h60 \| fixer_flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_97 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h61) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h61 \| fixer_flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_98 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h62) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h62 \| fixer_flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_99 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h63) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h63 \| fixer_flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_100 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h64) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h64 \| fixer_flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_101 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h65) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h65 \| fixer_flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_102 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h66) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h66 \| fixer_flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_103 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h67) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h67 \| fixer_flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_104 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h68) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h68 \| fixer_flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_105 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h69) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h69 \| fixer_flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_106 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6A \| fixer_flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_107 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6B \| fixer_flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_108 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6C \| fixer_flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_109 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6D \| fixer_flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_110 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6E \| fixer_flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_111 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6F \| fixer_flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_112 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h70) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h70 \| fixer_flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_113 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h71) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h71 \| fixer_flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_114 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h72) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h72 \| fixer_flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_115 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h73) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h73 \| fixer_flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_116 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h74) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h74 \| fixer_flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_117 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h75) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h75 \| fixer_flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_118 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h76) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h76 \| fixer_flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_119 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h77) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h77 \| fixer_flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_120 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h78) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h78 \| fixer_flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_121 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h79) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h79 \| fixer_flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_122 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7A \| fixer_flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_123 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7B \| fixer_flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_124 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7C \| fixer_flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_125 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7D \| fixer_flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_126 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7E \| fixer_flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_127 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7F \| fixer_flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_128 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h80) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h80 \| fixer_flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_pbus_out_i1_o2_a29d64s8k1z3u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s8k1z3u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] TLBuffer_a29d64s8k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (bus_xingOut_a_ready), .auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (bus_xingOut_d_valid), .auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode), .auto_in_d_bits_param (bus_xingOut_d_bits_param), .auto_in_d_bits_size (bus_xingOut_d_bits_size), .auto_in_d_bits_source (bus_xingOut_d_bits_source), .auto_in_d_bits_sink (bus_xingOut_d_bits_sink), .auto_in_d_bits_denied (bus_xingOut_d_bits_denied), .auto_in_d_bits_data (bus_xingOut_d_bits_data), .auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt), .auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_out_a_valid (in_xbar_auto_anon_in_a_valid), .auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param), .auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size), .auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source), .auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (in_xbar_auto_anon_in_d_ready), .auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9] .auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9] .auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_a_valid (nodeIn_a_valid), .auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param), .auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size), .auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source), .auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address), .auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask), .auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data), .auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_fragmenter_anon_out_d_ready (nodeIn_d_ready), .auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0), .auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0), .auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0), .auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0), .auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0), .auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0), .auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0), .auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0), .auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0), .auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0), .auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLMonitor_13 monitor ( // @[Nodes.scala:27:25] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_2 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_2 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut	module DivSqrtRecFMToRaw_small_e5_s11_2( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_2 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DatPath : input clock : Clock input reset : Reset output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ctl : { stall : UInt<1>, if_kill : UInt<1>, pc_sel : UInt<3>, op1_sel : UInt<2>, op2_sel : UInt<3>, alu_fun : UInt<5>, wb_sel : UInt<2>, rf_wen : UInt<1>, csr_cmd : UInt<3>, mem_val : UInt<1>, mem_fcn : UInt<2>, mem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>, pc_sel_no_xept : UInt<3>}, dat : { if_valid_resp : UInt<1>, inst : UInt<32>, br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, inst_misaligned : UInt<1>, data_misaligned : UInt<1>, mem_store : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} invalidate io.reset_vector invalidate io.hartid invalidate io.interrupt.meip invalidate io.interrupt.msip invalidate io.interrupt.mtip invalidate io.interrupt.debug invalidate io.dat.csr_interrupt invalidate io.dat.csr_eret invalidate io.dat.mem_store invalidate io.dat.data_misaligned invalidate io.dat.inst_misaligned invalidate io.dat.br_ltu invalidate io.dat.br_lt invalidate io.dat.br_eq invalidate io.dat.inst invalidate io.dat.if_valid_resp invalidate io.ctl.pc_sel_no_xept invalidate io.ctl.exception_cause invalidate io.ctl.exception invalidate io.ctl.mem_typ invalidate io.ctl.mem_fcn invalidate io.ctl.mem_val invalidate io.ctl.csr_cmd invalidate io.ctl.rf_wen invalidate io.ctl.wb_sel invalidate io.ctl.alu_fun invalidate io.ctl.op2_sel invalidate io.ctl.op1_sel invalidate io.ctl.pc_sel invalidate io.ctl.if_kill invalidate io.ctl.stall invalidate io.dmem.resp.bits.data invalidate io.dmem.resp.valid invalidate io.dmem.req.bits.typ invalidate io.dmem.req.bits.fcn invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.addr invalidate io.dmem.req.valid invalidate io.dmem.req.ready invalidate io.imem.resp.bits.data invalidate io.imem.resp.valid invalidate io.imem.req.bits.typ invalidate io.imem.req.bits.fcn invalidate io.imem.req.bits.data invalidate io.imem.req.bits.addr invalidate io.imem.req.valid invalidate io.imem.req.ready invalidate io.ddpath.resetpc invalidate io.ddpath.rdata invalidate io.ddpath.validreq invalidate io.ddpath.wdata invalidate io.ddpath.addr wire tval_data_ma : UInt<32> wire tval_inst_ma : UInt<32> regreset if_reg_pc : UInt, clock, reset, io.reset_vector regreset exe_reg_pc : UInt<32>, clock, reset, UInt<32>(0h0) regreset exe_reg_pc_plus4 : UInt<32>, clock, reset, UInt<32>(0h0) regreset exe_reg_inst : UInt<32>, clock, reset, UInt<32>(0h4033) regreset exe_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) wire if_pc_next : UInt<32> wire exe_br_target : UInt<32> wire exe_jmp_target : UInt<32> wire exe_jump_reg_target : UInt<32> wire exception_target : UInt<32> node _T = eq(io.ctl.stall, UInt<1>(0h0)) when _T : connect if_reg_pc, if_pc_next node _if_pc_plus4_T = add(if_reg_pc, UInt<32>(0h4)) node if_pc_plus4 = tail(_if_pc_plus4_T, 1) node _if_pc_next_T = eq(io.ctl.pc_sel, UInt<3>(0h0)) node _if_pc_next_T_1 = eq(io.ctl.pc_sel, UInt<3>(0h1)) node _if_pc_next_T_2 = eq(io.ctl.pc_sel, UInt<3>(0h2)) node _if_pc_next_T_3 = eq(io.ctl.pc_sel, UInt<3>(0h3)) node _if_pc_next_T_4 = eq(io.ctl.pc_sel, UInt<3>(0h4)) node _if_pc_next_T_5 = mux(_if_pc_next_T_4, exception_target, if_pc_plus4) node _if_pc_next_T_6 = mux(_if_pc_next_T_3, exe_jump_reg_target, _if_pc_next_T_5) node _if_pc_next_T_7 = mux(_if_pc_next_T_2, exe_jmp_target, _if_pc_next_T_6) node _if_pc_next_T_8 = mux(_if_pc_next_T_1, exe_br_target, _if_pc_next_T_7) node _if_pc_next_T_9 = mux(_if_pc_next_T, if_pc_plus4, _if_pc_next_T_8) connect if_pc_next, _if_pc_next_T_9 regreset if_inst_buffer : UInt<32>, clock, reset, UInt<32>(0h0) regreset if_inst_buffer_valid : UInt<1>, clock, reset, UInt<1>(0h0) when io.ctl.stall : when io.imem.resp.valid : connect if_inst_buffer_valid, UInt<1>(0h1) connect if_inst_buffer, io.imem.resp.bits.data else : connect if_inst_buffer, UInt<32>(0h0) connect if_inst_buffer_valid, UInt<1>(0h0) node _io_dat_if_valid_resp_T = or(if_inst_buffer_valid, io.imem.resp.valid) connect io.dat.if_valid_resp, _io_dat_if_valid_resp_T node _io_imem_req_valid_T = eq(if_inst_buffer_valid, UInt<1>(0h0)) connect io.imem.req.valid, _io_imem_req_valid_T connect io.imem.req.bits.fcn, UInt<1>(0h0) connect io.imem.req.bits.typ, UInt<3>(0h7) connect io.imem.req.bits.addr, if_reg_pc node if_inst = mux(if_inst_buffer_valid, if_inst_buffer, io.imem.resp.bits.data) when io.ctl.stall : connect exe_reg_inst, exe_reg_inst connect exe_reg_pc, exe_reg_pc else : when io.ctl.if_kill : connect exe_reg_inst, UInt<32>(0h4033) connect exe_reg_pc, UInt<1>(0h0) connect exe_reg_valid, UInt<1>(0h0) else : connect exe_reg_inst, if_inst connect exe_reg_pc, if_reg_pc connect exe_reg_valid, UInt<1>(0h1) connect exe_reg_pc_plus4, if_pc_plus4 node exe_rs1_addr = bits(exe_reg_inst, 19, 15) node exe_rs2_addr = bits(exe_reg_inst, 24, 20) node exe_wbaddr = bits(exe_reg_inst, 11, 7) wire exe_wbdata : UInt<32> node _exe_wben_T = eq(io.ctl.exception, UInt<1>(0h0)) node exe_wben = and(io.ctl.rf_wen, _exe_wben_T) cmem regfile : UInt<32> [32] infer mport io_ddpath_rdata_MPORT = regfile[io.ddpath.addr], clock connect io.ddpath.rdata, io_ddpath_rdata_MPORT when io.ddpath.validreq : infer mport MPORT = regfile[io.ddpath.addr], clock connect MPORT, io.ddpath.wdata node _T_1 = neq(exe_wbaddr, UInt<1>(0h0)) node _T_2 = and(exe_wben, _T_1) when _T_2 : infer mport MPORT_1 = regfile[exe_wbaddr], clock connect MPORT_1, exe_wbdata node _exe_rs1_data_T = neq(exe_rs1_addr, UInt<1>(0h0)) infer mport exe_rs1_data_MPORT = regfile[exe_rs1_addr], clock node exe_rs1_data = mux(_exe_rs1_data_T, exe_rs1_data_MPORT, UInt<1>(0h0)) node _exe_rs2_data_T = neq(exe_rs2_addr, UInt<1>(0h0)) infer mport exe_rs2_data_MPORT = regfile[exe_rs2_addr], clock node exe_rs2_data = mux(_exe_rs2_data_T, exe_rs2_data_MPORT, UInt<1>(0h0)) node imm_i = bits(exe_reg_inst, 31, 20) node _imm_s_T = bits(exe_reg_inst, 31, 25) node _imm_s_T_1 = bits(exe_reg_inst, 11, 7) node imm_s = cat(_imm_s_T, _imm_s_T_1) node _imm_b_T = bits(exe_reg_inst, 31, 31) node _imm_b_T_1 = bits(exe_reg_inst, 7, 7) node _imm_b_T_2 = bits(exe_reg_inst, 30, 25) node _imm_b_T_3 = bits(exe_reg_inst, 11, 8) node imm_b_lo = cat(_imm_b_T_2, _imm_b_T_3) node imm_b_hi = cat(_imm_b_T, _imm_b_T_1) node imm_b = cat(imm_b_hi, imm_b_lo) node imm_u = bits(exe_reg_inst, 31, 12) node _imm_j_T = bits(exe_reg_inst, 31, 31) node _imm_j_T_1 = bits(exe_reg_inst, 19, 12) node _imm_j_T_2 = bits(exe_reg_inst, 20, 20) node _imm_j_T_3 = bits(exe_reg_inst, 30, 21) node imm_j_lo = cat(_imm_j_T_2, _imm_j_T_3) node imm_j_hi = cat(_imm_j_T, _imm_j_T_1) node imm_j = cat(imm_j_hi, imm_j_lo) node _imm_z_T = mux(UInt<1>(0h0), UInt<27>(0h7ffffff), UInt<27>(0h0)) node _imm_z_T_1 = bits(exe_reg_inst, 19, 15) node imm_z = cat(_imm_z_T, _imm_z_T_1) node _imm_i_sext_T = bits(imm_i, 11, 11) node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) node _imm_s_sext_T = bits(imm_s, 11, 11) node _imm_s_sext_T_1 = mux(_imm_s_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_s_sext = cat(_imm_s_sext_T_1, imm_s) node _imm_b_sext_T = bits(imm_b, 11, 11) node _imm_b_sext_T_1 = mux(_imm_b_sext_T, UInt<19>(0h7ffff), UInt<19>(0h0)) node imm_b_sext_hi = cat(_imm_b_sext_T_1, imm_b) node imm_b_sext = cat(imm_b_sext_hi, UInt<1>(0h0)) node _imm_u_sext_T = mux(UInt<1>(0h0), UInt<12>(0hfff), UInt<12>(0h0)) node imm_u_sext = cat(imm_u, _imm_u_sext_T) node _imm_j_sext_T = bits(imm_j, 19, 19) node _imm_j_sext_T_1 = mux(_imm_j_sext_T, UInt<11>(0h7ff), UInt<11>(0h0)) node imm_j_sext_hi = cat(_imm_j_sext_T_1, imm_j) node imm_j_sext = cat(imm_j_sext_hi, UInt<1>(0h0)) node _exe_alu_op1_T = eq(io.ctl.op1_sel, UInt<2>(0h0)) node _exe_alu_op1_T_1 = eq(io.ctl.op1_sel, UInt<2>(0h1)) node _exe_alu_op1_T_2 = eq(io.ctl.op1_sel, UInt<2>(0h2)) node _exe_alu_op1_T_3 = mux(_exe_alu_op1_T_2, imm_z, UInt<1>(0h0)) node _exe_alu_op1_T_4 = mux(_exe_alu_op1_T_1, imm_u_sext, _exe_alu_op1_T_3) node exe_alu_op1 = mux(_exe_alu_op1_T, exe_rs1_data, _exe_alu_op1_T_4) node _exe_alu_op2_T = eq(io.ctl.op2_sel, UInt<3>(0h0)) node _exe_alu_op2_T_1 = eq(io.ctl.op2_sel, UInt<3>(0h1)) node _exe_alu_op2_T_2 = eq(io.ctl.op2_sel, UInt<3>(0h2)) node _exe_alu_op2_T_3 = eq(io.ctl.op2_sel, UInt<3>(0h3)) node _exe_alu_op2_T_4 = mux(_exe_alu_op2_T_3, imm_s_sext, UInt<1>(0h0)) node _exe_alu_op2_T_5 = mux(_exe_alu_op2_T_2, imm_i_sext, _exe_alu_op2_T_4) node _exe_alu_op2_T_6 = mux(_exe_alu_op2_T_1, exe_reg_pc, _exe_alu_op2_T_5) node exe_alu_op2 = mux(_exe_alu_op2_T, exe_rs2_data, _exe_alu_op2_T_6) wire exe_alu_out : UInt<32> node alu_shamt = bits(exe_alu_op2, 4, 0) node _exe_alu_out_T = eq(io.ctl.alu_fun, UInt<4>(0h1)) node _exe_alu_out_T_1 = add(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) node _exe_alu_out_T_3 = eq(io.ctl.alu_fun, UInt<4>(0h2)) node _exe_alu_out_T_4 = sub(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) node _exe_alu_out_T_6 = eq(io.ctl.alu_fun, UInt<4>(0h6)) node _exe_alu_out_T_7 = and(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_8 = eq(io.ctl.alu_fun, UInt<4>(0h7)) node _exe_alu_out_T_9 = or(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_10 = eq(io.ctl.alu_fun, UInt<4>(0h8)) node _exe_alu_out_T_11 = xor(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_12 = eq(io.ctl.alu_fun, UInt<4>(0h9)) node _exe_alu_out_T_13 = asSInt(exe_alu_op1) node _exe_alu_out_T_14 = asSInt(exe_alu_op2) node _exe_alu_out_T_15 = lt(_exe_alu_out_T_13, _exe_alu_out_T_14) node _exe_alu_out_T_16 = eq(io.ctl.alu_fun, UInt<4>(0ha)) node _exe_alu_out_T_17 = lt(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_18 = eq(io.ctl.alu_fun, UInt<4>(0h3)) node _exe_alu_out_T_19 = dshl(exe_alu_op1, alu_shamt) node _exe_alu_out_T_20 = bits(_exe_alu_out_T_19, 31, 0) node _exe_alu_out_T_21 = eq(io.ctl.alu_fun, UInt<4>(0h5)) node _exe_alu_out_T_22 = asSInt(exe_alu_op1) node _exe_alu_out_T_23 = dshr(_exe_alu_out_T_22, alu_shamt) node _exe_alu_out_T_24 = asUInt(_exe_alu_out_T_23) node _exe_alu_out_T_25 = eq(io.ctl.alu_fun, UInt<4>(0h4)) node _exe_alu_out_T_26 = dshr(exe_alu_op1, alu_shamt) node _exe_alu_out_T_27 = eq(io.ctl.alu_fun, UInt<4>(0hb)) node _exe_alu_out_T_28 = mux(_exe_alu_out_T_27, exe_alu_op1, UInt<1>(0h0)) node _exe_alu_out_T_29 = mux(_exe_alu_out_T_25, _exe_alu_out_T_26, _exe_alu_out_T_28) node _exe_alu_out_T_30 = mux(_exe_alu_out_T_21, _exe_alu_out_T_24, _exe_alu_out_T_29) node _exe_alu_out_T_31 = mux(_exe_alu_out_T_18, _exe_alu_out_T_20, _exe_alu_out_T_30) node _exe_alu_out_T_32 = mux(_exe_alu_out_T_16, _exe_alu_out_T_17, _exe_alu_out_T_31) node _exe_alu_out_T_33 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_32) node _exe_alu_out_T_34 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_33) node _exe_alu_out_T_35 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_34) node _exe_alu_out_T_36 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_35) node _exe_alu_out_T_37 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_36) node _exe_alu_out_T_38 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_37) connect exe_alu_out, _exe_alu_out_T_38 node _exe_br_target_T = add(exe_reg_pc, imm_b_sext) node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) connect exe_br_target, _exe_br_target_T_1 node _exe_jmp_target_T = add(exe_reg_pc, imm_j_sext) node _exe_jmp_target_T_1 = tail(_exe_jmp_target_T, 1) connect exe_jmp_target, _exe_jmp_target_T_1 node _exe_jump_reg_target_T = add(exe_rs1_data, imm_i_sext) node _exe_jump_reg_target_T_1 = tail(_exe_jump_reg_target_T, 1) node _exe_jump_reg_target_T_2 = not(UInt<32>(0h1)) node _exe_jump_reg_target_T_3 = and(_exe_jump_reg_target_T_1, _exe_jump_reg_target_T_2) connect exe_jump_reg_target, _exe_jump_reg_target_T_3 node _io_dat_inst_misaligned_T = bits(exe_br_target, 1, 0) node _io_dat_inst_misaligned_T_1 = orr(_io_dat_inst_misaligned_T) node _io_dat_inst_misaligned_T_2 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h1)) node _io_dat_inst_misaligned_T_3 = and(_io_dat_inst_misaligned_T_1, _io_dat_inst_misaligned_T_2) node _io_dat_inst_misaligned_T_4 = bits(exe_jmp_target, 1, 0) node _io_dat_inst_misaligned_T_5 = orr(_io_dat_inst_misaligned_T_4) node _io_dat_inst_misaligned_T_6 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h2)) node _io_dat_inst_misaligned_T_7 = and(_io_dat_inst_misaligned_T_5, _io_dat_inst_misaligned_T_6) node _io_dat_inst_misaligned_T_8 = or(_io_dat_inst_misaligned_T_3, _io_dat_inst_misaligned_T_7) node _io_dat_inst_misaligned_T_9 = bits(exe_jump_reg_target, 1, 0) node _io_dat_inst_misaligned_T_10 = orr(_io_dat_inst_misaligned_T_9) node _io_dat_inst_misaligned_T_11 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h3)) node _io_dat_inst_misaligned_T_12 = and(_io_dat_inst_misaligned_T_10, _io_dat_inst_misaligned_T_11) node _io_dat_inst_misaligned_T_13 = or(_io_dat_inst_misaligned_T_8, _io_dat_inst_misaligned_T_12) connect io.dat.inst_misaligned, _io_dat_inst_misaligned_T_13 node _tval_inst_ma_T = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h1)) node _tval_inst_ma_T_1 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h2)) node _tval_inst_ma_T_2 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h3)) node _tval_inst_ma_T_3 = mux(_tval_inst_ma_T_2, exe_jump_reg_target, UInt<1>(0h0)) node _tval_inst_ma_T_4 = mux(_tval_inst_ma_T_1, exe_jmp_target, _tval_inst_ma_T_3) node _tval_inst_ma_T_5 = mux(_tval_inst_ma_T, exe_br_target, _tval_inst_ma_T_4) connect tval_inst_ma, _tval_inst_ma_T_5 wire _hits_WIRE : UInt<1>[1] connect _hits_WIRE[0], UInt<1>(0h0) wire hits : UInt<1>[1] connect hits, _hits_WIRE inst csr of CSRFile connect csr.clock, clock connect csr.reset, reset invalidate csr.io.fiom invalidate csr.io.scontext invalidate csr.io.mcontext invalidate csr.io.trace[0].tval invalidate csr.io.trace[0].cause invalidate csr.io.trace[0].interrupt invalidate csr.io.trace[0].exception invalidate csr.io.trace[0].priv invalidate csr.io.trace[0].insn invalidate csr.io.trace[0].iaddr invalidate csr.io.trace[0].valid invalidate csr.io.inst[0] invalidate csr.io.inhibit_cycle invalidate csr.io.csrw_counter invalidate csr.io.interrupt_cause invalidate csr.io.interrupt invalidate csr.io.rocc_interrupt invalidate csr.io.fcsr_flags.bits invalidate csr.io.fcsr_flags.valid invalidate csr.io.fcsr_rm invalidate csr.io.time invalidate csr.io.gva invalidate csr.io.mhtinst_read_pseudo invalidate csr.io.htval invalidate csr.io.tval invalidate csr.io.pc invalidate csr.io.cause invalidate csr.io.retire invalidate csr.io.exception invalidate csr.io.evec invalidate csr.io.vsatp.ppn invalidate csr.io.vsatp.asid invalidate csr.io.vsatp.mode invalidate csr.io.hgatp.ppn invalidate csr.io.hgatp.asid invalidate csr.io.hgatp.mode invalidate csr.io.ptbr.ppn invalidate csr.io.ptbr.asid invalidate csr.io.ptbr.mode invalidate csr.io.gstatus.uie invalidate csr.io.gstatus.sie invalidate csr.io.gstatus.hie invalidate csr.io.gstatus.mie invalidate csr.io.gstatus.upie invalidate csr.io.gstatus.spie invalidate csr.io.gstatus.ube invalidate csr.io.gstatus.mpie invalidate csr.io.gstatus.spp invalidate csr.io.gstatus.vs invalidate csr.io.gstatus.mpp invalidate csr.io.gstatus.fs invalidate csr.io.gstatus.xs invalidate csr.io.gstatus.mprv invalidate csr.io.gstatus.sum invalidate csr.io.gstatus.mxr invalidate csr.io.gstatus.tvm invalidate csr.io.gstatus.tw invalidate csr.io.gstatus.tsr invalidate csr.io.gstatus.zero1 invalidate csr.io.gstatus.sd_rv32 invalidate csr.io.gstatus.uxl invalidate csr.io.gstatus.sxl invalidate csr.io.gstatus.sbe invalidate csr.io.gstatus.mbe invalidate csr.io.gstatus.gva invalidate csr.io.gstatus.mpv invalidate csr.io.gstatus.zero2 invalidate csr.io.gstatus.sd invalidate csr.io.gstatus.v invalidate csr.io.gstatus.prv invalidate csr.io.gstatus.dv invalidate csr.io.gstatus.dprv invalidate csr.io.gstatus.isa invalidate csr.io.gstatus.wfi invalidate csr.io.gstatus.cease invalidate csr.io.gstatus.debug invalidate csr.io.hstatus.zero1 invalidate csr.io.hstatus.vsbe invalidate csr.io.hstatus.gva invalidate csr.io.hstatus.spv invalidate csr.io.hstatus.spvp invalidate csr.io.hstatus.hu invalidate csr.io.hstatus.zero2 invalidate csr.io.hstatus.vgein invalidate csr.io.hstatus.zero3 invalidate csr.io.hstatus.vtvm invalidate csr.io.hstatus.vtw invalidate csr.io.hstatus.vtsr invalidate csr.io.hstatus.zero5 invalidate csr.io.hstatus.vsxl invalidate csr.io.hstatus.zero6 invalidate csr.io.status.uie invalidate csr.io.status.sie invalidate csr.io.status.hie invalidate csr.io.status.mie invalidate csr.io.status.upie invalidate csr.io.status.spie invalidate csr.io.status.ube invalidate csr.io.status.mpie invalidate csr.io.status.spp invalidate csr.io.status.vs invalidate csr.io.status.mpp invalidate csr.io.status.fs invalidate csr.io.status.xs invalidate csr.io.status.mprv invalidate csr.io.status.sum invalidate csr.io.status.mxr invalidate csr.io.status.tvm invalidate csr.io.status.tw invalidate csr.io.status.tsr invalidate csr.io.status.zero1 invalidate csr.io.status.sd_rv32 invalidate csr.io.status.uxl invalidate csr.io.status.sxl invalidate csr.io.status.sbe invalidate csr.io.status.mbe invalidate csr.io.status.gva invalidate csr.io.status.mpv invalidate csr.io.status.zero2 invalidate csr.io.status.sd invalidate csr.io.status.v invalidate csr.io.status.prv invalidate csr.io.status.dv invalidate csr.io.status.dprv invalidate csr.io.status.isa invalidate csr.io.status.wfi invalidate csr.io.status.cease invalidate csr.io.status.debug invalidate csr.io.singleStep invalidate csr.io.eret invalidate csr.io.rw_stall invalidate csr.io.csr_stall invalidate csr.io.decode[0].virtual_system_illegal invalidate csr.io.decode[0].virtual_access_illegal invalidate csr.io.decode[0].system_illegal invalidate csr.io.decode[0].write_flush invalidate csr.io.decode[0].write_illegal invalidate csr.io.decode[0].read_illegal invalidate csr.io.decode[0].rocc_illegal invalidate csr.io.decode[0].vector_csr invalidate csr.io.decode[0].fp_csr invalidate csr.io.decode[0].vector_illegal invalidate csr.io.decode[0].fp_illegal invalidate csr.io.decode[0].inst invalidate csr.io.rw.wdata invalidate csr.io.rw.rdata invalidate csr.io.rw.cmd invalidate csr.io.rw.addr invalidate csr.io.hartid invalidate csr.io.interrupts.meip invalidate csr.io.interrupts.msip invalidate csr.io.interrupts.mtip invalidate csr.io.interrupts.debug invalidate csr.io.ungated_clock connect csr.io.decode[0].inst, exe_reg_inst node _csr_io_rw_addr_T = bits(exe_reg_inst, 31, 20) connect csr.io.rw.addr, _csr_io_rw_addr_T connect csr.io.rw.cmd, io.ctl.csr_cmd connect csr.io.rw.wdata, exe_alu_out node _csr_io_retire_T = or(io.ctl.stall, io.ctl.exception) node _csr_io_retire_T_1 = eq(_csr_io_retire_T, UInt<1>(0h0)) node _csr_io_retire_T_2 = and(exe_reg_valid, _csr_io_retire_T_1) connect csr.io.retire, _csr_io_retire_T_2 connect csr.io.exception, io.ctl.exception connect csr.io.pc, exe_reg_pc connect exception_target, csr.io.evec node _csr_io_tval_T = eq(io.ctl.exception_cause, UInt<2>(0h2)) node _csr_io_tval_T_1 = eq(io.ctl.exception_cause, UInt<1>(0h0)) node _csr_io_tval_T_2 = eq(io.ctl.exception_cause, UInt<3>(0h6)) node _csr_io_tval_T_3 = eq(io.ctl.exception_cause, UInt<3>(0h4)) node _csr_io_tval_T_4 = mux(_csr_io_tval_T_3, tval_data_ma, UInt<1>(0h0)) node _csr_io_tval_T_5 = mux(_csr_io_tval_T_2, tval_data_ma, _csr_io_tval_T_4) node _csr_io_tval_T_6 = mux(_csr_io_tval_T_1, tval_inst_ma, _csr_io_tval_T_5) node _csr_io_tval_T_7 = mux(_csr_io_tval_T, exe_reg_inst, _csr_io_tval_T_6) connect csr.io.tval, _csr_io_tval_T_7 regreset reg_interrupt_handled : UInt<1>, clock, reset, UInt<1>(0h0) node _T_3 = eq(io.ctl.stall, UInt<1>(0h0)) when _T_3 : connect reg_interrupt_handled, csr.io.interrupt node _interrupt_edge_T = eq(reg_interrupt_handled, UInt<1>(0h0)) node interrupt_edge = and(csr.io.interrupt, _interrupt_edge_T) connect csr.io.interrupts.meip, io.interrupt.meip connect csr.io.interrupts.msip, io.interrupt.msip connect csr.io.interrupts.mtip, io.interrupt.mtip connect csr.io.interrupts.debug, io.interrupt.debug connect csr.io.hartid, io.hartid connect io.dat.csr_interrupt, interrupt_edge node _csr_io_cause_T = mux(io.ctl.exception, io.ctl.exception_cause, csr.io.interrupt_cause) connect csr.io.cause, _csr_io_cause_T connect csr.io.ungated_clock, clock connect io.dat.csr_eret, csr.io.eret node _exe_wbdata_T = eq(io.ctl.wb_sel, UInt<2>(0h0)) node _exe_wbdata_T_1 = eq(io.ctl.wb_sel, UInt<2>(0h1)) node _exe_wbdata_T_2 = eq(io.ctl.wb_sel, UInt<2>(0h2)) node _exe_wbdata_T_3 = eq(io.ctl.wb_sel, UInt<2>(0h3)) node _exe_wbdata_T_4 = mux(_exe_wbdata_T_3, csr.io.rw.rdata, exe_alu_out) node _exe_wbdata_T_5 = mux(_exe_wbdata_T_2, exe_reg_pc_plus4, _exe_wbdata_T_4) node _exe_wbdata_T_6 = mux(_exe_wbdata_T_1, io.dmem.resp.bits.data, _exe_wbdata_T_5) node _exe_wbdata_T_7 = mux(_exe_wbdata_T, exe_alu_out, _exe_wbdata_T_6) connect exe_wbdata, _exe_wbdata_T_7 connect io.dat.inst, exe_reg_inst node _io_dat_br_eq_T = eq(exe_rs1_data, exe_rs2_data) connect io.dat.br_eq, _io_dat_br_eq_T node _io_dat_br_lt_T = asSInt(exe_rs1_data) node _io_dat_br_lt_T_1 = asSInt(exe_rs2_data) node _io_dat_br_lt_T_2 = lt(_io_dat_br_lt_T, _io_dat_br_lt_T_1) connect io.dat.br_lt, _io_dat_br_lt_T_2 node _io_dat_br_ltu_T = lt(exe_rs1_data, exe_rs2_data) connect io.dat.br_ltu, _io_dat_br_ltu_T wire misaligned_mask : UInt<3> node _misaligned_mask_T = sub(io.ctl.mem_typ, UInt<1>(0h1)) node _misaligned_mask_T_1 = tail(_misaligned_mask_T, 1) node _misaligned_mask_T_2 = bits(_misaligned_mask_T_1, 1, 0) node _misaligned_mask_T_3 = dshl(UInt<3>(0h7), _misaligned_mask_T_2) node _misaligned_mask_T_4 = not(_misaligned_mask_T_3) connect misaligned_mask, _misaligned_mask_T_4 node _io_dat_data_misaligned_T = bits(exe_alu_out, 2, 0) node _io_dat_data_misaligned_T_1 = and(misaligned_mask, _io_dat_data_misaligned_T) node _io_dat_data_misaligned_T_2 = orr(_io_dat_data_misaligned_T_1) node _io_dat_data_misaligned_T_3 = and(_io_dat_data_misaligned_T_2, io.ctl.mem_val) connect io.dat.data_misaligned, _io_dat_data_misaligned_T_3 node _io_dat_mem_store_T = eq(io.ctl.mem_fcn, UInt<1>(0h1)) connect io.dat.mem_store, _io_dat_mem_store_T connect tval_data_ma, exe_alu_out connect io.dmem.req.bits.addr, exe_alu_out connect io.dmem.req.bits.data, exe_rs2_data node _T_4 = bits(csr.io.time, 31, 0) node _T_5 = mux(io.ctl.if_kill, UInt<8>(0h4b), UInt<8>(0h20)) node _T_6 = mux(io.ctl.stall, UInt<8>(0h53), _T_5) node _T_7 = eq(UInt<3>(0h1), io.ctl.pc_sel) node _T_8 = mux(_T_7, UInt<8>(0h42), UInt<8>(0h3f)) node _T_9 = eq(UInt<3>(0h2), io.ctl.pc_sel) node _T_10 = mux(_T_9, UInt<8>(0h4a), _T_8) node _T_11 = eq(UInt<3>(0h3), io.ctl.pc_sel) node _T_12 = mux(_T_11, UInt<8>(0h52), _T_10) node _T_13 = eq(UInt<3>(0h4), io.ctl.pc_sel) node _T_14 = mux(_T_13, UInt<8>(0h45), _T_12) node _T_15 = eq(UInt<3>(0h0), io.ctl.pc_sel) node _T_16 = mux(_T_15, UInt<8>(0h20), _T_14) node _T_17 = mux(csr.io.exception, UInt<8>(0h58), UInt<8>(0h20)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Cyc= %d [%d] pc=[%x] W[r%d=%x][%d] Op1=[r%d][%x] Op2=[r%d][%x] inst=[%x] %c%c%c DASM(%x)\n", _T_4, csr.io.retire, exe_reg_pc, exe_wbaddr, exe_wbdata, exe_wben, exe_rs1_addr, exe_alu_op1, exe_rs2_addr, exe_alu_op2, exe_reg_inst, _T_6, _T_16, _T_17, exe_reg_inst) : printf	module DatPath( // @[dpath.scala:46:7] input clock, // @[dpath.scala:46:7] input reset, // @[dpath.scala:46:7] output [31:0] io_ddpath_rdata, // @[dpath.scala:48:15] input io_imem_req_ready, // @[dpath.scala:48:15] output io_imem_req_valid, // @[dpath.scala:48:15] output [31:0] io_imem_req_bits_addr, // @[dpath.scala:48:15] input io_imem_resp_valid, // @[dpath.scala:48:15] input [31:0] io_imem_resp_bits_data, // @[dpath.scala:48:15] input io_dmem_req_ready, // @[dpath.scala:48:15] output [31:0] io_dmem_req_bits_addr, // @[dpath.scala:48:15] output [31:0] io_dmem_req_bits_data, // @[dpath.scala:48:15] input io_dmem_resp_valid, // @[dpath.scala:48:15] input [31:0] io_dmem_resp_bits_data, // @[dpath.scala:48:15] input io_ctl_stall, // @[dpath.scala:48:15] input io_ctl_if_kill, // @[dpath.scala:48:15] input [2:0] io_ctl_pc_sel, // @[dpath.scala:48:15] input [1:0] io_ctl_op1_sel, // @[dpath.scala:48:15] input [2:0] io_ctl_op2_sel, // @[dpath.scala:48:15] input [4:0] io_ctl_alu_fun, // @[dpath.scala:48:15] input [1:0] io_ctl_wb_sel, // @[dpath.scala:48:15] input io_ctl_rf_wen, // @[dpath.scala:48:15] input [2:0] io_ctl_csr_cmd, // @[dpath.scala:48:15] input io_ctl_mem_val, // @[dpath.scala:48:15] input [1:0] io_ctl_mem_fcn, // @[dpath.scala:48:15] input [2:0] io_ctl_mem_typ, // @[dpath.scala:48:15] input io_ctl_exception, // @[dpath.scala:48:15] input [31:0] io_ctl_exception_cause, // @[dpath.scala:48:15] input [2:0] io_ctl_pc_sel_no_xept, // @[dpath.scala:48:15] output io_dat_if_valid_resp, // @[dpath.scala:48:15] output [31:0] io_dat_inst, // @[dpath.scala:48:15] output io_dat_br_eq, // @[dpath.scala:48:15] output io_dat_br_lt, // @[dpath.scala:48:15] output io_dat_br_ltu, // @[dpath.scala:48:15] output io_dat_inst_misaligned, // @[dpath.scala:48:15] output io_dat_data_misaligned, // @[dpath.scala:48:15] output io_dat_mem_store, // @[dpath.scala:48:15] output io_dat_csr_eret, // @[dpath.scala:48:15] output io_dat_csr_interrupt, // @[dpath.scala:48:15] input io_interrupt_debug, // @[dpath.scala:48:15] input io_interrupt_mtip, // @[dpath.scala:48:15] input io_interrupt_msip, // @[dpath.scala:48:15] input io_interrupt_meip, // @[dpath.scala:48:15] input io_hartid // @[dpath.scala:48:15] ); wire [31:0] _csr_io_rw_rdata; // @[dpath.scala:228:20] wire [31:0] _csr_io_time; // @[dpath.scala:228:20] wire _csr_io_interrupt; // @[dpath.scala:228:20] wire [31:0] _csr_io_interrupt_cause; // @[dpath.scala:228:20] wire [31:0] _regfile_ext_R1_data; // @[dpath.scala:142:21] wire [31:0] _regfile_ext_R2_data; // @[dpath.scala:142:21] wire io_imem_req_ready_0 = io_imem_req_ready; // @[dpath.scala:46:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[dpath.scala:46:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[dpath.scala:46:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[dpath.scala:46:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[dpath.scala:46:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[dpath.scala:46:7] wire io_ctl_stall_0 = io_ctl_stall; // @[dpath.scala:46:7] wire io_ctl_if_kill_0 = io_ctl_if_kill; // @[dpath.scala:46:7] wire [2:0] io_ctl_pc_sel_0 = io_ctl_pc_sel; // @[dpath.scala:46:7] wire [1:0] io_ctl_op1_sel_0 = io_ctl_op1_sel; // @[dpath.scala:46:7] wire [2:0] io_ctl_op2_sel_0 = io_ctl_op2_sel; // @[dpath.scala:46:7] wire [4:0] io_ctl_alu_fun_0 = io_ctl_alu_fun; // @[dpath.scala:46:7] wire [1:0] io_ctl_wb_sel_0 = io_ctl_wb_sel; // @[dpath.scala:46:7] wire io_ctl_rf_wen_0 = io_ctl_rf_wen; // @[dpath.scala:46:7] wire [2:0] io_ctl_csr_cmd_0 = io_ctl_csr_cmd; // @[dpath.scala:46:7] wire io_ctl_mem_val_0 = io_ctl_mem_val; // @[dpath.scala:46:7] wire [1:0] io_ctl_mem_fcn_0 = io_ctl_mem_fcn; // @[dpath.scala:46:7] wire [2:0] io_ctl_mem_typ_0 = io_ctl_mem_typ; // @[dpath.scala:46:7] wire io_ctl_exception_0 = io_ctl_exception; // @[dpath.scala:46:7] wire [31:0] io_ctl_exception_cause_0 = io_ctl_exception_cause; // @[dpath.scala:46:7] wire [2:0] io_ctl_pc_sel_no_xept_0 = io_ctl_pc_sel_no_xept; // @[dpath.scala:46:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[dpath.scala:46:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[dpath.scala:46:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[dpath.scala:46:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[dpath.scala:46:7] wire io_hartid_0 = io_hartid; // @[dpath.scala:46:7] wire [4:0] io_ddpath_addr = 5'h0; // @[dpath.scala:46:7] wire [31:0] io_ddpath_wdata = 32'h0; // @[dpath.scala:46:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[dpath.scala:46:7] wire io_ddpath_validreq = 1'h0; // @[dpath.scala:46:7] wire io_ddpath_resetpc = 1'h0; // @[dpath.scala:46:7] wire io_imem_req_bits_fcn = 1'h0; // @[dpath.scala:46:7] wire io_dmem_req_valid = 1'h0; // @[dpath.scala:46:7] wire io_dmem_req_bits_fcn = 1'h0; // @[dpath.scala:46:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[dpath.scala:46:7] wire [2:0] io_dmem_req_bits_typ = 3'h0; // @[dpath.scala:46:7] wire [31:0] io_reset_vector = 32'h10000; // @[dpath.scala:46:7] wire [31:0] _exe_jump_reg_target_T_2 = 32'hFFFFFFFE; // @[dpath.scala:213:71] wire [11:0] _imm_u_sext_T = 12'h0; // @[dpath.scala:173:36] wire [26:0] _imm_z_T = 27'h0; // @[dpath.scala:167:24] wire _io_imem_req_valid_T; // @[dpath.scala:106:28] wire [31:0] exe_alu_out; // @[dpath.scala:192:28] wire [31:0] exe_rs2_data; // @[dpath.scala:158:26] wire _io_dat_if_valid_resp_T; // @[dpath.scala:103:49] wire _io_dat_br_eq_T; // @[dpath.scala:278:35] wire _io_dat_br_lt_T_2; // @[dpath.scala:279:42] wire _io_dat_br_ltu_T; // @[dpath.scala:280:42] wire _io_dat_inst_misaligned_T_13; // @[dpath.scala:219:98] wire _io_dat_data_misaligned_T_3; // @[dpath.scala:286:85] wire _io_dat_mem_store_T; // @[dpath.scala:287:39] wire interrupt_edge; // @[dpath.scala:253:42] wire [31:0] io_ddpath_rdata_0; // @[dpath.scala:46:7] wire [31:0] io_imem_req_bits_addr_0; // @[dpath.scala:46:7] wire io_imem_req_valid_0; // @[dpath.scala:46:7] wire [31:0] io_dmem_req_bits_addr_0; // @[dpath.scala:46:7] wire [31:0] io_dmem_req_bits_data_0; // @[dpath.scala:46:7] wire io_dat_if_valid_resp_0; // @[dpath.scala:46:7] wire [31:0] io_dat_inst_0; // @[dpath.scala:46:7] wire io_dat_br_eq_0; // @[dpath.scala:46:7] wire io_dat_br_lt_0; // @[dpath.scala:46:7] wire io_dat_br_ltu_0; // @[dpath.scala:46:7] wire io_dat_inst_misaligned_0; // @[dpath.scala:46:7] wire io_dat_data_misaligned_0; // @[dpath.scala:46:7] wire io_dat_mem_store_0; // @[dpath.scala:46:7] wire io_dat_csr_eret_0; // @[dpath.scala:46:7] wire io_dat_csr_interrupt_0; // @[dpath.scala:46:7] wire [31:0] tval_data_ma; // @[dpath.scala:52:27] wire [31:0] _tval_inst_ma_T_5; // @[Mux.scala:126:16] wire [31:0] tval_inst_ma; // @[dpath.scala:53:27] reg [31:0] if_reg_pc; // @[dpath.scala:57:27] assign io_imem_req_bits_addr_0 = if_reg_pc; // @[dpath.scala:46:7, :57:27] reg [31:0] exe_reg_pc; // @[dpath.scala:59:34] reg [31:0] exe_reg_pc_plus4; // @[dpath.scala:60:34] reg [31:0] exe_reg_inst; // @[dpath.scala:61:34] assign io_dat_inst_0 = exe_reg_inst; // @[dpath.scala:46:7, :61:34] reg exe_reg_valid; // @[dpath.scala:62:34] wire [31:0] _if_pc_next_T_9; // @[Mux.scala:126:16] wire [31:0] if_pc_next; // @[dpath.scala:66:34] wire [31:0] _exe_br_target_T_1; // @[dpath.scala:211:38] wire [31:0] exe_br_target; // @[dpath.scala:67:34] wire [31:0] _exe_jmp_target_T_1; // @[dpath.scala:212:38] wire [31:0] exe_jmp_target; // @[dpath.scala:68:34] wire [31:0] _exe_jump_reg_target_T_3; // @[dpath.scala:213:69] wire [31:0] exe_jump_reg_target; // @[dpath.scala:69:34] wire [31:0] exception_target; // @[dpath.scala:70:34] wire [32:0] _if_pc_plus4_T = {1'h0, if_reg_pc} + 33'h4; // @[dpath.scala:57:27, :77:33] wire [31:0] if_pc_plus4 = _if_pc_plus4_T[31:0]; // @[dpath.scala:77:33] wire _if_pc_next_T = io_ctl_pc_sel_0 == 3'h0; // @[dpath.scala:46:7, :80:34] wire _if_pc_next_T_1 = io_ctl_pc_sel_0 == 3'h1; // @[dpath.scala:46:7, :81:34] wire _if_pc_next_T_2 = io_ctl_pc_sel_0 == 3'h2; // @[dpath.scala:46:7, :82:34] wire _if_pc_next_T_3 = io_ctl_pc_sel_0 == 3'h3; // @[dpath.scala:46:7, :83:34] wire _if_pc_next_T_4 = io_ctl_pc_sel_0 == 3'h4; // @[dpath.scala:46:7, :84:34] wire [31:0] _if_pc_next_T_5 = _if_pc_next_T_4 ? exception_target : if_pc_plus4; // @[Mux.scala:126:16] wire [31:0] _if_pc_next_T_6 = _if_pc_next_T_3 ? exe_jump_reg_target : _if_pc_next_T_5; // @[Mux.scala:126:16] wire [31:0] _if_pc_next_T_7 = _if_pc_next_T_2 ? exe_jmp_target : _if_pc_next_T_6; // @[Mux.scala:126:16] wire [31:0] _if_pc_next_T_8 = _if_pc_next_T_1 ? exe_br_target : _if_pc_next_T_7; // @[Mux.scala:126:16] assign _if_pc_next_T_9 = _if_pc_next_T ? if_pc_plus4 : _if_pc_next_T_8; // @[Mux.scala:126:16] assign if_pc_next = _if_pc_next_T_9; // @[Mux.scala:126:16] reg [31:0] if_inst_buffer; // @[dpath.scala:89:32] reg if_inst_buffer_valid; // @[dpath.scala:90:38] assign _io_dat_if_valid_resp_T = if_inst_buffer_valid \| io_imem_resp_valid_0; // @[dpath.scala:46:7, :90:38, :103:49] assign io_dat_if_valid_resp_0 = _io_dat_if_valid_resp_T; // @[dpath.scala:46:7, :103:49] assign _io_imem_req_valid_T = ~if_inst_buffer_valid; // @[dpath.scala:90:38, :106:28] assign io_imem_req_valid_0 = _io_imem_req_valid_T; // @[dpath.scala:46:7, :106:28] wire [31:0] if_inst = if_inst_buffer_valid ? if_inst_buffer : io_imem_resp_bits_data_0; // @[dpath.scala:46:7, :89:32, :90:38, :110:21] wire [4:0] exe_rs1_addr = exe_reg_inst[19:15]; // @[dpath.scala:61:34, :134:35] wire [4:0] _imm_z_T_1 = exe_reg_inst[19:15]; // @[dpath.scala:61:34, :134:35, :167:46] wire [4:0] exe_rs2_addr = exe_reg_inst[24:20]; // @[dpath.scala:61:34, :135:35] wire [4:0] exe_wbaddr = exe_reg_inst[11:7]; // @[dpath.scala:61:34, :136:35] wire [4:0] _imm_s_T_1 = exe_reg_inst[11:7]; // @[dpath.scala:61:34, :136:35, :163:54] wire [31:0] _exe_wbdata_T_7; // @[Mux.scala:126:16] wire [31:0] exe_wbdata; // @[dpath.scala:138:25] wire _exe_wben_T = ~io_ctl_exception_0; // @[dpath.scala:46:7, :139:36] wire exe_wben = io_ctl_rf_wen_0 & _exe_wben_T; // @[dpath.scala:46:7, :139:{33,36}] wire _exe_rs1_data_T = \|exe_rs1_addr; // @[dpath.scala:134:35, :157:41] wire [31:0] exe_rs1_data = _exe_rs1_data_T ? _regfile_ext_R2_data : 32'h0; // @[dpath.scala:142:21, :157:{26,41}] wire [31:0] _io_dat_br_lt_T = exe_rs1_data; // @[dpath.scala:157:26, :279:35] wire _exe_rs2_data_T = \|exe_rs2_addr; // @[dpath.scala:135:35, :158:41] assign exe_rs2_data = _exe_rs2_data_T ? _regfile_ext_R1_data : 32'h0; // @[dpath.scala:142:21, :158:{26,41}] assign io_dmem_req_bits_data_0 = exe_rs2_data; // @[dpath.scala:46:7, :158:26] wire [31:0] _io_dat_br_lt_T_1 = exe_rs2_data; // @[dpath.scala:158:26, :279:57] wire [11:0] imm_i = exe_reg_inst[31:20]; // @[dpath.scala:61:34, :162:28] wire [11:0] _csr_io_rw_addr_T = exe_reg_inst[31:20]; // @[dpath.scala:61:34, :162:28, :231:35] wire [6:0] _imm_s_T = exe_reg_inst[31:25]; // @[dpath.scala:61:34, :163:32] wire [11:0] imm_s = {_imm_s_T, _imm_s_T_1}; // @[dpath.scala:163:{19,32,54}] wire _imm_b_T = exe_reg_inst[31]; // @[dpath.scala:61:34, :164:32] wire _imm_j_T = exe_reg_inst[31]; // @[dpath.scala:61:34, :164:32, :166:32] wire _imm_b_T_1 = exe_reg_inst[7]; // @[dpath.scala:61:34, :164:50] wire [5:0] _imm_b_T_2 = exe_reg_inst[30:25]; // @[dpath.scala:61:34, :164:67] wire [3:0] _imm_b_T_3 = exe_reg_inst[11:8]; // @[dpath.scala:61:34, :164:88] wire [9:0] imm_b_lo = {_imm_b_T_2, _imm_b_T_3}; // @[dpath.scala:164:{19,67,88}] wire [1:0] imm_b_hi = {_imm_b_T, _imm_b_T_1}; // @[dpath.scala:164:{19,32,50}] wire [11:0] imm_b = {imm_b_hi, imm_b_lo}; // @[dpath.scala:164:19] wire [19:0] imm_u = exe_reg_inst[31:12]; // @[dpath.scala:61:34, :165:28] wire [7:0] _imm_j_T_1 = exe_reg_inst[19:12]; // @[dpath.scala:61:34, :166:50] wire _imm_j_T_2 = exe_reg_inst[20]; // @[dpath.scala:61:34, :166:71] wire [9:0] _imm_j_T_3 = exe_reg_inst[30:21]; // @[dpath.scala:61:34, :166:89] wire [10:0] imm_j_lo = {_imm_j_T_2, _imm_j_T_3}; // @[dpath.scala:166:{19,71,89}] wire [8:0] imm_j_hi = {_imm_j_T, _imm_j_T_1}; // @[dpath.scala:166:{19,32,50}] wire [19:0] imm_j = {imm_j_hi, imm_j_lo}; // @[dpath.scala:166:19] wire [31:0] imm_z = {27'h0, _imm_z_T_1}; // @[dpath.scala:167:{19,46}] wire _imm_i_sext_T = imm_i[11]; // @[dpath.scala:162:28, :170:38] wire [19:0] _imm_i_sext_T_1 = {20{_imm_i_sext_T}}; // @[dpath.scala:170:{29,38}] wire [31:0] imm_i_sext = {_imm_i_sext_T_1, imm_i}; // @[dpath.scala:162:28, :170:{24,29}] wire _imm_s_sext_T = imm_s[11]; // @[dpath.scala:163:19, :171:38] wire [19:0] _imm_s_sext_T_1 = {20{_imm_s_sext_T}}; // @[dpath.scala:171:{29,38}] wire [31:0] imm_s_sext = {_imm_s_sext_T_1, imm_s}; // @[dpath.scala:163:19, :171:{24,29}] wire _imm_b_sext_T = imm_b[11]; // @[dpath.scala:164:19, :172:38] wire [18:0] _imm_b_sext_T_1 = {19{_imm_b_sext_T}}; // @[dpath.scala:172:{29,38}] wire [30:0] imm_b_sext_hi = {_imm_b_sext_T_1, imm_b}; // @[dpath.scala:164:19, :172:{24,29}] wire [31:0] imm_b_sext = {imm_b_sext_hi, 1'h0}; // @[dpath.scala:172:24] wire [31:0] imm_u_sext = {imm_u, 12'h0}; // @[dpath.scala:165:28, :173:24] wire _imm_j_sext_T = imm_j[19]; // @[dpath.scala:166:19, :174:38] wire [10:0] _imm_j_sext_T_1 = {11{_imm_j_sext_T}}; // @[dpath.scala:174:{29,38}] wire [30:0] imm_j_sext_hi = {_imm_j_sext_T_1, imm_j}; // @[dpath.scala:166:19, :174:{24,29}] wire [31:0] imm_j_sext = {imm_j_sext_hi, 1'h0}; // @[dpath.scala:174:24] wire _exe_alu_op1_T = io_ctl_op1_sel_0 == 2'h0; // @[dpath.scala:46:7, :178:32] wire _exe_alu_op1_T_1 = io_ctl_op1_sel_0 == 2'h1; // @[dpath.scala:46:7, :179:32] wire _exe_alu_op1_T_2 = io_ctl_op1_sel_0 == 2'h2; // @[dpath.scala:46:7, :180:32] wire [31:0] _exe_alu_op1_T_3 = _exe_alu_op1_T_2 ? imm_z : 32'h0; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op1_T_4 = _exe_alu_op1_T_1 ? imm_u_sext : _exe_alu_op1_T_3; // @[Mux.scala:126:16] wire [31:0] exe_alu_op1 = _exe_alu_op1_T ? exe_rs1_data : _exe_alu_op1_T_4; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_13 = exe_alu_op1; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_22 = exe_alu_op1; // @[Mux.scala:126:16] wire _exe_alu_op2_T = io_ctl_op2_sel_0 == 3'h0; // @[dpath.scala:46:7, :184:32] wire _exe_alu_op2_T_1 = io_ctl_op2_sel_0 == 3'h1; // @[dpath.scala:46:7, :185:32] wire _exe_alu_op2_T_2 = io_ctl_op2_sel_0 == 3'h2; // @[dpath.scala:46:7, :186:32] wire _exe_alu_op2_T_3 = io_ctl_op2_sel_0 == 3'h3; // @[dpath.scala:46:7, :187:32] wire [31:0] _exe_alu_op2_T_4 = _exe_alu_op2_T_3 ? imm_s_sext : 32'h0; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op2_T_5 = _exe_alu_op2_T_2 ? imm_i_sext : _exe_alu_op2_T_4; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op2_T_6 = _exe_alu_op2_T_1 ? exe_reg_pc : _exe_alu_op2_T_5; // @[Mux.scala:126:16] wire [31:0] exe_alu_op2 = _exe_alu_op2_T ? exe_rs2_data : _exe_alu_op2_T_6; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_14 = exe_alu_op2; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_38; // @[Mux.scala:126:16] assign io_dmem_req_bits_addr_0 = exe_alu_out; // @[dpath.scala:46:7, :192:28] assign tval_data_ma = exe_alu_out; // @[dpath.scala:52:27, :192:28] wire [4:0] alu_shamt = exe_alu_op2[4:0]; // @[Mux.scala:126:16] wire _exe_alu_out_T = io_ctl_alu_fun_0 == 5'h1; // @[dpath.scala:46:7, :197:35] wire [32:0] _GEN = {1'h0, exe_alu_op1}; // @[Mux.scala:126:16] wire [32:0] _GEN_0 = {1'h0, exe_alu_op2}; // @[Mux.scala:126:16] wire [32:0] _exe_alu_out_T_1 = _GEN + _GEN_0; // @[dpath.scala:197:65] wire [31:0] _exe_alu_out_T_2 = _exe_alu_out_T_1[31:0]; // @[dpath.scala:197:65] wire _exe_alu_out_T_3 = io_ctl_alu_fun_0 == 5'h2; // @[dpath.scala:46:7, :198:35] wire [32:0] _exe_alu_out_T_4 = _GEN - _GEN_0; // @[dpath.scala:197:65, :198:65] wire [31:0] _exe_alu_out_T_5 = _exe_alu_out_T_4[31:0]; // @[dpath.scala:198:65] wire _exe_alu_out_T_6 = io_ctl_alu_fun_0 == 5'h6; // @[dpath.scala:46:7, :199:35] wire [31:0] _exe_alu_out_T_7 = exe_alu_op1 & exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_8 = io_ctl_alu_fun_0 == 5'h7; // @[dpath.scala:46:7, :200:35] wire [31:0] _exe_alu_out_T_9 = exe_alu_op1 \| exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_10 = io_ctl_alu_fun_0 == 5'h8; // @[dpath.scala:46:7, :201:35] wire [31:0] _exe_alu_out_T_11 = exe_alu_op1 ^ exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_12 = io_ctl_alu_fun_0 == 5'h9; // @[dpath.scala:46:7, :202:35] wire _exe_alu_out_T_15 = $signed(_exe_alu_out_T_13) < $signed(_exe_alu_out_T_14); // @[dpath.scala:202:{65,72,86}] wire _exe_alu_out_T_16 = io_ctl_alu_fun_0 == 5'hA; // @[dpath.scala:46:7, :203:35] wire _exe_alu_out_T_17 = exe_alu_op1 < exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_18 = io_ctl_alu_fun_0 == 5'h3; // @[dpath.scala:46:7, :204:35] wire [62:0] _exe_alu_out_T_19 = {31'h0, exe_alu_op1} << alu_shamt; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_20 = _exe_alu_out_T_19[31:0]; // @[dpath.scala:204:{66,79}] wire _exe_alu_out_T_21 = io_ctl_alu_fun_0 == 5'h5; // @[dpath.scala:46:7, :205:35] wire [31:0] _GEN_1 = {27'h0, alu_shamt}; // @[dpath.scala:194:31, :205:72] wire [31:0] _exe_alu_out_T_23 = $signed($signed(_exe_alu_out_T_22) >>> _GEN_1); // @[dpath.scala:205:{65,72}] wire [31:0] _exe_alu_out_T_24 = _exe_alu_out_T_23; // @[dpath.scala:205:{72,86}] wire _exe_alu_out_T_25 = io_ctl_alu_fun_0 == 5'h4; // @[dpath.scala:46:7, :206:35] wire [31:0] _exe_alu_out_T_26 = exe_alu_op1 >> _GEN_1; // @[Mux.scala:126:16] wire _exe_alu_out_T_27 = io_ctl_alu_fun_0 == 5'hB; // @[dpath.scala:46:7, :207:35] wire [31:0] _exe_alu_out_T_28 = _exe_alu_out_T_27 ? exe_alu_op1 : 32'h0; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_25 ? _exe_alu_out_T_26 : _exe_alu_out_T_28; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_30 = _exe_alu_out_T_21 ? _exe_alu_out_T_24 : _exe_alu_out_T_29; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_31 = _exe_alu_out_T_18 ? _exe_alu_out_T_20 : _exe_alu_out_T_30; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_32 = _exe_alu_out_T_16 ? {31'h0, _exe_alu_out_T_17} : _exe_alu_out_T_31; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_33 = _exe_alu_out_T_12 ? {31'h0, _exe_alu_out_T_15} : _exe_alu_out_T_32; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_34 = _exe_alu_out_T_10 ? _exe_alu_out_T_11 : _exe_alu_out_T_33; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_35 = _exe_alu_out_T_8 ? _exe_alu_out_T_9 : _exe_alu_out_T_34; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_36 = _exe_alu_out_T_6 ? _exe_alu_out_T_7 : _exe_alu_out_T_35; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_37 = _exe_alu_out_T_3 ? _exe_alu_out_T_5 : _exe_alu_out_T_36; // @[Mux.scala:126:16] assign _exe_alu_out_T_38 = _exe_alu_out_T ? _exe_alu_out_T_2 : _exe_alu_out_T_37; // @[Mux.scala:126:16] assign exe_alu_out = _exe_alu_out_T_38; // @[Mux.scala:126:16] wire [32:0] _GEN_2 = {1'h0, exe_reg_pc}; // @[dpath.scala:59:34, :211:38] wire [32:0] _exe_br_target_T = _GEN_2 + {1'h0, imm_b_sext}; // @[dpath.scala:172:24, :211:38] assign _exe_br_target_T_1 = _exe_br_target_T[31:0]; // @[dpath.scala:211:38] assign exe_br_target = _exe_br_target_T_1; // @[dpath.scala:67:34, :211:38] wire [32:0] _exe_jmp_target_T = _GEN_2 + {1'h0, imm_j_sext}; // @[dpath.scala:174:24, :211:38, :212:38] assign _exe_jmp_target_T_1 = _exe_jmp_target_T[31:0]; // @[dpath.scala:212:38] assign exe_jmp_target = _exe_jmp_target_T_1; // @[dpath.scala:68:34, :212:38] wire [32:0] _exe_jump_reg_target_T = {1'h0, exe_rs1_data} + {1'h0, imm_i_sext}; // @[dpath.scala:157:26, :170:24, :213:48] wire [31:0] _exe_jump_reg_target_T_1 = _exe_jump_reg_target_T[31:0]; // @[dpath.scala:213:48] assign _exe_jump_reg_target_T_3 = _exe_jump_reg_target_T_1 & 32'hFFFFFFFE; // @[dpath.scala:213:{48,69}] assign exe_jump_reg_target = _exe_jump_reg_target_T_3; // @[dpath.scala:69:34, :213:69] wire [1:0] _io_dat_inst_misaligned_T = exe_br_target[1:0]; // @[dpath.scala:67:34, :218:45] wire _io_dat_inst_misaligned_T_1 = \|_io_dat_inst_misaligned_T; // @[dpath.scala:218:{45,52}] wire _GEN_3 = io_ctl_pc_sel_no_xept_0 == 3'h1; // @[dpath.scala:46:7, :218:87] wire _io_dat_inst_misaligned_T_2; // @[dpath.scala:218:87] assign _io_dat_inst_misaligned_T_2 = _GEN_3; // @[dpath.scala:218:87] wire _tval_inst_ma_T; // @[dpath.scala:222:42] assign _tval_inst_ma_T = _GEN_3; // @[dpath.scala:218:87, :222:42] wire _io_dat_inst_misaligned_T_3 = _io_dat_inst_misaligned_T_1 & _io_dat_inst_misaligned_T_2; // @[dpath.scala:218:{52,62,87}] wire [1:0] _io_dat_inst_misaligned_T_4 = exe_jmp_target[1:0]; // @[dpath.scala:68:34, :219:46] wire _io_dat_inst_misaligned_T_5 = \|_io_dat_inst_misaligned_T_4; // @[dpath.scala:219:{46,53}] wire _GEN_4 = io_ctl_pc_sel_no_xept_0 == 3'h2; // @[dpath.scala:46:7, :219:87] wire _io_dat_inst_misaligned_T_6; // @[dpath.scala:219:87] assign _io_dat_inst_misaligned_T_6 = _GEN_4; // @[dpath.scala:219:87] wire _tval_inst_ma_T_1; // @[dpath.scala:223:42] assign _tval_inst_ma_T_1 = _GEN_4; // @[dpath.scala:219:87, :223:42] wire _io_dat_inst_misaligned_T_7 = _io_dat_inst_misaligned_T_5 & _io_dat_inst_misaligned_T_6; // @[dpath.scala:219:{53,62,87}] wire _io_dat_inst_misaligned_T_8 = _io_dat_inst_misaligned_T_3 \| _io_dat_inst_misaligned_T_7; // @[dpath.scala:218:{62,98}, :219:62] wire [1:0] _io_dat_inst_misaligned_T_9 = exe_jump_reg_target[1:0]; // @[dpath.scala:69:34, :220:51] wire _io_dat_inst_misaligned_T_10 = \|_io_dat_inst_misaligned_T_9; // @[dpath.scala:220:{51,58}] wire _GEN_5 = io_ctl_pc_sel_no_xept_0 == 3'h3; // @[dpath.scala:46:7, :220:87] wire _io_dat_inst_misaligned_T_11; // @[dpath.scala:220:87] assign _io_dat_inst_misaligned_T_11 = _GEN_5; // @[dpath.scala:220:87] wire _tval_inst_ma_T_2; // @[dpath.scala:224:42] assign _tval_inst_ma_T_2 = _GEN_5; // @[dpath.scala:220:87, :224:42] wire _io_dat_inst_misaligned_T_12 = _io_dat_inst_misaligned_T_10 & _io_dat_inst_misaligned_T_11; // @[dpath.scala:220:{58,62,87}] assign _io_dat_inst_misaligned_T_13 = _io_dat_inst_misaligned_T_8 \| _io_dat_inst_misaligned_T_12; // @[dpath.scala:218:98, :219:98, :220:62] assign io_dat_inst_misaligned_0 = _io_dat_inst_misaligned_T_13; // @[dpath.scala:46:7, :219:98] wire [31:0] _tval_inst_ma_T_3 = _tval_inst_ma_T_2 ? exe_jump_reg_target : 32'h0; // @[Mux.scala:126:16] wire [31:0] _tval_inst_ma_T_4 = _tval_inst_ma_T_1 ? exe_jmp_target : _tval_inst_ma_T_3; // @[Mux.scala:126:16] assign _tval_inst_ma_T_5 = _tval_inst_ma_T ? exe_br_target : _tval_inst_ma_T_4; // @[Mux.scala:126:16] assign tval_inst_ma = _tval_inst_ma_T_5; // @[Mux.scala:126:16] wire _csr_io_retire_T = io_ctl_stall_0 \| io_ctl_exception_0; // @[dpath.scala:46:7, :236:56] wire _csr_io_retire_T_1 = ~_csr_io_retire_T; // @[dpath.scala:236:{41,56}] wire _csr_io_retire_T_2 = exe_reg_valid & _csr_io_retire_T_1; // @[dpath.scala:62:34, :236:{38,41}] wire _csr_io_tval_T = io_ctl_exception_cause_0 == 32'h2; // @[dpath.scala:46:7, :242:43] wire _csr_io_tval_T_1 = io_ctl_exception_cause_0 == 32'h0; // @[dpath.scala:46:7, :243:43] wire _csr_io_tval_T_2 = io_ctl_exception_cause_0 == 32'h6; // @[dpath.scala:46:7, :244:43] wire _csr_io_tval_T_3 = io_ctl_exception_cause_0 == 32'h4; // @[dpath.scala:46:7, :245:43] wire [31:0] _csr_io_tval_T_4 = _csr_io_tval_T_3 ? tval_data_ma : 32'h0; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_5 = _csr_io_tval_T_2 ? tval_data_ma : _csr_io_tval_T_4; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_6 = _csr_io_tval_T_1 ? tval_inst_ma : _csr_io_tval_T_5; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_7 = _csr_io_tval_T ? exe_reg_inst : _csr_io_tval_T_6; // @[Mux.scala:126:16] reg reg_interrupt_handled; // @[dpath.scala:249:39] wire _interrupt_edge_T = ~reg_interrupt_handled; // @[dpath.scala:249:39, :253:45] assign interrupt_edge = _csr_io_interrupt & _interrupt_edge_T; // @[dpath.scala:228:20, :253:{42,45}] assign io_dat_csr_interrupt_0 = interrupt_edge; // @[dpath.scala:46:7, :253:42] wire [31:0] _csr_io_cause_T = io_ctl_exception_0 ? io_ctl_exception_cause_0 : _csr_io_interrupt_cause; // @[dpath.scala:46:7, :228:20, :258:23] wire _exe_wbdata_T = io_ctl_wb_sel_0 == 2'h0; // @[dpath.scala:46:7, :269:34] wire _exe_wbdata_T_1 = io_ctl_wb_sel_0 == 2'h1; // @[dpath.scala:46:7, :270:34] wire _exe_wbdata_T_2 = io_ctl_wb_sel_0 == 2'h2; // @[dpath.scala:46:7, :271:34] wire _exe_wbdata_T_3 = &io_ctl_wb_sel_0; // @[dpath.scala:46:7, :272:34] wire [31:0] _exe_wbdata_T_4 = _exe_wbdata_T_3 ? _csr_io_rw_rdata : exe_alu_out; // @[Mux.scala:126:16] wire [31:0] _exe_wbdata_T_5 = _exe_wbdata_T_2 ? exe_reg_pc_plus4 : _exe_wbdata_T_4; // @[Mux.scala:126:16] wire [31:0] _exe_wbdata_T_6 = _exe_wbdata_T_1 ? io_dmem_resp_bits_data_0 : _exe_wbdata_T_5; // @[Mux.scala:126:16] assign _exe_wbdata_T_7 = _exe_wbdata_T ? exe_alu_out : _exe_wbdata_T_6; // @[Mux.scala:126:16] assign exe_wbdata = _exe_wbdata_T_7; // @[Mux.scala:126:16] assign _io_dat_br_eq_T = exe_rs1_data == exe_rs2_data; // @[dpath.scala:157:26, :158:26, :278:35] assign io_dat_br_eq_0 = _io_dat_br_eq_T; // @[dpath.scala:46:7, :278:35] assign _io_dat_br_lt_T_2 = $signed(_io_dat_br_lt_T) < $signed(_io_dat_br_lt_T_1); // @[dpath.scala:279:{35,42,57}] assign io_dat_br_lt_0 = _io_dat_br_lt_T_2; // @[dpath.scala:46:7, :279:42] assign _io_dat_br_ltu_T = exe_rs1_data < exe_rs2_data; // @[dpath.scala:157:26, :158:26, :280:42] assign io_dat_br_ltu_0 = _io_dat_br_ltu_T; // @[dpath.scala:46:7, :280:42] wire [2:0] misaligned_mask; // @[dpath.scala:284:30] wire [3:0] _misaligned_mask_T = {1'h0, io_ctl_mem_typ_0} - 4'h1; // @[dpath.scala:46:7, :285:53] wire [2:0] _misaligned_mask_T_1 = _misaligned_mask_T[2:0]; // @[dpath.scala:285:53] wire [1:0] _misaligned_mask_T_2 = _misaligned_mask_T_1[1:0]; // @[dpath.scala:285:{53,59}] wire [5:0] _misaligned_mask_T_3 = 6'h7 << _misaligned_mask_T_2; // @[dpath.scala:285:{34,59}] wire [5:0] _misaligned_mask_T_4 = ~_misaligned_mask_T_3; // @[dpath.scala:285:{23,34}] assign misaligned_mask = _misaligned_mask_T_4[2:0]; // @[dpath.scala:284:30, :285:{20,23}] wire [2:0] _io_dat_data_misaligned_T = exe_alu_out[2:0]; // @[dpath.scala:192:28, :286:73] wire [2:0] _io_dat_data_misaligned_T_1 = misaligned_mask & _io_dat_data_misaligned_T; // @[dpath.scala:284:30, :286:{47,73}] wire _io_dat_data_misaligned_T_2 = \|_io_dat_data_misaligned_T_1; // @[dpath.scala:286:{47,81}] assign _io_dat_data_misaligned_T_3 = _io_dat_data_misaligned_T_2 & io_ctl_mem_val_0; // @[dpath.scala:46:7, :286:{81,85}] assign io_dat_data_misaligned_0 = _io_dat_data_misaligned_T_3; // @[dpath.scala:46:7, :286:85] assign _io_dat_mem_store_T = io_ctl_mem_fcn_0 == 2'h1; // @[dpath.scala:46:7, :287:39] assign io_dat_mem_store_0 = _io_dat_mem_store_T; // @[dpath.scala:46:7, :287:39]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 13, 13) wire common_expOut : UInt<6> wire common_fractOut : UInt<10> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 5, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _roundMask_T_1) node _roundMask_T_2 = bits(roundMask_shift, 18, 7) node _roundMask_T_3 = bits(_roundMask_T_2, 7, 0) node _roundMask_T_4 = shl(UInt<4>(0hf), 4) node _roundMask_T_5 = xor(UInt<8>(0hff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 4) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 3, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 4) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 5, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 2) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 2) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 5, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 2) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 6, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 1) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 1) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 6, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 1) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_2, 11, 8) node _roundMask_T_34 = bits(_roundMask_T_33, 1, 0) node _roundMask_T_35 = bits(_roundMask_T_34, 0, 0) node _roundMask_T_36 = bits(_roundMask_T_34, 1, 1) node _roundMask_T_37 = cat(_roundMask_T_35, _roundMask_T_36) node _roundMask_T_38 = bits(_roundMask_T_33, 3, 2) node _roundMask_T_39 = bits(_roundMask_T_38, 0, 0) node _roundMask_T_40 = bits(_roundMask_T_38, 1, 1) node _roundMask_T_41 = cat(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = cat(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = cat(_roundMask_T_32, _roundMask_T_42) node _roundMask_T_44 = or(_roundMask_T_43, doShiftSigDown1) node roundMask = cat(_roundMask_T_44, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<13>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 11) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 5, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 10, 1) node _common_fractOut_T_1 = bits(roundedSig, 9, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 4) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<5>(0h8))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 12, 12) node _roundCarry_T_1 = bits(roundedSig, 11, 11) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 5) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<6>(0h38), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<6>(0h8)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<6>(0h10), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<6>(0h8), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<6>(0h8), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<6>(0h2f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<6>(0h30), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<6>(0h38), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<10>(0h200), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<10>(0h3ff), UInt<10>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20] wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [13:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[13]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [5:0] _roundMask_T = io_in_sExp_0[5:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56] wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22] wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22] wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20] wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20] wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_44 = {_roundMask_T_43[11:1], _roundMask_T_43[0] \| doShiftSigDown1}; // @[primitives.scala:77:20] wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [13:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [7:0] sRoundedExp = {io_in_sExp_0[6], io_in_sExp_0} + {{5{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[7:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 8'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[6:5]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 \| io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [5:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [5:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [5:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [5:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [9:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<15>(0h4000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_38, _T_43) node _T_85 = or(_T_84, _T_48) node _T_86 = or(_T_85, _T_53) node _T_87 = or(_T_86, _T_58) node _T_88 = or(_T_87, _T_63) node _T_89 = or(_T_88, _T_68) node _T_90 = or(_T_89, _T_73) node _T_91 = or(_T_90, _T_78) node _T_92 = or(_T_91, _T_83) node _T_93 = and(_T_33, _T_92) node _T_94 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<29>(0h10000000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = or(_T_100, _T_105) node _T_107 = and(_T_95, _T_106) node _T_108 = or(UInt<1>(0h0), _T_93) node _T_109 = or(_T_108, _T_107) node _T_110 = and(_T_32, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_110, UInt<1>(0h1), "") : assert_2 node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_115 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_114 connect _WIRE[1], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_117, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_119 node _T_120 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_121 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_122 = and(_T_120, _T_121) node _T_123 = or(UInt<1>(0h0), _T_122) node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_125 = cvt(_T_124) node _T_126 = and(_T_125, asSInt(UInt<14>(0h2000))) node _T_127 = asSInt(_T_126) node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0))) node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<17>(0h10000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<15>(0h4000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<18>(0h2f000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<17>(0h10000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<17>(0h10000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = or(_T_128, _T_133) node _T_185 = or(_T_184, _T_138) node _T_186 = or(_T_185, _T_143) node _T_187 = or(_T_186, _T_148) node _T_188 = or(_T_187, _T_153) node _T_189 = or(_T_188, _T_158) node _T_190 = or(_T_189, _T_163) node _T_191 = or(_T_190, _T_168) node _T_192 = or(_T_191, _T_173) node _T_193 = or(_T_192, _T_178) node _T_194 = or(_T_193, _T_183) node _T_195 = and(_T_123, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = and(_WIRE_1, _T_196) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_197, UInt<1>(0h1), "") : assert_3 node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(source_ok, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_204 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_204, UInt<1>(0h1), "") : assert_5 node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(is_aligned, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_211 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_211, UInt<1>(0h1), "") : assert_7 node _T_215 = not(io.in.a.bits.mask) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_216, UInt<1>(0h1), "") : assert_8 node _T_220 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_220, UInt<1>(0h1), "") : assert_9 node _T_224 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_224 : node _T_225 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_226 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_229 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_230 = or(_T_228, _T_229) node _T_231 = and(_T_227, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<15>(0h4000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<13>(0h1000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<18>(0h2f000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<17>(0h10000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<27>(0h4000000))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<13>(0h1000))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_238, _T_243) node _T_285 = or(_T_284, _T_248) node _T_286 = or(_T_285, _T_253) node _T_287 = or(_T_286, _T_258) node _T_288 = or(_T_287, _T_263) node _T_289 = or(_T_288, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = and(_T_233, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_232, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _T_314 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_314 connect _WIRE_2[1], _T_315 node _T_316 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_317 = mux(_WIRE_2[0], _T_316, UInt<1>(0h0)) node _T_318 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = or(_T_317, _T_318) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_319 node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<14>(0h2000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<13>(0h1000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<15>(0h4000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<18>(0h2f000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_328, _T_333) node _T_385 = or(_T_384, _T_338) node _T_386 = or(_T_385, _T_343) node _T_387 = or(_T_386, _T_348) node _T_388 = or(_T_387, _T_353) node _T_389 = or(_T_388, _T_358) node _T_390 = or(_T_389, _T_363) node _T_391 = or(_T_390, _T_368) node _T_392 = or(_T_391, _T_373) node _T_393 = or(_T_392, _T_378) node _T_394 = or(_T_393, _T_383) node _T_395 = and(_T_323, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = and(_WIRE_3, _T_396) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_397, UInt<1>(0h1), "") : assert_11 node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(source_ok, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_404 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_404, UInt<1>(0h1), "") : assert_13 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(is_aligned, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_411 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_411, UInt<1>(0h1), "") : assert_15 node _T_415 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_415, UInt<1>(0h1), "") : assert_16 node _T_419 = not(io.in.a.bits.mask) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_420, UInt<1>(0h1), "") : assert_17 node _T_424 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_424, UInt<1>(0h1), "") : assert_18 node _T_428 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_428 : node _T_429 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_430 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_433 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_434 = or(_T_432, _T_433) node _T_435 = and(_T_431, _T_434) node _T_436 = or(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_436, UInt<1>(0h1), "") : assert_19 node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = and(_T_443, _T_448) node _T_450 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_451 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_452 = and(_T_450, _T_451) node _T_453 = or(UInt<1>(0h0), _T_452) node _T_454 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<14>(0h2000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<18>(0h2f000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<13>(0h1000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<27>(0h4000000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<29>(0h10000000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = or(_T_458, _T_463) node _T_500 = or(_T_499, _T_468) node _T_501 = or(_T_500, _T_473) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_483) node _T_504 = or(_T_503, _T_488) node _T_505 = or(_T_504, _T_493) node _T_506 = or(_T_505, _T_498) node _T_507 = and(_T_453, _T_506) node _T_508 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_509 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_510 = and(_T_508, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<15>(0h4000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = or(_T_516, _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = or(UInt<1>(0h0), _T_449) node _T_525 = or(_T_524, _T_507) node _T_526 = or(_T_525, _T_523) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_526, UInt<1>(0h1), "") : assert_20 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_536 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_536, UInt<1>(0h1), "") : assert_23 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_540, UInt<1>(0h1), "") : assert_24 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_544, UInt<1>(0h1), "") : assert_25 node _T_548 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_553 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_554 = or(_T_552, _T_553) node _T_555 = and(_T_551, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = and(_T_560, _T_565) node _T_567 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_568 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<14>(0h2000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<18>(0h2f000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<17>(0h10000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<17>(0h10000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<27>(0h4000000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<13>(0h1000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<29>(0h10000000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = or(_T_575, _T_580) node _T_612 = or(_T_611, _T_585) node _T_613 = or(_T_612, _T_590) node _T_614 = or(_T_613, _T_595) node _T_615 = or(_T_614, _T_600) node _T_616 = or(_T_615, _T_605) node _T_617 = or(_T_616, _T_610) node _T_618 = and(_T_570, _T_617) node _T_619 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_620 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<15>(0h4000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = or(_T_634, _T_639) node _T_641 = and(_T_629, _T_640) node _T_642 = or(UInt<1>(0h0), _T_566) node _T_643 = or(_T_642, _T_618) node _T_644 = or(_T_643, _T_625) node _T_645 = or(_T_644, _T_641) node _T_646 = and(_T_556, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_646, UInt<1>(0h1), "") : assert_26 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(is_aligned, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_656 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(_T_656, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_656, UInt<1>(0h1), "") : assert_29 node _T_660 = eq(io.in.a.bits.mask, mask) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_660, UInt<1>(0h1), "") : assert_30 node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_664 : node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_669 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_670 = or(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_675 = and(_T_673, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<13>(0h1000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_685 = and(_T_683, _T_684) node _T_686 = or(UInt<1>(0h0), _T_685) node _T_687 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_688 = cvt(_T_687) node _T_689 = and(_T_688, asSInt(UInt<14>(0h2000))) node _T_690 = asSInt(_T_689) node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0))) node _T_692 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<18>(0h2f000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<17>(0h10000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<13>(0h1000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_718 = cvt(_T_717) node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000))) node _T_720 = asSInt(_T_719) node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0))) node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_723 = cvt(_T_722) node _T_724 = and(_T_723, asSInt(UInt<29>(0h10000000))) node _T_725 = asSInt(_T_724) node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0))) node _T_727 = or(_T_691, _T_696) node _T_728 = or(_T_727, _T_701) node _T_729 = or(_T_728, _T_706) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_716) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_726) node _T_734 = and(_T_686, _T_733) node _T_735 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_736 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = and(_T_735, _T_740) node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_743 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_744 = and(_T_742, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_682) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_757) node _T_762 = and(_T_672, _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_762, UInt<1>(0h1), "") : assert_31 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(is_aligned, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_772 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_772, UInt<1>(0h1), "") : assert_34 node _T_776 = not(mask) node _T_777 = and(io.in.a.bits.mask, _T_776) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_778, UInt<1>(0h1), "") : assert_35 node _T_782 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_787 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_788 = or(_T_786, _T_787) node _T_789 = and(_T_785, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<15>(0h4000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<18>(0h2f000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<29>(0h10000000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_799, _T_804) node _T_851 = or(_T_850, _T_809) node _T_852 = or(_T_851, _T_814) node _T_853 = or(_T_852, _T_819) node _T_854 = or(_T_853, _T_824) node _T_855 = or(_T_854, _T_829) node _T_856 = or(_T_855, _T_834) node _T_857 = or(_T_856, _T_839) node _T_858 = or(_T_857, _T_844) node _T_859 = or(_T_858, _T_849) node _T_860 = and(_T_794, _T_859) node _T_861 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_862 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<17>(0h10000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = and(_T_861, _T_866) node _T_868 = or(UInt<1>(0h0), _T_860) node _T_869 = or(_T_868, _T_867) node _T_870 = and(_T_790, _T_869) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_870, UInt<1>(0h1), "") : assert_36 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(source_ok, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(is_aligned, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_880 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_880, UInt<1>(0h1), "") : assert_39 node _T_884 = eq(io.in.a.bits.mask, mask) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_884, UInt<1>(0h1), "") : assert_40 node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_888 : node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_893 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_894 = or(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<14>(0h2000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<15>(0h4000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<13>(0h1000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<18>(0h2f000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<17>(0h10000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_932 = cvt(_T_931) node _T_933 = and(_T_932, asSInt(UInt<13>(0h1000))) node _T_934 = asSInt(_T_933) node _T_935 = eq(_T_934, asSInt(UInt<1>(0h0))) node _T_936 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<17>(0h10000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_942 = cvt(_T_941) node _T_943 = and(_T_942, asSInt(UInt<27>(0h4000000))) node _T_944 = asSInt(_T_943) node _T_945 = eq(_T_944, asSInt(UInt<1>(0h0))) node _T_946 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<13>(0h1000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<29>(0h10000000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = or(_T_905, _T_910) node _T_957 = or(_T_956, _T_915) node _T_958 = or(_T_957, _T_920) node _T_959 = or(_T_958, _T_925) node _T_960 = or(_T_959, _T_930) node _T_961 = or(_T_960, _T_935) node _T_962 = or(_T_961, _T_940) node _T_963 = or(_T_962, _T_945) node _T_964 = or(_T_963, _T_950) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_900, _T_965) node _T_967 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = and(_T_967, _T_972) node _T_974 = or(UInt<1>(0h0), _T_966) node _T_975 = or(_T_974, _T_973) node _T_976 = and(_T_896, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_976, UInt<1>(0h1), "") : assert_41 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_986 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_986, UInt<1>(0h1), "") : assert_44 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_990, UInt<1>(0h1), "") : assert_45 node _T_994 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_994 : node _T_995 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_996 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_997 = and(_T_995, _T_996) node _T_998 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_999 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_1000 = or(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) node _T_1002 = or(UInt<1>(0h0), _T_1001) node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = and(_T_1006, _T_1011) node _T_1013 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1014 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<14>(0h2000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<15>(0h4000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<18>(0h2f000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<13>(0h1000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<27>(0h4000000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1055 = cvt(_T_1054) node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000))) node _T_1057 = asSInt(_T_1056) node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0))) node _T_1059 = or(_T_1018, _T_1023) node _T_1060 = or(_T_1059, _T_1028) node _T_1061 = or(_T_1060, _T_1033) node _T_1062 = or(_T_1061, _T_1038) node _T_1063 = or(_T_1062, _T_1043) node _T_1064 = or(_T_1063, _T_1048) node _T_1065 = or(_T_1064, _T_1053) node _T_1066 = or(_T_1065, _T_1058) node _T_1067 = and(_T_1013, _T_1066) node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = or(UInt<1>(0h0), _T_1070) node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1073 = cvt(_T_1072) node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000))) node _T_1075 = asSInt(_T_1074) node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0))) node _T_1077 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<29>(0h10000000))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _T_1083 = and(_T_1071, _T_1082) node _T_1084 = or(UInt<1>(0h0), _T_1012) node _T_1085 = or(_T_1084, _T_1067) node _T_1086 = or(_T_1085, _T_1083) node _T_1087 = and(_T_1002, _T_1086) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_46 node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(is_aligned, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1097 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_49 node _T_1101 = eq(io.in.a.bits.mask, mask) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_50 node _T_1105 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1109 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_54 node _T_1121 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_55 node _T_1125 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_56 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_57 node _T_1133 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1133 : node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(source_ok_1, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(sink_ok, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1140 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_60 node _T_1144 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_61 node _T_1148 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_62 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_63 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = or(UInt<1>(0h1), _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_64 node _T_1161 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1161 : node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok_1, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(sink_ok, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1168 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_67 node _T_1172 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_68 node _T_1176 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_69 node _T_1180 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1181 = or(_T_1180, io.in.d.bits.corrupt) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_70 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_71 node _T_1190 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1190 : node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(source_ok_1, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1194 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_73 node _T_1198 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_74 node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1203 = or(UInt<1>(0h1), _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_75 node _T_1207 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1207 : node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(source_ok_1, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1211 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_77 node _T_1215 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1216 = or(_T_1215, io.in.d.bits.corrupt) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_78 node _T_1220 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1221 = or(UInt<1>(0h1), _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_79 node _T_1225 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1225 : node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(source_ok_1, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_81 node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_82 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1242 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_84 node _T_1246 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = or(_T_1247, _T_1252) node _T_1254 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) node _T_1256 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1255, _T_1260) node _T_1262 = and(_T_1253, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<18>(0h21000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<18>(0h22000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<13>(0h1000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<18>(0h23000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<13>(0h1000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[17] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2]) node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3]) node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4]) node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5]) node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15]) node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1266 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1266 : node _T_1267 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1268 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1267 connect _WIRE_4[1], _T_1268 node _T_1269 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1270 = mux(_WIRE_4[0], _T_1269, UInt<1>(0h0)) node _T_1271 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1272 = or(_T_1270, _T_1271) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1272 node _T_1273 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1274 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = or(UInt<1>(0h0), _T_1275) node _T_1277 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1278 = cvt(_T_1277) node _T_1279 = and(_T_1278, asSInt(UInt<14>(0h2000))) node _T_1280 = asSInt(_T_1279) node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0))) node _T_1282 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1288 = cvt(_T_1287) node _T_1289 = and(_T_1288, asSInt(UInt<17>(0h10000))) node _T_1290 = asSInt(_T_1289) node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0))) node _T_1292 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1293 = cvt(_T_1292) node _T_1294 = and(_T_1293, asSInt(UInt<15>(0h4000))) node _T_1295 = asSInt(_T_1294) node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0))) node _T_1297 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<18>(0h2f000))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1308 = cvt(_T_1307) node _T_1309 = and(_T_1308, asSInt(UInt<17>(0h10000))) node _T_1310 = asSInt(_T_1309) node _T_1311 = eq(_T_1310, asSInt(UInt<1>(0h0))) node _T_1312 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1313 = cvt(_T_1312) node _T_1314 = and(_T_1313, asSInt(UInt<13>(0h1000))) node _T_1315 = asSInt(_T_1314) node _T_1316 = eq(_T_1315, asSInt(UInt<1>(0h0))) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<27>(0h4000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<29>(0h10000000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1281, _T_1286) node _T_1338 = or(_T_1337, _T_1291) node _T_1339 = or(_T_1338, _T_1296) node _T_1340 = or(_T_1339, _T_1301) node _T_1341 = or(_T_1340, _T_1306) node _T_1342 = or(_T_1341, _T_1311) node _T_1343 = or(_T_1342, _T_1316) node _T_1344 = or(_T_1343, _T_1321) node _T_1345 = or(_T_1344, _T_1326) node _T_1346 = or(_T_1345, _T_1331) node _T_1347 = or(_T_1346, _T_1336) node _T_1348 = and(_T_1276, _T_1347) node _T_1349 = or(UInt<1>(0h0), _T_1348) node _T_1350 = and(_WIRE_5, _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_86 node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(address_ok, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(legal_source, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1363 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_90 node _T_1367 = eq(io.in.b.bits.mask, mask_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_91 node _T_1371 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_92 node _T_1375 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1375 : node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = or(UInt<1>(0h0), _T_1378) node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1391 = cvt(_T_1390) node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000))) node _T_1393 = asSInt(_T_1392) node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0))) node _T_1395 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1396 = cvt(_T_1395) node _T_1397 = and(_T_1396, asSInt(UInt<15>(0h4000))) node _T_1398 = asSInt(_T_1397) node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0))) node _T_1400 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1401 = cvt(_T_1400) node _T_1402 = and(_T_1401, asSInt(UInt<13>(0h1000))) node _T_1403 = asSInt(_T_1402) node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0))) node _T_1405 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<18>(0h2f000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1416 = cvt(_T_1415) node _T_1417 = and(_T_1416, asSInt(UInt<13>(0h1000))) node _T_1418 = asSInt(_T_1417) node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0))) node _T_1420 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1421 = cvt(_T_1420) node _T_1422 = and(_T_1421, asSInt(UInt<17>(0h10000))) node _T_1423 = asSInt(_T_1422) node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1426 = cvt(_T_1425) node _T_1427 = and(_T_1426, asSInt(UInt<27>(0h4000000))) node _T_1428 = asSInt(_T_1427) node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0))) node _T_1430 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1431 = cvt(_T_1430) node _T_1432 = and(_T_1431, asSInt(UInt<13>(0h1000))) node _T_1433 = asSInt(_T_1432) node _T_1434 = eq(_T_1433, asSInt(UInt<1>(0h0))) node _T_1435 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<29>(0h10000000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1384, _T_1389) node _T_1441 = or(_T_1440, _T_1394) node _T_1442 = or(_T_1441, _T_1399) node _T_1443 = or(_T_1442, _T_1404) node _T_1444 = or(_T_1443, _T_1409) node _T_1445 = or(_T_1444, _T_1414) node _T_1446 = or(_T_1445, _T_1419) node _T_1447 = or(_T_1446, _T_1424) node _T_1448 = or(_T_1447, _T_1429) node _T_1449 = or(_T_1448, _T_1434) node _T_1450 = or(_T_1449, _T_1439) node _T_1451 = and(_T_1379, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = and(UInt<1>(0h0), _T_1452) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_93 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(address_ok, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(legal_source, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1466 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_97 node _T_1470 = eq(io.in.b.bits.mask, mask_1) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_98 node _T_1474 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_99 node _T_1478 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1478 : node _T_1479 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1480 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = or(UInt<1>(0h0), _T_1481) node _T_1483 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1484 = cvt(_T_1483) node _T_1485 = and(_T_1484, asSInt(UInt<14>(0h2000))) node _T_1486 = asSInt(_T_1485) node _T_1487 = eq(_T_1486, asSInt(UInt<1>(0h0))) node _T_1488 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1489 = cvt(_T_1488) node _T_1490 = and(_T_1489, asSInt(UInt<13>(0h1000))) node _T_1491 = asSInt(_T_1490) node _T_1492 = eq(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1494 = cvt(_T_1493) node _T_1495 = and(_T_1494, asSInt(UInt<17>(0h10000))) node _T_1496 = asSInt(_T_1495) node _T_1497 = eq(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<15>(0h4000))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1504 = cvt(_T_1503) node _T_1505 = and(_T_1504, asSInt(UInt<13>(0h1000))) node _T_1506 = asSInt(_T_1505) node _T_1507 = eq(_T_1506, asSInt(UInt<1>(0h0))) node _T_1508 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<18>(0h2f000))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1514 = cvt(_T_1513) node _T_1515 = and(_T_1514, asSInt(UInt<17>(0h10000))) node _T_1516 = asSInt(_T_1515) node _T_1517 = eq(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1519 = cvt(_T_1518) node _T_1520 = and(_T_1519, asSInt(UInt<13>(0h1000))) node _T_1521 = asSInt(_T_1520) node _T_1522 = eq(_T_1521, asSInt(UInt<1>(0h0))) node _T_1523 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1524 = cvt(_T_1523) node _T_1525 = and(_T_1524, asSInt(UInt<17>(0h10000))) node _T_1526 = asSInt(_T_1525) node _T_1527 = eq(_T_1526, asSInt(UInt<1>(0h0))) node _T_1528 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<27>(0h4000000))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1534 = cvt(_T_1533) node _T_1535 = and(_T_1534, asSInt(UInt<13>(0h1000))) node _T_1536 = asSInt(_T_1535) node _T_1537 = eq(_T_1536, asSInt(UInt<1>(0h0))) node _T_1538 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<29>(0h10000000))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1487, _T_1492) node _T_1544 = or(_T_1543, _T_1497) node _T_1545 = or(_T_1544, _T_1502) node _T_1546 = or(_T_1545, _T_1507) node _T_1547 = or(_T_1546, _T_1512) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1522) node _T_1550 = or(_T_1549, _T_1527) node _T_1551 = or(_T_1550, _T_1532) node _T_1552 = or(_T_1551, _T_1537) node _T_1553 = or(_T_1552, _T_1542) node _T_1554 = and(_T_1482, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = and(UInt<1>(0h0), _T_1555) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(address_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(legal_source, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1569 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_104 node _T_1573 = eq(io.in.b.bits.mask, mask_1) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_105 node _T_1577 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1579 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = or(UInt<1>(0h0), _T_1580) node _T_1582 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1583 = cvt(_T_1582) node _T_1584 = and(_T_1583, asSInt(UInt<14>(0h2000))) node _T_1585 = asSInt(_T_1584) node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0))) node _T_1587 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<15>(0h4000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<18>(0h2f000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<17>(0h10000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<13>(0h1000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<17>(0h10000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<27>(0h4000000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<29>(0h10000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1586, _T_1591) node _T_1643 = or(_T_1642, _T_1596) node _T_1644 = or(_T_1643, _T_1601) node _T_1645 = or(_T_1644, _T_1606) node _T_1646 = or(_T_1645, _T_1611) node _T_1647 = or(_T_1646, _T_1616) node _T_1648 = or(_T_1647, _T_1621) node _T_1649 = or(_T_1648, _T_1626) node _T_1650 = or(_T_1649, _T_1631) node _T_1651 = or(_T_1650, _T_1636) node _T_1652 = or(_T_1651, _T_1641) node _T_1653 = and(_T_1581, _T_1652) node _T_1654 = or(UInt<1>(0h0), _T_1653) node _T_1655 = and(UInt<1>(0h0), _T_1654) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_106 node _T_1659 = asUInt(reset) node _T_1660 = eq(_T_1659, UInt<1>(0h0)) when _T_1660 : node _T_1661 = eq(address_ok, UInt<1>(0h0)) when _T_1661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(legal_source, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1668 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_110 node _T_1672 = not(mask_1) node _T_1673 = and(io.in.b.bits.mask, _T_1672) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_111 node _T_1678 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1678 : node _T_1679 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1680 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = or(UInt<1>(0h0), _T_1681) node _T_1683 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1684 = cvt(_T_1683) node _T_1685 = and(_T_1684, asSInt(UInt<14>(0h2000))) node _T_1686 = asSInt(_T_1685) node _T_1687 = eq(_T_1686, asSInt(UInt<1>(0h0))) node _T_1688 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1689 = cvt(_T_1688) node _T_1690 = and(_T_1689, asSInt(UInt<13>(0h1000))) node _T_1691 = asSInt(_T_1690) node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0))) node _T_1693 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1699 = cvt(_T_1698) node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000))) node _T_1701 = asSInt(_T_1700) node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0))) node _T_1703 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1704 = cvt(_T_1703) node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000))) node _T_1706 = asSInt(_T_1705) node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0))) node _T_1708 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1709 = cvt(_T_1708) node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000))) node _T_1711 = asSInt(_T_1710) node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0))) node _T_1713 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1714 = cvt(_T_1713) node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000))) node _T_1716 = asSInt(_T_1715) node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0))) node _T_1718 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1719 = cvt(_T_1718) node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000))) node _T_1721 = asSInt(_T_1720) node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1724 = cvt(_T_1723) node _T_1725 = and(_T_1724, asSInt(UInt<17>(0h10000))) node _T_1726 = asSInt(_T_1725) node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0))) node _T_1728 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<27>(0h4000000))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1734 = cvt(_T_1733) node _T_1735 = and(_T_1734, asSInt(UInt<13>(0h1000))) node _T_1736 = asSInt(_T_1735) node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0))) node _T_1738 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<29>(0h10000000))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1687, _T_1692) node _T_1744 = or(_T_1743, _T_1697) node _T_1745 = or(_T_1744, _T_1702) node _T_1746 = or(_T_1745, _T_1707) node _T_1747 = or(_T_1746, _T_1712) node _T_1748 = or(_T_1747, _T_1717) node _T_1749 = or(_T_1748, _T_1722) node _T_1750 = or(_T_1749, _T_1727) node _T_1751 = or(_T_1750, _T_1732) node _T_1752 = or(_T_1751, _T_1737) node _T_1753 = or(_T_1752, _T_1742) node _T_1754 = and(_T_1682, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_112 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_116 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_117 node _T_1777 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<15>(0h4000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<13>(0h1000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1786, _T_1791) node _T_1843 = or(_T_1842, _T_1796) node _T_1844 = or(_T_1843, _T_1801) node _T_1845 = or(_T_1844, _T_1806) node _T_1846 = or(_T_1845, _T_1811) node _T_1847 = or(_T_1846, _T_1816) node _T_1848 = or(_T_1847, _T_1821) node _T_1849 = or(_T_1848, _T_1826) node _T_1850 = or(_T_1849, _T_1831) node _T_1851 = or(_T_1850, _T_1836) node _T_1852 = or(_T_1851, _T_1841) node _T_1853 = and(_T_1781, _T_1852) node _T_1854 = or(UInt<1>(0h0), _T_1853) node _T_1855 = and(UInt<1>(0h0), _T_1854) node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(_T_1855, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1855, UInt<1>(0h1), "") : assert_118 node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(address_ok, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(legal_source, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1868 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_122 node _T_1872 = eq(io.in.b.bits.mask, mask_1) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_123 node _T_1876 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1876 : node _T_1877 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1878 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1879 = and(_T_1877, _T_1878) node _T_1880 = or(UInt<1>(0h0), _T_1879) node _T_1881 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<14>(0h2000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<13>(0h1000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<17>(0h10000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<15>(0h4000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1907 = cvt(_T_1906) node _T_1908 = and(_T_1907, asSInt(UInt<18>(0h2f000))) node _T_1909 = asSInt(_T_1908) node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0))) node _T_1911 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1912 = cvt(_T_1911) node _T_1913 = and(_T_1912, asSInt(UInt<17>(0h10000))) node _T_1914 = asSInt(_T_1913) node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0))) node _T_1916 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1917 = cvt(_T_1916) node _T_1918 = and(_T_1917, asSInt(UInt<13>(0h1000))) node _T_1919 = asSInt(_T_1918) node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0))) node _T_1921 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1922 = cvt(_T_1921) node _T_1923 = and(_T_1922, asSInt(UInt<17>(0h10000))) node _T_1924 = asSInt(_T_1923) node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0))) node _T_1926 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1927 = cvt(_T_1926) node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000))) node _T_1929 = asSInt(_T_1928) node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0))) node _T_1931 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<13>(0h1000))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h10000000))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1885, _T_1890) node _T_1942 = or(_T_1941, _T_1895) node _T_1943 = or(_T_1942, _T_1900) node _T_1944 = or(_T_1943, _T_1905) node _T_1945 = or(_T_1944, _T_1910) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1920) node _T_1948 = or(_T_1947, _T_1925) node _T_1949 = or(_T_1948, _T_1930) node _T_1950 = or(_T_1949, _T_1935) node _T_1951 = or(_T_1950, _T_1940) node _T_1952 = and(_T_1880, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = and(UInt<1>(0h0), _T_1953) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_124 node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(address_ok, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(legal_source, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1967 = eq(io.in.b.bits.mask, mask_1) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_128 node _T_1971 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1975 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<13>(0h1000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<17>(0h10000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<18>(0h21000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<13>(0h1000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<18>(0h22000)) node _address_ok_T_131 = cvt(_address_ok_T_130) node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<13>(0h1000))) node _address_ok_T_133 = asSInt(_address_ok_T_132) node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0))) node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<18>(0h23000)) node _address_ok_T_136 = cvt(_address_ok_T_135) node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000))) node _address_ok_T_138 = asSInt(_address_ok_T_137) node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0))) node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _address_ok_T_141 = cvt(_address_ok_T_140) node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<13>(0h1000))) node _address_ok_T_143 = asSInt(_address_ok_T_142) node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0))) node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_146 = cvt(_address_ok_T_145) node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000))) node _address_ok_T_148 = asSInt(_address_ok_T_147) node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0))) node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_151 = cvt(_address_ok_T_150) node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000))) node _address_ok_T_153 = asSInt(_address_ok_T_152) node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0))) node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_156 = cvt(_address_ok_T_155) node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000))) node _address_ok_T_158 = asSInt(_address_ok_T_157) node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0))) node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_161 = cvt(_address_ok_T_160) node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000))) node _address_ok_T_163 = asSInt(_address_ok_T_162) node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0))) node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_166 = cvt(_address_ok_T_165) node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000))) node _address_ok_T_168 = asSInt(_address_ok_T_167) node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0))) node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_171 = cvt(_address_ok_T_170) node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000))) node _address_ok_T_173 = asSInt(_address_ok_T_172) node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0))) node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_176 = cvt(_address_ok_T_175) node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000))) node _address_ok_T_178 = asSInt(_address_ok_T_177) node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0))) node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_181 = cvt(_address_ok_T_180) node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000))) node _address_ok_T_183 = asSInt(_address_ok_T_182) node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[17] connect _address_ok_WIRE_1[0], _address_ok_T_104 connect _address_ok_WIRE_1[1], _address_ok_T_109 connect _address_ok_WIRE_1[2], _address_ok_T_114 connect _address_ok_WIRE_1[3], _address_ok_T_119 connect _address_ok_WIRE_1[4], _address_ok_T_124 connect _address_ok_WIRE_1[5], _address_ok_T_129 connect _address_ok_WIRE_1[6], _address_ok_T_134 connect _address_ok_WIRE_1[7], _address_ok_T_139 connect _address_ok_WIRE_1[8], _address_ok_T_144 connect _address_ok_WIRE_1[9], _address_ok_T_149 connect _address_ok_WIRE_1[10], _address_ok_T_154 connect _address_ok_WIRE_1[11], _address_ok_T_159 connect _address_ok_WIRE_1[12], _address_ok_T_164 connect _address_ok_WIRE_1[13], _address_ok_T_169 connect _address_ok_WIRE_1[14], _address_ok_T_174 connect _address_ok_WIRE_1[15], _address_ok_T_179 connect _address_ok_WIRE_1[16], _address_ok_T_184 node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2]) node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3]) node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4]) node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5]) node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6]) node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7]) node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8]) node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9]) node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10]) node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11]) node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15]) node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16]) node _T_1979 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) node _T_1981 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = or(_T_1980, _T_1985) node _T_1987 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) node _T_1989 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = or(_T_1988, _T_1993) node _T_1995 = and(_T_1986, _T_1994) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_131 node _T_1999 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1999 : node _T_2000 = asUInt(reset) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) when _T_2001 : node _T_2002 = eq(address_ok_1, UInt<1>(0h0)) when _T_2002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(source_ok_2, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2006 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_134 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2013 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_136 node _T_2017 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_137 node _T_2021 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2021 : node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(address_ok_1, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(source_ok_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2028 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_140 node _T_2032 = asUInt(reset) node _T_2033 = eq(_T_2032, UInt<1>(0h0)) when _T_2033 : node _T_2034 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2035 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2036 = asUInt(reset) node _T_2037 = eq(_T_2036, UInt<1>(0h0)) when _T_2037 : node _T_2038 = eq(_T_2035, UInt<1>(0h0)) when _T_2038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2035, UInt<1>(0h1), "") : assert_142 node _T_2039 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2039 : node _T_2040 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2041 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2044 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2045 = or(_T_2043, _T_2044) node _T_2046 = and(_T_2042, _T_2045) node _T_2047 = or(UInt<1>(0h0), _T_2046) node _T_2048 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<14>(0h2000))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2055 = cvt(_T_2054) node _T_2056 = and(_T_2055, asSInt(UInt<13>(0h1000))) node _T_2057 = asSInt(_T_2056) node _T_2058 = eq(_T_2057, asSInt(UInt<1>(0h0))) node _T_2059 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2060 = cvt(_T_2059) node _T_2061 = and(_T_2060, asSInt(UInt<17>(0h10000))) node _T_2062 = asSInt(_T_2061) node _T_2063 = eq(_T_2062, asSInt(UInt<1>(0h0))) node _T_2064 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2065 = cvt(_T_2064) node _T_2066 = and(_T_2065, asSInt(UInt<15>(0h4000))) node _T_2067 = asSInt(_T_2066) node _T_2068 = eq(_T_2067, asSInt(UInt<1>(0h0))) node _T_2069 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2070 = cvt(_T_2069) node _T_2071 = and(_T_2070, asSInt(UInt<13>(0h1000))) node _T_2072 = asSInt(_T_2071) node _T_2073 = eq(_T_2072, asSInt(UInt<1>(0h0))) node _T_2074 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2075 = cvt(_T_2074) node _T_2076 = and(_T_2075, asSInt(UInt<18>(0h2f000))) node _T_2077 = asSInt(_T_2076) node _T_2078 = eq(_T_2077, asSInt(UInt<1>(0h0))) node _T_2079 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<17>(0h10000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<27>(0h4000000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<13>(0h1000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2053, _T_2058) node _T_2100 = or(_T_2099, _T_2063) node _T_2101 = or(_T_2100, _T_2068) node _T_2102 = or(_T_2101, _T_2073) node _T_2103 = or(_T_2102, _T_2078) node _T_2104 = or(_T_2103, _T_2083) node _T_2105 = or(_T_2104, _T_2088) node _T_2106 = or(_T_2105, _T_2093) node _T_2107 = or(_T_2106, _T_2098) node _T_2108 = and(_T_2048, _T_2107) node _T_2109 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2110 = or(UInt<1>(0h0), _T_2109) node _T_2111 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<17>(0h10000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<29>(0h10000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = or(_T_2115, _T_2120) node _T_2122 = and(_T_2110, _T_2121) node _T_2123 = or(UInt<1>(0h0), _T_2108) node _T_2124 = or(_T_2123, _T_2122) node _T_2125 = and(_T_2047, _T_2124) node _T_2126 = asUInt(reset) node _T_2127 = eq(_T_2126, UInt<1>(0h0)) when _T_2127 : node _T_2128 = eq(_T_2125, UInt<1>(0h0)) when _T_2128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2125, UInt<1>(0h1), "") : assert_143 node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2130 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_2129 connect _WIRE_6[1], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_6[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = or(_T_2132, _T_2133) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2134 node _T_2135 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2136 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = or(UInt<1>(0h0), _T_2137) node _T_2139 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2140 = cvt(_T_2139) node _T_2141 = and(_T_2140, asSInt(UInt<14>(0h2000))) node _T_2142 = asSInt(_T_2141) node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0))) node _T_2144 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2145 = cvt(_T_2144) node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000))) node _T_2147 = asSInt(_T_2146) node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0))) node _T_2149 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2150 = cvt(_T_2149) node _T_2151 = and(_T_2150, asSInt(UInt<17>(0h10000))) node _T_2152 = asSInt(_T_2151) node _T_2153 = eq(_T_2152, asSInt(UInt<1>(0h0))) node _T_2154 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2155 = cvt(_T_2154) node _T_2156 = and(_T_2155, asSInt(UInt<15>(0h4000))) node _T_2157 = asSInt(_T_2156) node _T_2158 = eq(_T_2157, asSInt(UInt<1>(0h0))) node _T_2159 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2160 = cvt(_T_2159) node _T_2161 = and(_T_2160, asSInt(UInt<13>(0h1000))) node _T_2162 = asSInt(_T_2161) node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0))) node _T_2164 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2165 = cvt(_T_2164) node _T_2166 = and(_T_2165, asSInt(UInt<18>(0h2f000))) node _T_2167 = asSInt(_T_2166) node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<17>(0h10000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<27>(0h4000000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<13>(0h1000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<29>(0h10000000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = or(_T_2143, _T_2148) node _T_2200 = or(_T_2199, _T_2153) node _T_2201 = or(_T_2200, _T_2158) node _T_2202 = or(_T_2201, _T_2163) node _T_2203 = or(_T_2202, _T_2168) node _T_2204 = or(_T_2203, _T_2173) node _T_2205 = or(_T_2204, _T_2178) node _T_2206 = or(_T_2205, _T_2183) node _T_2207 = or(_T_2206, _T_2188) node _T_2208 = or(_T_2207, _T_2193) node _T_2209 = or(_T_2208, _T_2198) node _T_2210 = and(_T_2138, _T_2209) node _T_2211 = or(UInt<1>(0h0), _T_2210) node _T_2212 = and(_WIRE_7, _T_2211) node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(_T_2212, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2212, UInt<1>(0h1), "") : assert_144 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(source_ok_2, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2219 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_146 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_148 node _T_2230 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_149 node _T_2234 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2234 : node _T_2235 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2236 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2239 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2240 = or(_T_2238, _T_2239) node _T_2241 = and(_T_2237, _T_2240) node _T_2242 = or(UInt<1>(0h0), _T_2241) node _T_2243 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2244 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2245 = cvt(_T_2244) node _T_2246 = and(_T_2245, asSInt(UInt<14>(0h2000))) node _T_2247 = asSInt(_T_2246) node _T_2248 = eq(_T_2247, asSInt(UInt<1>(0h0))) node _T_2249 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2250 = cvt(_T_2249) node _T_2251 = and(_T_2250, asSInt(UInt<13>(0h1000))) node _T_2252 = asSInt(_T_2251) node _T_2253 = eq(_T_2252, asSInt(UInt<1>(0h0))) node _T_2254 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2255 = cvt(_T_2254) node _T_2256 = and(_T_2255, asSInt(UInt<17>(0h10000))) node _T_2257 = asSInt(_T_2256) node _T_2258 = eq(_T_2257, asSInt(UInt<1>(0h0))) node _T_2259 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2260 = cvt(_T_2259) node _T_2261 = and(_T_2260, asSInt(UInt<15>(0h4000))) node _T_2262 = asSInt(_T_2261) node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0))) node _T_2264 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2265 = cvt(_T_2264) node _T_2266 = and(_T_2265, asSInt(UInt<13>(0h1000))) node _T_2267 = asSInt(_T_2266) node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0))) node _T_2269 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = or(_T_2248, _T_2253) node _T_2295 = or(_T_2294, _T_2258) node _T_2296 = or(_T_2295, _T_2263) node _T_2297 = or(_T_2296, _T_2268) node _T_2298 = or(_T_2297, _T_2273) node _T_2299 = or(_T_2298, _T_2278) node _T_2300 = or(_T_2299, _T_2283) node _T_2301 = or(_T_2300, _T_2288) node _T_2302 = or(_T_2301, _T_2293) node _T_2303 = and(_T_2243, _T_2302) node _T_2304 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2305 = or(UInt<1>(0h0), _T_2304) node _T_2306 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2307 = cvt(_T_2306) node _T_2308 = and(_T_2307, asSInt(UInt<17>(0h10000))) node _T_2309 = asSInt(_T_2308) node _T_2310 = eq(_T_2309, asSInt(UInt<1>(0h0))) node _T_2311 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2312 = cvt(_T_2311) node _T_2313 = and(_T_2312, asSInt(UInt<29>(0h10000000))) node _T_2314 = asSInt(_T_2313) node _T_2315 = eq(_T_2314, asSInt(UInt<1>(0h0))) node _T_2316 = or(_T_2310, _T_2315) node _T_2317 = and(_T_2305, _T_2316) node _T_2318 = or(UInt<1>(0h0), _T_2303) node _T_2319 = or(_T_2318, _T_2317) node _T_2320 = and(_T_2242, _T_2319) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_150 node _T_2324 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2325 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2324 connect _WIRE_8[1], _T_2325 node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = mux(_WIRE_8[0], _T_2326, UInt<1>(0h0)) node _T_2328 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2329 = or(_T_2327, _T_2328) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2329 node _T_2330 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2331 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2332 = and(_T_2330, _T_2331) node _T_2333 = or(UInt<1>(0h0), _T_2332) node _T_2334 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2335 = cvt(_T_2334) node _T_2336 = and(_T_2335, asSInt(UInt<14>(0h2000))) node _T_2337 = asSInt(_T_2336) node _T_2338 = eq(_T_2337, asSInt(UInt<1>(0h0))) node _T_2339 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2340 = cvt(_T_2339) node _T_2341 = and(_T_2340, asSInt(UInt<13>(0h1000))) node _T_2342 = asSInt(_T_2341) node _T_2343 = eq(_T_2342, asSInt(UInt<1>(0h0))) node _T_2344 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2345 = cvt(_T_2344) node _T_2346 = and(_T_2345, asSInt(UInt<17>(0h10000))) node _T_2347 = asSInt(_T_2346) node _T_2348 = eq(_T_2347, asSInt(UInt<1>(0h0))) node _T_2349 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2350 = cvt(_T_2349) node _T_2351 = and(_T_2350, asSInt(UInt<15>(0h4000))) node _T_2352 = asSInt(_T_2351) node _T_2353 = eq(_T_2352, asSInt(UInt<1>(0h0))) node _T_2354 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2355 = cvt(_T_2354) node _T_2356 = and(_T_2355, asSInt(UInt<13>(0h1000))) node _T_2357 = asSInt(_T_2356) node _T_2358 = eq(_T_2357, asSInt(UInt<1>(0h0))) node _T_2359 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2360 = cvt(_T_2359) node _T_2361 = and(_T_2360, asSInt(UInt<18>(0h2f000))) node _T_2362 = asSInt(_T_2361) node _T_2363 = eq(_T_2362, asSInt(UInt<1>(0h0))) node _T_2364 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2365 = cvt(_T_2364) node _T_2366 = and(_T_2365, asSInt(UInt<17>(0h10000))) node _T_2367 = asSInt(_T_2366) node _T_2368 = eq(_T_2367, asSInt(UInt<1>(0h0))) node _T_2369 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2370 = cvt(_T_2369) node _T_2371 = and(_T_2370, asSInt(UInt<13>(0h1000))) node _T_2372 = asSInt(_T_2371) node _T_2373 = eq(_T_2372, asSInt(UInt<1>(0h0))) node _T_2374 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2375 = cvt(_T_2374) node _T_2376 = and(_T_2375, asSInt(UInt<17>(0h10000))) node _T_2377 = asSInt(_T_2376) node _T_2378 = eq(_T_2377, asSInt(UInt<1>(0h0))) node _T_2379 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2380 = cvt(_T_2379) node _T_2381 = and(_T_2380, asSInt(UInt<27>(0h4000000))) node _T_2382 = asSInt(_T_2381) node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0))) node _T_2384 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2385 = cvt(_T_2384) node _T_2386 = and(_T_2385, asSInt(UInt<13>(0h1000))) node _T_2387 = asSInt(_T_2386) node _T_2388 = eq(_T_2387, asSInt(UInt<1>(0h0))) node _T_2389 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2390 = cvt(_T_2389) node _T_2391 = and(_T_2390, asSInt(UInt<29>(0h10000000))) node _T_2392 = asSInt(_T_2391) node _T_2393 = eq(_T_2392, asSInt(UInt<1>(0h0))) node _T_2394 = or(_T_2338, _T_2343) node _T_2395 = or(_T_2394, _T_2348) node _T_2396 = or(_T_2395, _T_2353) node _T_2397 = or(_T_2396, _T_2358) node _T_2398 = or(_T_2397, _T_2363) node _T_2399 = or(_T_2398, _T_2368) node _T_2400 = or(_T_2399, _T_2373) node _T_2401 = or(_T_2400, _T_2378) node _T_2402 = or(_T_2401, _T_2383) node _T_2403 = or(_T_2402, _T_2388) node _T_2404 = or(_T_2403, _T_2393) node _T_2405 = and(_T_2333, _T_2404) node _T_2406 = or(UInt<1>(0h0), _T_2405) node _T_2407 = and(_WIRE_9, _T_2406) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_151 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_2, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2414 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_153 node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2421 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_155 node _T_2425 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2425 : node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(address_ok_1, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(source_ok_2, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2435 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_159 node _T_2439 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_160 node _T_2443 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2443 : node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(address_ok_1, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(source_ok_2, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2453 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_164 node _T_2457 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2457 : node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(address_ok_1, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(source_ok_2, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2467 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_168 node _T_2471 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2472 = asUInt(reset) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) when _T_2473 : node _T_2474 = eq(_T_2471, UInt<1>(0h0)) when _T_2474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2471, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2478 = eq(a_first, UInt<1>(0h0)) node _T_2479 = and(io.in.a.valid, _T_2478) when _T_2479 : node _T_2480 = eq(io.in.a.bits.opcode, opcode) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_171 node _T_2484 = eq(io.in.a.bits.param, param) node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(_T_2484, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2484, UInt<1>(0h1), "") : assert_172 node _T_2488 = eq(io.in.a.bits.size, size) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_173 node _T_2492 = eq(io.in.a.bits.source, source) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_174 node _T_2496 = eq(io.in.a.bits.address, address) node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(_T_2496, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2496, UInt<1>(0h1), "") : assert_175 node _T_2500 = and(io.in.a.ready, io.in.a.valid) node _T_2501 = and(_T_2500, a_first) when _T_2501 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2502 = eq(d_first, UInt<1>(0h0)) node _T_2503 = and(io.in.d.valid, _T_2502) when _T_2503 : node _T_2504 = eq(io.in.d.bits.opcode, opcode_1) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_176 node _T_2508 = eq(io.in.d.bits.param, param_1) node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(_T_2508, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2508, UInt<1>(0h1), "") : assert_177 node _T_2512 = eq(io.in.d.bits.size, size_1) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_178 node _T_2516 = eq(io.in.d.bits.source, source_1) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_179 node _T_2520 = eq(io.in.d.bits.sink, sink) node _T_2521 = asUInt(reset) node _T_2522 = eq(_T_2521, UInt<1>(0h0)) when _T_2522 : node _T_2523 = eq(_T_2520, UInt<1>(0h0)) when _T_2523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2520, UInt<1>(0h1), "") : assert_180 node _T_2524 = eq(io.in.d.bits.denied, denied) node _T_2525 = asUInt(reset) node _T_2526 = eq(_T_2525, UInt<1>(0h0)) when _T_2526 : node _T_2527 = eq(_T_2524, UInt<1>(0h0)) when _T_2527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2524, UInt<1>(0h1), "") : assert_181 node _T_2528 = and(io.in.d.ready, io.in.d.valid) node _T_2529 = and(_T_2528, d_first) when _T_2529 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2530 = eq(b_first, UInt<1>(0h0)) node _T_2531 = and(io.in.b.valid, _T_2530) when _T_2531 : node _T_2532 = eq(io.in.b.bits.opcode, opcode_2) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_182 node _T_2536 = eq(io.in.b.bits.param, param_2) node _T_2537 = asUInt(reset) node _T_2538 = eq(_T_2537, UInt<1>(0h0)) when _T_2538 : node _T_2539 = eq(_T_2536, UInt<1>(0h0)) when _T_2539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2536, UInt<1>(0h1), "") : assert_183 node _T_2540 = eq(io.in.b.bits.size, size_2) node _T_2541 = asUInt(reset) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) when _T_2542 : node _T_2543 = eq(_T_2540, UInt<1>(0h0)) when _T_2543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2540, UInt<1>(0h1), "") : assert_184 node _T_2544 = eq(io.in.b.bits.source, source_2) node _T_2545 = asUInt(reset) node _T_2546 = eq(_T_2545, UInt<1>(0h0)) when _T_2546 : node _T_2547 = eq(_T_2544, UInt<1>(0h0)) when _T_2547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2544, UInt<1>(0h1), "") : assert_185 node _T_2548 = eq(io.in.b.bits.address, address_1) node _T_2549 = asUInt(reset) node _T_2550 = eq(_T_2549, UInt<1>(0h0)) when _T_2550 : node _T_2551 = eq(_T_2548, UInt<1>(0h0)) when _T_2551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2548, UInt<1>(0h1), "") : assert_186 node _T_2552 = and(io.in.b.ready, io.in.b.valid) node _T_2553 = and(_T_2552, b_first) when _T_2553 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2554 = eq(c_first, UInt<1>(0h0)) node _T_2555 = and(io.in.c.valid, _T_2554) when _T_2555 : node _T_2556 = eq(io.in.c.bits.opcode, opcode_3) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_187 node _T_2560 = eq(io.in.c.bits.param, param_3) node _T_2561 = asUInt(reset) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) when _T_2562 : node _T_2563 = eq(_T_2560, UInt<1>(0h0)) when _T_2563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2560, UInt<1>(0h1), "") : assert_188 node _T_2564 = eq(io.in.c.bits.size, size_3) node _T_2565 = asUInt(reset) node _T_2566 = eq(_T_2565, UInt<1>(0h0)) when _T_2566 : node _T_2567 = eq(_T_2564, UInt<1>(0h0)) when _T_2567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2564, UInt<1>(0h1), "") : assert_189 node _T_2568 = eq(io.in.c.bits.source, source_3) node _T_2569 = asUInt(reset) node _T_2570 = eq(_T_2569, UInt<1>(0h0)) when _T_2570 : node _T_2571 = eq(_T_2568, UInt<1>(0h0)) when _T_2571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2568, UInt<1>(0h1), "") : assert_190 node _T_2572 = eq(io.in.c.bits.address, address_2) node _T_2573 = asUInt(reset) node _T_2574 = eq(_T_2573, UInt<1>(0h0)) when _T_2574 : node _T_2575 = eq(_T_2572, UInt<1>(0h0)) when _T_2575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2572, UInt<1>(0h1), "") : assert_191 node _T_2576 = and(io.in.c.ready, io.in.c.valid) node _T_2577 = and(_T_2576, c_first) when _T_2577 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2578 = and(io.in.a.valid, a_first_1) node _T_2579 = and(_T_2578, UInt<1>(0h1)) when _T_2579 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2580 = and(io.in.a.ready, io.in.a.valid) node _T_2581 = and(_T_2580, a_first_1) node _T_2582 = and(_T_2581, UInt<1>(0h1)) when _T_2582 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2583 = dshr(inflight, io.in.a.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_1) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = eq(d_release_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2593 = and(io.in.d.ready, io.in.d.valid) node _T_2594 = and(_T_2593, d_first_1) node _T_2595 = and(_T_2594, UInt<1>(0h1)) node _T_2596 = eq(d_release_ack, UInt<1>(0h0)) node _T_2597 = and(_T_2595, _T_2596) when _T_2597 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2598 = and(io.in.d.valid, d_first_1) node _T_2599 = and(_T_2598, UInt<1>(0h1)) node _T_2600 = eq(d_release_ack, UInt<1>(0h0)) node _T_2601 = and(_T_2599, _T_2600) when _T_2601 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2602 = dshr(inflight, io.in.d.bits.source) node _T_2603 = bits(_T_2602, 0, 0) node _T_2604 = or(_T_2603, same_cycle_resp) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2608 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2609 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2610 = or(_T_2608, _T_2609) node _T_2611 = asUInt(reset) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) when _T_2612 : node _T_2613 = eq(_T_2610, UInt<1>(0h0)) when _T_2613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2610, UInt<1>(0h1), "") : assert_194 node _T_2614 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2615 = asUInt(reset) node _T_2616 = eq(_T_2615, UInt<1>(0h0)) when _T_2616 : node _T_2617 = eq(_T_2614, UInt<1>(0h0)) when _T_2617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2614, UInt<1>(0h1), "") : assert_195 else : node _T_2618 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2619 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2620 = or(_T_2618, _T_2619) node _T_2621 = asUInt(reset) node _T_2622 = eq(_T_2621, UInt<1>(0h0)) when _T_2622 : node _T_2623 = eq(_T_2620, UInt<1>(0h0)) when _T_2623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2620, UInt<1>(0h1), "") : assert_196 node _T_2624 = eq(io.in.d.bits.size, a_size_lookup) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_197 node _T_2628 = and(io.in.d.valid, d_first_1) node _T_2629 = and(_T_2628, a_first_1) node _T_2630 = and(_T_2629, io.in.a.valid) node _T_2631 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2632 = and(_T_2630, _T_2631) node _T_2633 = eq(d_release_ack, UInt<1>(0h0)) node _T_2634 = and(_T_2632, _T_2633) when _T_2634 : node _T_2635 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2636 = or(_T_2635, io.in.a.ready) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_198 node _T_2640 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2641 = orr(a_set_wo_ready) node _T_2642 = eq(_T_2641, UInt<1>(0h0)) node _T_2643 = or(_T_2640, _T_2642) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_14 node _T_2647 = orr(inflight) node _T_2648 = eq(_T_2647, UInt<1>(0h0)) node _T_2649 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2650 = or(_T_2648, _T_2649) node _T_2651 = lt(watchdog, plusarg_reader.out) node _T_2652 = or(_T_2650, _T_2651) node _T_2653 = asUInt(reset) node _T_2654 = eq(_T_2653, UInt<1>(0h0)) when _T_2654 : node _T_2655 = eq(_T_2652, UInt<1>(0h0)) when _T_2655 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2652, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2656 = and(io.in.a.ready, io.in.a.valid) node _T_2657 = and(io.in.d.ready, io.in.d.valid) node _T_2658 = or(_T_2656, _T_2657) when _T_2658 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2659 = and(io.in.c.valid, c_first_1) node _T_2660 = bits(io.in.c.bits.opcode, 2, 2) node _T_2661 = bits(io.in.c.bits.opcode, 1, 1) node _T_2662 = and(_T_2660, _T_2661) node _T_2663 = and(_T_2659, _T_2662) when _T_2663 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2664 = and(io.in.c.ready, io.in.c.valid) node _T_2665 = and(_T_2664, c_first_1) node _T_2666 = bits(io.in.c.bits.opcode, 2, 2) node _T_2667 = bits(io.in.c.bits.opcode, 1, 1) node _T_2668 = and(_T_2666, _T_2667) node _T_2669 = and(_T_2665, _T_2668) when _T_2669 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2670 = dshr(inflight_1, io.in.c.bits.source) node _T_2671 = bits(_T_2670, 0, 0) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) node _T_2673 = asUInt(reset) node _T_2674 = eq(_T_2673, UInt<1>(0h0)) when _T_2674 : node _T_2675 = eq(_T_2672, UInt<1>(0h0)) when _T_2675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2672, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2676 = and(io.in.d.valid, d_first_2) node _T_2677 = and(_T_2676, UInt<1>(0h1)) node _T_2678 = and(_T_2677, d_release_ack_1) when _T_2678 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2679 = and(io.in.d.ready, io.in.d.valid) node _T_2680 = and(_T_2679, d_first_2) node _T_2681 = and(_T_2680, UInt<1>(0h1)) node _T_2682 = and(_T_2681, d_release_ack_1) when _T_2682 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2683 = and(io.in.d.valid, d_first_2) node _T_2684 = and(_T_2683, UInt<1>(0h1)) node _T_2685 = and(_T_2684, d_release_ack_1) when _T_2685 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2686 = dshr(inflight_1, io.in.d.bits.source) node _T_2687 = bits(_T_2686, 0, 0) node _T_2688 = or(_T_2687, same_cycle_resp_1) node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(_T_2688, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2688, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2692 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2693 = asUInt(reset) node _T_2694 = eq(_T_2693, UInt<1>(0h0)) when _T_2694 : node _T_2695 = eq(_T_2692, UInt<1>(0h0)) when _T_2695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2692, UInt<1>(0h1), "") : assert_203 else : node _T_2696 = eq(io.in.d.bits.size, c_size_lookup) node _T_2697 = asUInt(reset) node _T_2698 = eq(_T_2697, UInt<1>(0h0)) when _T_2698 : node _T_2699 = eq(_T_2696, UInt<1>(0h0)) when _T_2699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2696, UInt<1>(0h1), "") : assert_204 node _T_2700 = and(io.in.d.valid, d_first_2) node _T_2701 = and(_T_2700, c_first_1) node _T_2702 = and(_T_2701, io.in.c.valid) node _T_2703 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2704 = and(_T_2702, _T_2703) node _T_2705 = and(_T_2704, d_release_ack_1) node _T_2706 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2707 = and(_T_2705, _T_2706) when _T_2707 : node _T_2708 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2709 = or(_T_2708, io.in.c.ready) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_205 node _T_2713 = orr(c_set_wo_ready) when _T_2713 : node _T_2714 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2715 = asUInt(reset) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) when _T_2716 : node _T_2717 = eq(_T_2714, UInt<1>(0h0)) when _T_2717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2714, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_15 node _T_2718 = orr(inflight_1) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) node _T_2720 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2721 = or(_T_2719, _T_2720) node _T_2722 = lt(watchdog_1, plusarg_reader_1.out) node _T_2723 = or(_T_2721, _T_2722) node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(_T_2723, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2723, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2727 = and(io.in.c.ready, io.in.c.valid) node _T_2728 = and(io.in.d.ready, io.in.d.valid) node _T_2729 = or(_T_2727, _T_2728) when _T_2729 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2730 = and(io.in.d.ready, io.in.d.valid) node _T_2731 = and(_T_2730, d_first_3) node _T_2732 = bits(io.in.d.bits.opcode, 2, 2) node _T_2733 = bits(io.in.d.bits.opcode, 1, 1) node _T_2734 = eq(_T_2733, UInt<1>(0h0)) node _T_2735 = and(_T_2732, _T_2734) node _T_2736 = and(_T_2731, _T_2735) when _T_2736 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2737 = dshr(inflight_2, io.in.d.bits.sink) node _T_2738 = bits(_T_2737, 0, 0) node _T_2739 = eq(_T_2738, UInt<1>(0h0)) node _T_2740 = asUInt(reset) node _T_2741 = eq(_T_2740, UInt<1>(0h0)) when _T_2741 : node _T_2742 = eq(_T_2739, UInt<1>(0h0)) when _T_2742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2739, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2743 = and(io.in.e.ready, io.in.e.valid) node _T_2744 = and(_T_2743, UInt<1>(0h1)) node _T_2745 = and(_T_2744, UInt<1>(0h1)) when _T_2745 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2746 = or(d_set, inflight_2) node _T_2747 = dshr(_T_2746, io.in.e.bits.sink) node _T_2748 = bits(_T_2747, 0, 0) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_7( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 \| _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 \| _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 \| _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 \| _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 \| _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_10 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_10; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_11 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_11; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_12 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_13 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_15 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_16 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_18 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_20 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_21 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_21}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 \| _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 \| _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 \| _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 \| _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 \| _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_22 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_22; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_23 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_23; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_23; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_24 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_24; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_24; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_25 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_26 = 2'h1 << _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_26; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_27 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_27; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_27; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_28 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_29 = 2'h1 << _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_29; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_30 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_31 = 2'h1 << _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_31; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_31; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_33 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_33; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_55 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} inst input_buffer of InputBuffer_55 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) inst route_arbiter of Arbiter2_RouteComputerReq_9 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2] wire vcalloc_vals : UInt<1>[2] node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0)) node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11) node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1]) when _T_19 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = bits(vcalloc_sel, 0, 0) node _mask_T_6 = bits(vcalloc_sel, 1, 1) node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_7, _mask_T_8) wire _mask_WIRE : UInt<2> connect _mask_WIRE, _mask_T_9 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2] node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10 connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2] node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_14 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_14.egress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_14.egress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_34 connect _io_vcalloc_req_bits_WIRE_14.ingress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_14.ingress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_14.vnet_id, _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_14 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_20 = bits(vcalloc_sel, 1, 1) node _T_21 = and(vcalloc_vals[1], _T_20) node _T_22 = and(_T_21, io.vcalloc_req.ready) when _T_22 : connect states[1].g, UInt<3>(0h3) node _T_23 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_23 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready) node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1) connect io.debug.va_stall, _io_debug_va_stall_T_3 node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_24 : node _T_25 = bits(vcalloc_sel, 0, 0) when _T_25 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_26 = bits(vcalloc_sel, 1, 1) when _T_26 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_136 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] node _credit_available_T = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node _credit_available_T_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node _credit_available_T_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi = cat(states[1].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi, credit_available_lo) node _credit_available_T_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node _credit_available_T_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_1 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_27 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_28 = and(_T_27, input_buffer.io.deq[1].bits.tail) when _T_28 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_5 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5 node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_7 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1) connect salloc_outs[0].vid, _salloc_outs_0_vid_T node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _vc_sel_WIRE : UInt<1>[2] node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_4 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_7 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_3 : UInt<1>[2] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_10 connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4 node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_13 connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5 connect vc_sel.`1`, _vc_sel_WIRE_3 wire _vc_sel_WIRE_6 : UInt<1>[2] node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_16 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_19 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 connect vc_sel.`2`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_22 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`3`, _vc_sel_WIRE_9 node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1) node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0)) node _virt_channel_T_7 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0)) node _virt_channel_T_8 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = or(_virt_channel_T_6, _virt_channel_T_7) node _virt_channel_T_11 = or(_virt_channel_T_10, _virt_channel_T_8) node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_9) wire virt_channel : UInt<1> connect virt_channel, _virt_channel_T_12 node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_29 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3) wire _salloc_outs_0_flit_payload_WIRE : UInt<37> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`3`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) node _T_30 = asUInt(reset) when _T_30 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0)	module InputUnit_55( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_1 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<14>(0h2000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<18>(0h2f000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<17>(0h10000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<27>(0h4000000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = or(_T_386, _T_391) node _T_423 = or(_T_422, _T_396) node _T_424 = or(_T_423, _T_401) node _T_425 = or(_T_424, _T_406) node _T_426 = or(_T_425, _T_411) node _T_427 = or(_T_426, _T_416) node _T_428 = or(_T_427, _T_421) node _T_429 = and(_T_381, _T_428) node _T_430 = or(UInt<1>(0h0), _T_429) node _T_431 = and(_T_380, _T_430) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_431, UInt<1>(0h1), "") : assert_2 node _T_435 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<1>(0h0)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_8) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_442 = shr(io.in.a.bits.source, 2) node _T_443 = eq(_T_442, UInt<1>(0h1)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_9) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_448 = shr(io.in.a.bits.source, 2) node _T_449 = eq(_T_448, UInt<2>(0h2)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_10) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_453 = and(_T_451, _T_452) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_454 = shr(io.in.a.bits.source, 2) node _T_455 = eq(_T_454, UInt<2>(0h3)) node _T_456 = leq(UInt<1>(0h0), uncommonBits_11) node _T_457 = and(_T_455, _T_456) node _T_458 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_484 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_435 connect _WIRE[1], _T_441 connect _WIRE[2], _T_447 connect _WIRE[3], _T_453 connect _WIRE[4], _T_459 connect _WIRE[5], _T_460 connect _WIRE[6], _T_461 connect _WIRE[7], _T_462 connect _WIRE[8], _T_463 connect _WIRE[9], _T_464 connect _WIRE[10], _T_465 connect _WIRE[11], _T_466 connect _WIRE[12], _T_467 connect _WIRE[13], _T_468 connect _WIRE[14], _T_469 connect _WIRE[15], _T_470 connect _WIRE[16], _T_471 connect _WIRE[17], _T_472 connect _WIRE[18], _T_473 connect _WIRE[19], _T_474 connect _WIRE[20], _T_475 connect _WIRE[21], _T_476 connect _WIRE[22], _T_477 connect _WIRE[23], _T_478 connect _WIRE[24], _T_479 connect _WIRE[25], _T_480 connect _WIRE[26], _T_481 connect _WIRE[27], _T_482 connect _WIRE[28], _T_483 connect _WIRE[29], _T_484 node _T_485 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_486 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_487 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_488 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_489 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_490 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_491 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_492 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_493 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_494 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_495 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_496 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_497 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_498 = mux(_WIRE[5], _T_485, UInt<1>(0h0)) node _T_499 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_500 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_501 = mux(_WIRE[8], _T_486, UInt<1>(0h0)) node _T_502 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_503 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_504 = mux(_WIRE[11], _T_487, UInt<1>(0h0)) node _T_505 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_506 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_507 = mux(_WIRE[14], _T_488, UInt<1>(0h0)) node _T_508 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_509 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_510 = mux(_WIRE[17], _T_489, UInt<1>(0h0)) node _T_511 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_512 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = mux(_WIRE[20], _T_490, UInt<1>(0h0)) node _T_514 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_515 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_516 = mux(_WIRE[23], _T_491, UInt<1>(0h0)) node _T_517 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_518 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE[26], _T_492, UInt<1>(0h0)) node _T_520 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_522 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = or(_T_493, _T_494) node _T_524 = or(_T_523, _T_495) node _T_525 = or(_T_524, _T_496) node _T_526 = or(_T_525, _T_497) node _T_527 = or(_T_526, _T_498) node _T_528 = or(_T_527, _T_499) node _T_529 = or(_T_528, _T_500) node _T_530 = or(_T_529, _T_501) node _T_531 = or(_T_530, _T_502) node _T_532 = or(_T_531, _T_503) node _T_533 = or(_T_532, _T_504) node _T_534 = or(_T_533, _T_505) node _T_535 = or(_T_534, _T_506) node _T_536 = or(_T_535, _T_507) node _T_537 = or(_T_536, _T_508) node _T_538 = or(_T_537, _T_509) node _T_539 = or(_T_538, _T_510) node _T_540 = or(_T_539, _T_511) node _T_541 = or(_T_540, _T_512) node _T_542 = or(_T_541, _T_513) node _T_543 = or(_T_542, _T_514) node _T_544 = or(_T_543, _T_515) node _T_545 = or(_T_544, _T_516) node _T_546 = or(_T_545, _T_517) node _T_547 = or(_T_546, _T_518) node _T_548 = or(_T_547, _T_519) node _T_549 = or(_T_548, _T_520) node _T_550 = or(_T_549, _T_521) node _T_551 = or(_T_550, _T_522) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_551 node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_553 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_554 = and(_T_552, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<14>(0h2000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<17>(0h10000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<18>(0h2f000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<17>(0h10000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<13>(0h1000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<27>(0h4000000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<13>(0h1000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = or(_T_560, _T_565) node _T_597 = or(_T_596, _T_570) node _T_598 = or(_T_597, _T_575) node _T_599 = or(_T_598, _T_580) node _T_600 = or(_T_599, _T_585) node _T_601 = or(_T_600, _T_590) node _T_602 = or(_T_601, _T_595) node _T_603 = and(_T_555, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = and(_WIRE_1, _T_604) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_605, UInt<1>(0h1), "") : assert_3 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(source_ok, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_612 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_612, UInt<1>(0h1), "") : assert_5 node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(is_aligned, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_619 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_619, UInt<1>(0h1), "") : assert_7 node _T_623 = not(io.in.a.bits.mask) node _T_624 = eq(_T_623, UInt<1>(0h0)) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_624, UInt<1>(0h1), "") : assert_8 node _T_628 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_628, UInt<1>(0h1), "") : assert_9 node _T_632 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_632 : node _T_633 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_634 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_635 = and(_T_633, _T_634) node _T_636 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<1>(0h0)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_12) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<1>(0h1)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_13) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_649 = shr(io.in.a.bits.source, 2) node _T_650 = eq(_T_649, UInt<2>(0h2)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_14) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_654 = and(_T_652, _T_653) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_655 = shr(io.in.a.bits.source, 2) node _T_656 = eq(_T_655, UInt<2>(0h3)) node _T_657 = leq(UInt<1>(0h0), uncommonBits_15) node _T_658 = and(_T_656, _T_657) node _T_659 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_662 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_663 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_664 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_667 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_668 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_669 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_685 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_686 = or(_T_636, _T_642) node _T_687 = or(_T_686, _T_648) node _T_688 = or(_T_687, _T_654) node _T_689 = or(_T_688, _T_660) node _T_690 = or(_T_689, _T_661) node _T_691 = or(_T_690, _T_662) node _T_692 = or(_T_691, _T_663) node _T_693 = or(_T_692, _T_664) node _T_694 = or(_T_693, _T_665) node _T_695 = or(_T_694, _T_666) node _T_696 = or(_T_695, _T_667) node _T_697 = or(_T_696, _T_668) node _T_698 = or(_T_697, _T_669) node _T_699 = or(_T_698, _T_670) node _T_700 = or(_T_699, _T_671) node _T_701 = or(_T_700, _T_672) node _T_702 = or(_T_701, _T_673) node _T_703 = or(_T_702, _T_674) node _T_704 = or(_T_703, _T_675) node _T_705 = or(_T_704, _T_676) node _T_706 = or(_T_705, _T_677) node _T_707 = or(_T_706, _T_678) node _T_708 = or(_T_707, _T_679) node _T_709 = or(_T_708, _T_680) node _T_710 = or(_T_709, _T_681) node _T_711 = or(_T_710, _T_682) node _T_712 = or(_T_711, _T_683) node _T_713 = or(_T_712, _T_684) node _T_714 = or(_T_713, _T_685) node _T_715 = and(_T_635, _T_714) node _T_716 = or(UInt<1>(0h0), _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<14>(0h2000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<13>(0h1000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<27>(0h4000000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = or(_T_722, _T_727) node _T_759 = or(_T_758, _T_732) node _T_760 = or(_T_759, _T_737) node _T_761 = or(_T_760, _T_742) node _T_762 = or(_T_761, _T_747) node _T_763 = or(_T_762, _T_752) node _T_764 = or(_T_763, _T_757) node _T_765 = and(_T_717, _T_764) node _T_766 = or(UInt<1>(0h0), _T_765) node _T_767 = and(_T_716, _T_766) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_767, UInt<1>(0h1), "") : assert_10 node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_16) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_17) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_18) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_19) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_817 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_818 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_819 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_771 connect _WIRE_2[1], _T_777 connect _WIRE_2[2], _T_783 connect _WIRE_2[3], _T_789 connect _WIRE_2[4], _T_795 connect _WIRE_2[5], _T_796 connect _WIRE_2[6], _T_797 connect _WIRE_2[7], _T_798 connect _WIRE_2[8], _T_799 connect _WIRE_2[9], _T_800 connect _WIRE_2[10], _T_801 connect _WIRE_2[11], _T_802 connect _WIRE_2[12], _T_803 connect _WIRE_2[13], _T_804 connect _WIRE_2[14], _T_805 connect _WIRE_2[15], _T_806 connect _WIRE_2[16], _T_807 connect _WIRE_2[17], _T_808 connect _WIRE_2[18], _T_809 connect _WIRE_2[19], _T_810 connect _WIRE_2[20], _T_811 connect _WIRE_2[21], _T_812 connect _WIRE_2[22], _T_813 connect _WIRE_2[23], _T_814 connect _WIRE_2[24], _T_815 connect _WIRE_2[25], _T_816 connect _WIRE_2[26], _T_817 connect _WIRE_2[27], _T_818 connect _WIRE_2[28], _T_819 connect _WIRE_2[29], _T_820 node _T_821 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_822 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_823 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_824 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_825 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_826 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_827 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_828 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_829 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_831 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_832 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_833 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_834 = mux(_WIRE_2[5], _T_821, UInt<1>(0h0)) node _T_835 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_836 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_837 = mux(_WIRE_2[8], _T_822, UInt<1>(0h0)) node _T_838 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_839 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_840 = mux(_WIRE_2[11], _T_823, UInt<1>(0h0)) node _T_841 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_842 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_843 = mux(_WIRE_2[14], _T_824, UInt<1>(0h0)) node _T_844 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_845 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_846 = mux(_WIRE_2[17], _T_825, UInt<1>(0h0)) node _T_847 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_848 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_849 = mux(_WIRE_2[20], _T_826, UInt<1>(0h0)) node _T_850 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_851 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_852 = mux(_WIRE_2[23], _T_827, UInt<1>(0h0)) node _T_853 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_855 = mux(_WIRE_2[26], _T_828, UInt<1>(0h0)) node _T_856 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_857 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_858 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_859 = or(_T_829, _T_830) node _T_860 = or(_T_859, _T_831) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = or(_T_886, _T_858) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_887 node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<14>(0h2000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<13>(0h1000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<18>(0h2f000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<27>(0h4000000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = or(_T_896, _T_901) node _T_933 = or(_T_932, _T_906) node _T_934 = or(_T_933, _T_911) node _T_935 = or(_T_934, _T_916) node _T_936 = or(_T_935, _T_921) node _T_937 = or(_T_936, _T_926) node _T_938 = or(_T_937, _T_931) node _T_939 = and(_T_891, _T_938) node _T_940 = or(UInt<1>(0h0), _T_939) node _T_941 = and(_WIRE_3, _T_940) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_941, UInt<1>(0h1), "") : assert_11 node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(source_ok, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_948 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_948, UInt<1>(0h1), "") : assert_13 node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(is_aligned, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_955 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_955, UInt<1>(0h1), "") : assert_15 node _T_959 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_959, UInt<1>(0h1), "") : assert_16 node _T_963 = not(io.in.a.bits.mask) node _T_964 = eq(_T_963, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_964, UInt<1>(0h1), "") : assert_17 node _T_968 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_968, UInt<1>(0h1), "") : assert_18 node _T_972 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_972 : node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_974 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_975 = and(_T_973, _T_974) node _T_976 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_977 = shr(io.in.a.bits.source, 2) node _T_978 = eq(_T_977, UInt<1>(0h0)) node _T_979 = leq(UInt<1>(0h0), uncommonBits_20) node _T_980 = and(_T_978, _T_979) node _T_981 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_983 = shr(io.in.a.bits.source, 2) node _T_984 = eq(_T_983, UInt<1>(0h1)) node _T_985 = leq(UInt<1>(0h0), uncommonBits_21) node _T_986 = and(_T_984, _T_985) node _T_987 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_988 = and(_T_986, _T_987) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_989 = shr(io.in.a.bits.source, 2) node _T_990 = eq(_T_989, UInt<2>(0h2)) node _T_991 = leq(UInt<1>(0h0), uncommonBits_22) node _T_992 = and(_T_990, _T_991) node _T_993 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_994 = and(_T_992, _T_993) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_995 = shr(io.in.a.bits.source, 2) node _T_996 = eq(_T_995, UInt<2>(0h3)) node _T_997 = leq(UInt<1>(0h0), uncommonBits_23) node _T_998 = and(_T_996, _T_997) node _T_999 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1025 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1026 = or(_T_976, _T_982) node _T_1027 = or(_T_1026, _T_988) node _T_1028 = or(_T_1027, _T_994) node _T_1029 = or(_T_1028, _T_1000) node _T_1030 = or(_T_1029, _T_1001) node _T_1031 = or(_T_1030, _T_1002) node _T_1032 = or(_T_1031, _T_1003) node _T_1033 = or(_T_1032, _T_1004) node _T_1034 = or(_T_1033, _T_1005) node _T_1035 = or(_T_1034, _T_1006) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = or(_T_1036, _T_1008) node _T_1038 = or(_T_1037, _T_1009) node _T_1039 = or(_T_1038, _T_1010) node _T_1040 = or(_T_1039, _T_1011) node _T_1041 = or(_T_1040, _T_1012) node _T_1042 = or(_T_1041, _T_1013) node _T_1043 = or(_T_1042, _T_1014) node _T_1044 = or(_T_1043, _T_1015) node _T_1045 = or(_T_1044, _T_1016) node _T_1046 = or(_T_1045, _T_1017) node _T_1047 = or(_T_1046, _T_1018) node _T_1048 = or(_T_1047, _T_1019) node _T_1049 = or(_T_1048, _T_1020) node _T_1050 = or(_T_1049, _T_1021) node _T_1051 = or(_T_1050, _T_1022) node _T_1052 = or(_T_1051, _T_1023) node _T_1053 = or(_T_1052, _T_1024) node _T_1054 = or(_T_1053, _T_1025) node _T_1055 = and(_T_975, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_19 node _T_1060 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1061 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1065 = cvt(_T_1064) node _T_1066 = and(_T_1065, asSInt(UInt<13>(0h1000))) node _T_1067 = asSInt(_T_1066) node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0))) node _T_1069 = and(_T_1063, _T_1068) node _T_1070 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1071 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = or(UInt<1>(0h0), _T_1072) node _T_1074 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1075 = cvt(_T_1074) node _T_1076 = and(_T_1075, asSInt(UInt<14>(0h2000))) node _T_1077 = asSInt(_T_1076) node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0))) node _T_1079 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1080 = cvt(_T_1079) node _T_1081 = and(_T_1080, asSInt(UInt<17>(0h10000))) node _T_1082 = asSInt(_T_1081) node _T_1083 = eq(_T_1082, asSInt(UInt<1>(0h0))) node _T_1084 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1085 = cvt(_T_1084) node _T_1086 = and(_T_1085, asSInt(UInt<18>(0h2f000))) node _T_1087 = asSInt(_T_1086) node _T_1088 = eq(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1090 = cvt(_T_1089) node _T_1091 = and(_T_1090, asSInt(UInt<17>(0h10000))) node _T_1092 = asSInt(_T_1091) node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0))) node _T_1094 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1095 = cvt(_T_1094) node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000))) node _T_1097 = asSInt(_T_1096) node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0))) node _T_1099 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<27>(0h4000000))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1105 = cvt(_T_1104) node _T_1106 = and(_T_1105, asSInt(UInt<13>(0h1000))) node _T_1107 = asSInt(_T_1106) node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0))) node _T_1109 = or(_T_1078, _T_1083) node _T_1110 = or(_T_1109, _T_1088) node _T_1111 = or(_T_1110, _T_1093) node _T_1112 = or(_T_1111, _T_1098) node _T_1113 = or(_T_1112, _T_1103) node _T_1114 = or(_T_1113, _T_1108) node _T_1115 = and(_T_1073, _T_1114) node _T_1116 = or(UInt<1>(0h0), _T_1069) node _T_1117 = or(_T_1116, _T_1115) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_20 node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(source_ok, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(is_aligned, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1127 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_23 node _T_1131 = eq(io.in.a.bits.mask, mask) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_24 node _T_1135 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_25 node _T_1139 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1139 : node _T_1140 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1141 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1144 = shr(io.in.a.bits.source, 2) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) node _T_1146 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1149 = and(_T_1147, _T_1148) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1150 = shr(io.in.a.bits.source, 2) node _T_1151 = eq(_T_1150, UInt<1>(0h1)) node _T_1152 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1155 = and(_T_1153, _T_1154) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1156 = shr(io.in.a.bits.source, 2) node _T_1157 = eq(_T_1156, UInt<2>(0h2)) node _T_1158 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1159 = and(_T_1157, _T_1158) node _T_1160 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1161 = and(_T_1159, _T_1160) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1162 = shr(io.in.a.bits.source, 2) node _T_1163 = eq(_T_1162, UInt<2>(0h3)) node _T_1164 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1165 = and(_T_1163, _T_1164) node _T_1166 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1169 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1170 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1171 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1172 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1173 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1174 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1175 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1176 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1177 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1178 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1179 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1180 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1181 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1182 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1193 = or(_T_1143, _T_1149) node _T_1194 = or(_T_1193, _T_1155) node _T_1195 = or(_T_1194, _T_1161) node _T_1196 = or(_T_1195, _T_1167) node _T_1197 = or(_T_1196, _T_1168) node _T_1198 = or(_T_1197, _T_1169) node _T_1199 = or(_T_1198, _T_1170) node _T_1200 = or(_T_1199, _T_1171) node _T_1201 = or(_T_1200, _T_1172) node _T_1202 = or(_T_1201, _T_1173) node _T_1203 = or(_T_1202, _T_1174) node _T_1204 = or(_T_1203, _T_1175) node _T_1205 = or(_T_1204, _T_1176) node _T_1206 = or(_T_1205, _T_1177) node _T_1207 = or(_T_1206, _T_1178) node _T_1208 = or(_T_1207, _T_1179) node _T_1209 = or(_T_1208, _T_1180) node _T_1210 = or(_T_1209, _T_1181) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = and(_T_1142, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = or(UInt<1>(0h0), _T_1226) node _T_1228 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1229 = cvt(_T_1228) node _T_1230 = and(_T_1229, asSInt(UInt<13>(0h1000))) node _T_1231 = asSInt(_T_1230) node _T_1232 = eq(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = and(_T_1227, _T_1232) node _T_1234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1235 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1236 = and(_T_1234, _T_1235) node _T_1237 = or(UInt<1>(0h0), _T_1236) node _T_1238 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<14>(0h2000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<18>(0h2f000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h10000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<13>(0h1000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<27>(0h4000000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<13>(0h1000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = or(_T_1242, _T_1247) node _T_1269 = or(_T_1268, _T_1252) node _T_1270 = or(_T_1269, _T_1257) node _T_1271 = or(_T_1270, _T_1262) node _T_1272 = or(_T_1271, _T_1267) node _T_1273 = and(_T_1237, _T_1272) node _T_1274 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1275 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<17>(0h10000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = and(_T_1274, _T_1279) node _T_1281 = or(UInt<1>(0h0), _T_1233) node _T_1282 = or(_T_1281, _T_1273) node _T_1283 = or(_T_1282, _T_1280) node _T_1284 = and(_T_1223, _T_1283) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_26 node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(source_ok, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(is_aligned, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1294 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_29 node _T_1298 = eq(io.in.a.bits.mask, mask) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_30 node _T_1302 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1302 : node _T_1303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1307 = shr(io.in.a.bits.source, 2) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) node _T_1309 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1310 = and(_T_1308, _T_1309) node _T_1311 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1312 = and(_T_1310, _T_1311) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1313 = shr(io.in.a.bits.source, 2) node _T_1314 = eq(_T_1313, UInt<1>(0h1)) node _T_1315 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1318 = and(_T_1316, _T_1317) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1319 = shr(io.in.a.bits.source, 2) node _T_1320 = eq(_T_1319, UInt<2>(0h2)) node _T_1321 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1324 = and(_T_1322, _T_1323) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1325 = shr(io.in.a.bits.source, 2) node _T_1326 = eq(_T_1325, UInt<2>(0h3)) node _T_1327 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1332 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1333 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1334 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1335 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1336 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1337 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1338 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1339 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1340 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1341 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1342 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1343 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1344 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1352 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1353 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1354 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1356 = or(_T_1306, _T_1312) node _T_1357 = or(_T_1356, _T_1318) node _T_1358 = or(_T_1357, _T_1324) node _T_1359 = or(_T_1358, _T_1330) node _T_1360 = or(_T_1359, _T_1331) node _T_1361 = or(_T_1360, _T_1332) node _T_1362 = or(_T_1361, _T_1333) node _T_1363 = or(_T_1362, _T_1334) node _T_1364 = or(_T_1363, _T_1335) node _T_1365 = or(_T_1364, _T_1336) node _T_1366 = or(_T_1365, _T_1337) node _T_1367 = or(_T_1366, _T_1338) node _T_1368 = or(_T_1367, _T_1339) node _T_1369 = or(_T_1368, _T_1340) node _T_1370 = or(_T_1369, _T_1341) node _T_1371 = or(_T_1370, _T_1342) node _T_1372 = or(_T_1371, _T_1343) node _T_1373 = or(_T_1372, _T_1344) node _T_1374 = or(_T_1373, _T_1345) node _T_1375 = or(_T_1374, _T_1346) node _T_1376 = or(_T_1375, _T_1347) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1349) node _T_1379 = or(_T_1378, _T_1350) node _T_1380 = or(_T_1379, _T_1351) node _T_1381 = or(_T_1380, _T_1352) node _T_1382 = or(_T_1381, _T_1353) node _T_1383 = or(_T_1382, _T_1354) node _T_1384 = or(_T_1383, _T_1355) node _T_1385 = and(_T_1305, _T_1384) node _T_1386 = or(UInt<1>(0h0), _T_1385) node _T_1387 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1388 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1389 = and(_T_1387, _T_1388) node _T_1390 = or(UInt<1>(0h0), _T_1389) node _T_1391 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = and(_T_1390, _T_1395) node _T_1397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1398 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1399 = and(_T_1397, _T_1398) node _T_1400 = or(UInt<1>(0h0), _T_1399) node _T_1401 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1402 = cvt(_T_1401) node _T_1403 = and(_T_1402, asSInt(UInt<14>(0h2000))) node _T_1404 = asSInt(_T_1403) node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0))) node _T_1406 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1407 = cvt(_T_1406) node _T_1408 = and(_T_1407, asSInt(UInt<18>(0h2f000))) node _T_1409 = asSInt(_T_1408) node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0))) node _T_1411 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<17>(0h10000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<27>(0h4000000))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1427 = cvt(_T_1426) node _T_1428 = and(_T_1427, asSInt(UInt<13>(0h1000))) node _T_1429 = asSInt(_T_1428) node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0))) node _T_1431 = or(_T_1405, _T_1410) node _T_1432 = or(_T_1431, _T_1415) node _T_1433 = or(_T_1432, _T_1420) node _T_1434 = or(_T_1433, _T_1425) node _T_1435 = or(_T_1434, _T_1430) node _T_1436 = and(_T_1400, _T_1435) node _T_1437 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1438 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1439 = cvt(_T_1438) node _T_1440 = and(_T_1439, asSInt(UInt<17>(0h10000))) node _T_1441 = asSInt(_T_1440) node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0))) node _T_1443 = and(_T_1437, _T_1442) node _T_1444 = or(UInt<1>(0h0), _T_1396) node _T_1445 = or(_T_1444, _T_1436) node _T_1446 = or(_T_1445, _T_1443) node _T_1447 = and(_T_1386, _T_1446) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_31 node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(source_ok, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(is_aligned, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1458 = asUInt(reset) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) when _T_1459 : node _T_1460 = eq(_T_1457, UInt<1>(0h0)) when _T_1460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1457, UInt<1>(0h1), "") : assert_34 node _T_1461 = not(mask) node _T_1462 = and(io.in.a.bits.mask, _T_1461) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_35 node _T_1467 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1467 : node _T_1468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1472 = shr(io.in.a.bits.source, 2) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) node _T_1474 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1475 = and(_T_1473, _T_1474) node _T_1476 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1477 = and(_T_1475, _T_1476) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1478 = shr(io.in.a.bits.source, 2) node _T_1479 = eq(_T_1478, UInt<1>(0h1)) node _T_1480 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1483 = and(_T_1481, _T_1482) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1484 = shr(io.in.a.bits.source, 2) node _T_1485 = eq(_T_1484, UInt<2>(0h2)) node _T_1486 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1489 = and(_T_1487, _T_1488) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1490 = shr(io.in.a.bits.source, 2) node _T_1491 = eq(_T_1490, UInt<2>(0h3)) node _T_1492 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1495 = and(_T_1493, _T_1494) node _T_1496 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1497 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1498 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1499 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1500 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1501 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1502 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1520 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1521 = or(_T_1471, _T_1477) node _T_1522 = or(_T_1521, _T_1483) node _T_1523 = or(_T_1522, _T_1489) node _T_1524 = or(_T_1523, _T_1495) node _T_1525 = or(_T_1524, _T_1496) node _T_1526 = or(_T_1525, _T_1497) node _T_1527 = or(_T_1526, _T_1498) node _T_1528 = or(_T_1527, _T_1499) node _T_1529 = or(_T_1528, _T_1500) node _T_1530 = or(_T_1529, _T_1501) node _T_1531 = or(_T_1530, _T_1502) node _T_1532 = or(_T_1531, _T_1503) node _T_1533 = or(_T_1532, _T_1504) node _T_1534 = or(_T_1533, _T_1505) node _T_1535 = or(_T_1534, _T_1506) node _T_1536 = or(_T_1535, _T_1507) node _T_1537 = or(_T_1536, _T_1508) node _T_1538 = or(_T_1537, _T_1509) node _T_1539 = or(_T_1538, _T_1510) node _T_1540 = or(_T_1539, _T_1511) node _T_1541 = or(_T_1540, _T_1512) node _T_1542 = or(_T_1541, _T_1513) node _T_1543 = or(_T_1542, _T_1514) node _T_1544 = or(_T_1543, _T_1515) node _T_1545 = or(_T_1544, _T_1516) node _T_1546 = or(_T_1545, _T_1517) node _T_1547 = or(_T_1546, _T_1518) node _T_1548 = or(_T_1547, _T_1519) node _T_1549 = or(_T_1548, _T_1520) node _T_1550 = and(_T_1470, _T_1549) node _T_1551 = or(UInt<1>(0h0), _T_1550) node _T_1552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1553 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1554 = and(_T_1552, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1557 = cvt(_T_1556) node _T_1558 = and(_T_1557, asSInt(UInt<15>(0h5000))) node _T_1559 = asSInt(_T_1558) node _T_1560 = eq(_T_1559, asSInt(UInt<1>(0h0))) node _T_1561 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1562 = cvt(_T_1561) node _T_1563 = and(_T_1562, asSInt(UInt<13>(0h1000))) node _T_1564 = asSInt(_T_1563) node _T_1565 = eq(_T_1564, asSInt(UInt<1>(0h0))) node _T_1566 = or(_T_1560, _T_1565) node _T_1567 = and(_T_1555, _T_1566) node _T_1568 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1569 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<17>(0h10000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1580 = cvt(_T_1579) node _T_1581 = and(_T_1580, asSInt(UInt<18>(0h2f000))) node _T_1582 = asSInt(_T_1581) node _T_1583 = eq(_T_1582, asSInt(UInt<1>(0h0))) node _T_1584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1585 = cvt(_T_1584) node _T_1586 = and(_T_1585, asSInt(UInt<17>(0h10000))) node _T_1587 = asSInt(_T_1586) node _T_1588 = eq(_T_1587, asSInt(UInt<1>(0h0))) node _T_1589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1590 = cvt(_T_1589) node _T_1591 = and(_T_1590, asSInt(UInt<13>(0h1000))) node _T_1592 = asSInt(_T_1591) node _T_1593 = eq(_T_1592, asSInt(UInt<1>(0h0))) node _T_1594 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1595 = cvt(_T_1594) node _T_1596 = and(_T_1595, asSInt(UInt<27>(0h4000000))) node _T_1597 = asSInt(_T_1596) node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0))) node _T_1599 = or(_T_1573, _T_1578) node _T_1600 = or(_T_1599, _T_1583) node _T_1601 = or(_T_1600, _T_1588) node _T_1602 = or(_T_1601, _T_1593) node _T_1603 = or(_T_1602, _T_1598) node _T_1604 = and(_T_1568, _T_1603) node _T_1605 = or(UInt<1>(0h0), _T_1567) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = and(_T_1551, _T_1606) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_36 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(source_ok, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1617 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_39 node _T_1621 = eq(io.in.a.bits.mask, mask) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_40 node _T_1625 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1627 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1630 = shr(io.in.a.bits.source, 2) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) node _T_1632 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1633 = and(_T_1631, _T_1632) node _T_1634 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1635 = and(_T_1633, _T_1634) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1636 = shr(io.in.a.bits.source, 2) node _T_1637 = eq(_T_1636, UInt<1>(0h1)) node _T_1638 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1639 = and(_T_1637, _T_1638) node _T_1640 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1641 = and(_T_1639, _T_1640) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1642 = shr(io.in.a.bits.source, 2) node _T_1643 = eq(_T_1642, UInt<2>(0h2)) node _T_1644 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1645 = and(_T_1643, _T_1644) node _T_1646 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1647 = and(_T_1645, _T_1646) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1648 = shr(io.in.a.bits.source, 2) node _T_1649 = eq(_T_1648, UInt<2>(0h3)) node _T_1650 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1651 = and(_T_1649, _T_1650) node _T_1652 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1653 = and(_T_1651, _T_1652) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1662 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1663 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1664 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1665 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1666 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1667 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1668 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1669 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1670 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1671 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1672 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1673 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1674 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1675 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1676 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1677 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1678 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1679 = or(_T_1629, _T_1635) node _T_1680 = or(_T_1679, _T_1641) node _T_1681 = or(_T_1680, _T_1647) node _T_1682 = or(_T_1681, _T_1653) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1655) node _T_1685 = or(_T_1684, _T_1656) node _T_1686 = or(_T_1685, _T_1657) node _T_1687 = or(_T_1686, _T_1658) node _T_1688 = or(_T_1687, _T_1659) node _T_1689 = or(_T_1688, _T_1660) node _T_1690 = or(_T_1689, _T_1661) node _T_1691 = or(_T_1690, _T_1662) node _T_1692 = or(_T_1691, _T_1663) node _T_1693 = or(_T_1692, _T_1664) node _T_1694 = or(_T_1693, _T_1665) node _T_1695 = or(_T_1694, _T_1666) node _T_1696 = or(_T_1695, _T_1667) node _T_1697 = or(_T_1696, _T_1668) node _T_1698 = or(_T_1697, _T_1669) node _T_1699 = or(_T_1698, _T_1670) node _T_1700 = or(_T_1699, _T_1671) node _T_1701 = or(_T_1700, _T_1672) node _T_1702 = or(_T_1701, _T_1673) node _T_1703 = or(_T_1702, _T_1674) node _T_1704 = or(_T_1703, _T_1675) node _T_1705 = or(_T_1704, _T_1676) node _T_1706 = or(_T_1705, _T_1677) node _T_1707 = or(_T_1706, _T_1678) node _T_1708 = and(_T_1628, _T_1707) node _T_1709 = or(UInt<1>(0h0), _T_1708) node _T_1710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1711 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1712 = and(_T_1710, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<15>(0h5000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<13>(0h1000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = or(_T_1718, _T_1723) node _T_1725 = and(_T_1713, _T_1724) node _T_1726 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1727 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<13>(0h1000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<17>(0h10000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<18>(0h2f000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<17>(0h10000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<13>(0h1000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = or(_T_1731, _T_1736) node _T_1758 = or(_T_1757, _T_1741) node _T_1759 = or(_T_1758, _T_1746) node _T_1760 = or(_T_1759, _T_1751) node _T_1761 = or(_T_1760, _T_1756) node _T_1762 = and(_T_1726, _T_1761) node _T_1763 = or(UInt<1>(0h0), _T_1725) node _T_1764 = or(_T_1763, _T_1762) node _T_1765 = and(_T_1709, _T_1764) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_41 node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(source_ok, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(is_aligned, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1775 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_44 node _T_1779 = eq(io.in.a.bits.mask, mask) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_45 node _T_1783 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1783 : node _T_1784 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1785 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1788 = shr(io.in.a.bits.source, 2) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1791 = and(_T_1789, _T_1790) node _T_1792 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1793 = and(_T_1791, _T_1792) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1794 = shr(io.in.a.bits.source, 2) node _T_1795 = eq(_T_1794, UInt<1>(0h1)) node _T_1796 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1797 = and(_T_1795, _T_1796) node _T_1798 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1799 = and(_T_1797, _T_1798) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1800 = shr(io.in.a.bits.source, 2) node _T_1801 = eq(_T_1800, UInt<2>(0h2)) node _T_1802 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1803 = and(_T_1801, _T_1802) node _T_1804 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1805 = and(_T_1803, _T_1804) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1806 = shr(io.in.a.bits.source, 2) node _T_1807 = eq(_T_1806, UInt<2>(0h3)) node _T_1808 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1809 = and(_T_1807, _T_1808) node _T_1810 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1813 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1814 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1815 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1816 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1817 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1818 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1819 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1820 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1821 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1822 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1823 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1824 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1825 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1826 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1836 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1837 = or(_T_1787, _T_1793) node _T_1838 = or(_T_1837, _T_1799) node _T_1839 = or(_T_1838, _T_1805) node _T_1840 = or(_T_1839, _T_1811) node _T_1841 = or(_T_1840, _T_1812) node _T_1842 = or(_T_1841, _T_1813) node _T_1843 = or(_T_1842, _T_1814) node _T_1844 = or(_T_1843, _T_1815) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1817) node _T_1847 = or(_T_1846, _T_1818) node _T_1848 = or(_T_1847, _T_1819) node _T_1849 = or(_T_1848, _T_1820) node _T_1850 = or(_T_1849, _T_1821) node _T_1851 = or(_T_1850, _T_1822) node _T_1852 = or(_T_1851, _T_1823) node _T_1853 = or(_T_1852, _T_1824) node _T_1854 = or(_T_1853, _T_1825) node _T_1855 = or(_T_1854, _T_1826) node _T_1856 = or(_T_1855, _T_1827) node _T_1857 = or(_T_1856, _T_1828) node _T_1858 = or(_T_1857, _T_1829) node _T_1859 = or(_T_1858, _T_1830) node _T_1860 = or(_T_1859, _T_1831) node _T_1861 = or(_T_1860, _T_1832) node _T_1862 = or(_T_1861, _T_1833) node _T_1863 = or(_T_1862, _T_1834) node _T_1864 = or(_T_1863, _T_1835) node _T_1865 = or(_T_1864, _T_1836) node _T_1866 = and(_T_1786, _T_1865) node _T_1867 = or(UInt<1>(0h0), _T_1866) node _T_1868 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1869 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1870 = and(_T_1868, _T_1869) node _T_1871 = or(UInt<1>(0h0), _T_1870) node _T_1872 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1873 = cvt(_T_1872) node _T_1874 = and(_T_1873, asSInt(UInt<13>(0h1000))) node _T_1875 = asSInt(_T_1874) node _T_1876 = eq(_T_1875, asSInt(UInt<1>(0h0))) node _T_1877 = and(_T_1871, _T_1876) node _T_1878 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1879 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1880 = cvt(_T_1879) node _T_1881 = and(_T_1880, asSInt(UInt<14>(0h2000))) node _T_1882 = asSInt(_T_1881) node _T_1883 = eq(_T_1882, asSInt(UInt<1>(0h0))) node _T_1884 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h10000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<18>(0h2f000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<13>(0h1000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<27>(0h4000000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = or(_T_1883, _T_1888) node _T_1915 = or(_T_1914, _T_1893) node _T_1916 = or(_T_1915, _T_1898) node _T_1917 = or(_T_1916, _T_1903) node _T_1918 = or(_T_1917, _T_1908) node _T_1919 = or(_T_1918, _T_1913) node _T_1920 = and(_T_1878, _T_1919) node _T_1921 = or(UInt<1>(0h0), _T_1877) node _T_1922 = or(_T_1921, _T_1920) node _T_1923 = and(_T_1867, _T_1922) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_46 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(source_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1930 = asUInt(reset) node _T_1931 = eq(_T_1930, UInt<1>(0h0)) when _T_1931 : node _T_1932 = eq(is_aligned, UInt<1>(0h0)) when _T_1932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1933 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1934 = asUInt(reset) node _T_1935 = eq(_T_1934, UInt<1>(0h0)) when _T_1935 : node _T_1936 = eq(_T_1933, UInt<1>(0h0)) when _T_1936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1933, UInt<1>(0h1), "") : assert_49 node _T_1937 = eq(io.in.a.bits.mask, mask) node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(_T_1937, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1937, UInt<1>(0h1), "") : assert_50 node _T_1941 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1945 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1946 = asUInt(reset) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) when _T_1947 : node _T_1948 = eq(_T_1945, UInt<1>(0h0)) when _T_1948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1945, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1949 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1949 : node _T_1950 = asUInt(reset) node _T_1951 = eq(_T_1950, UInt<1>(0h0)) when _T_1951 : node _T_1952 = eq(source_ok_1, UInt<1>(0h0)) when _T_1952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1953 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(_T_1953, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1953, UInt<1>(0h1), "") : assert_54 node _T_1957 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_55 node _T_1961 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_56 node _T_1965 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_57 node _T_1969 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(sink_ok, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1976 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_60 node _T_1980 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_61 node _T_1984 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1985 = asUInt(reset) node _T_1986 = eq(_T_1985, UInt<1>(0h0)) when _T_1986 : node _T_1987 = eq(_T_1984, UInt<1>(0h0)) when _T_1987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1984, UInt<1>(0h1), "") : assert_62 node _T_1988 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1989 = asUInt(reset) node _T_1990 = eq(_T_1989, UInt<1>(0h0)) when _T_1990 : node _T_1991 = eq(_T_1988, UInt<1>(0h0)) when _T_1991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1988, UInt<1>(0h1), "") : assert_63 node _T_1992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1993 = or(UInt<1>(0h1), _T_1992) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_64 node _T_1997 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1997 : node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(source_ok_1, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(sink_ok, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2004 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_67 node _T_2008 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_68 node _T_2012 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_69 node _T_2016 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2017 = or(_T_2016, io.in.d.bits.corrupt) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_70 node _T_2021 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2022 = or(UInt<1>(0h1), _T_2021) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_71 node _T_2026 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2026 : node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(source_ok_1, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2030 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_73 node _T_2034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_74 node _T_2038 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2039 = or(UInt<1>(0h1), _T_2038) node _T_2040 = asUInt(reset) node _T_2041 = eq(_T_2040, UInt<1>(0h0)) when _T_2041 : node _T_2042 = eq(_T_2039, UInt<1>(0h0)) when _T_2042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2039, UInt<1>(0h1), "") : assert_75 node _T_2043 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2043 : node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(source_ok_1, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2047 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2048 = asUInt(reset) node _T_2049 = eq(_T_2048, UInt<1>(0h0)) when _T_2049 : node _T_2050 = eq(_T_2047, UInt<1>(0h0)) when _T_2050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2047, UInt<1>(0h1), "") : assert_77 node _T_2051 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2052 = or(_T_2051, io.in.d.bits.corrupt) node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(_T_2052, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2052, UInt<1>(0h1), "") : assert_78 node _T_2056 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2057 = or(UInt<1>(0h1), _T_2056) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_79 node _T_2061 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2061 : node _T_2062 = asUInt(reset) node _T_2063 = eq(_T_2062, UInt<1>(0h0)) when _T_2063 : node _T_2064 = eq(source_ok_1, UInt<1>(0h0)) when _T_2064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2065 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_81 node _T_2069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_82 node _T_2073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2074 = or(UInt<1>(0h1), _T_2073) node _T_2075 = asUInt(reset) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) when _T_2076 : node _T_2077 = eq(_T_2074, UInt<1>(0h0)) when _T_2077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2074, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2079 = asUInt(reset) node _T_2080 = eq(_T_2079, UInt<1>(0h0)) when _T_2080 : node _T_2081 = eq(_T_2078, UInt<1>(0h0)) when _T_2081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2078, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2082 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2083 = asUInt(reset) node _T_2084 = eq(_T_2083, UInt<1>(0h0)) when _T_2084 : node _T_2085 = eq(_T_2082, UInt<1>(0h0)) when _T_2085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2082, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2086 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2087 = asUInt(reset) node _T_2088 = eq(_T_2087, UInt<1>(0h0)) when _T_2088 : node _T_2089 = eq(_T_2086, UInt<1>(0h0)) when _T_2089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2086, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2090 = eq(a_first, UInt<1>(0h0)) node _T_2091 = and(io.in.a.valid, _T_2090) when _T_2091 : node _T_2092 = eq(io.in.a.bits.opcode, opcode) node _T_2093 = asUInt(reset) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) when _T_2094 : node _T_2095 = eq(_T_2092, UInt<1>(0h0)) when _T_2095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2092, UInt<1>(0h1), "") : assert_87 node _T_2096 = eq(io.in.a.bits.param, param) node _T_2097 = asUInt(reset) node _T_2098 = eq(_T_2097, UInt<1>(0h0)) when _T_2098 : node _T_2099 = eq(_T_2096, UInt<1>(0h0)) when _T_2099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2096, UInt<1>(0h1), "") : assert_88 node _T_2100 = eq(io.in.a.bits.size, size) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_89 node _T_2104 = eq(io.in.a.bits.source, source) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_90 node _T_2108 = eq(io.in.a.bits.address, address) node _T_2109 = asUInt(reset) node _T_2110 = eq(_T_2109, UInt<1>(0h0)) when _T_2110 : node _T_2111 = eq(_T_2108, UInt<1>(0h0)) when _T_2111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2108, UInt<1>(0h1), "") : assert_91 node _T_2112 = and(io.in.a.ready, io.in.a.valid) node _T_2113 = and(_T_2112, a_first) when _T_2113 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2114 = eq(d_first, UInt<1>(0h0)) node _T_2115 = and(io.in.d.valid, _T_2114) when _T_2115 : node _T_2116 = eq(io.in.d.bits.opcode, opcode_1) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_92 node _T_2120 = eq(io.in.d.bits.param, param_1) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_93 node _T_2124 = eq(io.in.d.bits.size, size_1) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_94 node _T_2128 = eq(io.in.d.bits.source, source_1) node _T_2129 = asUInt(reset) node _T_2130 = eq(_T_2129, UInt<1>(0h0)) when _T_2130 : node _T_2131 = eq(_T_2128, UInt<1>(0h0)) when _T_2131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2128, UInt<1>(0h1), "") : assert_95 node _T_2132 = eq(io.in.d.bits.sink, sink) node _T_2133 = asUInt(reset) node _T_2134 = eq(_T_2133, UInt<1>(0h0)) when _T_2134 : node _T_2135 = eq(_T_2132, UInt<1>(0h0)) when _T_2135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2132, UInt<1>(0h1), "") : assert_96 node _T_2136 = eq(io.in.d.bits.denied, denied) node _T_2137 = asUInt(reset) node _T_2138 = eq(_T_2137, UInt<1>(0h0)) when _T_2138 : node _T_2139 = eq(_T_2136, UInt<1>(0h0)) when _T_2139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2136, UInt<1>(0h1), "") : assert_97 node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = and(_T_2140, d_first) when _T_2141 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2142 = and(io.in.a.valid, a_first_1) node _T_2143 = and(_T_2142, UInt<1>(0h1)) when _T_2143 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2144 = and(io.in.a.ready, io.in.a.valid) node _T_2145 = and(_T_2144, a_first_1) node _T_2146 = and(_T_2145, UInt<1>(0h1)) when _T_2146 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2147 = dshr(inflight, io.in.a.bits.source) node _T_2148 = bits(_T_2147, 0, 0) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = asUInt(reset) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) when _T_2151 : node _T_2152 = eq(_T_2149, UInt<1>(0h0)) when _T_2152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2149, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2153 = and(io.in.d.valid, d_first_1) node _T_2154 = and(_T_2153, UInt<1>(0h1)) node _T_2155 = eq(d_release_ack, UInt<1>(0h0)) node _T_2156 = and(_T_2154, _T_2155) when _T_2156 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2157 = and(io.in.d.ready, io.in.d.valid) node _T_2158 = and(_T_2157, d_first_1) node _T_2159 = and(_T_2158, UInt<1>(0h1)) node _T_2160 = eq(d_release_ack, UInt<1>(0h0)) node _T_2161 = and(_T_2159, _T_2160) when _T_2161 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2162 = and(io.in.d.valid, d_first_1) node _T_2163 = and(_T_2162, UInt<1>(0h1)) node _T_2164 = eq(d_release_ack, UInt<1>(0h0)) node _T_2165 = and(_T_2163, _T_2164) when _T_2165 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2166 = dshr(inflight, io.in.d.bits.source) node _T_2167 = bits(_T_2166, 0, 0) node _T_2168 = or(_T_2167, same_cycle_resp) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2172 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2173 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2174 = or(_T_2172, _T_2173) node _T_2175 = asUInt(reset) node _T_2176 = eq(_T_2175, UInt<1>(0h0)) when _T_2176 : node _T_2177 = eq(_T_2174, UInt<1>(0h0)) when _T_2177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2174, UInt<1>(0h1), "") : assert_100 node _T_2178 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2179 = asUInt(reset) node _T_2180 = eq(_T_2179, UInt<1>(0h0)) when _T_2180 : node _T_2181 = eq(_T_2178, UInt<1>(0h0)) when _T_2181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2178, UInt<1>(0h1), "") : assert_101 else : node _T_2182 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2183 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2184 = or(_T_2182, _T_2183) node _T_2185 = asUInt(reset) node _T_2186 = eq(_T_2185, UInt<1>(0h0)) when _T_2186 : node _T_2187 = eq(_T_2184, UInt<1>(0h0)) when _T_2187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2184, UInt<1>(0h1), "") : assert_102 node _T_2188 = eq(io.in.d.bits.size, a_size_lookup) node _T_2189 = asUInt(reset) node _T_2190 = eq(_T_2189, UInt<1>(0h0)) when _T_2190 : node _T_2191 = eq(_T_2188, UInt<1>(0h0)) when _T_2191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2188, UInt<1>(0h1), "") : assert_103 node _T_2192 = and(io.in.d.valid, d_first_1) node _T_2193 = and(_T_2192, a_first_1) node _T_2194 = and(_T_2193, io.in.a.valid) node _T_2195 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2196 = and(_T_2194, _T_2195) node _T_2197 = eq(d_release_ack, UInt<1>(0h0)) node _T_2198 = and(_T_2196, _T_2197) when _T_2198 : node _T_2199 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2200 = or(_T_2199, io.in.a.ready) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_72 node _T_2204 = orr(inflight) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) node _T_2206 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2207 = or(_T_2205, _T_2206) node _T_2208 = lt(watchdog, plusarg_reader.out) node _T_2209 = or(_T_2207, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2213 = and(io.in.a.ready, io.in.a.valid) node _T_2214 = and(io.in.d.ready, io.in.d.valid) node _T_2215 = or(_T_2213, _T_2214) when _T_2215 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2216 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2217 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2218 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2219 = and(_T_2217, _T_2218) node _T_2220 = and(_T_2216, _T_2219) when _T_2220 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2221 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2222 = and(_T_2221, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2223 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2224 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2225 = and(_T_2223, _T_2224) node _T_2226 = and(_T_2222, _T_2225) when _T_2226 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2227 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2228 = bits(_T_2227, 0, 0) node _T_2229 = eq(_T_2228, UInt<1>(0h0)) node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(_T_2229, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2229, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2233 = and(io.in.d.valid, d_first_2) node _T_2234 = and(_T_2233, UInt<1>(0h1)) node _T_2235 = and(_T_2234, d_release_ack_1) when _T_2235 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2236 = and(io.in.d.ready, io.in.d.valid) node _T_2237 = and(_T_2236, d_first_2) node _T_2238 = and(_T_2237, UInt<1>(0h1)) node _T_2239 = and(_T_2238, d_release_ack_1) when _T_2239 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2240 = and(io.in.d.valid, d_first_2) node _T_2241 = and(_T_2240, UInt<1>(0h1)) node _T_2242 = and(_T_2241, d_release_ack_1) when _T_2242 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2243 = dshr(inflight_1, io.in.d.bits.source) node _T_2244 = bits(_T_2243, 0, 0) node _T_2245 = or(_T_2244, same_cycle_resp_1) node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : node _T_2248 = eq(_T_2245, UInt<1>(0h0)) when _T_2248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2245, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2249 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : node _T_2252 = eq(_T_2249, UInt<1>(0h0)) when _T_2252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2249, UInt<1>(0h1), "") : assert_108 else : node _T_2253 = eq(io.in.d.bits.size, c_size_lookup) node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : node _T_2256 = eq(_T_2253, UInt<1>(0h0)) when _T_2256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2253, UInt<1>(0h1), "") : assert_109 node _T_2257 = and(io.in.d.valid, d_first_2) node _T_2258 = and(_T_2257, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2259 = and(_T_2258, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2260 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2261 = and(_T_2259, _T_2260) node _T_2262 = and(_T_2261, d_release_ack_1) node _T_2263 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2264 = and(_T_2262, _T_2263) when _T_2264 : node _T_2265 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2266 = or(_T_2265, _WIRE_27.ready) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_73 node _T_2270 = orr(inflight_1) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) node _T_2272 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2273 = or(_T_2271, _T_2272) node _T_2274 = lt(watchdog_1, plusarg_reader_1.out) node _T_2275 = or(_T_2273, _T_2274) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2279 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2280 = and(io.in.d.ready, io.in.d.valid) node _T_2281 = or(_T_2279, _T_2280) when _T_2281 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_2 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d64s6k5z4c_2 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<4>(0hf)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<4>(0he)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<4>(0hd)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<4>(0hc)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_5 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_5 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_5, 1, 0) node _io_flit_bits_egress_id_requestOH_T_25 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_26 = eq(_io_flit_bits_egress_id_requestOH_T_25, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_27 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_5) node _io_flit_bits_egress_id_requestOH_T_28 = and(_io_flit_bits_egress_id_requestOH_T_26, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_5, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_5 = and(_io_flit_bits_egress_id_requestOH_T_28, _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_6 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_6 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_6, 1, 0) node _io_flit_bits_egress_id_requestOH_T_30 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_31 = eq(_io_flit_bits_egress_id_requestOH_T_30, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_32 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_6) node _io_flit_bits_egress_id_requestOH_T_33 = and(_io_flit_bits_egress_id_requestOH_T_31, _io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_6, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_6 = and(_io_flit_bits_egress_id_requestOH_T_33, _io_flit_bits_egress_id_requestOH_T_34) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_7 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_7 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_7, 1, 0) node _io_flit_bits_egress_id_requestOH_T_35 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_36 = eq(_io_flit_bits_egress_id_requestOH_T_35, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_37 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_7) node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_36, _io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_7, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_7 = and(_io_flit_bits_egress_id_requestOH_T_38, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_8 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_8 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_8, 1, 0) node _io_flit_bits_egress_id_requestOH_T_40 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_41 = eq(_io_flit_bits_egress_id_requestOH_T_40, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_42 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_8) node _io_flit_bits_egress_id_requestOH_T_43 = and(_io_flit_bits_egress_id_requestOH_T_41, _io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_8, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_8 = and(_io_flit_bits_egress_id_requestOH_T_43, _io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<4>(0hd), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<4>(0hf), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_8 = mux(io_flit_bits_egress_id_requestOH_8, UInt<5>(0h11), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_9 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_10 = or(_io_flit_bits_egress_id_T_9, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_11 = or(_io_flit_bits_egress_id_T_10, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_12 = or(_io_flit_bits_egress_id_T_11, _io_flit_bits_egress_id_T_4) node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T_12, _io_flit_bits_egress_id_T_5) node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_6) node _io_flit_bits_egress_id_T_15 = or(_io_flit_bits_egress_id_T_14, _io_flit_bits_egress_id_T_7) node _io_flit_bits_egress_id_T_16 = or(_io_flit_bits_egress_id_T_15, _io_flit_bits_egress_id_T_8) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_16 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<5>(0h10)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T	module TLDToNoC_2( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 \| tail_beats1 == 3'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_270 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_270( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module BankBinder : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_39 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn	module BankBinder( // @[BankBinder.scala:61:9] input clock, // @[BankBinder.scala:61:9] input reset, // @[BankBinder.scala:61:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BankBinder.scala:61:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BankBinder.scala:61:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BankBinder.scala:61:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BankBinder.scala:61:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BankBinder.scala:61:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BankBinder.scala:61:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BankBinder.scala:61:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BankBinder.scala:61:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BankBinder.scala:61:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BankBinder.scala:61:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[BankBinder.scala:61:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[BankBinder.scala:61:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[BankBinder.scala:61:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[BankBinder.scala:61:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[BankBinder.scala:61:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[BankBinder.scala:61:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[BankBinder.scala:61:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[BankBinder.scala:61:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[BankBinder.scala:61:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[BankBinder.scala:61:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BankBinder.scala:61:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BankBinder.scala:61:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BankBinder.scala:61:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BankBinder.scala:61:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BankBinder.scala:61:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BankBinder.scala:61:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BankBinder.scala:61:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BankBinder.scala:61:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[BankBinder.scala:61:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[BankBinder.scala:61:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[BankBinder.scala:61:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[BankBinder.scala:61:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[BankBinder.scala:61:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[BankBinder.scala:61:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[BankBinder.scala:61:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[BankBinder.scala:61:9] wire auto_in_a_ready_0; // @[BankBinder.scala:61:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9] wire [1:0] auto_in_d_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] auto_in_d_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] auto_in_d_bits_source_0; // @[BankBinder.scala:61:9] wire auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9] wire auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9] wire [63:0] auto_in_d_bits_data_0; // @[BankBinder.scala:61:9] wire auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9] wire auto_in_d_valid_0; // @[BankBinder.scala:61:9] wire [2:0] auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9] wire [2:0] auto_out_a_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] auto_out_a_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] auto_out_a_bits_source_0; // @[BankBinder.scala:61:9] wire [31:0] auto_out_a_bits_address_0; // @[BankBinder.scala:61:9] wire [7:0] auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9] wire [63:0] auto_out_a_bits_data_0; // @[BankBinder.scala:61:9] wire auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9] wire auto_out_a_valid_0; // @[BankBinder.scala:61:9] wire auto_out_d_ready_0; // @[BankBinder.scala:61:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BankBinder.scala:61:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BankBinder.scala:61:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BankBinder.scala:61:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BankBinder.scala:61:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BankBinder.scala:61:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BankBinder.scala:61:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BankBinder.scala:61:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BankBinder.scala:61:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BankBinder.scala:61:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BankBinder.scala:61:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[BankBinder.scala:61:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BankBinder.scala:61:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[BankBinder.scala:61:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[BankBinder.scala:61:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[BankBinder.scala:61:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[BankBinder.scala:61:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[BankBinder.scala:61:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[BankBinder.scala:61:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[BankBinder.scala:61:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] TLMonitor_39 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BankBinder.scala:61:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[BankBinder.scala:61:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_6 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_6( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64_mulAddZ31 : input clock : Clock input reset : Reset output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} inst divSqrtRecF64ToRaw of DivSqrtRecF64ToRaw_mulAddZ31 connect divSqrtRecF64ToRaw.clock, clock connect divSqrtRecF64ToRaw.reset, reset connect io.inReady_div, divSqrtRecF64ToRaw.io.inReady_div connect io.inReady_sqrt, divSqrtRecF64ToRaw.io.inReady_sqrt connect divSqrtRecF64ToRaw.io.inValid, io.inValid connect divSqrtRecF64ToRaw.io.sqrtOp, io.sqrtOp connect divSqrtRecF64ToRaw.io.a, io.a connect divSqrtRecF64ToRaw.io.b, io.b connect divSqrtRecF64ToRaw.io.roundingMode, io.roundingMode connect io.usingMulAdd, divSqrtRecF64ToRaw.io.usingMulAdd connect io.latchMulAddA_0, divSqrtRecF64ToRaw.io.latchMulAddA_0 connect io.mulAddA_0, divSqrtRecF64ToRaw.io.mulAddA_0 connect io.latchMulAddB_0, divSqrtRecF64ToRaw.io.latchMulAddB_0 connect io.mulAddB_0, divSqrtRecF64ToRaw.io.mulAddB_0 connect io.mulAddC_2, divSqrtRecF64ToRaw.io.mulAddC_2 connect divSqrtRecF64ToRaw.io.mulAddResult_3, io.mulAddResult_3 connect io.outValid_div, divSqrtRecF64ToRaw.io.rawOutValid_div connect io.outValid_sqrt, divSqrtRecF64ToRaw.io.rawOutValid_sqrt inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_5 connect roundRawFNToRecFN.io.invalidExc, divSqrtRecF64ToRaw.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecF64ToRaw.io.infiniteExc connect roundRawFNToRecFN.io.in.sig, divSqrtRecF64ToRaw.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, divSqrtRecF64ToRaw.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, divSqrtRecF64ToRaw.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, divSqrtRecF64ToRaw.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, divSqrtRecF64ToRaw.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecF64ToRaw.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, divSqrtRecF64ToRaw.io.roundingModeOut connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module DivSqrtRecF64_mulAddZ31( // @[DivSqrtRecF64_mulAddZ31.scala:719:7] input clock, // @[DivSqrtRecF64_mulAddZ31.scala:719:7] input reset, // @[DivSqrtRecF64_mulAddZ31.scala:719:7] output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_outValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_outValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [64:0] io_out, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [4:0] io_exceptionFlags // @[DivSqrtRecF64_mulAddZ31.scala:721:16] ); wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_invalidExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_infiniteExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isNaN; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isInf; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isZero; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_sign; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_detectTininess = 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7, :721:16, :775:15] wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] DivSqrtRecF64ToRaw_mulAddZ31 divSqrtRecF64ToRaw ( // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .clock (clock), .reset (reset), .io_inReady_div (io_inReady_div_0), .io_inReady_sqrt (io_inReady_sqrt_0), .io_inValid (io_inValid_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_a (io_a_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_b (io_b_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_usingMulAdd (io_usingMulAdd_0), .io_latchMulAddA_0 (io_latchMulAddA_0_0), .io_mulAddA_0 (io_mulAddA_0_0), .io_latchMulAddB_0 (io_latchMulAddB_0_0), .io_mulAddB_0 (io_mulAddB_0_0), .io_mulAddC_2 (io_mulAddC_2_0), .io_mulAddResult_3 (io_mulAddResult_3_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_rawOutValid_div (io_outValid_div_0), .io_rawOutValid_sqrt (io_outValid_sqrt_0), .io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut), .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), .io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), .io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), .io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), .io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), .io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), .io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig) ); // @[DivSqrtRecF64_mulAddZ31.scala:751:36] RoundRawFNToRecFN_e11_s53_5 roundRawFNToRecFN ( // @[DivSqrtRecF64_mulAddZ31.scala:775:15] .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[DivSqrtRecF64_mulAddZ31.scala:775:15] assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_out = io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<14>(0h2000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<18>(0h2f000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<27>(0h4000000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<19>(0h40000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = or(_T_323, _T_328) node _T_365 = or(_T_364, _T_333) node _T_366 = or(_T_365, _T_338) node _T_367 = or(_T_366, _T_343) node _T_368 = or(_T_367, _T_348) node _T_369 = or(_T_368, _T_353) node _T_370 = or(_T_369, _T_358) node _T_371 = or(_T_370, _T_363) node _T_372 = and(_T_318, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_T_317, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_374, UInt<1>(0h1), "") : assert_2 node _T_378 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<7>(0h40)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_24) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<7>(0h41)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_25) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_391 = shr(io.in.a.bits.source, 2) node _T_392 = eq(_T_391, UInt<7>(0h42)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_26) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_397 = shr(io.in.a.bits.source, 2) node _T_398 = eq(_T_397, UInt<7>(0h43)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_27) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_404 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_405 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<1>(0h0)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_28) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<1>(0h1)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_29) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_418 = shr(io.in.a.bits.source, 5) node _T_419 = eq(_T_418, UInt<2>(0h2)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_30) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_424 = shr(io.in.a.bits.source, 5) node _T_425 = eq(_T_424, UInt<2>(0h3)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_31) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<3>(0h4)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_32) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_436 = shr(io.in.a.bits.source, 5) node _T_437 = eq(_T_436, UInt<3>(0h5)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_33) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_442 = shr(io.in.a.bits.source, 5) node _T_443 = eq(_T_442, UInt<3>(0h6)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_34) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h7)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_35) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_378 connect _WIRE[1], _T_384 connect _WIRE[2], _T_390 connect _WIRE[3], _T_396 connect _WIRE[4], _T_402 connect _WIRE[5], _T_403 connect _WIRE[6], _T_404 connect _WIRE[7], _T_405 connect _WIRE[8], _T_411 connect _WIRE[9], _T_417 connect _WIRE[10], _T_423 connect _WIRE[11], _T_429 connect _WIRE[12], _T_435 connect _WIRE[13], _T_441 connect _WIRE[14], _T_447 connect _WIRE[15], _T_453 connect _WIRE[16], _T_454 node _T_455 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_456 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[5], _T_455, UInt<1>(0h0)) node _T_462 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = or(_T_456, _T_457) node _T_474 = or(_T_473, _T_458) node _T_475 = or(_T_474, _T_459) node _T_476 = or(_T_475, _T_460) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_462) node _T_479 = or(_T_478, _T_463) node _T_480 = or(_T_479, _T_464) node _T_481 = or(_T_480, _T_465) node _T_482 = or(_T_481, _T_466) node _T_483 = or(_T_482, _T_467) node _T_484 = or(_T_483, _T_468) node _T_485 = or(_T_484, _T_469) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_471) node _T_488 = or(_T_487, _T_472) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_488 node _T_489 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_490 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<14>(0h2000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<17>(0h10000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<18>(0h2f000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<13>(0h1000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_529 = cvt(_T_528) node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000))) node _T_531 = asSInt(_T_530) node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0))) node _T_533 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<19>(0h40000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = or(_T_497, _T_502) node _T_539 = or(_T_538, _T_507) node _T_540 = or(_T_539, _T_512) node _T_541 = or(_T_540, _T_517) node _T_542 = or(_T_541, _T_522) node _T_543 = or(_T_542, _T_527) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_537) node _T_546 = and(_T_492, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_WIRE_1, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_548, UInt<1>(0h1), "") : assert_3 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(source_ok, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_555 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_555, UInt<1>(0h1), "") : assert_5 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(is_aligned, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_562 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_562, UInt<1>(0h1), "") : assert_7 node _T_566 = not(io.in.a.bits.mask) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_567, UInt<1>(0h1), "") : assert_8 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_571, UInt<1>(0h1), "") : assert_9 node _T_575 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<7>(0h40)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_36) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<7>(0h41)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_37) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<7>(0h42)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_38) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<7>(0h43)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_39) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_605 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_606 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_607 = shr(io.in.a.bits.source, 5) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_40) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_613 = shr(io.in.a.bits.source, 5) node _T_614 = eq(_T_613, UInt<1>(0h1)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_41) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_619 = shr(io.in.a.bits.source, 5) node _T_620 = eq(_T_619, UInt<2>(0h2)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_42) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_624 = and(_T_622, _T_623) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_625 = shr(io.in.a.bits.source, 5) node _T_626 = eq(_T_625, UInt<2>(0h3)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_43) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_631 = shr(io.in.a.bits.source, 5) node _T_632 = eq(_T_631, UInt<3>(0h4)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_44) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_637 = shr(io.in.a.bits.source, 5) node _T_638 = eq(_T_637, UInt<3>(0h5)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_45) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_643 = shr(io.in.a.bits.source, 5) node _T_644 = eq(_T_643, UInt<3>(0h6)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_46) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_649 = shr(io.in.a.bits.source, 5) node _T_650 = eq(_T_649, UInt<3>(0h7)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_47) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_656 = or(_T_579, _T_585) node _T_657 = or(_T_656, _T_591) node _T_658 = or(_T_657, _T_597) node _T_659 = or(_T_658, _T_603) node _T_660 = or(_T_659, _T_604) node _T_661 = or(_T_660, _T_605) node _T_662 = or(_T_661, _T_606) node _T_663 = or(_T_662, _T_612) node _T_664 = or(_T_663, _T_618) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_630) node _T_667 = or(_T_666, _T_636) node _T_668 = or(_T_667, _T_642) node _T_669 = or(_T_668, _T_648) node _T_670 = or(_T_669, _T_654) node _T_671 = or(_T_670, _T_655) node _T_672 = and(_T_578, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<14>(0h2000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<13>(0h1000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<17>(0h10000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<18>(0h2f000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<17>(0h10000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<27>(0h4000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<19>(0h40000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_679, _T_684) node _T_721 = or(_T_720, _T_689) node _T_722 = or(_T_721, _T_694) node _T_723 = or(_T_722, _T_699) node _T_724 = or(_T_723, _T_704) node _T_725 = or(_T_724, _T_709) node _T_726 = or(_T_725, _T_714) node _T_727 = or(_T_726, _T_719) node _T_728 = and(_T_674, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = and(_T_673, _T_729) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_730, UInt<1>(0h1), "") : assert_10 node _T_734 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_735 = shr(io.in.a.bits.source, 2) node _T_736 = eq(_T_735, UInt<7>(0h40)) node _T_737 = leq(UInt<1>(0h0), uncommonBits_48) node _T_738 = and(_T_736, _T_737) node _T_739 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_740 = and(_T_738, _T_739) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_741 = shr(io.in.a.bits.source, 2) node _T_742 = eq(_T_741, UInt<7>(0h41)) node _T_743 = leq(UInt<1>(0h0), uncommonBits_49) node _T_744 = and(_T_742, _T_743) node _T_745 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_746 = and(_T_744, _T_745) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_747 = shr(io.in.a.bits.source, 2) node _T_748 = eq(_T_747, UInt<7>(0h42)) node _T_749 = leq(UInt<1>(0h0), uncommonBits_50) node _T_750 = and(_T_748, _T_749) node _T_751 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_752 = and(_T_750, _T_751) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_753 = shr(io.in.a.bits.source, 2) node _T_754 = eq(_T_753, UInt<7>(0h43)) node _T_755 = leq(UInt<1>(0h0), uncommonBits_51) node _T_756 = and(_T_754, _T_755) node _T_757 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_760 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_761 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_762 = shr(io.in.a.bits.source, 5) node _T_763 = eq(_T_762, UInt<1>(0h0)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_52) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_767 = and(_T_765, _T_766) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_768 = shr(io.in.a.bits.source, 5) node _T_769 = eq(_T_768, UInt<1>(0h1)) node _T_770 = leq(UInt<1>(0h0), uncommonBits_53) node _T_771 = and(_T_769, _T_770) node _T_772 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_773 = and(_T_771, _T_772) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_774 = shr(io.in.a.bits.source, 5) node _T_775 = eq(_T_774, UInt<2>(0h2)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_54) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_780 = shr(io.in.a.bits.source, 5) node _T_781 = eq(_T_780, UInt<2>(0h3)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_55) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_786 = shr(io.in.a.bits.source, 5) node _T_787 = eq(_T_786, UInt<3>(0h4)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_56) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_792 = shr(io.in.a.bits.source, 5) node _T_793 = eq(_T_792, UInt<3>(0h5)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_57) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_797 = and(_T_795, _T_796) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_798 = shr(io.in.a.bits.source, 5) node _T_799 = eq(_T_798, UInt<3>(0h6)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_58) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_803 = and(_T_801, _T_802) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_804 = shr(io.in.a.bits.source, 5) node _T_805 = eq(_T_804, UInt<3>(0h7)) node _T_806 = leq(UInt<1>(0h0), uncommonBits_59) node _T_807 = and(_T_805, _T_806) node _T_808 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_809 = and(_T_807, _T_808) node _T_810 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_734 connect _WIRE_2[1], _T_740 connect _WIRE_2[2], _T_746 connect _WIRE_2[3], _T_752 connect _WIRE_2[4], _T_758 connect _WIRE_2[5], _T_759 connect _WIRE_2[6], _T_760 connect _WIRE_2[7], _T_761 connect _WIRE_2[8], _T_767 connect _WIRE_2[9], _T_773 connect _WIRE_2[10], _T_779 connect _WIRE_2[11], _T_785 connect _WIRE_2[12], _T_791 connect _WIRE_2[13], _T_797 connect _WIRE_2[14], _T_803 connect _WIRE_2[15], _T_809 connect _WIRE_2[16], _T_810 node _T_811 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_812 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_813 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_814 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_815 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_816 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = mux(_WIRE_2[5], _T_811, UInt<1>(0h0)) node _T_818 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_820 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_821 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_822 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_824 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_825 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_826 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_827 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_828 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_829 = or(_T_812, _T_813) node _T_830 = or(_T_829, _T_814) node _T_831 = or(_T_830, _T_815) node _T_832 = or(_T_831, _T_816) node _T_833 = or(_T_832, _T_817) node _T_834 = or(_T_833, _T_818) node _T_835 = or(_T_834, _T_819) node _T_836 = or(_T_835, _T_820) node _T_837 = or(_T_836, _T_821) node _T_838 = or(_T_837, _T_822) node _T_839 = or(_T_838, _T_823) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_825) node _T_842 = or(_T_841, _T_826) node _T_843 = or(_T_842, _T_827) node _T_844 = or(_T_843, _T_828) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_844 node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<14>(0h2000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<19>(0h40000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = or(_T_853, _T_858) node _T_895 = or(_T_894, _T_863) node _T_896 = or(_T_895, _T_868) node _T_897 = or(_T_896, _T_873) node _T_898 = or(_T_897, _T_878) node _T_899 = or(_T_898, _T_883) node _T_900 = or(_T_899, _T_888) node _T_901 = or(_T_900, _T_893) node _T_902 = and(_T_848, _T_901) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = and(_WIRE_3, _T_903) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_904, UInt<1>(0h1), "") : assert_11 node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_911 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_911, UInt<1>(0h1), "") : assert_13 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(is_aligned, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_918 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_918, UInt<1>(0h1), "") : assert_15 node _T_922 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_922, UInt<1>(0h1), "") : assert_16 node _T_926 = not(io.in.a.bits.mask) node _T_927 = eq(_T_926, UInt<1>(0h0)) node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(_T_927, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_927, UInt<1>(0h1), "") : assert_17 node _T_931 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_931, UInt<1>(0h1), "") : assert_18 node _T_935 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_935 : node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<7>(0h40)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_60) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<7>(0h41)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_61) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<7>(0h42)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_62) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<7>(0h43)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_63) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _T_964 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_967 = shr(io.in.a.bits.source, 5) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = leq(UInt<1>(0h0), uncommonBits_64) node _T_970 = and(_T_968, _T_969) node _T_971 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_972 = and(_T_970, _T_971) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_973 = shr(io.in.a.bits.source, 5) node _T_974 = eq(_T_973, UInt<1>(0h1)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_65) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_978 = and(_T_976, _T_977) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_979 = shr(io.in.a.bits.source, 5) node _T_980 = eq(_T_979, UInt<2>(0h2)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_66) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_985 = shr(io.in.a.bits.source, 5) node _T_986 = eq(_T_985, UInt<2>(0h3)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_67) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_991 = shr(io.in.a.bits.source, 5) node _T_992 = eq(_T_991, UInt<3>(0h4)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_68) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_996 = and(_T_994, _T_995) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_997 = shr(io.in.a.bits.source, 5) node _T_998 = eq(_T_997, UInt<3>(0h5)) node _T_999 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1000 = and(_T_998, _T_999) node _T_1001 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1002 = and(_T_1000, _T_1001) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1003 = shr(io.in.a.bits.source, 5) node _T_1004 = eq(_T_1003, UInt<3>(0h6)) node _T_1005 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1006 = and(_T_1004, _T_1005) node _T_1007 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1008 = and(_T_1006, _T_1007) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1009 = shr(io.in.a.bits.source, 5) node _T_1010 = eq(_T_1009, UInt<3>(0h7)) node _T_1011 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1016 = or(_T_939, _T_945) node _T_1017 = or(_T_1016, _T_951) node _T_1018 = or(_T_1017, _T_957) node _T_1019 = or(_T_1018, _T_963) node _T_1020 = or(_T_1019, _T_964) node _T_1021 = or(_T_1020, _T_965) node _T_1022 = or(_T_1021, _T_966) node _T_1023 = or(_T_1022, _T_972) node _T_1024 = or(_T_1023, _T_978) node _T_1025 = or(_T_1024, _T_984) node _T_1026 = or(_T_1025, _T_990) node _T_1027 = or(_T_1026, _T_996) node _T_1028 = or(_T_1027, _T_1002) node _T_1029 = or(_T_1028, _T_1008) node _T_1030 = or(_T_1029, _T_1014) node _T_1031 = or(_T_1030, _T_1015) node _T_1032 = and(_T_938, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_19 node _T_1037 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1038 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1039 = and(_T_1037, _T_1038) node _T_1040 = or(UInt<1>(0h0), _T_1039) node _T_1041 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1042 = cvt(_T_1041) node _T_1043 = and(_T_1042, asSInt(UInt<13>(0h1000))) node _T_1044 = asSInt(_T_1043) node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0))) node _T_1046 = and(_T_1040, _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1048 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<14>(0h2000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<18>(0h2f000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1067 = cvt(_T_1066) node _T_1068 = and(_T_1067, asSInt(UInt<17>(0h10000))) node _T_1069 = asSInt(_T_1068) node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0))) node _T_1071 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1072 = cvt(_T_1071) node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000))) node _T_1074 = asSInt(_T_1073) node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1077 = cvt(_T_1076) node _T_1078 = and(_T_1077, asSInt(UInt<27>(0h4000000))) node _T_1079 = asSInt(_T_1078) node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0))) node _T_1081 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1082 = cvt(_T_1081) node _T_1083 = and(_T_1082, asSInt(UInt<13>(0h1000))) node _T_1084 = asSInt(_T_1083) node _T_1085 = eq(_T_1084, asSInt(UInt<1>(0h0))) node _T_1086 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<19>(0h40000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1055, _T_1060) node _T_1092 = or(_T_1091, _T_1065) node _T_1093 = or(_T_1092, _T_1070) node _T_1094 = or(_T_1093, _T_1075) node _T_1095 = or(_T_1094, _T_1080) node _T_1096 = or(_T_1095, _T_1085) node _T_1097 = or(_T_1096, _T_1090) node _T_1098 = and(_T_1050, _T_1097) node _T_1099 = or(UInt<1>(0h0), _T_1046) node _T_1100 = or(_T_1099, _T_1098) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_20 node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(is_aligned, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1110 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_23 node _T_1114 = eq(io.in.a.bits.mask, mask) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_24 node _T_1118 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_25 node _T_1122 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1122 : node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1127 = shr(io.in.a.bits.source, 2) node _T_1128 = eq(_T_1127, UInt<7>(0h40)) node _T_1129 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1132 = and(_T_1130, _T_1131) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1133 = shr(io.in.a.bits.source, 2) node _T_1134 = eq(_T_1133, UInt<7>(0h41)) node _T_1135 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1138 = and(_T_1136, _T_1137) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_1139 = shr(io.in.a.bits.source, 2) node _T_1140 = eq(_T_1139, UInt<7>(0h42)) node _T_1141 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1145 = shr(io.in.a.bits.source, 2) node _T_1146 = eq(_T_1145, UInt<7>(0h43)) node _T_1147 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1152 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1153 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_1154 = shr(io.in.a.bits.source, 5) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) node _T_1156 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_1159 = and(_T_1157, _T_1158) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_1160 = shr(io.in.a.bits.source, 5) node _T_1161 = eq(_T_1160, UInt<1>(0h1)) node _T_1162 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_1165 = and(_T_1163, _T_1164) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_1166 = shr(io.in.a.bits.source, 5) node _T_1167 = eq(_T_1166, UInt<2>(0h2)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_1172 = shr(io.in.a.bits.source, 5) node _T_1173 = eq(_T_1172, UInt<2>(0h3)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_1178 = shr(io.in.a.bits.source, 5) node _T_1179 = eq(_T_1178, UInt<3>(0h4)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_1184 = shr(io.in.a.bits.source, 5) node _T_1185 = eq(_T_1184, UInt<3>(0h5)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_1190 = shr(io.in.a.bits.source, 5) node _T_1191 = eq(_T_1190, UInt<3>(0h6)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_1196 = shr(io.in.a.bits.source, 5) node _T_1197 = eq(_T_1196, UInt<3>(0h7)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1203 = or(_T_1126, _T_1132) node _T_1204 = or(_T_1203, _T_1138) node _T_1205 = or(_T_1204, _T_1144) node _T_1206 = or(_T_1205, _T_1150) node _T_1207 = or(_T_1206, _T_1151) node _T_1208 = or(_T_1207, _T_1152) node _T_1209 = or(_T_1208, _T_1153) node _T_1210 = or(_T_1209, _T_1159) node _T_1211 = or(_T_1210, _T_1165) node _T_1212 = or(_T_1211, _T_1171) node _T_1213 = or(_T_1212, _T_1177) node _T_1214 = or(_T_1213, _T_1183) node _T_1215 = or(_T_1214, _T_1189) node _T_1216 = or(_T_1215, _T_1195) node _T_1217 = or(_T_1216, _T_1201) node _T_1218 = or(_T_1217, _T_1202) node _T_1219 = and(_T_1125, _T_1218) node _T_1220 = or(UInt<1>(0h0), _T_1219) node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1223 = and(_T_1221, _T_1222) node _T_1224 = or(UInt<1>(0h0), _T_1223) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = and(_T_1224, _T_1229) node _T_1231 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1232 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1233) node _T_1235 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<14>(0h2000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<18>(0h2f000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<17>(0h10000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<27>(0h4000000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<13>(0h1000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<19>(0h40000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = or(_T_1239, _T_1244) node _T_1271 = or(_T_1270, _T_1249) node _T_1272 = or(_T_1271, _T_1254) node _T_1273 = or(_T_1272, _T_1259) node _T_1274 = or(_T_1273, _T_1264) node _T_1275 = or(_T_1274, _T_1269) node _T_1276 = and(_T_1234, _T_1275) node _T_1277 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1278 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = and(_T_1277, _T_1282) node _T_1284 = or(UInt<1>(0h0), _T_1230) node _T_1285 = or(_T_1284, _T_1276) node _T_1286 = or(_T_1285, _T_1283) node _T_1287 = and(_T_1220, _T_1286) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_26 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(is_aligned, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1297 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_29 node _T_1301 = eq(io.in.a.bits.mask, mask) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_30 node _T_1305 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1305 : node _T_1306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1310 = shr(io.in.a.bits.source, 2) node _T_1311 = eq(_T_1310, UInt<7>(0h40)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1316 = shr(io.in.a.bits.source, 2) node _T_1317 = eq(_T_1316, UInt<7>(0h41)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1322 = shr(io.in.a.bits.source, 2) node _T_1323 = eq(_T_1322, UInt<7>(0h42)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1327 = and(_T_1325, _T_1326) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1328 = shr(io.in.a.bits.source, 2) node _T_1329 = eq(_T_1328, UInt<7>(0h43)) node _T_1330 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1331 = and(_T_1329, _T_1330) node _T_1332 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1335 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1336 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1337 = shr(io.in.a.bits.source, 5) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) node _T_1339 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1342 = and(_T_1340, _T_1341) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1343 = shr(io.in.a.bits.source, 5) node _T_1344 = eq(_T_1343, UInt<1>(0h1)) node _T_1345 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1348 = and(_T_1346, _T_1347) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1349 = shr(io.in.a.bits.source, 5) node _T_1350 = eq(_T_1349, UInt<2>(0h2)) node _T_1351 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1352 = and(_T_1350, _T_1351) node _T_1353 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1354 = and(_T_1352, _T_1353) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1355 = shr(io.in.a.bits.source, 5) node _T_1356 = eq(_T_1355, UInt<2>(0h3)) node _T_1357 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1358 = and(_T_1356, _T_1357) node _T_1359 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1360 = and(_T_1358, _T_1359) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1361 = shr(io.in.a.bits.source, 5) node _T_1362 = eq(_T_1361, UInt<3>(0h4)) node _T_1363 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1366 = and(_T_1364, _T_1365) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1367 = shr(io.in.a.bits.source, 5) node _T_1368 = eq(_T_1367, UInt<3>(0h5)) node _T_1369 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1370 = and(_T_1368, _T_1369) node _T_1371 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1372 = and(_T_1370, _T_1371) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1373 = shr(io.in.a.bits.source, 5) node _T_1374 = eq(_T_1373, UInt<3>(0h6)) node _T_1375 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1376 = and(_T_1374, _T_1375) node _T_1377 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1378 = and(_T_1376, _T_1377) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1379 = shr(io.in.a.bits.source, 5) node _T_1380 = eq(_T_1379, UInt<3>(0h7)) node _T_1381 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1386 = or(_T_1309, _T_1315) node _T_1387 = or(_T_1386, _T_1321) node _T_1388 = or(_T_1387, _T_1327) node _T_1389 = or(_T_1388, _T_1333) node _T_1390 = or(_T_1389, _T_1334) node _T_1391 = or(_T_1390, _T_1335) node _T_1392 = or(_T_1391, _T_1336) node _T_1393 = or(_T_1392, _T_1342) node _T_1394 = or(_T_1393, _T_1348) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1360) node _T_1397 = or(_T_1396, _T_1366) node _T_1398 = or(_T_1397, _T_1372) node _T_1399 = or(_T_1398, _T_1378) node _T_1400 = or(_T_1399, _T_1384) node _T_1401 = or(_T_1400, _T_1385) node _T_1402 = and(_T_1308, _T_1401) node _T_1403 = or(UInt<1>(0h0), _T_1402) node _T_1404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1405 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1406 = and(_T_1404, _T_1405) node _T_1407 = or(UInt<1>(0h0), _T_1406) node _T_1408 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1409 = cvt(_T_1408) node _T_1410 = and(_T_1409, asSInt(UInt<13>(0h1000))) node _T_1411 = asSInt(_T_1410) node _T_1412 = eq(_T_1411, asSInt(UInt<1>(0h0))) node _T_1413 = and(_T_1407, _T_1412) node _T_1414 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1415 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1416 = and(_T_1414, _T_1415) node _T_1417 = or(UInt<1>(0h0), _T_1416) node _T_1418 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<14>(0h2000))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1424 = cvt(_T_1423) node _T_1425 = and(_T_1424, asSInt(UInt<18>(0h2f000))) node _T_1426 = asSInt(_T_1425) node _T_1427 = eq(_T_1426, asSInt(UInt<1>(0h0))) node _T_1428 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1429 = cvt(_T_1428) node _T_1430 = and(_T_1429, asSInt(UInt<17>(0h10000))) node _T_1431 = asSInt(_T_1430) node _T_1432 = eq(_T_1431, asSInt(UInt<1>(0h0))) node _T_1433 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1434 = cvt(_T_1433) node _T_1435 = and(_T_1434, asSInt(UInt<13>(0h1000))) node _T_1436 = asSInt(_T_1435) node _T_1437 = eq(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1439 = cvt(_T_1438) node _T_1440 = and(_T_1439, asSInt(UInt<27>(0h4000000))) node _T_1441 = asSInt(_T_1440) node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0))) node _T_1443 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<13>(0h1000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<19>(0h40000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1422, _T_1427) node _T_1454 = or(_T_1453, _T_1432) node _T_1455 = or(_T_1454, _T_1437) node _T_1456 = or(_T_1455, _T_1442) node _T_1457 = or(_T_1456, _T_1447) node _T_1458 = or(_T_1457, _T_1452) node _T_1459 = and(_T_1417, _T_1458) node _T_1460 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1461 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<17>(0h10000))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = and(_T_1460, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1413) node _T_1468 = or(_T_1467, _T_1459) node _T_1469 = or(_T_1468, _T_1466) node _T_1470 = and(_T_1403, _T_1469) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_31 node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(is_aligned, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1480 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_34 node _T_1484 = not(mask) node _T_1485 = and(io.in.a.bits.mask, _T_1484) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_35 node _T_1490 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1495 = shr(io.in.a.bits.source, 2) node _T_1496 = eq(_T_1495, UInt<7>(0h40)) node _T_1497 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1500 = and(_T_1498, _T_1499) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1501 = shr(io.in.a.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<7>(0h41)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1507 = shr(io.in.a.bits.source, 2) node _T_1508 = eq(_T_1507, UInt<7>(0h42)) node _T_1509 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1510 = and(_T_1508, _T_1509) node _T_1511 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1512 = and(_T_1510, _T_1511) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1513 = shr(io.in.a.bits.source, 2) node _T_1514 = eq(_T_1513, UInt<7>(0h43)) node _T_1515 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1516 = and(_T_1514, _T_1515) node _T_1517 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1518 = and(_T_1516, _T_1517) node _T_1519 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1520 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1521 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1522 = shr(io.in.a.bits.source, 5) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) node _T_1524 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1525 = and(_T_1523, _T_1524) node _T_1526 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1527 = and(_T_1525, _T_1526) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1528 = shr(io.in.a.bits.source, 5) node _T_1529 = eq(_T_1528, UInt<1>(0h1)) node _T_1530 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1531 = and(_T_1529, _T_1530) node _T_1532 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1533 = and(_T_1531, _T_1532) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1534 = shr(io.in.a.bits.source, 5) node _T_1535 = eq(_T_1534, UInt<2>(0h2)) node _T_1536 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1539 = and(_T_1537, _T_1538) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1540 = shr(io.in.a.bits.source, 5) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1545 = and(_T_1543, _T_1544) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1546 = shr(io.in.a.bits.source, 5) node _T_1547 = eq(_T_1546, UInt<3>(0h4)) node _T_1548 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1549 = and(_T_1547, _T_1548) node _T_1550 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1551 = and(_T_1549, _T_1550) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1552 = shr(io.in.a.bits.source, 5) node _T_1553 = eq(_T_1552, UInt<3>(0h5)) node _T_1554 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1557 = and(_T_1555, _T_1556) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1558 = shr(io.in.a.bits.source, 5) node _T_1559 = eq(_T_1558, UInt<3>(0h6)) node _T_1560 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1563 = and(_T_1561, _T_1562) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1564 = shr(io.in.a.bits.source, 5) node _T_1565 = eq(_T_1564, UInt<3>(0h7)) node _T_1566 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1569 = and(_T_1567, _T_1568) node _T_1570 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1571 = or(_T_1494, _T_1500) node _T_1572 = or(_T_1571, _T_1506) node _T_1573 = or(_T_1572, _T_1512) node _T_1574 = or(_T_1573, _T_1518) node _T_1575 = or(_T_1574, _T_1519) node _T_1576 = or(_T_1575, _T_1520) node _T_1577 = or(_T_1576, _T_1521) node _T_1578 = or(_T_1577, _T_1527) node _T_1579 = or(_T_1578, _T_1533) node _T_1580 = or(_T_1579, _T_1539) node _T_1581 = or(_T_1580, _T_1545) node _T_1582 = or(_T_1581, _T_1551) node _T_1583 = or(_T_1582, _T_1557) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1569) node _T_1586 = or(_T_1585, _T_1570) node _T_1587 = and(_T_1493, _T_1586) node _T_1588 = or(UInt<1>(0h0), _T_1587) node _T_1589 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1590 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = or(UInt<1>(0h0), _T_1591) node _T_1593 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1594 = cvt(_T_1593) node _T_1595 = and(_T_1594, asSInt(UInt<14>(0h2000))) node _T_1596 = asSInt(_T_1595) node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0))) node _T_1598 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1599 = cvt(_T_1598) node _T_1600 = and(_T_1599, asSInt(UInt<13>(0h1000))) node _T_1601 = asSInt(_T_1600) node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0))) node _T_1603 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1604 = cvt(_T_1603) node _T_1605 = and(_T_1604, asSInt(UInt<18>(0h2f000))) node _T_1606 = asSInt(_T_1605) node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0))) node _T_1608 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1609 = cvt(_T_1608) node _T_1610 = and(_T_1609, asSInt(UInt<17>(0h10000))) node _T_1611 = asSInt(_T_1610) node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0))) node _T_1613 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1614 = cvt(_T_1613) node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000))) node _T_1616 = asSInt(_T_1615) node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0))) node _T_1618 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<27>(0h4000000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<19>(0h40000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = or(_T_1597, _T_1602) node _T_1634 = or(_T_1633, _T_1607) node _T_1635 = or(_T_1634, _T_1612) node _T_1636 = or(_T_1635, _T_1617) node _T_1637 = or(_T_1636, _T_1622) node _T_1638 = or(_T_1637, _T_1627) node _T_1639 = or(_T_1638, _T_1632) node _T_1640 = and(_T_1592, _T_1639) node _T_1641 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1642 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1643 = cvt(_T_1642) node _T_1644 = and(_T_1643, asSInt(UInt<17>(0h10000))) node _T_1645 = asSInt(_T_1644) node _T_1646 = eq(_T_1645, asSInt(UInt<1>(0h0))) node _T_1647 = and(_T_1641, _T_1646) node _T_1648 = or(UInt<1>(0h0), _T_1640) node _T_1649 = or(_T_1648, _T_1647) node _T_1650 = and(_T_1588, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_36 node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(source_ok, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(is_aligned, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1660 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_39 node _T_1664 = eq(io.in.a.bits.mask, mask) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_40 node _T_1668 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1668 : node _T_1669 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1670 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1673 = shr(io.in.a.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<7>(0h40)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1679 = shr(io.in.a.bits.source, 2) node _T_1680 = eq(_T_1679, UInt<7>(0h41)) node _T_1681 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1684 = and(_T_1682, _T_1683) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1685 = shr(io.in.a.bits.source, 2) node _T_1686 = eq(_T_1685, UInt<7>(0h42)) node _T_1687 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1688 = and(_T_1686, _T_1687) node _T_1689 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1690 = and(_T_1688, _T_1689) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1691 = shr(io.in.a.bits.source, 2) node _T_1692 = eq(_T_1691, UInt<7>(0h43)) node _T_1693 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1694 = and(_T_1692, _T_1693) node _T_1695 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1696 = and(_T_1694, _T_1695) node _T_1697 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1698 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1699 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1700 = shr(io.in.a.bits.source, 5) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) node _T_1702 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1705 = and(_T_1703, _T_1704) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1706 = shr(io.in.a.bits.source, 5) node _T_1707 = eq(_T_1706, UInt<1>(0h1)) node _T_1708 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1709 = and(_T_1707, _T_1708) node _T_1710 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1711 = and(_T_1709, _T_1710) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1712 = shr(io.in.a.bits.source, 5) node _T_1713 = eq(_T_1712, UInt<2>(0h2)) node _T_1714 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1717 = and(_T_1715, _T_1716) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1718 = shr(io.in.a.bits.source, 5) node _T_1719 = eq(_T_1718, UInt<2>(0h3)) node _T_1720 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1723 = and(_T_1721, _T_1722) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1724 = shr(io.in.a.bits.source, 5) node _T_1725 = eq(_T_1724, UInt<3>(0h4)) node _T_1726 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1729 = and(_T_1727, _T_1728) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1730 = shr(io.in.a.bits.source, 5) node _T_1731 = eq(_T_1730, UInt<3>(0h5)) node _T_1732 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1733 = and(_T_1731, _T_1732) node _T_1734 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1735 = and(_T_1733, _T_1734) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1736 = shr(io.in.a.bits.source, 5) node _T_1737 = eq(_T_1736, UInt<3>(0h6)) node _T_1738 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1739 = and(_T_1737, _T_1738) node _T_1740 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1741 = and(_T_1739, _T_1740) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1742 = shr(io.in.a.bits.source, 5) node _T_1743 = eq(_T_1742, UInt<3>(0h7)) node _T_1744 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1745 = and(_T_1743, _T_1744) node _T_1746 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1747 = and(_T_1745, _T_1746) node _T_1748 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1749 = or(_T_1672, _T_1678) node _T_1750 = or(_T_1749, _T_1684) node _T_1751 = or(_T_1750, _T_1690) node _T_1752 = or(_T_1751, _T_1696) node _T_1753 = or(_T_1752, _T_1697) node _T_1754 = or(_T_1753, _T_1698) node _T_1755 = or(_T_1754, _T_1699) node _T_1756 = or(_T_1755, _T_1705) node _T_1757 = or(_T_1756, _T_1711) node _T_1758 = or(_T_1757, _T_1717) node _T_1759 = or(_T_1758, _T_1723) node _T_1760 = or(_T_1759, _T_1729) node _T_1761 = or(_T_1760, _T_1735) node _T_1762 = or(_T_1761, _T_1741) node _T_1763 = or(_T_1762, _T_1747) node _T_1764 = or(_T_1763, _T_1748) node _T_1765 = and(_T_1671, _T_1764) node _T_1766 = or(UInt<1>(0h0), _T_1765) node _T_1767 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1768 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1769 = and(_T_1767, _T_1768) node _T_1770 = or(UInt<1>(0h0), _T_1769) node _T_1771 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1772 = cvt(_T_1771) node _T_1773 = and(_T_1772, asSInt(UInt<14>(0h2000))) node _T_1774 = asSInt(_T_1773) node _T_1775 = eq(_T_1774, asSInt(UInt<1>(0h0))) node _T_1776 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1777 = cvt(_T_1776) node _T_1778 = and(_T_1777, asSInt(UInt<13>(0h1000))) node _T_1779 = asSInt(_T_1778) node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1782 = cvt(_T_1781) node _T_1783 = and(_T_1782, asSInt(UInt<18>(0h2f000))) node _T_1784 = asSInt(_T_1783) node _T_1785 = eq(_T_1784, asSInt(UInt<1>(0h0))) node _T_1786 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1787 = cvt(_T_1786) node _T_1788 = and(_T_1787, asSInt(UInt<17>(0h10000))) node _T_1789 = asSInt(_T_1788) node _T_1790 = eq(_T_1789, asSInt(UInt<1>(0h0))) node _T_1791 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1792 = cvt(_T_1791) node _T_1793 = and(_T_1792, asSInt(UInt<13>(0h1000))) node _T_1794 = asSInt(_T_1793) node _T_1795 = eq(_T_1794, asSInt(UInt<1>(0h0))) node _T_1796 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1797 = cvt(_T_1796) node _T_1798 = and(_T_1797, asSInt(UInt<27>(0h4000000))) node _T_1799 = asSInt(_T_1798) node _T_1800 = eq(_T_1799, asSInt(UInt<1>(0h0))) node _T_1801 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1802 = cvt(_T_1801) node _T_1803 = and(_T_1802, asSInt(UInt<13>(0h1000))) node _T_1804 = asSInt(_T_1803) node _T_1805 = eq(_T_1804, asSInt(UInt<1>(0h0))) node _T_1806 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1807 = cvt(_T_1806) node _T_1808 = and(_T_1807, asSInt(UInt<19>(0h40000))) node _T_1809 = asSInt(_T_1808) node _T_1810 = eq(_T_1809, asSInt(UInt<1>(0h0))) node _T_1811 = or(_T_1775, _T_1780) node _T_1812 = or(_T_1811, _T_1785) node _T_1813 = or(_T_1812, _T_1790) node _T_1814 = or(_T_1813, _T_1795) node _T_1815 = or(_T_1814, _T_1800) node _T_1816 = or(_T_1815, _T_1805) node _T_1817 = or(_T_1816, _T_1810) node _T_1818 = and(_T_1770, _T_1817) node _T_1819 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1820 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1821 = cvt(_T_1820) node _T_1822 = and(_T_1821, asSInt(UInt<17>(0h10000))) node _T_1823 = asSInt(_T_1822) node _T_1824 = eq(_T_1823, asSInt(UInt<1>(0h0))) node _T_1825 = and(_T_1819, _T_1824) node _T_1826 = or(UInt<1>(0h0), _T_1818) node _T_1827 = or(_T_1826, _T_1825) node _T_1828 = and(_T_1766, _T_1827) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_41 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(source_ok, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_44 node _T_1842 = eq(io.in.a.bits.mask, mask) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_45 node _T_1846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1851 = shr(io.in.a.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<7>(0h40)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1857 = shr(io.in.a.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<7>(0h41)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1863 = shr(io.in.a.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<7>(0h42)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1869 = shr(io.in.a.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<7>(0h43)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _T_1875 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1876 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1877 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1878 = shr(io.in.a.bits.source, 5) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1883 = and(_T_1881, _T_1882) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1884 = shr(io.in.a.bits.source, 5) node _T_1885 = eq(_T_1884, UInt<1>(0h1)) node _T_1886 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1887 = and(_T_1885, _T_1886) node _T_1888 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1889 = and(_T_1887, _T_1888) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1890 = shr(io.in.a.bits.source, 5) node _T_1891 = eq(_T_1890, UInt<2>(0h2)) node _T_1892 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1893 = and(_T_1891, _T_1892) node _T_1894 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1895 = and(_T_1893, _T_1894) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1896 = shr(io.in.a.bits.source, 5) node _T_1897 = eq(_T_1896, UInt<2>(0h3)) node _T_1898 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1901 = and(_T_1899, _T_1900) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1902 = shr(io.in.a.bits.source, 5) node _T_1903 = eq(_T_1902, UInt<3>(0h4)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1908 = shr(io.in.a.bits.source, 5) node _T_1909 = eq(_T_1908, UInt<3>(0h5)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1914 = shr(io.in.a.bits.source, 5) node _T_1915 = eq(_T_1914, UInt<3>(0h6)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1920 = shr(io.in.a.bits.source, 5) node _T_1921 = eq(_T_1920, UInt<3>(0h7)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1927 = or(_T_1850, _T_1856) node _T_1928 = or(_T_1927, _T_1862) node _T_1929 = or(_T_1928, _T_1868) node _T_1930 = or(_T_1929, _T_1874) node _T_1931 = or(_T_1930, _T_1875) node _T_1932 = or(_T_1931, _T_1876) node _T_1933 = or(_T_1932, _T_1877) node _T_1934 = or(_T_1933, _T_1883) node _T_1935 = or(_T_1934, _T_1889) node _T_1936 = or(_T_1935, _T_1895) node _T_1937 = or(_T_1936, _T_1901) node _T_1938 = or(_T_1937, _T_1907) node _T_1939 = or(_T_1938, _T_1913) node _T_1940 = or(_T_1939, _T_1919) node _T_1941 = or(_T_1940, _T_1925) node _T_1942 = or(_T_1941, _T_1926) node _T_1943 = and(_T_1849, _T_1942) node _T_1944 = or(UInt<1>(0h0), _T_1943) node _T_1945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1947 = and(_T_1945, _T_1946) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1950 = cvt(_T_1949) node _T_1951 = and(_T_1950, asSInt(UInt<13>(0h1000))) node _T_1952 = asSInt(_T_1951) node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0))) node _T_1954 = and(_T_1948, _T_1953) node _T_1955 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1956 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1957 = cvt(_T_1956) node _T_1958 = and(_T_1957, asSInt(UInt<14>(0h2000))) node _T_1959 = asSInt(_T_1958) node _T_1960 = eq(_T_1959, asSInt(UInt<1>(0h0))) node _T_1961 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1962 = cvt(_T_1961) node _T_1963 = and(_T_1962, asSInt(UInt<17>(0h10000))) node _T_1964 = asSInt(_T_1963) node _T_1965 = eq(_T_1964, asSInt(UInt<1>(0h0))) node _T_1966 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1967 = cvt(_T_1966) node _T_1968 = and(_T_1967, asSInt(UInt<18>(0h2f000))) node _T_1969 = asSInt(_T_1968) node _T_1970 = eq(_T_1969, asSInt(UInt<1>(0h0))) node _T_1971 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1972 = cvt(_T_1971) node _T_1973 = and(_T_1972, asSInt(UInt<17>(0h10000))) node _T_1974 = asSInt(_T_1973) node _T_1975 = eq(_T_1974, asSInt(UInt<1>(0h0))) node _T_1976 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1977 = cvt(_T_1976) node _T_1978 = and(_T_1977, asSInt(UInt<13>(0h1000))) node _T_1979 = asSInt(_T_1978) node _T_1980 = eq(_T_1979, asSInt(UInt<1>(0h0))) node _T_1981 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<27>(0h4000000))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1987 = cvt(_T_1986) node _T_1988 = and(_T_1987, asSInt(UInt<13>(0h1000))) node _T_1989 = asSInt(_T_1988) node _T_1990 = eq(_T_1989, asSInt(UInt<1>(0h0))) node _T_1991 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1992 = cvt(_T_1991) node _T_1993 = and(_T_1992, asSInt(UInt<19>(0h40000))) node _T_1994 = asSInt(_T_1993) node _T_1995 = eq(_T_1994, asSInt(UInt<1>(0h0))) node _T_1996 = or(_T_1960, _T_1965) node _T_1997 = or(_T_1996, _T_1970) node _T_1998 = or(_T_1997, _T_1975) node _T_1999 = or(_T_1998, _T_1980) node _T_2000 = or(_T_1999, _T_1985) node _T_2001 = or(_T_2000, _T_1990) node _T_2002 = or(_T_2001, _T_1995) node _T_2003 = and(_T_1955, _T_2002) node _T_2004 = or(UInt<1>(0h0), _T_1954) node _T_2005 = or(_T_2004, _T_2003) node _T_2006 = and(_T_1944, _T_2005) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_46 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(source_ok, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(is_aligned, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2016 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_49 node _T_2020 = eq(io.in.a.bits.mask, mask) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_50 node _T_2024 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(_T_2024, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2024, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2028 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2032 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2032 : node _T_2033 = asUInt(reset) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(source_ok_1, UInt<1>(0h0)) when _T_2035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_54 node _T_2040 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_55 node _T_2044 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_56 node _T_2048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2049 = asUInt(reset) node _T_2050 = eq(_T_2049, UInt<1>(0h0)) when _T_2050 : node _T_2051 = eq(_T_2048, UInt<1>(0h0)) when _T_2051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2048, UInt<1>(0h1), "") : assert_57 node _T_2052 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2052 : node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_1, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(sink_ok, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2059 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(_T_2059, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2059, UInt<1>(0h1), "") : assert_60 node _T_2063 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_61 node _T_2067 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_62 node _T_2071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_63 node _T_2075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2076 = or(UInt<1>(0h1), _T_2075) node _T_2077 = asUInt(reset) node _T_2078 = eq(_T_2077, UInt<1>(0h0)) when _T_2078 : node _T_2079 = eq(_T_2076, UInt<1>(0h0)) when _T_2079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2076, UInt<1>(0h1), "") : assert_64 node _T_2080 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2080 : node _T_2081 = asUInt(reset) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) when _T_2082 : node _T_2083 = eq(source_ok_1, UInt<1>(0h0)) when _T_2083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2084 = asUInt(reset) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) when _T_2085 : node _T_2086 = eq(sink_ok, UInt<1>(0h0)) when _T_2086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2087 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2088 = asUInt(reset) node _T_2089 = eq(_T_2088, UInt<1>(0h0)) when _T_2089 : node _T_2090 = eq(_T_2087, UInt<1>(0h0)) when _T_2090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2087, UInt<1>(0h1), "") : assert_67 node _T_2091 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2092 = asUInt(reset) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) when _T_2093 : node _T_2094 = eq(_T_2091, UInt<1>(0h0)) when _T_2094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2091, UInt<1>(0h1), "") : assert_68 node _T_2095 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(_T_2095, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2095, UInt<1>(0h1), "") : assert_69 node _T_2099 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2100 = or(_T_2099, io.in.d.bits.corrupt) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_70 node _T_2104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2105 = or(UInt<1>(0h1), _T_2104) node _T_2106 = asUInt(reset) node _T_2107 = eq(_T_2106, UInt<1>(0h0)) when _T_2107 : node _T_2108 = eq(_T_2105, UInt<1>(0h0)) when _T_2108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2105, UInt<1>(0h1), "") : assert_71 node _T_2109 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2109 : node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_1, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2113 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_73 node _T_2117 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2118 = asUInt(reset) node _T_2119 = eq(_T_2118, UInt<1>(0h0)) when _T_2119 : node _T_2120 = eq(_T_2117, UInt<1>(0h0)) when _T_2120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2117, UInt<1>(0h1), "") : assert_74 node _T_2121 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2122 = or(UInt<1>(0h1), _T_2121) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_75 node _T_2126 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2126 : node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(source_ok_1, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2130 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_77 node _T_2134 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2135 = or(_T_2134, io.in.d.bits.corrupt) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_78 node _T_2139 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2140 = or(UInt<1>(0h1), _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_79 node _T_2144 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2144 : node _T_2145 = asUInt(reset) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) when _T_2146 : node _T_2147 = eq(source_ok_1, UInt<1>(0h0)) when _T_2147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2148 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2149 = asUInt(reset) node _T_2150 = eq(_T_2149, UInt<1>(0h0)) when _T_2150 : node _T_2151 = eq(_T_2148, UInt<1>(0h0)) when _T_2151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2148, UInt<1>(0h1), "") : assert_81 node _T_2152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_82 node _T_2156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2157 = or(UInt<1>(0h1), _T_2156) node _T_2158 = asUInt(reset) node _T_2159 = eq(_T_2158, UInt<1>(0h0)) when _T_2159 : node _T_2160 = eq(_T_2157, UInt<1>(0h0)) when _T_2160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2157, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2161 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2165 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2169 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(_T_2169, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2169, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2173 = eq(a_first, UInt<1>(0h0)) node _T_2174 = and(io.in.a.valid, _T_2173) when _T_2174 : node _T_2175 = eq(io.in.a.bits.opcode, opcode) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_87 node _T_2179 = eq(io.in.a.bits.param, param) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_88 node _T_2183 = eq(io.in.a.bits.size, size) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_89 node _T_2187 = eq(io.in.a.bits.source, source) node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(_T_2187, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2187, UInt<1>(0h1), "") : assert_90 node _T_2191 = eq(io.in.a.bits.address, address) node _T_2192 = asUInt(reset) node _T_2193 = eq(_T_2192, UInt<1>(0h0)) when _T_2193 : node _T_2194 = eq(_T_2191, UInt<1>(0h0)) when _T_2194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2191, UInt<1>(0h1), "") : assert_91 node _T_2195 = and(io.in.a.ready, io.in.a.valid) node _T_2196 = and(_T_2195, a_first) when _T_2196 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2197 = eq(d_first, UInt<1>(0h0)) node _T_2198 = and(io.in.d.valid, _T_2197) when _T_2198 : node _T_2199 = eq(io.in.d.bits.opcode, opcode_1) node _T_2200 = asUInt(reset) node _T_2201 = eq(_T_2200, UInt<1>(0h0)) when _T_2201 : node _T_2202 = eq(_T_2199, UInt<1>(0h0)) when _T_2202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2199, UInt<1>(0h1), "") : assert_92 node _T_2203 = eq(io.in.d.bits.param, param_1) node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : node _T_2206 = eq(_T_2203, UInt<1>(0h0)) when _T_2206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2203, UInt<1>(0h1), "") : assert_93 node _T_2207 = eq(io.in.d.bits.size, size_1) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(_T_2207, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2207, UInt<1>(0h1), "") : assert_94 node _T_2211 = eq(io.in.d.bits.source, source_1) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_95 node _T_2215 = eq(io.in.d.bits.sink, sink) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_96 node _T_2219 = eq(io.in.d.bits.denied, denied) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_97 node _T_2223 = and(io.in.d.ready, io.in.d.valid) node _T_2224 = and(_T_2223, d_first) when _T_2224 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<4104> connect a_sizes_set, UInt<4104>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2225 = and(io.in.a.valid, a_first_1) node _T_2226 = and(_T_2225, UInt<1>(0h1)) when _T_2226 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2227 = and(io.in.a.ready, io.in.a.valid) node _T_2228 = and(_T_2227, a_first_1) node _T_2229 = and(_T_2228, UInt<1>(0h1)) when _T_2229 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2230 = dshr(inflight, io.in.a.bits.source) node _T_2231 = bits(_T_2230, 0, 0) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<4104> connect d_sizes_clr, UInt<4104>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2236 = and(io.in.d.valid, d_first_1) node _T_2237 = and(_T_2236, UInt<1>(0h1)) node _T_2238 = eq(d_release_ack, UInt<1>(0h0)) node _T_2239 = and(_T_2237, _T_2238) when _T_2239 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2240 = and(io.in.d.ready, io.in.d.valid) node _T_2241 = and(_T_2240, d_first_1) node _T_2242 = and(_T_2241, UInt<1>(0h1)) node _T_2243 = eq(d_release_ack, UInt<1>(0h0)) node _T_2244 = and(_T_2242, _T_2243) when _T_2244 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2245 = and(io.in.d.valid, d_first_1) node _T_2246 = and(_T_2245, UInt<1>(0h1)) node _T_2247 = eq(d_release_ack, UInt<1>(0h0)) node _T_2248 = and(_T_2246, _T_2247) when _T_2248 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2249 = dshr(inflight, io.in.d.bits.source) node _T_2250 = bits(_T_2249, 0, 0) node _T_2251 = or(_T_2250, same_cycle_resp) node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(_T_2251, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2251, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2255 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2256 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2257 = or(_T_2255, _T_2256) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_100 node _T_2261 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_101 else : node _T_2265 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2266 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2267 = or(_T_2265, _T_2266) node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : node _T_2270 = eq(_T_2267, UInt<1>(0h0)) when _T_2270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2267, UInt<1>(0h1), "") : assert_102 node _T_2271 = eq(io.in.d.bits.size, a_size_lookup) node _T_2272 = asUInt(reset) node _T_2273 = eq(_T_2272, UInt<1>(0h0)) when _T_2273 : node _T_2274 = eq(_T_2271, UInt<1>(0h0)) when _T_2274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2271, UInt<1>(0h1), "") : assert_103 node _T_2275 = and(io.in.d.valid, d_first_1) node _T_2276 = and(_T_2275, a_first_1) node _T_2277 = and(_T_2276, io.in.a.valid) node _T_2278 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = eq(d_release_ack, UInt<1>(0h0)) node _T_2281 = and(_T_2279, _T_2280) when _T_2281 : node _T_2282 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2283 = or(_T_2282, io.in.a.ready) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_104 node _T_2287 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2288 = orr(a_set_wo_ready) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) node _T_2290 = or(_T_2287, _T_2289) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_2294 = orr(inflight) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) node _T_2296 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2297 = or(_T_2295, _T_2296) node _T_2298 = lt(watchdog, plusarg_reader.out) node _T_2299 = or(_T_2297, _T_2298) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2303 = and(io.in.a.ready, io.in.a.valid) node _T_2304 = and(io.in.d.ready, io.in.d.valid) node _T_2305 = or(_T_2303, _T_2304) when _T_2305 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<4104> connect c_sizes_set, UInt<4104>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2306 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2307 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2308 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2309 = and(_T_2307, _T_2308) node _T_2310 = and(_T_2306, _T_2309) when _T_2310 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2311 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2312 = and(_T_2311, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2313 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2314 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2315 = and(_T_2313, _T_2314) node _T_2316 = and(_T_2312, _T_2315) when _T_2316 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2317 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2318 = bits(_T_2317, 0, 0) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<4104> connect d_sizes_clr_1, UInt<4104>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2323 = and(io.in.d.valid, d_first_2) node _T_2324 = and(_T_2323, UInt<1>(0h1)) node _T_2325 = and(_T_2324, d_release_ack_1) when _T_2325 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2326 = and(io.in.d.ready, io.in.d.valid) node _T_2327 = and(_T_2326, d_first_2) node _T_2328 = and(_T_2327, UInt<1>(0h1)) node _T_2329 = and(_T_2328, d_release_ack_1) when _T_2329 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2330 = and(io.in.d.valid, d_first_2) node _T_2331 = and(_T_2330, UInt<1>(0h1)) node _T_2332 = and(_T_2331, d_release_ack_1) when _T_2332 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2333 = dshr(inflight_1, io.in.d.bits.source) node _T_2334 = bits(_T_2333, 0, 0) node _T_2335 = or(_T_2334, same_cycle_resp_1) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2339 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_109 else : node _T_2343 = eq(io.in.d.bits.size, c_size_lookup) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_110 node _T_2347 = and(io.in.d.valid, d_first_2) node _T_2348 = and(_T_2347, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2349 = and(_T_2348, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2350 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2351 = and(_T_2349, _T_2350) node _T_2352 = and(_T_2351, d_release_ack_1) node _T_2353 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2354 = and(_T_2352, _T_2353) when _T_2354 : node _T_2355 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2356 = or(_T_2355, _WIRE_27.ready) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_111 node _T_2360 = orr(c_set_wo_ready) when _T_2360 : node _T_2361 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_2365 = orr(inflight_1) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) node _T_2367 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2368 = or(_T_2366, _T_2367) node _T_2369 = lt(watchdog_1, plusarg_reader_1.out) node _T_2370 = or(_T_2368, _T_2369) node _T_2371 = asUInt(reset) node _T_2372 = eq(_T_2371, UInt<1>(0h0)) when _T_2372 : node _T_2373 = eq(_T_2370, UInt<1>(0h0)) when _T_2373 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_2370, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2374 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2375 = and(io.in.d.ready, io.in.d.valid) node _T_2376 = or(_T_2374, _T_2375) when _T_2376 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 5) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h1f)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 5) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h1f)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_24 = shr(io.in.a.bits.source, 5) node _source_ok_T_25 = eq(_source_ok_T_24, UInt<3>(0h4)) node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26) node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_30 = shr(io.in.a.bits.source, 5) node _source_ok_T_31 = eq(_source_ok_T_30, UInt<3>(0h5)) node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_36 = shr(io.in.a.bits.source, 5) node _source_ok_T_37 = eq(_source_ok_T_36, UInt<3>(0h6)) node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_42 = shr(io.in.a.bits.source, 5) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<3>(0h7)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 connect _source_ok_WIRE[4], _source_ok_T_29 connect _source_ok_WIRE[5], _source_ok_T_35 connect _source_ok_WIRE[6], _source_ok_T_41 connect _source_ok_WIRE[7], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_17 = shr(io.in.a.bits.source, 5) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_30 = shr(io.in.a.bits.source, 5) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_43 = shr(io.in.a.bits.source, 5) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_56 = shr(io.in.a.bits.source, 5) node _T_57 = eq(_T_56, UInt<3>(0h4)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_4) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<1>(0h0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_69 = shr(io.in.a.bits.source, 5) node _T_70 = eq(_T_69, UInt<3>(0h5)) node _T_71 = leq(UInt<1>(0h0), uncommonBits_5) node _T_72 = and(_T_70, _T_71) node _T_73 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = or(_T_75, _T_80) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_82 = shr(io.in.a.bits.source, 5) node _T_83 = eq(_T_82, UInt<3>(0h6)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_6) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(_T_87, UInt<1>(0h0)) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_95 = shr(io.in.a.bits.source, 5) node _T_96 = eq(_T_95, UInt<3>(0h7)) node _T_97 = leq(UInt<1>(0h0), uncommonBits_7) node _T_98 = and(_T_96, _T_97) node _T_99 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_100 = and(_T_98, _T_99) node _T_101 = eq(_T_100, UInt<1>(0h0)) node _T_102 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = or(_T_101, _T_106) node _T_108 = and(_T_16, _T_29) node _T_109 = and(_T_108, _T_42) node _T_110 = and(_T_109, _T_55) node _T_111 = and(_T_110, _T_68) node _T_112 = and(_T_111, _T_81) node _T_113 = and(_T_112, _T_94) node _T_114 = and(_T_113, _T_107) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_114, UInt<1>(0h1), "") : assert_1 node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_118 : node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_121 = and(_T_119, _T_120) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_122 = shr(io.in.a.bits.source, 5) node _T_123 = eq(_T_122, UInt<1>(0h0)) node _T_124 = leq(UInt<1>(0h0), uncommonBits_8) node _T_125 = and(_T_123, _T_124) node _T_126 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_127 = and(_T_125, _T_126) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_128 = shr(io.in.a.bits.source, 5) node _T_129 = eq(_T_128, UInt<1>(0h1)) node _T_130 = leq(UInt<1>(0h0), uncommonBits_9) node _T_131 = and(_T_129, _T_130) node _T_132 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_133 = and(_T_131, _T_132) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_134 = shr(io.in.a.bits.source, 5) node _T_135 = eq(_T_134, UInt<2>(0h2)) node _T_136 = leq(UInt<1>(0h0), uncommonBits_10) node _T_137 = and(_T_135, _T_136) node _T_138 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_139 = and(_T_137, _T_138) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<2>(0h3)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_11) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0) node _T_146 = shr(io.in.a.bits.source, 5) node _T_147 = eq(_T_146, UInt<3>(0h4)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_12) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_12, UInt<5>(0h1f)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<3>(0h5)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_13) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_13, UInt<5>(0h1f)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_158 = shr(io.in.a.bits.source, 5) node _T_159 = eq(_T_158, UInt<3>(0h6)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_14) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_163 = and(_T_161, _T_162) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_164 = shr(io.in.a.bits.source, 5) node _T_165 = eq(_T_164, UInt<3>(0h7)) node _T_166 = leq(UInt<1>(0h0), uncommonBits_15) node _T_167 = and(_T_165, _T_166) node _T_168 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(_T_127, _T_133) node _T_171 = or(_T_170, _T_139) node _T_172 = or(_T_171, _T_145) node _T_173 = or(_T_172, _T_151) node _T_174 = or(_T_173, _T_157) node _T_175 = or(_T_174, _T_163) node _T_176 = or(_T_175, _T_169) node _T_177 = and(_T_121, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<14>(0h2000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_191 = cvt(_T_190) node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000))) node _T_193 = asSInt(_T_192) node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0))) node _T_195 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<18>(0h2f000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_201 = cvt(_T_200) node _T_202 = and(_T_201, asSInt(UInt<17>(0h10000))) node _T_203 = asSInt(_T_202) node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<27>(0h4000000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<19>(0h40000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = or(_T_184, _T_189) node _T_226 = or(_T_225, _T_194) node _T_227 = or(_T_226, _T_199) node _T_228 = or(_T_227, _T_204) node _T_229 = or(_T_228, _T_209) node _T_230 = or(_T_229, _T_214) node _T_231 = or(_T_230, _T_219) node _T_232 = or(_T_231, _T_224) node _T_233 = and(_T_179, _T_232) node _T_234 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_235 = or(UInt<1>(0h0), _T_234) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<29>(0h10000000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_240, _T_245) node _T_247 = and(_T_235, _T_246) node _T_248 = or(UInt<1>(0h0), _T_233) node _T_249 = or(_T_248, _T_247) node _T_250 = and(_T_178, _T_249) node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(_T_250, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_250, UInt<1>(0h1), "") : assert_2 node _T_254 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_255 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_256 = and(_T_254, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<14>(0h2000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<13>(0h1000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<17>(0h10000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<18>(0h2f000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<17>(0h10000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<27>(0h4000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<19>(0h40000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_262, _T_267) node _T_314 = or(_T_313, _T_272) node _T_315 = or(_T_314, _T_277) node _T_316 = or(_T_315, _T_282) node _T_317 = or(_T_316, _T_287) node _T_318 = or(_T_317, _T_292) node _T_319 = or(_T_318, _T_297) node _T_320 = or(_T_319, _T_302) node _T_321 = or(_T_320, _T_307) node _T_322 = or(_T_321, _T_312) node _T_323 = and(_T_257, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = and(UInt<1>(0h0), _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_325, UInt<1>(0h1), "") : assert_3 node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(source_ok, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_332 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_332, UInt<1>(0h1), "") : assert_5 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(is_aligned, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_339 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_339, UInt<1>(0h1), "") : assert_7 node _T_343 = not(io.in.a.bits.mask) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_344, UInt<1>(0h1), "") : assert_8 node _T_348 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_348, UInt<1>(0h1), "") : assert_9 node _T_352 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_352 : node _T_353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_354 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_355 = and(_T_353, _T_354) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_356 = shr(io.in.a.bits.source, 5) node _T_357 = eq(_T_356, UInt<1>(0h0)) node _T_358 = leq(UInt<1>(0h0), uncommonBits_16) node _T_359 = and(_T_357, _T_358) node _T_360 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_361 = and(_T_359, _T_360) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_362 = shr(io.in.a.bits.source, 5) node _T_363 = eq(_T_362, UInt<1>(0h1)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_367 = and(_T_365, _T_366) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_368 = shr(io.in.a.bits.source, 5) node _T_369 = eq(_T_368, UInt<2>(0h2)) node _T_370 = leq(UInt<1>(0h0), uncommonBits_18) node _T_371 = and(_T_369, _T_370) node _T_372 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<2>(0h3)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_19) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_380 = shr(io.in.a.bits.source, 5) node _T_381 = eq(_T_380, UInt<3>(0h4)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_20) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_386 = shr(io.in.a.bits.source, 5) node _T_387 = eq(_T_386, UInt<3>(0h5)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_21) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_392 = shr(io.in.a.bits.source, 5) node _T_393 = eq(_T_392, UInt<3>(0h6)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_22) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_398 = shr(io.in.a.bits.source, 5) node _T_399 = eq(_T_398, UInt<3>(0h7)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_23) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(_T_361, _T_367) node _T_405 = or(_T_404, _T_373) node _T_406 = or(_T_405, _T_379) node _T_407 = or(_T_406, _T_385) node _T_408 = or(_T_407, _T_391) node _T_409 = or(_T_408, _T_397) node _T_410 = or(_T_409, _T_403) node _T_411 = and(_T_355, _T_410) node _T_412 = or(UInt<1>(0h0), _T_411) node _T_413 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<19>(0h40000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = or(_T_418, _T_423) node _T_460 = or(_T_459, _T_428) node _T_461 = or(_T_460, _T_433) node _T_462 = or(_T_461, _T_438) node _T_463 = or(_T_462, _T_443) node _T_464 = or(_T_463, _T_448) node _T_465 = or(_T_464, _T_453) node _T_466 = or(_T_465, _T_458) node _T_467 = and(_T_413, _T_466) node _T_468 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_469 = or(UInt<1>(0h0), _T_468) node _T_470 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<17>(0h10000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<29>(0h10000000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = or(_T_474, _T_479) node _T_481 = and(_T_469, _T_480) node _T_482 = or(UInt<1>(0h0), _T_467) node _T_483 = or(_T_482, _T_481) node _T_484 = and(_T_412, _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_484, UInt<1>(0h1), "") : assert_10 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<14>(0h2000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<17>(0h10000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<19>(0h40000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<29>(0h10000000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = or(_T_496, _T_501) node _T_548 = or(_T_547, _T_506) node _T_549 = or(_T_548, _T_511) node _T_550 = or(_T_549, _T_516) node _T_551 = or(_T_550, _T_521) node _T_552 = or(_T_551, _T_526) node _T_553 = or(_T_552, _T_531) node _T_554 = or(_T_553, _T_536) node _T_555 = or(_T_554, _T_541) node _T_556 = or(_T_555, _T_546) node _T_557 = and(_T_491, _T_556) node _T_558 = or(UInt<1>(0h0), _T_557) node _T_559 = and(UInt<1>(0h0), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_559, UInt<1>(0h1), "") : assert_11 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_566 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_566, UInt<1>(0h1), "") : assert_13 node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(is_aligned, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_573 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_573, UInt<1>(0h1), "") : assert_15 node _T_577 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_577, UInt<1>(0h1), "") : assert_16 node _T_581 = not(io.in.a.bits.mask) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_582, UInt<1>(0h1), "") : assert_17 node _T_586 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_586, UInt<1>(0h1), "") : assert_18 node _T_590 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_590 : node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0) node _T_594 = shr(io.in.a.bits.source, 5) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_24) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_24, UInt<5>(0h1f)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0) node _T_600 = shr(io.in.a.bits.source, 5) node _T_601 = eq(_T_600, UInt<1>(0h1)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_25) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_25, UInt<5>(0h1f)) node _T_605 = and(_T_603, _T_604) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0) node _T_606 = shr(io.in.a.bits.source, 5) node _T_607 = eq(_T_606, UInt<2>(0h2)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_26) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_26, UInt<5>(0h1f)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0) node _T_612 = shr(io.in.a.bits.source, 5) node _T_613 = eq(_T_612, UInt<2>(0h3)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_27) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_27, UInt<5>(0h1f)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_618 = shr(io.in.a.bits.source, 5) node _T_619 = eq(_T_618, UInt<3>(0h4)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_28) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_624 = shr(io.in.a.bits.source, 5) node _T_625 = eq(_T_624, UInt<3>(0h5)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_29) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_630 = shr(io.in.a.bits.source, 5) node _T_631 = eq(_T_630, UInt<3>(0h6)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_30) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_636 = shr(io.in.a.bits.source, 5) node _T_637 = eq(_T_636, UInt<3>(0h7)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_31) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_641 = and(_T_639, _T_640) node _T_642 = or(_T_599, _T_605) node _T_643 = or(_T_642, _T_611) node _T_644 = or(_T_643, _T_617) node _T_645 = or(_T_644, _T_623) node _T_646 = or(_T_645, _T_629) node _T_647 = or(_T_646, _T_635) node _T_648 = or(_T_647, _T_641) node _T_649 = and(_T_593, _T_648) node _T_650 = or(UInt<1>(0h0), _T_649) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_650, UInt<1>(0h1), "") : assert_19 node _T_654 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_655 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_656 = and(_T_654, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = and(_T_657, _T_662) node _T_664 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_665 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_666 = and(_T_664, _T_665) node _T_667 = or(UInt<1>(0h0), _T_666) node _T_668 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<14>(0h2000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<18>(0h2f000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<17>(0h10000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<13>(0h1000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<27>(0h4000000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<19>(0h40000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<29>(0h10000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = or(_T_672, _T_677) node _T_719 = or(_T_718, _T_682) node _T_720 = or(_T_719, _T_687) node _T_721 = or(_T_720, _T_692) node _T_722 = or(_T_721, _T_697) node _T_723 = or(_T_722, _T_702) node _T_724 = or(_T_723, _T_707) node _T_725 = or(_T_724, _T_712) node _T_726 = or(_T_725, _T_717) node _T_727 = and(_T_667, _T_726) node _T_728 = or(UInt<1>(0h0), _T_663) node _T_729 = or(_T_728, _T_727) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_729, UInt<1>(0h1), "") : assert_20 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(source_ok, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(is_aligned, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_739 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_739, UInt<1>(0h1), "") : assert_23 node _T_743 = eq(io.in.a.bits.mask, mask) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_743, UInt<1>(0h1), "") : assert_24 node _T_747 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_747, UInt<1>(0h1), "") : assert_25 node _T_751 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_751 : node _T_752 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_753 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_755 = shr(io.in.a.bits.source, 5) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_32) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_761 = shr(io.in.a.bits.source, 5) node _T_762 = eq(_T_761, UInt<1>(0h1)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_33) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_767 = shr(io.in.a.bits.source, 5) node _T_768 = eq(_T_767, UInt<2>(0h2)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_34) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_773 = shr(io.in.a.bits.source, 5) node _T_774 = eq(_T_773, UInt<2>(0h3)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_35) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_779 = shr(io.in.a.bits.source, 5) node _T_780 = eq(_T_779, UInt<3>(0h4)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_36) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_785 = shr(io.in.a.bits.source, 5) node _T_786 = eq(_T_785, UInt<3>(0h5)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_37) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_790 = and(_T_788, _T_789) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_791 = shr(io.in.a.bits.source, 5) node _T_792 = eq(_T_791, UInt<3>(0h6)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_38) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_797 = shr(io.in.a.bits.source, 5) node _T_798 = eq(_T_797, UInt<3>(0h7)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_39) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_802 = and(_T_800, _T_801) node _T_803 = or(_T_760, _T_766) node _T_804 = or(_T_803, _T_772) node _T_805 = or(_T_804, _T_778) node _T_806 = or(_T_805, _T_784) node _T_807 = or(_T_806, _T_790) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_802) node _T_810 = and(_T_754, _T_809) node _T_811 = or(UInt<1>(0h0), _T_810) node _T_812 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_813 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_814 = and(_T_812, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_817 = cvt(_T_816) node _T_818 = and(_T_817, asSInt(UInt<13>(0h1000))) node _T_819 = asSInt(_T_818) node _T_820 = eq(_T_819, asSInt(UInt<1>(0h0))) node _T_821 = and(_T_815, _T_820) node _T_822 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_823 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_824 = and(_T_822, _T_823) node _T_825 = or(UInt<1>(0h0), _T_824) node _T_826 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<14>(0h2000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_832 = cvt(_T_831) node _T_833 = and(_T_832, asSInt(UInt<18>(0h2f000))) node _T_834 = asSInt(_T_833) node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0))) node _T_836 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_837 = cvt(_T_836) node _T_838 = and(_T_837, asSInt(UInt<17>(0h10000))) node _T_839 = asSInt(_T_838) node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0))) node _T_841 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_842 = cvt(_T_841) node _T_843 = and(_T_842, asSInt(UInt<13>(0h1000))) node _T_844 = asSInt(_T_843) node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0))) node _T_846 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<27>(0h4000000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<19>(0h40000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<29>(0h10000000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = or(_T_830, _T_835) node _T_872 = or(_T_871, _T_840) node _T_873 = or(_T_872, _T_845) node _T_874 = or(_T_873, _T_850) node _T_875 = or(_T_874, _T_855) node _T_876 = or(_T_875, _T_860) node _T_877 = or(_T_876, _T_865) node _T_878 = or(_T_877, _T_870) node _T_879 = and(_T_825, _T_878) node _T_880 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_881 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = and(_T_880, _T_885) node _T_887 = or(UInt<1>(0h0), _T_821) node _T_888 = or(_T_887, _T_879) node _T_889 = or(_T_888, _T_886) node _T_890 = and(_T_811, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_890, UInt<1>(0h1), "") : assert_26 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_900 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_900, UInt<1>(0h1), "") : assert_29 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_904, UInt<1>(0h1), "") : assert_30 node _T_908 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_908 : node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_911 = and(_T_909, _T_910) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_912 = shr(io.in.a.bits.source, 5) node _T_913 = eq(_T_912, UInt<1>(0h0)) node _T_914 = leq(UInt<1>(0h0), uncommonBits_40) node _T_915 = and(_T_913, _T_914) node _T_916 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_917 = and(_T_915, _T_916) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_918 = shr(io.in.a.bits.source, 5) node _T_919 = eq(_T_918, UInt<1>(0h1)) node _T_920 = leq(UInt<1>(0h0), uncommonBits_41) node _T_921 = and(_T_919, _T_920) node _T_922 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_923 = and(_T_921, _T_922) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_924 = shr(io.in.a.bits.source, 5) node _T_925 = eq(_T_924, UInt<2>(0h2)) node _T_926 = leq(UInt<1>(0h0), uncommonBits_42) node _T_927 = and(_T_925, _T_926) node _T_928 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_929 = and(_T_927, _T_928) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_930 = shr(io.in.a.bits.source, 5) node _T_931 = eq(_T_930, UInt<2>(0h3)) node _T_932 = leq(UInt<1>(0h0), uncommonBits_43) node _T_933 = and(_T_931, _T_932) node _T_934 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_935 = and(_T_933, _T_934) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_936 = shr(io.in.a.bits.source, 5) node _T_937 = eq(_T_936, UInt<3>(0h4)) node _T_938 = leq(UInt<1>(0h0), uncommonBits_44) node _T_939 = and(_T_937, _T_938) node _T_940 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_941 = and(_T_939, _T_940) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_942 = shr(io.in.a.bits.source, 5) node _T_943 = eq(_T_942, UInt<3>(0h5)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_45) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_948 = shr(io.in.a.bits.source, 5) node _T_949 = eq(_T_948, UInt<3>(0h6)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_46) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_954 = shr(io.in.a.bits.source, 5) node _T_955 = eq(_T_954, UInt<3>(0h7)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_47) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_959 = and(_T_957, _T_958) node _T_960 = or(_T_917, _T_923) node _T_961 = or(_T_960, _T_929) node _T_962 = or(_T_961, _T_935) node _T_963 = or(_T_962, _T_941) node _T_964 = or(_T_963, _T_947) node _T_965 = or(_T_964, _T_953) node _T_966 = or(_T_965, _T_959) node _T_967 = and(_T_911, _T_966) node _T_968 = or(UInt<1>(0h0), _T_967) node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_971 = and(_T_969, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<13>(0h1000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = and(_T_972, _T_977) node _T_979 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_980 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_981 = and(_T_979, _T_980) node _T_982 = or(UInt<1>(0h0), _T_981) node _T_983 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<14>(0h2000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_989 = cvt(_T_988) node _T_990 = and(_T_989, asSInt(UInt<18>(0h2f000))) node _T_991 = asSInt(_T_990) node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0))) node _T_993 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_994 = cvt(_T_993) node _T_995 = and(_T_994, asSInt(UInt<17>(0h10000))) node _T_996 = asSInt(_T_995) node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0))) node _T_998 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1004 = cvt(_T_1003) node _T_1005 = and(_T_1004, asSInt(UInt<17>(0h10000))) node _T_1006 = asSInt(_T_1005) node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0))) node _T_1008 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<27>(0h4000000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<19>(0h40000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<29>(0h10000000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = or(_T_987, _T_992) node _T_1029 = or(_T_1028, _T_997) node _T_1030 = or(_T_1029, _T_1002) node _T_1031 = or(_T_1030, _T_1007) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1017) node _T_1034 = or(_T_1033, _T_1022) node _T_1035 = or(_T_1034, _T_1027) node _T_1036 = and(_T_982, _T_1035) node _T_1037 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1038 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<17>(0h10000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = and(_T_1037, _T_1042) node _T_1044 = or(UInt<1>(0h0), _T_978) node _T_1045 = or(_T_1044, _T_1036) node _T_1046 = or(_T_1045, _T_1043) node _T_1047 = and(_T_968, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_31 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1057 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_34 node _T_1061 = not(mask) node _T_1062 = and(io.in.a.bits.mask, _T_1061) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_35 node _T_1067 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1067 : node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1070 = and(_T_1068, _T_1069) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0) node _T_1071 = shr(io.in.a.bits.source, 5) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1074 = and(_T_1072, _T_1073) node _T_1075 = leq(uncommonBits_48, UInt<5>(0h1f)) node _T_1076 = and(_T_1074, _T_1075) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0) node _T_1077 = shr(io.in.a.bits.source, 5) node _T_1078 = eq(_T_1077, UInt<1>(0h1)) node _T_1079 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = leq(uncommonBits_49, UInt<5>(0h1f)) node _T_1082 = and(_T_1080, _T_1081) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_1083 = shr(io.in.a.bits.source, 5) node _T_1084 = eq(_T_1083, UInt<2>(0h2)) node _T_1085 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_1088 = and(_T_1086, _T_1087) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_1089 = shr(io.in.a.bits.source, 5) node _T_1090 = eq(_T_1089, UInt<2>(0h3)) node _T_1091 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_1094 = and(_T_1092, _T_1093) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_1095 = shr(io.in.a.bits.source, 5) node _T_1096 = eq(_T_1095, UInt<3>(0h4)) node _T_1097 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1098 = and(_T_1096, _T_1097) node _T_1099 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_1100 = and(_T_1098, _T_1099) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_1101 = shr(io.in.a.bits.source, 5) node _T_1102 = eq(_T_1101, UInt<3>(0h5)) node _T_1103 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1104 = and(_T_1102, _T_1103) node _T_1105 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_1106 = and(_T_1104, _T_1105) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_1107 = shr(io.in.a.bits.source, 5) node _T_1108 = eq(_T_1107, UInt<3>(0h6)) node _T_1109 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_1112 = and(_T_1110, _T_1111) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_1113 = shr(io.in.a.bits.source, 5) node _T_1114 = eq(_T_1113, UInt<3>(0h7)) node _T_1115 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = or(_T_1076, _T_1082) node _T_1120 = or(_T_1119, _T_1088) node _T_1121 = or(_T_1120, _T_1094) node _T_1122 = or(_T_1121, _T_1100) node _T_1123 = or(_T_1122, _T_1106) node _T_1124 = or(_T_1123, _T_1112) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = and(_T_1070, _T_1125) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1129 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = or(UInt<1>(0h0), _T_1130) node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<14>(0h2000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<17>(0h10000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<27>(0h4000000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<19>(0h40000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<29>(0h10000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = or(_T_1136, _T_1141) node _T_1183 = or(_T_1182, _T_1146) node _T_1184 = or(_T_1183, _T_1151) node _T_1185 = or(_T_1184, _T_1156) node _T_1186 = or(_T_1185, _T_1161) node _T_1187 = or(_T_1186, _T_1166) node _T_1188 = or(_T_1187, _T_1171) node _T_1189 = or(_T_1188, _T_1176) node _T_1190 = or(_T_1189, _T_1181) node _T_1191 = and(_T_1131, _T_1190) node _T_1192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<17>(0h10000))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = and(_T_1192, _T_1197) node _T_1199 = or(UInt<1>(0h0), _T_1191) node _T_1200 = or(_T_1199, _T_1198) node _T_1201 = and(_T_1127, _T_1200) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_36 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(source_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(is_aligned, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1211 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_39 node _T_1215 = eq(io.in.a.bits.mask, mask) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_40 node _T_1219 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1219 : node _T_1220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1222 = and(_T_1220, _T_1221) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_1223 = shr(io.in.a.bits.source, 5) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) node _T_1225 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_1228 = and(_T_1226, _T_1227) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_1229 = shr(io.in.a.bits.source, 5) node _T_1230 = eq(_T_1229, UInt<1>(0h1)) node _T_1231 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1232 = and(_T_1230, _T_1231) node _T_1233 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_1234 = and(_T_1232, _T_1233) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_1235 = shr(io.in.a.bits.source, 5) node _T_1236 = eq(_T_1235, UInt<2>(0h2)) node _T_1237 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1238 = and(_T_1236, _T_1237) node _T_1239 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_1240 = and(_T_1238, _T_1239) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_1241 = shr(io.in.a.bits.source, 5) node _T_1242 = eq(_T_1241, UInt<2>(0h3)) node _T_1243 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1244 = and(_T_1242, _T_1243) node _T_1245 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_1246 = and(_T_1244, _T_1245) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_1247 = shr(io.in.a.bits.source, 5) node _T_1248 = eq(_T_1247, UInt<3>(0h4)) node _T_1249 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1250 = and(_T_1248, _T_1249) node _T_1251 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_1252 = and(_T_1250, _T_1251) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_1253 = shr(io.in.a.bits.source, 5) node _T_1254 = eq(_T_1253, UInt<3>(0h5)) node _T_1255 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1256 = and(_T_1254, _T_1255) node _T_1257 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_1258 = and(_T_1256, _T_1257) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_1259 = shr(io.in.a.bits.source, 5) node _T_1260 = eq(_T_1259, UInt<3>(0h6)) node _T_1261 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_1264 = and(_T_1262, _T_1263) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_1265 = shr(io.in.a.bits.source, 5) node _T_1266 = eq(_T_1265, UInt<3>(0h7)) node _T_1267 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = or(_T_1228, _T_1234) node _T_1272 = or(_T_1271, _T_1240) node _T_1273 = or(_T_1272, _T_1246) node _T_1274 = or(_T_1273, _T_1252) node _T_1275 = or(_T_1274, _T_1258) node _T_1276 = or(_T_1275, _T_1264) node _T_1277 = or(_T_1276, _T_1270) node _T_1278 = and(_T_1222, _T_1277) node _T_1279 = or(UInt<1>(0h0), _T_1278) node _T_1280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1281 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1285 = cvt(_T_1284) node _T_1286 = and(_T_1285, asSInt(UInt<14>(0h2000))) node _T_1287 = asSInt(_T_1286) node _T_1288 = eq(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1290 = cvt(_T_1289) node _T_1291 = and(_T_1290, asSInt(UInt<13>(0h1000))) node _T_1292 = asSInt(_T_1291) node _T_1293 = eq(_T_1292, asSInt(UInt<1>(0h0))) node _T_1294 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<18>(0h2f000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1300 = cvt(_T_1299) node _T_1301 = and(_T_1300, asSInt(UInt<17>(0h10000))) node _T_1302 = asSInt(_T_1301) node _T_1303 = eq(_T_1302, asSInt(UInt<1>(0h0))) node _T_1304 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1305 = cvt(_T_1304) node _T_1306 = and(_T_1305, asSInt(UInt<13>(0h1000))) node _T_1307 = asSInt(_T_1306) node _T_1308 = eq(_T_1307, asSInt(UInt<1>(0h0))) node _T_1309 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1310 = cvt(_T_1309) node _T_1311 = and(_T_1310, asSInt(UInt<17>(0h10000))) node _T_1312 = asSInt(_T_1311) node _T_1313 = eq(_T_1312, asSInt(UInt<1>(0h0))) node _T_1314 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<27>(0h4000000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<19>(0h40000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<29>(0h10000000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = or(_T_1288, _T_1293) node _T_1335 = or(_T_1334, _T_1298) node _T_1336 = or(_T_1335, _T_1303) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1313) node _T_1339 = or(_T_1338, _T_1318) node _T_1340 = or(_T_1339, _T_1323) node _T_1341 = or(_T_1340, _T_1328) node _T_1342 = or(_T_1341, _T_1333) node _T_1343 = and(_T_1283, _T_1342) node _T_1344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<17>(0h10000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = and(_T_1344, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1343) node _T_1352 = or(_T_1351, _T_1350) node _T_1353 = and(_T_1279, _T_1352) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_41 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1363 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_44 node _T_1367 = eq(io.in.a.bits.mask, mask) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_45 node _T_1371 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1371 : node _T_1372 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1373 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1374 = and(_T_1372, _T_1373) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_1375 = shr(io.in.a.bits.source, 5) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_1381 = shr(io.in.a.bits.source, 5) node _T_1382 = eq(_T_1381, UInt<1>(0h1)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_1386 = and(_T_1384, _T_1385) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_1387 = shr(io.in.a.bits.source, 5) node _T_1388 = eq(_T_1387, UInt<2>(0h2)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_1393 = shr(io.in.a.bits.source, 5) node _T_1394 = eq(_T_1393, UInt<2>(0h3)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_1399 = shr(io.in.a.bits.source, 5) node _T_1400 = eq(_T_1399, UInt<3>(0h4)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_1405 = shr(io.in.a.bits.source, 5) node _T_1406 = eq(_T_1405, UInt<3>(0h5)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1410 = and(_T_1408, _T_1409) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1411 = shr(io.in.a.bits.source, 5) node _T_1412 = eq(_T_1411, UInt<3>(0h6)) node _T_1413 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1416 = and(_T_1414, _T_1415) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1417 = shr(io.in.a.bits.source, 5) node _T_1418 = eq(_T_1417, UInt<3>(0h7)) node _T_1419 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1422 = and(_T_1420, _T_1421) node _T_1423 = or(_T_1380, _T_1386) node _T_1424 = or(_T_1423, _T_1392) node _T_1425 = or(_T_1424, _T_1398) node _T_1426 = or(_T_1425, _T_1404) node _T_1427 = or(_T_1426, _T_1410) node _T_1428 = or(_T_1427, _T_1416) node _T_1429 = or(_T_1428, _T_1422) node _T_1430 = and(_T_1374, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1433 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = and(_T_1435, _T_1440) node _T_1442 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1443 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<14>(0h2000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<17>(0h10000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1454 = cvt(_T_1453) node _T_1455 = and(_T_1454, asSInt(UInt<18>(0h2f000))) node _T_1456 = asSInt(_T_1455) node _T_1457 = eq(_T_1456, asSInt(UInt<1>(0h0))) node _T_1458 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1459 = cvt(_T_1458) node _T_1460 = and(_T_1459, asSInt(UInt<17>(0h10000))) node _T_1461 = asSInt(_T_1460) node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) node _T_1463 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1464 = cvt(_T_1463) node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) node _T_1466 = asSInt(_T_1465) node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) node _T_1468 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1469 = cvt(_T_1468) node _T_1470 = and(_T_1469, asSInt(UInt<27>(0h4000000))) node _T_1471 = asSInt(_T_1470) node _T_1472 = eq(_T_1471, asSInt(UInt<1>(0h0))) node _T_1473 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1474 = cvt(_T_1473) node _T_1475 = and(_T_1474, asSInt(UInt<13>(0h1000))) node _T_1476 = asSInt(_T_1475) node _T_1477 = eq(_T_1476, asSInt(UInt<1>(0h0))) node _T_1478 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1479 = cvt(_T_1478) node _T_1480 = and(_T_1479, asSInt(UInt<19>(0h40000))) node _T_1481 = asSInt(_T_1480) node _T_1482 = eq(_T_1481, asSInt(UInt<1>(0h0))) node _T_1483 = or(_T_1447, _T_1452) node _T_1484 = or(_T_1483, _T_1457) node _T_1485 = or(_T_1484, _T_1462) node _T_1486 = or(_T_1485, _T_1467) node _T_1487 = or(_T_1486, _T_1472) node _T_1488 = or(_T_1487, _T_1477) node _T_1489 = or(_T_1488, _T_1482) node _T_1490 = and(_T_1442, _T_1489) node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h10000))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h10000000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1441) node _T_1508 = or(_T_1507, _T_1490) node _T_1509 = or(_T_1508, _T_1506) node _T_1510 = and(_T_1431, _T_1509) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_46 node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(source_ok, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(is_aligned, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1520 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_49 node _T_1524 = eq(io.in.a.bits.mask, mask) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_50 node _T_1528 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1532 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 5) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<1>(0h0)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 5) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<1>(0h1)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 5) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<2>(0h2)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 5) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<2>(0h3)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 5) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<3>(0h4)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h1f)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 5) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<3>(0h5)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h1f)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 5) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<3>(0h6)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_96 = shr(io.in.d.bits.source, 5) node _source_ok_T_97 = eq(_source_ok_T_96, UInt<3>(0h7)) node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98) node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_59 connect _source_ok_WIRE_1[1], _source_ok_T_65 connect _source_ok_WIRE_1[2], _source_ok_T_71 connect _source_ok_WIRE_1[3], _source_ok_T_77 connect _source_ok_WIRE_1[4], _source_ok_T_83 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_95 connect _source_ok_WIRE_1[7], _source_ok_T_101 node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1536 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1536 : node _T_1537 = asUInt(reset) node _T_1538 = eq(_T_1537, UInt<1>(0h0)) when _T_1538 : node _T_1539 = eq(source_ok_1, UInt<1>(0h0)) when _T_1539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1540 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(_T_1540, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1540, UInt<1>(0h1), "") : assert_54 node _T_1544 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_55 node _T_1548 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_56 node _T_1552 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_57 node _T_1556 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1556 : node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(source_ok_1, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(sink_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1563 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_60 node _T_1567 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_61 node _T_1571 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_62 node _T_1575 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_63 node _T_1579 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1580 = or(UInt<1>(0h1), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_64 node _T_1584 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1584 : node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(source_ok_1, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(sink_ok, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1591 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_67 node _T_1595 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_68 node _T_1599 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_69 node _T_1603 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1604 = or(_T_1603, io.in.d.bits.corrupt) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_70 node _T_1608 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1609 = or(UInt<1>(0h1), _T_1608) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_71 node _T_1613 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1613 : node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(source_ok_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1617 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_73 node _T_1621 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_74 node _T_1625 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1626 = or(UInt<1>(0h1), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_75 node _T_1630 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1630 : node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(source_ok_1, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1634 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(_T_1634, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1634, UInt<1>(0h1), "") : assert_77 node _T_1638 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1639 = or(_T_1638, io.in.d.bits.corrupt) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_78 node _T_1643 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1644 = or(UInt<1>(0h1), _T_1643) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_79 node _T_1648 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1648 : node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(source_ok_1, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1652 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(_T_1652, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1652, UInt<1>(0h1), "") : assert_81 node _T_1656 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_82 node _T_1660 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1661 = or(UInt<1>(0h1), _T_1660) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1665 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1669 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1673 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1677 = eq(a_first, UInt<1>(0h0)) node _T_1678 = and(io.in.a.valid, _T_1677) when _T_1678 : node _T_1679 = eq(io.in.a.bits.opcode, opcode) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_87 node _T_1683 = eq(io.in.a.bits.param, param) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_88 node _T_1687 = eq(io.in.a.bits.size, size) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_89 node _T_1691 = eq(io.in.a.bits.source, source) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_90 node _T_1695 = eq(io.in.a.bits.address, address) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_91 node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first) when _T_1700 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1701 = eq(d_first, UInt<1>(0h0)) node _T_1702 = and(io.in.d.valid, _T_1701) when _T_1702 : node _T_1703 = eq(io.in.d.bits.opcode, opcode_1) node _T_1704 = asUInt(reset) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) when _T_1705 : node _T_1706 = eq(_T_1703, UInt<1>(0h0)) when _T_1706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1703, UInt<1>(0h1), "") : assert_92 node _T_1707 = eq(io.in.d.bits.param, param_1) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_93 node _T_1711 = eq(io.in.d.bits.size, size_1) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_94 node _T_1715 = eq(io.in.d.bits.source, source_1) node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(_T_1715, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1715, UInt<1>(0h1), "") : assert_95 node _T_1719 = eq(io.in.d.bits.sink, sink) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_96 node _T_1723 = eq(io.in.d.bits.denied, denied) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_97 node _T_1727 = and(io.in.d.ready, io.in.d.valid) node _T_1728 = and(_T_1727, d_first) when _T_1728 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes : UInt<2048>, clock, reset, UInt<2048>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<256> connect a_set, UInt<256>(0h0) wire a_set_wo_ready : UInt<256> connect a_set_wo_ready, UInt<256>(0h0) wire a_opcodes_set : UInt<1024> connect a_opcodes_set, UInt<1024>(0h0) wire a_sizes_set : UInt<2048> connect a_sizes_set, UInt<2048>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1729 = and(io.in.a.valid, a_first_1) node _T_1730 = and(_T_1729, UInt<1>(0h1)) when _T_1730 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1731 = and(io.in.a.ready, io.in.a.valid) node _T_1732 = and(_T_1731, a_first_1) node _T_1733 = and(_T_1732, UInt<1>(0h1)) when _T_1733 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1734 = dshr(inflight, io.in.a.bits.source) node _T_1735 = bits(_T_1734, 0, 0) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<256> connect d_clr, UInt<256>(0h0) wire d_clr_wo_ready : UInt<256> connect d_clr_wo_ready, UInt<256>(0h0) wire d_opcodes_clr : UInt<1024> connect d_opcodes_clr, UInt<1024>(0h0) wire d_sizes_clr : UInt<2048> connect d_sizes_clr, UInt<2048>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1740 = and(io.in.d.valid, d_first_1) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = eq(d_release_ack, UInt<1>(0h0)) node _T_1743 = and(_T_1741, _T_1742) when _T_1743 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1744 = and(io.in.d.ready, io.in.d.valid) node _T_1745 = and(_T_1744, d_first_1) node _T_1746 = and(_T_1745, UInt<1>(0h1)) node _T_1747 = eq(d_release_ack, UInt<1>(0h0)) node _T_1748 = and(_T_1746, _T_1747) when _T_1748 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1749 = and(io.in.d.valid, d_first_1) node _T_1750 = and(_T_1749, UInt<1>(0h1)) node _T_1751 = eq(d_release_ack, UInt<1>(0h0)) node _T_1752 = and(_T_1750, _T_1751) when _T_1752 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1753 = dshr(inflight, io.in.d.bits.source) node _T_1754 = bits(_T_1753, 0, 0) node _T_1755 = or(_T_1754, same_cycle_resp) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1759 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1760 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = asUInt(reset) node _T_1763 = eq(_T_1762, UInt<1>(0h0)) when _T_1763 : node _T_1764 = eq(_T_1761, UInt<1>(0h0)) when _T_1764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1761, UInt<1>(0h1), "") : assert_100 node _T_1765 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_101 else : node _T_1769 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1770 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_102 node _T_1775 = eq(io.in.d.bits.size, a_size_lookup) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_103 node _T_1779 = and(io.in.d.valid, d_first_1) node _T_1780 = and(_T_1779, a_first_1) node _T_1781 = and(_T_1780, io.in.a.valid) node _T_1782 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1783 = and(_T_1781, _T_1782) node _T_1784 = eq(d_release_ack, UInt<1>(0h0)) node _T_1785 = and(_T_1783, _T_1784) when _T_1785 : node _T_1786 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1787 = or(_T_1786, io.in.a.ready) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_104 node _T_1791 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1792 = orr(a_set_wo_ready) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = or(_T_1791, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_131 node _T_1798 = orr(inflight) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1801 = or(_T_1799, _T_1800) node _T_1802 = lt(watchdog, plusarg_reader.out) node _T_1803 = or(_T_1801, _T_1802) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1807 = and(io.in.a.ready, io.in.a.valid) node _T_1808 = and(io.in.d.ready, io.in.d.valid) node _T_1809 = or(_T_1807, _T_1808) when _T_1809 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes_1 : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes_1 : UInt<2048>, clock, reset, UInt<2048>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<256> connect c_set, UInt<256>(0h0) wire c_set_wo_ready : UInt<256> connect c_set_wo_ready, UInt<256>(0h0) wire c_opcodes_set : UInt<1024> connect c_opcodes_set, UInt<1024>(0h0) wire c_sizes_set : UInt<2048> connect c_sizes_set, UInt<2048>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1810 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1811 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1812 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1813 = and(_T_1811, _T_1812) node _T_1814 = and(_T_1810, _T_1813) when _T_1814 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1815 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1816 = and(_T_1815, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1817 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1818 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = and(_T_1816, _T_1819) when _T_1820 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1821 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1822 = bits(_T_1821, 0, 0) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(_T_1823, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1823, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<256> connect d_clr_1, UInt<256>(0h0) wire d_clr_wo_ready_1 : UInt<256> connect d_clr_wo_ready_1, UInt<256>(0h0) wire d_opcodes_clr_1 : UInt<1024> connect d_opcodes_clr_1, UInt<1024>(0h0) wire d_sizes_clr_1 : UInt<2048> connect d_sizes_clr_1, UInt<2048>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1827 = and(io.in.d.valid, d_first_2) node _T_1828 = and(_T_1827, UInt<1>(0h1)) node _T_1829 = and(_T_1828, d_release_ack_1) when _T_1829 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1830 = and(io.in.d.ready, io.in.d.valid) node _T_1831 = and(_T_1830, d_first_2) node _T_1832 = and(_T_1831, UInt<1>(0h1)) node _T_1833 = and(_T_1832, d_release_ack_1) when _T_1833 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1834 = and(io.in.d.valid, d_first_2) node _T_1835 = and(_T_1834, UInt<1>(0h1)) node _T_1836 = and(_T_1835, d_release_ack_1) when _T_1836 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1837 = dshr(inflight_1, io.in.d.bits.source) node _T_1838 = bits(_T_1837, 0, 0) node _T_1839 = or(_T_1838, same_cycle_resp_1) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1843 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_109 else : node _T_1847 = eq(io.in.d.bits.size, c_size_lookup) node _T_1848 = asUInt(reset) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) when _T_1849 : node _T_1850 = eq(_T_1847, UInt<1>(0h0)) when _T_1850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1847, UInt<1>(0h1), "") : assert_110 node _T_1851 = and(io.in.d.valid, d_first_2) node _T_1852 = and(_T_1851, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1853 = and(_T_1852, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1854 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1855 = and(_T_1853, _T_1854) node _T_1856 = and(_T_1855, d_release_ack_1) node _T_1857 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1858 = and(_T_1856, _T_1857) when _T_1858 : node _T_1859 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1860 = or(_T_1859, _WIRE_23.ready) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_111 node _T_1864 = orr(c_set_wo_ready) when _T_1864 : node _T_1865 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_132 node _T_1869 = orr(inflight_1) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) node _T_1871 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1872 = or(_T_1870, _T_1871) node _T_1873 = lt(watchdog_1, plusarg_reader_1.out) node _T_1874 = or(_T_1872, _T_1873) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/nvdla/src/main/scala/devices/nvdla/NVDLA.scala:44:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1878 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1879 = and(io.in.d.ready, io.in.d.valid) node _T_1880 = or(_T_1878, _T_1879) when _T_1880 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [255:0] inflight; // @[Monitor.scala:614:27] reg [1023:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2047:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [255:0] inflight_1; // @[Monitor.scala:726:35] reg [2047:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T

module MulAddRecFNToRaw_postMul_e8_s24( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire roundingMode_min = io_roundingMode == 3'h2; // @[MulAddRecFN.scala:186:45] wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:190:42] wire [25:0] _sigSum_T_3 = io_mulAddResult[48] ? io_fromPreMul_highAlignedSigC + 26'h1 : io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:192:{16,32}, :193:47] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[47:24]} : {1'h0, io_fromPreMul_highAlignedSigC[25:24], _sigSum_T_3[23:0], io_mulAddResult[47:25]}; // @[MulAddRecFN.scala:192:16, :205:12, :206:{13,20}, :209:{46,71}, :210:23] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:205:12, :219:24] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2])); // @[primitives.scala:52:21, :76:56] wire [50:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + {50'h0, io_fromPreMul_doSubMags}; // @[MulAddRecFN.scala:192:16, :196:28, :232:36, :234:12, :235:{13,20}, :236:41] wire [4:0] notCDom_normDistReduced2 = notCDom_absSigSum[50] ? 5'h0 : (|(notCDom_absSigSum[49:48])) ? 5'h1 : (|(notCDom_absSigSum[47:46])) ? 5'h2 : (|(notCDom_absSigSum[45:44])) ? 5'h3 : (|(notCDom_absSigSum[43:42])) ? 5'h4 : (|(notCDom_absSigSum[41:40])) ? 5'h5 : (|(notCDom_absSigSum[39:38])) ? 5'h6 : (|(notCDom_absSigSum[37:36])) ? 5'h7 : (|(notCDom_absSigSum[35:34])) ? 5'h8 : (|(notCDom_absSigSum[33:32])) ? 5'h9 : (|(notCDom_absSigSum[31:30])) ? 5'hA : (|(notCDom_absSigSum[29:28])) ? 5'hB : (|(notCDom_absSigSum[27:26])) ? 5'hC : (|(notCDom_absSigSum[25:24])) ? 5'hD : (|(notCDom_absSigSum[23:22])) ? 5'hE : (|(notCDom_absSigSum[21:20])) ? 5'hF : (|(notCDom_absSigSum[19:18])) ? 5'h10 : (|(notCDom_absSigSum[17:16])) ? 5'h11 : (|(notCDom_absSigSum[15:14])) ? 5'h12 : (|(notCDom_absSigSum[13:12])) ? 5'h13 : (|(notCDom_absSigSum[11:10])) ? 5'h14 : (|(notCDom_absSigSum[9:8])) ? 5'h15 : (|(notCDom_absSigSum[7:6])) ? 5'h16 : (|(notCDom_absSigSum[5:4])) ? 5'h17 : {4'hC, ~(|(notCDom_absSigSum[3:2]))}; // @[Mux.scala:50:70] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1])); // @[Mux.scala:50:70] wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0; // @[primitives.scala:103:54] wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; // @[MulAddRecFN.scala:264:49] wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; // @[MulAddRecFN.scala:264:49, :265:44] wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:267:{32,58}] assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7, :264:49, :271:35, :272:{31,57}, :273:{32,57}, :274:{10,36}, :275:61, :276:35] assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isInf = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; // @[MulAddRecFN.scala:169:7, :255:50, :267:58, :282:25, :283:{14,42}] assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]); // @[MulAddRecFN.scala:169:7, :186:45, :190:42, :192:16, :232:36, :255:50, :257:12, :259:36, :264:49, :265:44, :267:58, :285:{27,54}, :286:{31,43}, :287:{26,29,48}, :288:{36,48}, :289:{26,46}, :290:{37,50}, :291:{10,28,31,49}, :292:17] assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[49:24], (|{_CDom_mainSig_T[23:21], {|(CDom_absSigSum[20:17]), |(CDom_absSigSum[16:13]), |(CDom_absSigSum[12:9]), |(CDom_absSigSum[8:5]), |(CDom_absSigSum[4:1]), CDom_absSigSum[0]} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[23:0] != 24'hFFFFFF : (|(io_mulAddResult[24:0])))} : {_notCDom_mainSig_T[51:26], |{_notCDom_mainSig_T[25:23], {|{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6]}}}; // @[primitives.scala:76:56, :77:20, :78:22, :103:{33,54}, :120:{33,54}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_13 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_13( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_57 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_57( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module PE_443 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_187 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_443( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_187 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_3 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_3( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControlRemapper_2 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn

module ReRoCCManagerControlRemapper_2( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_109 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_109( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_147 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_162 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_147( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_162 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TageBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 3) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 3) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire f3_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} node _T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node lo = cat(_T_1, _T) node hi = cat(_T_3, _T_2) node _T_4 = cat(hi, lo) node lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _T_5 = cat(hi_1, lo_1) node lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _T_6 = cat(hi_2, lo_2) node lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _T_7 = cat(hi_3, lo_3) node _T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node lo_4 = cat(_T_9, _T_8) node hi_4 = cat(_T_11, _T_10) node _T_12 = cat(hi_4, lo_4) node lo_5 = cat(_T_5, _T_4) node hi_hi = cat(_T_12, _T_7) node hi_5 = cat(hi_hi, _T_6) node _T_13 = cat(hi_5, lo_5) inst tt_0_1 of TageTable_6 connect tt_0_1.clock, clock connect tt_0_1.reset, reset reg t_io_f1_req_valid_REG : UInt<1>, clock connect t_io_f1_req_valid_REG, io.f0_valid connect tt_0_1.io.f1_req_valid, t_io_f1_req_valid_REG reg t_io_f1_req_pc_REG : UInt, clock connect t_io_f1_req_pc_REG, io.f0_pc connect tt_0_1.io.f1_req_pc, t_io_f1_req_pc_REG connect tt_0_1.io.f1_req_ghist, io.f1_ghist inst tt_1_1 of TageTable_7 connect tt_1_1.clock, clock connect tt_1_1.reset, reset reg t_io_f1_req_valid_REG_1 : UInt<1>, clock connect t_io_f1_req_valid_REG_1, io.f0_valid connect tt_1_1.io.f1_req_valid, t_io_f1_req_valid_REG_1 reg t_io_f1_req_pc_REG_1 : UInt, clock connect t_io_f1_req_pc_REG_1, io.f0_pc connect tt_1_1.io.f1_req_pc, t_io_f1_req_pc_REG_1 connect tt_1_1.io.f1_req_ghist, io.f1_ghist inst tt_2_1 of TageTable_8 connect tt_2_1.clock, clock connect tt_2_1.reset, reset reg t_io_f1_req_valid_REG_2 : UInt<1>, clock connect t_io_f1_req_valid_REG_2, io.f0_valid connect tt_2_1.io.f1_req_valid, t_io_f1_req_valid_REG_2 reg t_io_f1_req_pc_REG_2 : UInt, clock connect t_io_f1_req_pc_REG_2, io.f0_pc connect tt_2_1.io.f1_req_pc, t_io_f1_req_pc_REG_2 connect tt_2_1.io.f1_req_ghist, io.f1_ghist inst tt_3_1 of TageTable_9 connect tt_3_1.clock, clock connect tt_3_1.reset, reset reg t_io_f1_req_valid_REG_3 : UInt<1>, clock connect t_io_f1_req_valid_REG_3, io.f0_valid connect tt_3_1.io.f1_req_valid, t_io_f1_req_valid_REG_3 reg t_io_f1_req_pc_REG_3 : UInt, clock connect t_io_f1_req_pc_REG_3, io.f0_pc connect tt_3_1.io.f1_req_pc, t_io_f1_req_pc_REG_3 connect tt_3_1.io.f1_req_ghist, io.f1_ghist inst tt_4_1 of TageTable_10 connect tt_4_1.clock, clock connect tt_4_1.reset, reset reg t_io_f1_req_valid_REG_4 : UInt<1>, clock connect t_io_f1_req_valid_REG_4, io.f0_valid connect tt_4_1.io.f1_req_valid, t_io_f1_req_valid_REG_4 reg t_io_f1_req_pc_REG_4 : UInt, clock connect t_io_f1_req_pc_REG_4, io.f0_pc connect tt_4_1.io.f1_req_pc, t_io_f1_req_pc_REG_4 connect tt_4_1.io.f1_req_ghist, io.f1_ghist inst tt_5_1 of TageTable_11 connect tt_5_1.clock, clock connect tt_5_1.reset, reset reg t_io_f1_req_valid_REG_5 : UInt<1>, clock connect t_io_f1_req_valid_REG_5, io.f0_valid connect tt_5_1.io.f1_req_valid, t_io_f1_req_valid_REG_5 reg t_io_f1_req_pc_REG_5 : UInt, clock connect t_io_f1_req_pc_REG_5, io.f0_pc connect tt_5_1.io.f1_req_pc, t_io_f1_req_pc_REG_5 connect tt_5_1.io.f1_req_ghist, io.f1_ghist wire f3_resps : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4][6] connect f3_resps[0], tt_0_1.io.f3_resp connect f3_resps[1], tt_1_1.io.f3_resp connect f3_resps[2], tt_2_1.io.f3_resp connect f3_resps[3], tt_3_1.io.f3_resp connect f3_resps[4], tt_4_1.io.f3_resp connect f3_resps[5], tt_5_1.io.f3_resp wire s1_update_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} wire _s1_update_meta_WIRE : UInt<56> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 2, 0) connect s1_update_meta.allocate[0].bits, _s1_update_meta_T node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 3) connect s1_update_meta.allocate[0].valid, _s1_update_meta_T_1 node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 6, 4) connect s1_update_meta.allocate[1].bits, _s1_update_meta_T_2 node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 7) connect s1_update_meta.allocate[1].valid, _s1_update_meta_T_3 node _s1_update_meta_T_4 = bits(_s1_update_meta_WIRE, 10, 8) connect s1_update_meta.allocate[2].bits, _s1_update_meta_T_4 node _s1_update_meta_T_5 = bits(_s1_update_meta_WIRE, 11, 11) connect s1_update_meta.allocate[2].valid, _s1_update_meta_T_5 node _s1_update_meta_T_6 = bits(_s1_update_meta_WIRE, 14, 12) connect s1_update_meta.allocate[3].bits, _s1_update_meta_T_6 node _s1_update_meta_T_7 = bits(_s1_update_meta_WIRE, 15, 15) connect s1_update_meta.allocate[3].valid, _s1_update_meta_T_7 node _s1_update_meta_T_8 = bits(_s1_update_meta_WIRE, 18, 16) connect s1_update_meta.provider_ctr[0], _s1_update_meta_T_8 node _s1_update_meta_T_9 = bits(_s1_update_meta_WIRE, 21, 19) connect s1_update_meta.provider_ctr[1], _s1_update_meta_T_9 node _s1_update_meta_T_10 = bits(_s1_update_meta_WIRE, 24, 22) connect s1_update_meta.provider_ctr[2], _s1_update_meta_T_10 node _s1_update_meta_T_11 = bits(_s1_update_meta_WIRE, 27, 25) connect s1_update_meta.provider_ctr[3], _s1_update_meta_T_11 node _s1_update_meta_T_12 = bits(_s1_update_meta_WIRE, 29, 28) connect s1_update_meta.provider_u[0], _s1_update_meta_T_12 node _s1_update_meta_T_13 = bits(_s1_update_meta_WIRE, 31, 30) connect s1_update_meta.provider_u[1], _s1_update_meta_T_13 node _s1_update_meta_T_14 = bits(_s1_update_meta_WIRE, 33, 32) connect s1_update_meta.provider_u[2], _s1_update_meta_T_14 node _s1_update_meta_T_15 = bits(_s1_update_meta_WIRE, 35, 34) connect s1_update_meta.provider_u[3], _s1_update_meta_T_15 node _s1_update_meta_T_16 = bits(_s1_update_meta_WIRE, 36, 36) connect s1_update_meta.alt_differs[0], _s1_update_meta_T_16 node _s1_update_meta_T_17 = bits(_s1_update_meta_WIRE, 37, 37) connect s1_update_meta.alt_differs[1], _s1_update_meta_T_17 node _s1_update_meta_T_18 = bits(_s1_update_meta_WIRE, 38, 38) connect s1_update_meta.alt_differs[2], _s1_update_meta_T_18 node _s1_update_meta_T_19 = bits(_s1_update_meta_WIRE, 39, 39) connect s1_update_meta.alt_differs[3], _s1_update_meta_T_19 node _s1_update_meta_T_20 = bits(_s1_update_meta_WIRE, 42, 40) connect s1_update_meta.provider[0].bits, _s1_update_meta_T_20 node _s1_update_meta_T_21 = bits(_s1_update_meta_WIRE, 43, 43) connect s1_update_meta.provider[0].valid, _s1_update_meta_T_21 node _s1_update_meta_T_22 = bits(_s1_update_meta_WIRE, 46, 44) connect s1_update_meta.provider[1].bits, _s1_update_meta_T_22 node _s1_update_meta_T_23 = bits(_s1_update_meta_WIRE, 47, 47) connect s1_update_meta.provider[1].valid, _s1_update_meta_T_23 node _s1_update_meta_T_24 = bits(_s1_update_meta_WIRE, 50, 48) connect s1_update_meta.provider[2].bits, _s1_update_meta_T_24 node _s1_update_meta_T_25 = bits(_s1_update_meta_WIRE, 51, 51) connect s1_update_meta.provider[2].valid, _s1_update_meta_T_25 node _s1_update_meta_T_26 = bits(_s1_update_meta_WIRE, 54, 52) connect s1_update_meta.provider[3].bits, _s1_update_meta_T_26 node _s1_update_meta_T_27 = bits(_s1_update_meta_WIRE, 55, 55) connect s1_update_meta.provider[3].valid, _s1_update_meta_T_27 node _s1_update_mispredict_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_mispredict_mask_T_1 = mux(s1_update.bits.cfi_mispredicted, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_mispredict_mask = and(_s1_update_mispredict_mask_T, _s1_update_mispredict_mask_T_1) wire _s1_update_mask_WIRE : UInt<1>[4][6] connect _s1_update_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_mask : UInt<1>[4][6] connect s1_update_mask, _s1_update_mask_WIRE wire _s1_update_u_mask_WIRE : UInt<1>[4][6] connect _s1_update_u_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_u_mask : UInt<1>[4][6] connect s1_update_u_mask, _s1_update_u_mask_WIRE wire s1_update_taken : UInt<1>[4][6] wire s1_update_old_ctr : UInt<3>[4][6] wire s1_update_alloc : UInt<1>[4][6] wire s1_update_u : UInt<2>[4][6] invalidate s1_update_taken[0][0] invalidate s1_update_taken[0][1] invalidate s1_update_taken[0][2] invalidate s1_update_taken[0][3] invalidate s1_update_taken[1][0] invalidate s1_update_taken[1][1] invalidate s1_update_taken[1][2] invalidate s1_update_taken[1][3] invalidate s1_update_taken[2][0] invalidate s1_update_taken[2][1] invalidate s1_update_taken[2][2] invalidate s1_update_taken[2][3] invalidate s1_update_taken[3][0] invalidate s1_update_taken[3][1] invalidate s1_update_taken[3][2] invalidate s1_update_taken[3][3] invalidate s1_update_taken[4][0] invalidate s1_update_taken[4][1] invalidate s1_update_taken[4][2] invalidate s1_update_taken[4][3] invalidate s1_update_taken[5][0] invalidate s1_update_taken[5][1] invalidate s1_update_taken[5][2] invalidate s1_update_taken[5][3] invalidate s1_update_old_ctr[0][0] invalidate s1_update_old_ctr[0][1] invalidate s1_update_old_ctr[0][2] invalidate s1_update_old_ctr[0][3] invalidate s1_update_old_ctr[1][0] invalidate s1_update_old_ctr[1][1] invalidate s1_update_old_ctr[1][2] invalidate s1_update_old_ctr[1][3] invalidate s1_update_old_ctr[2][0] invalidate s1_update_old_ctr[2][1] invalidate s1_update_old_ctr[2][2] invalidate s1_update_old_ctr[2][3] invalidate s1_update_old_ctr[3][0] invalidate s1_update_old_ctr[3][1] invalidate s1_update_old_ctr[3][2] invalidate s1_update_old_ctr[3][3] invalidate s1_update_old_ctr[4][0] invalidate s1_update_old_ctr[4][1] invalidate s1_update_old_ctr[4][2] invalidate s1_update_old_ctr[4][3] invalidate s1_update_old_ctr[5][0] invalidate s1_update_old_ctr[5][1] invalidate s1_update_old_ctr[5][2] invalidate s1_update_old_ctr[5][3] invalidate s1_update_alloc[0][0] invalidate s1_update_alloc[0][1] invalidate s1_update_alloc[0][2] invalidate s1_update_alloc[0][3] invalidate s1_update_alloc[1][0] invalidate s1_update_alloc[1][1] invalidate s1_update_alloc[1][2] invalidate s1_update_alloc[1][3] invalidate s1_update_alloc[2][0] invalidate s1_update_alloc[2][1] invalidate s1_update_alloc[2][2] invalidate s1_update_alloc[2][3] invalidate s1_update_alloc[3][0] invalidate s1_update_alloc[3][1] invalidate s1_update_alloc[3][2] invalidate s1_update_alloc[3][3] invalidate s1_update_alloc[4][0] invalidate s1_update_alloc[4][1] invalidate s1_update_alloc[4][2] invalidate s1_update_alloc[4][3] invalidate s1_update_alloc[5][0] invalidate s1_update_alloc[5][1] invalidate s1_update_alloc[5][2] invalidate s1_update_alloc[5][3] invalidate s1_update_u[0][0] invalidate s1_update_u[0][1] invalidate s1_update_u[0][2] invalidate s1_update_u[0][3] invalidate s1_update_u[1][0] invalidate s1_update_u[1][1] invalidate s1_update_u[1][2] invalidate s1_update_u[1][3] invalidate s1_update_u[2][0] invalidate s1_update_u[2][1] invalidate s1_update_u[2][2] invalidate s1_update_u[2][3] invalidate s1_update_u[3][0] invalidate s1_update_u[3][1] invalidate s1_update_u[3][2] invalidate s1_update_u[3][3] invalidate s1_update_u[4][0] invalidate s1_update_u[4][1] invalidate s1_update_u[4][2] invalidate s1_update_u[4][3] invalidate s1_update_u[5][0] invalidate s1_update_u[5][1] invalidate s1_update_u[5][2] invalidate s1_update_u[5][3] wire final_altpred : UInt<1> connect final_altpred, io.resp_in[0].f3[0].taken connect io.resp.f3[0].taken, io.resp_in[0].f3[0].taken when f3_resps[0][0].valid : node _io_resp_f3_0_taken_T = eq(f3_resps[0][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_1 = eq(f3_resps[0][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_2 = or(_io_resp_f3_0_taken_T, _io_resp_f3_0_taken_T_1) node _io_resp_f3_0_taken_T_3 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_4 = mux(_io_resp_f3_0_taken_T_2, io.resp_in[0].f3[0].taken, _io_resp_f3_0_taken_T_3) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_4 connect final_altpred, io.resp_in[0].f3[0].taken node _T_14 = or(UInt<1>(0h0), f3_resps[0][0].valid) node _T_15 = mux(f3_resps[0][0].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_16 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _T_17 = mux(f3_resps[0][0].valid, _T_16, io.resp_in[0].f3[0].taken) when f3_resps[1][0].valid : node _io_resp_f3_0_taken_T_5 = eq(f3_resps[1][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_6 = eq(f3_resps[1][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_7 = or(_io_resp_f3_0_taken_T_5, _io_resp_f3_0_taken_T_6) node _io_resp_f3_0_taken_T_8 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_9 = mux(_io_resp_f3_0_taken_T_7, _T_17, _io_resp_f3_0_taken_T_8) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_9 connect final_altpred, _T_17 node _T_18 = or(_T_14, f3_resps[1][0].valid) node _T_19 = mux(f3_resps[1][0].valid, UInt<1>(0h1), _T_15) node _T_20 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _T_21 = mux(f3_resps[1][0].valid, _T_20, _T_17) when f3_resps[2][0].valid : node _io_resp_f3_0_taken_T_10 = eq(f3_resps[2][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_11 = eq(f3_resps[2][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_12 = or(_io_resp_f3_0_taken_T_10, _io_resp_f3_0_taken_T_11) node _io_resp_f3_0_taken_T_13 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_14 = mux(_io_resp_f3_0_taken_T_12, _T_21, _io_resp_f3_0_taken_T_13) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_14 connect final_altpred, _T_21 node _T_22 = or(_T_18, f3_resps[2][0].valid) node _T_23 = mux(f3_resps[2][0].valid, UInt<2>(0h2), _T_19) node _T_24 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _T_25 = mux(f3_resps[2][0].valid, _T_24, _T_21) when f3_resps[3][0].valid : node _io_resp_f3_0_taken_T_15 = eq(f3_resps[3][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_16 = eq(f3_resps[3][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_17 = or(_io_resp_f3_0_taken_T_15, _io_resp_f3_0_taken_T_16) node _io_resp_f3_0_taken_T_18 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_19 = mux(_io_resp_f3_0_taken_T_17, _T_25, _io_resp_f3_0_taken_T_18) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_19 connect final_altpred, _T_25 node _T_26 = or(_T_22, f3_resps[3][0].valid) node _T_27 = mux(f3_resps[3][0].valid, UInt<2>(0h3), _T_23) node _T_28 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _T_29 = mux(f3_resps[3][0].valid, _T_28, _T_25) when f3_resps[4][0].valid : node _io_resp_f3_0_taken_T_20 = eq(f3_resps[4][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_21 = eq(f3_resps[4][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_22 = or(_io_resp_f3_0_taken_T_20, _io_resp_f3_0_taken_T_21) node _io_resp_f3_0_taken_T_23 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_24 = mux(_io_resp_f3_0_taken_T_22, _T_29, _io_resp_f3_0_taken_T_23) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_24 connect final_altpred, _T_29 node _T_30 = or(_T_26, f3_resps[4][0].valid) node _T_31 = mux(f3_resps[4][0].valid, UInt<3>(0h4), _T_27) node _T_32 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _T_33 = mux(f3_resps[4][0].valid, _T_32, _T_29) when f3_resps[5][0].valid : node _io_resp_f3_0_taken_T_25 = eq(f3_resps[5][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_26 = eq(f3_resps[5][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_27 = or(_io_resp_f3_0_taken_T_25, _io_resp_f3_0_taken_T_26) node _io_resp_f3_0_taken_T_28 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_29 = mux(_io_resp_f3_0_taken_T_27, _T_33, _io_resp_f3_0_taken_T_28) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_29 connect final_altpred, _T_33 node _T_34 = or(_T_30, f3_resps[5][0].valid) node _T_35 = mux(f3_resps[5][0].valid, UInt<3>(0h5), _T_31) node _T_36 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _T_37 = mux(f3_resps[5][0].valid, _T_36, _T_33) connect f3_meta.provider[0].valid, _T_34 connect f3_meta.provider[0].bits, _T_35 node _f3_meta_alt_differs_0_T = neq(final_altpred, io.resp.f3[0].taken) connect f3_meta.alt_differs[0], _f3_meta_alt_differs_0_T connect f3_meta.provider_u[0], f3_resps[_T_35][0].bits.u connect f3_meta.provider_ctr[0], f3_resps[_T_35][0].bits.ctr node _allocatable_slots_T = eq(f3_resps[0][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_1 = eq(f3_resps[0][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_2 = and(_allocatable_slots_T, _allocatable_slots_T_1) node _allocatable_slots_T_3 = eq(f3_resps[1][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_4 = eq(f3_resps[1][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_5 = and(_allocatable_slots_T_3, _allocatable_slots_T_4) node _allocatable_slots_T_6 = eq(f3_resps[2][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_7 = eq(f3_resps[2][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_8 = and(_allocatable_slots_T_6, _allocatable_slots_T_7) node _allocatable_slots_T_9 = eq(f3_resps[3][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_10 = eq(f3_resps[3][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_11 = and(_allocatable_slots_T_9, _allocatable_slots_T_10) node _allocatable_slots_T_12 = eq(f3_resps[4][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_13 = eq(f3_resps[4][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_14 = and(_allocatable_slots_T_12, _allocatable_slots_T_13) node _allocatable_slots_T_15 = eq(f3_resps[5][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_16 = eq(f3_resps[5][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_17 = and(_allocatable_slots_T_15, _allocatable_slots_T_16) wire _allocatable_slots_WIRE : UInt<1>[6] connect _allocatable_slots_WIRE[0], _allocatable_slots_T_2 connect _allocatable_slots_WIRE[1], _allocatable_slots_T_5 connect _allocatable_slots_WIRE[2], _allocatable_slots_T_8 connect _allocatable_slots_WIRE[3], _allocatable_slots_T_11 connect _allocatable_slots_WIRE[4], _allocatable_slots_T_14 connect _allocatable_slots_WIRE[5], _allocatable_slots_T_17 node allocatable_slots_lo_hi = cat(_allocatable_slots_WIRE[2], _allocatable_slots_WIRE[1]) node allocatable_slots_lo = cat(allocatable_slots_lo_hi, _allocatable_slots_WIRE[0]) node allocatable_slots_hi_hi = cat(_allocatable_slots_WIRE[5], _allocatable_slots_WIRE[4]) node allocatable_slots_hi = cat(allocatable_slots_hi_hi, _allocatable_slots_WIRE[3]) node _allocatable_slots_T_18 = cat(allocatable_slots_hi, allocatable_slots_lo) node _allocatable_slots_T_19 = dshl(UInt<1>(0h1), _T_35) node _allocatable_slots_T_20 = dshr(_allocatable_slots_T_19, UInt<1>(0h0)) node _allocatable_slots_T_21 = dshr(_allocatable_slots_T_19, UInt<1>(0h1)) node _allocatable_slots_T_22 = dshr(_allocatable_slots_T_19, UInt<2>(0h2)) node _allocatable_slots_T_23 = dshr(_allocatable_slots_T_19, UInt<2>(0h3)) node _allocatable_slots_T_24 = dshr(_allocatable_slots_T_19, UInt<3>(0h4)) node _allocatable_slots_T_25 = dshr(_allocatable_slots_T_19, UInt<3>(0h5)) node _allocatable_slots_T_26 = dshr(_allocatable_slots_T_19, UInt<3>(0h6)) node _allocatable_slots_T_27 = dshr(_allocatable_slots_T_19, UInt<3>(0h7)) node _allocatable_slots_T_28 = or(_allocatable_slots_T_20, _allocatable_slots_T_21) node _allocatable_slots_T_29 = or(_allocatable_slots_T_28, _allocatable_slots_T_22) node _allocatable_slots_T_30 = or(_allocatable_slots_T_29, _allocatable_slots_T_23) node _allocatable_slots_T_31 = or(_allocatable_slots_T_30, _allocatable_slots_T_24) node _allocatable_slots_T_32 = or(_allocatable_slots_T_31, _allocatable_slots_T_25) node _allocatable_slots_T_33 = or(_allocatable_slots_T_32, _allocatable_slots_T_26) node _allocatable_slots_T_34 = or(_allocatable_slots_T_33, _allocatable_slots_T_27) node _allocatable_slots_T_35 = mux(_T_34, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_36 = and(_allocatable_slots_T_34, _allocatable_slots_T_35) node _allocatable_slots_T_37 = not(_allocatable_slots_T_36) node allocatable_slots = and(_allocatable_slots_T_18, _allocatable_slots_T_37) inst alloc_lfsr_prng of MaxPeriodFibonacciLFSR_9 connect alloc_lfsr_prng.clock, clock connect alloc_lfsr_prng.reset, reset connect alloc_lfsr_prng.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng.io.seed.bits[0] invalidate alloc_lfsr_prng.io.seed.bits[1] invalidate alloc_lfsr_prng.io.seed.bits[2] invalidate alloc_lfsr_prng.io.seed.bits[3] invalidate alloc_lfsr_prng.io.seed.bits[4] invalidate alloc_lfsr_prng.io.seed.bits[5] connect alloc_lfsr_prng.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi = cat(alloc_lfsr_prng.io.out[2], alloc_lfsr_prng.io.out[1]) node alloc_lfsr_lo = cat(alloc_lfsr_lo_hi, alloc_lfsr_prng.io.out[0]) node alloc_lfsr_hi_hi = cat(alloc_lfsr_prng.io.out[5], alloc_lfsr_prng.io.out[4]) node alloc_lfsr_hi = cat(alloc_lfsr_hi_hi, alloc_lfsr_prng.io.out[3]) node alloc_lfsr = cat(alloc_lfsr_hi, alloc_lfsr_lo) node _first_entry_T = bits(allocatable_slots, 0, 0) node _first_entry_T_1 = bits(allocatable_slots, 1, 1) node _first_entry_T_2 = bits(allocatable_slots, 2, 2) node _first_entry_T_3 = bits(allocatable_slots, 3, 3) node _first_entry_T_4 = bits(allocatable_slots, 4, 4) node _first_entry_T_5 = bits(allocatable_slots, 5, 5) node _first_entry_T_6 = bits(allocatable_slots, 6, 6) node _first_entry_T_7 = bits(allocatable_slots, 7, 7) node _first_entry_T_8 = mux(_first_entry_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_9 = mux(_first_entry_T_5, UInt<3>(0h5), _first_entry_T_8) node _first_entry_T_10 = mux(_first_entry_T_4, UInt<3>(0h4), _first_entry_T_9) node _first_entry_T_11 = mux(_first_entry_T_3, UInt<2>(0h3), _first_entry_T_10) node _first_entry_T_12 = mux(_first_entry_T_2, UInt<2>(0h2), _first_entry_T_11) node _first_entry_T_13 = mux(_first_entry_T_1, UInt<1>(0h1), _first_entry_T_12) node first_entry = mux(_first_entry_T, UInt<1>(0h0), _first_entry_T_13) node _masked_entry_T = and(allocatable_slots, alloc_lfsr) node _masked_entry_T_1 = bits(_masked_entry_T, 0, 0) node _masked_entry_T_2 = bits(_masked_entry_T, 1, 1) node _masked_entry_T_3 = bits(_masked_entry_T, 2, 2) node _masked_entry_T_4 = bits(_masked_entry_T, 3, 3) node _masked_entry_T_5 = bits(_masked_entry_T, 4, 4) node _masked_entry_T_6 = bits(_masked_entry_T, 5, 5) node _masked_entry_T_7 = bits(_masked_entry_T, 6, 6) node _masked_entry_T_8 = bits(_masked_entry_T, 7, 7) node _masked_entry_T_9 = mux(_masked_entry_T_7, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_10 = mux(_masked_entry_T_6, UInt<3>(0h5), _masked_entry_T_9) node _masked_entry_T_11 = mux(_masked_entry_T_5, UInt<3>(0h4), _masked_entry_T_10) node _masked_entry_T_12 = mux(_masked_entry_T_4, UInt<2>(0h3), _masked_entry_T_11) node _masked_entry_T_13 = mux(_masked_entry_T_3, UInt<2>(0h2), _masked_entry_T_12) node _masked_entry_T_14 = mux(_masked_entry_T_2, UInt<1>(0h1), _masked_entry_T_13) node masked_entry = mux(_masked_entry_T_1, UInt<1>(0h0), _masked_entry_T_14) node _alloc_entry_T = dshr(allocatable_slots, masked_entry) node _alloc_entry_T_1 = bits(_alloc_entry_T, 0, 0) node alloc_entry = mux(_alloc_entry_T_1, masked_entry, first_entry) node _f3_meta_allocate_0_valid_T = neq(allocatable_slots, UInt<1>(0h0)) connect f3_meta.allocate[0].valid, _f3_meta_allocate_0_valid_T connect f3_meta.allocate[0].bits, alloc_entry node _update_was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _update_was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T) node update_was_taken = and(_update_was_taken_T_1, s1_update.bits.cfi_taken) node _T_38 = bits(s1_update.bits.br_mask, 0, 0) node _T_39 = and(_T_38, s1_update.valid) node _T_40 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_41 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = and(_T_39, _T_43) when _T_44 : when s1_update_meta.provider[0].valid : connect s1_update_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) node _new_u_T = bits(s1_update_mispredict_mask, 0, 0) node _new_u_T_1 = eq(s1_update_meta.alt_differs[0], UInt<1>(0h0)) node _new_u_T_2 = eq(s1_update_meta.provider_u[0], UInt<1>(0h0)) node _new_u_T_3 = sub(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_4 = tail(_new_u_T_3, 1) node _new_u_T_5 = mux(_new_u_T_2, UInt<1>(0h0), _new_u_T_4) node _new_u_T_6 = eq(s1_update_meta.provider_u[0], UInt<2>(0h3)) node _new_u_T_7 = add(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_8 = tail(_new_u_T_7, 1) node _new_u_T_9 = mux(_new_u_T_6, UInt<2>(0h3), _new_u_T_8) node _new_u_T_10 = mux(_new_u_T, _new_u_T_5, _new_u_T_9) node new_u = mux(_new_u_T_1, s1_update_meta.provider_u[0], _new_u_T_10) connect s1_update_u[s1_update_meta.provider[0].bits][0], new_u connect s1_update_taken[s1_update_meta.provider[0].bits][0], update_was_taken connect s1_update_old_ctr[s1_update_meta.provider[0].bits][0], s1_update_meta.provider_ctr[0] connect s1_update_alloc[s1_update_meta.provider[0].bits][0], UInt<1>(0h0) wire final_altpred_1 : UInt<1> connect final_altpred_1, io.resp_in[0].f3[1].taken connect io.resp.f3[1].taken, io.resp_in[0].f3[1].taken when f3_resps[0][1].valid : node _io_resp_f3_1_taken_T = eq(f3_resps[0][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_1 = eq(f3_resps[0][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_2 = or(_io_resp_f3_1_taken_T, _io_resp_f3_1_taken_T_1) node _io_resp_f3_1_taken_T_3 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_4 = mux(_io_resp_f3_1_taken_T_2, io.resp_in[0].f3[1].taken, _io_resp_f3_1_taken_T_3) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_4 connect final_altpred_1, io.resp_in[0].f3[1].taken node _T_45 = or(UInt<1>(0h0), f3_resps[0][1].valid) node _T_46 = mux(f3_resps[0][1].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _T_48 = mux(f3_resps[0][1].valid, _T_47, io.resp_in[0].f3[1].taken) when f3_resps[1][1].valid : node _io_resp_f3_1_taken_T_5 = eq(f3_resps[1][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_6 = eq(f3_resps[1][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_7 = or(_io_resp_f3_1_taken_T_5, _io_resp_f3_1_taken_T_6) node _io_resp_f3_1_taken_T_8 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_9 = mux(_io_resp_f3_1_taken_T_7, _T_48, _io_resp_f3_1_taken_T_8) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_9 connect final_altpred_1, _T_48 node _T_49 = or(_T_45, f3_resps[1][1].valid) node _T_50 = mux(f3_resps[1][1].valid, UInt<1>(0h1), _T_46) node _T_51 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _T_52 = mux(f3_resps[1][1].valid, _T_51, _T_48) when f3_resps[2][1].valid : node _io_resp_f3_1_taken_T_10 = eq(f3_resps[2][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_11 = eq(f3_resps[2][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_12 = or(_io_resp_f3_1_taken_T_10, _io_resp_f3_1_taken_T_11) node _io_resp_f3_1_taken_T_13 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_14 = mux(_io_resp_f3_1_taken_T_12, _T_52, _io_resp_f3_1_taken_T_13) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_14 connect final_altpred_1, _T_52 node _T_53 = or(_T_49, f3_resps[2][1].valid) node _T_54 = mux(f3_resps[2][1].valid, UInt<2>(0h2), _T_50) node _T_55 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _T_56 = mux(f3_resps[2][1].valid, _T_55, _T_52) when f3_resps[3][1].valid : node _io_resp_f3_1_taken_T_15 = eq(f3_resps[3][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_16 = eq(f3_resps[3][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_17 = or(_io_resp_f3_1_taken_T_15, _io_resp_f3_1_taken_T_16) node _io_resp_f3_1_taken_T_18 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_19 = mux(_io_resp_f3_1_taken_T_17, _T_56, _io_resp_f3_1_taken_T_18) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_19 connect final_altpred_1, _T_56 node _T_57 = or(_T_53, f3_resps[3][1].valid) node _T_58 = mux(f3_resps[3][1].valid, UInt<2>(0h3), _T_54) node _T_59 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _T_60 = mux(f3_resps[3][1].valid, _T_59, _T_56) when f3_resps[4][1].valid : node _io_resp_f3_1_taken_T_20 = eq(f3_resps[4][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_21 = eq(f3_resps[4][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_22 = or(_io_resp_f3_1_taken_T_20, _io_resp_f3_1_taken_T_21) node _io_resp_f3_1_taken_T_23 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_24 = mux(_io_resp_f3_1_taken_T_22, _T_60, _io_resp_f3_1_taken_T_23) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_24 connect final_altpred_1, _T_60 node _T_61 = or(_T_57, f3_resps[4][1].valid) node _T_62 = mux(f3_resps[4][1].valid, UInt<3>(0h4), _T_58) node _T_63 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _T_64 = mux(f3_resps[4][1].valid, _T_63, _T_60) when f3_resps[5][1].valid : node _io_resp_f3_1_taken_T_25 = eq(f3_resps[5][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_26 = eq(f3_resps[5][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_27 = or(_io_resp_f3_1_taken_T_25, _io_resp_f3_1_taken_T_26) node _io_resp_f3_1_taken_T_28 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_29 = mux(_io_resp_f3_1_taken_T_27, _T_64, _io_resp_f3_1_taken_T_28) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_29 connect final_altpred_1, _T_64 node _T_65 = or(_T_61, f3_resps[5][1].valid) node _T_66 = mux(f3_resps[5][1].valid, UInt<3>(0h5), _T_62) node _T_67 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _T_68 = mux(f3_resps[5][1].valid, _T_67, _T_64) connect f3_meta.provider[1].valid, _T_65 connect f3_meta.provider[1].bits, _T_66 node _f3_meta_alt_differs_1_T = neq(final_altpred_1, io.resp.f3[1].taken) connect f3_meta.alt_differs[1], _f3_meta_alt_differs_1_T connect f3_meta.provider_u[1], f3_resps[_T_66][1].bits.u connect f3_meta.provider_ctr[1], f3_resps[_T_66][1].bits.ctr node _allocatable_slots_T_38 = eq(f3_resps[0][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_39 = eq(f3_resps[0][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_40 = and(_allocatable_slots_T_38, _allocatable_slots_T_39) node _allocatable_slots_T_41 = eq(f3_resps[1][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_42 = eq(f3_resps[1][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_43 = and(_allocatable_slots_T_41, _allocatable_slots_T_42) node _allocatable_slots_T_44 = eq(f3_resps[2][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_45 = eq(f3_resps[2][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_46 = and(_allocatable_slots_T_44, _allocatable_slots_T_45) node _allocatable_slots_T_47 = eq(f3_resps[3][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_48 = eq(f3_resps[3][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_49 = and(_allocatable_slots_T_47, _allocatable_slots_T_48) node _allocatable_slots_T_50 = eq(f3_resps[4][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_51 = eq(f3_resps[4][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_52 = and(_allocatable_slots_T_50, _allocatable_slots_T_51) node _allocatable_slots_T_53 = eq(f3_resps[5][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_54 = eq(f3_resps[5][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_55 = and(_allocatable_slots_T_53, _allocatable_slots_T_54) wire _allocatable_slots_WIRE_1 : UInt<1>[6] connect _allocatable_slots_WIRE_1[0], _allocatable_slots_T_40 connect _allocatable_slots_WIRE_1[1], _allocatable_slots_T_43 connect _allocatable_slots_WIRE_1[2], _allocatable_slots_T_46 connect _allocatable_slots_WIRE_1[3], _allocatable_slots_T_49 connect _allocatable_slots_WIRE_1[4], _allocatable_slots_T_52 connect _allocatable_slots_WIRE_1[5], _allocatable_slots_T_55 node allocatable_slots_lo_hi_1 = cat(_allocatable_slots_WIRE_1[2], _allocatable_slots_WIRE_1[1]) node allocatable_slots_lo_1 = cat(allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1[0]) node allocatable_slots_hi_hi_1 = cat(_allocatable_slots_WIRE_1[5], _allocatable_slots_WIRE_1[4]) node allocatable_slots_hi_1 = cat(allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1[3]) node _allocatable_slots_T_56 = cat(allocatable_slots_hi_1, allocatable_slots_lo_1) node _allocatable_slots_T_57 = dshl(UInt<1>(0h1), _T_66) node _allocatable_slots_T_58 = dshr(_allocatable_slots_T_57, UInt<1>(0h0)) node _allocatable_slots_T_59 = dshr(_allocatable_slots_T_57, UInt<1>(0h1)) node _allocatable_slots_T_60 = dshr(_allocatable_slots_T_57, UInt<2>(0h2)) node _allocatable_slots_T_61 = dshr(_allocatable_slots_T_57, UInt<2>(0h3)) node _allocatable_slots_T_62 = dshr(_allocatable_slots_T_57, UInt<3>(0h4)) node _allocatable_slots_T_63 = dshr(_allocatable_slots_T_57, UInt<3>(0h5)) node _allocatable_slots_T_64 = dshr(_allocatable_slots_T_57, UInt<3>(0h6)) node _allocatable_slots_T_65 = dshr(_allocatable_slots_T_57, UInt<3>(0h7)) node _allocatable_slots_T_66 = or(_allocatable_slots_T_58, _allocatable_slots_T_59) node _allocatable_slots_T_67 = or(_allocatable_slots_T_66, _allocatable_slots_T_60) node _allocatable_slots_T_68 = or(_allocatable_slots_T_67, _allocatable_slots_T_61) node _allocatable_slots_T_69 = or(_allocatable_slots_T_68, _allocatable_slots_T_62) node _allocatable_slots_T_70 = or(_allocatable_slots_T_69, _allocatable_slots_T_63) node _allocatable_slots_T_71 = or(_allocatable_slots_T_70, _allocatable_slots_T_64) node _allocatable_slots_T_72 = or(_allocatable_slots_T_71, _allocatable_slots_T_65) node _allocatable_slots_T_73 = mux(_T_65, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_74 = and(_allocatable_slots_T_72, _allocatable_slots_T_73) node _allocatable_slots_T_75 = not(_allocatable_slots_T_74) node allocatable_slots_1 = and(_allocatable_slots_T_56, _allocatable_slots_T_75) inst alloc_lfsr_prng_1 of MaxPeriodFibonacciLFSR_10 connect alloc_lfsr_prng_1.clock, clock connect alloc_lfsr_prng_1.reset, reset connect alloc_lfsr_prng_1.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_1.io.seed.bits[0] invalidate alloc_lfsr_prng_1.io.seed.bits[1] invalidate alloc_lfsr_prng_1.io.seed.bits[2] invalidate alloc_lfsr_prng_1.io.seed.bits[3] invalidate alloc_lfsr_prng_1.io.seed.bits[4] invalidate alloc_lfsr_prng_1.io.seed.bits[5] connect alloc_lfsr_prng_1.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_1 = cat(alloc_lfsr_prng_1.io.out[2], alloc_lfsr_prng_1.io.out[1]) node alloc_lfsr_lo_1 = cat(alloc_lfsr_lo_hi_1, alloc_lfsr_prng_1.io.out[0]) node alloc_lfsr_hi_hi_1 = cat(alloc_lfsr_prng_1.io.out[5], alloc_lfsr_prng_1.io.out[4]) node alloc_lfsr_hi_1 = cat(alloc_lfsr_hi_hi_1, alloc_lfsr_prng_1.io.out[3]) node alloc_lfsr_1 = cat(alloc_lfsr_hi_1, alloc_lfsr_lo_1) node _first_entry_T_14 = bits(allocatable_slots_1, 0, 0) node _first_entry_T_15 = bits(allocatable_slots_1, 1, 1) node _first_entry_T_16 = bits(allocatable_slots_1, 2, 2) node _first_entry_T_17 = bits(allocatable_slots_1, 3, 3) node _first_entry_T_18 = bits(allocatable_slots_1, 4, 4) node _first_entry_T_19 = bits(allocatable_slots_1, 5, 5) node _first_entry_T_20 = bits(allocatable_slots_1, 6, 6) node _first_entry_T_21 = bits(allocatable_slots_1, 7, 7) node _first_entry_T_22 = mux(_first_entry_T_20, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_23 = mux(_first_entry_T_19, UInt<3>(0h5), _first_entry_T_22) node _first_entry_T_24 = mux(_first_entry_T_18, UInt<3>(0h4), _first_entry_T_23) node _first_entry_T_25 = mux(_first_entry_T_17, UInt<2>(0h3), _first_entry_T_24) node _first_entry_T_26 = mux(_first_entry_T_16, UInt<2>(0h2), _first_entry_T_25) node _first_entry_T_27 = mux(_first_entry_T_15, UInt<1>(0h1), _first_entry_T_26) node first_entry_1 = mux(_first_entry_T_14, UInt<1>(0h0), _first_entry_T_27) node _masked_entry_T_15 = and(allocatable_slots_1, alloc_lfsr_1) node _masked_entry_T_16 = bits(_masked_entry_T_15, 0, 0) node _masked_entry_T_17 = bits(_masked_entry_T_15, 1, 1) node _masked_entry_T_18 = bits(_masked_entry_T_15, 2, 2) node _masked_entry_T_19 = bits(_masked_entry_T_15, 3, 3) node _masked_entry_T_20 = bits(_masked_entry_T_15, 4, 4) node _masked_entry_T_21 = bits(_masked_entry_T_15, 5, 5) node _masked_entry_T_22 = bits(_masked_entry_T_15, 6, 6) node _masked_entry_T_23 = bits(_masked_entry_T_15, 7, 7) node _masked_entry_T_24 = mux(_masked_entry_T_22, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_25 = mux(_masked_entry_T_21, UInt<3>(0h5), _masked_entry_T_24) node _masked_entry_T_26 = mux(_masked_entry_T_20, UInt<3>(0h4), _masked_entry_T_25) node _masked_entry_T_27 = mux(_masked_entry_T_19, UInt<2>(0h3), _masked_entry_T_26) node _masked_entry_T_28 = mux(_masked_entry_T_18, UInt<2>(0h2), _masked_entry_T_27) node _masked_entry_T_29 = mux(_masked_entry_T_17, UInt<1>(0h1), _masked_entry_T_28) node masked_entry_1 = mux(_masked_entry_T_16, UInt<1>(0h0), _masked_entry_T_29) node _alloc_entry_T_2 = dshr(allocatable_slots_1, masked_entry_1) node _alloc_entry_T_3 = bits(_alloc_entry_T_2, 0, 0) node alloc_entry_1 = mux(_alloc_entry_T_3, masked_entry_1, first_entry_1) node _f3_meta_allocate_1_valid_T = neq(allocatable_slots_1, UInt<1>(0h0)) connect f3_meta.allocate[1].valid, _f3_meta_allocate_1_valid_T connect f3_meta.allocate[1].bits, alloc_entry_1 node _update_was_taken_T_2 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _update_was_taken_T_3 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_2) node update_was_taken_1 = and(_update_was_taken_T_3, s1_update.bits.cfi_taken) node _T_69 = bits(s1_update.bits.br_mask, 1, 1) node _T_70 = and(_T_69, s1_update.valid) node _T_71 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_72 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_73 = or(_T_71, _T_72) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = and(_T_70, _T_74) when _T_75 : when s1_update_meta.provider[1].valid : connect s1_update_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) node _new_u_T_11 = bits(s1_update_mispredict_mask, 1, 1) node _new_u_T_12 = eq(s1_update_meta.alt_differs[1], UInt<1>(0h0)) node _new_u_T_13 = eq(s1_update_meta.provider_u[1], UInt<1>(0h0)) node _new_u_T_14 = sub(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_15 = tail(_new_u_T_14, 1) node _new_u_T_16 = mux(_new_u_T_13, UInt<1>(0h0), _new_u_T_15) node _new_u_T_17 = eq(s1_update_meta.provider_u[1], UInt<2>(0h3)) node _new_u_T_18 = add(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_19 = tail(_new_u_T_18, 1) node _new_u_T_20 = mux(_new_u_T_17, UInt<2>(0h3), _new_u_T_19) node _new_u_T_21 = mux(_new_u_T_11, _new_u_T_16, _new_u_T_20) node new_u_1 = mux(_new_u_T_12, s1_update_meta.provider_u[1], _new_u_T_21) connect s1_update_u[s1_update_meta.provider[1].bits][1], new_u_1 connect s1_update_taken[s1_update_meta.provider[1].bits][1], update_was_taken_1 connect s1_update_old_ctr[s1_update_meta.provider[1].bits][1], s1_update_meta.provider_ctr[1] connect s1_update_alloc[s1_update_meta.provider[1].bits][1], UInt<1>(0h0) wire final_altpred_2 : UInt<1> connect final_altpred_2, io.resp_in[0].f3[2].taken connect io.resp.f3[2].taken, io.resp_in[0].f3[2].taken when f3_resps[0][2].valid : node _io_resp_f3_2_taken_T = eq(f3_resps[0][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_1 = eq(f3_resps[0][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_2 = or(_io_resp_f3_2_taken_T, _io_resp_f3_2_taken_T_1) node _io_resp_f3_2_taken_T_3 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_4 = mux(_io_resp_f3_2_taken_T_2, io.resp_in[0].f3[2].taken, _io_resp_f3_2_taken_T_3) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_4 connect final_altpred_2, io.resp_in[0].f3[2].taken node _T_76 = or(UInt<1>(0h0), f3_resps[0][2].valid) node _T_77 = mux(f3_resps[0][2].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_78 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _T_79 = mux(f3_resps[0][2].valid, _T_78, io.resp_in[0].f3[2].taken) when f3_resps[1][2].valid : node _io_resp_f3_2_taken_T_5 = eq(f3_resps[1][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_6 = eq(f3_resps[1][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_7 = or(_io_resp_f3_2_taken_T_5, _io_resp_f3_2_taken_T_6) node _io_resp_f3_2_taken_T_8 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_9 = mux(_io_resp_f3_2_taken_T_7, _T_79, _io_resp_f3_2_taken_T_8) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_9 connect final_altpred_2, _T_79 node _T_80 = or(_T_76, f3_resps[1][2].valid) node _T_81 = mux(f3_resps[1][2].valid, UInt<1>(0h1), _T_77) node _T_82 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _T_83 = mux(f3_resps[1][2].valid, _T_82, _T_79) when f3_resps[2][2].valid : node _io_resp_f3_2_taken_T_10 = eq(f3_resps[2][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_11 = eq(f3_resps[2][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_12 = or(_io_resp_f3_2_taken_T_10, _io_resp_f3_2_taken_T_11) node _io_resp_f3_2_taken_T_13 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_14 = mux(_io_resp_f3_2_taken_T_12, _T_83, _io_resp_f3_2_taken_T_13) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_14 connect final_altpred_2, _T_83 node _T_84 = or(_T_80, f3_resps[2][2].valid) node _T_85 = mux(f3_resps[2][2].valid, UInt<2>(0h2), _T_81) node _T_86 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _T_87 = mux(f3_resps[2][2].valid, _T_86, _T_83) when f3_resps[3][2].valid : node _io_resp_f3_2_taken_T_15 = eq(f3_resps[3][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_16 = eq(f3_resps[3][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_17 = or(_io_resp_f3_2_taken_T_15, _io_resp_f3_2_taken_T_16) node _io_resp_f3_2_taken_T_18 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_19 = mux(_io_resp_f3_2_taken_T_17, _T_87, _io_resp_f3_2_taken_T_18) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_19 connect final_altpred_2, _T_87 node _T_88 = or(_T_84, f3_resps[3][2].valid) node _T_89 = mux(f3_resps[3][2].valid, UInt<2>(0h3), _T_85) node _T_90 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _T_91 = mux(f3_resps[3][2].valid, _T_90, _T_87) when f3_resps[4][2].valid : node _io_resp_f3_2_taken_T_20 = eq(f3_resps[4][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_21 = eq(f3_resps[4][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_22 = or(_io_resp_f3_2_taken_T_20, _io_resp_f3_2_taken_T_21) node _io_resp_f3_2_taken_T_23 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_24 = mux(_io_resp_f3_2_taken_T_22, _T_91, _io_resp_f3_2_taken_T_23) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_24 connect final_altpred_2, _T_91 node _T_92 = or(_T_88, f3_resps[4][2].valid) node _T_93 = mux(f3_resps[4][2].valid, UInt<3>(0h4), _T_89) node _T_94 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _T_95 = mux(f3_resps[4][2].valid, _T_94, _T_91) when f3_resps[5][2].valid : node _io_resp_f3_2_taken_T_25 = eq(f3_resps[5][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_26 = eq(f3_resps[5][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_27 = or(_io_resp_f3_2_taken_T_25, _io_resp_f3_2_taken_T_26) node _io_resp_f3_2_taken_T_28 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_29 = mux(_io_resp_f3_2_taken_T_27, _T_95, _io_resp_f3_2_taken_T_28) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_29 connect final_altpred_2, _T_95 node _T_96 = or(_T_92, f3_resps[5][2].valid) node _T_97 = mux(f3_resps[5][2].valid, UInt<3>(0h5), _T_93) node _T_98 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _T_99 = mux(f3_resps[5][2].valid, _T_98, _T_95) connect f3_meta.provider[2].valid, _T_96 connect f3_meta.provider[2].bits, _T_97 node _f3_meta_alt_differs_2_T = neq(final_altpred_2, io.resp.f3[2].taken) connect f3_meta.alt_differs[2], _f3_meta_alt_differs_2_T connect f3_meta.provider_u[2], f3_resps[_T_97][2].bits.u connect f3_meta.provider_ctr[2], f3_resps[_T_97][2].bits.ctr node _allocatable_slots_T_76 = eq(f3_resps[0][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_77 = eq(f3_resps[0][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_78 = and(_allocatable_slots_T_76, _allocatable_slots_T_77) node _allocatable_slots_T_79 = eq(f3_resps[1][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_80 = eq(f3_resps[1][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_81 = and(_allocatable_slots_T_79, _allocatable_slots_T_80) node _allocatable_slots_T_82 = eq(f3_resps[2][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_83 = eq(f3_resps[2][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_84 = and(_allocatable_slots_T_82, _allocatable_slots_T_83) node _allocatable_slots_T_85 = eq(f3_resps[3][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_86 = eq(f3_resps[3][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_87 = and(_allocatable_slots_T_85, _allocatable_slots_T_86) node _allocatable_slots_T_88 = eq(f3_resps[4][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_89 = eq(f3_resps[4][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_90 = and(_allocatable_slots_T_88, _allocatable_slots_T_89) node _allocatable_slots_T_91 = eq(f3_resps[5][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_92 = eq(f3_resps[5][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_93 = and(_allocatable_slots_T_91, _allocatable_slots_T_92) wire _allocatable_slots_WIRE_2 : UInt<1>[6] connect _allocatable_slots_WIRE_2[0], _allocatable_slots_T_78 connect _allocatable_slots_WIRE_2[1], _allocatable_slots_T_81 connect _allocatable_slots_WIRE_2[2], _allocatable_slots_T_84 connect _allocatable_slots_WIRE_2[3], _allocatable_slots_T_87 connect _allocatable_slots_WIRE_2[4], _allocatable_slots_T_90 connect _allocatable_slots_WIRE_2[5], _allocatable_slots_T_93 node allocatable_slots_lo_hi_2 = cat(_allocatable_slots_WIRE_2[2], _allocatable_slots_WIRE_2[1]) node allocatable_slots_lo_2 = cat(allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2[0]) node allocatable_slots_hi_hi_2 = cat(_allocatable_slots_WIRE_2[5], _allocatable_slots_WIRE_2[4]) node allocatable_slots_hi_2 = cat(allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2[3]) node _allocatable_slots_T_94 = cat(allocatable_slots_hi_2, allocatable_slots_lo_2) node _allocatable_slots_T_95 = dshl(UInt<1>(0h1), _T_97) node _allocatable_slots_T_96 = dshr(_allocatable_slots_T_95, UInt<1>(0h0)) node _allocatable_slots_T_97 = dshr(_allocatable_slots_T_95, UInt<1>(0h1)) node _allocatable_slots_T_98 = dshr(_allocatable_slots_T_95, UInt<2>(0h2)) node _allocatable_slots_T_99 = dshr(_allocatable_slots_T_95, UInt<2>(0h3)) node _allocatable_slots_T_100 = dshr(_allocatable_slots_T_95, UInt<3>(0h4)) node _allocatable_slots_T_101 = dshr(_allocatable_slots_T_95, UInt<3>(0h5)) node _allocatable_slots_T_102 = dshr(_allocatable_slots_T_95, UInt<3>(0h6)) node _allocatable_slots_T_103 = dshr(_allocatable_slots_T_95, UInt<3>(0h7)) node _allocatable_slots_T_104 = or(_allocatable_slots_T_96, _allocatable_slots_T_97) node _allocatable_slots_T_105 = or(_allocatable_slots_T_104, _allocatable_slots_T_98) node _allocatable_slots_T_106 = or(_allocatable_slots_T_105, _allocatable_slots_T_99) node _allocatable_slots_T_107 = or(_allocatable_slots_T_106, _allocatable_slots_T_100) node _allocatable_slots_T_108 = or(_allocatable_slots_T_107, _allocatable_slots_T_101) node _allocatable_slots_T_109 = or(_allocatable_slots_T_108, _allocatable_slots_T_102) node _allocatable_slots_T_110 = or(_allocatable_slots_T_109, _allocatable_slots_T_103) node _allocatable_slots_T_111 = mux(_T_96, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_112 = and(_allocatable_slots_T_110, _allocatable_slots_T_111) node _allocatable_slots_T_113 = not(_allocatable_slots_T_112) node allocatable_slots_2 = and(_allocatable_slots_T_94, _allocatable_slots_T_113) inst alloc_lfsr_prng_2 of MaxPeriodFibonacciLFSR_11 connect alloc_lfsr_prng_2.clock, clock connect alloc_lfsr_prng_2.reset, reset connect alloc_lfsr_prng_2.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_2.io.seed.bits[0] invalidate alloc_lfsr_prng_2.io.seed.bits[1] invalidate alloc_lfsr_prng_2.io.seed.bits[2] invalidate alloc_lfsr_prng_2.io.seed.bits[3] invalidate alloc_lfsr_prng_2.io.seed.bits[4] invalidate alloc_lfsr_prng_2.io.seed.bits[5] connect alloc_lfsr_prng_2.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_2 = cat(alloc_lfsr_prng_2.io.out[2], alloc_lfsr_prng_2.io.out[1]) node alloc_lfsr_lo_2 = cat(alloc_lfsr_lo_hi_2, alloc_lfsr_prng_2.io.out[0]) node alloc_lfsr_hi_hi_2 = cat(alloc_lfsr_prng_2.io.out[5], alloc_lfsr_prng_2.io.out[4]) node alloc_lfsr_hi_2 = cat(alloc_lfsr_hi_hi_2, alloc_lfsr_prng_2.io.out[3]) node alloc_lfsr_2 = cat(alloc_lfsr_hi_2, alloc_lfsr_lo_2) node _first_entry_T_28 = bits(allocatable_slots_2, 0, 0) node _first_entry_T_29 = bits(allocatable_slots_2, 1, 1) node _first_entry_T_30 = bits(allocatable_slots_2, 2, 2) node _first_entry_T_31 = bits(allocatable_slots_2, 3, 3) node _first_entry_T_32 = bits(allocatable_slots_2, 4, 4) node _first_entry_T_33 = bits(allocatable_slots_2, 5, 5) node _first_entry_T_34 = bits(allocatable_slots_2, 6, 6) node _first_entry_T_35 = bits(allocatable_slots_2, 7, 7) node _first_entry_T_36 = mux(_first_entry_T_34, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_37 = mux(_first_entry_T_33, UInt<3>(0h5), _first_entry_T_36) node _first_entry_T_38 = mux(_first_entry_T_32, UInt<3>(0h4), _first_entry_T_37) node _first_entry_T_39 = mux(_first_entry_T_31, UInt<2>(0h3), _first_entry_T_38) node _first_entry_T_40 = mux(_first_entry_T_30, UInt<2>(0h2), _first_entry_T_39) node _first_entry_T_41 = mux(_first_entry_T_29, UInt<1>(0h1), _first_entry_T_40) node first_entry_2 = mux(_first_entry_T_28, UInt<1>(0h0), _first_entry_T_41) node _masked_entry_T_30 = and(allocatable_slots_2, alloc_lfsr_2) node _masked_entry_T_31 = bits(_masked_entry_T_30, 0, 0) node _masked_entry_T_32 = bits(_masked_entry_T_30, 1, 1) node _masked_entry_T_33 = bits(_masked_entry_T_30, 2, 2) node _masked_entry_T_34 = bits(_masked_entry_T_30, 3, 3) node _masked_entry_T_35 = bits(_masked_entry_T_30, 4, 4) node _masked_entry_T_36 = bits(_masked_entry_T_30, 5, 5) node _masked_entry_T_37 = bits(_masked_entry_T_30, 6, 6) node _masked_entry_T_38 = bits(_masked_entry_T_30, 7, 7) node _masked_entry_T_39 = mux(_masked_entry_T_37, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_40 = mux(_masked_entry_T_36, UInt<3>(0h5), _masked_entry_T_39) node _masked_entry_T_41 = mux(_masked_entry_T_35, UInt<3>(0h4), _masked_entry_T_40) node _masked_entry_T_42 = mux(_masked_entry_T_34, UInt<2>(0h3), _masked_entry_T_41) node _masked_entry_T_43 = mux(_masked_entry_T_33, UInt<2>(0h2), _masked_entry_T_42) node _masked_entry_T_44 = mux(_masked_entry_T_32, UInt<1>(0h1), _masked_entry_T_43) node masked_entry_2 = mux(_masked_entry_T_31, UInt<1>(0h0), _masked_entry_T_44) node _alloc_entry_T_4 = dshr(allocatable_slots_2, masked_entry_2) node _alloc_entry_T_5 = bits(_alloc_entry_T_4, 0, 0) node alloc_entry_2 = mux(_alloc_entry_T_5, masked_entry_2, first_entry_2) node _f3_meta_allocate_2_valid_T = neq(allocatable_slots_2, UInt<1>(0h0)) connect f3_meta.allocate[2].valid, _f3_meta_allocate_2_valid_T connect f3_meta.allocate[2].bits, alloc_entry_2 node _update_was_taken_T_4 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _update_was_taken_T_5 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_4) node update_was_taken_2 = and(_update_was_taken_T_5, s1_update.bits.cfi_taken) node _T_100 = bits(s1_update.bits.br_mask, 2, 2) node _T_101 = and(_T_100, s1_update.valid) node _T_102 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_103 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_104 = or(_T_102, _T_103) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = and(_T_101, _T_105) when _T_106 : when s1_update_meta.provider[2].valid : connect s1_update_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) node _new_u_T_22 = bits(s1_update_mispredict_mask, 2, 2) node _new_u_T_23 = eq(s1_update_meta.alt_differs[2], UInt<1>(0h0)) node _new_u_T_24 = eq(s1_update_meta.provider_u[2], UInt<1>(0h0)) node _new_u_T_25 = sub(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_26 = tail(_new_u_T_25, 1) node _new_u_T_27 = mux(_new_u_T_24, UInt<1>(0h0), _new_u_T_26) node _new_u_T_28 = eq(s1_update_meta.provider_u[2], UInt<2>(0h3)) node _new_u_T_29 = add(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_30 = tail(_new_u_T_29, 1) node _new_u_T_31 = mux(_new_u_T_28, UInt<2>(0h3), _new_u_T_30) node _new_u_T_32 = mux(_new_u_T_22, _new_u_T_27, _new_u_T_31) node new_u_2 = mux(_new_u_T_23, s1_update_meta.provider_u[2], _new_u_T_32) connect s1_update_u[s1_update_meta.provider[2].bits][2], new_u_2 connect s1_update_taken[s1_update_meta.provider[2].bits][2], update_was_taken_2 connect s1_update_old_ctr[s1_update_meta.provider[2].bits][2], s1_update_meta.provider_ctr[2] connect s1_update_alloc[s1_update_meta.provider[2].bits][2], UInt<1>(0h0) wire final_altpred_3 : UInt<1> connect final_altpred_3, io.resp_in[0].f3[3].taken connect io.resp.f3[3].taken, io.resp_in[0].f3[3].taken when f3_resps[0][3].valid : node _io_resp_f3_3_taken_T = eq(f3_resps[0][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_1 = eq(f3_resps[0][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_2 = or(_io_resp_f3_3_taken_T, _io_resp_f3_3_taken_T_1) node _io_resp_f3_3_taken_T_3 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_4 = mux(_io_resp_f3_3_taken_T_2, io.resp_in[0].f3[3].taken, _io_resp_f3_3_taken_T_3) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_4 connect final_altpred_3, io.resp_in[0].f3[3].taken node _T_107 = or(UInt<1>(0h0), f3_resps[0][3].valid) node _T_108 = mux(f3_resps[0][3].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_109 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _T_110 = mux(f3_resps[0][3].valid, _T_109, io.resp_in[0].f3[3].taken) when f3_resps[1][3].valid : node _io_resp_f3_3_taken_T_5 = eq(f3_resps[1][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_6 = eq(f3_resps[1][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_7 = or(_io_resp_f3_3_taken_T_5, _io_resp_f3_3_taken_T_6) node _io_resp_f3_3_taken_T_8 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_9 = mux(_io_resp_f3_3_taken_T_7, _T_110, _io_resp_f3_3_taken_T_8) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_9 connect final_altpred_3, _T_110 node _T_111 = or(_T_107, f3_resps[1][3].valid) node _T_112 = mux(f3_resps[1][3].valid, UInt<1>(0h1), _T_108) node _T_113 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _T_114 = mux(f3_resps[1][3].valid, _T_113, _T_110) when f3_resps[2][3].valid : node _io_resp_f3_3_taken_T_10 = eq(f3_resps[2][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_11 = eq(f3_resps[2][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_12 = or(_io_resp_f3_3_taken_T_10, _io_resp_f3_3_taken_T_11) node _io_resp_f3_3_taken_T_13 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_14 = mux(_io_resp_f3_3_taken_T_12, _T_114, _io_resp_f3_3_taken_T_13) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_14 connect final_altpred_3, _T_114 node _T_115 = or(_T_111, f3_resps[2][3].valid) node _T_116 = mux(f3_resps[2][3].valid, UInt<2>(0h2), _T_112) node _T_117 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _T_118 = mux(f3_resps[2][3].valid, _T_117, _T_114) when f3_resps[3][3].valid : node _io_resp_f3_3_taken_T_15 = eq(f3_resps[3][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_16 = eq(f3_resps[3][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_17 = or(_io_resp_f3_3_taken_T_15, _io_resp_f3_3_taken_T_16) node _io_resp_f3_3_taken_T_18 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_19 = mux(_io_resp_f3_3_taken_T_17, _T_118, _io_resp_f3_3_taken_T_18) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_19 connect final_altpred_3, _T_118 node _T_119 = or(_T_115, f3_resps[3][3].valid) node _T_120 = mux(f3_resps[3][3].valid, UInt<2>(0h3), _T_116) node _T_121 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _T_122 = mux(f3_resps[3][3].valid, _T_121, _T_118) when f3_resps[4][3].valid : node _io_resp_f3_3_taken_T_20 = eq(f3_resps[4][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_21 = eq(f3_resps[4][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_22 = or(_io_resp_f3_3_taken_T_20, _io_resp_f3_3_taken_T_21) node _io_resp_f3_3_taken_T_23 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_24 = mux(_io_resp_f3_3_taken_T_22, _T_122, _io_resp_f3_3_taken_T_23) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_24 connect final_altpred_3, _T_122 node _T_123 = or(_T_119, f3_resps[4][3].valid) node _T_124 = mux(f3_resps[4][3].valid, UInt<3>(0h4), _T_120) node _T_125 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _T_126 = mux(f3_resps[4][3].valid, _T_125, _T_122) when f3_resps[5][3].valid : node _io_resp_f3_3_taken_T_25 = eq(f3_resps[5][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_26 = eq(f3_resps[5][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_27 = or(_io_resp_f3_3_taken_T_25, _io_resp_f3_3_taken_T_26) node _io_resp_f3_3_taken_T_28 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_29 = mux(_io_resp_f3_3_taken_T_27, _T_126, _io_resp_f3_3_taken_T_28) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_29 connect final_altpred_3, _T_126 node _T_127 = or(_T_123, f3_resps[5][3].valid) node _T_128 = mux(f3_resps[5][3].valid, UInt<3>(0h5), _T_124) node _T_129 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _T_130 = mux(f3_resps[5][3].valid, _T_129, _T_126) connect f3_meta.provider[3].valid, _T_127 connect f3_meta.provider[3].bits, _T_128 node _f3_meta_alt_differs_3_T = neq(final_altpred_3, io.resp.f3[3].taken) connect f3_meta.alt_differs[3], _f3_meta_alt_differs_3_T connect f3_meta.provider_u[3], f3_resps[_T_128][3].bits.u connect f3_meta.provider_ctr[3], f3_resps[_T_128][3].bits.ctr node _allocatable_slots_T_114 = eq(f3_resps[0][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_115 = eq(f3_resps[0][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_116 = and(_allocatable_slots_T_114, _allocatable_slots_T_115) node _allocatable_slots_T_117 = eq(f3_resps[1][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_118 = eq(f3_resps[1][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_119 = and(_allocatable_slots_T_117, _allocatable_slots_T_118) node _allocatable_slots_T_120 = eq(f3_resps[2][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_121 = eq(f3_resps[2][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_122 = and(_allocatable_slots_T_120, _allocatable_slots_T_121) node _allocatable_slots_T_123 = eq(f3_resps[3][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_124 = eq(f3_resps[3][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_125 = and(_allocatable_slots_T_123, _allocatable_slots_T_124) node _allocatable_slots_T_126 = eq(f3_resps[4][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_127 = eq(f3_resps[4][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_128 = and(_allocatable_slots_T_126, _allocatable_slots_T_127) node _allocatable_slots_T_129 = eq(f3_resps[5][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_130 = eq(f3_resps[5][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_131 = and(_allocatable_slots_T_129, _allocatable_slots_T_130) wire _allocatable_slots_WIRE_3 : UInt<1>[6] connect _allocatable_slots_WIRE_3[0], _allocatable_slots_T_116 connect _allocatable_slots_WIRE_3[1], _allocatable_slots_T_119 connect _allocatable_slots_WIRE_3[2], _allocatable_slots_T_122 connect _allocatable_slots_WIRE_3[3], _allocatable_slots_T_125 connect _allocatable_slots_WIRE_3[4], _allocatable_slots_T_128 connect _allocatable_slots_WIRE_3[5], _allocatable_slots_T_131 node allocatable_slots_lo_hi_3 = cat(_allocatable_slots_WIRE_3[2], _allocatable_slots_WIRE_3[1]) node allocatable_slots_lo_3 = cat(allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3[0]) node allocatable_slots_hi_hi_3 = cat(_allocatable_slots_WIRE_3[5], _allocatable_slots_WIRE_3[4]) node allocatable_slots_hi_3 = cat(allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3[3]) node _allocatable_slots_T_132 = cat(allocatable_slots_hi_3, allocatable_slots_lo_3) node _allocatable_slots_T_133 = dshl(UInt<1>(0h1), _T_128) node _allocatable_slots_T_134 = dshr(_allocatable_slots_T_133, UInt<1>(0h0)) node _allocatable_slots_T_135 = dshr(_allocatable_slots_T_133, UInt<1>(0h1)) node _allocatable_slots_T_136 = dshr(_allocatable_slots_T_133, UInt<2>(0h2)) node _allocatable_slots_T_137 = dshr(_allocatable_slots_T_133, UInt<2>(0h3)) node _allocatable_slots_T_138 = dshr(_allocatable_slots_T_133, UInt<3>(0h4)) node _allocatable_slots_T_139 = dshr(_allocatable_slots_T_133, UInt<3>(0h5)) node _allocatable_slots_T_140 = dshr(_allocatable_slots_T_133, UInt<3>(0h6)) node _allocatable_slots_T_141 = dshr(_allocatable_slots_T_133, UInt<3>(0h7)) node _allocatable_slots_T_142 = or(_allocatable_slots_T_134, _allocatable_slots_T_135) node _allocatable_slots_T_143 = or(_allocatable_slots_T_142, _allocatable_slots_T_136) node _allocatable_slots_T_144 = or(_allocatable_slots_T_143, _allocatable_slots_T_137) node _allocatable_slots_T_145 = or(_allocatable_slots_T_144, _allocatable_slots_T_138) node _allocatable_slots_T_146 = or(_allocatable_slots_T_145, _allocatable_slots_T_139) node _allocatable_slots_T_147 = or(_allocatable_slots_T_146, _allocatable_slots_T_140) node _allocatable_slots_T_148 = or(_allocatable_slots_T_147, _allocatable_slots_T_141) node _allocatable_slots_T_149 = mux(_T_127, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_150 = and(_allocatable_slots_T_148, _allocatable_slots_T_149) node _allocatable_slots_T_151 = not(_allocatable_slots_T_150) node allocatable_slots_3 = and(_allocatable_slots_T_132, _allocatable_slots_T_151) inst alloc_lfsr_prng_3 of MaxPeriodFibonacciLFSR_12 connect alloc_lfsr_prng_3.clock, clock connect alloc_lfsr_prng_3.reset, reset connect alloc_lfsr_prng_3.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_3.io.seed.bits[0] invalidate alloc_lfsr_prng_3.io.seed.bits[1] invalidate alloc_lfsr_prng_3.io.seed.bits[2] invalidate alloc_lfsr_prng_3.io.seed.bits[3] invalidate alloc_lfsr_prng_3.io.seed.bits[4] invalidate alloc_lfsr_prng_3.io.seed.bits[5] connect alloc_lfsr_prng_3.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_3 = cat(alloc_lfsr_prng_3.io.out[2], alloc_lfsr_prng_3.io.out[1]) node alloc_lfsr_lo_3 = cat(alloc_lfsr_lo_hi_3, alloc_lfsr_prng_3.io.out[0]) node alloc_lfsr_hi_hi_3 = cat(alloc_lfsr_prng_3.io.out[5], alloc_lfsr_prng_3.io.out[4]) node alloc_lfsr_hi_3 = cat(alloc_lfsr_hi_hi_3, alloc_lfsr_prng_3.io.out[3]) node alloc_lfsr_3 = cat(alloc_lfsr_hi_3, alloc_lfsr_lo_3) node _first_entry_T_42 = bits(allocatable_slots_3, 0, 0) node _first_entry_T_43 = bits(allocatable_slots_3, 1, 1) node _first_entry_T_44 = bits(allocatable_slots_3, 2, 2) node _first_entry_T_45 = bits(allocatable_slots_3, 3, 3) node _first_entry_T_46 = bits(allocatable_slots_3, 4, 4) node _first_entry_T_47 = bits(allocatable_slots_3, 5, 5) node _first_entry_T_48 = bits(allocatable_slots_3, 6, 6) node _first_entry_T_49 = bits(allocatable_slots_3, 7, 7) node _first_entry_T_50 = mux(_first_entry_T_48, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_51 = mux(_first_entry_T_47, UInt<3>(0h5), _first_entry_T_50) node _first_entry_T_52 = mux(_first_entry_T_46, UInt<3>(0h4), _first_entry_T_51) node _first_entry_T_53 = mux(_first_entry_T_45, UInt<2>(0h3), _first_entry_T_52) node _first_entry_T_54 = mux(_first_entry_T_44, UInt<2>(0h2), _first_entry_T_53) node _first_entry_T_55 = mux(_first_entry_T_43, UInt<1>(0h1), _first_entry_T_54) node first_entry_3 = mux(_first_entry_T_42, UInt<1>(0h0), _first_entry_T_55) node _masked_entry_T_45 = and(allocatable_slots_3, alloc_lfsr_3) node _masked_entry_T_46 = bits(_masked_entry_T_45, 0, 0) node _masked_entry_T_47 = bits(_masked_entry_T_45, 1, 1) node _masked_entry_T_48 = bits(_masked_entry_T_45, 2, 2) node _masked_entry_T_49 = bits(_masked_entry_T_45, 3, 3) node _masked_entry_T_50 = bits(_masked_entry_T_45, 4, 4) node _masked_entry_T_51 = bits(_masked_entry_T_45, 5, 5) node _masked_entry_T_52 = bits(_masked_entry_T_45, 6, 6) node _masked_entry_T_53 = bits(_masked_entry_T_45, 7, 7) node _masked_entry_T_54 = mux(_masked_entry_T_52, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_55 = mux(_masked_entry_T_51, UInt<3>(0h5), _masked_entry_T_54) node _masked_entry_T_56 = mux(_masked_entry_T_50, UInt<3>(0h4), _masked_entry_T_55) node _masked_entry_T_57 = mux(_masked_entry_T_49, UInt<2>(0h3), _masked_entry_T_56) node _masked_entry_T_58 = mux(_masked_entry_T_48, UInt<2>(0h2), _masked_entry_T_57) node _masked_entry_T_59 = mux(_masked_entry_T_47, UInt<1>(0h1), _masked_entry_T_58) node masked_entry_3 = mux(_masked_entry_T_46, UInt<1>(0h0), _masked_entry_T_59) node _alloc_entry_T_6 = dshr(allocatable_slots_3, masked_entry_3) node _alloc_entry_T_7 = bits(_alloc_entry_T_6, 0, 0) node alloc_entry_3 = mux(_alloc_entry_T_7, masked_entry_3, first_entry_3) node _f3_meta_allocate_3_valid_T = neq(allocatable_slots_3, UInt<1>(0h0)) connect f3_meta.allocate[3].valid, _f3_meta_allocate_3_valid_T connect f3_meta.allocate[3].bits, alloc_entry_3 node _update_was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _update_was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_6) node update_was_taken_3 = and(_update_was_taken_T_7, s1_update.bits.cfi_taken) node _T_131 = bits(s1_update.bits.br_mask, 3, 3) node _T_132 = and(_T_131, s1_update.valid) node _T_133 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_134 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_135 = or(_T_133, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = and(_T_132, _T_136) when _T_137 : when s1_update_meta.provider[3].valid : connect s1_update_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) node _new_u_T_33 = bits(s1_update_mispredict_mask, 3, 3) node _new_u_T_34 = eq(s1_update_meta.alt_differs[3], UInt<1>(0h0)) node _new_u_T_35 = eq(s1_update_meta.provider_u[3], UInt<1>(0h0)) node _new_u_T_36 = sub(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_37 = tail(_new_u_T_36, 1) node _new_u_T_38 = mux(_new_u_T_35, UInt<1>(0h0), _new_u_T_37) node _new_u_T_39 = eq(s1_update_meta.provider_u[3], UInt<2>(0h3)) node _new_u_T_40 = add(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_41 = tail(_new_u_T_40, 1) node _new_u_T_42 = mux(_new_u_T_39, UInt<2>(0h3), _new_u_T_41) node _new_u_T_43 = mux(_new_u_T_33, _new_u_T_38, _new_u_T_42) node new_u_3 = mux(_new_u_T_34, s1_update_meta.provider_u[3], _new_u_T_43) connect s1_update_u[s1_update_meta.provider[3].bits][3], new_u_3 connect s1_update_taken[s1_update_meta.provider[3].bits][3], update_was_taken_3 connect s1_update_old_ctr[s1_update_meta.provider[3].bits][3], s1_update_meta.provider_ctr[3] connect s1_update_alloc[s1_update_meta.provider[3].bits][3], UInt<1>(0h0) node _T_138 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_139 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_140 = or(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = and(s1_update.valid, _T_141) node _T_143 = and(_T_142, s1_update.bits.cfi_mispredicted) node _T_144 = and(_T_143, s1_update.bits.cfi_idx.valid) when _T_144 : when s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].valid : connect s1_update_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_taken[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], s1_update.bits.cfi_taken connect s1_update_alloc[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) else : node _decr_mask_T = dshl(UInt<1>(0h1), s1_update_meta.provider[s1_update.bits.cfi_idx.bits].bits) node _decr_mask_T_1 = dshr(_decr_mask_T, UInt<1>(0h0)) node _decr_mask_T_2 = dshr(_decr_mask_T, UInt<1>(0h1)) node _decr_mask_T_3 = dshr(_decr_mask_T, UInt<2>(0h2)) node _decr_mask_T_4 = dshr(_decr_mask_T, UInt<2>(0h3)) node _decr_mask_T_5 = dshr(_decr_mask_T, UInt<3>(0h4)) node _decr_mask_T_6 = dshr(_decr_mask_T, UInt<3>(0h5)) node _decr_mask_T_7 = dshr(_decr_mask_T, UInt<3>(0h6)) node _decr_mask_T_8 = dshr(_decr_mask_T, UInt<3>(0h7)) node _decr_mask_T_9 = or(_decr_mask_T_1, _decr_mask_T_2) node _decr_mask_T_10 = or(_decr_mask_T_9, _decr_mask_T_3) node _decr_mask_T_11 = or(_decr_mask_T_10, _decr_mask_T_4) node _decr_mask_T_12 = or(_decr_mask_T_11, _decr_mask_T_5) node _decr_mask_T_13 = or(_decr_mask_T_12, _decr_mask_T_6) node _decr_mask_T_14 = or(_decr_mask_T_13, _decr_mask_T_7) node _decr_mask_T_15 = or(_decr_mask_T_14, _decr_mask_T_8) node _decr_mask_T_16 = not(_decr_mask_T_15) node decr_mask = mux(s1_update_meta.provider[s1_update.bits.cfi_idx.bits].valid, _decr_mask_T_16, UInt<1>(0h0)) node _T_145 = bits(decr_mask, 0, 0) when _T_145 : connect s1_update_u_mask[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_146 = bits(decr_mask, 1, 1) when _T_146 : connect s1_update_u_mask[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_147 = bits(decr_mask, 2, 2) when _T_147 : connect s1_update_u_mask[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_148 = bits(decr_mask, 3, 3) when _T_148 : connect s1_update_u_mask[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_149 = bits(decr_mask, 4, 4) when _T_149 : connect s1_update_u_mask[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_150 = bits(decr_mask, 5, 5) when _T_150 : connect s1_update_u_mask[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) reg tt_0_1_io_update_mask_0_REG : UInt<1>, clock connect tt_0_1_io_update_mask_0_REG, s1_update_mask[0][0] connect tt_0_1.io.update_mask[0], tt_0_1_io_update_mask_0_REG reg tt_0_1_io_update_taken_0_REG : UInt<1>, clock connect tt_0_1_io_update_taken_0_REG, s1_update_taken[0][0] connect tt_0_1.io.update_taken[0], tt_0_1_io_update_taken_0_REG reg tt_0_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_0_REG, s1_update_alloc[0][0] connect tt_0_1.io.update_alloc[0], tt_0_1_io_update_alloc_0_REG reg tt_0_1_io_update_old_ctr_0_REG : UInt, clock connect tt_0_1_io_update_old_ctr_0_REG, s1_update_old_ctr[0][0] connect tt_0_1.io.update_old_ctr[0], tt_0_1_io_update_old_ctr_0_REG reg tt_0_1_io_update_u_mask_0_REG : UInt, clock connect tt_0_1_io_update_u_mask_0_REG, s1_update_u_mask[0][0] connect tt_0_1.io.update_u_mask[0], tt_0_1_io_update_u_mask_0_REG reg tt_0_1_io_update_u_0_REG : UInt, clock connect tt_0_1_io_update_u_0_REG, s1_update_u[0][0] connect tt_0_1.io.update_u[0], tt_0_1_io_update_u_0_REG reg tt_0_1_io_update_mask_1_REG : UInt<1>, clock connect tt_0_1_io_update_mask_1_REG, s1_update_mask[0][1] connect tt_0_1.io.update_mask[1], tt_0_1_io_update_mask_1_REG reg tt_0_1_io_update_taken_1_REG : UInt<1>, clock connect tt_0_1_io_update_taken_1_REG, s1_update_taken[0][1] connect tt_0_1.io.update_taken[1], tt_0_1_io_update_taken_1_REG reg tt_0_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_1_REG, s1_update_alloc[0][1] connect tt_0_1.io.update_alloc[1], tt_0_1_io_update_alloc_1_REG reg tt_0_1_io_update_old_ctr_1_REG : UInt, clock connect tt_0_1_io_update_old_ctr_1_REG, s1_update_old_ctr[0][1] connect tt_0_1.io.update_old_ctr[1], tt_0_1_io_update_old_ctr_1_REG reg tt_0_1_io_update_u_mask_1_REG : UInt, clock connect tt_0_1_io_update_u_mask_1_REG, s1_update_u_mask[0][1] connect tt_0_1.io.update_u_mask[1], tt_0_1_io_update_u_mask_1_REG reg tt_0_1_io_update_u_1_REG : UInt, clock connect tt_0_1_io_update_u_1_REG, s1_update_u[0][1] connect tt_0_1.io.update_u[1], tt_0_1_io_update_u_1_REG reg tt_0_1_io_update_mask_2_REG : UInt<1>, clock connect tt_0_1_io_update_mask_2_REG, s1_update_mask[0][2] connect tt_0_1.io.update_mask[2], tt_0_1_io_update_mask_2_REG reg tt_0_1_io_update_taken_2_REG : UInt<1>, clock connect tt_0_1_io_update_taken_2_REG, s1_update_taken[0][2] connect tt_0_1.io.update_taken[2], tt_0_1_io_update_taken_2_REG reg tt_0_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_2_REG, s1_update_alloc[0][2] connect tt_0_1.io.update_alloc[2], tt_0_1_io_update_alloc_2_REG reg tt_0_1_io_update_old_ctr_2_REG : UInt, clock connect tt_0_1_io_update_old_ctr_2_REG, s1_update_old_ctr[0][2] connect tt_0_1.io.update_old_ctr[2], tt_0_1_io_update_old_ctr_2_REG reg tt_0_1_io_update_u_mask_2_REG : UInt, clock connect tt_0_1_io_update_u_mask_2_REG, s1_update_u_mask[0][2] connect tt_0_1.io.update_u_mask[2], tt_0_1_io_update_u_mask_2_REG reg tt_0_1_io_update_u_2_REG : UInt, clock connect tt_0_1_io_update_u_2_REG, s1_update_u[0][2] connect tt_0_1.io.update_u[2], tt_0_1_io_update_u_2_REG reg tt_0_1_io_update_mask_3_REG : UInt<1>, clock connect tt_0_1_io_update_mask_3_REG, s1_update_mask[0][3] connect tt_0_1.io.update_mask[3], tt_0_1_io_update_mask_3_REG reg tt_0_1_io_update_taken_3_REG : UInt<1>, clock connect tt_0_1_io_update_taken_3_REG, s1_update_taken[0][3] connect tt_0_1.io.update_taken[3], tt_0_1_io_update_taken_3_REG reg tt_0_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_3_REG, s1_update_alloc[0][3] connect tt_0_1.io.update_alloc[3], tt_0_1_io_update_alloc_3_REG reg tt_0_1_io_update_old_ctr_3_REG : UInt, clock connect tt_0_1_io_update_old_ctr_3_REG, s1_update_old_ctr[0][3] connect tt_0_1.io.update_old_ctr[3], tt_0_1_io_update_old_ctr_3_REG reg tt_0_1_io_update_u_mask_3_REG : UInt, clock connect tt_0_1_io_update_u_mask_3_REG, s1_update_u_mask[0][3] connect tt_0_1.io.update_u_mask[3], tt_0_1_io_update_u_mask_3_REG reg tt_0_1_io_update_u_3_REG : UInt, clock connect tt_0_1_io_update_u_3_REG, s1_update_u[0][3] connect tt_0_1.io.update_u[3], tt_0_1_io_update_u_3_REG reg tt_0_1_io_update_pc_REG : UInt, clock connect tt_0_1_io_update_pc_REG, s1_update.bits.pc connect tt_0_1.io.update_pc, tt_0_1_io_update_pc_REG reg tt_0_1_io_update_hist_REG : UInt, clock connect tt_0_1_io_update_hist_REG, s1_update.bits.ghist connect tt_0_1.io.update_hist, tt_0_1_io_update_hist_REG reg tt_1_1_io_update_mask_0_REG : UInt<1>, clock connect tt_1_1_io_update_mask_0_REG, s1_update_mask[1][0] connect tt_1_1.io.update_mask[0], tt_1_1_io_update_mask_0_REG reg tt_1_1_io_update_taken_0_REG : UInt<1>, clock connect tt_1_1_io_update_taken_0_REG, s1_update_taken[1][0] connect tt_1_1.io.update_taken[0], tt_1_1_io_update_taken_0_REG reg tt_1_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_0_REG, s1_update_alloc[1][0] connect tt_1_1.io.update_alloc[0], tt_1_1_io_update_alloc_0_REG reg tt_1_1_io_update_old_ctr_0_REG : UInt, clock connect tt_1_1_io_update_old_ctr_0_REG, s1_update_old_ctr[1][0] connect tt_1_1.io.update_old_ctr[0], tt_1_1_io_update_old_ctr_0_REG reg tt_1_1_io_update_u_mask_0_REG : UInt, clock connect tt_1_1_io_update_u_mask_0_REG, s1_update_u_mask[1][0] connect tt_1_1.io.update_u_mask[0], tt_1_1_io_update_u_mask_0_REG reg tt_1_1_io_update_u_0_REG : UInt, clock connect tt_1_1_io_update_u_0_REG, s1_update_u[1][0] connect tt_1_1.io.update_u[0], tt_1_1_io_update_u_0_REG reg tt_1_1_io_update_mask_1_REG : UInt<1>, clock connect tt_1_1_io_update_mask_1_REG, s1_update_mask[1][1] connect tt_1_1.io.update_mask[1], tt_1_1_io_update_mask_1_REG reg tt_1_1_io_update_taken_1_REG : UInt<1>, clock connect tt_1_1_io_update_taken_1_REG, s1_update_taken[1][1] connect tt_1_1.io.update_taken[1], tt_1_1_io_update_taken_1_REG reg tt_1_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_1_REG, s1_update_alloc[1][1] connect tt_1_1.io.update_alloc[1], tt_1_1_io_update_alloc_1_REG reg tt_1_1_io_update_old_ctr_1_REG : UInt, clock connect tt_1_1_io_update_old_ctr_1_REG, s1_update_old_ctr[1][1] connect tt_1_1.io.update_old_ctr[1], tt_1_1_io_update_old_ctr_1_REG reg tt_1_1_io_update_u_mask_1_REG : UInt, clock connect tt_1_1_io_update_u_mask_1_REG, s1_update_u_mask[1][1] connect tt_1_1.io.update_u_mask[1], tt_1_1_io_update_u_mask_1_REG reg tt_1_1_io_update_u_1_REG : UInt, clock connect tt_1_1_io_update_u_1_REG, s1_update_u[1][1] connect tt_1_1.io.update_u[1], tt_1_1_io_update_u_1_REG reg tt_1_1_io_update_mask_2_REG : UInt<1>, clock connect tt_1_1_io_update_mask_2_REG, s1_update_mask[1][2] connect tt_1_1.io.update_mask[2], tt_1_1_io_update_mask_2_REG reg tt_1_1_io_update_taken_2_REG : UInt<1>, clock connect tt_1_1_io_update_taken_2_REG, s1_update_taken[1][2] connect tt_1_1.io.update_taken[2], tt_1_1_io_update_taken_2_REG reg tt_1_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_2_REG, s1_update_alloc[1][2] connect tt_1_1.io.update_alloc[2], tt_1_1_io_update_alloc_2_REG reg tt_1_1_io_update_old_ctr_2_REG : UInt, clock connect tt_1_1_io_update_old_ctr_2_REG, s1_update_old_ctr[1][2] connect tt_1_1.io.update_old_ctr[2], tt_1_1_io_update_old_ctr_2_REG reg tt_1_1_io_update_u_mask_2_REG : UInt, clock connect tt_1_1_io_update_u_mask_2_REG, s1_update_u_mask[1][2] connect tt_1_1.io.update_u_mask[2], tt_1_1_io_update_u_mask_2_REG reg tt_1_1_io_update_u_2_REG : UInt, clock connect tt_1_1_io_update_u_2_REG, s1_update_u[1][2] connect tt_1_1.io.update_u[2], tt_1_1_io_update_u_2_REG reg tt_1_1_io_update_mask_3_REG : UInt<1>, clock connect tt_1_1_io_update_mask_3_REG, s1_update_mask[1][3] connect tt_1_1.io.update_mask[3], tt_1_1_io_update_mask_3_REG reg tt_1_1_io_update_taken_3_REG : UInt<1>, clock connect tt_1_1_io_update_taken_3_REG, s1_update_taken[1][3] connect tt_1_1.io.update_taken[3], tt_1_1_io_update_taken_3_REG reg tt_1_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_3_REG, s1_update_alloc[1][3] connect tt_1_1.io.update_alloc[3], tt_1_1_io_update_alloc_3_REG reg tt_1_1_io_update_old_ctr_3_REG : UInt, clock connect tt_1_1_io_update_old_ctr_3_REG, s1_update_old_ctr[1][3] connect tt_1_1.io.update_old_ctr[3], tt_1_1_io_update_old_ctr_3_REG reg tt_1_1_io_update_u_mask_3_REG : UInt, clock connect tt_1_1_io_update_u_mask_3_REG, s1_update_u_mask[1][3] connect tt_1_1.io.update_u_mask[3], tt_1_1_io_update_u_mask_3_REG reg tt_1_1_io_update_u_3_REG : UInt, clock connect tt_1_1_io_update_u_3_REG, s1_update_u[1][3] connect tt_1_1.io.update_u[3], tt_1_1_io_update_u_3_REG reg tt_1_1_io_update_pc_REG : UInt, clock connect tt_1_1_io_update_pc_REG, s1_update.bits.pc connect tt_1_1.io.update_pc, tt_1_1_io_update_pc_REG reg tt_1_1_io_update_hist_REG : UInt, clock connect tt_1_1_io_update_hist_REG, s1_update.bits.ghist connect tt_1_1.io.update_hist, tt_1_1_io_update_hist_REG reg tt_2_1_io_update_mask_0_REG : UInt<1>, clock connect tt_2_1_io_update_mask_0_REG, s1_update_mask[2][0] connect tt_2_1.io.update_mask[0], tt_2_1_io_update_mask_0_REG reg tt_2_1_io_update_taken_0_REG : UInt<1>, clock connect tt_2_1_io_update_taken_0_REG, s1_update_taken[2][0] connect tt_2_1.io.update_taken[0], tt_2_1_io_update_taken_0_REG reg tt_2_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_0_REG, s1_update_alloc[2][0] connect tt_2_1.io.update_alloc[0], tt_2_1_io_update_alloc_0_REG reg tt_2_1_io_update_old_ctr_0_REG : UInt, clock connect tt_2_1_io_update_old_ctr_0_REG, s1_update_old_ctr[2][0] connect tt_2_1.io.update_old_ctr[0], tt_2_1_io_update_old_ctr_0_REG reg tt_2_1_io_update_u_mask_0_REG : UInt, clock connect tt_2_1_io_update_u_mask_0_REG, s1_update_u_mask[2][0] connect tt_2_1.io.update_u_mask[0], tt_2_1_io_update_u_mask_0_REG reg tt_2_1_io_update_u_0_REG : UInt, clock connect tt_2_1_io_update_u_0_REG, s1_update_u[2][0] connect tt_2_1.io.update_u[0], tt_2_1_io_update_u_0_REG reg tt_2_1_io_update_mask_1_REG : UInt<1>, clock connect tt_2_1_io_update_mask_1_REG, s1_update_mask[2][1] connect tt_2_1.io.update_mask[1], tt_2_1_io_update_mask_1_REG reg tt_2_1_io_update_taken_1_REG : UInt<1>, clock connect tt_2_1_io_update_taken_1_REG, s1_update_taken[2][1] connect tt_2_1.io.update_taken[1], tt_2_1_io_update_taken_1_REG reg tt_2_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_1_REG, s1_update_alloc[2][1] connect tt_2_1.io.update_alloc[1], tt_2_1_io_update_alloc_1_REG reg tt_2_1_io_update_old_ctr_1_REG : UInt, clock connect tt_2_1_io_update_old_ctr_1_REG, s1_update_old_ctr[2][1] connect tt_2_1.io.update_old_ctr[1], tt_2_1_io_update_old_ctr_1_REG reg tt_2_1_io_update_u_mask_1_REG : UInt, clock connect tt_2_1_io_update_u_mask_1_REG, s1_update_u_mask[2][1] connect tt_2_1.io.update_u_mask[1], tt_2_1_io_update_u_mask_1_REG reg tt_2_1_io_update_u_1_REG : UInt, clock connect tt_2_1_io_update_u_1_REG, s1_update_u[2][1] connect tt_2_1.io.update_u[1], tt_2_1_io_update_u_1_REG reg tt_2_1_io_update_mask_2_REG : UInt<1>, clock connect tt_2_1_io_update_mask_2_REG, s1_update_mask[2][2] connect tt_2_1.io.update_mask[2], tt_2_1_io_update_mask_2_REG reg tt_2_1_io_update_taken_2_REG : UInt<1>, clock connect tt_2_1_io_update_taken_2_REG, s1_update_taken[2][2] connect tt_2_1.io.update_taken[2], tt_2_1_io_update_taken_2_REG reg tt_2_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_2_REG, s1_update_alloc[2][2] connect tt_2_1.io.update_alloc[2], tt_2_1_io_update_alloc_2_REG reg tt_2_1_io_update_old_ctr_2_REG : UInt, clock connect tt_2_1_io_update_old_ctr_2_REG, s1_update_old_ctr[2][2] connect tt_2_1.io.update_old_ctr[2], tt_2_1_io_update_old_ctr_2_REG reg tt_2_1_io_update_u_mask_2_REG : UInt, clock connect tt_2_1_io_update_u_mask_2_REG, s1_update_u_mask[2][2] connect tt_2_1.io.update_u_mask[2], tt_2_1_io_update_u_mask_2_REG reg tt_2_1_io_update_u_2_REG : UInt, clock connect tt_2_1_io_update_u_2_REG, s1_update_u[2][2] connect tt_2_1.io.update_u[2], tt_2_1_io_update_u_2_REG reg tt_2_1_io_update_mask_3_REG : UInt<1>, clock connect tt_2_1_io_update_mask_3_REG, s1_update_mask[2][3] connect tt_2_1.io.update_mask[3], tt_2_1_io_update_mask_3_REG reg tt_2_1_io_update_taken_3_REG : UInt<1>, clock connect tt_2_1_io_update_taken_3_REG, s1_update_taken[2][3] connect tt_2_1.io.update_taken[3], tt_2_1_io_update_taken_3_REG reg tt_2_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_3_REG, s1_update_alloc[2][3] connect tt_2_1.io.update_alloc[3], tt_2_1_io_update_alloc_3_REG reg tt_2_1_io_update_old_ctr_3_REG : UInt, clock connect tt_2_1_io_update_old_ctr_3_REG, s1_update_old_ctr[2][3] connect tt_2_1.io.update_old_ctr[3], tt_2_1_io_update_old_ctr_3_REG reg tt_2_1_io_update_u_mask_3_REG : UInt, clock connect tt_2_1_io_update_u_mask_3_REG, s1_update_u_mask[2][3] connect tt_2_1.io.update_u_mask[3], tt_2_1_io_update_u_mask_3_REG reg tt_2_1_io_update_u_3_REG : UInt, clock connect tt_2_1_io_update_u_3_REG, s1_update_u[2][3] connect tt_2_1.io.update_u[3], tt_2_1_io_update_u_3_REG reg tt_2_1_io_update_pc_REG : UInt, clock connect tt_2_1_io_update_pc_REG, s1_update.bits.pc connect tt_2_1.io.update_pc, tt_2_1_io_update_pc_REG reg tt_2_1_io_update_hist_REG : UInt, clock connect tt_2_1_io_update_hist_REG, s1_update.bits.ghist connect tt_2_1.io.update_hist, tt_2_1_io_update_hist_REG reg tt_3_1_io_update_mask_0_REG : UInt<1>, clock connect tt_3_1_io_update_mask_0_REG, s1_update_mask[3][0] connect tt_3_1.io.update_mask[0], tt_3_1_io_update_mask_0_REG reg tt_3_1_io_update_taken_0_REG : UInt<1>, clock connect tt_3_1_io_update_taken_0_REG, s1_update_taken[3][0] connect tt_3_1.io.update_taken[0], tt_3_1_io_update_taken_0_REG reg tt_3_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_0_REG, s1_update_alloc[3][0] connect tt_3_1.io.update_alloc[0], tt_3_1_io_update_alloc_0_REG reg tt_3_1_io_update_old_ctr_0_REG : UInt, clock connect tt_3_1_io_update_old_ctr_0_REG, s1_update_old_ctr[3][0] connect tt_3_1.io.update_old_ctr[0], tt_3_1_io_update_old_ctr_0_REG reg tt_3_1_io_update_u_mask_0_REG : UInt, clock connect tt_3_1_io_update_u_mask_0_REG, s1_update_u_mask[3][0] connect tt_3_1.io.update_u_mask[0], tt_3_1_io_update_u_mask_0_REG reg tt_3_1_io_update_u_0_REG : UInt, clock connect tt_3_1_io_update_u_0_REG, s1_update_u[3][0] connect tt_3_1.io.update_u[0], tt_3_1_io_update_u_0_REG reg tt_3_1_io_update_mask_1_REG : UInt<1>, clock connect tt_3_1_io_update_mask_1_REG, s1_update_mask[3][1] connect tt_3_1.io.update_mask[1], tt_3_1_io_update_mask_1_REG reg tt_3_1_io_update_taken_1_REG : UInt<1>, clock connect tt_3_1_io_update_taken_1_REG, s1_update_taken[3][1] connect tt_3_1.io.update_taken[1], tt_3_1_io_update_taken_1_REG reg tt_3_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_1_REG, s1_update_alloc[3][1] connect tt_3_1.io.update_alloc[1], tt_3_1_io_update_alloc_1_REG reg tt_3_1_io_update_old_ctr_1_REG : UInt, clock connect tt_3_1_io_update_old_ctr_1_REG, s1_update_old_ctr[3][1] connect tt_3_1.io.update_old_ctr[1], tt_3_1_io_update_old_ctr_1_REG reg tt_3_1_io_update_u_mask_1_REG : UInt, clock connect tt_3_1_io_update_u_mask_1_REG, s1_update_u_mask[3][1] connect tt_3_1.io.update_u_mask[1], tt_3_1_io_update_u_mask_1_REG reg tt_3_1_io_update_u_1_REG : UInt, clock connect tt_3_1_io_update_u_1_REG, s1_update_u[3][1] connect tt_3_1.io.update_u[1], tt_3_1_io_update_u_1_REG reg tt_3_1_io_update_mask_2_REG : UInt<1>, clock connect tt_3_1_io_update_mask_2_REG, s1_update_mask[3][2] connect tt_3_1.io.update_mask[2], tt_3_1_io_update_mask_2_REG reg tt_3_1_io_update_taken_2_REG : UInt<1>, clock connect tt_3_1_io_update_taken_2_REG, s1_update_taken[3][2] connect tt_3_1.io.update_taken[2], tt_3_1_io_update_taken_2_REG reg tt_3_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_2_REG, s1_update_alloc[3][2] connect tt_3_1.io.update_alloc[2], tt_3_1_io_update_alloc_2_REG reg tt_3_1_io_update_old_ctr_2_REG : UInt, clock connect tt_3_1_io_update_old_ctr_2_REG, s1_update_old_ctr[3][2] connect tt_3_1.io.update_old_ctr[2], tt_3_1_io_update_old_ctr_2_REG reg tt_3_1_io_update_u_mask_2_REG : UInt, clock connect tt_3_1_io_update_u_mask_2_REG, s1_update_u_mask[3][2] connect tt_3_1.io.update_u_mask[2], tt_3_1_io_update_u_mask_2_REG reg tt_3_1_io_update_u_2_REG : UInt, clock connect tt_3_1_io_update_u_2_REG, s1_update_u[3][2] connect tt_3_1.io.update_u[2], tt_3_1_io_update_u_2_REG reg tt_3_1_io_update_mask_3_REG : UInt<1>, clock connect tt_3_1_io_update_mask_3_REG, s1_update_mask[3][3] connect tt_3_1.io.update_mask[3], tt_3_1_io_update_mask_3_REG reg tt_3_1_io_update_taken_3_REG : UInt<1>, clock connect tt_3_1_io_update_taken_3_REG, s1_update_taken[3][3] connect tt_3_1.io.update_taken[3], tt_3_1_io_update_taken_3_REG reg tt_3_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_3_REG, s1_update_alloc[3][3] connect tt_3_1.io.update_alloc[3], tt_3_1_io_update_alloc_3_REG reg tt_3_1_io_update_old_ctr_3_REG : UInt, clock connect tt_3_1_io_update_old_ctr_3_REG, s1_update_old_ctr[3][3] connect tt_3_1.io.update_old_ctr[3], tt_3_1_io_update_old_ctr_3_REG reg tt_3_1_io_update_u_mask_3_REG : UInt, clock connect tt_3_1_io_update_u_mask_3_REG, s1_update_u_mask[3][3] connect tt_3_1.io.update_u_mask[3], tt_3_1_io_update_u_mask_3_REG reg tt_3_1_io_update_u_3_REG : UInt, clock connect tt_3_1_io_update_u_3_REG, s1_update_u[3][3] connect tt_3_1.io.update_u[3], tt_3_1_io_update_u_3_REG reg tt_3_1_io_update_pc_REG : UInt, clock connect tt_3_1_io_update_pc_REG, s1_update.bits.pc connect tt_3_1.io.update_pc, tt_3_1_io_update_pc_REG reg tt_3_1_io_update_hist_REG : UInt, clock connect tt_3_1_io_update_hist_REG, s1_update.bits.ghist connect tt_3_1.io.update_hist, tt_3_1_io_update_hist_REG reg tt_4_1_io_update_mask_0_REG : UInt<1>, clock connect tt_4_1_io_update_mask_0_REG, s1_update_mask[4][0] connect tt_4_1.io.update_mask[0], tt_4_1_io_update_mask_0_REG reg tt_4_1_io_update_taken_0_REG : UInt<1>, clock connect tt_4_1_io_update_taken_0_REG, s1_update_taken[4][0] connect tt_4_1.io.update_taken[0], tt_4_1_io_update_taken_0_REG reg tt_4_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_0_REG, s1_update_alloc[4][0] connect tt_4_1.io.update_alloc[0], tt_4_1_io_update_alloc_0_REG reg tt_4_1_io_update_old_ctr_0_REG : UInt, clock connect tt_4_1_io_update_old_ctr_0_REG, s1_update_old_ctr[4][0] connect tt_4_1.io.update_old_ctr[0], tt_4_1_io_update_old_ctr_0_REG reg tt_4_1_io_update_u_mask_0_REG : UInt, clock connect tt_4_1_io_update_u_mask_0_REG, s1_update_u_mask[4][0] connect tt_4_1.io.update_u_mask[0], tt_4_1_io_update_u_mask_0_REG reg tt_4_1_io_update_u_0_REG : UInt, clock connect tt_4_1_io_update_u_0_REG, s1_update_u[4][0] connect tt_4_1.io.update_u[0], tt_4_1_io_update_u_0_REG reg tt_4_1_io_update_mask_1_REG : UInt<1>, clock connect tt_4_1_io_update_mask_1_REG, s1_update_mask[4][1] connect tt_4_1.io.update_mask[1], tt_4_1_io_update_mask_1_REG reg tt_4_1_io_update_taken_1_REG : UInt<1>, clock connect tt_4_1_io_update_taken_1_REG, s1_update_taken[4][1] connect tt_4_1.io.update_taken[1], tt_4_1_io_update_taken_1_REG reg tt_4_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_1_REG, s1_update_alloc[4][1] connect tt_4_1.io.update_alloc[1], tt_4_1_io_update_alloc_1_REG reg tt_4_1_io_update_old_ctr_1_REG : UInt, clock connect tt_4_1_io_update_old_ctr_1_REG, s1_update_old_ctr[4][1] connect tt_4_1.io.update_old_ctr[1], tt_4_1_io_update_old_ctr_1_REG reg tt_4_1_io_update_u_mask_1_REG : UInt, clock connect tt_4_1_io_update_u_mask_1_REG, s1_update_u_mask[4][1] connect tt_4_1.io.update_u_mask[1], tt_4_1_io_update_u_mask_1_REG reg tt_4_1_io_update_u_1_REG : UInt, clock connect tt_4_1_io_update_u_1_REG, s1_update_u[4][1] connect tt_4_1.io.update_u[1], tt_4_1_io_update_u_1_REG reg tt_4_1_io_update_mask_2_REG : UInt<1>, clock connect tt_4_1_io_update_mask_2_REG, s1_update_mask[4][2] connect tt_4_1.io.update_mask[2], tt_4_1_io_update_mask_2_REG reg tt_4_1_io_update_taken_2_REG : UInt<1>, clock connect tt_4_1_io_update_taken_2_REG, s1_update_taken[4][2] connect tt_4_1.io.update_taken[2], tt_4_1_io_update_taken_2_REG reg tt_4_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_2_REG, s1_update_alloc[4][2] connect tt_4_1.io.update_alloc[2], tt_4_1_io_update_alloc_2_REG reg tt_4_1_io_update_old_ctr_2_REG : UInt, clock connect tt_4_1_io_update_old_ctr_2_REG, s1_update_old_ctr[4][2] connect tt_4_1.io.update_old_ctr[2], tt_4_1_io_update_old_ctr_2_REG reg tt_4_1_io_update_u_mask_2_REG : UInt, clock connect tt_4_1_io_update_u_mask_2_REG, s1_update_u_mask[4][2] connect tt_4_1.io.update_u_mask[2], tt_4_1_io_update_u_mask_2_REG reg tt_4_1_io_update_u_2_REG : UInt, clock connect tt_4_1_io_update_u_2_REG, s1_update_u[4][2] connect tt_4_1.io.update_u[2], tt_4_1_io_update_u_2_REG reg tt_4_1_io_update_mask_3_REG : UInt<1>, clock connect tt_4_1_io_update_mask_3_REG, s1_update_mask[4][3] connect tt_4_1.io.update_mask[3], tt_4_1_io_update_mask_3_REG reg tt_4_1_io_update_taken_3_REG : UInt<1>, clock connect tt_4_1_io_update_taken_3_REG, s1_update_taken[4][3] connect tt_4_1.io.update_taken[3], tt_4_1_io_update_taken_3_REG reg tt_4_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_3_REG, s1_update_alloc[4][3] connect tt_4_1.io.update_alloc[3], tt_4_1_io_update_alloc_3_REG reg tt_4_1_io_update_old_ctr_3_REG : UInt, clock connect tt_4_1_io_update_old_ctr_3_REG, s1_update_old_ctr[4][3] connect tt_4_1.io.update_old_ctr[3], tt_4_1_io_update_old_ctr_3_REG reg tt_4_1_io_update_u_mask_3_REG : UInt, clock connect tt_4_1_io_update_u_mask_3_REG, s1_update_u_mask[4][3] connect tt_4_1.io.update_u_mask[3], tt_4_1_io_update_u_mask_3_REG reg tt_4_1_io_update_u_3_REG : UInt, clock connect tt_4_1_io_update_u_3_REG, s1_update_u[4][3] connect tt_4_1.io.update_u[3], tt_4_1_io_update_u_3_REG reg tt_4_1_io_update_pc_REG : UInt, clock connect tt_4_1_io_update_pc_REG, s1_update.bits.pc connect tt_4_1.io.update_pc, tt_4_1_io_update_pc_REG reg tt_4_1_io_update_hist_REG : UInt, clock connect tt_4_1_io_update_hist_REG, s1_update.bits.ghist connect tt_4_1.io.update_hist, tt_4_1_io_update_hist_REG reg tt_5_1_io_update_mask_0_REG : UInt<1>, clock connect tt_5_1_io_update_mask_0_REG, s1_update_mask[5][0] connect tt_5_1.io.update_mask[0], tt_5_1_io_update_mask_0_REG reg tt_5_1_io_update_taken_0_REG : UInt<1>, clock connect tt_5_1_io_update_taken_0_REG, s1_update_taken[5][0] connect tt_5_1.io.update_taken[0], tt_5_1_io_update_taken_0_REG reg tt_5_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_0_REG, s1_update_alloc[5][0] connect tt_5_1.io.update_alloc[0], tt_5_1_io_update_alloc_0_REG reg tt_5_1_io_update_old_ctr_0_REG : UInt, clock connect tt_5_1_io_update_old_ctr_0_REG, s1_update_old_ctr[5][0] connect tt_5_1.io.update_old_ctr[0], tt_5_1_io_update_old_ctr_0_REG reg tt_5_1_io_update_u_mask_0_REG : UInt, clock connect tt_5_1_io_update_u_mask_0_REG, s1_update_u_mask[5][0] connect tt_5_1.io.update_u_mask[0], tt_5_1_io_update_u_mask_0_REG reg tt_5_1_io_update_u_0_REG : UInt, clock connect tt_5_1_io_update_u_0_REG, s1_update_u[5][0] connect tt_5_1.io.update_u[0], tt_5_1_io_update_u_0_REG reg tt_5_1_io_update_mask_1_REG : UInt<1>, clock connect tt_5_1_io_update_mask_1_REG, s1_update_mask[5][1] connect tt_5_1.io.update_mask[1], tt_5_1_io_update_mask_1_REG reg tt_5_1_io_update_taken_1_REG : UInt<1>, clock connect tt_5_1_io_update_taken_1_REG, s1_update_taken[5][1] connect tt_5_1.io.update_taken[1], tt_5_1_io_update_taken_1_REG reg tt_5_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_1_REG, s1_update_alloc[5][1] connect tt_5_1.io.update_alloc[1], tt_5_1_io_update_alloc_1_REG reg tt_5_1_io_update_old_ctr_1_REG : UInt, clock connect tt_5_1_io_update_old_ctr_1_REG, s1_update_old_ctr[5][1] connect tt_5_1.io.update_old_ctr[1], tt_5_1_io_update_old_ctr_1_REG reg tt_5_1_io_update_u_mask_1_REG : UInt, clock connect tt_5_1_io_update_u_mask_1_REG, s1_update_u_mask[5][1] connect tt_5_1.io.update_u_mask[1], tt_5_1_io_update_u_mask_1_REG reg tt_5_1_io_update_u_1_REG : UInt, clock connect tt_5_1_io_update_u_1_REG, s1_update_u[5][1] connect tt_5_1.io.update_u[1], tt_5_1_io_update_u_1_REG reg tt_5_1_io_update_mask_2_REG : UInt<1>, clock connect tt_5_1_io_update_mask_2_REG, s1_update_mask[5][2] connect tt_5_1.io.update_mask[2], tt_5_1_io_update_mask_2_REG reg tt_5_1_io_update_taken_2_REG : UInt<1>, clock connect tt_5_1_io_update_taken_2_REG, s1_update_taken[5][2] connect tt_5_1.io.update_taken[2], tt_5_1_io_update_taken_2_REG reg tt_5_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_2_REG, s1_update_alloc[5][2] connect tt_5_1.io.update_alloc[2], tt_5_1_io_update_alloc_2_REG reg tt_5_1_io_update_old_ctr_2_REG : UInt, clock connect tt_5_1_io_update_old_ctr_2_REG, s1_update_old_ctr[5][2] connect tt_5_1.io.update_old_ctr[2], tt_5_1_io_update_old_ctr_2_REG reg tt_5_1_io_update_u_mask_2_REG : UInt, clock connect tt_5_1_io_update_u_mask_2_REG, s1_update_u_mask[5][2] connect tt_5_1.io.update_u_mask[2], tt_5_1_io_update_u_mask_2_REG reg tt_5_1_io_update_u_2_REG : UInt, clock connect tt_5_1_io_update_u_2_REG, s1_update_u[5][2] connect tt_5_1.io.update_u[2], tt_5_1_io_update_u_2_REG reg tt_5_1_io_update_mask_3_REG : UInt<1>, clock connect tt_5_1_io_update_mask_3_REG, s1_update_mask[5][3] connect tt_5_1.io.update_mask[3], tt_5_1_io_update_mask_3_REG reg tt_5_1_io_update_taken_3_REG : UInt<1>, clock connect tt_5_1_io_update_taken_3_REG, s1_update_taken[5][3] connect tt_5_1.io.update_taken[3], tt_5_1_io_update_taken_3_REG reg tt_5_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_3_REG, s1_update_alloc[5][3] connect tt_5_1.io.update_alloc[3], tt_5_1_io_update_alloc_3_REG reg tt_5_1_io_update_old_ctr_3_REG : UInt, clock connect tt_5_1_io_update_old_ctr_3_REG, s1_update_old_ctr[5][3] connect tt_5_1.io.update_old_ctr[3], tt_5_1_io_update_old_ctr_3_REG reg tt_5_1_io_update_u_mask_3_REG : UInt, clock connect tt_5_1_io_update_u_mask_3_REG, s1_update_u_mask[5][3] connect tt_5_1.io.update_u_mask[3], tt_5_1_io_update_u_mask_3_REG reg tt_5_1_io_update_u_3_REG : UInt, clock connect tt_5_1_io_update_u_3_REG, s1_update_u[5][3] connect tt_5_1.io.update_u[3], tt_5_1_io_update_u_3_REG reg tt_5_1_io_update_pc_REG : UInt, clock connect tt_5_1_io_update_pc_REG, s1_update.bits.pc connect tt_5_1.io.update_pc, tt_5_1_io_update_pc_REG reg tt_5_1_io_update_hist_REG : UInt, clock connect tt_5_1_io_update_hist_REG, s1_update.bits.ghist connect tt_5_1.io.update_hist, tt_5_1_io_update_hist_REG node _io_f3_meta_T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _io_f3_meta_T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _io_f3_meta_T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _io_f3_meta_T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node io_f3_meta_lo = cat(_io_f3_meta_T_1, _io_f3_meta_T) node io_f3_meta_hi = cat(_io_f3_meta_T_3, _io_f3_meta_T_2) node _io_f3_meta_T_4 = cat(io_f3_meta_hi, io_f3_meta_lo) node io_f3_meta_lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node io_f3_meta_hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _io_f3_meta_T_5 = cat(io_f3_meta_hi_1, io_f3_meta_lo_1) node io_f3_meta_lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node io_f3_meta_hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _io_f3_meta_T_6 = cat(io_f3_meta_hi_2, io_f3_meta_lo_2) node io_f3_meta_lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node io_f3_meta_hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _io_f3_meta_T_7 = cat(io_f3_meta_hi_3, io_f3_meta_lo_3) node _io_f3_meta_T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _io_f3_meta_T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _io_f3_meta_T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _io_f3_meta_T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node io_f3_meta_lo_4 = cat(_io_f3_meta_T_9, _io_f3_meta_T_8) node io_f3_meta_hi_4 = cat(_io_f3_meta_T_11, _io_f3_meta_T_10) node _io_f3_meta_T_12 = cat(io_f3_meta_hi_4, io_f3_meta_lo_4) node io_f3_meta_lo_5 = cat(_io_f3_meta_T_5, _io_f3_meta_T_4) node io_f3_meta_hi_hi = cat(_io_f3_meta_T_12, _io_f3_meta_T_7) node io_f3_meta_hi_5 = cat(io_f3_meta_hi_hi, _io_f3_meta_T_6) node _io_f3_meta_T_13 = cat(io_f3_meta_hi_5, io_f3_meta_lo_5) connect io.f3_meta, _io_f3_meta_T_13

module TageBranchPredictorBank_1( // @[tage.scala:198:7] input clock, // @[tage.scala:198:7] input reset, // @[tage.scala:198:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [2:0] s1_update_meta_provider_ctr_3; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_2; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_1; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_0; // @[tage.scala:236:52] wire _alloc_lfsr_prng_3_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire io_f0_valid_0 = io_f0_valid; // @[tage.scala:198:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[tage.scala:198:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[tage.scala:198:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_f3_fire_0 = io_f3_fire; // @[tage.scala:198:7] wire io_update_valid_0 = io_update_valid; // @[tage.scala:198:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[tage.scala:198:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[tage.scala:198:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[tage.scala:198:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[tage.scala:198:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[tage.scala:198:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[tage.scala:198:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[tage.scala:198:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[tage.scala:198:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[tage.scala:198:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[tage.scala:198:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[tage.scala:198:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[tage.scala:198:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[tage.scala:198:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[tage.scala:198:7] wire io_f1_lhist = 1'h0; // @[tage.scala:198:7] wire _s1_update_mask_WIRE_0_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_u_mask_WIRE_0_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_3 = 1'h0; // @[tage.scala:241:50] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_taken_0; // @[tage.scala:198:7] wire io_resp_f3_1_taken_0; // @[tage.scala:198:7] wire io_resp_f3_2_taken_0; // @[tage.scala:198:7] wire io_resp_f3_3_taken_0; // @[tage.scala:198:7] wire [119:0] io_f3_meta_0; // @[tage.scala:198:7] wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35] reg [36:0] s1_idx; // @[predictor.scala:163:29] reg [36:0] s2_idx; // @[predictor.scala:164:29] reg [36:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [36:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _f3_meta_alt_differs_0_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_1_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_2_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_3_T; // @[tage.scala:275:48] wire _f3_meta_allocate_0_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry; // @[tage.scala:289:26] wire _f3_meta_allocate_1_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_1; // @[tage.scala:289:26] wire _f3_meta_allocate_2_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_2; // @[tage.scala:289:26] wire _f3_meta_allocate_3_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_3; // @[tage.scala:289:26] wire f3_meta_provider_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_0_bits; // @[tage.scala:212:21] wire f3_meta_provider_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_1_bits; // @[tage.scala:212:21] wire f3_meta_provider_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_2_bits; // @[tage.scala:212:21] wire f3_meta_provider_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_3_bits; // @[tage.scala:212:21] wire f3_meta_alt_differs_0; // @[tage.scala:212:21] wire f3_meta_alt_differs_1; // @[tage.scala:212:21] wire f3_meta_alt_differs_2; // @[tage.scala:212:21] wire f3_meta_alt_differs_3; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_0; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_1; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_2; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_3; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_0; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_1; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_2; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_3; // @[tage.scala:212:21] wire f3_meta_allocate_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_0_bits; // @[tage.scala:212:21] wire f3_meta_allocate_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_1_bits; // @[tage.scala:212:21] wire f3_meta_allocate_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_2_bits; // @[tage.scala:212:21] wire f3_meta_allocate_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_3_bits; // @[tage.scala:212:21] wire [3:0] _io_f3_meta_T = {f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_1 = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_2 = {f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_3 = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits, f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits, f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33] wire [5:0] _GEN = {f3_meta_provider_ctr_1, f3_meta_provider_ctr_0}; // @[tage.scala:212:21, :213:33] wire [5:0] lo_1; // @[tage.scala:213:33] assign lo_1 = _GEN; // @[tage.scala:213:33] wire [5:0] io_f3_meta_lo_1; // @[tage.scala:359:25] assign io_f3_meta_lo_1 = _GEN; // @[tage.scala:213:33, :359:25] wire [5:0] _GEN_0 = {f3_meta_provider_ctr_3, f3_meta_provider_ctr_2}; // @[tage.scala:212:21, :213:33] wire [5:0] hi_1; // @[tage.scala:213:33] assign hi_1 = _GEN_0; // @[tage.scala:213:33] wire [5:0] io_f3_meta_hi_1; // @[tage.scala:359:25] assign io_f3_meta_hi_1 = _GEN_0; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_1 = {f3_meta_provider_u_1, f3_meta_provider_u_0}; // @[tage.scala:212:21, :213:33] wire [3:0] lo_2; // @[tage.scala:213:33] assign lo_2 = _GEN_1; // @[tage.scala:213:33] wire [3:0] io_f3_meta_lo_2; // @[tage.scala:359:25] assign io_f3_meta_lo_2 = _GEN_1; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_2 = {f3_meta_provider_u_3, f3_meta_provider_u_2}; // @[tage.scala:212:21, :213:33] wire [3:0] hi_2; // @[tage.scala:213:33] assign hi_2 = _GEN_2; // @[tage.scala:213:33] wire [3:0] io_f3_meta_hi_2; // @[tage.scala:359:25] assign io_f3_meta_hi_2 = _GEN_2; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_3 = {f3_meta_alt_differs_1, f3_meta_alt_differs_0}; // @[tage.scala:212:21, :213:33] wire [1:0] lo_3; // @[tage.scala:213:33] assign lo_3 = _GEN_3; // @[tage.scala:213:33] wire [1:0] io_f3_meta_lo_3; // @[tage.scala:359:25] assign io_f3_meta_lo_3 = _GEN_3; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_4 = {f3_meta_alt_differs_3, f3_meta_alt_differs_2}; // @[tage.scala:212:21, :213:33] wire [1:0] hi_3; // @[tage.scala:213:33] assign hi_3 = _GEN_4; // @[tage.scala:213:33] wire [1:0] io_f3_meta_hi_3; // @[tage.scala:359:25] assign io_f3_meta_hi_3 = _GEN_4; // @[tage.scala:213:33, :359:25] wire [3:0] _io_f3_meta_T_8 = {f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_9 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_10 = {f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_11 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo_4 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits, f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi_4 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits, f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33] wire [27:0] lo_5 = {hi_1, lo_1, hi, lo}; // @[tage.scala:213:33] wire [19:0] hi_hi = {hi_4, lo_4, hi_3, lo_3}; // @[tage.scala:213:33] wire [27:0] hi_5 = {hi_hi, hi_2, lo_2}; // @[tage.scala:213:33] reg t_io_f1_req_valid_REG; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_1; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_1; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_2; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_2; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_3; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_3; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_4; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_4; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_5; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_5; // @[tage.scala:226:35] wire [2:0] f3_resps_0_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_0_bits_u; // @[tage.scala:234:25] wire f3_resps_0_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_1_bits_u; // @[tage.scala:234:25] wire f3_resps_0_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_2_bits_u; // @[tage.scala:234:25] wire f3_resps_0_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_3_bits_u; // @[tage.scala:234:25] wire f3_resps_0_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_0_bits_u; // @[tage.scala:234:25] wire f3_resps_1_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_1_bits_u; // @[tage.scala:234:25] wire f3_resps_1_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_2_bits_u; // @[tage.scala:234:25] wire f3_resps_1_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_3_bits_u; // @[tage.scala:234:25] wire f3_resps_1_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_0_bits_u; // @[tage.scala:234:25] wire f3_resps_2_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_1_bits_u; // @[tage.scala:234:25] wire f3_resps_2_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_2_bits_u; // @[tage.scala:234:25] wire f3_resps_2_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_3_bits_u; // @[tage.scala:234:25] wire f3_resps_2_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_0_bits_u; // @[tage.scala:234:25] wire f3_resps_3_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_1_bits_u; // @[tage.scala:234:25] wire f3_resps_3_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_2_bits_u; // @[tage.scala:234:25] wire f3_resps_3_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_3_bits_u; // @[tage.scala:234:25] wire f3_resps_3_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_0_bits_u; // @[tage.scala:234:25] wire f3_resps_4_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_1_bits_u; // @[tage.scala:234:25] wire f3_resps_4_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_2_bits_u; // @[tage.scala:234:25] wire f3_resps_4_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_3_bits_u; // @[tage.scala:234:25] wire f3_resps_4_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_0_bits_u; // @[tage.scala:234:25] wire f3_resps_5_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_1_bits_u; // @[tage.scala:234:25] wire f3_resps_5_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_2_bits_u; // @[tage.scala:234:25] wire f3_resps_5_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_3_bits_u; // @[tage.scala:234:25] wire f3_resps_5_3_valid; // @[tage.scala:234:25] wire _s1_update_meta_T_21; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_20; // @[tage.scala:236:52] wire _s1_update_meta_T_23; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_22; // @[tage.scala:236:52] wire _s1_update_meta_T_25; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_24; // @[tage.scala:236:52] wire _s1_update_meta_T_27; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_26; // @[tage.scala:236:52] wire _s1_update_meta_T_16; // @[tage.scala:236:52] wire _s1_update_meta_T_17; // @[tage.scala:236:52] wire _s1_update_meta_T_18; // @[tage.scala:236:52] wire _s1_update_meta_T_19; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_12; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_13; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_14; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_15; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_8; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_9; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_10; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_11; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire _s1_update_meta_T_1; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T; // @[tage.scala:236:52] wire _s1_update_meta_T_3; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_2; // @[tage.scala:236:52] wire _s1_update_meta_T_5; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_4; // @[tage.scala:236:52] wire _s1_update_meta_T_7; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_6; // @[tage.scala:236:52] wire s1_update_meta_provider_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_0_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_1_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_2_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_3_bits; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_0; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_1; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_2; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_3; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_0; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_1; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_2; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_3; // @[tage.scala:236:52] wire s1_update_meta_allocate_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_0_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_1_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_2_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_3_bits; // @[tage.scala:236:52] wire [55:0] _s1_update_meta_WIRE = s1_update_bits_meta[55:0]; // @[tage.scala:236:52] assign _s1_update_meta_T = _s1_update_meta_WIRE[2:0]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_bits = _s1_update_meta_T; // @[tage.scala:236:52] assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_valid = _s1_update_meta_T_1; // @[tage.scala:236:52] assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[6:4]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_bits = _s1_update_meta_T_2; // @[tage.scala:236:52] assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_valid = _s1_update_meta_T_3; // @[tage.scala:236:52] assign _s1_update_meta_T_4 = _s1_update_meta_WIRE[10:8]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_bits = _s1_update_meta_T_4; // @[tage.scala:236:52] assign _s1_update_meta_T_5 = _s1_update_meta_WIRE[11]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_valid = _s1_update_meta_T_5; // @[tage.scala:236:52] assign _s1_update_meta_T_6 = _s1_update_meta_WIRE[14:12]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_bits = _s1_update_meta_T_6; // @[tage.scala:236:52] assign _s1_update_meta_T_7 = _s1_update_meta_WIRE[15]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_valid = _s1_update_meta_T_7; // @[tage.scala:236:52] assign _s1_update_meta_T_8 = _s1_update_meta_WIRE[18:16]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_0 = _s1_update_meta_T_8; // @[tage.scala:236:52] assign _s1_update_meta_T_9 = _s1_update_meta_WIRE[21:19]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_1 = _s1_update_meta_T_9; // @[tage.scala:236:52] assign _s1_update_meta_T_10 = _s1_update_meta_WIRE[24:22]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_2 = _s1_update_meta_T_10; // @[tage.scala:236:52] assign _s1_update_meta_T_11 = _s1_update_meta_WIRE[27:25]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_3 = _s1_update_meta_T_11; // @[tage.scala:236:52] assign _s1_update_meta_T_12 = _s1_update_meta_WIRE[29:28]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_0 = _s1_update_meta_T_12; // @[tage.scala:236:52] assign _s1_update_meta_T_13 = _s1_update_meta_WIRE[31:30]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_1 = _s1_update_meta_T_13; // @[tage.scala:236:52] assign _s1_update_meta_T_14 = _s1_update_meta_WIRE[33:32]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_2 = _s1_update_meta_T_14; // @[tage.scala:236:52] assign _s1_update_meta_T_15 = _s1_update_meta_WIRE[35:34]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_3 = _s1_update_meta_T_15; // @[tage.scala:236:52] assign _s1_update_meta_T_16 = _s1_update_meta_WIRE[36]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_0 = _s1_update_meta_T_16; // @[tage.scala:236:52] assign _s1_update_meta_T_17 = _s1_update_meta_WIRE[37]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_1 = _s1_update_meta_T_17; // @[tage.scala:236:52] assign _s1_update_meta_T_18 = _s1_update_meta_WIRE[38]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_2 = _s1_update_meta_T_18; // @[tage.scala:236:52] assign _s1_update_meta_T_19 = _s1_update_meta_WIRE[39]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_3 = _s1_update_meta_T_19; // @[tage.scala:236:52] assign _s1_update_meta_T_20 = _s1_update_meta_WIRE[42:40]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_bits = _s1_update_meta_T_20; // @[tage.scala:236:52] assign _s1_update_meta_T_21 = _s1_update_meta_WIRE[43]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_valid = _s1_update_meta_T_21; // @[tage.scala:236:52] assign _s1_update_meta_T_22 = _s1_update_meta_WIRE[46:44]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_bits = _s1_update_meta_T_22; // @[tage.scala:236:52] assign _s1_update_meta_T_23 = _s1_update_meta_WIRE[47]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_valid = _s1_update_meta_T_23; // @[tage.scala:236:52] assign _s1_update_meta_T_24 = _s1_update_meta_WIRE[50:48]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_bits = _s1_update_meta_T_24; // @[tage.scala:236:52] assign _s1_update_meta_T_25 = _s1_update_meta_WIRE[51]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_valid = _s1_update_meta_T_25; // @[tage.scala:236:52] assign _s1_update_meta_T_26 = _s1_update_meta_WIRE[54:52]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_bits = _s1_update_meta_T_26; // @[tage.scala:236:52] assign _s1_update_meta_T_27 = _s1_update_meta_WIRE[55]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_valid = _s1_update_meta_T_27; // @[tage.scala:236:52] wire [3:0] _s1_update_mispredict_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire [3:0] _s1_update_mispredict_mask_T_1 = {4{s1_update_bits_cfi_mispredicted}}; // @[tage.scala:238:9] wire [3:0] s1_update_mispredict_mask = _s1_update_mispredict_mask_T & _s1_update_mispredict_mask_T_1; // @[OneHot.scala:58:35] wire s1_update_mask_0_0; // @[tage.scala:240:33] wire s1_update_mask_0_1; // @[tage.scala:240:33] wire s1_update_mask_0_2; // @[tage.scala:240:33] wire s1_update_mask_0_3; // @[tage.scala:240:33] wire s1_update_mask_1_0; // @[tage.scala:240:33] wire s1_update_mask_1_1; // @[tage.scala:240:33] wire s1_update_mask_1_2; // @[tage.scala:240:33] wire s1_update_mask_1_3; // @[tage.scala:240:33] wire s1_update_mask_2_0; // @[tage.scala:240:33] wire s1_update_mask_2_1; // @[tage.scala:240:33] wire s1_update_mask_2_2; // @[tage.scala:240:33] wire s1_update_mask_2_3; // @[tage.scala:240:33] wire s1_update_mask_3_0; // @[tage.scala:240:33] wire s1_update_mask_3_1; // @[tage.scala:240:33] wire s1_update_mask_3_2; // @[tage.scala:240:33] wire s1_update_mask_3_3; // @[tage.scala:240:33] wire s1_update_mask_4_0; // @[tage.scala:240:33] wire s1_update_mask_4_1; // @[tage.scala:240:33] wire s1_update_mask_4_2; // @[tage.scala:240:33] wire s1_update_mask_4_3; // @[tage.scala:240:33] wire s1_update_mask_5_0; // @[tage.scala:240:33] wire s1_update_mask_5_1; // @[tage.scala:240:33] wire s1_update_mask_5_2; // @[tage.scala:240:33] wire s1_update_mask_5_3; // @[tage.scala:240:33] wire s1_update_u_mask_0_0; // @[tage.scala:241:35] wire s1_update_u_mask_0_1; // @[tage.scala:241:35] wire s1_update_u_mask_0_2; // @[tage.scala:241:35] wire s1_update_u_mask_0_3; // @[tage.scala:241:35] wire s1_update_u_mask_1_0; // @[tage.scala:241:35] wire s1_update_u_mask_1_1; // @[tage.scala:241:35] wire s1_update_u_mask_1_2; // @[tage.scala:241:35] wire s1_update_u_mask_1_3; // @[tage.scala:241:35] wire s1_update_u_mask_2_0; // @[tage.scala:241:35] wire s1_update_u_mask_2_1; // @[tage.scala:241:35] wire s1_update_u_mask_2_2; // @[tage.scala:241:35] wire s1_update_u_mask_2_3; // @[tage.scala:241:35] wire s1_update_u_mask_3_0; // @[tage.scala:241:35] wire s1_update_u_mask_3_1; // @[tage.scala:241:35] wire s1_update_u_mask_3_2; // @[tage.scala:241:35] wire s1_update_u_mask_3_3; // @[tage.scala:241:35] wire s1_update_u_mask_4_0; // @[tage.scala:241:35] wire s1_update_u_mask_4_1; // @[tage.scala:241:35] wire s1_update_u_mask_4_2; // @[tage.scala:241:35] wire s1_update_u_mask_4_3; // @[tage.scala:241:35] wire s1_update_u_mask_5_0; // @[tage.scala:241:35] wire s1_update_u_mask_5_1; // @[tage.scala:241:35] wire s1_update_u_mask_5_2; // @[tage.scala:241:35] wire s1_update_u_mask_5_3; // @[tage.scala:241:35] wire s1_update_taken_0_0; // @[tage.scala:243:31] wire s1_update_taken_0_1; // @[tage.scala:243:31] wire s1_update_taken_0_2; // @[tage.scala:243:31] wire s1_update_taken_0_3; // @[tage.scala:243:31] wire s1_update_taken_1_0; // @[tage.scala:243:31] wire s1_update_taken_1_1; // @[tage.scala:243:31] wire s1_update_taken_1_2; // @[tage.scala:243:31] wire s1_update_taken_1_3; // @[tage.scala:243:31] wire s1_update_taken_2_0; // @[tage.scala:243:31] wire s1_update_taken_2_1; // @[tage.scala:243:31] wire s1_update_taken_2_2; // @[tage.scala:243:31] wire s1_update_taken_2_3; // @[tage.scala:243:31] wire s1_update_taken_3_0; // @[tage.scala:243:31] wire s1_update_taken_3_1; // @[tage.scala:243:31] wire s1_update_taken_3_2; // @[tage.scala:243:31] wire s1_update_taken_3_3; // @[tage.scala:243:31] wire s1_update_taken_4_0; // @[tage.scala:243:31] wire s1_update_taken_4_1; // @[tage.scala:243:31] wire s1_update_taken_4_2; // @[tage.scala:243:31] wire s1_update_taken_4_3; // @[tage.scala:243:31] wire s1_update_taken_5_0; // @[tage.scala:243:31] wire s1_update_taken_5_1; // @[tage.scala:243:31] wire s1_update_taken_5_2; // @[tage.scala:243:31] wire s1_update_taken_5_3; // @[tage.scala:243:31] wire s1_update_alloc_0_0; // @[tage.scala:245:31] wire s1_update_alloc_0_1; // @[tage.scala:245:31] wire s1_update_alloc_0_2; // @[tage.scala:245:31] wire s1_update_alloc_0_3; // @[tage.scala:245:31] wire s1_update_alloc_1_0; // @[tage.scala:245:31] wire s1_update_alloc_1_1; // @[tage.scala:245:31] wire s1_update_alloc_1_2; // @[tage.scala:245:31] wire s1_update_alloc_1_3; // @[tage.scala:245:31] wire s1_update_alloc_2_0; // @[tage.scala:245:31] wire s1_update_alloc_2_1; // @[tage.scala:245:31] wire s1_update_alloc_2_2; // @[tage.scala:245:31] wire s1_update_alloc_2_3; // @[tage.scala:245:31] wire s1_update_alloc_3_0; // @[tage.scala:245:31] wire s1_update_alloc_3_1; // @[tage.scala:245:31] wire s1_update_alloc_3_2; // @[tage.scala:245:31] wire s1_update_alloc_3_3; // @[tage.scala:245:31] wire s1_update_alloc_4_0; // @[tage.scala:245:31] wire s1_update_alloc_4_1; // @[tage.scala:245:31] wire s1_update_alloc_4_2; // @[tage.scala:245:31] wire s1_update_alloc_4_3; // @[tage.scala:245:31] wire s1_update_alloc_5_0; // @[tage.scala:245:31] wire s1_update_alloc_5_1; // @[tage.scala:245:31] wire s1_update_alloc_5_2; // @[tage.scala:245:31] wire s1_update_alloc_5_3; // @[tage.scala:245:31] wire [1:0] s1_update_u_0_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_3; // @[tage.scala:246:31] wire final_altpred; // @[tage.scala:256:33] wire _io_resp_f3_0_taken_T = f3_resps_0_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_1 = f3_resps_0_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_2 = _io_resp_f3_0_taken_T | _io_resp_f3_0_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_3 = f3_resps_0_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_4 = _io_resp_f3_0_taken_T_2 ? io_resp_in_0_f3_0_taken_0 : _io_resp_f3_0_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_17 = f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_5 = f3_resps_1_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_6 = f3_resps_1_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_7 = _io_resp_f3_0_taken_T_5 | _io_resp_f3_0_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_8 = f3_resps_1_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_9 = _io_resp_f3_0_taken_T_7 ? _T_17 : _io_resp_f3_0_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_21 = f3_resps_1_0_valid ? f3_resps_1_0_bits_ctr[2] : _T_17; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_10 = f3_resps_2_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_11 = f3_resps_2_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_12 = _io_resp_f3_0_taken_T_10 | _io_resp_f3_0_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_13 = f3_resps_2_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_14 = _io_resp_f3_0_taken_T_12 ? _T_21 : _io_resp_f3_0_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_25 = f3_resps_2_0_valid ? f3_resps_2_0_bits_ctr[2] : _T_21; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_15 = f3_resps_3_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_16 = f3_resps_3_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_17 = _io_resp_f3_0_taken_T_15 | _io_resp_f3_0_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_18 = f3_resps_3_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_19 = _io_resp_f3_0_taken_T_17 ? _T_25 : _io_resp_f3_0_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_29 = f3_resps_3_0_valid ? f3_resps_3_0_bits_ctr[2] : _T_25; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_20 = f3_resps_4_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_21 = f3_resps_4_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_22 = _io_resp_f3_0_taken_T_20 | _io_resp_f3_0_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_23 = f3_resps_4_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_24 = _io_resp_f3_0_taken_T_22 ? _T_29 : _io_resp_f3_0_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_33 = f3_resps_4_0_valid ? f3_resps_4_0_bits_ctr[2] : _T_29; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_25 = f3_resps_5_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_26 = f3_resps_5_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_27 = _io_resp_f3_0_taken_T_25 | _io_resp_f3_0_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_28 = f3_resps_5_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_29 = _io_resp_f3_0_taken_T_27 ? _T_33 : _io_resp_f3_0_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_0_taken_0 = f3_resps_5_0_valid ? _io_resp_f3_0_taken_T_29 : f3_resps_4_0_valid ? _io_resp_f3_0_taken_T_24 : f3_resps_3_0_valid ? _io_resp_f3_0_taken_T_19 : f3_resps_2_0_valid ? _io_resp_f3_0_taken_T_14 : f3_resps_1_0_valid ? _io_resp_f3_0_taken_T_9 : f3_resps_0_0_valid ? _io_resp_f3_0_taken_T_4 : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred = f3_resps_5_0_valid ? _T_33 : f3_resps_4_0_valid ? _T_29 : f3_resps_3_0_valid ? _T_25 : f3_resps_2_0_valid ? _T_21 : f3_resps_1_0_valid & f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_0_valid = f3_resps_0_0_valid | f3_resps_1_0_valid | f3_resps_2_0_valid | f3_resps_3_0_valid | f3_resps_4_0_valid | f3_resps_5_0_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_0_bits = f3_resps_5_0_valid ? 3'h5 : f3_resps_4_0_valid ? 3'h4 : {1'h0, f3_resps_3_0_valid ? 2'h3 : f3_resps_2_0_valid ? 2'h2 : {1'h0, f3_resps_1_0_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_0_T = final_altpred != io_resp_f3_0_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_0 = _f3_meta_alt_differs_0_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_5 = {{f3_resps_0_0_bits_ctr}, {f3_resps_0_0_bits_ctr}, {f3_resps_5_0_bits_ctr}, {f3_resps_4_0_bits_ctr}, {f3_resps_3_0_bits_ctr}, {f3_resps_2_0_bits_ctr}, {f3_resps_1_0_bits_ctr}, {f3_resps_0_0_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_0 = _GEN_5[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_6 = {{f3_resps_0_0_bits_u}, {f3_resps_0_0_bits_u}, {f3_resps_5_0_bits_u}, {f3_resps_4_0_bits_u}, {f3_resps_3_0_bits_u}, {f3_resps_2_0_bits_u}, {f3_resps_1_0_bits_u}, {f3_resps_0_0_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_0 = _GEN_6[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T = ~f3_resps_0_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_1 = f3_resps_0_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_2 = _allocatable_slots_T & _allocatable_slots_T_1; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_0 = _allocatable_slots_T_2; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_3 = ~f3_resps_1_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_4 = f3_resps_1_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_5 = _allocatable_slots_T_3 & _allocatable_slots_T_4; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1 = _allocatable_slots_T_5; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_6 = ~f3_resps_2_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_7 = f3_resps_2_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_8 = _allocatable_slots_T_6 & _allocatable_slots_T_7; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2 = _allocatable_slots_T_8; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_9 = ~f3_resps_3_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_10 = f3_resps_3_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_11 = _allocatable_slots_T_9 & _allocatable_slots_T_10; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3 = _allocatable_slots_T_11; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_12 = ~f3_resps_4_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_13 = f3_resps_4_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_14 = _allocatable_slots_T_12 & _allocatable_slots_T_13; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_4 = _allocatable_slots_T_14; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_15 = ~f3_resps_5_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_16 = f3_resps_5_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_17 = _allocatable_slots_T_15 & _allocatable_slots_T_16; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_5 = _allocatable_slots_T_17; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi = {_allocatable_slots_WIRE_2, _allocatable_slots_WIRE_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo = {allocatable_slots_lo_hi, _allocatable_slots_WIRE_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi = {_allocatable_slots_WIRE_5, _allocatable_slots_WIRE_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi = {allocatable_slots_hi_hi, _allocatable_slots_WIRE_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_18 = {allocatable_slots_hi, allocatable_slots_lo}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_19 = 8'h1 << f3_meta_provider_0_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_20 = _allocatable_slots_T_19; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_21 = {1'h0, _allocatable_slots_T_19[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_22 = {2'h0, _allocatable_slots_T_19[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_23 = {3'h0, _allocatable_slots_T_19[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_24 = {4'h0, _allocatable_slots_T_19[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_25 = {5'h0, _allocatable_slots_T_19[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_26 = {6'h0, _allocatable_slots_T_19[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_27 = {7'h0, _allocatable_slots_T_19[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_28 = _allocatable_slots_T_20 | _allocatable_slots_T_21; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_29 = _allocatable_slots_T_28 | _allocatable_slots_T_22; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_30 = _allocatable_slots_T_29 | _allocatable_slots_T_23; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_31 = _allocatable_slots_T_30 | _allocatable_slots_T_24; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_32 = _allocatable_slots_T_31 | _allocatable_slots_T_25; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_33 = _allocatable_slots_T_32 | _allocatable_slots_T_26; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_34 = _allocatable_slots_T_33 | _allocatable_slots_T_27; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_35 = {6{f3_meta_provider_0_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_36 = {2'h0, _allocatable_slots_T_34[5:0] & _allocatable_slots_T_35}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_37 = ~_allocatable_slots_T_36; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots = {2'h0, _allocatable_slots_T_37[5:0] & _allocatable_slots_T_18}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi = {_alloc_lfsr_prng_io_out_2, _alloc_lfsr_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo = {alloc_lfsr_lo_hi, _alloc_lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi = {_alloc_lfsr_prng_io_out_5, _alloc_lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi = {alloc_lfsr_hi_hi, _alloc_lfsr_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr = {alloc_lfsr_hi, alloc_lfsr_lo}; // @[PRNG.scala:95:17] wire _first_entry_T = allocatable_slots[0]; // @[OneHot.scala:48:45] wire _first_entry_T_1 = allocatable_slots[1]; // @[OneHot.scala:48:45] wire _first_entry_T_2 = allocatable_slots[2]; // @[OneHot.scala:48:45] wire _first_entry_T_3 = allocatable_slots[3]; // @[OneHot.scala:48:45] wire _first_entry_T_4 = allocatable_slots[4]; // @[OneHot.scala:48:45] wire _first_entry_T_5 = allocatable_slots[5]; // @[OneHot.scala:48:45] wire _first_entry_T_6 = allocatable_slots[6]; // @[OneHot.scala:48:45] wire _first_entry_T_7 = allocatable_slots[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_8 = {2'h3, ~_first_entry_T_6}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_9 = _first_entry_T_5 ? 3'h5 : _first_entry_T_8; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_10 = _first_entry_T_4 ? 3'h4 : _first_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_11 = _first_entry_T_3 ? 3'h3 : _first_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_12 = _first_entry_T_2 ? 3'h2 : _first_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_13 = _first_entry_T_1 ? 3'h1 : _first_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] first_entry = _first_entry_T ? 3'h0 : _first_entry_T_13; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T = {2'h0, allocatable_slots[5:0] & alloc_lfsr}; // @[PRNG.scala:95:17] wire _masked_entry_T_1 = _masked_entry_T[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_2 = _masked_entry_T[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_3 = _masked_entry_T[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_4 = _masked_entry_T[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_5 = _masked_entry_T[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_6 = _masked_entry_T[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_7 = _masked_entry_T[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_8 = _masked_entry_T[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_9 = {2'h3, ~_masked_entry_T_7}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_10 = _masked_entry_T_6 ? 3'h5 : _masked_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_11 = _masked_entry_T_5 ? 3'h4 : _masked_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_12 = _masked_entry_T_4 ? 3'h3 : _masked_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_13 = _masked_entry_T_3 ? 3'h2 : _masked_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_14 = _masked_entry_T_2 ? 3'h1 : _masked_entry_T_13; // @[OneHot.scala:48:45] wire [2:0] masked_entry = _masked_entry_T_1 ? 3'h0 : _masked_entry_T_14; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T = allocatable_slots >> masked_entry; // @[Mux.scala:50:70] wire _alloc_entry_T_1 = _alloc_entry_T[0]; // @[tage.scala:289:44] assign alloc_entry = _alloc_entry_T_1 ? masked_entry : first_entry; // @[Mux.scala:50:70] assign f3_meta_allocate_0_bits = alloc_entry; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_0_valid_T = |allocatable_slots; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_0_valid = _f3_meta_allocate_0_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[tage.scala:297:58] wire _update_was_taken_T_1 = s1_update_bits_cfi_idx_valid & _update_was_taken_T; // @[tage.scala:296:58, :297:58] wire update_was_taken = _update_was_taken_T_1 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire [4:0] _GEN_7 = {s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30] wire _T_44 = s1_update_bits_br_mask[0] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_8 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_9 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_10 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_11 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_12 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_13 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T = s1_update_mispredict_mask[0]; // @[tage.scala:237:73, :308:52] wire _new_u_T_1 = ~s1_update_meta_alt_differs_0; // @[tage.scala:217:9, :236:52] wire _new_u_T_2 = s1_update_meta_provider_u_0 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_14 = {1'h0, s1_update_meta_provider_u_0}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_3 = _GEN_14 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_4 = _new_u_T_3[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_5 = _new_u_T_2 ? 2'h0 : _new_u_T_4; // @[tage.scala:218:{24,27,43}] wire _new_u_T_6 = &s1_update_meta_provider_u_0; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_7 = _GEN_14 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_8 = _new_u_T_7[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_9 = _new_u_T_6 ? 2'h3 : _new_u_T_8; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_10 = _new_u_T ? _new_u_T_5 : _new_u_T_9; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u = _new_u_T_1 ? s1_update_meta_provider_u_0 : _new_u_T_10; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_1; // @[tage.scala:256:33] wire _io_resp_f3_1_taken_T = f3_resps_0_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_1 = f3_resps_0_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_2 = _io_resp_f3_1_taken_T | _io_resp_f3_1_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_3 = f3_resps_0_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_4 = _io_resp_f3_1_taken_T_2 ? io_resp_in_0_f3_1_taken_0 : _io_resp_f3_1_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_48 = f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_5 = f3_resps_1_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_6 = f3_resps_1_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_7 = _io_resp_f3_1_taken_T_5 | _io_resp_f3_1_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_8 = f3_resps_1_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_9 = _io_resp_f3_1_taken_T_7 ? _T_48 : _io_resp_f3_1_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_52 = f3_resps_1_1_valid ? f3_resps_1_1_bits_ctr[2] : _T_48; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_10 = f3_resps_2_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_11 = f3_resps_2_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_12 = _io_resp_f3_1_taken_T_10 | _io_resp_f3_1_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_13 = f3_resps_2_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_14 = _io_resp_f3_1_taken_T_12 ? _T_52 : _io_resp_f3_1_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_56 = f3_resps_2_1_valid ? f3_resps_2_1_bits_ctr[2] : _T_52; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_15 = f3_resps_3_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_16 = f3_resps_3_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_17 = _io_resp_f3_1_taken_T_15 | _io_resp_f3_1_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_18 = f3_resps_3_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_19 = _io_resp_f3_1_taken_T_17 ? _T_56 : _io_resp_f3_1_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_60 = f3_resps_3_1_valid ? f3_resps_3_1_bits_ctr[2] : _T_56; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_20 = f3_resps_4_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_21 = f3_resps_4_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_22 = _io_resp_f3_1_taken_T_20 | _io_resp_f3_1_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_23 = f3_resps_4_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_24 = _io_resp_f3_1_taken_T_22 ? _T_60 : _io_resp_f3_1_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_64 = f3_resps_4_1_valid ? f3_resps_4_1_bits_ctr[2] : _T_60; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_25 = f3_resps_5_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_26 = f3_resps_5_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_27 = _io_resp_f3_1_taken_T_25 | _io_resp_f3_1_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_28 = f3_resps_5_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_29 = _io_resp_f3_1_taken_T_27 ? _T_64 : _io_resp_f3_1_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_1_taken_0 = f3_resps_5_1_valid ? _io_resp_f3_1_taken_T_29 : f3_resps_4_1_valid ? _io_resp_f3_1_taken_T_24 : f3_resps_3_1_valid ? _io_resp_f3_1_taken_T_19 : f3_resps_2_1_valid ? _io_resp_f3_1_taken_T_14 : f3_resps_1_1_valid ? _io_resp_f3_1_taken_T_9 : f3_resps_0_1_valid ? _io_resp_f3_1_taken_T_4 : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_1 = f3_resps_5_1_valid ? _T_64 : f3_resps_4_1_valid ? _T_60 : f3_resps_3_1_valid ? _T_56 : f3_resps_2_1_valid ? _T_52 : f3_resps_1_1_valid & f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_1_valid = f3_resps_0_1_valid | f3_resps_1_1_valid | f3_resps_2_1_valid | f3_resps_3_1_valid | f3_resps_4_1_valid | f3_resps_5_1_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_1_bits = f3_resps_5_1_valid ? 3'h5 : f3_resps_4_1_valid ? 3'h4 : {1'h0, f3_resps_3_1_valid ? 2'h3 : f3_resps_2_1_valid ? 2'h2 : {1'h0, f3_resps_1_1_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_1_T = final_altpred_1 != io_resp_f3_1_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_1 = _f3_meta_alt_differs_1_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_15 = {{f3_resps_0_1_bits_ctr}, {f3_resps_0_1_bits_ctr}, {f3_resps_5_1_bits_ctr}, {f3_resps_4_1_bits_ctr}, {f3_resps_3_1_bits_ctr}, {f3_resps_2_1_bits_ctr}, {f3_resps_1_1_bits_ctr}, {f3_resps_0_1_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_1 = _GEN_15[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_16 = {{f3_resps_0_1_bits_u}, {f3_resps_0_1_bits_u}, {f3_resps_5_1_bits_u}, {f3_resps_4_1_bits_u}, {f3_resps_3_1_bits_u}, {f3_resps_2_1_bits_u}, {f3_resps_1_1_bits_u}, {f3_resps_0_1_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_1 = _GEN_16[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_38 = ~f3_resps_0_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_39 = f3_resps_0_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_40 = _allocatable_slots_T_38 & _allocatable_slots_T_39; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_0 = _allocatable_slots_T_40; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_41 = ~f3_resps_1_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_42 = f3_resps_1_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_43 = _allocatable_slots_T_41 & _allocatable_slots_T_42; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_1 = _allocatable_slots_T_43; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_44 = ~f3_resps_2_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_45 = f3_resps_2_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_46 = _allocatable_slots_T_44 & _allocatable_slots_T_45; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_2 = _allocatable_slots_T_46; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_47 = ~f3_resps_3_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_48 = f3_resps_3_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_49 = _allocatable_slots_T_47 & _allocatable_slots_T_48; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_3 = _allocatable_slots_T_49; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_50 = ~f3_resps_4_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_51 = f3_resps_4_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_52 = _allocatable_slots_T_50 & _allocatable_slots_T_51; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_4 = _allocatable_slots_T_52; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_53 = ~f3_resps_5_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_54 = f3_resps_5_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_55 = _allocatable_slots_T_53 & _allocatable_slots_T_54; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_5 = _allocatable_slots_T_55; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_1 = {_allocatable_slots_WIRE_1_2, _allocatable_slots_WIRE_1_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_1 = {allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_1 = {_allocatable_slots_WIRE_1_5, _allocatable_slots_WIRE_1_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_1 = {allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_56 = {allocatable_slots_hi_1, allocatable_slots_lo_1}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_57 = 8'h1 << f3_meta_provider_1_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_58 = _allocatable_slots_T_57; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_59 = {1'h0, _allocatable_slots_T_57[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_60 = {2'h0, _allocatable_slots_T_57[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_61 = {3'h0, _allocatable_slots_T_57[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_62 = {4'h0, _allocatable_slots_T_57[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_63 = {5'h0, _allocatable_slots_T_57[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_64 = {6'h0, _allocatable_slots_T_57[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_65 = {7'h0, _allocatable_slots_T_57[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_66 = _allocatable_slots_T_58 | _allocatable_slots_T_59; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_67 = _allocatable_slots_T_66 | _allocatable_slots_T_60; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_68 = _allocatable_slots_T_67 | _allocatable_slots_T_61; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_69 = _allocatable_slots_T_68 | _allocatable_slots_T_62; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_70 = _allocatable_slots_T_69 | _allocatable_slots_T_63; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_71 = _allocatable_slots_T_70 | _allocatable_slots_T_64; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_72 = _allocatable_slots_T_71 | _allocatable_slots_T_65; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_73 = {6{f3_meta_provider_1_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_74 = {2'h0, _allocatable_slots_T_72[5:0] & _allocatable_slots_T_73}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_75 = ~_allocatable_slots_T_74; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_1 = {2'h0, _allocatable_slots_T_75[5:0] & _allocatable_slots_T_56}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_1 = {_alloc_lfsr_prng_1_io_out_2, _alloc_lfsr_prng_1_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_1 = {alloc_lfsr_lo_hi_1, _alloc_lfsr_prng_1_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_1 = {_alloc_lfsr_prng_1_io_out_5, _alloc_lfsr_prng_1_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_1 = {alloc_lfsr_hi_hi_1, _alloc_lfsr_prng_1_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_1 = {alloc_lfsr_hi_1, alloc_lfsr_lo_1}; // @[PRNG.scala:95:17] wire _first_entry_T_14 = allocatable_slots_1[0]; // @[OneHot.scala:48:45] wire _first_entry_T_15 = allocatable_slots_1[1]; // @[OneHot.scala:48:45] wire _first_entry_T_16 = allocatable_slots_1[2]; // @[OneHot.scala:48:45] wire _first_entry_T_17 = allocatable_slots_1[3]; // @[OneHot.scala:48:45] wire _first_entry_T_18 = allocatable_slots_1[4]; // @[OneHot.scala:48:45] wire _first_entry_T_19 = allocatable_slots_1[5]; // @[OneHot.scala:48:45] wire _first_entry_T_20 = allocatable_slots_1[6]; // @[OneHot.scala:48:45] wire _first_entry_T_21 = allocatable_slots_1[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_22 = {2'h3, ~_first_entry_T_20}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_23 = _first_entry_T_19 ? 3'h5 : _first_entry_T_22; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_24 = _first_entry_T_18 ? 3'h4 : _first_entry_T_23; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_25 = _first_entry_T_17 ? 3'h3 : _first_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_26 = _first_entry_T_16 ? 3'h2 : _first_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_27 = _first_entry_T_15 ? 3'h1 : _first_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] first_entry_1 = _first_entry_T_14 ? 3'h0 : _first_entry_T_27; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_15 = {2'h0, allocatable_slots_1[5:0] & alloc_lfsr_1}; // @[PRNG.scala:95:17] wire _masked_entry_T_16 = _masked_entry_T_15[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_17 = _masked_entry_T_15[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_18 = _masked_entry_T_15[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_19 = _masked_entry_T_15[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_20 = _masked_entry_T_15[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_21 = _masked_entry_T_15[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_22 = _masked_entry_T_15[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_23 = _masked_entry_T_15[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_24 = {2'h3, ~_masked_entry_T_22}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_25 = _masked_entry_T_21 ? 3'h5 : _masked_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_26 = _masked_entry_T_20 ? 3'h4 : _masked_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_27 = _masked_entry_T_19 ? 3'h3 : _masked_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_28 = _masked_entry_T_18 ? 3'h2 : _masked_entry_T_27; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_29 = _masked_entry_T_17 ? 3'h1 : _masked_entry_T_28; // @[OneHot.scala:48:45] wire [2:0] masked_entry_1 = _masked_entry_T_16 ? 3'h0 : _masked_entry_T_29; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_2 = allocatable_slots_1 >> masked_entry_1; // @[Mux.scala:50:70] wire _alloc_entry_T_3 = _alloc_entry_T_2[0]; // @[tage.scala:289:44] assign alloc_entry_1 = _alloc_entry_T_3 ? masked_entry_1 : first_entry_1; // @[Mux.scala:50:70] assign f3_meta_allocate_1_bits = alloc_entry_1; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_1_valid_T = |allocatable_slots_1; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_1_valid = _f3_meta_allocate_1_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_2 = s1_update_bits_cfi_idx_bits == 2'h1; // @[tage.scala:297:58] wire _update_was_taken_T_3 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_2; // @[tage.scala:296:58, :297:58] wire update_was_taken_1 = _update_was_taken_T_3 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_75 = s1_update_bits_br_mask[1] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_17 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_18 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_19 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_20 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_21 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_22 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_11 = s1_update_mispredict_mask[1]; // @[tage.scala:237:73, :308:52] wire _new_u_T_12 = ~s1_update_meta_alt_differs_1; // @[tage.scala:217:9, :236:52] wire _new_u_T_13 = s1_update_meta_provider_u_1 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_23 = {1'h0, s1_update_meta_provider_u_1}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_14 = _GEN_23 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_15 = _new_u_T_14[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_16 = _new_u_T_13 ? 2'h0 : _new_u_T_15; // @[tage.scala:218:{24,27,43}] wire _new_u_T_17 = &s1_update_meta_provider_u_1; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_18 = _GEN_23 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_19 = _new_u_T_18[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_20 = _new_u_T_17 ? 2'h3 : _new_u_T_19; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_21 = _new_u_T_11 ? _new_u_T_16 : _new_u_T_20; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_1 = _new_u_T_12 ? s1_update_meta_provider_u_1 : _new_u_T_21; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_2; // @[tage.scala:256:33] wire _io_resp_f3_2_taken_T = f3_resps_0_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_1 = f3_resps_0_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_2 = _io_resp_f3_2_taken_T | _io_resp_f3_2_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_3 = f3_resps_0_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_4 = _io_resp_f3_2_taken_T_2 ? io_resp_in_0_f3_2_taken_0 : _io_resp_f3_2_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_79 = f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_5 = f3_resps_1_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_6 = f3_resps_1_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_7 = _io_resp_f3_2_taken_T_5 | _io_resp_f3_2_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_8 = f3_resps_1_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_9 = _io_resp_f3_2_taken_T_7 ? _T_79 : _io_resp_f3_2_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_83 = f3_resps_1_2_valid ? f3_resps_1_2_bits_ctr[2] : _T_79; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_10 = f3_resps_2_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_11 = f3_resps_2_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_12 = _io_resp_f3_2_taken_T_10 | _io_resp_f3_2_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_13 = f3_resps_2_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_14 = _io_resp_f3_2_taken_T_12 ? _T_83 : _io_resp_f3_2_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_87 = f3_resps_2_2_valid ? f3_resps_2_2_bits_ctr[2] : _T_83; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_15 = f3_resps_3_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_16 = f3_resps_3_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_17 = _io_resp_f3_2_taken_T_15 | _io_resp_f3_2_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_18 = f3_resps_3_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_19 = _io_resp_f3_2_taken_T_17 ? _T_87 : _io_resp_f3_2_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_91 = f3_resps_3_2_valid ? f3_resps_3_2_bits_ctr[2] : _T_87; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_20 = f3_resps_4_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_21 = f3_resps_4_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_22 = _io_resp_f3_2_taken_T_20 | _io_resp_f3_2_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_23 = f3_resps_4_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_24 = _io_resp_f3_2_taken_T_22 ? _T_91 : _io_resp_f3_2_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_95 = f3_resps_4_2_valid ? f3_resps_4_2_bits_ctr[2] : _T_91; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_25 = f3_resps_5_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_26 = f3_resps_5_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_27 = _io_resp_f3_2_taken_T_25 | _io_resp_f3_2_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_28 = f3_resps_5_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_29 = _io_resp_f3_2_taken_T_27 ? _T_95 : _io_resp_f3_2_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_2_taken_0 = f3_resps_5_2_valid ? _io_resp_f3_2_taken_T_29 : f3_resps_4_2_valid ? _io_resp_f3_2_taken_T_24 : f3_resps_3_2_valid ? _io_resp_f3_2_taken_T_19 : f3_resps_2_2_valid ? _io_resp_f3_2_taken_T_14 : f3_resps_1_2_valid ? _io_resp_f3_2_taken_T_9 : f3_resps_0_2_valid ? _io_resp_f3_2_taken_T_4 : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_2 = f3_resps_5_2_valid ? _T_95 : f3_resps_4_2_valid ? _T_91 : f3_resps_3_2_valid ? _T_87 : f3_resps_2_2_valid ? _T_83 : f3_resps_1_2_valid & f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_2_valid = f3_resps_0_2_valid | f3_resps_1_2_valid | f3_resps_2_2_valid | f3_resps_3_2_valid | f3_resps_4_2_valid | f3_resps_5_2_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_2_bits = f3_resps_5_2_valid ? 3'h5 : f3_resps_4_2_valid ? 3'h4 : {1'h0, f3_resps_3_2_valid ? 2'h3 : f3_resps_2_2_valid ? 2'h2 : {1'h0, f3_resps_1_2_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_2_T = final_altpred_2 != io_resp_f3_2_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_2 = _f3_meta_alt_differs_2_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_24 = {{f3_resps_0_2_bits_ctr}, {f3_resps_0_2_bits_ctr}, {f3_resps_5_2_bits_ctr}, {f3_resps_4_2_bits_ctr}, {f3_resps_3_2_bits_ctr}, {f3_resps_2_2_bits_ctr}, {f3_resps_1_2_bits_ctr}, {f3_resps_0_2_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_2 = _GEN_24[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_25 = {{f3_resps_0_2_bits_u}, {f3_resps_0_2_bits_u}, {f3_resps_5_2_bits_u}, {f3_resps_4_2_bits_u}, {f3_resps_3_2_bits_u}, {f3_resps_2_2_bits_u}, {f3_resps_1_2_bits_u}, {f3_resps_0_2_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_2 = _GEN_25[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_76 = ~f3_resps_0_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_77 = f3_resps_0_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_78 = _allocatable_slots_T_76 & _allocatable_slots_T_77; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_0 = _allocatable_slots_T_78; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_79 = ~f3_resps_1_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_80 = f3_resps_1_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_81 = _allocatable_slots_T_79 & _allocatable_slots_T_80; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_1 = _allocatable_slots_T_81; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_82 = ~f3_resps_2_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_83 = f3_resps_2_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_84 = _allocatable_slots_T_82 & _allocatable_slots_T_83; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_2 = _allocatable_slots_T_84; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_85 = ~f3_resps_3_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_86 = f3_resps_3_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_87 = _allocatable_slots_T_85 & _allocatable_slots_T_86; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_3 = _allocatable_slots_T_87; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_88 = ~f3_resps_4_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_89 = f3_resps_4_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_90 = _allocatable_slots_T_88 & _allocatable_slots_T_89; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_4 = _allocatable_slots_T_90; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_91 = ~f3_resps_5_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_92 = f3_resps_5_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_93 = _allocatable_slots_T_91 & _allocatable_slots_T_92; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_5 = _allocatable_slots_T_93; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_2 = {_allocatable_slots_WIRE_2_2, _allocatable_slots_WIRE_2_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_2 = {allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_2 = {_allocatable_slots_WIRE_2_5, _allocatable_slots_WIRE_2_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_2 = {allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_94 = {allocatable_slots_hi_2, allocatable_slots_lo_2}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_95 = 8'h1 << f3_meta_provider_2_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_96 = _allocatable_slots_T_95; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_97 = {1'h0, _allocatable_slots_T_95[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_98 = {2'h0, _allocatable_slots_T_95[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_99 = {3'h0, _allocatable_slots_T_95[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_100 = {4'h0, _allocatable_slots_T_95[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_101 = {5'h0, _allocatable_slots_T_95[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_102 = {6'h0, _allocatable_slots_T_95[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_103 = {7'h0, _allocatable_slots_T_95[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_104 = _allocatable_slots_T_96 | _allocatable_slots_T_97; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_105 = _allocatable_slots_T_104 | _allocatable_slots_T_98; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_106 = _allocatable_slots_T_105 | _allocatable_slots_T_99; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_107 = _allocatable_slots_T_106 | _allocatable_slots_T_100; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_108 = _allocatable_slots_T_107 | _allocatable_slots_T_101; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_109 = _allocatable_slots_T_108 | _allocatable_slots_T_102; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_110 = _allocatable_slots_T_109 | _allocatable_slots_T_103; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_111 = {6{f3_meta_provider_2_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_112 = {2'h0, _allocatable_slots_T_110[5:0] & _allocatable_slots_T_111}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_113 = ~_allocatable_slots_T_112; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_2 = {2'h0, _allocatable_slots_T_113[5:0] & _allocatable_slots_T_94}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_2 = {_alloc_lfsr_prng_2_io_out_2, _alloc_lfsr_prng_2_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_2 = {alloc_lfsr_lo_hi_2, _alloc_lfsr_prng_2_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_2 = {_alloc_lfsr_prng_2_io_out_5, _alloc_lfsr_prng_2_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_2 = {alloc_lfsr_hi_hi_2, _alloc_lfsr_prng_2_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_2 = {alloc_lfsr_hi_2, alloc_lfsr_lo_2}; // @[PRNG.scala:95:17] wire _first_entry_T_28 = allocatable_slots_2[0]; // @[OneHot.scala:48:45] wire _first_entry_T_29 = allocatable_slots_2[1]; // @[OneHot.scala:48:45] wire _first_entry_T_30 = allocatable_slots_2[2]; // @[OneHot.scala:48:45] wire _first_entry_T_31 = allocatable_slots_2[3]; // @[OneHot.scala:48:45] wire _first_entry_T_32 = allocatable_slots_2[4]; // @[OneHot.scala:48:45] wire _first_entry_T_33 = allocatable_slots_2[5]; // @[OneHot.scala:48:45] wire _first_entry_T_34 = allocatable_slots_2[6]; // @[OneHot.scala:48:45] wire _first_entry_T_35 = allocatable_slots_2[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_36 = {2'h3, ~_first_entry_T_34}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_37 = _first_entry_T_33 ? 3'h5 : _first_entry_T_36; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_38 = _first_entry_T_32 ? 3'h4 : _first_entry_T_37; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_39 = _first_entry_T_31 ? 3'h3 : _first_entry_T_38; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_40 = _first_entry_T_30 ? 3'h2 : _first_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_41 = _first_entry_T_29 ? 3'h1 : _first_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] first_entry_2 = _first_entry_T_28 ? 3'h0 : _first_entry_T_41; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_30 = {2'h0, allocatable_slots_2[5:0] & alloc_lfsr_2}; // @[PRNG.scala:95:17] wire _masked_entry_T_31 = _masked_entry_T_30[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_32 = _masked_entry_T_30[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_33 = _masked_entry_T_30[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_34 = _masked_entry_T_30[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_35 = _masked_entry_T_30[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_36 = _masked_entry_T_30[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_37 = _masked_entry_T_30[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_38 = _masked_entry_T_30[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_39 = {2'h3, ~_masked_entry_T_37}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_40 = _masked_entry_T_36 ? 3'h5 : _masked_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_41 = _masked_entry_T_35 ? 3'h4 : _masked_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_42 = _masked_entry_T_34 ? 3'h3 : _masked_entry_T_41; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_43 = _masked_entry_T_33 ? 3'h2 : _masked_entry_T_42; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_44 = _masked_entry_T_32 ? 3'h1 : _masked_entry_T_43; // @[OneHot.scala:48:45] wire [2:0] masked_entry_2 = _masked_entry_T_31 ? 3'h0 : _masked_entry_T_44; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_4 = allocatable_slots_2 >> masked_entry_2; // @[Mux.scala:50:70] wire _alloc_entry_T_5 = _alloc_entry_T_4[0]; // @[tage.scala:289:44] assign alloc_entry_2 = _alloc_entry_T_5 ? masked_entry_2 : first_entry_2; // @[Mux.scala:50:70] assign f3_meta_allocate_2_bits = alloc_entry_2; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_2_valid_T = |allocatable_slots_2; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_2_valid = _f3_meta_allocate_2_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_4 = s1_update_bits_cfi_idx_bits == 2'h2; // @[tage.scala:297:58] wire _update_was_taken_T_5 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_4; // @[tage.scala:296:58, :297:58] wire update_was_taken_2 = _update_was_taken_T_5 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_106 = s1_update_bits_br_mask[2] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_26 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_27 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_28 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_29 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_30 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_31 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_22 = s1_update_mispredict_mask[2]; // @[tage.scala:237:73, :308:52] wire _new_u_T_23 = ~s1_update_meta_alt_differs_2; // @[tage.scala:217:9, :236:52] wire _new_u_T_24 = s1_update_meta_provider_u_2 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_32 = {1'h0, s1_update_meta_provider_u_2}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_25 = _GEN_32 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_26 = _new_u_T_25[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_27 = _new_u_T_24 ? 2'h0 : _new_u_T_26; // @[tage.scala:218:{24,27,43}] wire _new_u_T_28 = &s1_update_meta_provider_u_2; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_29 = _GEN_32 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_30 = _new_u_T_29[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_31 = _new_u_T_28 ? 2'h3 : _new_u_T_30; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_32 = _new_u_T_22 ? _new_u_T_27 : _new_u_T_31; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_2 = _new_u_T_23 ? s1_update_meta_provider_u_2 : _new_u_T_32; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_3; // @[tage.scala:256:33] wire _io_resp_f3_3_taken_T = f3_resps_0_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_1 = f3_resps_0_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_2 = _io_resp_f3_3_taken_T | _io_resp_f3_3_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_3 = f3_resps_0_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_4 = _io_resp_f3_3_taken_T_2 ? io_resp_in_0_f3_3_taken_0 : _io_resp_f3_3_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_110 = f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_5 = f3_resps_1_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_6 = f3_resps_1_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_7 = _io_resp_f3_3_taken_T_5 | _io_resp_f3_3_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_8 = f3_resps_1_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_9 = _io_resp_f3_3_taken_T_7 ? _T_110 : _io_resp_f3_3_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_114 = f3_resps_1_3_valid ? f3_resps_1_3_bits_ctr[2] : _T_110; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_10 = f3_resps_2_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_11 = f3_resps_2_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_12 = _io_resp_f3_3_taken_T_10 | _io_resp_f3_3_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_13 = f3_resps_2_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_14 = _io_resp_f3_3_taken_T_12 ? _T_114 : _io_resp_f3_3_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_118 = f3_resps_2_3_valid ? f3_resps_2_3_bits_ctr[2] : _T_114; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_15 = f3_resps_3_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_16 = f3_resps_3_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_17 = _io_resp_f3_3_taken_T_15 | _io_resp_f3_3_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_18 = f3_resps_3_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_19 = _io_resp_f3_3_taken_T_17 ? _T_118 : _io_resp_f3_3_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_122 = f3_resps_3_3_valid ? f3_resps_3_3_bits_ctr[2] : _T_118; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_20 = f3_resps_4_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_21 = f3_resps_4_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_22 = _io_resp_f3_3_taken_T_20 | _io_resp_f3_3_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_23 = f3_resps_4_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_24 = _io_resp_f3_3_taken_T_22 ? _T_122 : _io_resp_f3_3_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_126 = f3_resps_4_3_valid ? f3_resps_4_3_bits_ctr[2] : _T_122; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_25 = f3_resps_5_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_26 = f3_resps_5_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_27 = _io_resp_f3_3_taken_T_25 | _io_resp_f3_3_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_28 = f3_resps_5_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_29 = _io_resp_f3_3_taken_T_27 ? _T_126 : _io_resp_f3_3_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_3_taken_0 = f3_resps_5_3_valid ? _io_resp_f3_3_taken_T_29 : f3_resps_4_3_valid ? _io_resp_f3_3_taken_T_24 : f3_resps_3_3_valid ? _io_resp_f3_3_taken_T_19 : f3_resps_2_3_valid ? _io_resp_f3_3_taken_T_14 : f3_resps_1_3_valid ? _io_resp_f3_3_taken_T_9 : f3_resps_0_3_valid ? _io_resp_f3_3_taken_T_4 : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_3 = f3_resps_5_3_valid ? _T_126 : f3_resps_4_3_valid ? _T_122 : f3_resps_3_3_valid ? _T_118 : f3_resps_2_3_valid ? _T_114 : f3_resps_1_3_valid & f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_3_valid = f3_resps_0_3_valid | f3_resps_1_3_valid | f3_resps_2_3_valid | f3_resps_3_3_valid | f3_resps_4_3_valid | f3_resps_5_3_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_3_bits = f3_resps_5_3_valid ? 3'h5 : f3_resps_4_3_valid ? 3'h4 : {1'h0, f3_resps_3_3_valid ? 2'h3 : f3_resps_2_3_valid ? 2'h2 : {1'h0, f3_resps_1_3_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_3_T = final_altpred_3 != io_resp_f3_3_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_3 = _f3_meta_alt_differs_3_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_33 = {{f3_resps_0_3_bits_ctr}, {f3_resps_0_3_bits_ctr}, {f3_resps_5_3_bits_ctr}, {f3_resps_4_3_bits_ctr}, {f3_resps_3_3_bits_ctr}, {f3_resps_2_3_bits_ctr}, {f3_resps_1_3_bits_ctr}, {f3_resps_0_3_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_3 = _GEN_33[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_34 = {{f3_resps_0_3_bits_u}, {f3_resps_0_3_bits_u}, {f3_resps_5_3_bits_u}, {f3_resps_4_3_bits_u}, {f3_resps_3_3_bits_u}, {f3_resps_2_3_bits_u}, {f3_resps_1_3_bits_u}, {f3_resps_0_3_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_3 = _GEN_34[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_114 = ~f3_resps_0_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_115 = f3_resps_0_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_116 = _allocatable_slots_T_114 & _allocatable_slots_T_115; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_0 = _allocatable_slots_T_116; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_117 = ~f3_resps_1_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_118 = f3_resps_1_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_119 = _allocatable_slots_T_117 & _allocatable_slots_T_118; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_1 = _allocatable_slots_T_119; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_120 = ~f3_resps_2_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_121 = f3_resps_2_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_122 = _allocatable_slots_T_120 & _allocatable_slots_T_121; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_2 = _allocatable_slots_T_122; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_123 = ~f3_resps_3_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_124 = f3_resps_3_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_125 = _allocatable_slots_T_123 & _allocatable_slots_T_124; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_3 = _allocatable_slots_T_125; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_126 = ~f3_resps_4_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_127 = f3_resps_4_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_128 = _allocatable_slots_T_126 & _allocatable_slots_T_127; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_4 = _allocatable_slots_T_128; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_129 = ~f3_resps_5_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_130 = f3_resps_5_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_131 = _allocatable_slots_T_129 & _allocatable_slots_T_130; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_5 = _allocatable_slots_T_131; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_3 = {_allocatable_slots_WIRE_3_2, _allocatable_slots_WIRE_3_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_3 = {allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_3 = {_allocatable_slots_WIRE_3_5, _allocatable_slots_WIRE_3_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_3 = {allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_132 = {allocatable_slots_hi_3, allocatable_slots_lo_3}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_133 = 8'h1 << f3_meta_provider_3_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_134 = _allocatable_slots_T_133; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_135 = {1'h0, _allocatable_slots_T_133[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_136 = {2'h0, _allocatable_slots_T_133[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_137 = {3'h0, _allocatable_slots_T_133[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_138 = {4'h0, _allocatable_slots_T_133[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_139 = {5'h0, _allocatable_slots_T_133[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_140 = {6'h0, _allocatable_slots_T_133[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_141 = {7'h0, _allocatable_slots_T_133[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_142 = _allocatable_slots_T_134 | _allocatable_slots_T_135; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_143 = _allocatable_slots_T_142 | _allocatable_slots_T_136; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_144 = _allocatable_slots_T_143 | _allocatable_slots_T_137; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_145 = _allocatable_slots_T_144 | _allocatable_slots_T_138; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_146 = _allocatable_slots_T_145 | _allocatable_slots_T_139; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_147 = _allocatable_slots_T_146 | _allocatable_slots_T_140; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_148 = _allocatable_slots_T_147 | _allocatable_slots_T_141; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_149 = {6{f3_meta_provider_3_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_150 = {2'h0, _allocatable_slots_T_148[5:0] & _allocatable_slots_T_149}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_151 = ~_allocatable_slots_T_150; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_3 = {2'h0, _allocatable_slots_T_151[5:0] & _allocatable_slots_T_132}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_3 = {_alloc_lfsr_prng_3_io_out_2, _alloc_lfsr_prng_3_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_3 = {alloc_lfsr_lo_hi_3, _alloc_lfsr_prng_3_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_3 = {_alloc_lfsr_prng_3_io_out_5, _alloc_lfsr_prng_3_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_3 = {alloc_lfsr_hi_hi_3, _alloc_lfsr_prng_3_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_3 = {alloc_lfsr_hi_3, alloc_lfsr_lo_3}; // @[PRNG.scala:95:17] wire _first_entry_T_42 = allocatable_slots_3[0]; // @[OneHot.scala:48:45] wire _first_entry_T_43 = allocatable_slots_3[1]; // @[OneHot.scala:48:45] wire _first_entry_T_44 = allocatable_slots_3[2]; // @[OneHot.scala:48:45] wire _first_entry_T_45 = allocatable_slots_3[3]; // @[OneHot.scala:48:45] wire _first_entry_T_46 = allocatable_slots_3[4]; // @[OneHot.scala:48:45] wire _first_entry_T_47 = allocatable_slots_3[5]; // @[OneHot.scala:48:45] wire _first_entry_T_48 = allocatable_slots_3[6]; // @[OneHot.scala:48:45] wire _first_entry_T_49 = allocatable_slots_3[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_50 = {2'h3, ~_first_entry_T_48}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_51 = _first_entry_T_47 ? 3'h5 : _first_entry_T_50; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_52 = _first_entry_T_46 ? 3'h4 : _first_entry_T_51; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_53 = _first_entry_T_45 ? 3'h3 : _first_entry_T_52; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_54 = _first_entry_T_44 ? 3'h2 : _first_entry_T_53; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_55 = _first_entry_T_43 ? 3'h1 : _first_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] first_entry_3 = _first_entry_T_42 ? 3'h0 : _first_entry_T_55; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_45 = {2'h0, allocatable_slots_3[5:0] & alloc_lfsr_3}; // @[PRNG.scala:95:17] wire _masked_entry_T_46 = _masked_entry_T_45[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_47 = _masked_entry_T_45[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_48 = _masked_entry_T_45[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_49 = _masked_entry_T_45[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_50 = _masked_entry_T_45[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_51 = _masked_entry_T_45[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_52 = _masked_entry_T_45[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_53 = _masked_entry_T_45[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_54 = {2'h3, ~_masked_entry_T_52}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_55 = _masked_entry_T_51 ? 3'h5 : _masked_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_56 = _masked_entry_T_50 ? 3'h4 : _masked_entry_T_55; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_57 = _masked_entry_T_49 ? 3'h3 : _masked_entry_T_56; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_58 = _masked_entry_T_48 ? 3'h2 : _masked_entry_T_57; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_59 = _masked_entry_T_47 ? 3'h1 : _masked_entry_T_58; // @[OneHot.scala:48:45] wire [2:0] masked_entry_3 = _masked_entry_T_46 ? 3'h0 : _masked_entry_T_59; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_6 = allocatable_slots_3 >> masked_entry_3; // @[Mux.scala:50:70] wire _alloc_entry_T_7 = _alloc_entry_T_6[0]; // @[tage.scala:289:44] assign alloc_entry_3 = _alloc_entry_T_7 ? masked_entry_3 : first_entry_3; // @[Mux.scala:50:70] assign f3_meta_allocate_3_bits = alloc_entry_3; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_3_valid_T = |allocatable_slots_3; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_3_valid = _f3_meta_allocate_3_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_6 = &s1_update_bits_cfi_idx_bits; // @[tage.scala:297:58] wire _update_was_taken_T_7 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_6; // @[tage.scala:296:58, :297:58] wire update_was_taken_3 = _update_was_taken_T_7 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_137 = s1_update_bits_br_mask[3] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_35 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_36 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_37 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_38 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_39 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_40 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_33 = s1_update_mispredict_mask[3]; // @[tage.scala:237:73, :308:52] wire _new_u_T_34 = ~s1_update_meta_alt_differs_3; // @[tage.scala:217:9, :236:52] wire _new_u_T_35 = s1_update_meta_provider_u_3 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_41 = {1'h0, s1_update_meta_provider_u_3}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_36 = _GEN_41 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_37 = _new_u_T_36[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_38 = _new_u_T_35 ? 2'h0 : _new_u_T_37; // @[tage.scala:218:{24,27,43}] wire _new_u_T_39 = &s1_update_meta_provider_u_3; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_40 = _GEN_41 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_41 = _new_u_T_40[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_42 = _new_u_T_39 ? 2'h3 : _new_u_T_41; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_43 = _new_u_T_33 ? _new_u_T_38 : _new_u_T_42; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_3 = _new_u_T_34 ? s1_update_meta_provider_u_3 : _new_u_T_43; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire _T_144 = s1_update_valid & _GEN_7 == 5'h0 & s1_update_bits_cfi_mispredicted & s1_update_bits_cfi_idx_valid; // @[OneHot.scala:58:35] wire [3:0] _GEN_42 = {{s1_update_meta_allocate_3_valid}, {s1_update_meta_allocate_2_valid}, {s1_update_meta_allocate_1_valid}, {s1_update_meta_allocate_0_valid}}; // @[tage.scala:236:52, :320:27] wire _GEN_43 = _GEN_42[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire [3:0][2:0] _GEN_44 = {{s1_update_meta_allocate_3_bits}, {s1_update_meta_allocate_2_bits}, {s1_update_meta_allocate_1_bits}, {s1_update_meta_allocate_0_bits}}; // @[tage.scala:236:52, :320:27] wire [2:0] _GEN_45 = _GEN_44[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire _GEN_46 = _GEN_45 == 3'h0; // @[tage.scala:320:27, :321:43] wire _GEN_47 = _T_144 & _GEN_43 & _GEN_46; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_0_0 = _GEN_47 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_0 = s1_update_alloc_0_0 | _GEN_8; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_1 = _GEN_47 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_1 = s1_update_alloc_0_1 | _GEN_17; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_2 = _GEN_47 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_2 = s1_update_alloc_0_2 | _GEN_26; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_3 = _GEN_47 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_3 = s1_update_alloc_0_3 | _GEN_35; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_48 = _GEN_45 == 3'h1; // @[tage.scala:218:43, :320:27, :321:43] wire _GEN_49 = _T_144 & _GEN_43 & _GEN_48; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_1_0 = _GEN_49 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_0 = s1_update_alloc_1_0 | _GEN_9; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_1 = _GEN_49 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_1 = s1_update_alloc_1_1 | _GEN_18; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_2 = _GEN_49 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_2 = s1_update_alloc_1_2 | _GEN_27; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_3 = _GEN_49 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_3 = s1_update_alloc_1_3 | _GEN_36; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_50 = _GEN_45 == 3'h2; // @[tage.scala:320:27, :321:43] wire _GEN_51 = _T_144 & _GEN_43 & _GEN_50; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_2_0 = _GEN_51 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_0 = s1_update_alloc_2_0 | _GEN_10; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_1 = _GEN_51 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_1 = s1_update_alloc_2_1 | _GEN_19; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_2 = _GEN_51 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_2 = s1_update_alloc_2_2 | _GEN_28; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_3 = _GEN_51 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_3 = s1_update_alloc_2_3 | _GEN_37; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_52 = _GEN_45 == 3'h3; // @[tage.scala:265:40, :320:27, :321:43] wire _GEN_53 = _T_144 & _GEN_43 & _GEN_52; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_3_0 = _GEN_53 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_0 = s1_update_alloc_3_0 | _GEN_11; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_1 = _GEN_53 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_1 = s1_update_alloc_3_1 | _GEN_20; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_2 = _GEN_53 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_2 = s1_update_alloc_3_2 | _GEN_29; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_3 = _GEN_53 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_3 = s1_update_alloc_3_3 | _GEN_38; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_54 = _GEN_45 == 3'h4; // @[tage.scala:320:27, :321:43] wire _GEN_55 = _T_144 & _GEN_43 & _GEN_54; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_4_0 = _GEN_55 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_0 = s1_update_alloc_4_0 | _GEN_12; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_1 = _GEN_55 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_1 = s1_update_alloc_4_1 | _GEN_21; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_2 = _GEN_55 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_2 = s1_update_alloc_4_2 | _GEN_30; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_3 = _GEN_55 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_3 = s1_update_alloc_4_3 | _GEN_39; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_56 = _GEN_45 == 3'h5; // @[tage.scala:320:27, :321:43] wire _GEN_57 = _T_144 & _GEN_43 & _GEN_56; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_5_0 = _GEN_57 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_0 = s1_update_alloc_5_0 | _GEN_13; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_1 = _GEN_57 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_1 = s1_update_alloc_5_1 | _GEN_22; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_2 = _GEN_57 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_2 = s1_update_alloc_5_2 | _GEN_31; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_3 = _GEN_57 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_3 = s1_update_alloc_5_3 | _GEN_40; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_58 = _GEN_46 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_0 = _T_144 & _GEN_43 & _GEN_58 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_59 = _GEN_46 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_1 = _T_144 & _GEN_43 & _GEN_59 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_60 = _GEN_46 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_2 = _T_144 & _GEN_43 & _GEN_60 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_61 = _GEN_46 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_3 = _T_144 & _GEN_43 & _GEN_61 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_62 = _GEN_48 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_0 = _T_144 & _GEN_43 & _GEN_62 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_63 = _GEN_48 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_1 = _T_144 & _GEN_43 & _GEN_63 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_64 = _GEN_48 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_2 = _T_144 & _GEN_43 & _GEN_64 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_65 = _GEN_48 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_3 = _T_144 & _GEN_43 & _GEN_65 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_66 = _GEN_50 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_0 = _T_144 & _GEN_43 & _GEN_66 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_67 = _GEN_50 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_1 = _T_144 & _GEN_43 & _GEN_67 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_68 = _GEN_50 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_2 = _T_144 & _GEN_43 & _GEN_68 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_69 = _GEN_50 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_3 = _T_144 & _GEN_43 & _GEN_69 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_70 = _GEN_52 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_0 = _T_144 & _GEN_43 & _GEN_70 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_71 = _GEN_52 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_1 = _T_144 & _GEN_43 & _GEN_71 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_72 = _GEN_52 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_2 = _T_144 & _GEN_43 & _GEN_72 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_73 = _GEN_52 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_3 = _T_144 & _GEN_43 & _GEN_73 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_74 = _GEN_54 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_0 = _T_144 & _GEN_43 & _GEN_74 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_75 = _GEN_54 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_1 = _T_144 & _GEN_43 & _GEN_75 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_76 = _GEN_54 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_2 = _T_144 & _GEN_43 & _GEN_76 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_77 = _GEN_54 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_3 = _T_144 & _GEN_43 & _GEN_77 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_78 = _GEN_56 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_0 = _T_144 & _GEN_43 & _GEN_78 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_79 = _GEN_56 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_1 = _T_144 & _GEN_43 & _GEN_79 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_80 = _GEN_56 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_2 = _T_144 & _GEN_43 & _GEN_80 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_81 = _GEN_56 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_3 = _T_144 & _GEN_43 & _GEN_81 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire [3:0] _GEN_82 = {{s1_update_meta_provider_3_valid}, {s1_update_meta_provider_2_valid}, {s1_update_meta_provider_1_valid}, {s1_update_meta_provider_0_valid}}; // @[OneHot.scala:58:35] wire [3:0][2:0] _GEN_83 = {{s1_update_meta_provider_3_bits}, {s1_update_meta_provider_2_bits}, {s1_update_meta_provider_1_bits}, {s1_update_meta_provider_0_bits}}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T = 8'h1 << _GEN_83[s1_update_bits_cfi_idx_bits]; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_1 = _decr_mask_T; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_2 = {1'h0, _decr_mask_T[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_3 = {2'h0, _decr_mask_T[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_4 = {3'h0, _decr_mask_T[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_5 = {4'h0, _decr_mask_T[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_6 = {5'h0, _decr_mask_T[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_7 = {6'h0, _decr_mask_T[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_8 = {7'h0, _decr_mask_T[7]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_9 = _decr_mask_T_1 | _decr_mask_T_2; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_10 = _decr_mask_T_9 | _decr_mask_T_3; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_11 = _decr_mask_T_10 | _decr_mask_T_4; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_12 = _decr_mask_T_11 | _decr_mask_T_5; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_13 = _decr_mask_T_12 | _decr_mask_T_6; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_14 = _decr_mask_T_13 | _decr_mask_T_7; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_15 = _decr_mask_T_14 | _decr_mask_T_8; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_16 = ~_decr_mask_T_15; // @[util.scala:373:45] wire [7:0] decr_mask = _GEN_82[s1_update_bits_cfi_idx_bits] ? _decr_mask_T_16 : 8'h0; // @[OneHot.scala:58:35] assign s1_update_u_mask_0_0 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T | _GEN_8 : decr_mask[0] & _update_was_taken_T | _GEN_8) : _GEN_8; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_1 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_2 | _GEN_17 : decr_mask[0] & _update_was_taken_T_2 | _GEN_17) : _GEN_17; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_2 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_4 | _GEN_26 : decr_mask[0] & _update_was_taken_T_4 | _GEN_26) : _GEN_26; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_3 = _T_144 ? (_GEN_43 ? _GEN_46 & (&s1_update_bits_cfi_idx_bits) | _GEN_35 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits) | _GEN_35) : _GEN_35; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_0_0 = _T_144 & (_GEN_43 ? _GEN_58 : decr_mask[0] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_1 = _T_144 & (_GEN_43 ? _GEN_59 : decr_mask[0] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_2 = _T_144 & (_GEN_43 ? _GEN_60 : decr_mask[0] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_3 = _T_144 & (_GEN_43 ? _GEN_61 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_1_0 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T | _GEN_9 : decr_mask[1] & _update_was_taken_T | _GEN_9) : _GEN_9; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_1 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_2 | _GEN_18 : decr_mask[1] & _update_was_taken_T_2 | _GEN_18) : _GEN_18; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_2 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_4 | _GEN_27 : decr_mask[1] & _update_was_taken_T_4 | _GEN_27) : _GEN_27; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_3 = _T_144 ? (_GEN_43 ? _GEN_48 & (&s1_update_bits_cfi_idx_bits) | _GEN_36 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits) | _GEN_36) : _GEN_36; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_1_0 = _T_144 & (_GEN_43 ? _GEN_62 : decr_mask[1] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_1 = _T_144 & (_GEN_43 ? _GEN_63 : decr_mask[1] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_2 = _T_144 & (_GEN_43 ? _GEN_64 : decr_mask[1] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_3 = _T_144 & (_GEN_43 ? _GEN_65 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_2_0 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T | _GEN_10 : decr_mask[2] & _update_was_taken_T | _GEN_10) : _GEN_10; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_1 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_2 | _GEN_19 : decr_mask[2] & _update_was_taken_T_2 | _GEN_19) : _GEN_19; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_2 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_4 | _GEN_28 : decr_mask[2] & _update_was_taken_T_4 | _GEN_28) : _GEN_28; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_3 = _T_144 ? (_GEN_43 ? _GEN_50 & (&s1_update_bits_cfi_idx_bits) | _GEN_37 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits) | _GEN_37) : _GEN_37; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_2_0 = _T_144 & (_GEN_43 ? _GEN_66 : decr_mask[2] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_1 = _T_144 & (_GEN_43 ? _GEN_67 : decr_mask[2] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_2 = _T_144 & (_GEN_43 ? _GEN_68 : decr_mask[2] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_3 = _T_144 & (_GEN_43 ? _GEN_69 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_3_0 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T | _GEN_11 : decr_mask[3] & _update_was_taken_T | _GEN_11) : _GEN_11; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_1 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_2 | _GEN_20 : decr_mask[3] & _update_was_taken_T_2 | _GEN_20) : _GEN_20; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_2 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_4 | _GEN_29 : decr_mask[3] & _update_was_taken_T_4 | _GEN_29) : _GEN_29; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_3 = _T_144 ? (_GEN_43 ? _GEN_52 & (&s1_update_bits_cfi_idx_bits) | _GEN_38 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits) | _GEN_38) : _GEN_38; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_3_0 = _T_144 & (_GEN_43 ? _GEN_70 : decr_mask[3] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_1 = _T_144 & (_GEN_43 ? _GEN_71 : decr_mask[3] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_2 = _T_144 & (_GEN_43 ? _GEN_72 : decr_mask[3] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_3 = _T_144 & (_GEN_43 ? _GEN_73 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_4_0 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T | _GEN_12 : decr_mask[4] & _update_was_taken_T | _GEN_12) : _GEN_12; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_1 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_2 | _GEN_21 : decr_mask[4] & _update_was_taken_T_2 | _GEN_21) : _GEN_21; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_2 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_4 | _GEN_30 : decr_mask[4] & _update_was_taken_T_4 | _GEN_30) : _GEN_30; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_3 = _T_144 ? (_GEN_43 ? _GEN_54 & (&s1_update_bits_cfi_idx_bits) | _GEN_39 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits) | _GEN_39) : _GEN_39; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_4_0 = _T_144 & (_GEN_43 ? _GEN_74 : decr_mask[4] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_1 = _T_144 & (_GEN_43 ? _GEN_75 : decr_mask[4] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_2 = _T_144 & (_GEN_43 ? _GEN_76 : decr_mask[4] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_3 = _T_144 & (_GEN_43 ? _GEN_77 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_5_0 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T | _GEN_13 : decr_mask[5] & _update_was_taken_T | _GEN_13) : _GEN_13; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_1 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_2 | _GEN_22 : decr_mask[5] & _update_was_taken_T_2 | _GEN_22) : _GEN_22; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_2 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_4 | _GEN_31 : decr_mask[5] & _update_was_taken_T_4 | _GEN_31) : _GEN_31; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_3 = _T_144 ? (_GEN_43 ? _GEN_56 & (&s1_update_bits_cfi_idx_bits) | _GEN_40 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits) | _GEN_40) : _GEN_40; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_5_0 = _T_144 & (_GEN_43 ? _GEN_78 : decr_mask[5] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_1 = _T_144 & (_GEN_43 ? _GEN_79 : decr_mask[5] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_2 = _T_144 & (_GEN_43 ? _GEN_80 : decr_mask[5] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_3 = _T_144 & (_GEN_43 ? _GEN_81 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] reg tt_0_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_0_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_0_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_1_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_1_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_1_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_2_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_2_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_2_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_3_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_3_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_3_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_4_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_4_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_4_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_5_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_5_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_5_1_io_update_hist_REG; // @[tage.scala:354:41] wire [7:0] io_f3_meta_lo = {_io_f3_meta_T_1, _io_f3_meta_T}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi = {_io_f3_meta_T_3, _io_f3_meta_T_2}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_4 = {io_f3_meta_hi, io_f3_meta_lo}; // @[tage.scala:359:25] wire [11:0] _io_f3_meta_T_5 = {io_f3_meta_hi_1, io_f3_meta_lo_1}; // @[tage.scala:359:25] wire [7:0] _io_f3_meta_T_6 = {io_f3_meta_hi_2, io_f3_meta_lo_2}; // @[tage.scala:359:25] wire [3:0] _io_f3_meta_T_7 = {io_f3_meta_hi_3, io_f3_meta_lo_3}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_lo_4 = {_io_f3_meta_T_9, _io_f3_meta_T_8}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi_4 = {_io_f3_meta_T_11, _io_f3_meta_T_10}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_12 = {io_f3_meta_hi_4, io_f3_meta_lo_4}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_lo_5 = {_io_f3_meta_T_5, _io_f3_meta_T_4}; // @[tage.scala:359:25] wire [19:0] io_f3_meta_hi_hi = {_io_f3_meta_T_12, _io_f3_meta_T_7}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_hi_5 = {io_f3_meta_hi_hi, _io_f3_meta_T_6}; // @[tage.scala:359:25] wire [55:0] _io_f3_meta_T_13 = {io_f3_meta_hi_5, io_f3_meta_lo_5}; // @[tage.scala:359:25] assign io_f3_meta_0 = {64'h0, _io_f3_meta_T_13}; // @[tage.scala:198:7, :359:{14,25}] always @(posedge clock) begin // @[tage.scala:198:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[tage.scala:198:7] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[tage.scala:198:7] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[tage.scala:198:7] s1_update_valid <= io_update_valid_0; // @[tage.scala:198:7] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[tage.scala:198:7] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[tage.scala:198:7] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[tage.scala:198:7] s1_update_bits_pc <= io_update_bits_pc_0; // @[tage.scala:198:7] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[tage.scala:198:7] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[tage.scala:198:7] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[tage.scala:198:7] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[tage.scala:198:7] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[tage.scala:198:7] s1_update_bits_target <= io_update_bits_target_0; // @[tage.scala:198:7] s1_update_bits_meta <= io_update_bits_meta_0; // @[tage.scala:198:7] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[tage.scala:198:7] t_io_f1_req_valid_REG <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_1 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_1 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_2 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_2 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_3 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_3 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_4 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_4 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_5 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_5 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] tt_0_1_io_update_mask_0_REG <= s1_update_mask_0_0; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_0_REG <= s1_update_taken_0_0; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_0_REG <= s1_update_alloc_0_0; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_0_0; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_0_REG <= s1_update_u_mask_0_0; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_0_REG <= s1_update_u_0_0; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_1_REG <= s1_update_mask_0_1; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_1_REG <= s1_update_taken_0_1; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_1_REG <= s1_update_alloc_0_1; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_0_1; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_1_REG <= s1_update_u_mask_0_1; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_1_REG <= s1_update_u_0_1; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_2_REG <= s1_update_mask_0_2; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_2_REG <= s1_update_taken_0_2; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_2_REG <= s1_update_alloc_0_2; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_0_2; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_2_REG <= s1_update_u_mask_0_2; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_2_REG <= s1_update_u_0_2; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_3_REG <= s1_update_mask_0_3; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_3_REG <= s1_update_taken_0_3; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_3_REG <= s1_update_alloc_0_3; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_0_3; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_3_REG <= s1_update_u_mask_0_3; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_3_REG <= s1_update_u_0_3; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_0_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_1_1_io_update_mask_0_REG <= s1_update_mask_1_0; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_0_REG <= s1_update_taken_1_0; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_0_REG <= s1_update_alloc_1_0; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_1_0; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_0_REG <= s1_update_u_mask_1_0; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_0_REG <= s1_update_u_1_0; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_1_REG <= s1_update_mask_1_1; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_1_REG <= s1_update_taken_1_1; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_1_REG <= s1_update_alloc_1_1; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_1_1; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_1_REG <= s1_update_u_mask_1_1; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_1_REG <= s1_update_u_1_1; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_2_REG <= s1_update_mask_1_2; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_2_REG <= s1_update_taken_1_2; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_2_REG <= s1_update_alloc_1_2; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_1_2; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_2_REG <= s1_update_u_mask_1_2; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_2_REG <= s1_update_u_1_2; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_3_REG <= s1_update_mask_1_3; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_3_REG <= s1_update_taken_1_3; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_3_REG <= s1_update_alloc_1_3; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_1_3; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_3_REG <= s1_update_u_mask_1_3; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_3_REG <= s1_update_u_1_3; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_1_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_2_1_io_update_mask_0_REG <= s1_update_mask_2_0; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_0_REG <= s1_update_taken_2_0; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_0_REG <= s1_update_alloc_2_0; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_2_0; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_0_REG <= s1_update_u_mask_2_0; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_0_REG <= s1_update_u_2_0; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_1_REG <= s1_update_mask_2_1; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_1_REG <= s1_update_taken_2_1; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_1_REG <= s1_update_alloc_2_1; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_2_1; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_1_REG <= s1_update_u_mask_2_1; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_1_REG <= s1_update_u_2_1; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_2_REG <= s1_update_mask_2_2; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_2_REG <= s1_update_taken_2_2; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_2_REG <= s1_update_alloc_2_2; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_2_2; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_2_REG <= s1_update_u_mask_2_2; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_2_REG <= s1_update_u_2_2; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_3_REG <= s1_update_mask_2_3; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_3_REG <= s1_update_taken_2_3; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_3_REG <= s1_update_alloc_2_3; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_2_3; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_3_REG <= s1_update_u_mask_2_3; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_3_REG <= s1_update_u_2_3; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_2_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_3_1_io_update_mask_0_REG <= s1_update_mask_3_0; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_0_REG <= s1_update_taken_3_0; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_0_REG <= s1_update_alloc_3_0; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_3_0; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_0_REG <= s1_update_u_mask_3_0; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_0_REG <= s1_update_u_3_0; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_1_REG <= s1_update_mask_3_1; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_1_REG <= s1_update_taken_3_1; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_1_REG <= s1_update_alloc_3_1; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_3_1; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_1_REG <= s1_update_u_mask_3_1; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_1_REG <= s1_update_u_3_1; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_2_REG <= s1_update_mask_3_2; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_2_REG <= s1_update_taken_3_2; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_2_REG <= s1_update_alloc_3_2; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_3_2; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_2_REG <= s1_update_u_mask_3_2; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_2_REG <= s1_update_u_3_2; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_3_REG <= s1_update_mask_3_3; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_3_REG <= s1_update_taken_3_3; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_3_REG <= s1_update_alloc_3_3; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_3_3; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_3_REG <= s1_update_u_mask_3_3; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_3_REG <= s1_update_u_3_3; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_3_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_4_1_io_update_mask_0_REG <= s1_update_mask_4_0; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_0_REG <= s1_update_taken_4_0; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_0_REG <= s1_update_alloc_4_0; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_4_0; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_0_REG <= s1_update_u_mask_4_0; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_0_REG <= s1_update_u_4_0; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_1_REG <= s1_update_mask_4_1; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_1_REG <= s1_update_taken_4_1; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_1_REG <= s1_update_alloc_4_1; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_4_1; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_1_REG <= s1_update_u_mask_4_1; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_1_REG <= s1_update_u_4_1; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_2_REG <= s1_update_mask_4_2; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_2_REG <= s1_update_taken_4_2; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_2_REG <= s1_update_alloc_4_2; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_4_2; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_2_REG <= s1_update_u_mask_4_2; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_2_REG <= s1_update_u_4_2; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_3_REG <= s1_update_mask_4_3; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_3_REG <= s1_update_taken_4_3; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_3_REG <= s1_update_alloc_4_3; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_4_3; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_3_REG <= s1_update_u_mask_4_3; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_3_REG <= s1_update_u_4_3; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_4_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_5_1_io_update_mask_0_REG <= s1_update_mask_5_0; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_0_REG <= s1_update_taken_5_0; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_0_REG <= s1_update_alloc_5_0; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_5_0; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_0_REG <= s1_update_u_mask_5_0; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_0_REG <= s1_update_u_5_0; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_1_REG <= s1_update_mask_5_1; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_1_REG <= s1_update_taken_5_1; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_1_REG <= s1_update_alloc_5_1; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_5_1; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_1_REG <= s1_update_u_mask_5_1; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_1_REG <= s1_update_u_5_1; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_2_REG <= s1_update_mask_5_2; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_2_REG <= s1_update_taken_5_2; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_2_REG <= s1_update_alloc_5_2; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_5_2; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_2_REG <= s1_update_u_mask_5_2; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_2_REG <= s1_update_u_5_2; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_3_REG <= s1_update_mask_5_3; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_3_REG <= s1_update_taken_5_3; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_3_REG <= s1_update_alloc_5_3; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_5_3; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_3_REG <= s1_update_u_mask_5_3; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_3_REG <= s1_update_u_5_3; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_5_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] always @(posedge) TageTable_6 tt_0_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_0_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_0_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_0_0_bits_u), .io_f3_resp_1_valid (f3_resps_0_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_0_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_0_1_bits_u), .io_f3_resp_2_valid (f3_resps_0_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_0_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_0_2_bits_u), .io_f3_resp_3_valid (f3_resps_0_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_0_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_0_3_bits_u), .io_update_mask_0 (tt_0_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_0_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_0_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_0_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_0_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_0_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_0_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_0_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_0_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_0_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_0_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_0_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_0_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_0_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_0_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_0_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_0_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_0_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_0_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_0_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_0_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_0_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_0_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_0_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_0_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_0_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_7 tt_1_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_1), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_1), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_1_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_1_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_1_0_bits_u), .io_f3_resp_1_valid (f3_resps_1_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_1_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_1_1_bits_u), .io_f3_resp_2_valid (f3_resps_1_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_1_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_1_2_bits_u), .io_f3_resp_3_valid (f3_resps_1_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_1_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_1_3_bits_u), .io_update_mask_0 (tt_1_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_1_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_1_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_1_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_1_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_1_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_1_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_1_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_1_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_1_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_1_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_1_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_1_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_1_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_1_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_1_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_1_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_1_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_1_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_1_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_1_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_1_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_1_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_1_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_1_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_1_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_8 tt_2_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_2), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_2), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_2_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_2_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_2_0_bits_u), .io_f3_resp_1_valid (f3_resps_2_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_2_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_2_1_bits_u), .io_f3_resp_2_valid (f3_resps_2_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_2_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_2_2_bits_u), .io_f3_resp_3_valid (f3_resps_2_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_2_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_2_3_bits_u), .io_update_mask_0 (tt_2_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_2_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_2_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_2_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_2_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_2_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_2_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_2_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_2_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_2_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_2_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_2_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_2_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_2_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_2_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_2_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_2_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_2_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_2_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_2_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_2_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_2_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_2_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_2_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_2_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_2_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_9 tt_3_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_3), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_3), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_3_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_3_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_3_0_bits_u), .io_f3_resp_1_valid (f3_resps_3_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_3_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_3_1_bits_u), .io_f3_resp_2_valid (f3_resps_3_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_3_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_3_2_bits_u), .io_f3_resp_3_valid (f3_resps_3_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_3_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_3_3_bits_u), .io_update_mask_0 (tt_3_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_3_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_3_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_3_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_3_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_3_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_3_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_3_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_3_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_3_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_3_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_3_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_3_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_3_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_3_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_3_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_3_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_3_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_3_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_3_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_3_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_3_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_3_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_3_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_3_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_3_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_10 tt_4_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_4), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_4), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_4_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_4_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_4_0_bits_u), .io_f3_resp_1_valid (f3_resps_4_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_4_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_4_1_bits_u), .io_f3_resp_2_valid (f3_resps_4_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_4_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_4_2_bits_u), .io_f3_resp_3_valid (f3_resps_4_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_4_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_4_3_bits_u), .io_update_mask_0 (tt_4_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_4_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_4_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_4_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_4_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_4_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_4_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_4_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_4_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_4_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_4_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_4_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_4_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_4_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_4_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_4_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_4_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_4_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_4_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_4_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_4_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_4_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_4_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_4_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_4_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_4_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_11 tt_5_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_5), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_5), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_5_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_5_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_5_0_bits_u), .io_f3_resp_1_valid (f3_resps_5_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_5_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_5_1_bits_u), .io_f3_resp_2_valid (f3_resps_5_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_5_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_5_2_bits_u), .io_f3_resp_3_valid (f3_resps_5_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_5_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_5_3_bits_u), .io_update_mask_0 (tt_5_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_5_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_5_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_5_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_5_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_5_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_5_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_5_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_5_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_5_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_5_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_5_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_5_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_5_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_5_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_5_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_5_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_5_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_5_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_5_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_5_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_5_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_5_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_5_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_5_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_5_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] MaxPeriodFibonacciLFSR_9 alloc_lfsr_prng ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_io_out_0), .io_out_1 (_alloc_lfsr_prng_io_out_1), .io_out_2 (_alloc_lfsr_prng_io_out_2), .io_out_3 (_alloc_lfsr_prng_io_out_3), .io_out_4 (_alloc_lfsr_prng_io_out_4), .io_out_5 (_alloc_lfsr_prng_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_10 alloc_lfsr_prng_1 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_1_io_out_0), .io_out_1 (_alloc_lfsr_prng_1_io_out_1), .io_out_2 (_alloc_lfsr_prng_1_io_out_2), .io_out_3 (_alloc_lfsr_prng_1_io_out_3), .io_out_4 (_alloc_lfsr_prng_1_io_out_4), .io_out_5 (_alloc_lfsr_prng_1_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_11 alloc_lfsr_prng_2 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_2_io_out_0), .io_out_1 (_alloc_lfsr_prng_2_io_out_1), .io_out_2 (_alloc_lfsr_prng_2_io_out_2), .io_out_3 (_alloc_lfsr_prng_2_io_out_3), .io_out_4 (_alloc_lfsr_prng_2_io_out_4), .io_out_5 (_alloc_lfsr_prng_2_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_12 alloc_lfsr_prng_3 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_3_io_out_0), .io_out_1 (_alloc_lfsr_prng_3_io_out_1), .io_out_2 (_alloc_lfsr_prng_3_io_out_2), .io_out_3 (_alloc_lfsr_prng_3_io_out_3), .io_out_4 (_alloc_lfsr_prng_3_io_out_4), .io_out_5 (_alloc_lfsr_prng_3_io_out_5) ); // @[PRNG.scala:91:22] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_f3_meta = io_f3_meta_0; // @[tage.scala:198:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_26 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_26( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_12 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_12( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_104 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_104( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_128 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_128( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_5 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_5( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 connect _source_ok_WIRE[10], _source_ok_T_45 node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _T_127 = and(_T_11, _T_24) node _T_128 = and(_T_127, _T_37) node _T_129 = and(_T_128, _T_50) node _T_130 = and(_T_129, _T_63) node _T_131 = and(_T_130, _T_76) node _T_132 = and(_T_131, _T_89) node _T_133 = and(_T_132, _T_102) node _T_134 = and(_T_133, _T_110) node _T_135 = and(_T_134, _T_118) node _T_136 = and(_T_135, _T_126) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_136, UInt<1>(0h1), "") : assert_1 node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_140 : node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_7) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<1>(0h1)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_8) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h2)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_9) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<2>(0h3)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_10) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_169 = shr(io.in.a.bits.source, 3) node _T_170 = eq(_T_169, UInt<2>(0h3)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_11) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_175 = shr(io.in.a.bits.source, 3) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_12) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_181 = shr(io.in.a.bits.source, 3) node _T_182 = eq(_T_181, UInt<4>(0h8)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_190 = or(_T_144, _T_150) node _T_191 = or(_T_190, _T_156) node _T_192 = or(_T_191, _T_162) node _T_193 = or(_T_192, _T_168) node _T_194 = or(_T_193, _T_174) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_186) node _T_197 = or(_T_196, _T_187) node _T_198 = or(_T_197, _T_188) node _T_199 = or(_T_198, _T_189) node _T_200 = and(_T_143, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = and(_T_202, _T_207) node _T_209 = or(UInt<1>(0h0), _T_208) node _T_210 = and(_T_201, _T_209) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_210, UInt<1>(0h1), "") : assert_2 node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_14) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<1>(0h1)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_15) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_227 = shr(io.in.a.bits.source, 2) node _T_228 = eq(_T_227, UInt<2>(0h2)) node _T_229 = leq(UInt<1>(0h0), uncommonBits_16) node _T_230 = and(_T_228, _T_229) node _T_231 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<2>(0h3)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_239 = shr(io.in.a.bits.source, 3) node _T_240 = eq(_T_239, UInt<2>(0h3)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_18) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_245 = shr(io.in.a.bits.source, 3) node _T_246 = eq(_T_245, UInt<2>(0h2)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_19) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_251 = shr(io.in.a.bits.source, 3) node _T_252 = eq(_T_251, UInt<4>(0h8)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_20) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_256 = and(_T_254, _T_255) node _T_257 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_258 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_259 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_214 connect _WIRE[1], _T_220 connect _WIRE[2], _T_226 connect _WIRE[3], _T_232 connect _WIRE[4], _T_238 connect _WIRE[5], _T_244 connect _WIRE[6], _T_250 connect _WIRE[7], _T_256 connect _WIRE[8], _T_257 connect _WIRE[9], _T_258 connect _WIRE[10], _T_259 node _T_260 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_261 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_262 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_265 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_266 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_267 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = mux(_WIRE[7], _T_260, UInt<1>(0h0)) node _T_269 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = or(_T_261, _T_262) node _T_273 = or(_T_272, _T_263) node _T_274 = or(_T_273, _T_264) node _T_275 = or(_T_274, _T_265) node _T_276 = or(_T_275, _T_266) node _T_277 = or(_T_276, _T_267) node _T_278 = or(_T_277, _T_268) node _T_279 = or(_T_278, _T_269) node _T_280 = or(_T_279, _T_270) node _T_281 = or(_T_280, _T_271) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_281 node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_284 = and(_T_282, _T_283) node _T_285 = or(UInt<1>(0h0), _T_284) node _T_286 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_WIRE_1, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_293, UInt<1>(0h1), "") : assert_3 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(source_ok, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_300 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_301 = asUInt(reset) node _T_302 = eq(_T_301, UInt<1>(0h0)) when _T_302 : node _T_303 = eq(_T_300, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_300, UInt<1>(0h1), "") : assert_5 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(is_aligned, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_307 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_307, UInt<1>(0h1), "") : assert_7 node _T_311 = not(io.in.a.bits.mask) node _T_312 = eq(_T_311, UInt<1>(0h0)) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_312, UInt<1>(0h1), "") : assert_8 node _T_316 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_316, UInt<1>(0h1), "") : assert_9 node _T_320 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_320 : node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_323 = and(_T_321, _T_322) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_21) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<1>(0h1)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_22) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<2>(0h2)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_23) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<2>(0h3)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_24) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_349 = shr(io.in.a.bits.source, 3) node _T_350 = eq(_T_349, UInt<2>(0h3)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_25) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_355 = shr(io.in.a.bits.source, 3) node _T_356 = eq(_T_355, UInt<2>(0h2)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_26) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_361 = shr(io.in.a.bits.source, 3) node _T_362 = eq(_T_361, UInt<4>(0h8)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_27) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_368 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_369 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_370 = or(_T_324, _T_330) node _T_371 = or(_T_370, _T_336) node _T_372 = or(_T_371, _T_342) node _T_373 = or(_T_372, _T_348) node _T_374 = or(_T_373, _T_354) node _T_375 = or(_T_374, _T_360) node _T_376 = or(_T_375, _T_366) node _T_377 = or(_T_376, _T_367) node _T_378 = or(_T_377, _T_368) node _T_379 = or(_T_378, _T_369) node _T_380 = and(_T_323, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<13>(0h1000))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = and(_T_382, _T_387) node _T_389 = or(UInt<1>(0h0), _T_388) node _T_390 = and(_T_381, _T_389) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_390, UInt<1>(0h1), "") : assert_10 node _T_394 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_395 = shr(io.in.a.bits.source, 2) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = leq(UInt<1>(0h0), uncommonBits_28) node _T_398 = and(_T_396, _T_397) node _T_399 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_400 = and(_T_398, _T_399) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_401 = shr(io.in.a.bits.source, 2) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_29) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<2>(0h2)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_30) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<2>(0h3)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_31) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_419 = shr(io.in.a.bits.source, 3) node _T_420 = eq(_T_419, UInt<2>(0h3)) node _T_421 = leq(UInt<1>(0h0), uncommonBits_32) node _T_422 = and(_T_420, _T_421) node _T_423 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_424 = and(_T_422, _T_423) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_425 = shr(io.in.a.bits.source, 3) node _T_426 = eq(_T_425, UInt<2>(0h2)) node _T_427 = leq(UInt<1>(0h0), uncommonBits_33) node _T_428 = and(_T_426, _T_427) node _T_429 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_430 = and(_T_428, _T_429) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_431 = shr(io.in.a.bits.source, 3) node _T_432 = eq(_T_431, UInt<4>(0h8)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_34) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_436 = and(_T_434, _T_435) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_439 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_394 connect _WIRE_2[1], _T_400 connect _WIRE_2[2], _T_406 connect _WIRE_2[3], _T_412 connect _WIRE_2[4], _T_418 connect _WIRE_2[5], _T_424 connect _WIRE_2[6], _T_430 connect _WIRE_2[7], _T_436 connect _WIRE_2[8], _T_437 connect _WIRE_2[9], _T_438 connect _WIRE_2[10], _T_439 node _T_440 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_441 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_442 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_443 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_444 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_445 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_446 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_447 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = mux(_WIRE_2[7], _T_440, UInt<1>(0h0)) node _T_449 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_450 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = or(_T_441, _T_442) node _T_453 = or(_T_452, _T_443) node _T_454 = or(_T_453, _T_444) node _T_455 = or(_T_454, _T_445) node _T_456 = or(_T_455, _T_446) node _T_457 = or(_T_456, _T_447) node _T_458 = or(_T_457, _T_448) node _T_459 = or(_T_458, _T_449) node _T_460 = or(_T_459, _T_450) node _T_461 = or(_T_460, _T_451) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_461 node _T_462 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_463 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_464 = and(_T_462, _T_463) node _T_465 = or(UInt<1>(0h0), _T_464) node _T_466 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<13>(0h1000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = and(_T_465, _T_470) node _T_472 = or(UInt<1>(0h0), _T_471) node _T_473 = and(_WIRE_3, _T_472) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_473, UInt<1>(0h1), "") : assert_11 node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(source_ok, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_480 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_480, UInt<1>(0h1), "") : assert_13 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_487 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_487, UInt<1>(0h1), "") : assert_15 node _T_491 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_491, UInt<1>(0h1), "") : assert_16 node _T_495 = not(io.in.a.bits.mask) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_496, UInt<1>(0h1), "") : assert_17 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_500, UInt<1>(0h1), "") : assert_18 node _T_504 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_509 = shr(io.in.a.bits.source, 2) node _T_510 = eq(_T_509, UInt<1>(0h0)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_35) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h1)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_36) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<2>(0h2)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_37) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h3)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_38) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_533 = shr(io.in.a.bits.source, 3) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_39) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<2>(0h2)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_40) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_545 = shr(io.in.a.bits.source, 3) node _T_546 = eq(_T_545, UInt<4>(0h8)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_41) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_550 = and(_T_548, _T_549) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_553 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_554 = or(_T_508, _T_514) node _T_555 = or(_T_554, _T_520) node _T_556 = or(_T_555, _T_526) node _T_557 = or(_T_556, _T_532) node _T_558 = or(_T_557, _T_538) node _T_559 = or(_T_558, _T_544) node _T_560 = or(_T_559, _T_550) node _T_561 = or(_T_560, _T_551) node _T_562 = or(_T_561, _T_552) node _T_563 = or(_T_562, _T_553) node _T_564 = and(_T_507, _T_563) node _T_565 = or(UInt<1>(0h0), _T_564) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_565, UInt<1>(0h1), "") : assert_19 node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = and(_T_572, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_579, UInt<1>(0h1), "") : assert_20 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(is_aligned, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_589 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_589, UInt<1>(0h1), "") : assert_23 node _T_593 = eq(io.in.a.bits.mask, mask) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_593, UInt<1>(0h1), "") : assert_24 node _T_597 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_597, UInt<1>(0h1), "") : assert_25 node _T_601 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_601 : node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_604 = and(_T_602, _T_603) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_606 = shr(io.in.a.bits.source, 2) node _T_607 = eq(_T_606, UInt<1>(0h0)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_42) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_612 = shr(io.in.a.bits.source, 2) node _T_613 = eq(_T_612, UInt<1>(0h1)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_43) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_618 = shr(io.in.a.bits.source, 2) node _T_619 = eq(_T_618, UInt<2>(0h2)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_44) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_624 = shr(io.in.a.bits.source, 2) node _T_625 = eq(_T_624, UInt<2>(0h3)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_45) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_630 = shr(io.in.a.bits.source, 3) node _T_631 = eq(_T_630, UInt<2>(0h3)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_46) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_636 = shr(io.in.a.bits.source, 3) node _T_637 = eq(_T_636, UInt<2>(0h2)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_47) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_641 = and(_T_639, _T_640) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_642 = shr(io.in.a.bits.source, 3) node _T_643 = eq(_T_642, UInt<4>(0h8)) node _T_644 = leq(UInt<1>(0h0), uncommonBits_48) node _T_645 = and(_T_643, _T_644) node _T_646 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_647 = and(_T_645, _T_646) node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_650 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_651 = or(_T_605, _T_611) node _T_652 = or(_T_651, _T_617) node _T_653 = or(_T_652, _T_623) node _T_654 = or(_T_653, _T_629) node _T_655 = or(_T_654, _T_635) node _T_656 = or(_T_655, _T_641) node _T_657 = or(_T_656, _T_647) node _T_658 = or(_T_657, _T_648) node _T_659 = or(_T_658, _T_649) node _T_660 = or(_T_659, _T_650) node _T_661 = and(_T_604, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_664 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<13>(0h1000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = and(_T_662, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_674, UInt<1>(0h1), "") : assert_26 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(source_ok, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_684, UInt<1>(0h1), "") : assert_29 node _T_688 = eq(io.in.a.bits.mask, mask) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_688, UInt<1>(0h1), "") : assert_30 node _T_692 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_49) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_50) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_51) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_52) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_721 = shr(io.in.a.bits.source, 3) node _T_722 = eq(_T_721, UInt<2>(0h3)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_53) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_727 = shr(io.in.a.bits.source, 3) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_54) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_733 = shr(io.in.a.bits.source, 3) node _T_734 = eq(_T_733, UInt<4>(0h8)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_55) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_740 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_741 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_742 = or(_T_696, _T_702) node _T_743 = or(_T_742, _T_708) node _T_744 = or(_T_743, _T_714) node _T_745 = or(_T_744, _T_720) node _T_746 = or(_T_745, _T_726) node _T_747 = or(_T_746, _T_732) node _T_748 = or(_T_747, _T_738) node _T_749 = or(_T_748, _T_739) node _T_750 = or(_T_749, _T_740) node _T_751 = or(_T_750, _T_741) node _T_752 = and(_T_695, _T_751) node _T_753 = or(UInt<1>(0h0), _T_752) node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_756 = and(_T_754, _T_755) node _T_757 = or(UInt<1>(0h0), _T_756) node _T_758 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = and(_T_757, _T_762) node _T_764 = or(UInt<1>(0h0), _T_763) node _T_765 = and(_T_753, _T_764) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_765, UInt<1>(0h1), "") : assert_31 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(source_ok, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_775 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_775, UInt<1>(0h1), "") : assert_34 node _T_779 = not(mask) node _T_780 = and(io.in.a.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_781, UInt<1>(0h1), "") : assert_35 node _T_785 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<1>(0h0)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_56) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_796 = shr(io.in.a.bits.source, 2) node _T_797 = eq(_T_796, UInt<1>(0h1)) node _T_798 = leq(UInt<1>(0h0), uncommonBits_57) node _T_799 = and(_T_797, _T_798) node _T_800 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<2>(0h2)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_58) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<2>(0h3)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_59) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_814 = shr(io.in.a.bits.source, 3) node _T_815 = eq(_T_814, UInt<2>(0h3)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_60) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_820 = shr(io.in.a.bits.source, 3) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_61) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_826 = shr(io.in.a.bits.source, 3) node _T_827 = eq(_T_826, UInt<4>(0h8)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_62) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_833 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_834 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_835 = or(_T_789, _T_795) node _T_836 = or(_T_835, _T_801) node _T_837 = or(_T_836, _T_807) node _T_838 = or(_T_837, _T_813) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_825) node _T_841 = or(_T_840, _T_831) node _T_842 = or(_T_841, _T_832) node _T_843 = or(_T_842, _T_833) node _T_844 = or(_T_843, _T_834) node _T_845 = and(_T_788, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_848 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = and(_T_847, _T_852) node _T_854 = or(UInt<1>(0h0), _T_853) node _T_855 = and(_T_846, _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_855, UInt<1>(0h1), "") : assert_36 node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(source_ok, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(is_aligned, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_865 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_865, UInt<1>(0h1), "") : assert_39 node _T_869 = eq(io.in.a.bits.mask, mask) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_869, UInt<1>(0h1), "") : assert_40 node _T_873 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_873 : node _T_874 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_875 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_876 = and(_T_874, _T_875) node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<1>(0h0)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_63) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_884 = shr(io.in.a.bits.source, 2) node _T_885 = eq(_T_884, UInt<1>(0h1)) node _T_886 = leq(UInt<1>(0h0), uncommonBits_64) node _T_887 = and(_T_885, _T_886) node _T_888 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_889 = and(_T_887, _T_888) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_890 = shr(io.in.a.bits.source, 2) node _T_891 = eq(_T_890, UInt<2>(0h2)) node _T_892 = leq(UInt<1>(0h0), uncommonBits_65) node _T_893 = and(_T_891, _T_892) node _T_894 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_895 = and(_T_893, _T_894) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_896 = shr(io.in.a.bits.source, 2) node _T_897 = eq(_T_896, UInt<2>(0h3)) node _T_898 = leq(UInt<1>(0h0), uncommonBits_66) node _T_899 = and(_T_897, _T_898) node _T_900 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_901 = and(_T_899, _T_900) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_902 = shr(io.in.a.bits.source, 3) node _T_903 = eq(_T_902, UInt<2>(0h3)) node _T_904 = leq(UInt<1>(0h0), uncommonBits_67) node _T_905 = and(_T_903, _T_904) node _T_906 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_907 = and(_T_905, _T_906) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_908 = shr(io.in.a.bits.source, 3) node _T_909 = eq(_T_908, UInt<2>(0h2)) node _T_910 = leq(UInt<1>(0h0), uncommonBits_68) node _T_911 = and(_T_909, _T_910) node _T_912 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_913 = and(_T_911, _T_912) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_914 = shr(io.in.a.bits.source, 3) node _T_915 = eq(_T_914, UInt<4>(0h8)) node _T_916 = leq(UInt<1>(0h0), uncommonBits_69) node _T_917 = and(_T_915, _T_916) node _T_918 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_919 = and(_T_917, _T_918) node _T_920 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_921 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_922 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_923 = or(_T_877, _T_883) node _T_924 = or(_T_923, _T_889) node _T_925 = or(_T_924, _T_895) node _T_926 = or(_T_925, _T_901) node _T_927 = or(_T_926, _T_907) node _T_928 = or(_T_927, _T_913) node _T_929 = or(_T_928, _T_919) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_921) node _T_932 = or(_T_931, _T_922) node _T_933 = and(_T_876, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_936 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<13>(0h1000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = and(_T_935, _T_940) node _T_942 = or(UInt<1>(0h0), _T_941) node _T_943 = and(_T_934, _T_942) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_943, UInt<1>(0h1), "") : assert_41 node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(source_ok, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(is_aligned, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_953 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_953, UInt<1>(0h1), "") : assert_44 node _T_957 = eq(io.in.a.bits.mask, mask) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_957, UInt<1>(0h1), "") : assert_45 node _T_961 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_961 : node _T_962 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_963 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_964 = and(_T_962, _T_963) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_966 = shr(io.in.a.bits.source, 2) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_70) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_971 = and(_T_969, _T_970) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_972 = shr(io.in.a.bits.source, 2) node _T_973 = eq(_T_972, UInt<1>(0h1)) node _T_974 = leq(UInt<1>(0h0), uncommonBits_71) node _T_975 = and(_T_973, _T_974) node _T_976 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_977 = and(_T_975, _T_976) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<2>(0h2)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_72) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<2>(0h3)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_73) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_990 = shr(io.in.a.bits.source, 3) node _T_991 = eq(_T_990, UInt<2>(0h3)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_74) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_996 = shr(io.in.a.bits.source, 3) node _T_997 = eq(_T_996, UInt<2>(0h2)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_75) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1002 = shr(io.in.a.bits.source, 3) node _T_1003 = eq(_T_1002, UInt<4>(0h8)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1009 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1010 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1011 = or(_T_965, _T_971) node _T_1012 = or(_T_1011, _T_977) node _T_1013 = or(_T_1012, _T_983) node _T_1014 = or(_T_1013, _T_989) node _T_1015 = or(_T_1014, _T_995) node _T_1016 = or(_T_1015, _T_1001) node _T_1017 = or(_T_1016, _T_1007) node _T_1018 = or(_T_1017, _T_1008) node _T_1019 = or(_T_1018, _T_1009) node _T_1020 = or(_T_1019, _T_1010) node _T_1021 = and(_T_964, _T_1020) node _T_1022 = or(UInt<1>(0h0), _T_1021) node _T_1023 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1024 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<13>(0h1000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = and(_T_1023, _T_1028) node _T_1030 = or(UInt<1>(0h0), _T_1029) node _T_1031 = and(_T_1022, _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_46 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(source_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(is_aligned, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1041 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_49 node _T_1045 = eq(io.in.a.bits.mask, mask) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_50 node _T_1049 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1053 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_52 node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 2) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_92 = shr(io.in.d.bits.source, 3) node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8)) node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_55 connect _source_ok_WIRE_1[1], _source_ok_T_61 connect _source_ok_WIRE_1[2], _source_ok_T_67 connect _source_ok_WIRE_1[3], _source_ok_T_73 connect _source_ok_WIRE_1[4], _source_ok_T_79 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_91 connect _source_ok_WIRE_1[7], _source_ok_T_97 connect _source_ok_WIRE_1[8], _source_ok_T_98 connect _source_ok_WIRE_1[9], _source_ok_T_99 connect _source_ok_WIRE_1[10], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1061 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_54 node _T_1065 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_55 node _T_1069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_56 node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_57 node _T_1077 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1077 : node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(source_ok_1, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(sink_ok, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1084 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_60 node _T_1088 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_61 node _T_1092 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_62 node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_63 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(UInt<1>(0h0), _T_1100) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_64 node _T_1105 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(source_ok_1, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(sink_ok, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1112 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_67 node _T_1116 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_68 node _T_1120 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_69 node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1125 = or(_T_1124, io.in.d.bits.corrupt) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_70 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = or(UInt<1>(0h0), _T_1129) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_71 node _T_1134 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1134 : node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(source_ok_1, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1138 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_73 node _T_1142 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_74 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h0), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_75 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_77 node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1160 = or(_T_1159, io.in.d.bits.corrupt) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_78 node _T_1164 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1165 = or(UInt<1>(0h0), _T_1164) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_79 node _T_1169 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1169 : node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(source_ok_1, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_81 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_82 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h0), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1186 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1190 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1194 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1198 = eq(a_first, UInt<1>(0h0)) node _T_1199 = and(io.in.a.valid, _T_1198) when _T_1199 : node _T_1200 = eq(io.in.a.bits.opcode, opcode) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_87 node _T_1204 = eq(io.in.a.bits.param, param) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_88 node _T_1208 = eq(io.in.a.bits.size, size) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_89 node _T_1212 = eq(io.in.a.bits.source, source) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_90 node _T_1216 = eq(io.in.a.bits.address, address) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_91 node _T_1220 = and(io.in.a.ready, io.in.a.valid) node _T_1221 = and(_T_1220, a_first) when _T_1221 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1222 = eq(d_first, UInt<1>(0h0)) node _T_1223 = and(io.in.d.valid, _T_1222) when _T_1223 : node _T_1224 = eq(io.in.d.bits.opcode, opcode_1) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.d.bits.param, param_1) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_93 node _T_1232 = eq(io.in.d.bits.size, size_1) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_94 node _T_1236 = eq(io.in.d.bits.source, source_1) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_95 node _T_1240 = eq(io.in.d.bits.sink, sink) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_96 node _T_1244 = eq(io.in.d.bits.denied, denied) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_97 node _T_1248 = and(io.in.d.ready, io.in.d.valid) node _T_1249 = and(_T_1248, d_first) when _T_1249 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1250 = and(io.in.a.valid, a_first_1) node _T_1251 = and(_T_1250, UInt<1>(0h1)) when _T_1251 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1252 = and(io.in.a.ready, io.in.a.valid) node _T_1253 = and(_T_1252, a_first_1) node _T_1254 = and(_T_1253, UInt<1>(0h1)) when _T_1254 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1255 = dshr(inflight, io.in.a.bits.source) node _T_1256 = bits(_T_1255, 0, 0) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(_T_1257, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1257, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1261 = and(io.in.d.valid, d_first_1) node _T_1262 = and(_T_1261, UInt<1>(0h1)) node _T_1263 = eq(d_release_ack, UInt<1>(0h0)) node _T_1264 = and(_T_1262, _T_1263) when _T_1264 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1265 = and(io.in.d.ready, io.in.d.valid) node _T_1266 = and(_T_1265, d_first_1) node _T_1267 = and(_T_1266, UInt<1>(0h1)) node _T_1268 = eq(d_release_ack, UInt<1>(0h0)) node _T_1269 = and(_T_1267, _T_1268) when _T_1269 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1270 = and(io.in.d.valid, d_first_1) node _T_1271 = and(_T_1270, UInt<1>(0h1)) node _T_1272 = eq(d_release_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1274 = dshr(inflight, io.in.d.bits.source) node _T_1275 = bits(_T_1274, 0, 0) node _T_1276 = or(_T_1275, same_cycle_resp) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1280 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1281 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1282 = or(_T_1280, _T_1281) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_100 node _T_1286 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_101 else : node _T_1290 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1291 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1292 = or(_T_1290, _T_1291) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_102 node _T_1296 = eq(io.in.d.bits.size, a_size_lookup) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_103 node _T_1300 = and(io.in.d.valid, d_first_1) node _T_1301 = and(_T_1300, a_first_1) node _T_1302 = and(_T_1301, io.in.a.valid) node _T_1303 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1304 = and(_T_1302, _T_1303) node _T_1305 = eq(d_release_ack, UInt<1>(0h0)) node _T_1306 = and(_T_1304, _T_1305) when _T_1306 : node _T_1307 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1308 = or(_T_1307, io.in.a.ready) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_1312 = orr(inflight) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) node _T_1314 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1315 = or(_T_1313, _T_1314) node _T_1316 = lt(watchdog, plusarg_reader.out) node _T_1317 = or(_T_1315, _T_1316) node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(_T_1317, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1317, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1321 = and(io.in.a.ready, io.in.a.valid) node _T_1322 = and(io.in.d.ready, io.in.d.valid) node _T_1323 = or(_T_1321, _T_1322) when _T_1323 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1324 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1325 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1326 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = and(_T_1324, _T_1327) when _T_1328 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1329 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1330 = and(_T_1329, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1331 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1332 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = and(_T_1330, _T_1333) when _T_1334 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1335 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1336 = bits(_T_1335, 0, 0) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1341 = and(io.in.d.valid, d_first_2) node _T_1342 = and(_T_1341, UInt<1>(0h1)) node _T_1343 = and(_T_1342, d_release_ack_1) when _T_1343 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1344 = and(io.in.d.ready, io.in.d.valid) node _T_1345 = and(_T_1344, d_first_2) node _T_1346 = and(_T_1345, UInt<1>(0h1)) node _T_1347 = and(_T_1346, d_release_ack_1) when _T_1347 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1348 = and(io.in.d.valid, d_first_2) node _T_1349 = and(_T_1348, UInt<1>(0h1)) node _T_1350 = and(_T_1349, d_release_ack_1) when _T_1350 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1351 = dshr(inflight_1, io.in.d.bits.source) node _T_1352 = bits(_T_1351, 0, 0) node _T_1353 = or(_T_1352, same_cycle_resp_1) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1357 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_108 else : node _T_1361 = eq(io.in.d.bits.size, c_size_lookup) node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(_T_1361, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1361, UInt<1>(0h1), "") : assert_109 node _T_1365 = and(io.in.d.valid, d_first_2) node _T_1366 = and(_T_1365, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1367 = and(_T_1366, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1368 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1369 = and(_T_1367, _T_1368) node _T_1370 = and(_T_1369, d_release_ack_1) node _T_1371 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1372 = and(_T_1370, _T_1371) when _T_1372 : node _T_1373 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1374 = or(_T_1373, _WIRE_27.ready) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_1378 = orr(inflight_1) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) node _T_1380 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1381 = or(_T_1379, _T_1380) node _T_1382 = lt(watchdog_1, plusarg_reader_1.out) node _T_1383 = or(_T_1381, _T_1382) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1387 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1388 = and(io.in.d.ready, io.in.d.valid) node _T_1389 = or(_T_1387, _T_1388) when _T_1389 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1321 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1321; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1321; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1389 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1389; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1389; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1389; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1254 = _T_1321 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1254 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1254 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1254 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1254 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1254 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1300 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1300 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1269 = _T_1389 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1269 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1269 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1269 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1365 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1365 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1347 = _T_1389 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1347 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1347 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1347 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module SodorInternalTile : input clock : Clock input reset : Reset output io : { flip debug_port : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, master_port : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}[1], flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} inst core of Core connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector invalidate core.io.hartid invalidate core.io.interrupt.meip invalidate core.io.interrupt.msip invalidate core.io.interrupt.mtip invalidate core.io.interrupt.debug invalidate core.io.mem.resp.bits.data invalidate core.io.mem.resp.valid invalidate core.io.mem.req.bits.typ invalidate core.io.mem.req.bits.fcn invalidate core.io.mem.req.bits.data invalidate core.io.mem.req.bits.addr invalidate core.io.mem.req.valid invalidate core.io.mem.req.ready invalidate core.io.dcpath.halt invalidate core.io.ddpath.resetpc invalidate core.io.ddpath.rdata invalidate core.io.ddpath.validreq invalidate core.io.ddpath.wdata invalidate core.io.ddpath.addr inst memory of AsyncScratchPadMemory connect memory.clock, clock connect memory.reset, reset inst router of SodorRequestRouter connect router.clock, clock connect router.reset, reset connect router.io.corePort, core.io.mem connect memory.io.core_ports[0], router.io.scratchPort connect router.io.masterPort.resp, io.master_port[0].resp connect io.master_port[0].req.bits, router.io.masterPort.req.bits connect io.master_port[0].req.valid, router.io.masterPort.req.valid connect router.io.masterPort.req.ready, io.master_port[0].req.ready connect router.io.respAddress, core.io.mem.req.bits.addr connect memory.io.debug_port, io.debug_port connect core.io.interrupt, io.interrupt connect core.io.hartid, io.hartid connect core.io.reset_vector, io.reset_vector

module SodorInternalTile( // @[sodor_internal_tile.scala:117:7] input clock, // @[sodor_internal_tile.scala:117:7] input reset, // @[sodor_internal_tile.scala:117:7] input io_debug_port_req_valid, // @[sodor_internal_tile.scala:34:14] input [31:0] io_debug_port_req_bits_addr, // @[sodor_internal_tile.scala:34:14] input [31:0] io_debug_port_req_bits_data, // @[sodor_internal_tile.scala:34:14] input io_debug_port_req_bits_fcn, // @[sodor_internal_tile.scala:34:14] input [2:0] io_debug_port_req_bits_typ, // @[sodor_internal_tile.scala:34:14] output io_debug_port_resp_valid, // @[sodor_internal_tile.scala:34:14] output [31:0] io_debug_port_resp_bits_data, // @[sodor_internal_tile.scala:34:14] input io_master_port_0_req_ready, // @[sodor_internal_tile.scala:34:14] output io_master_port_0_req_valid, // @[sodor_internal_tile.scala:34:14] output [31:0] io_master_port_0_req_bits_addr, // @[sodor_internal_tile.scala:34:14] output [31:0] io_master_port_0_req_bits_data, // @[sodor_internal_tile.scala:34:14] output io_master_port_0_req_bits_fcn, // @[sodor_internal_tile.scala:34:14] output [2:0] io_master_port_0_req_bits_typ, // @[sodor_internal_tile.scala:34:14] input io_master_port_0_resp_valid, // @[sodor_internal_tile.scala:34:14] input [31:0] io_master_port_0_resp_bits_data, // @[sodor_internal_tile.scala:34:14] input io_interrupt_debug, // @[sodor_internal_tile.scala:34:14] input io_interrupt_mtip, // @[sodor_internal_tile.scala:34:14] input io_interrupt_msip, // @[sodor_internal_tile.scala:34:14] input io_interrupt_meip, // @[sodor_internal_tile.scala:34:14] input io_hartid // @[sodor_internal_tile.scala:34:14] ); wire _router_io_scratchPort_req_valid; // @[sodor_internal_tile.scala:126:24] wire [31:0] _router_io_scratchPort_req_bits_addr; // @[sodor_internal_tile.scala:126:24] wire [31:0] _router_io_scratchPort_req_bits_data; // @[sodor_internal_tile.scala:126:24] wire _router_io_scratchPort_req_bits_fcn; // @[sodor_internal_tile.scala:126:24] wire [2:0] _router_io_scratchPort_req_bits_typ; // @[sodor_internal_tile.scala:126:24] wire _router_io_corePort_req_ready; // @[sodor_internal_tile.scala:126:24] wire _router_io_corePort_resp_valid; // @[sodor_internal_tile.scala:126:24] wire [31:0] _router_io_corePort_resp_bits_data; // @[sodor_internal_tile.scala:126:24] wire _memory_io_core_ports_0_resp_valid; // @[sodor_internal_tile.scala:122:22] wire [31:0] _memory_io_core_ports_0_resp_bits_data; // @[sodor_internal_tile.scala:122:22] wire _core_io_mem_req_valid; // @[sodor_internal_tile.scala:120:22] wire [31:0] _core_io_mem_req_bits_addr; // @[sodor_internal_tile.scala:120:22] wire [31:0] _core_io_mem_req_bits_data; // @[sodor_internal_tile.scala:120:22] wire _core_io_mem_req_bits_fcn; // @[sodor_internal_tile.scala:120:22] wire [2:0] _core_io_mem_req_bits_typ; // @[sodor_internal_tile.scala:120:22] wire io_debug_port_req_valid_0 = io_debug_port_req_valid; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_debug_port_req_bits_addr_0 = io_debug_port_req_bits_addr; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_debug_port_req_bits_data_0 = io_debug_port_req_bits_data; // @[sodor_internal_tile.scala:117:7] wire io_debug_port_req_bits_fcn_0 = io_debug_port_req_bits_fcn; // @[sodor_internal_tile.scala:117:7] wire [2:0] io_debug_port_req_bits_typ_0 = io_debug_port_req_bits_typ; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_req_ready_0 = io_master_port_0_req_ready; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_resp_valid_0 = io_master_port_0_resp_valid; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_master_port_0_resp_bits_data_0 = io_master_port_0_resp_bits_data; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[sodor_internal_tile.scala:117:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[sodor_internal_tile.scala:117:7] wire io_hartid_0 = io_hartid; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_reset_vector = 32'h10000; // @[sodor_internal_tile.scala:34:14, :117:7, :120:22] wire io_debug_port_req_ready = 1'h1; // @[sodor_internal_tile.scala:34:14, :117:7, :122:22, :126:24] wire [31:0] io_debug_port_resp_bits_data_0; // @[sodor_internal_tile.scala:117:7] wire io_debug_port_resp_valid_0; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_master_port_0_req_bits_addr_0; // @[sodor_internal_tile.scala:117:7] wire [31:0] io_master_port_0_req_bits_data_0; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_req_bits_fcn_0; // @[sodor_internal_tile.scala:117:7] wire [2:0] io_master_port_0_req_bits_typ_0; // @[sodor_internal_tile.scala:117:7] wire io_master_port_0_req_valid_0; // @[sodor_internal_tile.scala:117:7] Core core ( // @[sodor_internal_tile.scala:120:22] .clock (clock), .reset (reset), .io_mem_req_ready (_router_io_corePort_req_ready), // @[sodor_internal_tile.scala:126:24] .io_mem_req_valid (_core_io_mem_req_valid), .io_mem_req_bits_addr (_core_io_mem_req_bits_addr), .io_mem_req_bits_data (_core_io_mem_req_bits_data), .io_mem_req_bits_fcn (_core_io_mem_req_bits_fcn), .io_mem_req_bits_typ (_core_io_mem_req_bits_typ), .io_mem_resp_valid (_router_io_corePort_resp_valid), // @[sodor_internal_tile.scala:126:24] .io_mem_resp_bits_data (_router_io_corePort_resp_bits_data), // @[sodor_internal_tile.scala:126:24] .io_interrupt_debug (io_interrupt_debug_0), // @[sodor_internal_tile.scala:117:7] .io_interrupt_mtip (io_interrupt_mtip_0), // @[sodor_internal_tile.scala:117:7] .io_interrupt_msip (io_interrupt_msip_0), // @[sodor_internal_tile.scala:117:7] .io_interrupt_meip (io_interrupt_meip_0), // @[sodor_internal_tile.scala:117:7] .io_hartid (io_hartid_0) // @[sodor_internal_tile.scala:117:7] ); // @[sodor_internal_tile.scala:120:22] AsyncScratchPadMemory memory ( // @[sodor_internal_tile.scala:122:22] .clock (clock), .reset (reset), .io_core_ports_0_req_valid (_router_io_scratchPort_req_valid), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_addr (_router_io_scratchPort_req_bits_addr), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_data (_router_io_scratchPort_req_bits_data), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_fcn (_router_io_scratchPort_req_bits_fcn), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_req_bits_typ (_router_io_scratchPort_req_bits_typ), // @[sodor_internal_tile.scala:126:24] .io_core_ports_0_resp_valid (_memory_io_core_ports_0_resp_valid), .io_core_ports_0_resp_bits_data (_memory_io_core_ports_0_resp_bits_data), .io_debug_port_req_valid (io_debug_port_req_valid_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_addr (io_debug_port_req_bits_addr_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_data (io_debug_port_req_bits_data_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_fcn (io_debug_port_req_bits_fcn_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_req_bits_typ (io_debug_port_req_bits_typ_0), // @[sodor_internal_tile.scala:117:7] .io_debug_port_resp_valid (io_debug_port_resp_valid_0), .io_debug_port_resp_bits_data (io_debug_port_resp_bits_data_0) ); // @[sodor_internal_tile.scala:122:22] SodorRequestRouter router ( // @[sodor_internal_tile.scala:126:24] .clock (clock), .reset (reset), .io_masterPort_req_ready (io_master_port_0_req_ready_0), // @[sodor_internal_tile.scala:117:7] .io_masterPort_req_valid (io_master_port_0_req_valid_0), .io_masterPort_req_bits_addr (io_master_port_0_req_bits_addr_0), .io_masterPort_req_bits_data (io_master_port_0_req_bits_data_0), .io_masterPort_req_bits_fcn (io_master_port_0_req_bits_fcn_0), .io_masterPort_req_bits_typ (io_master_port_0_req_bits_typ_0), .io_masterPort_resp_valid (io_master_port_0_resp_valid_0), // @[sodor_internal_tile.scala:117:7] .io_masterPort_resp_bits_data (io_master_port_0_resp_bits_data_0), // @[sodor_internal_tile.scala:117:7] .io_scratchPort_req_valid (_router_io_scratchPort_req_valid), .io_scratchPort_req_bits_addr (_router_io_scratchPort_req_bits_addr), .io_scratchPort_req_bits_data (_router_io_scratchPort_req_bits_data), .io_scratchPort_req_bits_fcn (_router_io_scratchPort_req_bits_fcn), .io_scratchPort_req_bits_typ (_router_io_scratchPort_req_bits_typ), .io_scratchPort_resp_valid (_memory_io_core_ports_0_resp_valid), // @[sodor_internal_tile.scala:122:22] .io_scratchPort_resp_bits_data (_memory_io_core_ports_0_resp_bits_data), // @[sodor_internal_tile.scala:122:22] .io_corePort_req_ready (_router_io_corePort_req_ready), .io_corePort_req_valid (_core_io_mem_req_valid), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_addr (_core_io_mem_req_bits_addr), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_data (_core_io_mem_req_bits_data), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_fcn (_core_io_mem_req_bits_fcn), // @[sodor_internal_tile.scala:120:22] .io_corePort_req_bits_typ (_core_io_mem_req_bits_typ), // @[sodor_internal_tile.scala:120:22] .io_corePort_resp_valid (_router_io_corePort_resp_valid), .io_corePort_resp_bits_data (_router_io_corePort_resp_bits_data), .io_respAddress (_core_io_mem_req_bits_addr) // @[sodor_internal_tile.scala:120:22] ); // @[sodor_internal_tile.scala:126:24] assign io_debug_port_resp_valid = io_debug_port_resp_valid_0; // @[sodor_internal_tile.scala:117:7] assign io_debug_port_resp_bits_data = io_debug_port_resp_bits_data_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_valid = io_master_port_0_req_valid_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_addr = io_master_port_0_req_bits_addr_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_data = io_master_port_0_req_bits_data_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_fcn = io_master_port_0_req_bits_fcn_0; // @[sodor_internal_tile.scala:117:7] assign io_master_port_0_req_bits_typ = io_master_port_0_req_bits_typ_0; // @[sodor_internal_tile.scala:117:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module CaptureChain_JTAGIdcodeBundle : input clock : Clock input reset : Reset output io : { flip chainIn : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, chainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, capture : { flip bits : { version : UInt<4>, partNumber : UInt<16>, mfrId : UInt<11>, always1 : UInt<1>}, capture : UInt<1>}} connect io.chainOut.shift, io.chainIn.shift connect io.chainOut.capture, io.chainIn.capture connect io.chainOut.update, io.chainIn.update reg regs_0 : UInt<1>, clock reg regs_1 : UInt<1>, clock reg regs_2 : UInt<1>, clock reg regs_3 : UInt<1>, clock reg regs_4 : UInt<1>, clock reg regs_5 : UInt<1>, clock reg regs_6 : UInt<1>, clock reg regs_7 : UInt<1>, clock reg regs_8 : UInt<1>, clock reg regs_9 : UInt<1>, clock reg regs_10 : UInt<1>, clock reg regs_11 : UInt<1>, clock reg regs_12 : UInt<1>, clock reg regs_13 : UInt<1>, clock reg regs_14 : UInt<1>, clock reg regs_15 : UInt<1>, clock reg regs_16 : UInt<1>, clock reg regs_17 : UInt<1>, clock reg regs_18 : UInt<1>, clock reg regs_19 : UInt<1>, clock reg regs_20 : UInt<1>, clock reg regs_21 : UInt<1>, clock reg regs_22 : UInt<1>, clock reg regs_23 : UInt<1>, clock reg regs_24 : UInt<1>, clock reg regs_25 : UInt<1>, clock reg regs_26 : UInt<1>, clock reg regs_27 : UInt<1>, clock reg regs_28 : UInt<1>, clock reg regs_29 : UInt<1>, clock reg regs_30 : UInt<1>, clock reg regs_31 : UInt<1>, clock connect io.chainOut.data, regs_0 when io.chainIn.capture : node regs_0_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_0_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_0_T = cat(regs_0_hi, regs_0_lo) node _regs_0_T_1 = bits(_regs_0_T, 0, 0) connect regs_0, _regs_0_T_1 node regs_1_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_1_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_1_T = cat(regs_1_hi, regs_1_lo) node _regs_1_T_1 = bits(_regs_1_T, 1, 1) connect regs_1, _regs_1_T_1 node regs_2_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_2_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_2_T = cat(regs_2_hi, regs_2_lo) node _regs_2_T_1 = bits(_regs_2_T, 2, 2) connect regs_2, _regs_2_T_1 node regs_3_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_3_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_3_T = cat(regs_3_hi, regs_3_lo) node _regs_3_T_1 = bits(_regs_3_T, 3, 3) connect regs_3, _regs_3_T_1 node regs_4_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_4_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_4_T = cat(regs_4_hi, regs_4_lo) node _regs_4_T_1 = bits(_regs_4_T, 4, 4) connect regs_4, _regs_4_T_1 node regs_5_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_5_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_5_T = cat(regs_5_hi, regs_5_lo) node _regs_5_T_1 = bits(_regs_5_T, 5, 5) connect regs_5, _regs_5_T_1 node regs_6_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_6_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_6_T = cat(regs_6_hi, regs_6_lo) node _regs_6_T_1 = bits(_regs_6_T, 6, 6) connect regs_6, _regs_6_T_1 node regs_7_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_7_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_7_T = cat(regs_7_hi, regs_7_lo) node _regs_7_T_1 = bits(_regs_7_T, 7, 7) connect regs_7, _regs_7_T_1 node regs_8_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_8_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_8_T = cat(regs_8_hi, regs_8_lo) node _regs_8_T_1 = bits(_regs_8_T, 8, 8) connect regs_8, _regs_8_T_1 node regs_9_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_9_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_9_T = cat(regs_9_hi, regs_9_lo) node _regs_9_T_1 = bits(_regs_9_T, 9, 9) connect regs_9, _regs_9_T_1 node regs_10_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_10_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_10_T = cat(regs_10_hi, regs_10_lo) node _regs_10_T_1 = bits(_regs_10_T, 10, 10) connect regs_10, _regs_10_T_1 node regs_11_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_11_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_11_T = cat(regs_11_hi, regs_11_lo) node _regs_11_T_1 = bits(_regs_11_T, 11, 11) connect regs_11, _regs_11_T_1 node regs_12_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_12_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_12_T = cat(regs_12_hi, regs_12_lo) node _regs_12_T_1 = bits(_regs_12_T, 12, 12) connect regs_12, _regs_12_T_1 node regs_13_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_13_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_13_T = cat(regs_13_hi, regs_13_lo) node _regs_13_T_1 = bits(_regs_13_T, 13, 13) connect regs_13, _regs_13_T_1 node regs_14_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_14_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_14_T = cat(regs_14_hi, regs_14_lo) node _regs_14_T_1 = bits(_regs_14_T, 14, 14) connect regs_14, _regs_14_T_1 node regs_15_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_15_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_15_T = cat(regs_15_hi, regs_15_lo) node _regs_15_T_1 = bits(_regs_15_T, 15, 15) connect regs_15, _regs_15_T_1 node regs_16_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_16_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_16_T = cat(regs_16_hi, regs_16_lo) node _regs_16_T_1 = bits(_regs_16_T, 16, 16) connect regs_16, _regs_16_T_1 node regs_17_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_17_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_17_T = cat(regs_17_hi, regs_17_lo) node _regs_17_T_1 = bits(_regs_17_T, 17, 17) connect regs_17, _regs_17_T_1 node regs_18_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_18_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_18_T = cat(regs_18_hi, regs_18_lo) node _regs_18_T_1 = bits(_regs_18_T, 18, 18) connect regs_18, _regs_18_T_1 node regs_19_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_19_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_19_T = cat(regs_19_hi, regs_19_lo) node _regs_19_T_1 = bits(_regs_19_T, 19, 19) connect regs_19, _regs_19_T_1 node regs_20_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_20_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_20_T = cat(regs_20_hi, regs_20_lo) node _regs_20_T_1 = bits(_regs_20_T, 20, 20) connect regs_20, _regs_20_T_1 node regs_21_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_21_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_21_T = cat(regs_21_hi, regs_21_lo) node _regs_21_T_1 = bits(_regs_21_T, 21, 21) connect regs_21, _regs_21_T_1 node regs_22_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_22_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_22_T = cat(regs_22_hi, regs_22_lo) node _regs_22_T_1 = bits(_regs_22_T, 22, 22) connect regs_22, _regs_22_T_1 node regs_23_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_23_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_23_T = cat(regs_23_hi, regs_23_lo) node _regs_23_T_1 = bits(_regs_23_T, 23, 23) connect regs_23, _regs_23_T_1 node regs_24_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_24_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_24_T = cat(regs_24_hi, regs_24_lo) node _regs_24_T_1 = bits(_regs_24_T, 24, 24) connect regs_24, _regs_24_T_1 node regs_25_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_25_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_25_T = cat(regs_25_hi, regs_25_lo) node _regs_25_T_1 = bits(_regs_25_T, 25, 25) connect regs_25, _regs_25_T_1 node regs_26_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_26_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_26_T = cat(regs_26_hi, regs_26_lo) node _regs_26_T_1 = bits(_regs_26_T, 26, 26) connect regs_26, _regs_26_T_1 node regs_27_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_27_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_27_T = cat(regs_27_hi, regs_27_lo) node _regs_27_T_1 = bits(_regs_27_T, 27, 27) connect regs_27, _regs_27_T_1 node regs_28_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_28_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_28_T = cat(regs_28_hi, regs_28_lo) node _regs_28_T_1 = bits(_regs_28_T, 28, 28) connect regs_28, _regs_28_T_1 node regs_29_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_29_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_29_T = cat(regs_29_hi, regs_29_lo) node _regs_29_T_1 = bits(_regs_29_T, 29, 29) connect regs_29, _regs_29_T_1 node regs_30_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_30_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_30_T = cat(regs_30_hi, regs_30_lo) node _regs_30_T_1 = bits(_regs_30_T, 30, 30) connect regs_30, _regs_30_T_1 node regs_31_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_31_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_31_T = cat(regs_31_hi, regs_31_lo) node _regs_31_T_1 = bits(_regs_31_T, 31, 31) connect regs_31, _regs_31_T_1 connect io.capture.capture, UInt<1>(0h1) else : when io.chainIn.shift : connect regs_31, io.chainIn.data connect regs_0, regs_1 connect regs_1, regs_2 connect regs_2, regs_3 connect regs_3, regs_4 connect regs_4, regs_5 connect regs_5, regs_6 connect regs_6, regs_7 connect regs_7, regs_8 connect regs_8, regs_9 connect regs_9, regs_10 connect regs_10, regs_11 connect regs_11, regs_12 connect regs_12, regs_13 connect regs_13, regs_14 connect regs_14, regs_15 connect regs_15, regs_16 connect regs_16, regs_17 connect regs_17, regs_18 connect regs_18, regs_19 connect regs_19, regs_20 connect regs_20, regs_21 connect regs_21, regs_22 connect regs_22, regs_23 connect regs_23, regs_24 connect regs_24, regs_25 connect regs_25, regs_26 connect regs_26, regs_27 connect regs_27, regs_28 connect regs_28, regs_29 connect regs_29, regs_30 connect regs_30, regs_31 connect io.capture.capture, UInt<1>(0h0) else : connect io.capture.capture, UInt<1>(0h0) node _T = and(io.chainIn.capture, io.chainIn.update) node _T_1 = eq(_T, UInt<1>(0h0)) node _T_2 = and(io.chainIn.capture, io.chainIn.shift) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = and(_T_1, _T_3) node _T_5 = and(io.chainIn.update, io.chainIn.shift) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = and(_T_4, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at JtagShifter.scala:118 assert(!(io.chainIn.capture && io.chainIn.update)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert

module CaptureChain_JTAGIdcodeBundle( // @[JtagShifter.scala:89:7] input clock, // @[JtagShifter.scala:89:7] input reset, // @[JtagShifter.scala:89:7] input io_chainIn_shift, // @[JtagShifter.scala:94:14] input io_chainIn_data, // @[JtagShifter.scala:94:14] input io_chainIn_capture, // @[JtagShifter.scala:94:14] input io_chainIn_update, // @[JtagShifter.scala:94:14] output io_chainOut_data // @[JtagShifter.scala:94:14] ); reg regs_0; // @[JtagShifter.scala:102:39] reg regs_1; // @[JtagShifter.scala:102:39] reg regs_2; // @[JtagShifter.scala:102:39] reg regs_3; // @[JtagShifter.scala:102:39] reg regs_4; // @[JtagShifter.scala:102:39] reg regs_5; // @[JtagShifter.scala:102:39] reg regs_6; // @[JtagShifter.scala:102:39] reg regs_7; // @[JtagShifter.scala:102:39] reg regs_8; // @[JtagShifter.scala:102:39] reg regs_9; // @[JtagShifter.scala:102:39] reg regs_10; // @[JtagShifter.scala:102:39] reg regs_11; // @[JtagShifter.scala:102:39] reg regs_12; // @[JtagShifter.scala:102:39] reg regs_13; // @[JtagShifter.scala:102:39] reg regs_14; // @[JtagShifter.scala:102:39] reg regs_15; // @[JtagShifter.scala:102:39] reg regs_16; // @[JtagShifter.scala:102:39] reg regs_17; // @[JtagShifter.scala:102:39] reg regs_18; // @[JtagShifter.scala:102:39] reg regs_19; // @[JtagShifter.scala:102:39] reg regs_20; // @[JtagShifter.scala:102:39] reg regs_21; // @[JtagShifter.scala:102:39] reg regs_22; // @[JtagShifter.scala:102:39] reg regs_23; // @[JtagShifter.scala:102:39] reg regs_24; // @[JtagShifter.scala:102:39] reg regs_25; // @[JtagShifter.scala:102:39] reg regs_26; // @[JtagShifter.scala:102:39] reg regs_27; // @[JtagShifter.scala:102:39] reg regs_28; // @[JtagShifter.scala:102:39] reg regs_29; // @[JtagShifter.scala:102:39] reg regs_30; // @[JtagShifter.scala:102:39] reg regs_31; // @[JtagShifter.scala:102:39]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<4>(0h8)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_141 = shr(io.in.a.bits.source, 2) node _T_142 = eq(_T_141, UInt<4>(0h8)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<4>(0h8)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<17>(0h10000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<4>(0h8)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<2>(0h2)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<4>(0h8)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<2>(0h2)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<4>(0h8)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<17>(0h10000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<4>(0h8)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<2>(0h2)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<17>(0h10000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = and(_T_547, _T_552) node _T_554 = or(UInt<1>(0h0), _T_553) node _T_555 = and(_T_546, _T_554) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_555, UInt<1>(0h1), "") : assert_26 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(source_ok, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(is_aligned, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_565 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_565, UInt<1>(0h1), "") : assert_29 node _T_569 = eq(io.in.a.bits.mask, mask) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_569, UInt<1>(0h1), "") : assert_30 node _T_573 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_573 : node _T_574 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_575 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_578 = shr(io.in.a.bits.source, 2) node _T_579 = eq(_T_578, UInt<1>(0h0)) node _T_580 = leq(UInt<1>(0h0), uncommonBits_35) node _T_581 = and(_T_579, _T_580) node _T_582 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_583 = and(_T_581, _T_582) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_584 = shr(io.in.a.bits.source, 2) node _T_585 = eq(_T_584, UInt<1>(0h1)) node _T_586 = leq(UInt<1>(0h0), uncommonBits_36) node _T_587 = and(_T_585, _T_586) node _T_588 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_589 = and(_T_587, _T_588) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_590 = shr(io.in.a.bits.source, 2) node _T_591 = eq(_T_590, UInt<2>(0h2)) node _T_592 = leq(UInt<1>(0h0), uncommonBits_37) node _T_593 = and(_T_591, _T_592) node _T_594 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_595 = and(_T_593, _T_594) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<2>(0h3)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_38) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<4>(0h8)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_39) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_39, UInt<2>(0h2)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_610 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_611 = or(_T_577, _T_583) node _T_612 = or(_T_611, _T_589) node _T_613 = or(_T_612, _T_595) node _T_614 = or(_T_613, _T_601) node _T_615 = or(_T_614, _T_607) node _T_616 = or(_T_615, _T_608) node _T_617 = or(_T_616, _T_609) node _T_618 = or(_T_617, _T_610) node _T_619 = and(_T_576, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_623 = cvt(_T_622) node _T_624 = and(_T_623, asSInt(UInt<17>(0h10000))) node _T_625 = asSInt(_T_624) node _T_626 = eq(_T_625, asSInt(UInt<1>(0h0))) node _T_627 = and(_T_621, _T_626) node _T_628 = or(UInt<1>(0h0), _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_629, UInt<1>(0h1), "") : assert_31 node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(source_ok, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(is_aligned, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_639 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_639, UInt<1>(0h1), "") : assert_34 node _T_643 = not(mask) node _T_644 = and(io.in.a.bits.mask, _T_643) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_645, UInt<1>(0h1), "") : assert_35 node _T_649 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_649 : node _T_650 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_651 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_652 = and(_T_650, _T_651) node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_654 = shr(io.in.a.bits.source, 2) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_40) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h1)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_41) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<2>(0h2)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_42) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h3)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_43) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<4>(0h8)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_44) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_44, UInt<2>(0h2)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_686 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_687 = or(_T_653, _T_659) node _T_688 = or(_T_687, _T_665) node _T_689 = or(_T_688, _T_671) node _T_690 = or(_T_689, _T_677) node _T_691 = or(_T_690, _T_683) node _T_692 = or(_T_691, _T_684) node _T_693 = or(_T_692, _T_685) node _T_694 = or(_T_693, _T_686) node _T_695 = and(_T_652, _T_694) node _T_696 = or(UInt<1>(0h0), _T_695) node _T_697 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_698 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<17>(0h10000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = and(_T_697, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = and(_T_696, _T_704) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_705, UInt<1>(0h1), "") : assert_36 node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(source_ok, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(is_aligned, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_715 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_715, UInt<1>(0h1), "") : assert_39 node _T_719 = eq(io.in.a.bits.mask, mask) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_719, UInt<1>(0h1), "") : assert_40 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _T_727 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_728 = shr(io.in.a.bits.source, 2) node _T_729 = eq(_T_728, UInt<1>(0h0)) node _T_730 = leq(UInt<1>(0h0), uncommonBits_45) node _T_731 = and(_T_729, _T_730) node _T_732 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_733 = and(_T_731, _T_732) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h1)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_46) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<2>(0h2)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_47) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h3)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_48) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<4>(0h8)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_49) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_49, UInt<2>(0h2)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_759 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_761 = or(_T_727, _T_733) node _T_762 = or(_T_761, _T_739) node _T_763 = or(_T_762, _T_745) node _T_764 = or(_T_763, _T_751) node _T_765 = or(_T_764, _T_757) node _T_766 = or(_T_765, _T_758) node _T_767 = or(_T_766, _T_759) node _T_768 = or(_T_767, _T_760) node _T_769 = and(_T_726, _T_768) node _T_770 = or(UInt<1>(0h0), _T_769) node _T_771 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_772 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_773 = cvt(_T_772) node _T_774 = and(_T_773, asSInt(UInt<17>(0h10000))) node _T_775 = asSInt(_T_774) node _T_776 = eq(_T_775, asSInt(UInt<1>(0h0))) node _T_777 = and(_T_771, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = and(_T_770, _T_778) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_779, UInt<1>(0h1), "") : assert_41 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(source_ok, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(is_aligned, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_789 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_789, UInt<1>(0h1), "") : assert_44 node _T_793 = eq(io.in.a.bits.mask, mask) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_793, UInt<1>(0h1), "") : assert_45 node _T_797 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_797 : node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<1>(0h0)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_50) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h1)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_51) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<2>(0h2)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_52) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h3)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_53) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<4>(0h8)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_54) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_54, UInt<2>(0h2)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_834 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_835 = or(_T_801, _T_807) node _T_836 = or(_T_835, _T_813) node _T_837 = or(_T_836, _T_819) node _T_838 = or(_T_837, _T_825) node _T_839 = or(_T_838, _T_831) node _T_840 = or(_T_839, _T_832) node _T_841 = or(_T_840, _T_833) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_800, _T_842) node _T_844 = or(UInt<1>(0h0), _T_843) node _T_845 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_846 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = and(_T_845, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = and(_T_844, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_853, UInt<1>(0h1), "") : assert_46 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_863 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_863, UInt<1>(0h1), "") : assert_49 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_867, UInt<1>(0h1), "") : assert_50 node _T_871 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(_T_871, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_871, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_875 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_875, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_879 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_879 : node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(source_ok_1, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_883 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_883, UInt<1>(0h1), "") : assert_54 node _T_887 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_887, UInt<1>(0h1), "") : assert_55 node _T_891 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_891, UInt<1>(0h1), "") : assert_56 node _T_895 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_895, UInt<1>(0h1), "") : assert_57 node _T_899 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_899 : node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(source_ok_1, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(sink_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_906 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_906, UInt<1>(0h1), "") : assert_60 node _T_910 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_910, UInt<1>(0h1), "") : assert_61 node _T_914 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_914, UInt<1>(0h1), "") : assert_62 node _T_918 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_918, UInt<1>(0h1), "") : assert_63 node _T_922 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_923 = or(UInt<1>(0h0), _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_923, UInt<1>(0h1), "") : assert_64 node _T_927 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_927 : node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(source_ok_1, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(sink_ok, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_934 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_934, UInt<1>(0h1), "") : assert_67 node _T_938 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_938, UInt<1>(0h1), "") : assert_68 node _T_942 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_942, UInt<1>(0h1), "") : assert_69 node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_947 = or(_T_946, io.in.d.bits.corrupt) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_947, UInt<1>(0h1), "") : assert_70 node _T_951 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_952, UInt<1>(0h1), "") : assert_71 node _T_956 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_956 : node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(source_ok_1, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_960 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_960, UInt<1>(0h1), "") : assert_73 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_964, UInt<1>(0h1), "") : assert_74 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_969, UInt<1>(0h1), "") : assert_75 node _T_973 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_977, UInt<1>(0h1), "") : assert_77 node _T_981 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_982 = or(_T_981, io.in.d.bits.corrupt) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_982, UInt<1>(0h1), "") : assert_78 node _T_986 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_987, UInt<1>(0h1), "") : assert_79 node _T_991 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_991 : node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(source_ok_1, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_995 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_995, UInt<1>(0h1), "") : assert_81 node _T_999 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_999, UInt<1>(0h1), "") : assert_82 node _T_1003 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1008 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1012 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1016 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1020 = eq(a_first, UInt<1>(0h0)) node _T_1021 = and(io.in.a.valid, _T_1020) when _T_1021 : node _T_1022 = eq(io.in.a.bits.opcode, opcode) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_87 node _T_1026 = eq(io.in.a.bits.param, param) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_88 node _T_1030 = eq(io.in.a.bits.size, size) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_89 node _T_1034 = eq(io.in.a.bits.source, source) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_90 node _T_1038 = eq(io.in.a.bits.address, address) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_91 node _T_1042 = and(io.in.a.ready, io.in.a.valid) node _T_1043 = and(_T_1042, a_first) when _T_1043 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1044 = eq(d_first, UInt<1>(0h0)) node _T_1045 = and(io.in.d.valid, _T_1044) when _T_1045 : node _T_1046 = eq(io.in.d.bits.opcode, opcode_1) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_92 node _T_1050 = eq(io.in.d.bits.param, param_1) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_93 node _T_1054 = eq(io.in.d.bits.size, size_1) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_94 node _T_1058 = eq(io.in.d.bits.source, source_1) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_95 node _T_1062 = eq(io.in.d.bits.sink, sink) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_96 node _T_1066 = eq(io.in.d.bits.denied, denied) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_97 node _T_1070 = and(io.in.d.ready, io.in.d.valid) node _T_1071 = and(_T_1070, d_first) when _T_1071 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1072 = and(io.in.a.valid, a_first_1) node _T_1073 = and(_T_1072, UInt<1>(0h1)) when _T_1073 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1074 = and(io.in.a.ready, io.in.a.valid) node _T_1075 = and(_T_1074, a_first_1) node _T_1076 = and(_T_1075, UInt<1>(0h1)) when _T_1076 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1077 = dshr(inflight, io.in.a.bits.source) node _T_1078 = bits(_T_1077, 0, 0) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1083 = and(io.in.d.valid, d_first_1) node _T_1084 = and(_T_1083, UInt<1>(0h1)) node _T_1085 = eq(d_release_ack, UInt<1>(0h0)) node _T_1086 = and(_T_1084, _T_1085) when _T_1086 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1087 = and(io.in.d.ready, io.in.d.valid) node _T_1088 = and(_T_1087, d_first_1) node _T_1089 = and(_T_1088, UInt<1>(0h1)) node _T_1090 = eq(d_release_ack, UInt<1>(0h0)) node _T_1091 = and(_T_1089, _T_1090) when _T_1091 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1092 = and(io.in.d.valid, d_first_1) node _T_1093 = and(_T_1092, UInt<1>(0h1)) node _T_1094 = eq(d_release_ack, UInt<1>(0h0)) node _T_1095 = and(_T_1093, _T_1094) when _T_1095 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1096 = dshr(inflight, io.in.d.bits.source) node _T_1097 = bits(_T_1096, 0, 0) node _T_1098 = or(_T_1097, same_cycle_resp) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1102 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1103 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1104 = or(_T_1102, _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_100 node _T_1108 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_101 else : node _T_1112 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1113 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1114 = or(_T_1112, _T_1113) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_102 node _T_1118 = eq(io.in.d.bits.size, a_size_lookup) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_103 node _T_1122 = and(io.in.d.valid, d_first_1) node _T_1123 = and(_T_1122, a_first_1) node _T_1124 = and(_T_1123, io.in.a.valid) node _T_1125 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = eq(d_release_ack, UInt<1>(0h0)) node _T_1128 = and(_T_1126, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1130 = or(_T_1129, io.in.a.ready) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_1134 = orr(inflight) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) node _T_1136 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) node _T_1138 = lt(watchdog, plusarg_reader.out) node _T_1139 = or(_T_1137, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1143 = and(io.in.a.ready, io.in.a.valid) node _T_1144 = and(io.in.d.ready, io.in.d.valid) node _T_1145 = or(_T_1143, _T_1144) when _T_1145 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1146 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1147 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1148 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1146, _T_1149) when _T_1150 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1151 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1152 = and(_T_1151, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1153 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1154 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = and(_T_1152, _T_1155) when _T_1156 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1157 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1158 = bits(_T_1157, 0, 0) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1163 = and(io.in.d.valid, d_first_2) node _T_1164 = and(_T_1163, UInt<1>(0h1)) node _T_1165 = and(_T_1164, d_release_ack_1) when _T_1165 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1166 = and(io.in.d.ready, io.in.d.valid) node _T_1167 = and(_T_1166, d_first_2) node _T_1168 = and(_T_1167, UInt<1>(0h1)) node _T_1169 = and(_T_1168, d_release_ack_1) when _T_1169 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1170 = and(io.in.d.valid, d_first_2) node _T_1171 = and(_T_1170, UInt<1>(0h1)) node _T_1172 = and(_T_1171, d_release_ack_1) when _T_1172 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1173 = dshr(inflight_1, io.in.d.bits.source) node _T_1174 = bits(_T_1173, 0, 0) node _T_1175 = or(_T_1174, same_cycle_resp_1) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1179 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_108 else : node _T_1183 = eq(io.in.d.bits.size, c_size_lookup) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_109 node _T_1187 = and(io.in.d.valid, d_first_2) node _T_1188 = and(_T_1187, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1189 = and(_T_1188, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1190 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = and(_T_1191, d_release_ack_1) node _T_1193 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) when _T_1194 : node _T_1195 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1196 = or(_T_1195, _WIRE_27.ready) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_1200 = orr(inflight_1) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1203 = or(_T_1201, _T_1202) node _T_1204 = lt(watchdog_1, plusarg_reader_1.out) node _T_1205 = or(_T_1203, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1209 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = or(_T_1209, _T_1210) when _T_1211 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [259:0] _inflight_opcodes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [259:0] _inflight_sizes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [64:0] _inflight_T_4 = 65'h1FFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [259:0] d_opcodes_clr_1 = 260'h0; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1 = 260'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [64:0] d_clr_1 = 65'h0; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1 = 65'h0; // @[Monitor.scala:775:34] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1143 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1143; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1143; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1211 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1211; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1211; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1211; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1076 = _T_1143 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1076 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1076 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1076 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1076 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1076 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_1122 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_4 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1122 ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1089 = _T_1211 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_1089 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1089 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1089 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_19 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_19 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_19( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_19 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_134 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_134( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_47 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_94 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_47 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0he) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0he)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_16 = eq(UInt<4>(0hb), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_95 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_47 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node _c_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[1], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], _c_T_1) node _c_T_2 = cat(c_hi, _c_T) node _c_T_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _c_T_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node c_hi_1 = cat(io.out_credit_available.`2`[0], _c_T_4) node _c_T_5 = cat(c_hi_1, _c_T_3) node _c_T_6 = and(_c_T_2, _c_T_5) node c = neq(_c_T_6, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node out_channel_oh_0 = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_channel_oh_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _out_bundle_bits_out_virt_channel_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _out_bundle_bits_out_virt_channel_T_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 1) node _out_bundle_bits_out_virt_channel_T_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[1], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_1, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_5 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_3, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_6 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_4, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_8 = or(_out_bundle_bits_out_virt_channel_T_7, _out_bundle_bits_out_virt_channel_T_6) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<1> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_8 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_47( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hE; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hE; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d32s7k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a32d32s7k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [3:0] saved_mask; // @[Repeater.scala:21:18] reg [31:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_223 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], chosen_oh : UInt<2>[1]} regreset lock_0 : UInt<2>, clock, reset, UInt<2>(0h0) node _unassigned_T = cat(io.in[1].valid, io.in[0].valid) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire choices : UInt<2>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = mux(_sel_T_6, UInt<4>(0h8), UInt<4>(0h0)) node _sel_T_8 = mux(_sel_T_5, UInt<4>(0h4), _sel_T_7) node _sel_T_9 = mux(_sel_T_4, UInt<4>(0h2), _sel_T_8) node sel = mux(_sel_T_3, UInt<4>(0h1), _sel_T_9) node _choices_0_T = shr(sel, 2) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = mux(_T_3, UInt<2>(0h2), UInt<2>(0h0)) node _T_5 = mux(_T_2, UInt<2>(0h1), _T_4) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) node in_tails = cat(io.in[1].bits.tail, io.in[0].bits.tail) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node in_valids = cat(_in_valids_T_3, _in_valids_T_1) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<2>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) wire _io_out_0_bits_WIRE : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>} node _io_out_0_bits_T_2 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_4 = or(_io_out_0_bits_T_2, _io_out_0_bits_T_3) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_4 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_out_0_bits_WIRE_3 : UInt<1>[5] node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_5, _io_out_0_bits_T_6) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_7 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_10 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_13 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_13 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_14, _io_out_0_bits_T_15) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_16 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_19 = or(_io_out_0_bits_T_17, _io_out_0_bits_T_18) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_19 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_9 : UInt<1>[5] node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_21 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_21) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_9[0], _io_out_0_bits_WIRE_10 node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_25 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_25 connect _io_out_0_bits_WIRE_9[1], _io_out_0_bits_WIRE_11 node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_28 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_27) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_28 connect _io_out_0_bits_WIRE_9[2], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_30) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_31 connect _io_out_0_bits_WIRE_9[3], _io_out_0_bits_WIRE_13 node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_34 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33) wire _io_out_0_bits_WIRE_14 : UInt<1> connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_34 connect _io_out_0_bits_WIRE_9[4], _io_out_0_bits_WIRE_14 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_9 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_6 = bits(chosen, 0, 0) node _T_7 = and(_T_6, io.out[0].ready) when _T_7 : connect io.in[0].ready, UInt<1>(0h1) node _T_8 = bits(chosen, 1, 1) node _T_9 = and(_T_8, io.out[0].ready) when _T_9 : connect io.in[1].ready, UInt<1>(0h1) node _T_10 = or(UInt<2>(0h0), chosen) node _T_11 = and(io.out[0].ready, io.out[0].valid) when _T_11 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_12 = and(io.out[0].ready, io.out[0].valid) when _T_12 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = or(_mask_T, _mask_T_1) connect mask, _mask_T_2 else : node _mask_T_3 = not(mask) node _mask_T_4 = eq(_mask_T_3, UInt<1>(0h0)) node _mask_T_5 = shl(mask, 1) node _mask_T_6 = or(_mask_T_5, UInt<1>(0h1)) node _mask_T_7 = mux(_mask_T_4, UInt<1>(0h0), _mask_T_6) connect mask, _mask_T_7

module SwitchArbiter_223( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [1:0] mask; // @[SwitchAllocator.scala:27:21] wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71] wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [1:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[1:0] | sel[3:2]; // @[Mux.scala:50:70] wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38] mask <= 2'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (|_io_out_0_valid_T) ? {chosen[1], |chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,71}, :60:{10,16,23,49}] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_196 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_196( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_102 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_108 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_102( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_108 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_fbus_from_debug_sb : input clock : Clock input reset : Reset output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst widget of TLWidthWidget1 connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect widget.auto.anon_out.d, tlIn.d connect tlIn.a.bits, widget.auto.anon_out.a.bits connect tlIn.a.valid, widget.auto.anon_out.a.valid connect widget.auto.anon_out.a.ready, tlIn.a.ready connect auto.tl_out, tlOut connect widget.auto.anon_in, auto.widget_anon_in extmodule plusarg_reader_84 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_85 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLInterconnectCoupler_fbus_from_debug_sb( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLWidthWidget1 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode), .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size), .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address), .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data), .auto_anon_in_d_ready (auto_widget_anon_in_d_ready), .auto_anon_in_d_valid (auto_widget_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt), .auto_anon_out_a_ready (auto_tl_out_a_ready), .auto_anon_out_a_valid (auto_tl_out_a_valid), .auto_anon_out_a_bits_opcode (auto_tl_out_a_bits_opcode), .auto_anon_out_a_bits_size (auto_tl_out_a_bits_size), .auto_anon_out_a_bits_address (auto_tl_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_tl_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_tl_out_a_bits_data), .auto_anon_out_d_ready (auto_tl_out_d_ready), .auto_anon_out_d_valid (auto_tl_out_d_valid), .auto_anon_out_d_bits_opcode (auto_tl_out_d_bits_opcode), .auto_anon_out_d_bits_param (auto_tl_out_d_bits_param), .auto_anon_out_d_bits_size (auto_tl_out_d_bits_size), .auto_anon_out_d_bits_sink (auto_tl_out_d_bits_sink), .auto_anon_out_d_bits_denied (auto_tl_out_d_bits_denied), .auto_anon_out_d_bits_data (auto_tl_out_d_bits_data), .auto_anon_out_d_bits_corrupt (auto_tl_out_d_bits_corrupt) ); // @[WidthWidget.scala:230:28] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_130 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_131 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_62( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1148 = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1148 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1148 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1148 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1148 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1148 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_26 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} [15] wire _valids_WIRE : UInt<1>[15] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) regreset valids : UInt<1>[15], clock, reset, _valids_WIRE reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[15], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask) node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0)) node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0)) node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0)) node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4) node _do_enq_T_6 = and(io.flush, io.enq.bits.uop.uses_ldq) node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0)) node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7) wire do_enq : UInt<1> connect do_enq, _do_enq_T_8 node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0)) node _valids_0_T_4 = and(valids[0], _valids_0_T_3) node _valids_0_T_5 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0)) node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6) connect valids[0], _valids_0_T_7 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0)) node _valids_1_T_4 = and(valids[1], _valids_1_T_3) node _valids_1_T_5 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0)) node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6) connect valids[1], _valids_1_T_7 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0)) node _valids_2_T_4 = and(valids[2], _valids_2_T_3) node _valids_2_T_5 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0)) node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6) connect valids[2], _valids_2_T_7 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0)) node _valids_3_T_4 = and(valids[3], _valids_3_T_3) node _valids_3_T_5 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0)) node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6) connect valids[3], _valids_3_T_7 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0)) node _valids_4_T_4 = and(valids[4], _valids_4_T_3) node _valids_4_T_5 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0)) node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6) connect valids[4], _valids_4_T_7 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0)) node _valids_5_T_4 = and(valids[5], _valids_5_T_3) node _valids_5_T_5 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0)) node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6) connect valids[5], _valids_5_T_7 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0)) node _valids_6_T_4 = and(valids[6], _valids_6_T_3) node _valids_6_T_5 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0)) node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6) connect valids[6], _valids_6_T_7 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0)) node _valids_7_T_4 = and(valids[7], _valids_7_T_3) node _valids_7_T_5 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0)) node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6) connect valids[7], _valids_7_T_7 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = or(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = eq(_valids_8_T_2, UInt<1>(0h0)) node _valids_8_T_4 = and(valids[8], _valids_8_T_3) node _valids_8_T_5 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_6 = eq(_valids_8_T_5, UInt<1>(0h0)) node _valids_8_T_7 = and(_valids_8_T_4, _valids_8_T_6) connect valids[8], _valids_8_T_7 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = or(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = eq(_valids_9_T_2, UInt<1>(0h0)) node _valids_9_T_4 = and(valids[9], _valids_9_T_3) node _valids_9_T_5 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_6 = eq(_valids_9_T_5, UInt<1>(0h0)) node _valids_9_T_7 = and(_valids_9_T_4, _valids_9_T_6) connect valids[9], _valids_9_T_7 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = or(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = eq(_valids_10_T_2, UInt<1>(0h0)) node _valids_10_T_4 = and(valids[10], _valids_10_T_3) node _valids_10_T_5 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_6 = eq(_valids_10_T_5, UInt<1>(0h0)) node _valids_10_T_7 = and(_valids_10_T_4, _valids_10_T_6) connect valids[10], _valids_10_T_7 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = or(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = eq(_valids_11_T_2, UInt<1>(0h0)) node _valids_11_T_4 = and(valids[11], _valids_11_T_3) node _valids_11_T_5 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_6 = eq(_valids_11_T_5, UInt<1>(0h0)) node _valids_11_T_7 = and(_valids_11_T_4, _valids_11_T_6) connect valids[11], _valids_11_T_7 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = or(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = eq(_valids_12_T_2, UInt<1>(0h0)) node _valids_12_T_4 = and(valids[12], _valids_12_T_3) node _valids_12_T_5 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_6 = eq(_valids_12_T_5, UInt<1>(0h0)) node _valids_12_T_7 = and(_valids_12_T_4, _valids_12_T_6) connect valids[12], _valids_12_T_7 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = or(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = eq(_valids_13_T_2, UInt<1>(0h0)) node _valids_13_T_4 = and(valids[13], _valids_13_T_3) node _valids_13_T_5 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_6 = eq(_valids_13_T_5, UInt<1>(0h0)) node _valids_13_T_7 = and(_valids_13_T_4, _valids_13_T_6) connect valids[13], _valids_13_T_7 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = or(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = eq(_valids_14_T_2, UInt<1>(0h0)) node _valids_14_T_4 = and(valids[14], _valids_14_T_3) node _valids_14_T_5 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_6 = eq(_valids_14_T_5, UInt<1>(0h0)) node _valids_14_T_7 = and(_valids_14_T_4, _valids_14_T_6) connect valids[14], _valids_14_T_7 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0he)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when wrap : connect enq_ptr_value, UInt<1>(0h0) when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0he)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 when wrap_1 : connect deq_ptr_value, UInt<1>(0h0) node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) connect io.deq.valid, _io_deq_valid_T_1 connect io.deq.bits, out node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = mux(maybe_full, UInt<4>(0hf), UInt<1>(0h0)) node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value) node _io_count_T_2 = add(UInt<4>(0hf), ptr_diff) node _io_count_T_3 = tail(_io_count_T_2, 1) node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff) node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4) connect io.count, _io_count_T_5

module BranchKillableQueue_26( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_133 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_389 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_133( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_389 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg s1_id : UInt, clock reg s2_id : UInt, clock connect s2_id, s1_id node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) connect io.mem.req.valid, _io_mem_req_valid_T connect io.requestor[0].req.ready, io.mem.req.ready node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 connect io.mem.req.bits, io.requestor[1].req.bits node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T connect s1_id, UInt<1>(0h1) connect io.mem.s1_kill, io.requestor[1].s1_kill connect io.mem.s1_data, io.requestor[1].s1_data connect io.mem.s2_kill, io.requestor[1].s2_kill when io.requestor[0].req.valid : connect io.mem.req.bits, io.requestor[0].req.bits node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 connect s1_id, UInt<1>(0h0) node _T = eq(s1_id, UInt<1>(0h0)) when _T : connect io.mem.s1_kill, io.requestor[0].s1_kill connect io.mem.s1_data, io.requestor[0].s1_data node _T_1 = eq(s2_id, UInt<1>(0h0)) when _T_1 : connect io.mem.s2_kill, io.requestor[0].s2_kill node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt connect io.requestor[0].s2_gpa, io.mem.s2_gpa connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[0].ordered, io.mem.ordered connect io.requestor[0].store_pending, io.mem.store_pending connect io.requestor[0].perf, io.mem.perf node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[0].s2_uncached, io.mem.s2_uncached connect io.requestor[0].s2_paddr, io.mem.s2_paddr connect io.requestor[0].clock_enabled, io.mem.clock_enabled connect io.requestor[0].resp.bits, io.mem.resp.bits node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T connect io.requestor[0].replay_next, io.mem.replay_next node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt connect io.requestor[1].s2_gpa, io.mem.s2_gpa connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[1].ordered, io.mem.ordered connect io.requestor[1].store_pending, io.mem.store_pending connect io.requestor[1].perf, io.mem.perf node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[1].s2_uncached, io.mem.s2_uncached connect io.requestor[1].s2_paddr, io.mem.s2_paddr connect io.requestor[1].clock_enabled, io.mem.clock_enabled connect io.requestor[1].resp.bits, io.mem.resp.bits node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T connect io.requestor[1].replay_next, io.mem.replay_next

module HellaCacheArbiter( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [6:0] io_requestor_0_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_0_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_0_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_0_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_1_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [33:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [6:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_xcpt, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [6:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [33:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_req_bits_tag_0 = io_requestor_0_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd_0 = io_requestor_0_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_size_0 = io_requestor_0_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed_0 = io_requestor_0_req_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp_0 = io_requestor_0_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_s1_data_data_0 = io_requestor_0_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled_0 = io_requestor_0_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [7:0] _io_mem_req_bits_tag_T = 8'h1; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_1_req_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [6:0] io_requestor_1_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_dprv = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_mem_keep_clock_enabled_T = io_requestor_0_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63] wire io_mem_req_bits_phys_0 = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] wire io_mem_req_bits_no_xcpt_0 = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [33:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] reg s1_id; // @[HellaCacheArbiter.scala:20:20] reg s2_id; // @[HellaCacheArbiter.scala:21:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58] assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T; // @[HellaCacheArbiter.scala:10:7, :23:81] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_cmd_0 : io_requestor_1_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_size_0 : io_requestor_1_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_signed_0 = io_requestor_0_req_valid_0 & io_requestor_0_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = {2{io_requestor_0_req_valid_0}}; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 & io_requestor_0_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_no_resp_0 = io_requestor_0_req_valid_0 & io_requestor_0_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] wire [7:0] _io_mem_req_bits_tag_T_1 = {io_requestor_0_req_bits_tag_0, 1'h0}; // @[HellaCacheArbiter.scala:10:7, :34:35] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? _io_mem_req_bits_tag_T_1[6:0] : 7'h1; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26] assign io_mem_s1_kill_0 = s1_id ? io_requestor_1_s1_kill_0 : io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:30] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : io_requestor_0_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30] assign io_mem_s1_data_mask_0 = s1_id ? io_requestor_1_s1_data_mask_0 : 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :20:20, :33:25, :39:24, :50:26, :51:30] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_xcpt = io_mem_req_bits_no_xcpt_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_115 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_115 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 5) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h1f)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 5) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h1f)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_24 = shr(io.in.a.bits.source, 5) node _source_ok_T_25 = eq(_source_ok_T_24, UInt<3>(0h4)) node _source_ok_T_26 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_27 = and(_source_ok_T_25, _source_ok_T_26) node _source_ok_T_28 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_30 = shr(io.in.a.bits.source, 5) node _source_ok_T_31 = eq(_source_ok_T_30, UInt<3>(0h5)) node _source_ok_T_32 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_T_34 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_36 = shr(io.in.a.bits.source, 5) node _source_ok_T_37 = eq(_source_ok_T_36, UInt<3>(0h6)) node _source_ok_T_38 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_T_40 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_42 = shr(io.in.a.bits.source, 5) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<3>(0h7)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 connect _source_ok_WIRE[4], _source_ok_T_29 connect _source_ok_WIRE[5], _source_ok_T_35 connect _source_ok_WIRE[6], _source_ok_T_41 connect _source_ok_WIRE[7], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_17 = shr(io.in.a.bits.source, 5) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_30 = shr(io.in.a.bits.source, 5) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_43 = shr(io.in.a.bits.source, 5) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_56 = shr(io.in.a.bits.source, 5) node _T_57 = eq(_T_56, UInt<3>(0h4)) node _T_58 = leq(UInt<1>(0h0), uncommonBits_4) node _T_59 = and(_T_57, _T_58) node _T_60 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<1>(0h0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_69 = shr(io.in.a.bits.source, 5) node _T_70 = eq(_T_69, UInt<3>(0h5)) node _T_71 = leq(UInt<1>(0h0), uncommonBits_5) node _T_72 = and(_T_70, _T_71) node _T_73 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_77 = cvt(_T_76) node _T_78 = and(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = asSInt(_T_78) node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0))) node _T_81 = or(_T_75, _T_80) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_82 = shr(io.in.a.bits.source, 5) node _T_83 = eq(_T_82, UInt<3>(0h6)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_6) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(_T_87, UInt<1>(0h0)) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_95 = shr(io.in.a.bits.source, 5) node _T_96 = eq(_T_95, UInt<3>(0h7)) node _T_97 = leq(UInt<1>(0h0), uncommonBits_7) node _T_98 = and(_T_96, _T_97) node _T_99 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_100 = and(_T_98, _T_99) node _T_101 = eq(_T_100, UInt<1>(0h0)) node _T_102 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = or(_T_101, _T_106) node _T_108 = and(_T_16, _T_29) node _T_109 = and(_T_108, _T_42) node _T_110 = and(_T_109, _T_55) node _T_111 = and(_T_110, _T_68) node _T_112 = and(_T_111, _T_81) node _T_113 = and(_T_112, _T_94) node _T_114 = and(_T_113, _T_107) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_114, UInt<1>(0h1), "") : assert_1 node _T_118 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_118 : node _T_119 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_120 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_121 = and(_T_119, _T_120) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_122 = shr(io.in.a.bits.source, 5) node _T_123 = eq(_T_122, UInt<1>(0h0)) node _T_124 = leq(UInt<1>(0h0), uncommonBits_8) node _T_125 = and(_T_123, _T_124) node _T_126 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_127 = and(_T_125, _T_126) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_128 = shr(io.in.a.bits.source, 5) node _T_129 = eq(_T_128, UInt<1>(0h1)) node _T_130 = leq(UInt<1>(0h0), uncommonBits_9) node _T_131 = and(_T_129, _T_130) node _T_132 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_133 = and(_T_131, _T_132) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_134 = shr(io.in.a.bits.source, 5) node _T_135 = eq(_T_134, UInt<2>(0h2)) node _T_136 = leq(UInt<1>(0h0), uncommonBits_10) node _T_137 = and(_T_135, _T_136) node _T_138 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_139 = and(_T_137, _T_138) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<2>(0h3)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_11) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0) node _T_146 = shr(io.in.a.bits.source, 5) node _T_147 = eq(_T_146, UInt<3>(0h4)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_12) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_12, UInt<5>(0h1f)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<3>(0h5)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_13) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_13, UInt<5>(0h1f)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_158 = shr(io.in.a.bits.source, 5) node _T_159 = eq(_T_158, UInt<3>(0h6)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_14) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_163 = and(_T_161, _T_162) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_164 = shr(io.in.a.bits.source, 5) node _T_165 = eq(_T_164, UInt<3>(0h7)) node _T_166 = leq(UInt<1>(0h0), uncommonBits_15) node _T_167 = and(_T_165, _T_166) node _T_168 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_169 = and(_T_167, _T_168) node _T_170 = or(_T_127, _T_133) node _T_171 = or(_T_170, _T_139) node _T_172 = or(_T_171, _T_145) node _T_173 = or(_T_172, _T_151) node _T_174 = or(_T_173, _T_157) node _T_175 = or(_T_174, _T_163) node _T_176 = or(_T_175, _T_169) node _T_177 = and(_T_121, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<14>(0h2000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_191 = cvt(_T_190) node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000))) node _T_193 = asSInt(_T_192) node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0))) node _T_195 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<18>(0h2f000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_201 = cvt(_T_200) node _T_202 = and(_T_201, asSInt(UInt<17>(0h10000))) node _T_203 = asSInt(_T_202) node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<27>(0h4000000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<19>(0h40000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = or(_T_184, _T_189) node _T_226 = or(_T_225, _T_194) node _T_227 = or(_T_226, _T_199) node _T_228 = or(_T_227, _T_204) node _T_229 = or(_T_228, _T_209) node _T_230 = or(_T_229, _T_214) node _T_231 = or(_T_230, _T_219) node _T_232 = or(_T_231, _T_224) node _T_233 = and(_T_179, _T_232) node _T_234 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_235 = or(UInt<1>(0h0), _T_234) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<29>(0h10000000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_240, _T_245) node _T_247 = and(_T_235, _T_246) node _T_248 = or(UInt<1>(0h0), _T_233) node _T_249 = or(_T_248, _T_247) node _T_250 = and(_T_178, _T_249) node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(_T_250, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_250, UInt<1>(0h1), "") : assert_2 node _T_254 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_255 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_256 = and(_T_254, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<14>(0h2000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<13>(0h1000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<17>(0h10000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<18>(0h2f000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<17>(0h10000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<27>(0h4000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<19>(0h40000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_262, _T_267) node _T_314 = or(_T_313, _T_272) node _T_315 = or(_T_314, _T_277) node _T_316 = or(_T_315, _T_282) node _T_317 = or(_T_316, _T_287) node _T_318 = or(_T_317, _T_292) node _T_319 = or(_T_318, _T_297) node _T_320 = or(_T_319, _T_302) node _T_321 = or(_T_320, _T_307) node _T_322 = or(_T_321, _T_312) node _T_323 = and(_T_257, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = and(UInt<1>(0h0), _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_325, UInt<1>(0h1), "") : assert_3 node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(source_ok, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_332 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_332, UInt<1>(0h1), "") : assert_5 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(is_aligned, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_339 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_339, UInt<1>(0h1), "") : assert_7 node _T_343 = not(io.in.a.bits.mask) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_344, UInt<1>(0h1), "") : assert_8 node _T_348 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_348, UInt<1>(0h1), "") : assert_9 node _T_352 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_352 : node _T_353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_354 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_355 = and(_T_353, _T_354) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_356 = shr(io.in.a.bits.source, 5) node _T_357 = eq(_T_356, UInt<1>(0h0)) node _T_358 = leq(UInt<1>(0h0), uncommonBits_16) node _T_359 = and(_T_357, _T_358) node _T_360 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_361 = and(_T_359, _T_360) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_362 = shr(io.in.a.bits.source, 5) node _T_363 = eq(_T_362, UInt<1>(0h1)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_367 = and(_T_365, _T_366) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_368 = shr(io.in.a.bits.source, 5) node _T_369 = eq(_T_368, UInt<2>(0h2)) node _T_370 = leq(UInt<1>(0h0), uncommonBits_18) node _T_371 = and(_T_369, _T_370) node _T_372 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<2>(0h3)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_19) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_380 = shr(io.in.a.bits.source, 5) node _T_381 = eq(_T_380, UInt<3>(0h4)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_20) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_386 = shr(io.in.a.bits.source, 5) node _T_387 = eq(_T_386, UInt<3>(0h5)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_21) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_392 = shr(io.in.a.bits.source, 5) node _T_393 = eq(_T_392, UInt<3>(0h6)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_22) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_398 = shr(io.in.a.bits.source, 5) node _T_399 = eq(_T_398, UInt<3>(0h7)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_23) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(_T_361, _T_367) node _T_405 = or(_T_404, _T_373) node _T_406 = or(_T_405, _T_379) node _T_407 = or(_T_406, _T_385) node _T_408 = or(_T_407, _T_391) node _T_409 = or(_T_408, _T_397) node _T_410 = or(_T_409, _T_403) node _T_411 = and(_T_355, _T_410) node _T_412 = or(UInt<1>(0h0), _T_411) node _T_413 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<19>(0h40000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = or(_T_418, _T_423) node _T_460 = or(_T_459, _T_428) node _T_461 = or(_T_460, _T_433) node _T_462 = or(_T_461, _T_438) node _T_463 = or(_T_462, _T_443) node _T_464 = or(_T_463, _T_448) node _T_465 = or(_T_464, _T_453) node _T_466 = or(_T_465, _T_458) node _T_467 = and(_T_413, _T_466) node _T_468 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_469 = or(UInt<1>(0h0), _T_468) node _T_470 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<17>(0h10000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<29>(0h10000000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = or(_T_474, _T_479) node _T_481 = and(_T_469, _T_480) node _T_482 = or(UInt<1>(0h0), _T_467) node _T_483 = or(_T_482, _T_481) node _T_484 = and(_T_412, _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_484, UInt<1>(0h1), "") : assert_10 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<14>(0h2000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<17>(0h10000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<19>(0h40000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<29>(0h10000000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = or(_T_496, _T_501) node _T_548 = or(_T_547, _T_506) node _T_549 = or(_T_548, _T_511) node _T_550 = or(_T_549, _T_516) node _T_551 = or(_T_550, _T_521) node _T_552 = or(_T_551, _T_526) node _T_553 = or(_T_552, _T_531) node _T_554 = or(_T_553, _T_536) node _T_555 = or(_T_554, _T_541) node _T_556 = or(_T_555, _T_546) node _T_557 = and(_T_491, _T_556) node _T_558 = or(UInt<1>(0h0), _T_557) node _T_559 = and(UInt<1>(0h0), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_559, UInt<1>(0h1), "") : assert_11 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_566 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_566, UInt<1>(0h1), "") : assert_13 node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(is_aligned, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_573 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_573, UInt<1>(0h1), "") : assert_15 node _T_577 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_577, UInt<1>(0h1), "") : assert_16 node _T_581 = not(io.in.a.bits.mask) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_582, UInt<1>(0h1), "") : assert_17 node _T_586 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_586, UInt<1>(0h1), "") : assert_18 node _T_590 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_590 : node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0) node _T_594 = shr(io.in.a.bits.source, 5) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_24) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_24, UInt<5>(0h1f)) node _T_599 = and(_T_597, _T_598) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0) node _T_600 = shr(io.in.a.bits.source, 5) node _T_601 = eq(_T_600, UInt<1>(0h1)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_25) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_25, UInt<5>(0h1f)) node _T_605 = and(_T_603, _T_604) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0) node _T_606 = shr(io.in.a.bits.source, 5) node _T_607 = eq(_T_606, UInt<2>(0h2)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_26) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_26, UInt<5>(0h1f)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0) node _T_612 = shr(io.in.a.bits.source, 5) node _T_613 = eq(_T_612, UInt<2>(0h3)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_27) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_27, UInt<5>(0h1f)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_618 = shr(io.in.a.bits.source, 5) node _T_619 = eq(_T_618, UInt<3>(0h4)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_28) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_624 = shr(io.in.a.bits.source, 5) node _T_625 = eq(_T_624, UInt<3>(0h5)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_29) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_630 = shr(io.in.a.bits.source, 5) node _T_631 = eq(_T_630, UInt<3>(0h6)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_30) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_636 = shr(io.in.a.bits.source, 5) node _T_637 = eq(_T_636, UInt<3>(0h7)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_31) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_641 = and(_T_639, _T_640) node _T_642 = or(_T_599, _T_605) node _T_643 = or(_T_642, _T_611) node _T_644 = or(_T_643, _T_617) node _T_645 = or(_T_644, _T_623) node _T_646 = or(_T_645, _T_629) node _T_647 = or(_T_646, _T_635) node _T_648 = or(_T_647, _T_641) node _T_649 = and(_T_593, _T_648) node _T_650 = or(UInt<1>(0h0), _T_649) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_650, UInt<1>(0h1), "") : assert_19 node _T_654 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_655 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_656 = and(_T_654, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = and(_T_657, _T_662) node _T_664 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_665 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_666 = and(_T_664, _T_665) node _T_667 = or(UInt<1>(0h0), _T_666) node _T_668 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<14>(0h2000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<18>(0h2f000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<17>(0h10000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<13>(0h1000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<27>(0h4000000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<19>(0h40000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<29>(0h10000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = or(_T_672, _T_677) node _T_719 = or(_T_718, _T_682) node _T_720 = or(_T_719, _T_687) node _T_721 = or(_T_720, _T_692) node _T_722 = or(_T_721, _T_697) node _T_723 = or(_T_722, _T_702) node _T_724 = or(_T_723, _T_707) node _T_725 = or(_T_724, _T_712) node _T_726 = or(_T_725, _T_717) node _T_727 = and(_T_667, _T_726) node _T_728 = or(UInt<1>(0h0), _T_663) node _T_729 = or(_T_728, _T_727) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_729, UInt<1>(0h1), "") : assert_20 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(source_ok, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(is_aligned, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_739 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_739, UInt<1>(0h1), "") : assert_23 node _T_743 = eq(io.in.a.bits.mask, mask) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_743, UInt<1>(0h1), "") : assert_24 node _T_747 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_747, UInt<1>(0h1), "") : assert_25 node _T_751 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_751 : node _T_752 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_753 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_755 = shr(io.in.a.bits.source, 5) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_32) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_761 = shr(io.in.a.bits.source, 5) node _T_762 = eq(_T_761, UInt<1>(0h1)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_33) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_767 = shr(io.in.a.bits.source, 5) node _T_768 = eq(_T_767, UInt<2>(0h2)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_34) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_773 = shr(io.in.a.bits.source, 5) node _T_774 = eq(_T_773, UInt<2>(0h3)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_35) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_779 = shr(io.in.a.bits.source, 5) node _T_780 = eq(_T_779, UInt<3>(0h4)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_36) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_785 = shr(io.in.a.bits.source, 5) node _T_786 = eq(_T_785, UInt<3>(0h5)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_37) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_790 = and(_T_788, _T_789) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_791 = shr(io.in.a.bits.source, 5) node _T_792 = eq(_T_791, UInt<3>(0h6)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_38) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_797 = shr(io.in.a.bits.source, 5) node _T_798 = eq(_T_797, UInt<3>(0h7)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_39) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_802 = and(_T_800, _T_801) node _T_803 = or(_T_760, _T_766) node _T_804 = or(_T_803, _T_772) node _T_805 = or(_T_804, _T_778) node _T_806 = or(_T_805, _T_784) node _T_807 = or(_T_806, _T_790) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_802) node _T_810 = and(_T_754, _T_809) node _T_811 = or(UInt<1>(0h0), _T_810) node _T_812 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_813 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_814 = and(_T_812, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_817 = cvt(_T_816) node _T_818 = and(_T_817, asSInt(UInt<13>(0h1000))) node _T_819 = asSInt(_T_818) node _T_820 = eq(_T_819, asSInt(UInt<1>(0h0))) node _T_821 = and(_T_815, _T_820) node _T_822 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_823 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_824 = and(_T_822, _T_823) node _T_825 = or(UInt<1>(0h0), _T_824) node _T_826 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<14>(0h2000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_832 = cvt(_T_831) node _T_833 = and(_T_832, asSInt(UInt<18>(0h2f000))) node _T_834 = asSInt(_T_833) node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0))) node _T_836 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_837 = cvt(_T_836) node _T_838 = and(_T_837, asSInt(UInt<17>(0h10000))) node _T_839 = asSInt(_T_838) node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0))) node _T_841 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_842 = cvt(_T_841) node _T_843 = and(_T_842, asSInt(UInt<13>(0h1000))) node _T_844 = asSInt(_T_843) node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0))) node _T_846 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<27>(0h4000000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<19>(0h40000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<29>(0h10000000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = or(_T_830, _T_835) node _T_872 = or(_T_871, _T_840) node _T_873 = or(_T_872, _T_845) node _T_874 = or(_T_873, _T_850) node _T_875 = or(_T_874, _T_855) node _T_876 = or(_T_875, _T_860) node _T_877 = or(_T_876, _T_865) node _T_878 = or(_T_877, _T_870) node _T_879 = and(_T_825, _T_878) node _T_880 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_881 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = and(_T_880, _T_885) node _T_887 = or(UInt<1>(0h0), _T_821) node _T_888 = or(_T_887, _T_879) node _T_889 = or(_T_888, _T_886) node _T_890 = and(_T_811, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_890, UInt<1>(0h1), "") : assert_26 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_900 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_900, UInt<1>(0h1), "") : assert_29 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_904, UInt<1>(0h1), "") : assert_30 node _T_908 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_908 : node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_911 = and(_T_909, _T_910) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_912 = shr(io.in.a.bits.source, 5) node _T_913 = eq(_T_912, UInt<1>(0h0)) node _T_914 = leq(UInt<1>(0h0), uncommonBits_40) node _T_915 = and(_T_913, _T_914) node _T_916 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_917 = and(_T_915, _T_916) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_918 = shr(io.in.a.bits.source, 5) node _T_919 = eq(_T_918, UInt<1>(0h1)) node _T_920 = leq(UInt<1>(0h0), uncommonBits_41) node _T_921 = and(_T_919, _T_920) node _T_922 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_923 = and(_T_921, _T_922) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_924 = shr(io.in.a.bits.source, 5) node _T_925 = eq(_T_924, UInt<2>(0h2)) node _T_926 = leq(UInt<1>(0h0), uncommonBits_42) node _T_927 = and(_T_925, _T_926) node _T_928 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_929 = and(_T_927, _T_928) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_930 = shr(io.in.a.bits.source, 5) node _T_931 = eq(_T_930, UInt<2>(0h3)) node _T_932 = leq(UInt<1>(0h0), uncommonBits_43) node _T_933 = and(_T_931, _T_932) node _T_934 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_935 = and(_T_933, _T_934) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_936 = shr(io.in.a.bits.source, 5) node _T_937 = eq(_T_936, UInt<3>(0h4)) node _T_938 = leq(UInt<1>(0h0), uncommonBits_44) node _T_939 = and(_T_937, _T_938) node _T_940 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_941 = and(_T_939, _T_940) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_942 = shr(io.in.a.bits.source, 5) node _T_943 = eq(_T_942, UInt<3>(0h5)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_45) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_948 = shr(io.in.a.bits.source, 5) node _T_949 = eq(_T_948, UInt<3>(0h6)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_46) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_954 = shr(io.in.a.bits.source, 5) node _T_955 = eq(_T_954, UInt<3>(0h7)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_47) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_959 = and(_T_957, _T_958) node _T_960 = or(_T_917, _T_923) node _T_961 = or(_T_960, _T_929) node _T_962 = or(_T_961, _T_935) node _T_963 = or(_T_962, _T_941) node _T_964 = or(_T_963, _T_947) node _T_965 = or(_T_964, _T_953) node _T_966 = or(_T_965, _T_959) node _T_967 = and(_T_911, _T_966) node _T_968 = or(UInt<1>(0h0), _T_967) node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_971 = and(_T_969, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<13>(0h1000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = and(_T_972, _T_977) node _T_979 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_980 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_981 = and(_T_979, _T_980) node _T_982 = or(UInt<1>(0h0), _T_981) node _T_983 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<14>(0h2000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_989 = cvt(_T_988) node _T_990 = and(_T_989, asSInt(UInt<18>(0h2f000))) node _T_991 = asSInt(_T_990) node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0))) node _T_993 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_994 = cvt(_T_993) node _T_995 = and(_T_994, asSInt(UInt<17>(0h10000))) node _T_996 = asSInt(_T_995) node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0))) node _T_998 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1004 = cvt(_T_1003) node _T_1005 = and(_T_1004, asSInt(UInt<17>(0h10000))) node _T_1006 = asSInt(_T_1005) node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0))) node _T_1008 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<27>(0h4000000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<19>(0h40000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<29>(0h10000000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = or(_T_987, _T_992) node _T_1029 = or(_T_1028, _T_997) node _T_1030 = or(_T_1029, _T_1002) node _T_1031 = or(_T_1030, _T_1007) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1017) node _T_1034 = or(_T_1033, _T_1022) node _T_1035 = or(_T_1034, _T_1027) node _T_1036 = and(_T_982, _T_1035) node _T_1037 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1038 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<17>(0h10000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = and(_T_1037, _T_1042) node _T_1044 = or(UInt<1>(0h0), _T_978) node _T_1045 = or(_T_1044, _T_1036) node _T_1046 = or(_T_1045, _T_1043) node _T_1047 = and(_T_968, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_31 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1057 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_34 node _T_1061 = not(mask) node _T_1062 = and(io.in.a.bits.mask, _T_1061) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_35 node _T_1067 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1067 : node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1070 = and(_T_1068, _T_1069) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 4, 0) node _T_1071 = shr(io.in.a.bits.source, 5) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1074 = and(_T_1072, _T_1073) node _T_1075 = leq(uncommonBits_48, UInt<5>(0h1f)) node _T_1076 = and(_T_1074, _T_1075) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 4, 0) node _T_1077 = shr(io.in.a.bits.source, 5) node _T_1078 = eq(_T_1077, UInt<1>(0h1)) node _T_1079 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = leq(uncommonBits_49, UInt<5>(0h1f)) node _T_1082 = and(_T_1080, _T_1081) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_1083 = shr(io.in.a.bits.source, 5) node _T_1084 = eq(_T_1083, UInt<2>(0h2)) node _T_1085 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_1088 = and(_T_1086, _T_1087) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_1089 = shr(io.in.a.bits.source, 5) node _T_1090 = eq(_T_1089, UInt<2>(0h3)) node _T_1091 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_1094 = and(_T_1092, _T_1093) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_1095 = shr(io.in.a.bits.source, 5) node _T_1096 = eq(_T_1095, UInt<3>(0h4)) node _T_1097 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1098 = and(_T_1096, _T_1097) node _T_1099 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_1100 = and(_T_1098, _T_1099) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_1101 = shr(io.in.a.bits.source, 5) node _T_1102 = eq(_T_1101, UInt<3>(0h5)) node _T_1103 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1104 = and(_T_1102, _T_1103) node _T_1105 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_1106 = and(_T_1104, _T_1105) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_1107 = shr(io.in.a.bits.source, 5) node _T_1108 = eq(_T_1107, UInt<3>(0h6)) node _T_1109 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_1112 = and(_T_1110, _T_1111) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_1113 = shr(io.in.a.bits.source, 5) node _T_1114 = eq(_T_1113, UInt<3>(0h7)) node _T_1115 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = or(_T_1076, _T_1082) node _T_1120 = or(_T_1119, _T_1088) node _T_1121 = or(_T_1120, _T_1094) node _T_1122 = or(_T_1121, _T_1100) node _T_1123 = or(_T_1122, _T_1106) node _T_1124 = or(_T_1123, _T_1112) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = and(_T_1070, _T_1125) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1129 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = or(UInt<1>(0h0), _T_1130) node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<14>(0h2000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<17>(0h10000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<27>(0h4000000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<19>(0h40000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<29>(0h10000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = or(_T_1136, _T_1141) node _T_1183 = or(_T_1182, _T_1146) node _T_1184 = or(_T_1183, _T_1151) node _T_1185 = or(_T_1184, _T_1156) node _T_1186 = or(_T_1185, _T_1161) node _T_1187 = or(_T_1186, _T_1166) node _T_1188 = or(_T_1187, _T_1171) node _T_1189 = or(_T_1188, _T_1176) node _T_1190 = or(_T_1189, _T_1181) node _T_1191 = and(_T_1131, _T_1190) node _T_1192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<17>(0h10000))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = and(_T_1192, _T_1197) node _T_1199 = or(UInt<1>(0h0), _T_1191) node _T_1200 = or(_T_1199, _T_1198) node _T_1201 = and(_T_1127, _T_1200) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_36 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(source_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(is_aligned, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1211 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_39 node _T_1215 = eq(io.in.a.bits.mask, mask) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_40 node _T_1219 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1219 : node _T_1220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1222 = and(_T_1220, _T_1221) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_1223 = shr(io.in.a.bits.source, 5) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) node _T_1225 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_1228 = and(_T_1226, _T_1227) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_1229 = shr(io.in.a.bits.source, 5) node _T_1230 = eq(_T_1229, UInt<1>(0h1)) node _T_1231 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1232 = and(_T_1230, _T_1231) node _T_1233 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_1234 = and(_T_1232, _T_1233) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_1235 = shr(io.in.a.bits.source, 5) node _T_1236 = eq(_T_1235, UInt<2>(0h2)) node _T_1237 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1238 = and(_T_1236, _T_1237) node _T_1239 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_1240 = and(_T_1238, _T_1239) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_1241 = shr(io.in.a.bits.source, 5) node _T_1242 = eq(_T_1241, UInt<2>(0h3)) node _T_1243 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1244 = and(_T_1242, _T_1243) node _T_1245 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_1246 = and(_T_1244, _T_1245) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_1247 = shr(io.in.a.bits.source, 5) node _T_1248 = eq(_T_1247, UInt<3>(0h4)) node _T_1249 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1250 = and(_T_1248, _T_1249) node _T_1251 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_1252 = and(_T_1250, _T_1251) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_1253 = shr(io.in.a.bits.source, 5) node _T_1254 = eq(_T_1253, UInt<3>(0h5)) node _T_1255 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1256 = and(_T_1254, _T_1255) node _T_1257 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_1258 = and(_T_1256, _T_1257) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_1259 = shr(io.in.a.bits.source, 5) node _T_1260 = eq(_T_1259, UInt<3>(0h6)) node _T_1261 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_1264 = and(_T_1262, _T_1263) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_1265 = shr(io.in.a.bits.source, 5) node _T_1266 = eq(_T_1265, UInt<3>(0h7)) node _T_1267 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = or(_T_1228, _T_1234) node _T_1272 = or(_T_1271, _T_1240) node _T_1273 = or(_T_1272, _T_1246) node _T_1274 = or(_T_1273, _T_1252) node _T_1275 = or(_T_1274, _T_1258) node _T_1276 = or(_T_1275, _T_1264) node _T_1277 = or(_T_1276, _T_1270) node _T_1278 = and(_T_1222, _T_1277) node _T_1279 = or(UInt<1>(0h0), _T_1278) node _T_1280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1281 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1285 = cvt(_T_1284) node _T_1286 = and(_T_1285, asSInt(UInt<14>(0h2000))) node _T_1287 = asSInt(_T_1286) node _T_1288 = eq(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1290 = cvt(_T_1289) node _T_1291 = and(_T_1290, asSInt(UInt<13>(0h1000))) node _T_1292 = asSInt(_T_1291) node _T_1293 = eq(_T_1292, asSInt(UInt<1>(0h0))) node _T_1294 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<18>(0h2f000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1300 = cvt(_T_1299) node _T_1301 = and(_T_1300, asSInt(UInt<17>(0h10000))) node _T_1302 = asSInt(_T_1301) node _T_1303 = eq(_T_1302, asSInt(UInt<1>(0h0))) node _T_1304 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1305 = cvt(_T_1304) node _T_1306 = and(_T_1305, asSInt(UInt<13>(0h1000))) node _T_1307 = asSInt(_T_1306) node _T_1308 = eq(_T_1307, asSInt(UInt<1>(0h0))) node _T_1309 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1310 = cvt(_T_1309) node _T_1311 = and(_T_1310, asSInt(UInt<17>(0h10000))) node _T_1312 = asSInt(_T_1311) node _T_1313 = eq(_T_1312, asSInt(UInt<1>(0h0))) node _T_1314 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<27>(0h4000000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<19>(0h40000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<29>(0h10000000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = or(_T_1288, _T_1293) node _T_1335 = or(_T_1334, _T_1298) node _T_1336 = or(_T_1335, _T_1303) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1313) node _T_1339 = or(_T_1338, _T_1318) node _T_1340 = or(_T_1339, _T_1323) node _T_1341 = or(_T_1340, _T_1328) node _T_1342 = or(_T_1341, _T_1333) node _T_1343 = and(_T_1283, _T_1342) node _T_1344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<17>(0h10000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = and(_T_1344, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1343) node _T_1352 = or(_T_1351, _T_1350) node _T_1353 = and(_T_1279, _T_1352) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_41 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1363 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_44 node _T_1367 = eq(io.in.a.bits.mask, mask) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_45 node _T_1371 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1371 : node _T_1372 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1373 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1374 = and(_T_1372, _T_1373) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_1375 = shr(io.in.a.bits.source, 5) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_1381 = shr(io.in.a.bits.source, 5) node _T_1382 = eq(_T_1381, UInt<1>(0h1)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_1386 = and(_T_1384, _T_1385) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_1387 = shr(io.in.a.bits.source, 5) node _T_1388 = eq(_T_1387, UInt<2>(0h2)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_1393 = shr(io.in.a.bits.source, 5) node _T_1394 = eq(_T_1393, UInt<2>(0h3)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_1399 = shr(io.in.a.bits.source, 5) node _T_1400 = eq(_T_1399, UInt<3>(0h4)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_1405 = shr(io.in.a.bits.source, 5) node _T_1406 = eq(_T_1405, UInt<3>(0h5)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1410 = and(_T_1408, _T_1409) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1411 = shr(io.in.a.bits.source, 5) node _T_1412 = eq(_T_1411, UInt<3>(0h6)) node _T_1413 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1416 = and(_T_1414, _T_1415) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1417 = shr(io.in.a.bits.source, 5) node _T_1418 = eq(_T_1417, UInt<3>(0h7)) node _T_1419 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1422 = and(_T_1420, _T_1421) node _T_1423 = or(_T_1380, _T_1386) node _T_1424 = or(_T_1423, _T_1392) node _T_1425 = or(_T_1424, _T_1398) node _T_1426 = or(_T_1425, _T_1404) node _T_1427 = or(_T_1426, _T_1410) node _T_1428 = or(_T_1427, _T_1416) node _T_1429 = or(_T_1428, _T_1422) node _T_1430 = and(_T_1374, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1433 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = and(_T_1435, _T_1440) node _T_1442 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1443 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<14>(0h2000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<17>(0h10000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1454 = cvt(_T_1453) node _T_1455 = and(_T_1454, asSInt(UInt<18>(0h2f000))) node _T_1456 = asSInt(_T_1455) node _T_1457 = eq(_T_1456, asSInt(UInt<1>(0h0))) node _T_1458 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1459 = cvt(_T_1458) node _T_1460 = and(_T_1459, asSInt(UInt<17>(0h10000))) node _T_1461 = asSInt(_T_1460) node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) node _T_1463 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1464 = cvt(_T_1463) node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) node _T_1466 = asSInt(_T_1465) node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) node _T_1468 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1469 = cvt(_T_1468) node _T_1470 = and(_T_1469, asSInt(UInt<27>(0h4000000))) node _T_1471 = asSInt(_T_1470) node _T_1472 = eq(_T_1471, asSInt(UInt<1>(0h0))) node _T_1473 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1474 = cvt(_T_1473) node _T_1475 = and(_T_1474, asSInt(UInt<13>(0h1000))) node _T_1476 = asSInt(_T_1475) node _T_1477 = eq(_T_1476, asSInt(UInt<1>(0h0))) node _T_1478 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1479 = cvt(_T_1478) node _T_1480 = and(_T_1479, asSInt(UInt<19>(0h40000))) node _T_1481 = asSInt(_T_1480) node _T_1482 = eq(_T_1481, asSInt(UInt<1>(0h0))) node _T_1483 = or(_T_1447, _T_1452) node _T_1484 = or(_T_1483, _T_1457) node _T_1485 = or(_T_1484, _T_1462) node _T_1486 = or(_T_1485, _T_1467) node _T_1487 = or(_T_1486, _T_1472) node _T_1488 = or(_T_1487, _T_1477) node _T_1489 = or(_T_1488, _T_1482) node _T_1490 = and(_T_1442, _T_1489) node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h10000))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h10000000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1441) node _T_1508 = or(_T_1507, _T_1490) node _T_1509 = or(_T_1508, _T_1506) node _T_1510 = and(_T_1431, _T_1509) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_46 node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(source_ok, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(is_aligned, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1520 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_49 node _T_1524 = eq(io.in.a.bits.mask, mask) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_50 node _T_1528 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1532 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 5) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<1>(0h0)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 5) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<1>(0h1)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 5) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<2>(0h2)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_72 = shr(io.in.d.bits.source, 5) node _source_ok_T_73 = eq(_source_ok_T_72, UInt<2>(0h3)) node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 4, 0) node _source_ok_T_78 = shr(io.in.d.bits.source, 5) node _source_ok_T_79 = eq(_source_ok_T_78, UInt<3>(0h4)) node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80) node _source_ok_T_82 = leq(source_ok_uncommonBits_12, UInt<5>(0h1f)) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 4, 0) node _source_ok_T_84 = shr(io.in.d.bits.source, 5) node _source_ok_T_85 = eq(_source_ok_T_84, UInt<3>(0h5)) node _source_ok_T_86 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86) node _source_ok_T_88 = leq(source_ok_uncommonBits_13, UInt<5>(0h1f)) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_90 = shr(io.in.d.bits.source, 5) node _source_ok_T_91 = eq(_source_ok_T_90, UInt<3>(0h6)) node _source_ok_T_92 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92) node _source_ok_T_94 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_96 = shr(io.in.d.bits.source, 5) node _source_ok_T_97 = eq(_source_ok_T_96, UInt<3>(0h7)) node _source_ok_T_98 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_99 = and(_source_ok_T_97, _source_ok_T_98) node _source_ok_T_100 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_101 = and(_source_ok_T_99, _source_ok_T_100) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_59 connect _source_ok_WIRE_1[1], _source_ok_T_65 connect _source_ok_WIRE_1[2], _source_ok_T_71 connect _source_ok_WIRE_1[3], _source_ok_T_77 connect _source_ok_WIRE_1[4], _source_ok_T_83 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_95 connect _source_ok_WIRE_1[7], _source_ok_T_101 node _source_ok_T_102 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[2]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[3]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[4]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[5]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1536 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1536 : node _T_1537 = asUInt(reset) node _T_1538 = eq(_T_1537, UInt<1>(0h0)) when _T_1538 : node _T_1539 = eq(source_ok_1, UInt<1>(0h0)) when _T_1539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1540 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(_T_1540, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1540, UInt<1>(0h1), "") : assert_54 node _T_1544 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_55 node _T_1548 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_56 node _T_1552 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_57 node _T_1556 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1556 : node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(source_ok_1, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(sink_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1563 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_60 node _T_1567 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_61 node _T_1571 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_62 node _T_1575 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_63 node _T_1579 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1580 = or(UInt<1>(0h1), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_64 node _T_1584 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1584 : node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(source_ok_1, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(sink_ok, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1591 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_67 node _T_1595 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_68 node _T_1599 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_69 node _T_1603 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1604 = or(_T_1603, io.in.d.bits.corrupt) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_70 node _T_1608 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1609 = or(UInt<1>(0h1), _T_1608) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_71 node _T_1613 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1613 : node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(source_ok_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1617 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_73 node _T_1621 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_74 node _T_1625 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1626 = or(UInt<1>(0h1), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_75 node _T_1630 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1630 : node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(source_ok_1, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1634 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(_T_1634, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1634, UInt<1>(0h1), "") : assert_77 node _T_1638 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1639 = or(_T_1638, io.in.d.bits.corrupt) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_78 node _T_1643 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1644 = or(UInt<1>(0h1), _T_1643) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_79 node _T_1648 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1648 : node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(source_ok_1, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1652 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(_T_1652, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1652, UInt<1>(0h1), "") : assert_81 node _T_1656 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_82 node _T_1660 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1661 = or(UInt<1>(0h1), _T_1660) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1665 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1669 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1673 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1677 = eq(a_first, UInt<1>(0h0)) node _T_1678 = and(io.in.a.valid, _T_1677) when _T_1678 : node _T_1679 = eq(io.in.a.bits.opcode, opcode) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_87 node _T_1683 = eq(io.in.a.bits.param, param) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_88 node _T_1687 = eq(io.in.a.bits.size, size) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_89 node _T_1691 = eq(io.in.a.bits.source, source) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_90 node _T_1695 = eq(io.in.a.bits.address, address) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_91 node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first) when _T_1700 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1701 = eq(d_first, UInt<1>(0h0)) node _T_1702 = and(io.in.d.valid, _T_1701) when _T_1702 : node _T_1703 = eq(io.in.d.bits.opcode, opcode_1) node _T_1704 = asUInt(reset) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) when _T_1705 : node _T_1706 = eq(_T_1703, UInt<1>(0h0)) when _T_1706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1703, UInt<1>(0h1), "") : assert_92 node _T_1707 = eq(io.in.d.bits.param, param_1) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_93 node _T_1711 = eq(io.in.d.bits.size, size_1) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_94 node _T_1715 = eq(io.in.d.bits.source, source_1) node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(_T_1715, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1715, UInt<1>(0h1), "") : assert_95 node _T_1719 = eq(io.in.d.bits.sink, sink) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_96 node _T_1723 = eq(io.in.d.bits.denied, denied) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_97 node _T_1727 = and(io.in.d.ready, io.in.d.valid) node _T_1728 = and(_T_1727, d_first) when _T_1728 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes : UInt<2048>, clock, reset, UInt<2048>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<256> connect a_set, UInt<256>(0h0) wire a_set_wo_ready : UInt<256> connect a_set_wo_ready, UInt<256>(0h0) wire a_opcodes_set : UInt<1024> connect a_opcodes_set, UInt<1024>(0h0) wire a_sizes_set : UInt<2048> connect a_sizes_set, UInt<2048>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1729 = and(io.in.a.valid, a_first_1) node _T_1730 = and(_T_1729, UInt<1>(0h1)) when _T_1730 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1731 = and(io.in.a.ready, io.in.a.valid) node _T_1732 = and(_T_1731, a_first_1) node _T_1733 = and(_T_1732, UInt<1>(0h1)) when _T_1733 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1734 = dshr(inflight, io.in.a.bits.source) node _T_1735 = bits(_T_1734, 0, 0) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<256> connect d_clr, UInt<256>(0h0) wire d_clr_wo_ready : UInt<256> connect d_clr_wo_ready, UInt<256>(0h0) wire d_opcodes_clr : UInt<1024> connect d_opcodes_clr, UInt<1024>(0h0) wire d_sizes_clr : UInt<2048> connect d_sizes_clr, UInt<2048>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1740 = and(io.in.d.valid, d_first_1) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = eq(d_release_ack, UInt<1>(0h0)) node _T_1743 = and(_T_1741, _T_1742) when _T_1743 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1744 = and(io.in.d.ready, io.in.d.valid) node _T_1745 = and(_T_1744, d_first_1) node _T_1746 = and(_T_1745, UInt<1>(0h1)) node _T_1747 = eq(d_release_ack, UInt<1>(0h0)) node _T_1748 = and(_T_1746, _T_1747) when _T_1748 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1749 = and(io.in.d.valid, d_first_1) node _T_1750 = and(_T_1749, UInt<1>(0h1)) node _T_1751 = eq(d_release_ack, UInt<1>(0h0)) node _T_1752 = and(_T_1750, _T_1751) when _T_1752 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1753 = dshr(inflight, io.in.d.bits.source) node _T_1754 = bits(_T_1753, 0, 0) node _T_1755 = or(_T_1754, same_cycle_resp) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1759 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1760 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = asUInt(reset) node _T_1763 = eq(_T_1762, UInt<1>(0h0)) when _T_1763 : node _T_1764 = eq(_T_1761, UInt<1>(0h0)) when _T_1764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1761, UInt<1>(0h1), "") : assert_100 node _T_1765 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_101 else : node _T_1769 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1770 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_102 node _T_1775 = eq(io.in.d.bits.size, a_size_lookup) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_103 node _T_1779 = and(io.in.d.valid, d_first_1) node _T_1780 = and(_T_1779, a_first_1) node _T_1781 = and(_T_1780, io.in.a.valid) node _T_1782 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1783 = and(_T_1781, _T_1782) node _T_1784 = eq(d_release_ack, UInt<1>(0h0)) node _T_1785 = and(_T_1783, _T_1784) when _T_1785 : node _T_1786 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1787 = or(_T_1786, io.in.a.ready) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_104 node _T_1791 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1792 = orr(a_set_wo_ready) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = or(_T_1791, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_10 node _T_1798 = orr(inflight) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1801 = or(_T_1799, _T_1800) node _T_1802 = lt(watchdog, plusarg_reader.out) node _T_1803 = or(_T_1801, _T_1802) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1807 = and(io.in.a.ready, io.in.a.valid) node _T_1808 = and(io.in.d.ready, io.in.d.valid) node _T_1809 = or(_T_1807, _T_1808) when _T_1809 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<256>, clock, reset, UInt<256>(0h0) regreset inflight_opcodes_1 : UInt<1024>, clock, reset, UInt<1024>(0h0) regreset inflight_sizes_1 : UInt<2048>, clock, reset, UInt<2048>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<256> connect c_set, UInt<256>(0h0) wire c_set_wo_ready : UInt<256> connect c_set_wo_ready, UInt<256>(0h0) wire c_opcodes_set : UInt<1024> connect c_opcodes_set, UInt<1024>(0h0) wire c_sizes_set : UInt<2048> connect c_sizes_set, UInt<2048>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1810 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1811 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1812 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1813 = and(_T_1811, _T_1812) node _T_1814 = and(_T_1810, _T_1813) when _T_1814 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1815 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1816 = and(_T_1815, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1817 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1818 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = and(_T_1816, _T_1819) when _T_1820 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1821 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1822 = bits(_T_1821, 0, 0) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(_T_1823, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1823, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<256> connect d_clr_1, UInt<256>(0h0) wire d_clr_wo_ready_1 : UInt<256> connect d_clr_wo_ready_1, UInt<256>(0h0) wire d_opcodes_clr_1 : UInt<1024> connect d_opcodes_clr_1, UInt<1024>(0h0) wire d_sizes_clr_1 : UInt<2048> connect d_sizes_clr_1, UInt<2048>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1827 = and(io.in.d.valid, d_first_2) node _T_1828 = and(_T_1827, UInt<1>(0h1)) node _T_1829 = and(_T_1828, d_release_ack_1) when _T_1829 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1830 = and(io.in.d.ready, io.in.d.valid) node _T_1831 = and(_T_1830, d_first_2) node _T_1832 = and(_T_1831, UInt<1>(0h1)) node _T_1833 = and(_T_1832, d_release_ack_1) when _T_1833 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1834 = and(io.in.d.valid, d_first_2) node _T_1835 = and(_T_1834, UInt<1>(0h1)) node _T_1836 = and(_T_1835, d_release_ack_1) when _T_1836 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1837 = dshr(inflight_1, io.in.d.bits.source) node _T_1838 = bits(_T_1837, 0, 0) node _T_1839 = or(_T_1838, same_cycle_resp_1) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1843 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_109 else : node _T_1847 = eq(io.in.d.bits.size, c_size_lookup) node _T_1848 = asUInt(reset) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) when _T_1849 : node _T_1850 = eq(_T_1847, UInt<1>(0h0)) when _T_1850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1847, UInt<1>(0h1), "") : assert_110 node _T_1851 = and(io.in.d.valid, d_first_2) node _T_1852 = and(_T_1851, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1853 = and(_T_1852, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1854 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1855 = and(_T_1853, _T_1854) node _T_1856 = and(_T_1855, d_release_ack_1) node _T_1857 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1858 = and(_T_1856, _T_1857) when _T_1858 : node _T_1859 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1860 = or(_T_1859, _WIRE_23.ready) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_111 node _T_1864 = orr(c_set_wo_ready) when _T_1864 : node _T_1865 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_11 node _T_1869 = orr(inflight_1) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) node _T_1871 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1872 = or(_T_1870, _T_1871) node _T_1873 = lt(watchdog_1, plusarg_reader_1.out) node _T_1874 = or(_T_1872, _T_1873) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:96)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1878 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1879 = and(io.in.d.ready, io.in.d.valid) node _T_1880 = or(_T_1878, _T_1879) when _T_1880 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [255:0] inflight; // @[Monitor.scala:614:27] reg [1023:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2047:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [255:0] inflight_1; // @[Monitor.scala:726:35] reg [2047:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Directory_5 : input clock : Clock input reset : Reset output io : { flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, flip read : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>}}, result : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, ready : UInt<1>} smem cc_dir : UInt<13>[16] [2048] inst write_q of Queue1_DirectoryWrite_5 connect write_q.clock, clock connect write_q.reset, reset connect write_q.io.enq.valid, io.write.valid connect write_q.io.enq.bits.data.tag, io.write.bits.data.tag connect write_q.io.enq.bits.data.clients, io.write.bits.data.clients connect write_q.io.enq.bits.data.state, io.write.bits.data.state connect write_q.io.enq.bits.data.dirty, io.write.bits.data.dirty connect write_q.io.enq.bits.way, io.write.bits.way connect write_q.io.enq.bits.set, io.write.bits.set connect io.write.ready, write_q.io.enq.ready regreset wipeCount : UInt<12>, clock, reset, UInt<12>(0h0) regreset wipeOff : UInt<1>, clock, reset, UInt<1>(0h1) connect wipeOff, UInt<1>(0h0) node wipeDone = bits(wipeCount, 11, 11) node wipeSet = bits(wipeCount, 10, 0) connect io.ready, wipeDone node _T = eq(wipeDone, UInt<1>(0h0)) node _T_1 = eq(wipeOff, UInt<1>(0h0)) node _T_2 = and(_T, _T_1) when _T_2 : node _wipeCount_T = add(wipeCount, UInt<1>(0h1)) node _wipeCount_T_1 = tail(_wipeCount_T, 1) connect wipeCount, _wipeCount_T_1 node _T_3 = eq(io.read.valid, UInt<1>(0h0)) node _T_4 = or(wipeDone, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:86 assert (wipeDone || !io.read.valid)\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _wen_T = eq(wipeDone, UInt<1>(0h0)) node _wen_T_1 = eq(wipeOff, UInt<1>(0h0)) node _wen_T_2 = and(_wen_T, _wen_T_1) node wen = or(_wen_T_2, write_q.io.deq.valid) node _T_8 = eq(io.read.valid, UInt<1>(0h0)) node _T_9 = or(_T_8, wipeDone) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:91 assert (!io.read.valid || wipeDone)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 node _q_io_deq_ready_T = eq(io.read.valid, UInt<1>(0h0)) connect write_q.io.deq.ready, _q_io_deq_ready_T node _T_13 = eq(io.read.valid, UInt<1>(0h0)) node _T_14 = and(_T_13, wen) when _T_14 : node _T_15 = mux(wipeDone, write_q.io.deq.bits.set, wipeSet) node lo = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_16 = cat(hi, lo) node _T_17 = mux(wipeDone, _T_16, UInt<1>(0h0)) node lo_1 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_1 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_18 = cat(hi_1, lo_1) node _T_19 = mux(wipeDone, _T_18, UInt<1>(0h0)) node lo_2 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_2 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_20 = cat(hi_2, lo_2) node _T_21 = mux(wipeDone, _T_20, UInt<1>(0h0)) node lo_3 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_3 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_22 = cat(hi_3, lo_3) node _T_23 = mux(wipeDone, _T_22, UInt<1>(0h0)) node lo_4 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_4 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_24 = cat(hi_4, lo_4) node _T_25 = mux(wipeDone, _T_24, UInt<1>(0h0)) node lo_5 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_5 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_26 = cat(hi_5, lo_5) node _T_27 = mux(wipeDone, _T_26, UInt<1>(0h0)) node lo_6 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_6 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_28 = cat(hi_6, lo_6) node _T_29 = mux(wipeDone, _T_28, UInt<1>(0h0)) node lo_7 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_7 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_30 = cat(hi_7, lo_7) node _T_31 = mux(wipeDone, _T_30, UInt<1>(0h0)) node lo_8 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_8 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_32 = cat(hi_8, lo_8) node _T_33 = mux(wipeDone, _T_32, UInt<1>(0h0)) node lo_9 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_9 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_34 = cat(hi_9, lo_9) node _T_35 = mux(wipeDone, _T_34, UInt<1>(0h0)) node lo_10 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_10 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_36 = cat(hi_10, lo_10) node _T_37 = mux(wipeDone, _T_36, UInt<1>(0h0)) node lo_11 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_11 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_38 = cat(hi_11, lo_11) node _T_39 = mux(wipeDone, _T_38, UInt<1>(0h0)) node lo_12 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_12 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_40 = cat(hi_12, lo_12) node _T_41 = mux(wipeDone, _T_40, UInt<1>(0h0)) node lo_13 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_13 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_42 = cat(hi_13, lo_13) node _T_43 = mux(wipeDone, _T_42, UInt<1>(0h0)) node lo_14 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_14 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_44 = cat(hi_14, lo_14) node _T_45 = mux(wipeDone, _T_44, UInt<1>(0h0)) node lo_15 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_15 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_46 = cat(hi_15, lo_15) node _T_47 = mux(wipeDone, _T_46, UInt<1>(0h0)) wire _WIRE : UInt<13>[16] connect _WIRE[0], _T_17 connect _WIRE[1], _T_19 connect _WIRE[2], _T_21 connect _WIRE[3], _T_23 connect _WIRE[4], _T_25 connect _WIRE[5], _T_27 connect _WIRE[6], _T_29 connect _WIRE[7], _T_31 connect _WIRE[8], _T_33 connect _WIRE[9], _T_35 connect _WIRE[10], _T_37 connect _WIRE[11], _T_39 connect _WIRE[12], _T_41 connect _WIRE[13], _T_43 connect _WIRE[14], _T_45 connect _WIRE[15], _T_47 node shiftAmount = bits(write_q.io.deq.bits.way, 3, 0) node _T_48 = dshl(UInt<1>(0h1), shiftAmount) node _T_49 = bits(_T_48, 15, 0) node _T_50 = bits(_T_49, 0, 0) node _T_51 = bits(_T_49, 1, 1) node _T_52 = bits(_T_49, 2, 2) node _T_53 = bits(_T_49, 3, 3) node _T_54 = bits(_T_49, 4, 4) node _T_55 = bits(_T_49, 5, 5) node _T_56 = bits(_T_49, 6, 6) node _T_57 = bits(_T_49, 7, 7) node _T_58 = bits(_T_49, 8, 8) node _T_59 = bits(_T_49, 9, 9) node _T_60 = bits(_T_49, 10, 10) node _T_61 = bits(_T_49, 11, 11) node _T_62 = bits(_T_49, 12, 12) node _T_63 = bits(_T_49, 13, 13) node _T_64 = bits(_T_49, 14, 14) node _T_65 = bits(_T_49, 15, 15) node _T_66 = eq(wipeDone, UInt<1>(0h0)) node _T_67 = or(_T_50, _T_66) node _T_68 = eq(wipeDone, UInt<1>(0h0)) node _T_69 = or(_T_51, _T_68) node _T_70 = eq(wipeDone, UInt<1>(0h0)) node _T_71 = or(_T_52, _T_70) node _T_72 = eq(wipeDone, UInt<1>(0h0)) node _T_73 = or(_T_53, _T_72) node _T_74 = eq(wipeDone, UInt<1>(0h0)) node _T_75 = or(_T_54, _T_74) node _T_76 = eq(wipeDone, UInt<1>(0h0)) node _T_77 = or(_T_55, _T_76) node _T_78 = eq(wipeDone, UInt<1>(0h0)) node _T_79 = or(_T_56, _T_78) node _T_80 = eq(wipeDone, UInt<1>(0h0)) node _T_81 = or(_T_57, _T_80) node _T_82 = eq(wipeDone, UInt<1>(0h0)) node _T_83 = or(_T_58, _T_82) node _T_84 = eq(wipeDone, UInt<1>(0h0)) node _T_85 = or(_T_59, _T_84) node _T_86 = eq(wipeDone, UInt<1>(0h0)) node _T_87 = or(_T_60, _T_86) node _T_88 = eq(wipeDone, UInt<1>(0h0)) node _T_89 = or(_T_61, _T_88) node _T_90 = eq(wipeDone, UInt<1>(0h0)) node _T_91 = or(_T_62, _T_90) node _T_92 = eq(wipeDone, UInt<1>(0h0)) node _T_93 = or(_T_63, _T_92) node _T_94 = eq(wipeDone, UInt<1>(0h0)) node _T_95 = or(_T_64, _T_94) node _T_96 = eq(wipeDone, UInt<1>(0h0)) node _T_97 = or(_T_65, _T_96) write mport MPORT = cc_dir[_T_15], clock when _T_67 : connect MPORT[0], _WIRE[0] when _T_69 : connect MPORT[1], _WIRE[1] when _T_71 : connect MPORT[2], _WIRE[2] when _T_73 : connect MPORT[3], _WIRE[3] when _T_75 : connect MPORT[4], _WIRE[4] when _T_77 : connect MPORT[5], _WIRE[5] when _T_79 : connect MPORT[6], _WIRE[6] when _T_81 : connect MPORT[7], _WIRE[7] when _T_83 : connect MPORT[8], _WIRE[8] when _T_85 : connect MPORT[9], _WIRE[9] when _T_87 : connect MPORT[10], _WIRE[10] when _T_89 : connect MPORT[11], _WIRE[11] when _T_91 : connect MPORT[12], _WIRE[12] when _T_93 : connect MPORT[13], _WIRE[13] when _T_95 : connect MPORT[14], _WIRE[14] when _T_97 : connect MPORT[15], _WIRE[15] regreset ren1 : UInt<1>, clock, reset, UInt<1>(0h0) connect ren1, ren1 connect ren1, io.read.valid node _bypass_T = and(ren1, write_q.io.deq.valid) wire _regout_WIRE : UInt<11> invalidate _regout_WIRE when io.read.valid : connect _regout_WIRE, io.read.bits.set read mport regout = cc_dir[_regout_WIRE], clock reg tag : UInt<9>, clock when io.read.valid : connect tag, io.read.bits.tag reg set : UInt<11>, clock when io.read.valid : connect set, io.read.bits.set inst victimLFSR_prng of MaxPeriodFibonacciLFSR_5 connect victimLFSR_prng.clock, clock connect victimLFSR_prng.reset, reset connect victimLFSR_prng.io.seed.valid, UInt<1>(0h0) invalidate victimLFSR_prng.io.seed.bits[0] invalidate victimLFSR_prng.io.seed.bits[1] invalidate victimLFSR_prng.io.seed.bits[2] invalidate victimLFSR_prng.io.seed.bits[3] invalidate victimLFSR_prng.io.seed.bits[4] invalidate victimLFSR_prng.io.seed.bits[5] invalidate victimLFSR_prng.io.seed.bits[6] invalidate victimLFSR_prng.io.seed.bits[7] invalidate victimLFSR_prng.io.seed.bits[8] invalidate victimLFSR_prng.io.seed.bits[9] invalidate victimLFSR_prng.io.seed.bits[10] invalidate victimLFSR_prng.io.seed.bits[11] invalidate victimLFSR_prng.io.seed.bits[12] invalidate victimLFSR_prng.io.seed.bits[13] invalidate victimLFSR_prng.io.seed.bits[14] invalidate victimLFSR_prng.io.seed.bits[15] connect victimLFSR_prng.io.increment, io.read.valid node victimLFSR_lo_lo_lo = cat(victimLFSR_prng.io.out[1], victimLFSR_prng.io.out[0]) node victimLFSR_lo_lo_hi = cat(victimLFSR_prng.io.out[3], victimLFSR_prng.io.out[2]) node victimLFSR_lo_lo = cat(victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo) node victimLFSR_lo_hi_lo = cat(victimLFSR_prng.io.out[5], victimLFSR_prng.io.out[4]) node victimLFSR_lo_hi_hi = cat(victimLFSR_prng.io.out[7], victimLFSR_prng.io.out[6]) node victimLFSR_lo_hi = cat(victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo) node victimLFSR_lo = cat(victimLFSR_lo_hi, victimLFSR_lo_lo) node victimLFSR_hi_lo_lo = cat(victimLFSR_prng.io.out[9], victimLFSR_prng.io.out[8]) node victimLFSR_hi_lo_hi = cat(victimLFSR_prng.io.out[11], victimLFSR_prng.io.out[10]) node victimLFSR_hi_lo = cat(victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo) node victimLFSR_hi_hi_lo = cat(victimLFSR_prng.io.out[13], victimLFSR_prng.io.out[12]) node victimLFSR_hi_hi_hi = cat(victimLFSR_prng.io.out[15], victimLFSR_prng.io.out[14]) node victimLFSR_hi_hi = cat(victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo) node victimLFSR_hi = cat(victimLFSR_hi_hi, victimLFSR_hi_lo) node _victimLFSR_T = cat(victimLFSR_hi, victimLFSR_lo) node victimLFSR = bits(_victimLFSR_T, 9, 0) node _victimLTE_T = leq(UInt<1>(0h0), victimLFSR) node _victimLTE_T_1 = leq(UInt<7>(0h40), victimLFSR) node _victimLTE_T_2 = leq(UInt<8>(0h80), victimLFSR) node _victimLTE_T_3 = leq(UInt<8>(0hc0), victimLFSR) node _victimLTE_T_4 = leq(UInt<9>(0h100), victimLFSR) node _victimLTE_T_5 = leq(UInt<9>(0h140), victimLFSR) node _victimLTE_T_6 = leq(UInt<9>(0h180), victimLFSR) node _victimLTE_T_7 = leq(UInt<9>(0h1c0), victimLFSR) node _victimLTE_T_8 = leq(UInt<10>(0h200), victimLFSR) node _victimLTE_T_9 = leq(UInt<10>(0h240), victimLFSR) node _victimLTE_T_10 = leq(UInt<10>(0h280), victimLFSR) node _victimLTE_T_11 = leq(UInt<10>(0h2c0), victimLFSR) node _victimLTE_T_12 = leq(UInt<10>(0h300), victimLFSR) node _victimLTE_T_13 = leq(UInt<10>(0h340), victimLFSR) node _victimLTE_T_14 = leq(UInt<10>(0h380), victimLFSR) node _victimLTE_T_15 = leq(UInt<10>(0h3c0), victimLFSR) node victimLTE_lo_lo_lo = cat(_victimLTE_T_1, _victimLTE_T) node victimLTE_lo_lo_hi = cat(_victimLTE_T_3, _victimLTE_T_2) node victimLTE_lo_lo = cat(victimLTE_lo_lo_hi, victimLTE_lo_lo_lo) node victimLTE_lo_hi_lo = cat(_victimLTE_T_5, _victimLTE_T_4) node victimLTE_lo_hi_hi = cat(_victimLTE_T_7, _victimLTE_T_6) node victimLTE_lo_hi = cat(victimLTE_lo_hi_hi, victimLTE_lo_hi_lo) node victimLTE_lo = cat(victimLTE_lo_hi, victimLTE_lo_lo) node victimLTE_hi_lo_lo = cat(_victimLTE_T_9, _victimLTE_T_8) node victimLTE_hi_lo_hi = cat(_victimLTE_T_11, _victimLTE_T_10) node victimLTE_hi_lo = cat(victimLTE_hi_lo_hi, victimLTE_hi_lo_lo) node victimLTE_hi_hi_lo = cat(_victimLTE_T_13, _victimLTE_T_12) node victimLTE_hi_hi_hi = cat(_victimLTE_T_15, _victimLTE_T_14) node victimLTE_hi_hi = cat(victimLTE_hi_hi_hi, victimLTE_hi_hi_lo) node victimLTE_hi = cat(victimLTE_hi_hi, victimLTE_hi_lo) node victimLTE = cat(victimLTE_hi, victimLTE_lo) node _victimSimp_T = bits(victimLTE, 15, 1) node victimSimp_hi = cat(UInt<1>(0h0), _victimSimp_T) node victimSimp = cat(victimSimp_hi, UInt<1>(0h1)) node _victimWayOH_T = bits(victimSimp, 15, 0) node _victimWayOH_T_1 = shr(victimSimp, 1) node _victimWayOH_T_2 = not(_victimWayOH_T_1) node victimWayOH = and(_victimWayOH_T, _victimWayOH_T_2) node victimWay_hi = bits(victimWayOH, 15, 8) node victimWay_lo = bits(victimWayOH, 7, 0) node _victimWay_T = orr(victimWay_hi) node _victimWay_T_1 = or(victimWay_hi, victimWay_lo) node victimWay_hi_1 = bits(_victimWay_T_1, 7, 4) node victimWay_lo_1 = bits(_victimWay_T_1, 3, 0) node _victimWay_T_2 = orr(victimWay_hi_1) node _victimWay_T_3 = or(victimWay_hi_1, victimWay_lo_1) node victimWay_hi_2 = bits(_victimWay_T_3, 3, 2) node victimWay_lo_2 = bits(_victimWay_T_3, 1, 0) node _victimWay_T_4 = orr(victimWay_hi_2) node _victimWay_T_5 = or(victimWay_hi_2, victimWay_lo_2) node _victimWay_T_6 = bits(_victimWay_T_5, 1, 1) node _victimWay_T_7 = cat(_victimWay_T_4, _victimWay_T_6) node _victimWay_T_8 = cat(_victimWay_T_2, _victimWay_T_7) node victimWay = cat(_victimWay_T, _victimWay_T_8) node _T_98 = eq(ren1, UInt<1>(0h0)) node _T_99 = bits(victimLTE, 0, 0) node _T_100 = eq(_T_99, UInt<1>(0h1)) node _T_101 = or(_T_98, _T_100) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:121 assert (!ren2 || victimLTE(0) === 1.U)\n") : printf_2 assert(clock, _T_101, UInt<1>(0h1), "") : assert_2 node _T_105 = eq(ren1, UInt<1>(0h0)) node _T_106 = shr(victimSimp, 1) node _T_107 = not(victimSimp) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = or(_T_105, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:122 assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone\n") : printf_3 assert(clock, _T_110, UInt<1>(0h1), "") : assert_3 node _T_114 = eq(ren1, UInt<1>(0h0)) node _T_115 = bits(victimWayOH, 0, 0) node _T_116 = bits(victimWayOH, 1, 1) node _T_117 = bits(victimWayOH, 2, 2) node _T_118 = bits(victimWayOH, 3, 3) node _T_119 = bits(victimWayOH, 4, 4) node _T_120 = bits(victimWayOH, 5, 5) node _T_121 = bits(victimWayOH, 6, 6) node _T_122 = bits(victimWayOH, 7, 7) node _T_123 = bits(victimWayOH, 8, 8) node _T_124 = bits(victimWayOH, 9, 9) node _T_125 = bits(victimWayOH, 10, 10) node _T_126 = bits(victimWayOH, 11, 11) node _T_127 = bits(victimWayOH, 12, 12) node _T_128 = bits(victimWayOH, 13, 13) node _T_129 = bits(victimWayOH, 14, 14) node _T_130 = bits(victimWayOH, 15, 15) node _T_131 = add(_T_115, _T_116) node _T_132 = bits(_T_131, 1, 0) node _T_133 = add(_T_117, _T_118) node _T_134 = bits(_T_133, 1, 0) node _T_135 = add(_T_132, _T_134) node _T_136 = bits(_T_135, 2, 0) node _T_137 = add(_T_119, _T_120) node _T_138 = bits(_T_137, 1, 0) node _T_139 = add(_T_121, _T_122) node _T_140 = bits(_T_139, 1, 0) node _T_141 = add(_T_138, _T_140) node _T_142 = bits(_T_141, 2, 0) node _T_143 = add(_T_136, _T_142) node _T_144 = bits(_T_143, 3, 0) node _T_145 = add(_T_123, _T_124) node _T_146 = bits(_T_145, 1, 0) node _T_147 = add(_T_125, _T_126) node _T_148 = bits(_T_147, 1, 0) node _T_149 = add(_T_146, _T_148) node _T_150 = bits(_T_149, 2, 0) node _T_151 = add(_T_127, _T_128) node _T_152 = bits(_T_151, 1, 0) node _T_153 = add(_T_129, _T_130) node _T_154 = bits(_T_153, 1, 0) node _T_155 = add(_T_152, _T_154) node _T_156 = bits(_T_155, 2, 0) node _T_157 = add(_T_150, _T_156) node _T_158 = bits(_T_157, 3, 0) node _T_159 = add(_T_144, _T_158) node _T_160 = bits(_T_159, 4, 0) node _T_161 = eq(_T_160, UInt<1>(0h1)) node _T_162 = or(_T_114, _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:123 assert (!ren2 || PopCount(victimWayOH) === 1.U)\n") : printf_4 assert(clock, _T_162, UInt<1>(0h1), "") : assert_4 node _setQuash_T = eq(write_q.io.deq.bits.set, set) node setQuash = and(write_q.io.deq.valid, _setQuash_T) node tagMatch = eq(write_q.io.deq.bits.data.tag, tag) node wayMatch = eq(write_q.io.deq.bits.way, victimWay) wire ways_0 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE : UInt<13> connect _ways_WIRE, regout[0] node _ways_T = bits(_ways_WIRE, 8, 0) connect ways_0.tag, _ways_T node _ways_T_1 = bits(_ways_WIRE, 9, 9) connect ways_0.clients, _ways_T_1 node _ways_T_2 = bits(_ways_WIRE, 11, 10) connect ways_0.state, _ways_T_2 node _ways_T_3 = bits(_ways_WIRE, 12, 12) connect ways_0.dirty, _ways_T_3 wire ways_1 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_1 : UInt<13> connect _ways_WIRE_1, regout[1] node _ways_T_4 = bits(_ways_WIRE_1, 8, 0) connect ways_1.tag, _ways_T_4 node _ways_T_5 = bits(_ways_WIRE_1, 9, 9) connect ways_1.clients, _ways_T_5 node _ways_T_6 = bits(_ways_WIRE_1, 11, 10) connect ways_1.state, _ways_T_6 node _ways_T_7 = bits(_ways_WIRE_1, 12, 12) connect ways_1.dirty, _ways_T_7 wire ways_2 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_2 : UInt<13> connect _ways_WIRE_2, regout[2] node _ways_T_8 = bits(_ways_WIRE_2, 8, 0) connect ways_2.tag, _ways_T_8 node _ways_T_9 = bits(_ways_WIRE_2, 9, 9) connect ways_2.clients, _ways_T_9 node _ways_T_10 = bits(_ways_WIRE_2, 11, 10) connect ways_2.state, _ways_T_10 node _ways_T_11 = bits(_ways_WIRE_2, 12, 12) connect ways_2.dirty, _ways_T_11 wire ways_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_3 : UInt<13> connect _ways_WIRE_3, regout[3] node _ways_T_12 = bits(_ways_WIRE_3, 8, 0) connect ways_3.tag, _ways_T_12 node _ways_T_13 = bits(_ways_WIRE_3, 9, 9) connect ways_3.clients, _ways_T_13 node _ways_T_14 = bits(_ways_WIRE_3, 11, 10) connect ways_3.state, _ways_T_14 node _ways_T_15 = bits(_ways_WIRE_3, 12, 12) connect ways_3.dirty, _ways_T_15 wire ways_4 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_4 : UInt<13> connect _ways_WIRE_4, regout[4] node _ways_T_16 = bits(_ways_WIRE_4, 8, 0) connect ways_4.tag, _ways_T_16 node _ways_T_17 = bits(_ways_WIRE_4, 9, 9) connect ways_4.clients, _ways_T_17 node _ways_T_18 = bits(_ways_WIRE_4, 11, 10) connect ways_4.state, _ways_T_18 node _ways_T_19 = bits(_ways_WIRE_4, 12, 12) connect ways_4.dirty, _ways_T_19 wire ways_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_5 : UInt<13> connect _ways_WIRE_5, regout[5] node _ways_T_20 = bits(_ways_WIRE_5, 8, 0) connect ways_5.tag, _ways_T_20 node _ways_T_21 = bits(_ways_WIRE_5, 9, 9) connect ways_5.clients, _ways_T_21 node _ways_T_22 = bits(_ways_WIRE_5, 11, 10) connect ways_5.state, _ways_T_22 node _ways_T_23 = bits(_ways_WIRE_5, 12, 12) connect ways_5.dirty, _ways_T_23 wire ways_6 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_6 : UInt<13> connect _ways_WIRE_6, regout[6] node _ways_T_24 = bits(_ways_WIRE_6, 8, 0) connect ways_6.tag, _ways_T_24 node _ways_T_25 = bits(_ways_WIRE_6, 9, 9) connect ways_6.clients, _ways_T_25 node _ways_T_26 = bits(_ways_WIRE_6, 11, 10) connect ways_6.state, _ways_T_26 node _ways_T_27 = bits(_ways_WIRE_6, 12, 12) connect ways_6.dirty, _ways_T_27 wire ways_7 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_7 : UInt<13> connect _ways_WIRE_7, regout[7] node _ways_T_28 = bits(_ways_WIRE_7, 8, 0) connect ways_7.tag, _ways_T_28 node _ways_T_29 = bits(_ways_WIRE_7, 9, 9) connect ways_7.clients, _ways_T_29 node _ways_T_30 = bits(_ways_WIRE_7, 11, 10) connect ways_7.state, _ways_T_30 node _ways_T_31 = bits(_ways_WIRE_7, 12, 12) connect ways_7.dirty, _ways_T_31 wire ways_8 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_8 : UInt<13> connect _ways_WIRE_8, regout[8] node _ways_T_32 = bits(_ways_WIRE_8, 8, 0) connect ways_8.tag, _ways_T_32 node _ways_T_33 = bits(_ways_WIRE_8, 9, 9) connect ways_8.clients, _ways_T_33 node _ways_T_34 = bits(_ways_WIRE_8, 11, 10) connect ways_8.state, _ways_T_34 node _ways_T_35 = bits(_ways_WIRE_8, 12, 12) connect ways_8.dirty, _ways_T_35 wire ways_9 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_9 : UInt<13> connect _ways_WIRE_9, regout[9] node _ways_T_36 = bits(_ways_WIRE_9, 8, 0) connect ways_9.tag, _ways_T_36 node _ways_T_37 = bits(_ways_WIRE_9, 9, 9) connect ways_9.clients, _ways_T_37 node _ways_T_38 = bits(_ways_WIRE_9, 11, 10) connect ways_9.state, _ways_T_38 node _ways_T_39 = bits(_ways_WIRE_9, 12, 12) connect ways_9.dirty, _ways_T_39 wire ways_10 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_10 : UInt<13> connect _ways_WIRE_10, regout[10] node _ways_T_40 = bits(_ways_WIRE_10, 8, 0) connect ways_10.tag, _ways_T_40 node _ways_T_41 = bits(_ways_WIRE_10, 9, 9) connect ways_10.clients, _ways_T_41 node _ways_T_42 = bits(_ways_WIRE_10, 11, 10) connect ways_10.state, _ways_T_42 node _ways_T_43 = bits(_ways_WIRE_10, 12, 12) connect ways_10.dirty, _ways_T_43 wire ways_11 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_11 : UInt<13> connect _ways_WIRE_11, regout[11] node _ways_T_44 = bits(_ways_WIRE_11, 8, 0) connect ways_11.tag, _ways_T_44 node _ways_T_45 = bits(_ways_WIRE_11, 9, 9) connect ways_11.clients, _ways_T_45 node _ways_T_46 = bits(_ways_WIRE_11, 11, 10) connect ways_11.state, _ways_T_46 node _ways_T_47 = bits(_ways_WIRE_11, 12, 12) connect ways_11.dirty, _ways_T_47 wire ways_12 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_12 : UInt<13> connect _ways_WIRE_12, regout[12] node _ways_T_48 = bits(_ways_WIRE_12, 8, 0) connect ways_12.tag, _ways_T_48 node _ways_T_49 = bits(_ways_WIRE_12, 9, 9) connect ways_12.clients, _ways_T_49 node _ways_T_50 = bits(_ways_WIRE_12, 11, 10) connect ways_12.state, _ways_T_50 node _ways_T_51 = bits(_ways_WIRE_12, 12, 12) connect ways_12.dirty, _ways_T_51 wire ways_13 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_13 : UInt<13> connect _ways_WIRE_13, regout[13] node _ways_T_52 = bits(_ways_WIRE_13, 8, 0) connect ways_13.tag, _ways_T_52 node _ways_T_53 = bits(_ways_WIRE_13, 9, 9) connect ways_13.clients, _ways_T_53 node _ways_T_54 = bits(_ways_WIRE_13, 11, 10) connect ways_13.state, _ways_T_54 node _ways_T_55 = bits(_ways_WIRE_13, 12, 12) connect ways_13.dirty, _ways_T_55 wire ways_14 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_14 : UInt<13> connect _ways_WIRE_14, regout[14] node _ways_T_56 = bits(_ways_WIRE_14, 8, 0) connect ways_14.tag, _ways_T_56 node _ways_T_57 = bits(_ways_WIRE_14, 9, 9) connect ways_14.clients, _ways_T_57 node _ways_T_58 = bits(_ways_WIRE_14, 11, 10) connect ways_14.state, _ways_T_58 node _ways_T_59 = bits(_ways_WIRE_14, 12, 12) connect ways_14.dirty, _ways_T_59 wire ways_15 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_15 : UInt<13> connect _ways_WIRE_15, regout[15] node _ways_T_60 = bits(_ways_WIRE_15, 8, 0) connect ways_15.tag, _ways_T_60 node _ways_T_61 = bits(_ways_WIRE_15, 9, 9) connect ways_15.clients, _ways_T_61 node _ways_T_62 = bits(_ways_WIRE_15, 11, 10) connect ways_15.state, _ways_T_62 node _ways_T_63 = bits(_ways_WIRE_15, 12, 12) connect ways_15.dirty, _ways_T_63 node _hits_T = eq(ways_0.tag, tag) node _hits_T_1 = neq(ways_0.state, UInt<2>(0h0)) node _hits_T_2 = and(_hits_T, _hits_T_1) node _hits_T_3 = eq(setQuash, UInt<1>(0h0)) node _hits_T_4 = neq(UInt<1>(0h0), write_q.io.deq.bits.way) node _hits_T_5 = or(_hits_T_3, _hits_T_4) node _hits_T_6 = and(_hits_T_2, _hits_T_5) node _hits_T_7 = eq(ways_1.tag, tag) node _hits_T_8 = neq(ways_1.state, UInt<2>(0h0)) node _hits_T_9 = and(_hits_T_7, _hits_T_8) node _hits_T_10 = eq(setQuash, UInt<1>(0h0)) node _hits_T_11 = neq(UInt<1>(0h1), write_q.io.deq.bits.way) node _hits_T_12 = or(_hits_T_10, _hits_T_11) node _hits_T_13 = and(_hits_T_9, _hits_T_12) node _hits_T_14 = eq(ways_2.tag, tag) node _hits_T_15 = neq(ways_2.state, UInt<2>(0h0)) node _hits_T_16 = and(_hits_T_14, _hits_T_15) node _hits_T_17 = eq(setQuash, UInt<1>(0h0)) node _hits_T_18 = neq(UInt<2>(0h2), write_q.io.deq.bits.way) node _hits_T_19 = or(_hits_T_17, _hits_T_18) node _hits_T_20 = and(_hits_T_16, _hits_T_19) node _hits_T_21 = eq(ways_3.tag, tag) node _hits_T_22 = neq(ways_3.state, UInt<2>(0h0)) node _hits_T_23 = and(_hits_T_21, _hits_T_22) node _hits_T_24 = eq(setQuash, UInt<1>(0h0)) node _hits_T_25 = neq(UInt<2>(0h3), write_q.io.deq.bits.way) node _hits_T_26 = or(_hits_T_24, _hits_T_25) node _hits_T_27 = and(_hits_T_23, _hits_T_26) node _hits_T_28 = eq(ways_4.tag, tag) node _hits_T_29 = neq(ways_4.state, UInt<2>(0h0)) node _hits_T_30 = and(_hits_T_28, _hits_T_29) node _hits_T_31 = eq(setQuash, UInt<1>(0h0)) node _hits_T_32 = neq(UInt<3>(0h4), write_q.io.deq.bits.way) node _hits_T_33 = or(_hits_T_31, _hits_T_32) node _hits_T_34 = and(_hits_T_30, _hits_T_33) node _hits_T_35 = eq(ways_5.tag, tag) node _hits_T_36 = neq(ways_5.state, UInt<2>(0h0)) node _hits_T_37 = and(_hits_T_35, _hits_T_36) node _hits_T_38 = eq(setQuash, UInt<1>(0h0)) node _hits_T_39 = neq(UInt<3>(0h5), write_q.io.deq.bits.way) node _hits_T_40 = or(_hits_T_38, _hits_T_39) node _hits_T_41 = and(_hits_T_37, _hits_T_40) node _hits_T_42 = eq(ways_6.tag, tag) node _hits_T_43 = neq(ways_6.state, UInt<2>(0h0)) node _hits_T_44 = and(_hits_T_42, _hits_T_43) node _hits_T_45 = eq(setQuash, UInt<1>(0h0)) node _hits_T_46 = neq(UInt<3>(0h6), write_q.io.deq.bits.way) node _hits_T_47 = or(_hits_T_45, _hits_T_46) node _hits_T_48 = and(_hits_T_44, _hits_T_47) node _hits_T_49 = eq(ways_7.tag, tag) node _hits_T_50 = neq(ways_7.state, UInt<2>(0h0)) node _hits_T_51 = and(_hits_T_49, _hits_T_50) node _hits_T_52 = eq(setQuash, UInt<1>(0h0)) node _hits_T_53 = neq(UInt<3>(0h7), write_q.io.deq.bits.way) node _hits_T_54 = or(_hits_T_52, _hits_T_53) node _hits_T_55 = and(_hits_T_51, _hits_T_54) node _hits_T_56 = eq(ways_8.tag, tag) node _hits_T_57 = neq(ways_8.state, UInt<2>(0h0)) node _hits_T_58 = and(_hits_T_56, _hits_T_57) node _hits_T_59 = eq(setQuash, UInt<1>(0h0)) node _hits_T_60 = neq(UInt<4>(0h8), write_q.io.deq.bits.way) node _hits_T_61 = or(_hits_T_59, _hits_T_60) node _hits_T_62 = and(_hits_T_58, _hits_T_61) node _hits_T_63 = eq(ways_9.tag, tag) node _hits_T_64 = neq(ways_9.state, UInt<2>(0h0)) node _hits_T_65 = and(_hits_T_63, _hits_T_64) node _hits_T_66 = eq(setQuash, UInt<1>(0h0)) node _hits_T_67 = neq(UInt<4>(0h9), write_q.io.deq.bits.way) node _hits_T_68 = or(_hits_T_66, _hits_T_67) node _hits_T_69 = and(_hits_T_65, _hits_T_68) node _hits_T_70 = eq(ways_10.tag, tag) node _hits_T_71 = neq(ways_10.state, UInt<2>(0h0)) node _hits_T_72 = and(_hits_T_70, _hits_T_71) node _hits_T_73 = eq(setQuash, UInt<1>(0h0)) node _hits_T_74 = neq(UInt<4>(0ha), write_q.io.deq.bits.way) node _hits_T_75 = or(_hits_T_73, _hits_T_74) node _hits_T_76 = and(_hits_T_72, _hits_T_75) node _hits_T_77 = eq(ways_11.tag, tag) node _hits_T_78 = neq(ways_11.state, UInt<2>(0h0)) node _hits_T_79 = and(_hits_T_77, _hits_T_78) node _hits_T_80 = eq(setQuash, UInt<1>(0h0)) node _hits_T_81 = neq(UInt<4>(0hb), write_q.io.deq.bits.way) node _hits_T_82 = or(_hits_T_80, _hits_T_81) node _hits_T_83 = and(_hits_T_79, _hits_T_82) node _hits_T_84 = eq(ways_12.tag, tag) node _hits_T_85 = neq(ways_12.state, UInt<2>(0h0)) node _hits_T_86 = and(_hits_T_84, _hits_T_85) node _hits_T_87 = eq(setQuash, UInt<1>(0h0)) node _hits_T_88 = neq(UInt<4>(0hc), write_q.io.deq.bits.way) node _hits_T_89 = or(_hits_T_87, _hits_T_88) node _hits_T_90 = and(_hits_T_86, _hits_T_89) node _hits_T_91 = eq(ways_13.tag, tag) node _hits_T_92 = neq(ways_13.state, UInt<2>(0h0)) node _hits_T_93 = and(_hits_T_91, _hits_T_92) node _hits_T_94 = eq(setQuash, UInt<1>(0h0)) node _hits_T_95 = neq(UInt<4>(0hd), write_q.io.deq.bits.way) node _hits_T_96 = or(_hits_T_94, _hits_T_95) node _hits_T_97 = and(_hits_T_93, _hits_T_96) node _hits_T_98 = eq(ways_14.tag, tag) node _hits_T_99 = neq(ways_14.state, UInt<2>(0h0)) node _hits_T_100 = and(_hits_T_98, _hits_T_99) node _hits_T_101 = eq(setQuash, UInt<1>(0h0)) node _hits_T_102 = neq(UInt<4>(0he), write_q.io.deq.bits.way) node _hits_T_103 = or(_hits_T_101, _hits_T_102) node _hits_T_104 = and(_hits_T_100, _hits_T_103) node _hits_T_105 = eq(ways_15.tag, tag) node _hits_T_106 = neq(ways_15.state, UInt<2>(0h0)) node _hits_T_107 = and(_hits_T_105, _hits_T_106) node _hits_T_108 = eq(setQuash, UInt<1>(0h0)) node _hits_T_109 = neq(UInt<4>(0hf), write_q.io.deq.bits.way) node _hits_T_110 = or(_hits_T_108, _hits_T_109) node _hits_T_111 = and(_hits_T_107, _hits_T_110) node hits_lo_lo_lo = cat(_hits_T_13, _hits_T_6) node hits_lo_lo_hi = cat(_hits_T_27, _hits_T_20) node hits_lo_lo = cat(hits_lo_lo_hi, hits_lo_lo_lo) node hits_lo_hi_lo = cat(_hits_T_41, _hits_T_34) node hits_lo_hi_hi = cat(_hits_T_55, _hits_T_48) node hits_lo_hi = cat(hits_lo_hi_hi, hits_lo_hi_lo) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo_lo = cat(_hits_T_69, _hits_T_62) node hits_hi_lo_hi = cat(_hits_T_83, _hits_T_76) node hits_hi_lo = cat(hits_hi_lo_hi, hits_hi_lo_lo) node hits_hi_hi_lo = cat(_hits_T_97, _hits_T_90) node hits_hi_hi_hi = cat(_hits_T_111, _hits_T_104) node hits_hi_hi = cat(hits_hi_hi_hi, hits_hi_hi_lo) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node hits = cat(hits_hi, hits_lo) node hit = orr(hits) connect io.result.valid, ren1 node _view__T = bits(hits, 0, 0) node _view__T_1 = bits(hits, 1, 1) node _view__T_2 = bits(hits, 2, 2) node _view__T_3 = bits(hits, 3, 3) node _view__T_4 = bits(hits, 4, 4) node _view__T_5 = bits(hits, 5, 5) node _view__T_6 = bits(hits, 6, 6) node _view__T_7 = bits(hits, 7, 7) node _view__T_8 = bits(hits, 8, 8) node _view__T_9 = bits(hits, 9, 9) node _view__T_10 = bits(hits, 10, 10) node _view__T_11 = bits(hits, 11, 11) node _view__T_12 = bits(hits, 12, 12) node _view__T_13 = bits(hits, 13, 13) node _view__T_14 = bits(hits, 14, 14) node _view__T_15 = bits(hits, 15, 15) wire _view__WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_16 = mux(_view__T, ways_0.tag, UInt<1>(0h0)) node _view__T_17 = mux(_view__T_1, ways_1.tag, UInt<1>(0h0)) node _view__T_18 = mux(_view__T_2, ways_2.tag, UInt<1>(0h0)) node _view__T_19 = mux(_view__T_3, ways_3.tag, UInt<1>(0h0)) node _view__T_20 = mux(_view__T_4, ways_4.tag, UInt<1>(0h0)) node _view__T_21 = mux(_view__T_5, ways_5.tag, UInt<1>(0h0)) node _view__T_22 = mux(_view__T_6, ways_6.tag, UInt<1>(0h0)) node _view__T_23 = mux(_view__T_7, ways_7.tag, UInt<1>(0h0)) node _view__T_24 = mux(_view__T_8, ways_8.tag, UInt<1>(0h0)) node _view__T_25 = mux(_view__T_9, ways_9.tag, UInt<1>(0h0)) node _view__T_26 = mux(_view__T_10, ways_10.tag, UInt<1>(0h0)) node _view__T_27 = mux(_view__T_11, ways_11.tag, UInt<1>(0h0)) node _view__T_28 = mux(_view__T_12, ways_12.tag, UInt<1>(0h0)) node _view__T_29 = mux(_view__T_13, ways_13.tag, UInt<1>(0h0)) node _view__T_30 = mux(_view__T_14, ways_14.tag, UInt<1>(0h0)) node _view__T_31 = mux(_view__T_15, ways_15.tag, UInt<1>(0h0)) node _view__T_32 = or(_view__T_16, _view__T_17) node _view__T_33 = or(_view__T_32, _view__T_18) node _view__T_34 = or(_view__T_33, _view__T_19) node _view__T_35 = or(_view__T_34, _view__T_20) node _view__T_36 = or(_view__T_35, _view__T_21) node _view__T_37 = or(_view__T_36, _view__T_22) node _view__T_38 = or(_view__T_37, _view__T_23) node _view__T_39 = or(_view__T_38, _view__T_24) node _view__T_40 = or(_view__T_39, _view__T_25) node _view__T_41 = or(_view__T_40, _view__T_26) node _view__T_42 = or(_view__T_41, _view__T_27) node _view__T_43 = or(_view__T_42, _view__T_28) node _view__T_44 = or(_view__T_43, _view__T_29) node _view__T_45 = or(_view__T_44, _view__T_30) node _view__T_46 = or(_view__T_45, _view__T_31) wire _view__WIRE_1 : UInt<9> connect _view__WIRE_1, _view__T_46 connect _view__WIRE.tag, _view__WIRE_1 node _view__T_47 = mux(_view__T, ways_0.clients, UInt<1>(0h0)) node _view__T_48 = mux(_view__T_1, ways_1.clients, UInt<1>(0h0)) node _view__T_49 = mux(_view__T_2, ways_2.clients, UInt<1>(0h0)) node _view__T_50 = mux(_view__T_3, ways_3.clients, UInt<1>(0h0)) node _view__T_51 = mux(_view__T_4, ways_4.clients, UInt<1>(0h0)) node _view__T_52 = mux(_view__T_5, ways_5.clients, UInt<1>(0h0)) node _view__T_53 = mux(_view__T_6, ways_6.clients, UInt<1>(0h0)) node _view__T_54 = mux(_view__T_7, ways_7.clients, UInt<1>(0h0)) node _view__T_55 = mux(_view__T_8, ways_8.clients, UInt<1>(0h0)) node _view__T_56 = mux(_view__T_9, ways_9.clients, UInt<1>(0h0)) node _view__T_57 = mux(_view__T_10, ways_10.clients, UInt<1>(0h0)) node _view__T_58 = mux(_view__T_11, ways_11.clients, UInt<1>(0h0)) node _view__T_59 = mux(_view__T_12, ways_12.clients, UInt<1>(0h0)) node _view__T_60 = mux(_view__T_13, ways_13.clients, UInt<1>(0h0)) node _view__T_61 = mux(_view__T_14, ways_14.clients, UInt<1>(0h0)) node _view__T_62 = mux(_view__T_15, ways_15.clients, UInt<1>(0h0)) node _view__T_63 = or(_view__T_47, _view__T_48) node _view__T_64 = or(_view__T_63, _view__T_49) node _view__T_65 = or(_view__T_64, _view__T_50) node _view__T_66 = or(_view__T_65, _view__T_51) node _view__T_67 = or(_view__T_66, _view__T_52) node _view__T_68 = or(_view__T_67, _view__T_53) node _view__T_69 = or(_view__T_68, _view__T_54) node _view__T_70 = or(_view__T_69, _view__T_55) node _view__T_71 = or(_view__T_70, _view__T_56) node _view__T_72 = or(_view__T_71, _view__T_57) node _view__T_73 = or(_view__T_72, _view__T_58) node _view__T_74 = or(_view__T_73, _view__T_59) node _view__T_75 = or(_view__T_74, _view__T_60) node _view__T_76 = or(_view__T_75, _view__T_61) node _view__T_77 = or(_view__T_76, _view__T_62) wire _view__WIRE_2 : UInt<1> connect _view__WIRE_2, _view__T_77 connect _view__WIRE.clients, _view__WIRE_2 node _view__T_78 = mux(_view__T, ways_0.state, UInt<1>(0h0)) node _view__T_79 = mux(_view__T_1, ways_1.state, UInt<1>(0h0)) node _view__T_80 = mux(_view__T_2, ways_2.state, UInt<1>(0h0)) node _view__T_81 = mux(_view__T_3, ways_3.state, UInt<1>(0h0)) node _view__T_82 = mux(_view__T_4, ways_4.state, UInt<1>(0h0)) node _view__T_83 = mux(_view__T_5, ways_5.state, UInt<1>(0h0)) node _view__T_84 = mux(_view__T_6, ways_6.state, UInt<1>(0h0)) node _view__T_85 = mux(_view__T_7, ways_7.state, UInt<1>(0h0)) node _view__T_86 = mux(_view__T_8, ways_8.state, UInt<1>(0h0)) node _view__T_87 = mux(_view__T_9, ways_9.state, UInt<1>(0h0)) node _view__T_88 = mux(_view__T_10, ways_10.state, UInt<1>(0h0)) node _view__T_89 = mux(_view__T_11, ways_11.state, UInt<1>(0h0)) node _view__T_90 = mux(_view__T_12, ways_12.state, UInt<1>(0h0)) node _view__T_91 = mux(_view__T_13, ways_13.state, UInt<1>(0h0)) node _view__T_92 = mux(_view__T_14, ways_14.state, UInt<1>(0h0)) node _view__T_93 = mux(_view__T_15, ways_15.state, UInt<1>(0h0)) node _view__T_94 = or(_view__T_78, _view__T_79) node _view__T_95 = or(_view__T_94, _view__T_80) node _view__T_96 = or(_view__T_95, _view__T_81) node _view__T_97 = or(_view__T_96, _view__T_82) node _view__T_98 = or(_view__T_97, _view__T_83) node _view__T_99 = or(_view__T_98, _view__T_84) node _view__T_100 = or(_view__T_99, _view__T_85) node _view__T_101 = or(_view__T_100, _view__T_86) node _view__T_102 = or(_view__T_101, _view__T_87) node _view__T_103 = or(_view__T_102, _view__T_88) node _view__T_104 = or(_view__T_103, _view__T_89) node _view__T_105 = or(_view__T_104, _view__T_90) node _view__T_106 = or(_view__T_105, _view__T_91) node _view__T_107 = or(_view__T_106, _view__T_92) node _view__T_108 = or(_view__T_107, _view__T_93) wire _view__WIRE_3 : UInt<2> connect _view__WIRE_3, _view__T_108 connect _view__WIRE.state, _view__WIRE_3 node _view__T_109 = mux(_view__T, ways_0.dirty, UInt<1>(0h0)) node _view__T_110 = mux(_view__T_1, ways_1.dirty, UInt<1>(0h0)) node _view__T_111 = mux(_view__T_2, ways_2.dirty, UInt<1>(0h0)) node _view__T_112 = mux(_view__T_3, ways_3.dirty, UInt<1>(0h0)) node _view__T_113 = mux(_view__T_4, ways_4.dirty, UInt<1>(0h0)) node _view__T_114 = mux(_view__T_5, ways_5.dirty, UInt<1>(0h0)) node _view__T_115 = mux(_view__T_6, ways_6.dirty, UInt<1>(0h0)) node _view__T_116 = mux(_view__T_7, ways_7.dirty, UInt<1>(0h0)) node _view__T_117 = mux(_view__T_8, ways_8.dirty, UInt<1>(0h0)) node _view__T_118 = mux(_view__T_9, ways_9.dirty, UInt<1>(0h0)) node _view__T_119 = mux(_view__T_10, ways_10.dirty, UInt<1>(0h0)) node _view__T_120 = mux(_view__T_11, ways_11.dirty, UInt<1>(0h0)) node _view__T_121 = mux(_view__T_12, ways_12.dirty, UInt<1>(0h0)) node _view__T_122 = mux(_view__T_13, ways_13.dirty, UInt<1>(0h0)) node _view__T_123 = mux(_view__T_14, ways_14.dirty, UInt<1>(0h0)) node _view__T_124 = mux(_view__T_15, ways_15.dirty, UInt<1>(0h0)) node _view__T_125 = or(_view__T_109, _view__T_110) node _view__T_126 = or(_view__T_125, _view__T_111) node _view__T_127 = or(_view__T_126, _view__T_112) node _view__T_128 = or(_view__T_127, _view__T_113) node _view__T_129 = or(_view__T_128, _view__T_114) node _view__T_130 = or(_view__T_129, _view__T_115) node _view__T_131 = or(_view__T_130, _view__T_116) node _view__T_132 = or(_view__T_131, _view__T_117) node _view__T_133 = or(_view__T_132, _view__T_118) node _view__T_134 = or(_view__T_133, _view__T_119) node _view__T_135 = or(_view__T_134, _view__T_120) node _view__T_136 = or(_view__T_135, _view__T_121) node _view__T_137 = or(_view__T_136, _view__T_122) node _view__T_138 = or(_view__T_137, _view__T_123) node _view__T_139 = or(_view__T_138, _view__T_124) wire _view__WIRE_4 : UInt<1> connect _view__WIRE_4, _view__T_139 connect _view__WIRE.dirty, _view__WIRE_4 node _view__T_140 = or(tagMatch, wayMatch) node _view__T_141 = and(setQuash, _view__T_140) node _view__T_142 = bits(victimWayOH, 0, 0) node _view__T_143 = bits(victimWayOH, 1, 1) node _view__T_144 = bits(victimWayOH, 2, 2) node _view__T_145 = bits(victimWayOH, 3, 3) node _view__T_146 = bits(victimWayOH, 4, 4) node _view__T_147 = bits(victimWayOH, 5, 5) node _view__T_148 = bits(victimWayOH, 6, 6) node _view__T_149 = bits(victimWayOH, 7, 7) node _view__T_150 = bits(victimWayOH, 8, 8) node _view__T_151 = bits(victimWayOH, 9, 9) node _view__T_152 = bits(victimWayOH, 10, 10) node _view__T_153 = bits(victimWayOH, 11, 11) node _view__T_154 = bits(victimWayOH, 12, 12) node _view__T_155 = bits(victimWayOH, 13, 13) node _view__T_156 = bits(victimWayOH, 14, 14) node _view__T_157 = bits(victimWayOH, 15, 15) wire _view__WIRE_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_158 = mux(_view__T_142, ways_0.tag, UInt<1>(0h0)) node _view__T_159 = mux(_view__T_143, ways_1.tag, UInt<1>(0h0)) node _view__T_160 = mux(_view__T_144, ways_2.tag, UInt<1>(0h0)) node _view__T_161 = mux(_view__T_145, ways_3.tag, UInt<1>(0h0)) node _view__T_162 = mux(_view__T_146, ways_4.tag, UInt<1>(0h0)) node _view__T_163 = mux(_view__T_147, ways_5.tag, UInt<1>(0h0)) node _view__T_164 = mux(_view__T_148, ways_6.tag, UInt<1>(0h0)) node _view__T_165 = mux(_view__T_149, ways_7.tag, UInt<1>(0h0)) node _view__T_166 = mux(_view__T_150, ways_8.tag, UInt<1>(0h0)) node _view__T_167 = mux(_view__T_151, ways_9.tag, UInt<1>(0h0)) node _view__T_168 = mux(_view__T_152, ways_10.tag, UInt<1>(0h0)) node _view__T_169 = mux(_view__T_153, ways_11.tag, UInt<1>(0h0)) node _view__T_170 = mux(_view__T_154, ways_12.tag, UInt<1>(0h0)) node _view__T_171 = mux(_view__T_155, ways_13.tag, UInt<1>(0h0)) node _view__T_172 = mux(_view__T_156, ways_14.tag, UInt<1>(0h0)) node _view__T_173 = mux(_view__T_157, ways_15.tag, UInt<1>(0h0)) node _view__T_174 = or(_view__T_158, _view__T_159) node _view__T_175 = or(_view__T_174, _view__T_160) node _view__T_176 = or(_view__T_175, _view__T_161) node _view__T_177 = or(_view__T_176, _view__T_162) node _view__T_178 = or(_view__T_177, _view__T_163) node _view__T_179 = or(_view__T_178, _view__T_164) node _view__T_180 = or(_view__T_179, _view__T_165) node _view__T_181 = or(_view__T_180, _view__T_166) node _view__T_182 = or(_view__T_181, _view__T_167) node _view__T_183 = or(_view__T_182, _view__T_168) node _view__T_184 = or(_view__T_183, _view__T_169) node _view__T_185 = or(_view__T_184, _view__T_170) node _view__T_186 = or(_view__T_185, _view__T_171) node _view__T_187 = or(_view__T_186, _view__T_172) node _view__T_188 = or(_view__T_187, _view__T_173) wire _view__WIRE_6 : UInt<9> connect _view__WIRE_6, _view__T_188 connect _view__WIRE_5.tag, _view__WIRE_6 node _view__T_189 = mux(_view__T_142, ways_0.clients, UInt<1>(0h0)) node _view__T_190 = mux(_view__T_143, ways_1.clients, UInt<1>(0h0)) node _view__T_191 = mux(_view__T_144, ways_2.clients, UInt<1>(0h0)) node _view__T_192 = mux(_view__T_145, ways_3.clients, UInt<1>(0h0)) node _view__T_193 = mux(_view__T_146, ways_4.clients, UInt<1>(0h0)) node _view__T_194 = mux(_view__T_147, ways_5.clients, UInt<1>(0h0)) node _view__T_195 = mux(_view__T_148, ways_6.clients, UInt<1>(0h0)) node _view__T_196 = mux(_view__T_149, ways_7.clients, UInt<1>(0h0)) node _view__T_197 = mux(_view__T_150, ways_8.clients, UInt<1>(0h0)) node _view__T_198 = mux(_view__T_151, ways_9.clients, UInt<1>(0h0)) node _view__T_199 = mux(_view__T_152, ways_10.clients, UInt<1>(0h0)) node _view__T_200 = mux(_view__T_153, ways_11.clients, UInt<1>(0h0)) node _view__T_201 = mux(_view__T_154, ways_12.clients, UInt<1>(0h0)) node _view__T_202 = mux(_view__T_155, ways_13.clients, UInt<1>(0h0)) node _view__T_203 = mux(_view__T_156, ways_14.clients, UInt<1>(0h0)) node _view__T_204 = mux(_view__T_157, ways_15.clients, UInt<1>(0h0)) node _view__T_205 = or(_view__T_189, _view__T_190) node _view__T_206 = or(_view__T_205, _view__T_191) node _view__T_207 = or(_view__T_206, _view__T_192) node _view__T_208 = or(_view__T_207, _view__T_193) node _view__T_209 = or(_view__T_208, _view__T_194) node _view__T_210 = or(_view__T_209, _view__T_195) node _view__T_211 = or(_view__T_210, _view__T_196) node _view__T_212 = or(_view__T_211, _view__T_197) node _view__T_213 = or(_view__T_212, _view__T_198) node _view__T_214 = or(_view__T_213, _view__T_199) node _view__T_215 = or(_view__T_214, _view__T_200) node _view__T_216 = or(_view__T_215, _view__T_201) node _view__T_217 = or(_view__T_216, _view__T_202) node _view__T_218 = or(_view__T_217, _view__T_203) node _view__T_219 = or(_view__T_218, _view__T_204) wire _view__WIRE_7 : UInt<1> connect _view__WIRE_7, _view__T_219 connect _view__WIRE_5.clients, _view__WIRE_7 node _view__T_220 = mux(_view__T_142, ways_0.state, UInt<1>(0h0)) node _view__T_221 = mux(_view__T_143, ways_1.state, UInt<1>(0h0)) node _view__T_222 = mux(_view__T_144, ways_2.state, UInt<1>(0h0)) node _view__T_223 = mux(_view__T_145, ways_3.state, UInt<1>(0h0)) node _view__T_224 = mux(_view__T_146, ways_4.state, UInt<1>(0h0)) node _view__T_225 = mux(_view__T_147, ways_5.state, UInt<1>(0h0)) node _view__T_226 = mux(_view__T_148, ways_6.state, UInt<1>(0h0)) node _view__T_227 = mux(_view__T_149, ways_7.state, UInt<1>(0h0)) node _view__T_228 = mux(_view__T_150, ways_8.state, UInt<1>(0h0)) node _view__T_229 = mux(_view__T_151, ways_9.state, UInt<1>(0h0)) node _view__T_230 = mux(_view__T_152, ways_10.state, UInt<1>(0h0)) node _view__T_231 = mux(_view__T_153, ways_11.state, UInt<1>(0h0)) node _view__T_232 = mux(_view__T_154, ways_12.state, UInt<1>(0h0)) node _view__T_233 = mux(_view__T_155, ways_13.state, UInt<1>(0h0)) node _view__T_234 = mux(_view__T_156, ways_14.state, UInt<1>(0h0)) node _view__T_235 = mux(_view__T_157, ways_15.state, UInt<1>(0h0)) node _view__T_236 = or(_view__T_220, _view__T_221) node _view__T_237 = or(_view__T_236, _view__T_222) node _view__T_238 = or(_view__T_237, _view__T_223) node _view__T_239 = or(_view__T_238, _view__T_224) node _view__T_240 = or(_view__T_239, _view__T_225) node _view__T_241 = or(_view__T_240, _view__T_226) node _view__T_242 = or(_view__T_241, _view__T_227) node _view__T_243 = or(_view__T_242, _view__T_228) node _view__T_244 = or(_view__T_243, _view__T_229) node _view__T_245 = or(_view__T_244, _view__T_230) node _view__T_246 = or(_view__T_245, _view__T_231) node _view__T_247 = or(_view__T_246, _view__T_232) node _view__T_248 = or(_view__T_247, _view__T_233) node _view__T_249 = or(_view__T_248, _view__T_234) node _view__T_250 = or(_view__T_249, _view__T_235) wire _view__WIRE_8 : UInt<2> connect _view__WIRE_8, _view__T_250 connect _view__WIRE_5.state, _view__WIRE_8 node _view__T_251 = mux(_view__T_142, ways_0.dirty, UInt<1>(0h0)) node _view__T_252 = mux(_view__T_143, ways_1.dirty, UInt<1>(0h0)) node _view__T_253 = mux(_view__T_144, ways_2.dirty, UInt<1>(0h0)) node _view__T_254 = mux(_view__T_145, ways_3.dirty, UInt<1>(0h0)) node _view__T_255 = mux(_view__T_146, ways_4.dirty, UInt<1>(0h0)) node _view__T_256 = mux(_view__T_147, ways_5.dirty, UInt<1>(0h0)) node _view__T_257 = mux(_view__T_148, ways_6.dirty, UInt<1>(0h0)) node _view__T_258 = mux(_view__T_149, ways_7.dirty, UInt<1>(0h0)) node _view__T_259 = mux(_view__T_150, ways_8.dirty, UInt<1>(0h0)) node _view__T_260 = mux(_view__T_151, ways_9.dirty, UInt<1>(0h0)) node _view__T_261 = mux(_view__T_152, ways_10.dirty, UInt<1>(0h0)) node _view__T_262 = mux(_view__T_153, ways_11.dirty, UInt<1>(0h0)) node _view__T_263 = mux(_view__T_154, ways_12.dirty, UInt<1>(0h0)) node _view__T_264 = mux(_view__T_155, ways_13.dirty, UInt<1>(0h0)) node _view__T_265 = mux(_view__T_156, ways_14.dirty, UInt<1>(0h0)) node _view__T_266 = mux(_view__T_157, ways_15.dirty, UInt<1>(0h0)) node _view__T_267 = or(_view__T_251, _view__T_252) node _view__T_268 = or(_view__T_267, _view__T_253) node _view__T_269 = or(_view__T_268, _view__T_254) node _view__T_270 = or(_view__T_269, _view__T_255) node _view__T_271 = or(_view__T_270, _view__T_256) node _view__T_272 = or(_view__T_271, _view__T_257) node _view__T_273 = or(_view__T_272, _view__T_258) node _view__T_274 = or(_view__T_273, _view__T_259) node _view__T_275 = or(_view__T_274, _view__T_260) node _view__T_276 = or(_view__T_275, _view__T_261) node _view__T_277 = or(_view__T_276, _view__T_262) node _view__T_278 = or(_view__T_277, _view__T_263) node _view__T_279 = or(_view__T_278, _view__T_264) node _view__T_280 = or(_view__T_279, _view__T_265) node _view__T_281 = or(_view__T_280, _view__T_266) wire _view__WIRE_9 : UInt<1> connect _view__WIRE_9, _view__T_281 connect _view__WIRE_5.dirty, _view__WIRE_9 node _view__T_282 = mux(_view__T_141, write_q.io.deq.bits.data, _view__WIRE_5) node _view__T_283 = mux(hit, _view__WIRE, _view__T_282) connect io.result.bits.tag, _view__T_283.tag connect io.result.bits.clients, _view__T_283.clients connect io.result.bits.state, _view__T_283.state connect io.result.bits.dirty, _view__T_283.dirty node _io_result_bits_hit_T = and(setQuash, tagMatch) node _io_result_bits_hit_T_1 = neq(write_q.io.deq.bits.data.state, UInt<2>(0h0)) node _io_result_bits_hit_T_2 = and(_io_result_bits_hit_T, _io_result_bits_hit_T_1) node _io_result_bits_hit_T_3 = or(hit, _io_result_bits_hit_T_2) connect io.result.bits.hit, _io_result_bits_hit_T_3 node io_result_bits_way_hi = bits(hits, 15, 8) node io_result_bits_way_lo = bits(hits, 7, 0) node _io_result_bits_way_T = orr(io_result_bits_way_hi) node _io_result_bits_way_T_1 = or(io_result_bits_way_hi, io_result_bits_way_lo) node io_result_bits_way_hi_1 = bits(_io_result_bits_way_T_1, 7, 4) node io_result_bits_way_lo_1 = bits(_io_result_bits_way_T_1, 3, 0) node _io_result_bits_way_T_2 = orr(io_result_bits_way_hi_1) node _io_result_bits_way_T_3 = or(io_result_bits_way_hi_1, io_result_bits_way_lo_1) node io_result_bits_way_hi_2 = bits(_io_result_bits_way_T_3, 3, 2) node io_result_bits_way_lo_2 = bits(_io_result_bits_way_T_3, 1, 0) node _io_result_bits_way_T_4 = orr(io_result_bits_way_hi_2) node _io_result_bits_way_T_5 = or(io_result_bits_way_hi_2, io_result_bits_way_lo_2) node _io_result_bits_way_T_6 = bits(_io_result_bits_way_T_5, 1, 1) node _io_result_bits_way_T_7 = cat(_io_result_bits_way_T_4, _io_result_bits_way_T_6) node _io_result_bits_way_T_8 = cat(_io_result_bits_way_T_2, _io_result_bits_way_T_7) node _io_result_bits_way_T_9 = cat(_io_result_bits_way_T, _io_result_bits_way_T_8) node _io_result_bits_way_T_10 = and(setQuash, tagMatch) node _io_result_bits_way_T_11 = mux(_io_result_bits_way_T_10, write_q.io.deq.bits.way, victimWay) node _io_result_bits_way_T_12 = mux(hit, _io_result_bits_way_T_9, _io_result_bits_way_T_11) connect io.result.bits.way, _io_result_bits_way_T_12 node _T_166 = and(ren1, setQuash) node _T_167 = and(_T_166, tagMatch) node _T_168 = and(ren1, setQuash) node _T_169 = eq(tagMatch, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = and(_T_170, wayMatch)

module Directory_5( // @[Directory.scala:56:7] input clock, // @[Directory.scala:56:7] input reset, // @[Directory.scala:56:7] output io_write_ready, // @[Directory.scala:58:14] input io_write_valid, // @[Directory.scala:58:14] input [10:0] io_write_bits_set, // @[Directory.scala:58:14] input [3:0] io_write_bits_way, // @[Directory.scala:58:14] input io_write_bits_data_dirty, // @[Directory.scala:58:14] input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14] input io_write_bits_data_clients, // @[Directory.scala:58:14] input [8:0] io_write_bits_data_tag, // @[Directory.scala:58:14] input io_read_valid, // @[Directory.scala:58:14] input [10:0] io_read_bits_set, // @[Directory.scala:58:14] input [8:0] io_read_bits_tag, // @[Directory.scala:58:14] output io_result_bits_dirty, // @[Directory.scala:58:14] output [1:0] io_result_bits_state, // @[Directory.scala:58:14] output io_result_bits_clients, // @[Directory.scala:58:14] output [8:0] io_result_bits_tag, // @[Directory.scala:58:14] output io_result_bits_hit, // @[Directory.scala:58:14] output [3:0] io_result_bits_way, // @[Directory.scala:58:14] output io_ready // @[Directory.scala:58:14] ); wire cc_dir_MPORT_mask_15; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_14; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_13; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_12; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_11; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_10; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_9; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_8; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65] wire [12:0] _T_47; // @[Directory.scala:99:44] wire [12:0] _T_45; // @[Directory.scala:99:44] wire [12:0] _T_43; // @[Directory.scala:99:44] wire [12:0] _T_41; // @[Directory.scala:99:44] wire [12:0] _T_39; // @[Directory.scala:99:44] wire [12:0] _T_37; // @[Directory.scala:99:44] wire [12:0] _T_35; // @[Directory.scala:99:44] wire [12:0] _T_33; // @[Directory.scala:99:44] wire [12:0] _T_31; // @[Directory.scala:99:44] wire [12:0] _T_29; // @[Directory.scala:99:44] wire [12:0] _T_27; // @[Directory.scala:99:44] wire [12:0] _T_25; // @[Directory.scala:99:44] wire [12:0] _T_23; // @[Directory.scala:99:44] wire [12:0] _T_21; // @[Directory.scala:99:44] wire [12:0] _T_19; // @[Directory.scala:99:44] wire [12:0] _T_17; // @[Directory.scala:99:44] wire [10:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10] wire cc_dir_MPORT_en; // @[Directory.scala:96:14] wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_10; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_11; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_12; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_13; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_14; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_15; // @[PRNG.scala:91:22] wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [10:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21] wire [3:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21] wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21] wire [8:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21] wire [207:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_write_valid_0 = io_write_valid; // @[Directory.scala:56:7] wire [10:0] io_write_bits_set_0 = io_write_bits_set; // @[Directory.scala:56:7] wire [3:0] io_write_bits_way_0 = io_write_bits_way; // @[Directory.scala:56:7] wire io_write_bits_data_dirty_0 = io_write_bits_data_dirty; // @[Directory.scala:56:7] wire [1:0] io_write_bits_data_state_0 = io_write_bits_data_state; // @[Directory.scala:56:7] wire io_write_bits_data_clients_0 = io_write_bits_data_clients; // @[Directory.scala:56:7] wire [8:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[Directory.scala:56:7] wire io_read_valid_0 = io_read_valid; // @[Directory.scala:56:7] wire [10:0] io_read_bits_set_0 = io_read_bits_set; // @[Directory.scala:56:7] wire [8:0] io_read_bits_tag_0 = io_read_bits_tag; // @[Directory.scala:56:7] wire _victimLTE_T = 1'h1; // @[Directory.scala:117:43] wire [10:0] _regout_WIRE = io_read_bits_set_0; // @[Directory.scala:56:7, :110:41] wire _view__T_283_dirty; // @[Directory.scala:136:67] wire [1:0] _view__T_283_state; // @[Directory.scala:136:67] wire _view__T_283_clients; // @[Directory.scala:136:67] wire [8:0] _view__T_283_tag; // @[Directory.scala:136:67] wire _io_result_bits_hit_T_3; // @[Directory.scala:137:29] wire [3:0] _io_result_bits_way_T_12; // @[Directory.scala:138:28] wire wipeDone; // @[Directory.scala:81:27] wire io_write_ready_0; // @[Directory.scala:56:7] wire io_result_bits_dirty_0; // @[Directory.scala:56:7] wire [1:0] io_result_bits_state_0; // @[Directory.scala:56:7] wire io_result_bits_clients_0; // @[Directory.scala:56:7] wire [8:0] io_result_bits_tag_0; // @[Directory.scala:56:7] wire io_result_bits_hit_0; // @[Directory.scala:56:7] wire [3:0] io_result_bits_way_0; // @[Directory.scala:56:7] wire io_result_valid; // @[Directory.scala:56:7] wire io_ready_0; // @[Directory.scala:56:7] wire [12:0] _ways_WIRE = _cc_dir_RW0_rdata[12:0]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_1 = _cc_dir_RW0_rdata[25:13]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_2 = _cc_dir_RW0_rdata[38:26]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_3 = _cc_dir_RW0_rdata[51:39]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_4 = _cc_dir_RW0_rdata[64:52]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_5 = _cc_dir_RW0_rdata[77:65]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_6 = _cc_dir_RW0_rdata[90:78]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_7 = _cc_dir_RW0_rdata[103:91]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_8 = _cc_dir_RW0_rdata[116:104]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_9 = _cc_dir_RW0_rdata[129:117]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_10 = _cc_dir_RW0_rdata[142:130]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_11 = _cc_dir_RW0_rdata[155:143]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_12 = _cc_dir_RW0_rdata[168:156]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_13 = _cc_dir_RW0_rdata[181:169]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_14 = _cc_dir_RW0_rdata[194:182]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_15 = _cc_dir_RW0_rdata[207:195]; // @[DescribedSRAM.scala:17:26] reg [11:0] wipeCount; // @[Directory.scala:79:26] reg wipeOff; // @[Directory.scala:80:24] assign wipeDone = wipeCount[11]; // @[Directory.scala:79:26, :81:27] assign io_ready_0 = wipeDone; // @[Directory.scala:56:7, :81:27] wire [10:0] wipeSet = wipeCount[10:0]; // @[Directory.scala:79:26, :82:26] wire _wen_T_1 = ~wipeOff; // @[Directory.scala:80:24, :85:22, :90:27] wire [12:0] _wipeCount_T = {1'h0, wipeCount} + 13'h1; // @[Directory.scala:79:26, :85:57] wire [11:0] _wipeCount_T_1 = _wipeCount_T[11:0]; // @[Directory.scala:85:57] wire _wen_T = ~wipeDone; // @[Directory.scala:81:27, :85:9, :90:14] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Directory.scala:90:{14,24,27}] wire wen = _wen_T_2 | _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _q_io_deq_ready_T = ~io_read_valid_0; // @[Directory.scala:56:7, :86:23, :95:18] assign cc_dir_MPORT_en = ~io_read_valid_0 & wen; // @[Directory.scala:56:7, :86:23, :90:37, :96:14] assign cc_dir_MPORT_addr = wipeDone ? _write_q_io_deq_bits_set : wipeSet; // @[Decoupled.scala:362:21] wire [9:0] _GEN = {_write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag}; // @[Decoupled.scala:362:21] wire [9:0] lo; // @[Directory.scala:99:71] assign lo = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_1; // @[Directory.scala:99:71] assign lo_1 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_2; // @[Directory.scala:99:71] assign lo_2 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_3; // @[Directory.scala:99:71] assign lo_3 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_4; // @[Directory.scala:99:71] assign lo_4 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_5; // @[Directory.scala:99:71] assign lo_5 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_6; // @[Directory.scala:99:71] assign lo_6 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_7; // @[Directory.scala:99:71] assign lo_7 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_8; // @[Directory.scala:99:71] assign lo_8 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_9; // @[Directory.scala:99:71] assign lo_9 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_10; // @[Directory.scala:99:71] assign lo_10 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_11; // @[Directory.scala:99:71] assign lo_11 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_12; // @[Directory.scala:99:71] assign lo_12 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_13; // @[Directory.scala:99:71] assign lo_13 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_14; // @[Directory.scala:99:71] assign lo_14 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_15; // @[Directory.scala:99:71] assign lo_15 = _GEN; // @[Directory.scala:99:71] wire [2:0] _GEN_0 = {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state}; // @[Decoupled.scala:362:21] wire [2:0] hi; // @[Directory.scala:99:71] assign hi = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_1; // @[Directory.scala:99:71] assign hi_1 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_2; // @[Directory.scala:99:71] assign hi_2 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_3; // @[Directory.scala:99:71] assign hi_3 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_4; // @[Directory.scala:99:71] assign hi_4 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_5; // @[Directory.scala:99:71] assign hi_5 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_6; // @[Directory.scala:99:71] assign hi_6 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_7; // @[Directory.scala:99:71] assign hi_7 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_8; // @[Directory.scala:99:71] assign hi_8 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_9; // @[Directory.scala:99:71] assign hi_9 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_10; // @[Directory.scala:99:71] assign hi_10 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_11; // @[Directory.scala:99:71] assign hi_11 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_12; // @[Directory.scala:99:71] assign hi_12 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_13; // @[Directory.scala:99:71] assign hi_13 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_14; // @[Directory.scala:99:71] assign hi_14 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_15; // @[Directory.scala:99:71] assign hi_15 = _GEN_0; // @[Directory.scala:99:71] assign _T_17 = wipeDone ? {hi, lo} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_19 = wipeDone ? {hi_1, lo_1} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_21 = wipeDone ? {hi_2, lo_2} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_23 = wipeDone ? {hi_3, lo_3} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_25 = wipeDone ? {hi_4, lo_4} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_27 = wipeDone ? {hi_5, lo_5} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_29 = wipeDone ? {hi_6, lo_6} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_31 = wipeDone ? {hi_7, lo_7} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_33 = wipeDone ? {hi_8, lo_8} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_35 = wipeDone ? {hi_9, lo_9} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_37 = wipeDone ? {hi_10, lo_10} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_39 = wipeDone ? {hi_11, lo_11} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_41 = wipeDone ? {hi_12, lo_12} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_43 = wipeDone ? {hi_13, lo_13} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_45 = wipeDone ? {hi_14, lo_14} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_47 = wipeDone ? {hi_15, lo_15} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] wire [3:0] shiftAmount; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_0 = shiftAmount == 4'h0 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_1 = shiftAmount == 4'h1 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_2 = shiftAmount == 4'h2 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_3 = shiftAmount == 4'h3 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_4 = shiftAmount == 4'h4 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_5 = shiftAmount == 4'h5 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_6 = shiftAmount == 4'h6 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_7 = shiftAmount == 4'h7 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_8 = shiftAmount == 4'h8 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_9 = shiftAmount == 4'h9 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_10 = shiftAmount == 4'hA | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_11 = shiftAmount == 4'hB | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_12 = shiftAmount == 4'hC | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_13 = shiftAmount == 4'hD | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_14 = shiftAmount == 4'hE | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_15 = (&shiftAmount) | ~wipeDone; // @[OneHot.scala:64:49] reg ren1; // @[Directory.scala:103:21] assign io_result_valid = ren1; // @[Directory.scala:56:7, :103:21] wire _bypass_T = ren1 & _write_q_io_deq_valid; // @[Decoupled.scala:362:21] reg [8:0] tag; // @[Directory.scala:111:36] reg [10:0] set; // @[Directory.scala:112:36] wire [1:0] victimLFSR_lo_lo_lo = {_victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_lo_hi = {_victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_lo = {victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_lo_hi_lo = {_victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_hi_hi = {_victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_hi = {victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_lo = {victimLFSR_lo_hi, victimLFSR_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_lo_lo = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_lo_hi = {_victimLFSR_prng_io_out_11, _victimLFSR_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_lo = {victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_hi_lo = {_victimLFSR_prng_io_out_13, _victimLFSR_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_hi_hi = {_victimLFSR_prng_io_out_15, _victimLFSR_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_hi = {victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_hi = {victimLFSR_hi_hi, victimLFSR_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _victimLFSR_T = {victimLFSR_hi, victimLFSR_lo}; // @[PRNG.scala:95:17] wire [9:0] victimLFSR = _victimLFSR_T[9:0]; // @[PRNG.scala:95:17] wire _victimLTE_T_1 = |(victimLFSR[9:6]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_2 = |(victimLFSR[9:7]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_3 = victimLFSR > 10'hBF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_4 = |(victimLFSR[9:8]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_5 = victimLFSR > 10'h13F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_6 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_7 = victimLFSR > 10'h1BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_8 = victimLFSR[9]; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_9 = victimLFSR > 10'h23F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_10 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_11 = victimLFSR > 10'h2BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_12 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_13 = victimLFSR > 10'h33F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_14 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_15 = victimLFSR > 10'h3BF; // @[Directory.scala:115:63, :117:43] wire [1:0] victimLTE_lo_lo_lo = {_victimLTE_T_1, 1'h1}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_lo_hi = {_victimLTE_T_3, _victimLTE_T_2}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_lo = {victimLTE_lo_lo_hi, victimLTE_lo_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_lo_hi_lo = {_victimLTE_T_5, _victimLTE_T_4}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_hi_hi = {_victimLTE_T_7, _victimLTE_T_6}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_hi = {victimLTE_lo_hi_hi, victimLTE_lo_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_lo = {victimLTE_lo_hi, victimLTE_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_lo_lo = {_victimLTE_T_9, _victimLTE_T_8}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_lo_hi = {_victimLTE_T_11, _victimLTE_T_10}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_lo = {victimLTE_hi_lo_hi, victimLTE_hi_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_hi_lo = {_victimLTE_T_13, _victimLTE_T_12}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_hi_hi = {_victimLTE_T_15, _victimLTE_T_14}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_hi = {victimLTE_hi_hi_hi, victimLTE_hi_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_hi = {victimLTE_hi_hi, victimLTE_hi_lo}; // @[Directory.scala:117:23] wire [15:0] victimLTE = {victimLTE_hi, victimLTE_lo}; // @[Directory.scala:117:23] wire [14:0] _victimSimp_T = victimLTE[15:1]; // @[Directory.scala:117:23, :118:43] wire [15:0] victimSimp_hi = {1'h0, _victimSimp_T}; // @[Directory.scala:118:{23,43}] wire [16:0] victimSimp = {victimSimp_hi, 1'h1}; // @[Directory.scala:118:23] wire [15:0] _victimWayOH_T = victimSimp[15:0]; // @[Directory.scala:118:23, :119:31] wire [15:0] _victimWayOH_T_1 = victimSimp[16:1]; // @[Directory.scala:118:23, :119:70] wire [15:0] _victimWayOH_T_2 = ~_victimWayOH_T_1; // @[Directory.scala:119:{57,70}] wire [15:0] victimWayOH = _victimWayOH_T & _victimWayOH_T_2; // @[Directory.scala:119:{31,55,57}] wire [7:0] victimWay_hi = victimWayOH[15:8]; // @[OneHot.scala:30:18] wire [7:0] victimWay_lo = victimWayOH[7:0]; // @[OneHot.scala:31:18] wire _victimWay_T = |victimWay_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _victimWay_T_1 = victimWay_hi | victimWay_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] victimWay_hi_1 = _victimWay_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] victimWay_lo_1 = _victimWay_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_2 = |victimWay_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _victimWay_T_3 = victimWay_hi_1 | victimWay_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] victimWay_hi_2 = _victimWay_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] victimWay_lo_2 = _victimWay_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_4 = |victimWay_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _victimWay_T_5 = victimWay_hi_2 | victimWay_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _victimWay_T_6 = _victimWay_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _victimWay_T_7 = {_victimWay_T_4, _victimWay_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _victimWay_T_8 = {_victimWay_T_2, _victimWay_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] victimWay = {_victimWay_T, _victimWay_T_8}; // @[OneHot.scala:32:{10,14}] wire _view__T_142 = victimWayOH[0]; // @[Mux.scala:32:36] wire _view__T_143 = victimWayOH[1]; // @[Mux.scala:32:36] wire _view__T_144 = victimWayOH[2]; // @[Mux.scala:32:36] wire _view__T_145 = victimWayOH[3]; // @[Mux.scala:32:36] wire _view__T_146 = victimWayOH[4]; // @[Mux.scala:32:36] wire _view__T_147 = victimWayOH[5]; // @[Mux.scala:32:36] wire _view__T_148 = victimWayOH[6]; // @[Mux.scala:32:36] wire _view__T_149 = victimWayOH[7]; // @[Mux.scala:32:36] wire _view__T_150 = victimWayOH[8]; // @[Mux.scala:32:36] wire _view__T_151 = victimWayOH[9]; // @[Mux.scala:32:36] wire _view__T_152 = victimWayOH[10]; // @[Mux.scala:32:36] wire _view__T_153 = victimWayOH[11]; // @[Mux.scala:32:36] wire _view__T_154 = victimWayOH[12]; // @[Mux.scala:32:36] wire _view__T_155 = victimWayOH[13]; // @[Mux.scala:32:36] wire _view__T_156 = victimWayOH[14]; // @[Mux.scala:32:36] wire _view__T_157 = victimWayOH[15]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_88 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_88( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Pipeline : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, busy : UInt<1>} reg stages : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}[4], clock wire _valids_WIRE : UInt<1>[4] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) regreset valids : UInt<1>[4], clock, reset, _valids_WIRE wire stalling : UInt<1>[4] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) connect stalling[2], UInt<1>(0h0) connect stalling[3], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(_io_busy_T, valids[2]) node _io_busy_T_2 = or(_io_busy_T_1, valids[3]) node _io_busy_T_3 = or(io.in.valid, _io_busy_T_2) connect io.busy, _io_busy_T_3 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_3_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_3_T_1 = and(valids[3], _stalling_3_T) connect stalling[3], _stalling_3_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T node _stalling_1_T = and(valids[1], stalling[2]) connect stalling[1], _stalling_1_T node _stalling_2_T = and(valids[2], stalling[3]) connect stalling[2], _stalling_2_T connect io.out.valid, valids[3] when io.out.ready : connect valids[3], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = eq(stalling[2], UInt<1>(0h0)) when _T_1 : connect valids[1], UInt<1>(0h0) node _T_2 = eq(stalling[3], UInt<1>(0h0)) when _T_2 : connect valids[2], UInt<1>(0h0) node _T_3 = and(io.in.ready, io.in.valid) when _T_3 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) when valids[1] : connect valids[2], UInt<1>(0h1) when valids[2] : connect valids[3], UInt<1>(0h1) node _T_4 = and(io.in.ready, io.in.valid) when _T_4 : connect stages[0], io.in.bits connect io.out.bits, stages[3] node _T_5 = eq(stalling[1], UInt<1>(0h0)) when _T_5 : connect stages[1], stages[0] node _T_6 = eq(stalling[2], UInt<1>(0h0)) when _T_6 : connect stages[2], stages[1] node _T_7 = eq(stalling[3], UInt<1>(0h0)) when _T_7 : connect stages[3], stages[2]

module Pipeline( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_0_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_1_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_2_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_3_bits, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_row, // @[Pipeline.scala:7:14] input io_in_bits_last, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_tag_data, // @[Pipeline.scala:7:14] input [13:0] io_in_bits_tag_addr, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_0, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_1, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_2, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_3, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_4, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_5, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_6, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_7, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_8, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_9, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_10, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_11, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_12, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_13, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_14, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_15, // @[Pipeline.scala:7:14] input io_in_bits_tag_is_acc, // @[Pipeline.scala:7:14] input io_in_bits_tag_accumulate, // @[Pipeline.scala:7:14] input io_in_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_tag_scale, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_repeats, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_len, // @[Pipeline.scala:7:14] input io_in_bits_tag_last, // @[Pipeline.scala:7:14] input [7:0] io_in_bits_tag_bytes_read, // @[Pipeline.scala:7:14] input [7:0] io_in_bits_tag_cmd_id, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_0_bits, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_1_bits, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_2_bits, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_3_bits, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_row, // @[Pipeline.scala:7:14] output io_out_bits_last, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_tag_data, // @[Pipeline.scala:7:14] output [13:0] io_out_bits_tag_addr, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_0, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_1, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_2, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_3, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_4, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_5, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_6, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_7, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_8, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_9, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_10, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_11, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_12, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_13, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_14, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_15, // @[Pipeline.scala:7:14] output io_out_bits_tag_is_acc, // @[Pipeline.scala:7:14] output io_out_bits_tag_accumulate, // @[Pipeline.scala:7:14] output io_out_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_tag_scale, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_repeats, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_len, // @[Pipeline.scala:7:14] output io_out_bits_tag_last, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_tag_bytes_read, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_tag_cmd_id // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_0_bits_0 = io_in_bits_out_0_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_1_bits_0 = io_in_bits_out_1_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_2_bits_0 = io_in_bits_out_2_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_3_bits_0 = io_in_bits_out_3_bits; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_row_0 = io_in_bits_row; // @[Pipeline.scala:6:7] wire io_in_bits_last_0 = io_in_bits_last; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_tag_data_0 = io_in_bits_tag_data; // @[Pipeline.scala:6:7] wire [13:0] io_in_bits_tag_addr_0 = io_in_bits_tag_addr; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_0_0 = io_in_bits_tag_mask_0; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_1_0 = io_in_bits_tag_mask_1; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_2_0 = io_in_bits_tag_mask_2; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_3_0 = io_in_bits_tag_mask_3; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_4_0 = io_in_bits_tag_mask_4; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_5_0 = io_in_bits_tag_mask_5; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_6_0 = io_in_bits_tag_mask_6; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_7_0 = io_in_bits_tag_mask_7; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_8_0 = io_in_bits_tag_mask_8; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_9_0 = io_in_bits_tag_mask_9; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_10_0 = io_in_bits_tag_mask_10; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_11_0 = io_in_bits_tag_mask_11; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_12_0 = io_in_bits_tag_mask_12; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_13_0 = io_in_bits_tag_mask_13; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_14_0 = io_in_bits_tag_mask_14; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_15_0 = io_in_bits_tag_mask_15; // @[Pipeline.scala:6:7] wire io_in_bits_tag_is_acc_0 = io_in_bits_tag_is_acc; // @[Pipeline.scala:6:7] wire io_in_bits_tag_accumulate_0 = io_in_bits_tag_accumulate; // @[Pipeline.scala:6:7] wire io_in_bits_tag_has_acc_bitwidth_0 = io_in_bits_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_tag_scale_0 = io_in_bits_tag_scale; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_repeats_0 = io_in_bits_tag_repeats; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_pixel_repeats_0 = io_in_bits_tag_pixel_repeats; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_len_0 = io_in_bits_tag_len; // @[Pipeline.scala:6:7] wire io_in_bits_tag_last_0 = io_in_bits_tag_last; // @[Pipeline.scala:6:7] wire [7:0] io_in_bits_tag_bytes_read_0 = io_in_bits_tag_bytes_read; // @[Pipeline.scala:6:7] wire [7:0] io_in_bits_tag_cmd_id_0 = io_in_bits_tag_cmd_id; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_3; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_0_bits_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_1_bits_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_2_bits_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_3_bits_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_tag_data_0; // @[Pipeline.scala:6:7] wire [13:0] io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_len_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_last_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_row_0; // @[Pipeline.scala:6:7] wire io_out_bits_last_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [31:0] stages_0_out_0_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_out_1_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_out_2_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_out_3_bits; // @[Pipeline.scala:21:21] reg [15:0] stages_0_row; // @[Pipeline.scala:21:21] reg stages_0_last; // @[Pipeline.scala:21:21] reg [127:0] stages_0_tag_data; // @[Pipeline.scala:21:21] reg [13:0] stages_0_tag_addr; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_0; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_1; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_2; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_3; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_4; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_5; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_6; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_7; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_8; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_9; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_10; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_11; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_12; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_13; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_14; // @[Pipeline.scala:21:21] reg stages_0_tag_mask_15; // @[Pipeline.scala:21:21] reg stages_0_tag_is_acc; // @[Pipeline.scala:21:21] reg stages_0_tag_accumulate; // @[Pipeline.scala:21:21] reg stages_0_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] reg [31:0] stages_0_tag_scale; // @[Pipeline.scala:21:21] reg [15:0] stages_0_tag_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_0_tag_pixel_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_0_tag_len; // @[Pipeline.scala:21:21] reg stages_0_tag_last; // @[Pipeline.scala:21:21] reg [7:0] stages_0_tag_bytes_read; // @[Pipeline.scala:21:21] reg [7:0] stages_0_tag_cmd_id; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_0_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_1_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_2_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_out_3_bits; // @[Pipeline.scala:21:21] reg [15:0] stages_1_row; // @[Pipeline.scala:21:21] reg stages_1_last; // @[Pipeline.scala:21:21] reg [127:0] stages_1_tag_data; // @[Pipeline.scala:21:21] reg [13:0] stages_1_tag_addr; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_0; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_1; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_2; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_3; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_4; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_5; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_6; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_7; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_8; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_9; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_10; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_11; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_12; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_13; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_14; // @[Pipeline.scala:21:21] reg stages_1_tag_mask_15; // @[Pipeline.scala:21:21] reg stages_1_tag_is_acc; // @[Pipeline.scala:21:21] reg stages_1_tag_accumulate; // @[Pipeline.scala:21:21] reg stages_1_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] reg [31:0] stages_1_tag_scale; // @[Pipeline.scala:21:21] reg [15:0] stages_1_tag_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_1_tag_pixel_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_1_tag_len; // @[Pipeline.scala:21:21] reg stages_1_tag_last; // @[Pipeline.scala:21:21] reg [7:0] stages_1_tag_bytes_read; // @[Pipeline.scala:21:21] reg [7:0] stages_1_tag_cmd_id; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_0_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_1_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_2_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_out_3_bits; // @[Pipeline.scala:21:21] reg [15:0] stages_2_row; // @[Pipeline.scala:21:21] reg stages_2_last; // @[Pipeline.scala:21:21] reg [127:0] stages_2_tag_data; // @[Pipeline.scala:21:21] reg [13:0] stages_2_tag_addr; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_0; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_1; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_2; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_3; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_4; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_5; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_6; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_7; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_8; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_9; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_10; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_11; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_12; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_13; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_14; // @[Pipeline.scala:21:21] reg stages_2_tag_mask_15; // @[Pipeline.scala:21:21] reg stages_2_tag_is_acc; // @[Pipeline.scala:21:21] reg stages_2_tag_accumulate; // @[Pipeline.scala:21:21] reg stages_2_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] reg [31:0] stages_2_tag_scale; // @[Pipeline.scala:21:21] reg [15:0] stages_2_tag_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_2_tag_pixel_repeats; // @[Pipeline.scala:21:21] reg [15:0] stages_2_tag_len; // @[Pipeline.scala:21:21] reg stages_2_tag_last; // @[Pipeline.scala:21:21] reg [7:0] stages_2_tag_bytes_read; // @[Pipeline.scala:21:21] reg [7:0] stages_2_tag_cmd_id; // @[Pipeline.scala:21:21] reg [31:0] stages_3_out_0_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_0_bits_0 = stages_3_out_0_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_out_1_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_1_bits_0 = stages_3_out_1_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_out_2_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_2_bits_0 = stages_3_out_2_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_out_3_bits; // @[Pipeline.scala:21:21] assign io_out_bits_out_3_bits_0 = stages_3_out_3_bits; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_row; // @[Pipeline.scala:21:21] assign io_out_bits_row_0 = stages_3_row; // @[Pipeline.scala:6:7, :21:21] reg stages_3_last; // @[Pipeline.scala:21:21] assign io_out_bits_last_0 = stages_3_last; // @[Pipeline.scala:6:7, :21:21] reg [127:0] stages_3_tag_data; // @[Pipeline.scala:21:21] assign io_out_bits_tag_data_0 = stages_3_tag_data; // @[Pipeline.scala:6:7, :21:21] reg [13:0] stages_3_tag_addr; // @[Pipeline.scala:21:21] assign io_out_bits_tag_addr_0 = stages_3_tag_addr; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_0; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_0_0 = stages_3_tag_mask_0; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_1; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_1_0 = stages_3_tag_mask_1; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_2; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_2_0 = stages_3_tag_mask_2; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_3; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_3_0 = stages_3_tag_mask_3; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_4; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_4_0 = stages_3_tag_mask_4; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_5; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_5_0 = stages_3_tag_mask_5; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_6; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_6_0 = stages_3_tag_mask_6; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_7; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_7_0 = stages_3_tag_mask_7; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_8; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_8_0 = stages_3_tag_mask_8; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_9; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_9_0 = stages_3_tag_mask_9; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_10; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_10_0 = stages_3_tag_mask_10; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_11; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_11_0 = stages_3_tag_mask_11; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_12; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_12_0 = stages_3_tag_mask_12; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_13; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_13_0 = stages_3_tag_mask_13; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_14; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_14_0 = stages_3_tag_mask_14; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_mask_15; // @[Pipeline.scala:21:21] assign io_out_bits_tag_mask_15_0 = stages_3_tag_mask_15; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_is_acc; // @[Pipeline.scala:21:21] assign io_out_bits_tag_is_acc_0 = stages_3_tag_is_acc; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_accumulate; // @[Pipeline.scala:21:21] assign io_out_bits_tag_accumulate_0 = stages_3_tag_accumulate; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] assign io_out_bits_tag_has_acc_bitwidth_0 = stages_3_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_3_tag_scale; // @[Pipeline.scala:21:21] assign io_out_bits_tag_scale_0 = stages_3_tag_scale; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_tag_repeats; // @[Pipeline.scala:21:21] assign io_out_bits_tag_repeats_0 = stages_3_tag_repeats; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_tag_pixel_repeats; // @[Pipeline.scala:21:21] assign io_out_bits_tag_pixel_repeats_0 = stages_3_tag_pixel_repeats; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_3_tag_len; // @[Pipeline.scala:21:21] assign io_out_bits_tag_len_0 = stages_3_tag_len; // @[Pipeline.scala:6:7, :21:21] reg stages_3_tag_last; // @[Pipeline.scala:21:21] assign io_out_bits_tag_last_0 = stages_3_tag_last; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_3_tag_bytes_read; // @[Pipeline.scala:21:21] assign io_out_bits_tag_bytes_read_0 = stages_3_tag_bytes_read; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_3_tag_cmd_id; // @[Pipeline.scala:21:21] assign io_out_bits_tag_cmd_id_0 = stages_3_tag_cmd_id; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_3 = io_in_valid_0 | _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_4) begin // @[Decoupled.scala:51:35] stages_0_out_0_bits <= io_in_bits_out_0_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_out_1_bits <= io_in_bits_out_1_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_out_2_bits <= io_in_bits_out_2_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_out_3_bits <= io_in_bits_out_3_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_row <= io_in_bits_row_0; // @[Pipeline.scala:6:7, :21:21] stages_0_last <= io_in_bits_last_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_data <= io_in_bits_tag_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_addr <= io_in_bits_tag_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_0 <= io_in_bits_tag_mask_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_1 <= io_in_bits_tag_mask_1_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_2 <= io_in_bits_tag_mask_2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_3 <= io_in_bits_tag_mask_3_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_4 <= io_in_bits_tag_mask_4_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_5 <= io_in_bits_tag_mask_5_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_6 <= io_in_bits_tag_mask_6_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_7 <= io_in_bits_tag_mask_7_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_8 <= io_in_bits_tag_mask_8_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_9 <= io_in_bits_tag_mask_9_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_10 <= io_in_bits_tag_mask_10_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_11 <= io_in_bits_tag_mask_11_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_12 <= io_in_bits_tag_mask_12_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_13 <= io_in_bits_tag_mask_13_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_14 <= io_in_bits_tag_mask_14_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_mask_15 <= io_in_bits_tag_mask_15_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_is_acc <= io_in_bits_tag_is_acc_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_accumulate <= io_in_bits_tag_accumulate_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_has_acc_bitwidth <= io_in_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_scale <= io_in_bits_tag_scale_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_repeats <= io_in_bits_tag_repeats_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_pixel_repeats <= io_in_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_len <= io_in_bits_tag_len_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_last <= io_in_bits_tag_last_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_bytes_read <= io_in_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7, :21:21] stages_0_tag_cmd_id <= io_in_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_out_0_bits <= stages_0_out_0_bits; // @[Pipeline.scala:21:21] stages_1_out_1_bits <= stages_0_out_1_bits; // @[Pipeline.scala:21:21] stages_1_out_2_bits <= stages_0_out_2_bits; // @[Pipeline.scala:21:21] stages_1_out_3_bits <= stages_0_out_3_bits; // @[Pipeline.scala:21:21] stages_1_row <= stages_0_row; // @[Pipeline.scala:21:21] stages_1_last <= stages_0_last; // @[Pipeline.scala:21:21] stages_1_tag_data <= stages_0_tag_data; // @[Pipeline.scala:21:21] stages_1_tag_addr <= stages_0_tag_addr; // @[Pipeline.scala:21:21] stages_1_tag_mask_0 <= stages_0_tag_mask_0; // @[Pipeline.scala:21:21] stages_1_tag_mask_1 <= stages_0_tag_mask_1; // @[Pipeline.scala:21:21] stages_1_tag_mask_2 <= stages_0_tag_mask_2; // @[Pipeline.scala:21:21] stages_1_tag_mask_3 <= stages_0_tag_mask_3; // @[Pipeline.scala:21:21] stages_1_tag_mask_4 <= stages_0_tag_mask_4; // @[Pipeline.scala:21:21] stages_1_tag_mask_5 <= stages_0_tag_mask_5; // @[Pipeline.scala:21:21] stages_1_tag_mask_6 <= stages_0_tag_mask_6; // @[Pipeline.scala:21:21] stages_1_tag_mask_7 <= stages_0_tag_mask_7; // @[Pipeline.scala:21:21] stages_1_tag_mask_8 <= stages_0_tag_mask_8; // @[Pipeline.scala:21:21] stages_1_tag_mask_9 <= stages_0_tag_mask_9; // @[Pipeline.scala:21:21] stages_1_tag_mask_10 <= stages_0_tag_mask_10; // @[Pipeline.scala:21:21] stages_1_tag_mask_11 <= stages_0_tag_mask_11; // @[Pipeline.scala:21:21] stages_1_tag_mask_12 <= stages_0_tag_mask_12; // @[Pipeline.scala:21:21] stages_1_tag_mask_13 <= stages_0_tag_mask_13; // @[Pipeline.scala:21:21] stages_1_tag_mask_14 <= stages_0_tag_mask_14; // @[Pipeline.scala:21:21] stages_1_tag_mask_15 <= stages_0_tag_mask_15; // @[Pipeline.scala:21:21] stages_1_tag_is_acc <= stages_0_tag_is_acc; // @[Pipeline.scala:21:21] stages_1_tag_accumulate <= stages_0_tag_accumulate; // @[Pipeline.scala:21:21] stages_1_tag_has_acc_bitwidth <= stages_0_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] stages_1_tag_scale <= stages_0_tag_scale; // @[Pipeline.scala:21:21] stages_1_tag_repeats <= stages_0_tag_repeats; // @[Pipeline.scala:21:21] stages_1_tag_pixel_repeats <= stages_0_tag_pixel_repeats; // @[Pipeline.scala:21:21] stages_1_tag_len <= stages_0_tag_len; // @[Pipeline.scala:21:21] stages_1_tag_last <= stages_0_tag_last; // @[Pipeline.scala:21:21] stages_1_tag_bytes_read <= stages_0_tag_bytes_read; // @[Pipeline.scala:21:21] stages_1_tag_cmd_id <= stages_0_tag_cmd_id; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_out_0_bits <= stages_1_out_0_bits; // @[Pipeline.scala:21:21] stages_2_out_1_bits <= stages_1_out_1_bits; // @[Pipeline.scala:21:21] stages_2_out_2_bits <= stages_1_out_2_bits; // @[Pipeline.scala:21:21] stages_2_out_3_bits <= stages_1_out_3_bits; // @[Pipeline.scala:21:21] stages_2_row <= stages_1_row; // @[Pipeline.scala:21:21] stages_2_last <= stages_1_last; // @[Pipeline.scala:21:21] stages_2_tag_data <= stages_1_tag_data; // @[Pipeline.scala:21:21] stages_2_tag_addr <= stages_1_tag_addr; // @[Pipeline.scala:21:21] stages_2_tag_mask_0 <= stages_1_tag_mask_0; // @[Pipeline.scala:21:21] stages_2_tag_mask_1 <= stages_1_tag_mask_1; // @[Pipeline.scala:21:21] stages_2_tag_mask_2 <= stages_1_tag_mask_2; // @[Pipeline.scala:21:21] stages_2_tag_mask_3 <= stages_1_tag_mask_3; // @[Pipeline.scala:21:21] stages_2_tag_mask_4 <= stages_1_tag_mask_4; // @[Pipeline.scala:21:21] stages_2_tag_mask_5 <= stages_1_tag_mask_5; // @[Pipeline.scala:21:21] stages_2_tag_mask_6 <= stages_1_tag_mask_6; // @[Pipeline.scala:21:21] stages_2_tag_mask_7 <= stages_1_tag_mask_7; // @[Pipeline.scala:21:21] stages_2_tag_mask_8 <= stages_1_tag_mask_8; // @[Pipeline.scala:21:21] stages_2_tag_mask_9 <= stages_1_tag_mask_9; // @[Pipeline.scala:21:21] stages_2_tag_mask_10 <= stages_1_tag_mask_10; // @[Pipeline.scala:21:21] stages_2_tag_mask_11 <= stages_1_tag_mask_11; // @[Pipeline.scala:21:21] stages_2_tag_mask_12 <= stages_1_tag_mask_12; // @[Pipeline.scala:21:21] stages_2_tag_mask_13 <= stages_1_tag_mask_13; // @[Pipeline.scala:21:21] stages_2_tag_mask_14 <= stages_1_tag_mask_14; // @[Pipeline.scala:21:21] stages_2_tag_mask_15 <= stages_1_tag_mask_15; // @[Pipeline.scala:21:21] stages_2_tag_is_acc <= stages_1_tag_is_acc; // @[Pipeline.scala:21:21] stages_2_tag_accumulate <= stages_1_tag_accumulate; // @[Pipeline.scala:21:21] stages_2_tag_has_acc_bitwidth <= stages_1_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] stages_2_tag_scale <= stages_1_tag_scale; // @[Pipeline.scala:21:21] stages_2_tag_repeats <= stages_1_tag_repeats; // @[Pipeline.scala:21:21] stages_2_tag_pixel_repeats <= stages_1_tag_pixel_repeats; // @[Pipeline.scala:21:21] stages_2_tag_len <= stages_1_tag_len; // @[Pipeline.scala:21:21] stages_2_tag_last <= stages_1_tag_last; // @[Pipeline.scala:21:21] stages_2_tag_bytes_read <= stages_1_tag_bytes_read; // @[Pipeline.scala:21:21] stages_2_tag_cmd_id <= stages_1_tag_cmd_id; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_out_0_bits <= stages_2_out_0_bits; // @[Pipeline.scala:21:21] stages_3_out_1_bits <= stages_2_out_1_bits; // @[Pipeline.scala:21:21] stages_3_out_2_bits <= stages_2_out_2_bits; // @[Pipeline.scala:21:21] stages_3_out_3_bits <= stages_2_out_3_bits; // @[Pipeline.scala:21:21] stages_3_row <= stages_2_row; // @[Pipeline.scala:21:21] stages_3_last <= stages_2_last; // @[Pipeline.scala:21:21] stages_3_tag_data <= stages_2_tag_data; // @[Pipeline.scala:21:21] stages_3_tag_addr <= stages_2_tag_addr; // @[Pipeline.scala:21:21] stages_3_tag_mask_0 <= stages_2_tag_mask_0; // @[Pipeline.scala:21:21] stages_3_tag_mask_1 <= stages_2_tag_mask_1; // @[Pipeline.scala:21:21] stages_3_tag_mask_2 <= stages_2_tag_mask_2; // @[Pipeline.scala:21:21] stages_3_tag_mask_3 <= stages_2_tag_mask_3; // @[Pipeline.scala:21:21] stages_3_tag_mask_4 <= stages_2_tag_mask_4; // @[Pipeline.scala:21:21] stages_3_tag_mask_5 <= stages_2_tag_mask_5; // @[Pipeline.scala:21:21] stages_3_tag_mask_6 <= stages_2_tag_mask_6; // @[Pipeline.scala:21:21] stages_3_tag_mask_7 <= stages_2_tag_mask_7; // @[Pipeline.scala:21:21] stages_3_tag_mask_8 <= stages_2_tag_mask_8; // @[Pipeline.scala:21:21] stages_3_tag_mask_9 <= stages_2_tag_mask_9; // @[Pipeline.scala:21:21] stages_3_tag_mask_10 <= stages_2_tag_mask_10; // @[Pipeline.scala:21:21] stages_3_tag_mask_11 <= stages_2_tag_mask_11; // @[Pipeline.scala:21:21] stages_3_tag_mask_12 <= stages_2_tag_mask_12; // @[Pipeline.scala:21:21] stages_3_tag_mask_13 <= stages_2_tag_mask_13; // @[Pipeline.scala:21:21] stages_3_tag_mask_14 <= stages_2_tag_mask_14; // @[Pipeline.scala:21:21] stages_3_tag_mask_15 <= stages_2_tag_mask_15; // @[Pipeline.scala:21:21] stages_3_tag_is_acc <= stages_2_tag_is_acc; // @[Pipeline.scala:21:21] stages_3_tag_accumulate <= stages_2_tag_accumulate; // @[Pipeline.scala:21:21] stages_3_tag_has_acc_bitwidth <= stages_2_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21] stages_3_tag_scale <= stages_2_tag_scale; // @[Pipeline.scala:21:21] stages_3_tag_repeats <= stages_2_tag_repeats; // @[Pipeline.scala:21:21] stages_3_tag_pixel_repeats <= stages_2_tag_pixel_repeats; // @[Pipeline.scala:21:21] stages_3_tag_len <= stages_2_tag_len; // @[Pipeline.scala:21:21] stages_3_tag_last <= stages_2_tag_last; // @[Pipeline.scala:21:21] stages_3_tag_bytes_read <= stages_2_tag_bytes_read; // @[Pipeline.scala:21:21] stages_3_tag_cmd_id <= stages_2_tag_cmd_id; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_4 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 | ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_0_bits = io_out_bits_out_0_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_1_bits = io_out_bits_out_1_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_2_bits = io_out_bits_out_2_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_3_bits = io_out_bits_out_3_bits_0; // @[Pipeline.scala:6:7] assign io_out_bits_row = io_out_bits_row_0; // @[Pipeline.scala:6:7] assign io_out_bits_last = io_out_bits_last_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_data = io_out_bits_tag_data_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_addr = io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_0 = io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_1 = io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_2 = io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_3 = io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_4 = io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_5 = io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_6 = io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_7 = io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_8 = io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_9 = io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_10 = io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_11 = io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_12 = io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_13 = io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_14 = io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_15 = io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_is_acc = io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_accumulate = io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_has_acc_bitwidth = io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_scale = io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_repeats = io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_pixel_repeats = io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_len = io_out_bits_tag_len_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_last = io_out_bits_tag_last_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_bytes_read = io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_cmd_id = io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_5 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_5( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_146 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_146( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_13 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 2) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_17 = shr(io.in.a.bits.source, 2) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_30 = shr(io.in.a.bits.source, 2) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_43 = shr(io.in.a.bits.source, 2) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_66 = shr(io.in.a.bits.source, 2) node _T_67 = eq(_T_66, UInt<1>(0h0)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_72 = shr(io.in.a.bits.source, 2) node _T_73 = eq(_T_72, UInt<1>(0h1)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_78 = shr(io.in.a.bits.source, 2) node _T_79 = eq(_T_78, UInt<2>(0h2)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_84 = shr(io.in.a.bits.source, 2) node _T_85 = eq(_T_84, UInt<2>(0h3)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = or(_T_100, _T_105) node _T_137 = or(_T_136, _T_110) node _T_138 = or(_T_137, _T_115) node _T_139 = or(_T_138, _T_120) node _T_140 = or(_T_139, _T_125) node _T_141 = or(_T_140, _T_130) node _T_142 = or(_T_141, _T_135) node _T_143 = and(_T_95, _T_142) node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_150, _T_155) node _T_157 = and(_T_145, _T_156) node _T_158 = or(UInt<1>(0h0), _T_143) node _T_159 = or(_T_158, _T_157) node _T_160 = and(_T_94, _T_159) node _T_161 = asUInt(reset) node _T_162 = eq(_T_161, UInt<1>(0h0)) when _T_162 : node _T_163 = eq(_T_160, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_160, UInt<1>(0h1), "") : assert_2 node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_166 = and(_T_164, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_184 = cvt(_T_183) node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000))) node _T_186 = asSInt(_T_185) node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0))) node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = or(_T_172, _T_177) node _T_219 = or(_T_218, _T_182) node _T_220 = or(_T_219, _T_187) node _T_221 = or(_T_220, _T_192) node _T_222 = or(_T_221, _T_197) node _T_223 = or(_T_222, _T_202) node _T_224 = or(_T_223, _T_207) node _T_225 = or(_T_224, _T_212) node _T_226 = or(_T_225, _T_217) node _T_227 = and(_T_167, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = and(UInt<1>(0h0), _T_228) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_229, UInt<1>(0h1), "") : assert_3 node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(source_ok, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_237 = asUInt(reset) node _T_238 = eq(_T_237, UInt<1>(0h0)) when _T_238 : node _T_239 = eq(_T_236, UInt<1>(0h0)) when _T_239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_236, UInt<1>(0h1), "") : assert_5 node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(is_aligned, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_243, UInt<1>(0h1), "") : assert_7 node _T_247 = not(io.in.a.bits.mask) node _T_248 = eq(_T_247, UInt<1>(0h0)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_248, UInt<1>(0h1), "") : assert_8 node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(_T_252, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_252, UInt<1>(0h1), "") : assert_9 node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_256 : node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_260 = shr(io.in.a.bits.source, 2) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_8) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h1)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_9) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<2>(0h2)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_10) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h3)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_11) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _T_284 = or(_T_265, _T_271) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_283) node _T_287 = and(_T_259, _T_286) node _T_288 = or(UInt<1>(0h0), _T_287) node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = or(_T_294, _T_299) node _T_331 = or(_T_330, _T_304) node _T_332 = or(_T_331, _T_309) node _T_333 = or(_T_332, _T_314) node _T_334 = or(_T_333, _T_319) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_329) node _T_337 = and(_T_289, _T_336) node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_339 = or(UInt<1>(0h0), _T_338) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = or(_T_344, _T_349) node _T_351 = and(_T_339, _T_350) node _T_352 = or(UInt<1>(0h0), _T_337) node _T_353 = or(_T_352, _T_351) node _T_354 = and(_T_288, _T_353) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_354, UInt<1>(0h1), "") : assert_10 node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_366, _T_371) node _T_413 = or(_T_412, _T_376) node _T_414 = or(_T_413, _T_381) node _T_415 = or(_T_414, _T_386) node _T_416 = or(_T_415, _T_391) node _T_417 = or(_T_416, _T_396) node _T_418 = or(_T_417, _T_401) node _T_419 = or(_T_418, _T_406) node _T_420 = or(_T_419, _T_411) node _T_421 = and(_T_361, _T_420) node _T_422 = or(UInt<1>(0h0), _T_421) node _T_423 = and(UInt<1>(0h0), _T_422) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_423, UInt<1>(0h1), "") : assert_11 node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(source_ok, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_430, UInt<1>(0h1), "") : assert_13 node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(is_aligned, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_437, UInt<1>(0h1), "") : assert_15 node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_441, UInt<1>(0h1), "") : assert_16 node _T_445 = not(io.in.a.bits.mask) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_446, UInt<1>(0h1), "") : assert_17 node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_450, UInt<1>(0h1), "") : assert_18 node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_454 : node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_12) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_464 = shr(io.in.a.bits.source, 2) node _T_465 = eq(_T_464, UInt<1>(0h1)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_13) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_469 = and(_T_467, _T_468) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_470 = shr(io.in.a.bits.source, 2) node _T_471 = eq(_T_470, UInt<2>(0h2)) node _T_472 = leq(UInt<1>(0h0), uncommonBits_14) node _T_473 = and(_T_471, _T_472) node _T_474 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_475 = and(_T_473, _T_474) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_476 = shr(io.in.a.bits.source, 2) node _T_477 = eq(_T_476, UInt<2>(0h3)) node _T_478 = leq(UInt<1>(0h0), uncommonBits_15) node _T_479 = and(_T_477, _T_478) node _T_480 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_481 = and(_T_479, _T_480) node _T_482 = or(_T_463, _T_469) node _T_483 = or(_T_482, _T_475) node _T_484 = or(_T_483, _T_481) node _T_485 = and(_T_457, _T_484) node _T_486 = or(UInt<1>(0h0), _T_485) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_486, UInt<1>(0h1), "") : assert_19 node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_492 = and(_T_490, _T_491) node _T_493 = or(UInt<1>(0h0), _T_492) node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = and(_T_493, _T_498) node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_502 = and(_T_500, _T_501) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = or(_T_508, _T_513) node _T_550 = or(_T_549, _T_518) node _T_551 = or(_T_550, _T_523) node _T_552 = or(_T_551, _T_528) node _T_553 = or(_T_552, _T_533) node _T_554 = or(_T_553, _T_538) node _T_555 = or(_T_554, _T_543) node _T_556 = or(_T_555, _T_548) node _T_557 = and(_T_503, _T_556) node _T_558 = or(UInt<1>(0h0), _T_499) node _T_559 = or(_T_558, _T_557) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_559, UInt<1>(0h1), "") : assert_20 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_569, UInt<1>(0h1), "") : assert_23 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_573, UInt<1>(0h1), "") : assert_24 node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_577, UInt<1>(0h1), "") : assert_25 node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_581 : node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_584 = and(_T_582, _T_583) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_585 = shr(io.in.a.bits.source, 2) node _T_586 = eq(_T_585, UInt<1>(0h0)) node _T_587 = leq(UInt<1>(0h0), uncommonBits_16) node _T_588 = and(_T_586, _T_587) node _T_589 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_590 = and(_T_588, _T_589) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_591 = shr(io.in.a.bits.source, 2) node _T_592 = eq(_T_591, UInt<1>(0h1)) node _T_593 = leq(UInt<1>(0h0), uncommonBits_17) node _T_594 = and(_T_592, _T_593) node _T_595 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_596 = and(_T_594, _T_595) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<2>(0h2)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_18) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<2>(0h3)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_19) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(_T_590, _T_596) node _T_610 = or(_T_609, _T_602) node _T_611 = or(_T_610, _T_608) node _T_612 = and(_T_584, _T_611) node _T_613 = or(UInt<1>(0h0), _T_612) node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = and(_T_617, _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_649 = cvt(_T_648) node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000))) node _T_651 = asSInt(_T_650) node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0))) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = or(_T_632, _T_637) node _T_669 = or(_T_668, _T_642) node _T_670 = or(_T_669, _T_647) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_657) node _T_673 = or(_T_672, _T_662) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_627, _T_674) node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = or(UInt<1>(0h0), _T_623) node _T_684 = or(_T_683, _T_675) node _T_685 = or(_T_684, _T_682) node _T_686 = and(_T_613, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_686, UInt<1>(0h1), "") : assert_26 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(source_ok, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(is_aligned, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_696, UInt<1>(0h1), "") : assert_29 node _T_700 = eq(io.in.a.bits.mask, mask) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_700, UInt<1>(0h1), "") : assert_30 node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_704 : node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_707 = and(_T_705, _T_706) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_708 = shr(io.in.a.bits.source, 2) node _T_709 = eq(_T_708, UInt<1>(0h0)) node _T_710 = leq(UInt<1>(0h0), uncommonBits_20) node _T_711 = and(_T_709, _T_710) node _T_712 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_714 = shr(io.in.a.bits.source, 2) node _T_715 = eq(_T_714, UInt<1>(0h1)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_21) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_720 = shr(io.in.a.bits.source, 2) node _T_721 = eq(_T_720, UInt<2>(0h2)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_22) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<2>(0h3)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_23) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(_T_713, _T_719) node _T_733 = or(_T_732, _T_725) node _T_734 = or(_T_733, _T_731) node _T_735 = and(_T_707, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = and(_T_740, _T_745) node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = or(_T_755, _T_760) node _T_792 = or(_T_791, _T_765) node _T_793 = or(_T_792, _T_770) node _T_794 = or(_T_793, _T_775) node _T_795 = or(_T_794, _T_780) node _T_796 = or(_T_795, _T_785) node _T_797 = or(_T_796, _T_790) node _T_798 = and(_T_750, _T_797) node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = and(_T_799, _T_804) node _T_806 = or(UInt<1>(0h0), _T_746) node _T_807 = or(_T_806, _T_798) node _T_808 = or(_T_807, _T_805) node _T_809 = and(_T_736, _T_808) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_809, UInt<1>(0h1), "") : assert_31 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(source_ok, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(is_aligned, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_819, UInt<1>(0h1), "") : assert_34 node _T_823 = not(mask) node _T_824 = and(io.in.a.bits.mask, _T_823) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_825, UInt<1>(0h1), "") : assert_35 node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_829 : node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_832 = and(_T_830, _T_831) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_24) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<1>(0h1)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_25) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<2>(0h2)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_26) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<2>(0h3)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_27) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = or(_T_838, _T_844) node _T_858 = or(_T_857, _T_850) node _T_859 = or(_T_858, _T_856) node _T_860 = and(_T_832, _T_859) node _T_861 = or(UInt<1>(0h0), _T_860) node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _T_865 = or(UInt<1>(0h0), _T_864) node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_877 = cvt(_T_876) node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000))) node _T_879 = asSInt(_T_878) node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<17>(0h10000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<27>(0h4000000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<29>(0h10000000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = or(_T_870, _T_875) node _T_912 = or(_T_911, _T_880) node _T_913 = or(_T_912, _T_885) node _T_914 = or(_T_913, _T_890) node _T_915 = or(_T_914, _T_895) node _T_916 = or(_T_915, _T_900) node _T_917 = or(_T_916, _T_905) node _T_918 = or(_T_917, _T_910) node _T_919 = and(_T_865, _T_918) node _T_920 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_921 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<17>(0h10000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = and(_T_920, _T_925) node _T_927 = or(UInt<1>(0h0), _T_919) node _T_928 = or(_T_927, _T_926) node _T_929 = and(_T_861, _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_929, UInt<1>(0h1), "") : assert_36 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(source_ok, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(is_aligned, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_939 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_939, UInt<1>(0h1), "") : assert_39 node _T_943 = eq(io.in.a.bits.mask, mask) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_943, UInt<1>(0h1), "") : assert_40 node _T_947 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_947 : node _T_948 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_949 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<1>(0h0)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_28) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_957 = shr(io.in.a.bits.source, 2) node _T_958 = eq(_T_957, UInt<1>(0h1)) node _T_959 = leq(UInt<1>(0h0), uncommonBits_29) node _T_960 = and(_T_958, _T_959) node _T_961 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_962 = and(_T_960, _T_961) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_963 = shr(io.in.a.bits.source, 2) node _T_964 = eq(_T_963, UInt<2>(0h2)) node _T_965 = leq(UInt<1>(0h0), uncommonBits_30) node _T_966 = and(_T_964, _T_965) node _T_967 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_968 = and(_T_966, _T_967) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_969 = shr(io.in.a.bits.source, 2) node _T_970 = eq(_T_969, UInt<2>(0h3)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_31) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_974 = and(_T_972, _T_973) node _T_975 = or(_T_956, _T_962) node _T_976 = or(_T_975, _T_968) node _T_977 = or(_T_976, _T_974) node _T_978 = and(_T_950, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_981 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _T_983 = or(UInt<1>(0h0), _T_982) node _T_984 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<14>(0h2000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<13>(0h1000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<18>(0h2f000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<17>(0h10000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<13>(0h1000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1010 = cvt(_T_1009) node _T_1011 = and(_T_1010, asSInt(UInt<17>(0h10000))) node _T_1012 = asSInt(_T_1011) node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0))) node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<29>(0h10000000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = or(_T_988, _T_993) node _T_1030 = or(_T_1029, _T_998) node _T_1031 = or(_T_1030, _T_1003) node _T_1032 = or(_T_1031, _T_1008) node _T_1033 = or(_T_1032, _T_1013) node _T_1034 = or(_T_1033, _T_1018) node _T_1035 = or(_T_1034, _T_1023) node _T_1036 = or(_T_1035, _T_1028) node _T_1037 = and(_T_983, _T_1036) node _T_1038 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1039 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = and(_T_1038, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_1037) node _T_1046 = or(_T_1045, _T_1044) node _T_1047 = and(_T_979, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_41 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1057 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_44 node _T_1061 = eq(io.in.a.bits.mask, mask) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_45 node _T_1065 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1065 : node _T_1066 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1067 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1068 = and(_T_1066, _T_1067) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1069 = shr(io.in.a.bits.source, 2) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) node _T_1071 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1074 = and(_T_1072, _T_1073) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1075 = shr(io.in.a.bits.source, 2) node _T_1076 = eq(_T_1075, UInt<1>(0h1)) node _T_1077 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1080 = and(_T_1078, _T_1079) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1081 = shr(io.in.a.bits.source, 2) node _T_1082 = eq(_T_1081, UInt<2>(0h2)) node _T_1083 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1086 = and(_T_1084, _T_1085) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<2>(0h3)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = or(_T_1074, _T_1080) node _T_1094 = or(_T_1093, _T_1086) node _T_1095 = or(_T_1094, _T_1092) node _T_1096 = and(_T_1068, _T_1095) node _T_1097 = or(UInt<1>(0h0), _T_1096) node _T_1098 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1099 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = or(UInt<1>(0h0), _T_1100) node _T_1102 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<13>(0h1000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = and(_T_1101, _T_1106) node _T_1108 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1109 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1110 = cvt(_T_1109) node _T_1111 = and(_T_1110, asSInt(UInt<14>(0h2000))) node _T_1112 = asSInt(_T_1111) node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0))) node _T_1114 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<17>(0h10000))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<18>(0h2f000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<13>(0h1000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<27>(0h4000000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = or(_T_1113, _T_1118) node _T_1145 = or(_T_1144, _T_1123) node _T_1146 = or(_T_1145, _T_1128) node _T_1147 = or(_T_1146, _T_1133) node _T_1148 = or(_T_1147, _T_1138) node _T_1149 = or(_T_1148, _T_1143) node _T_1150 = and(_T_1108, _T_1149) node _T_1151 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1152 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1156 = cvt(_T_1155) node _T_1157 = and(_T_1156, asSInt(UInt<17>(0h10000))) node _T_1158 = asSInt(_T_1157) node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0))) node _T_1160 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<29>(0h10000000))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1154, _T_1165) node _T_1167 = or(UInt<1>(0h0), _T_1107) node _T_1168 = or(_T_1167, _T_1150) node _T_1169 = or(_T_1168, _T_1166) node _T_1170 = and(_T_1097, _T_1169) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_46 node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(source_ok, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(is_aligned, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1180 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_49 node _T_1184 = eq(io.in.a.bits.mask, mask) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_50 node _T_1188 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1192 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 2) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 2) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 2) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1196 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1196 : node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(source_ok_1, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1200 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_54 node _T_1204 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_55 node _T_1208 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_56 node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_57 node _T_1216 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1216 : node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(source_ok_1, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(sink_ok, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1223 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_60 node _T_1227 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_61 node _T_1231 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_62 node _T_1235 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_63 node _T_1239 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1240 = or(UInt<1>(0h1), _T_1239) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_64 node _T_1244 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1244 : node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(source_ok_1, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(sink_ok, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1251 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_67 node _T_1255 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_68 node _T_1259 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_69 node _T_1263 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1264 = or(_T_1263, io.in.d.bits.corrupt) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_70 node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1269 = or(UInt<1>(0h1), _T_1268) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_71 node _T_1273 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1273 : node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(source_ok_1, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1277 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_73 node _T_1281 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_74 node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1286 = or(UInt<1>(0h1), _T_1285) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_75 node _T_1290 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1290 : node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok_1, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1294 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_77 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(_T_1298, io.in.d.bits.corrupt) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_78 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_79 node _T_1308 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_81 node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_82 node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1321 = or(UInt<1>(0h1), _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1325 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1329 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1333 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(_T_1333, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1333, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1337 = eq(a_first, UInt<1>(0h0)) node _T_1338 = and(io.in.a.valid, _T_1337) when _T_1338 : node _T_1339 = eq(io.in.a.bits.opcode, opcode) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_87 node _T_1343 = eq(io.in.a.bits.param, param) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_88 node _T_1347 = eq(io.in.a.bits.size, size) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_89 node _T_1351 = eq(io.in.a.bits.source, source) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_90 node _T_1355 = eq(io.in.a.bits.address, address) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_91 node _T_1359 = and(io.in.a.ready, io.in.a.valid) node _T_1360 = and(_T_1359, a_first) when _T_1360 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1361 = eq(d_first, UInt<1>(0h0)) node _T_1362 = and(io.in.d.valid, _T_1361) when _T_1362 : node _T_1363 = eq(io.in.d.bits.opcode, opcode_1) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_92 node _T_1367 = eq(io.in.d.bits.param, param_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_93 node _T_1371 = eq(io.in.d.bits.size, size_1) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_94 node _T_1375 = eq(io.in.d.bits.source, source_1) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_95 node _T_1379 = eq(io.in.d.bits.sink, sink) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_96 node _T_1383 = eq(io.in.d.bits.denied, denied) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_97 node _T_1387 = and(io.in.d.ready, io.in.d.valid) node _T_1388 = and(_T_1387, d_first) when _T_1388 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<16> connect a_set, UInt<16>(0h0) wire a_set_wo_ready : UInt<16> connect a_set_wo_ready, UInt<16>(0h0) wire a_opcodes_set : UInt<64> connect a_opcodes_set, UInt<64>(0h0) wire a_sizes_set : UInt<128> connect a_sizes_set, UInt<128>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1389 = and(io.in.a.valid, a_first_1) node _T_1390 = and(_T_1389, UInt<1>(0h1)) when _T_1390 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1391 = and(io.in.a.ready, io.in.a.valid) node _T_1392 = and(_T_1391, a_first_1) node _T_1393 = and(_T_1392, UInt<1>(0h1)) when _T_1393 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1394 = dshr(inflight, io.in.a.bits.source) node _T_1395 = bits(_T_1394, 0, 0) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<16> connect d_clr, UInt<16>(0h0) wire d_clr_wo_ready : UInt<16> connect d_clr_wo_ready, UInt<16>(0h0) wire d_opcodes_clr : UInt<64> connect d_opcodes_clr, UInt<64>(0h0) wire d_sizes_clr : UInt<128> connect d_sizes_clr, UInt<128>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1400 = and(io.in.d.valid, d_first_1) node _T_1401 = and(_T_1400, UInt<1>(0h1)) node _T_1402 = eq(d_release_ack, UInt<1>(0h0)) node _T_1403 = and(_T_1401, _T_1402) when _T_1403 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1404 = and(io.in.d.ready, io.in.d.valid) node _T_1405 = and(_T_1404, d_first_1) node _T_1406 = and(_T_1405, UInt<1>(0h1)) node _T_1407 = eq(d_release_ack, UInt<1>(0h0)) node _T_1408 = and(_T_1406, _T_1407) when _T_1408 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1409 = and(io.in.d.valid, d_first_1) node _T_1410 = and(_T_1409, UInt<1>(0h1)) node _T_1411 = eq(d_release_ack, UInt<1>(0h0)) node _T_1412 = and(_T_1410, _T_1411) when _T_1412 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1413 = dshr(inflight, io.in.d.bits.source) node _T_1414 = bits(_T_1413, 0, 0) node _T_1415 = or(_T_1414, same_cycle_resp) node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(_T_1415, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1415, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1419 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1420 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1421 = or(_T_1419, _T_1420) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_100 node _T_1425 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_101 else : node _T_1429 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1431 = or(_T_1429, _T_1430) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_102 node _T_1435 = eq(io.in.d.bits.size, a_size_lookup) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_103 node _T_1439 = and(io.in.d.valid, d_first_1) node _T_1440 = and(_T_1439, a_first_1) node _T_1441 = and(_T_1440, io.in.a.valid) node _T_1442 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = eq(d_release_ack, UInt<1>(0h0)) node _T_1445 = and(_T_1443, _T_1444) when _T_1445 : node _T_1446 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1447 = or(_T_1446, io.in.a.ready) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_104 node _T_1451 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1452 = orr(a_set_wo_ready) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) node _T_1454 = or(_T_1451, _T_1453) node _T_1455 = asUInt(reset) node _T_1456 = eq(_T_1455, UInt<1>(0h0)) when _T_1456 : node _T_1457 = eq(_T_1454, UInt<1>(0h0)) when _T_1457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1454, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_26 node _T_1458 = orr(inflight) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) node _T_1460 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1461 = or(_T_1459, _T_1460) node _T_1462 = lt(watchdog, plusarg_reader.out) node _T_1463 = or(_T_1461, _T_1462) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1467 = and(io.in.a.ready, io.in.a.valid) node _T_1468 = and(io.in.d.ready, io.in.d.valid) node _T_1469 = or(_T_1467, _T_1468) when _T_1469 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<16> connect c_set, UInt<16>(0h0) wire c_set_wo_ready : UInt<16> connect c_set_wo_ready, UInt<16>(0h0) wire c_opcodes_set : UInt<64> connect c_opcodes_set, UInt<64>(0h0) wire c_sizes_set : UInt<128> connect c_sizes_set, UInt<128>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1470 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1471 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1472 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1473 = and(_T_1471, _T_1472) node _T_1474 = and(_T_1470, _T_1473) when _T_1474 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1475 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1476 = and(_T_1475, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1477 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1478 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = and(_T_1476, _T_1479) when _T_1480 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1481 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1482 = bits(_T_1481, 0, 0) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(_T_1483, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1483, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<16> connect d_clr_1, UInt<16>(0h0) wire d_clr_wo_ready_1 : UInt<16> connect d_clr_wo_ready_1, UInt<16>(0h0) wire d_opcodes_clr_1 : UInt<64> connect d_opcodes_clr_1, UInt<64>(0h0) wire d_sizes_clr_1 : UInt<128> connect d_sizes_clr_1, UInt<128>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1487 = and(io.in.d.valid, d_first_2) node _T_1488 = and(_T_1487, UInt<1>(0h1)) node _T_1489 = and(_T_1488, d_release_ack_1) when _T_1489 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1490 = and(io.in.d.ready, io.in.d.valid) node _T_1491 = and(_T_1490, d_first_2) node _T_1492 = and(_T_1491, UInt<1>(0h1)) node _T_1493 = and(_T_1492, d_release_ack_1) when _T_1493 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1494 = and(io.in.d.valid, d_first_2) node _T_1495 = and(_T_1494, UInt<1>(0h1)) node _T_1496 = and(_T_1495, d_release_ack_1) when _T_1496 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1497 = dshr(inflight_1, io.in.d.bits.source) node _T_1498 = bits(_T_1497, 0, 0) node _T_1499 = or(_T_1498, same_cycle_resp_1) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1503 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_109 else : node _T_1507 = eq(io.in.d.bits.size, c_size_lookup) node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(_T_1507, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1507, UInt<1>(0h1), "") : assert_110 node _T_1511 = and(io.in.d.valid, d_first_2) node _T_1512 = and(_T_1511, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1513 = and(_T_1512, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1514 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = and(_T_1515, d_release_ack_1) node _T_1517 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1518 = and(_T_1516, _T_1517) when _T_1518 : node _T_1519 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1520 = or(_T_1519, _WIRE_23.ready) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_111 node _T_1524 = orr(c_set_wo_ready) when _T_1524 : node _T_1525 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1526 = asUInt(reset) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) when _T_1527 : node _T_1528 = eq(_T_1525, UInt<1>(0h0)) when _T_1528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1525, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_27 node _T_1529 = orr(inflight_1) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) node _T_1531 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1532 = or(_T_1530, _T_1531) node _T_1533 = lt(watchdog_1, plusarg_reader_1.out) node _T_1534 = or(_T_1532, _T_1533) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1538 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1539 = and(io.in.d.ready, io.in.d.valid) node _T_1540 = or(_T_1538, _T_1539) when _T_1540 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_13( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1467 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1467; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1467; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1540 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1540; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1467 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1393 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1393 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1393 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1393 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1393 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1439 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1439 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1408 = _T_1540 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1408 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1408 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1408 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1511 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1511 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1493 = _T_1540 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1493 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1493 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1493 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_134 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_134 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_28 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_9 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_9 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_10 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_10 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_11 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_11 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_12 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_12 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_13 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_13 : connect states[7].g, UInt<3>(0h2) node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_14 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_14 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_15 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_15 : connect states[9].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_29 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_29 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_30 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_30 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_31 = and(io.router_req.ready, io.router_req.valid) when _T_31 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_32 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_33 = or(_T_32, vcalloc_vals[2]) node _T_34 = or(_T_33, vcalloc_vals[3]) node _T_35 = or(_T_34, vcalloc_vals[4]) node _T_36 = or(_T_35, vcalloc_vals[5]) node _T_37 = or(_T_36, vcalloc_vals[6]) node _T_38 = or(_T_37, vcalloc_vals[7]) node _T_39 = or(_T_38, vcalloc_vals[8]) node _T_40 = or(_T_39, vcalloc_vals[9]) when _T_40 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>[10] node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24[0], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410) node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_24[1], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435) node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436) node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446 connect _io_vcalloc_req_bits_WIRE_24[2], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450) node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451) node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452) node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453) node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454) node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455) node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465 connect _io_vcalloc_req_bits_WIRE_24[3], _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467) node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468) node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469) node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470) node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475) wire _io_vcalloc_req_bits_WIRE_29 : UInt<1> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484 connect _io_vcalloc_req_bits_WIRE_24[4], _io_vcalloc_req_bits_WIRE_29 node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503 connect _io_vcalloc_req_bits_WIRE_24[5], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_512 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_513 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_504, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_518 = or(_io_vcalloc_req_bits_T_517, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_519 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_510) node _io_vcalloc_req_bits_T_520 = or(_io_vcalloc_req_bits_T_519, _io_vcalloc_req_bits_T_511) node _io_vcalloc_req_bits_T_521 = or(_io_vcalloc_req_bits_T_520, _io_vcalloc_req_bits_T_512) node _io_vcalloc_req_bits_T_522 = or(_io_vcalloc_req_bits_T_521, _io_vcalloc_req_bits_T_513) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_522 connect _io_vcalloc_req_bits_WIRE_24[6], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_527 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_528 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_529 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_530 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_531 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_532 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_533 = or(_io_vcalloc_req_bits_T_523, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_534 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_525) node _io_vcalloc_req_bits_T_535 = or(_io_vcalloc_req_bits_T_534, _io_vcalloc_req_bits_T_526) node _io_vcalloc_req_bits_T_536 = or(_io_vcalloc_req_bits_T_535, _io_vcalloc_req_bits_T_527) node _io_vcalloc_req_bits_T_537 = or(_io_vcalloc_req_bits_T_536, _io_vcalloc_req_bits_T_528) node _io_vcalloc_req_bits_T_538 = or(_io_vcalloc_req_bits_T_537, _io_vcalloc_req_bits_T_529) node _io_vcalloc_req_bits_T_539 = or(_io_vcalloc_req_bits_T_538, _io_vcalloc_req_bits_T_530) node _io_vcalloc_req_bits_T_540 = or(_io_vcalloc_req_bits_T_539, _io_vcalloc_req_bits_T_531) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_540, _io_vcalloc_req_bits_T_532) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_541 connect _io_vcalloc_req_bits_WIRE_24[7], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_542 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_543 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_544 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_545 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_546 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_547 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_543) node _io_vcalloc_req_bits_T_553 = or(_io_vcalloc_req_bits_T_552, _io_vcalloc_req_bits_T_544) node _io_vcalloc_req_bits_T_554 = or(_io_vcalloc_req_bits_T_553, _io_vcalloc_req_bits_T_545) node _io_vcalloc_req_bits_T_555 = or(_io_vcalloc_req_bits_T_554, _io_vcalloc_req_bits_T_546) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_555, _io_vcalloc_req_bits_T_547) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_548) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_551) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_560 connect _io_vcalloc_req_bits_WIRE_24[8], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_561 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_562 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_562) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_563) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_578 = or(_io_vcalloc_req_bits_T_577, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_579 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_579 connect _io_vcalloc_req_bits_WIRE_24[9], _io_vcalloc_req_bits_WIRE_34 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_24 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_587 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_588 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_589 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_580, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_593 = or(_io_vcalloc_req_bits_T_592, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_594 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_585) node _io_vcalloc_req_bits_T_595 = or(_io_vcalloc_req_bits_T_594, _io_vcalloc_req_bits_T_586) node _io_vcalloc_req_bits_T_596 = or(_io_vcalloc_req_bits_T_595, _io_vcalloc_req_bits_T_587) node _io_vcalloc_req_bits_T_597 = or(_io_vcalloc_req_bits_T_596, _io_vcalloc_req_bits_T_588) node _io_vcalloc_req_bits_T_598 = or(_io_vcalloc_req_bits_T_597, _io_vcalloc_req_bits_T_589) wire _io_vcalloc_req_bits_WIRE_35 : UInt<4> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_598 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_35 wire _io_vcalloc_req_bits_WIRE_36 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_602 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_603 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_604 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_605 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_606 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_607 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = or(_io_vcalloc_req_bits_T_599, _io_vcalloc_req_bits_T_600) node _io_vcalloc_req_bits_T_610 = or(_io_vcalloc_req_bits_T_609, _io_vcalloc_req_bits_T_601) node _io_vcalloc_req_bits_T_611 = or(_io_vcalloc_req_bits_T_610, _io_vcalloc_req_bits_T_602) node _io_vcalloc_req_bits_T_612 = or(_io_vcalloc_req_bits_T_611, _io_vcalloc_req_bits_T_603) node _io_vcalloc_req_bits_T_613 = or(_io_vcalloc_req_bits_T_612, _io_vcalloc_req_bits_T_604) node _io_vcalloc_req_bits_T_614 = or(_io_vcalloc_req_bits_T_613, _io_vcalloc_req_bits_T_605) node _io_vcalloc_req_bits_T_615 = or(_io_vcalloc_req_bits_T_614, _io_vcalloc_req_bits_T_606) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_615, _io_vcalloc_req_bits_T_607) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_608) wire _io_vcalloc_req_bits_WIRE_37 : UInt<3> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_617 connect _io_vcalloc_req_bits_WIRE_36.egress_node_id, _io_vcalloc_req_bits_WIRE_37 node _io_vcalloc_req_bits_T_618 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_619 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_620 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_621 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_622 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_619) node _io_vcalloc_req_bits_T_629 = or(_io_vcalloc_req_bits_T_628, _io_vcalloc_req_bits_T_620) node _io_vcalloc_req_bits_T_630 = or(_io_vcalloc_req_bits_T_629, _io_vcalloc_req_bits_T_621) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_630, _io_vcalloc_req_bits_T_622) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_623) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_627) wire _io_vcalloc_req_bits_WIRE_38 : UInt<4> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_636 connect _io_vcalloc_req_bits_WIRE_36.egress_node, _io_vcalloc_req_bits_WIRE_38 node _io_vcalloc_req_bits_T_637 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_637, _io_vcalloc_req_bits_T_638) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_653 = or(_io_vcalloc_req_bits_T_652, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_654 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_645) node _io_vcalloc_req_bits_T_655 = or(_io_vcalloc_req_bits_T_654, _io_vcalloc_req_bits_T_646) wire _io_vcalloc_req_bits_WIRE_39 : UInt<2> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_655 connect _io_vcalloc_req_bits_WIRE_36.ingress_node_id, _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_662 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_663 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_664 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_665 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_656, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_668 = or(_io_vcalloc_req_bits_T_667, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_669 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_660) node _io_vcalloc_req_bits_T_670 = or(_io_vcalloc_req_bits_T_669, _io_vcalloc_req_bits_T_661) node _io_vcalloc_req_bits_T_671 = or(_io_vcalloc_req_bits_T_670, _io_vcalloc_req_bits_T_662) node _io_vcalloc_req_bits_T_672 = or(_io_vcalloc_req_bits_T_671, _io_vcalloc_req_bits_T_663) node _io_vcalloc_req_bits_T_673 = or(_io_vcalloc_req_bits_T_672, _io_vcalloc_req_bits_T_664) node _io_vcalloc_req_bits_T_674 = or(_io_vcalloc_req_bits_T_673, _io_vcalloc_req_bits_T_665) wire _io_vcalloc_req_bits_WIRE_40 : UInt<4> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_674 connect _io_vcalloc_req_bits_WIRE_36.ingress_node, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_677 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_678 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_679 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_680 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_681 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_682 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = or(_io_vcalloc_req_bits_T_675, _io_vcalloc_req_bits_T_676) node _io_vcalloc_req_bits_T_686 = or(_io_vcalloc_req_bits_T_685, _io_vcalloc_req_bits_T_677) node _io_vcalloc_req_bits_T_687 = or(_io_vcalloc_req_bits_T_686, _io_vcalloc_req_bits_T_678) node _io_vcalloc_req_bits_T_688 = or(_io_vcalloc_req_bits_T_687, _io_vcalloc_req_bits_T_679) node _io_vcalloc_req_bits_T_689 = or(_io_vcalloc_req_bits_T_688, _io_vcalloc_req_bits_T_680) node _io_vcalloc_req_bits_T_690 = or(_io_vcalloc_req_bits_T_689, _io_vcalloc_req_bits_T_681) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_690, _io_vcalloc_req_bits_T_682) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_683) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_684) wire _io_vcalloc_req_bits_WIRE_41 : UInt<3> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_693 connect _io_vcalloc_req_bits_WIRE_36.vnet_id, _io_vcalloc_req_bits_WIRE_41 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_36 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`0`[8] invalidate vcalloc_reqs[0].vc_sel.`0`[9] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[8] invalidate vcalloc_reqs[0].vc_sel.`1`[9] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[8] invalidate vcalloc_reqs[0].vc_sel.`2`[9] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`0`[5] invalidate vcalloc_reqs[1].vc_sel.`0`[6] invalidate vcalloc_reqs[1].vc_sel.`0`[7] invalidate vcalloc_reqs[1].vc_sel.`0`[8] invalidate vcalloc_reqs[1].vc_sel.`0`[9] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[5] invalidate vcalloc_reqs[1].vc_sel.`1`[6] invalidate vcalloc_reqs[1].vc_sel.`1`[7] invalidate vcalloc_reqs[1].vc_sel.`1`[8] invalidate vcalloc_reqs[1].vc_sel.`1`[9] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[3] invalidate vcalloc_reqs[1].vc_sel.`2`[4] invalidate vcalloc_reqs[1].vc_sel.`2`[5] invalidate vcalloc_reqs[1].vc_sel.`2`[6] invalidate vcalloc_reqs[1].vc_sel.`2`[7] invalidate vcalloc_reqs[1].vc_sel.`2`[8] invalidate vcalloc_reqs[1].vc_sel.`2`[9] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`0`[5] invalidate vcalloc_reqs[2].vc_sel.`0`[6] invalidate vcalloc_reqs[2].vc_sel.`0`[7] invalidate vcalloc_reqs[2].vc_sel.`0`[8] invalidate vcalloc_reqs[2].vc_sel.`0`[9] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[5] invalidate vcalloc_reqs[2].vc_sel.`1`[6] invalidate vcalloc_reqs[2].vc_sel.`1`[7] invalidate vcalloc_reqs[2].vc_sel.`1`[8] invalidate vcalloc_reqs[2].vc_sel.`1`[9] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[3] invalidate vcalloc_reqs[2].vc_sel.`2`[4] invalidate vcalloc_reqs[2].vc_sel.`2`[5] invalidate vcalloc_reqs[2].vc_sel.`2`[6] invalidate vcalloc_reqs[2].vc_sel.`2`[7] invalidate vcalloc_reqs[2].vc_sel.`2`[8] invalidate vcalloc_reqs[2].vc_sel.`2`[9] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].flow, states[3].flow node _T_41 = bits(vcalloc_sel, 3, 3) node _T_42 = and(vcalloc_vals[3], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_44 = bits(vcalloc_sel, 4, 4) node _T_45 = and(vcalloc_vals[4], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].flow, states[5].flow node _T_47 = bits(vcalloc_sel, 5, 5) node _T_48 = and(vcalloc_vals[5], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].flow, states[6].flow node _T_50 = bits(vcalloc_sel, 6, 6) node _T_51 = and(vcalloc_vals[6], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].flow, states[7].flow node _T_53 = bits(vcalloc_sel, 7, 7) node _T_54 = and(vcalloc_vals[7], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[7].g, UInt<3>(0h3) node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].flow, states[8].flow node _T_56 = bits(vcalloc_sel, 8, 8) node _T_57 = and(vcalloc_vals[8], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].flow, states[9].flow node _T_59 = bits(vcalloc_sel, 9, 9) node _T_60 = and(vcalloc_vals[9], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_62 : node _T_63 = bits(vcalloc_sel, 0, 0) when _T_63 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_64 = eq(states[0].g, UInt<3>(0h2)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_64, UInt<1>(0h1), "") : assert_3 node _T_68 = bits(vcalloc_sel, 1, 1) when _T_68 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_69 = eq(states[1].g, UInt<3>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 node _T_73 = bits(vcalloc_sel, 2, 2) when _T_73 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_74 = eq(states[2].g, UInt<3>(0h2)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = bits(vcalloc_sel, 3, 3) when _T_78 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_79 = eq(states[3].g, UInt<3>(0h2)) node _T_80 = asUInt(reset) node _T_81 = eq(_T_80, UInt<1>(0h0)) when _T_81 : node _T_82 = eq(_T_79, UInt<1>(0h0)) when _T_82 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_79, UInt<1>(0h1), "") : assert_6 node _T_83 = bits(vcalloc_sel, 4, 4) when _T_83 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_84 = eq(states[4].g, UInt<3>(0h2)) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_84, UInt<1>(0h1), "") : assert_7 node _T_88 = bits(vcalloc_sel, 5, 5) when _T_88 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_89 = eq(states[5].g, UInt<3>(0h2)) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_89, UInt<1>(0h1), "") : assert_8 node _T_93 = bits(vcalloc_sel, 6, 6) when _T_93 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_94 = eq(states[6].g, UInt<3>(0h2)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = bits(vcalloc_sel, 7, 7) when _T_98 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_99 = eq(states[7].g, UInt<3>(0h2)) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = bits(vcalloc_sel, 8, 8) when _T_103 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].g, UInt<3>(0h3) node _T_104 = eq(states[8].g, UInt<3>(0h2)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_104, UInt<1>(0h1), "") : assert_11 node _T_108 = bits(vcalloc_sel, 9, 9) when _T_108 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].g, UInt<3>(0h3) node _T_109 = eq(states[9].g, UInt<3>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_109, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_349 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[9] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[9] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[9] node credit_available_lo_lo = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[3].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[3].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_hi_1 = cat(states[3].vc_sel.`1`[4], states[3].vc_sel.`1`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[3].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[3].vc_sel.`1`[6], states[3].vc_sel.`1`[5]) node credit_available_hi_hi_hi_1 = cat(states[3].vc_sel.`1`[9], states[3].vc_sel.`1`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[3].vc_sel.`1`[7]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_hi_2 = cat(states[3].vc_sel.`2`[4], states[3].vc_sel.`2`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[3].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[3].vc_sel.`2`[6], states[3].vc_sel.`2`[5]) node credit_available_hi_hi_hi_2 = cat(states[3].vc_sel.`2`[9], states[3].vc_sel.`2`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[3].vc_sel.`2`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, io.out_credit_available.`1`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_4 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, io.out_credit_available.`1`[7]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`2`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`2`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[8], states[3].vc_sel.`1`[8] connect salloc_arb.io.in[3].bits.vc_sel.`1`[9], states[3].vc_sel.`1`[9] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[8], states[3].vc_sel.`2`[8] connect salloc_arb.io.in[3].bits.vc_sel.`2`[9], states[3].vc_sel.`2`[9] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_113 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_114 = and(_T_113, input_buffer.io.deq[3].bits.tail) when _T_114 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_6 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, states[4].vc_sel.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, states[4].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6) node credit_available_lo_lo_7 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_hi_7 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3]) node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, states[4].vc_sel.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(states[4].vc_sel.`1`[6], states[4].vc_sel.`1`[5]) node credit_available_hi_hi_hi_7 = cat(states[4].vc_sel.`1`[9], states[4].vc_sel.`1`[8]) node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, states[4].vc_sel.`1`[7]) node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7) node credit_available_lo_lo_8 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_hi_8 = cat(states[4].vc_sel.`2`[4], states[4].vc_sel.`2`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[4].vc_sel.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[4].vc_sel.`2`[6], states[4].vc_sel.`2`[5]) node credit_available_hi_hi_hi_8 = cat(states[4].vc_sel.`2`[9], states[4].vc_sel.`2`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[4].vc_sel.`2`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8) node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10) node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9) node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_10 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, io.out_credit_available.`1`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_10 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, io.out_credit_available.`1`[7]) node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10) node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`2`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`2`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11) node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14) node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13) node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16) node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_1) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[8], states[4].vc_sel.`1`[8] connect salloc_arb.io.in[4].bits.vc_sel.`1`[9], states[4].vc_sel.`1`[9] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[8], states[4].vc_sel.`2`[8] connect salloc_arb.io.in[4].bits.vc_sel.`2`[9], states[4].vc_sel.`2`[9] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_115 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_116 = and(_T_115, input_buffer.io.deq[4].bits.tail) when _T_116 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_12 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[5].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[5].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12) node credit_available_lo_lo_13 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_hi_13 = cat(states[5].vc_sel.`1`[4], states[5].vc_sel.`1`[3]) node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, states[5].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[5].vc_sel.`1`[6], states[5].vc_sel.`1`[5]) node credit_available_hi_hi_hi_13 = cat(states[5].vc_sel.`1`[9], states[5].vc_sel.`1`[8]) node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, states[5].vc_sel.`1`[7]) node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13) node credit_available_lo_lo_14 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_hi_14 = cat(states[5].vc_sel.`2`[4], states[5].vc_sel.`2`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, states[5].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[5].vc_sel.`2`[6], states[5].vc_sel.`2`[5]) node credit_available_hi_hi_hi_14 = cat(states[5].vc_sel.`2`[9], states[5].vc_sel.`2`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, states[5].vc_sel.`2`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14) node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19) node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_16 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_16, io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_16 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_16, io.out_credit_available.`1`[7]) node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_17 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_17 = cat(credit_available_lo_hi_hi_17, io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_17 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_17 = cat(credit_available_hi_hi_hi_17, io.out_credit_available.`2`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17) node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23) node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22) node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25) node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_2) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[8], states[5].vc_sel.`1`[8] connect salloc_arb.io.in[5].bits.vc_sel.`1`[9], states[5].vc_sel.`1`[9] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[8], states[5].vc_sel.`2`[8] connect salloc_arb.io.in[5].bits.vc_sel.`2`[9], states[5].vc_sel.`2`[9] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_117 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_118 = and(_T_117, input_buffer.io.deq[5].bits.tail) when _T_118 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_18 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_hi_18 = cat(states[6].vc_sel.`0`[4], states[6].vc_sel.`0`[3]) node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_18, states[6].vc_sel.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[6].vc_sel.`0`[6], states[6].vc_sel.`0`[5]) node credit_available_hi_hi_hi_18 = cat(states[6].vc_sel.`0`[9], states[6].vc_sel.`0`[8]) node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_18, states[6].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18) node credit_available_lo_lo_19 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_hi_19 = cat(states[6].vc_sel.`1`[4], states[6].vc_sel.`1`[3]) node credit_available_lo_hi_19 = cat(credit_available_lo_hi_hi_19, states[6].vc_sel.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[6].vc_sel.`1`[6], states[6].vc_sel.`1`[5]) node credit_available_hi_hi_hi_19 = cat(states[6].vc_sel.`1`[9], states[6].vc_sel.`1`[8]) node credit_available_hi_hi_19 = cat(credit_available_hi_hi_hi_19, states[6].vc_sel.`1`[7]) node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19) node credit_available_lo_lo_20 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_hi_20 = cat(states[6].vc_sel.`2`[4], states[6].vc_sel.`2`[3]) node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_20, states[6].vc_sel.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[6].vc_sel.`2`[6], states[6].vc_sel.`2`[5]) node credit_available_hi_hi_hi_20 = cat(states[6].vc_sel.`2`[9], states[6].vc_sel.`2`[8]) node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_20, states[6].vc_sel.`2`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20) node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28) node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27) node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_21 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_21 = cat(credit_available_lo_hi_hi_21, io.out_credit_available.`0`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_21 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_21 = cat(credit_available_hi_hi_hi_21, io.out_credit_available.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21) node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_22 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_22, io.out_credit_available.`1`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_22 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_22, io.out_credit_available.`1`[7]) node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22) node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_23 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_23 = cat(credit_available_lo_hi_hi_23, io.out_credit_available.`2`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_23 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_23 = cat(credit_available_hi_hi_hi_23, io.out_credit_available.`2`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23) node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32) node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31) node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34) node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_3) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`0`[8], states[6].vc_sel.`0`[8] connect salloc_arb.io.in[6].bits.vc_sel.`0`[9], states[6].vc_sel.`0`[9] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[8], states[6].vc_sel.`1`[8] connect salloc_arb.io.in[6].bits.vc_sel.`1`[9], states[6].vc_sel.`1`[9] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[8], states[6].vc_sel.`2`[8] connect salloc_arb.io.in[6].bits.vc_sel.`2`[9], states[6].vc_sel.`2`[9] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_119 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_120 = and(_T_119, input_buffer.io.deq[6].bits.tail) when _T_120 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_24 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_hi_24 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3]) node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_24, states[7].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5]) node credit_available_hi_hi_hi_24 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8]) node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_24, states[7].vc_sel.`0`[7]) node credit_available_hi_32 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_36 = cat(credit_available_hi_32, credit_available_lo_24) node credit_available_lo_lo_25 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_hi_25 = cat(states[7].vc_sel.`1`[4], states[7].vc_sel.`1`[3]) node credit_available_lo_hi_25 = cat(credit_available_lo_hi_hi_25, states[7].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[7].vc_sel.`1`[6], states[7].vc_sel.`1`[5]) node credit_available_hi_hi_hi_25 = cat(states[7].vc_sel.`1`[9], states[7].vc_sel.`1`[8]) node credit_available_hi_hi_25 = cat(credit_available_hi_hi_hi_25, states[7].vc_sel.`1`[7]) node credit_available_hi_33 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_37 = cat(credit_available_hi_33, credit_available_lo_25) node credit_available_lo_lo_26 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_hi_26 = cat(states[7].vc_sel.`2`[4], states[7].vc_sel.`2`[3]) node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_26, states[7].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[7].vc_sel.`2`[6], states[7].vc_sel.`2`[5]) node credit_available_hi_hi_hi_26 = cat(states[7].vc_sel.`2`[9], states[7].vc_sel.`2`[8]) node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_26, states[7].vc_sel.`2`[7]) node credit_available_hi_34 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_38 = cat(credit_available_hi_34, credit_available_lo_26) node credit_available_hi_35 = cat(_credit_available_T_38, _credit_available_T_37) node _credit_available_T_39 = cat(credit_available_hi_35, _credit_available_T_36) node credit_available_lo_lo_27 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_27 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_27 = cat(credit_available_lo_hi_hi_27, io.out_credit_available.`0`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_27 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_27 = cat(credit_available_hi_hi_hi_27, io.out_credit_available.`0`[7]) node credit_available_hi_36 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_40 = cat(credit_available_hi_36, credit_available_lo_27) node credit_available_lo_lo_28 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_28 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_28, io.out_credit_available.`1`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_28 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_28, io.out_credit_available.`1`[7]) node credit_available_hi_37 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_41 = cat(credit_available_hi_37, credit_available_lo_28) node credit_available_lo_lo_29 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_29 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_29 = cat(credit_available_lo_hi_hi_29, io.out_credit_available.`2`[2]) node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_29 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_29 = cat(credit_available_hi_hi_hi_29, io.out_credit_available.`2`[7]) node credit_available_hi_38 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_42 = cat(credit_available_hi_38, credit_available_lo_29) node credit_available_hi_39 = cat(_credit_available_T_42, _credit_available_T_41) node _credit_available_T_43 = cat(credit_available_hi_39, _credit_available_T_40) node _credit_available_T_44 = and(_credit_available_T_39, _credit_available_T_43) node credit_available_4 = neq(_credit_available_T_44, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_4) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8] connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[8], states[7].vc_sel.`1`[8] connect salloc_arb.io.in[7].bits.vc_sel.`1`[9], states[7].vc_sel.`1`[9] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[8], states[7].vc_sel.`2`[8] connect salloc_arb.io.in[7].bits.vc_sel.`2`[9], states[7].vc_sel.`2`[9] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_121 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_122 = and(_T_121, input_buffer.io.deq[7].bits.tail) when _T_122 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node credit_available_lo_lo_30 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_30 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_30, states[8].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_30 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_30, states[8].vc_sel.`0`[7]) node credit_available_hi_40 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_45 = cat(credit_available_hi_40, credit_available_lo_30) node credit_available_lo_lo_31 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0]) node credit_available_lo_hi_hi_31 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3]) node credit_available_lo_hi_31 = cat(credit_available_lo_hi_hi_31, states[8].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5]) node credit_available_hi_hi_hi_31 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8]) node credit_available_hi_hi_31 = cat(credit_available_hi_hi_hi_31, states[8].vc_sel.`1`[7]) node credit_available_hi_41 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_46 = cat(credit_available_hi_41, credit_available_lo_31) node credit_available_lo_lo_32 = cat(states[8].vc_sel.`2`[1], states[8].vc_sel.`2`[0]) node credit_available_lo_hi_hi_32 = cat(states[8].vc_sel.`2`[4], states[8].vc_sel.`2`[3]) node credit_available_lo_hi_32 = cat(credit_available_lo_hi_hi_32, states[8].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[8].vc_sel.`2`[6], states[8].vc_sel.`2`[5]) node credit_available_hi_hi_hi_32 = cat(states[8].vc_sel.`2`[9], states[8].vc_sel.`2`[8]) node credit_available_hi_hi_32 = cat(credit_available_hi_hi_hi_32, states[8].vc_sel.`2`[7]) node credit_available_hi_42 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_47 = cat(credit_available_hi_42, credit_available_lo_32) node credit_available_hi_43 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_43, _credit_available_T_45) node credit_available_lo_lo_33 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_33 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_33 = cat(credit_available_lo_hi_hi_33, io.out_credit_available.`0`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_33 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_33 = cat(credit_available_hi_hi_hi_33, io.out_credit_available.`0`[7]) node credit_available_hi_44 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_49 = cat(credit_available_hi_44, credit_available_lo_33) node credit_available_lo_lo_34 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_34 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_34 = cat(credit_available_lo_hi_hi_34, io.out_credit_available.`1`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_34 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_34 = cat(credit_available_hi_hi_hi_34, io.out_credit_available.`1`[7]) node credit_available_hi_45 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_50 = cat(credit_available_hi_45, credit_available_lo_34) node credit_available_lo_lo_35 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_35 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_35 = cat(credit_available_lo_hi_hi_35, io.out_credit_available.`2`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_35 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_35 = cat(credit_available_hi_hi_hi_35, io.out_credit_available.`2`[7]) node credit_available_hi_46 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_51 = cat(credit_available_hi_46, credit_available_lo_35) node credit_available_hi_47 = cat(_credit_available_T_51, _credit_available_T_50) node _credit_available_T_52 = cat(credit_available_hi_47, _credit_available_T_49) node _credit_available_T_53 = and(_credit_available_T_48, _credit_available_T_52) node credit_available_5 = neq(_credit_available_T_53, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_5) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1] connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2] connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3] connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4] connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5] connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6] connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7] connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8] connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[1], states[8].vc_sel.`2`[1] connect salloc_arb.io.in[8].bits.vc_sel.`2`[2], states[8].vc_sel.`2`[2] connect salloc_arb.io.in[8].bits.vc_sel.`2`[3], states[8].vc_sel.`2`[3] connect salloc_arb.io.in[8].bits.vc_sel.`2`[4], states[8].vc_sel.`2`[4] connect salloc_arb.io.in[8].bits.vc_sel.`2`[5], states[8].vc_sel.`2`[5] connect salloc_arb.io.in[8].bits.vc_sel.`2`[6], states[8].vc_sel.`2`[6] connect salloc_arb.io.in[8].bits.vc_sel.`2`[7], states[8].vc_sel.`2`[7] connect salloc_arb.io.in[8].bits.vc_sel.`2`[8], states[8].vc_sel.`2`[8] connect salloc_arb.io.in[8].bits.vc_sel.`2`[9], states[8].vc_sel.`2`[9] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_123 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_124 = and(_T_123, input_buffer.io.deq[8].bits.tail) when _T_124 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_36 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_36 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_36 = cat(credit_available_lo_hi_hi_36, states[9].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_36 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_36 = cat(credit_available_hi_hi_hi_36, states[9].vc_sel.`0`[7]) node credit_available_hi_48 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_54 = cat(credit_available_hi_48, credit_available_lo_36) node credit_available_lo_lo_37 = cat(states[9].vc_sel.`1`[1], states[9].vc_sel.`1`[0]) node credit_available_lo_hi_hi_37 = cat(states[9].vc_sel.`1`[4], states[9].vc_sel.`1`[3]) node credit_available_lo_hi_37 = cat(credit_available_lo_hi_hi_37, states[9].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(states[9].vc_sel.`1`[6], states[9].vc_sel.`1`[5]) node credit_available_hi_hi_hi_37 = cat(states[9].vc_sel.`1`[9], states[9].vc_sel.`1`[8]) node credit_available_hi_hi_37 = cat(credit_available_hi_hi_hi_37, states[9].vc_sel.`1`[7]) node credit_available_hi_49 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_55 = cat(credit_available_hi_49, credit_available_lo_37) node credit_available_lo_lo_38 = cat(states[9].vc_sel.`2`[1], states[9].vc_sel.`2`[0]) node credit_available_lo_hi_hi_38 = cat(states[9].vc_sel.`2`[4], states[9].vc_sel.`2`[3]) node credit_available_lo_hi_38 = cat(credit_available_lo_hi_hi_38, states[9].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(states[9].vc_sel.`2`[6], states[9].vc_sel.`2`[5]) node credit_available_hi_hi_hi_38 = cat(states[9].vc_sel.`2`[9], states[9].vc_sel.`2`[8]) node credit_available_hi_hi_38 = cat(credit_available_hi_hi_hi_38, states[9].vc_sel.`2`[7]) node credit_available_hi_50 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_56 = cat(credit_available_hi_50, credit_available_lo_38) node credit_available_hi_51 = cat(_credit_available_T_56, _credit_available_T_55) node _credit_available_T_57 = cat(credit_available_hi_51, _credit_available_T_54) node credit_available_lo_lo_39 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_39 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_39 = cat(credit_available_lo_hi_hi_39, io.out_credit_available.`0`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_39 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_39 = cat(credit_available_hi_hi_hi_39, io.out_credit_available.`0`[7]) node credit_available_hi_52 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_58 = cat(credit_available_hi_52, credit_available_lo_39) node credit_available_lo_lo_40 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_40 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_40 = cat(credit_available_lo_hi_hi_40, io.out_credit_available.`1`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_40 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_40 = cat(credit_available_hi_hi_hi_40, io.out_credit_available.`1`[7]) node credit_available_hi_53 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_59 = cat(credit_available_hi_53, credit_available_lo_40) node credit_available_lo_lo_41 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_41 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_41 = cat(credit_available_lo_hi_hi_41, io.out_credit_available.`2`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_41 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_41 = cat(credit_available_hi_hi_hi_41, io.out_credit_available.`2`[7]) node credit_available_hi_54 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_60 = cat(credit_available_hi_54, credit_available_lo_41) node credit_available_hi_55 = cat(_credit_available_T_60, _credit_available_T_59) node _credit_available_T_61 = cat(credit_available_hi_55, _credit_available_T_58) node _credit_available_T_62 = and(_credit_available_T_57, _credit_available_T_61) node credit_available_6 = neq(_credit_available_T_62, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_6) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`1`[1], states[9].vc_sel.`1`[1] connect salloc_arb.io.in[9].bits.vc_sel.`1`[2], states[9].vc_sel.`1`[2] connect salloc_arb.io.in[9].bits.vc_sel.`1`[3], states[9].vc_sel.`1`[3] connect salloc_arb.io.in[9].bits.vc_sel.`1`[4], states[9].vc_sel.`1`[4] connect salloc_arb.io.in[9].bits.vc_sel.`1`[5], states[9].vc_sel.`1`[5] connect salloc_arb.io.in[9].bits.vc_sel.`1`[6], states[9].vc_sel.`1`[6] connect salloc_arb.io.in[9].bits.vc_sel.`1`[7], states[9].vc_sel.`1`[7] connect salloc_arb.io.in[9].bits.vc_sel.`1`[8], states[9].vc_sel.`1`[8] connect salloc_arb.io.in[9].bits.vc_sel.`1`[9], states[9].vc_sel.`1`[9] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[1], states[9].vc_sel.`2`[1] connect salloc_arb.io.in[9].bits.vc_sel.`2`[2], states[9].vc_sel.`2`[2] connect salloc_arb.io.in[9].bits.vc_sel.`2`[3], states[9].vc_sel.`2`[3] connect salloc_arb.io.in[9].bits.vc_sel.`2`[4], states[9].vc_sel.`2`[4] connect salloc_arb.io.in[9].bits.vc_sel.`2`[5], states[9].vc_sel.`2`[5] connect salloc_arb.io.in[9].bits.vc_sel.`2`[6], states[9].vc_sel.`2`[6] connect salloc_arb.io.in[9].bits.vc_sel.`2`[7], states[9].vc_sel.`2`[7] connect salloc_arb.io.in[9].bits.vc_sel.`2`[8], states[9].vc_sel.`2`[8] connect salloc_arb.io.in[9].bits.vc_sel.`2`[9], states[9].vc_sel.`2`[9] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_125 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_126 = and(_T_125, input_buffer.io.deq[9].bits.tail) when _T_126 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[10] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_237 connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13 node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_256 connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14 node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_275 connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15 node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_294 connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16 node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298) node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299) node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300) node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301) node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302) node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303) node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_313 connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17 node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315) node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316) node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317) node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318) node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319) node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320) node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321) node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_332 connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18 node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334) node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335) node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336) node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_351 connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19 node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358) node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359) node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360) node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_370 connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20 node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373) node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374) node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375) node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376) node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377) node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378) node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379) node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_389 connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_22 : UInt<1>[10] node _vc_sel_T_390 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_391 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_392 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_393 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_394 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_395 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_396 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_397 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_398 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_400 = or(_vc_sel_T_390, _vc_sel_T_391) node _vc_sel_T_401 = or(_vc_sel_T_400, _vc_sel_T_392) node _vc_sel_T_402 = or(_vc_sel_T_401, _vc_sel_T_393) node _vc_sel_T_403 = or(_vc_sel_T_402, _vc_sel_T_394) node _vc_sel_T_404 = or(_vc_sel_T_403, _vc_sel_T_395) node _vc_sel_T_405 = or(_vc_sel_T_404, _vc_sel_T_396) node _vc_sel_T_406 = or(_vc_sel_T_405, _vc_sel_T_397) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_398) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_399) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_408 connect _vc_sel_WIRE_22[0], _vc_sel_WIRE_23 node _vc_sel_T_409 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_410 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_411 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_412 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_413 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_419 = or(_vc_sel_T_409, _vc_sel_T_410) node _vc_sel_T_420 = or(_vc_sel_T_419, _vc_sel_T_411) node _vc_sel_T_421 = or(_vc_sel_T_420, _vc_sel_T_412) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_413) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_414) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_415) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_416) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_417) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_418) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_427 connect _vc_sel_WIRE_22[1], _vc_sel_WIRE_24 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_436 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_437 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_438 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_430) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_431) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_432) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_433) node _vc_sel_T_443 = or(_vc_sel_T_442, _vc_sel_T_434) node _vc_sel_T_444 = or(_vc_sel_T_443, _vc_sel_T_435) node _vc_sel_T_445 = or(_vc_sel_T_444, _vc_sel_T_436) node _vc_sel_T_446 = or(_vc_sel_T_445, _vc_sel_T_437) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_446 connect _vc_sel_WIRE_22[2], _vc_sel_WIRE_25 node _vc_sel_T_447 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_451 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_452 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_453 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_454 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_455 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_456 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_457 = or(_vc_sel_T_447, _vc_sel_T_448) node _vc_sel_T_458 = or(_vc_sel_T_457, _vc_sel_T_449) node _vc_sel_T_459 = or(_vc_sel_T_458, _vc_sel_T_450) node _vc_sel_T_460 = or(_vc_sel_T_459, _vc_sel_T_451) node _vc_sel_T_461 = or(_vc_sel_T_460, _vc_sel_T_452) node _vc_sel_T_462 = or(_vc_sel_T_461, _vc_sel_T_453) node _vc_sel_T_463 = or(_vc_sel_T_462, _vc_sel_T_454) node _vc_sel_T_464 = or(_vc_sel_T_463, _vc_sel_T_455) node _vc_sel_T_465 = or(_vc_sel_T_464, _vc_sel_T_456) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_465 connect _vc_sel_WIRE_22[3], _vc_sel_WIRE_26 node _vc_sel_T_466 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_467 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_468 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_469 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_470 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_471 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_472 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_473 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_476 = or(_vc_sel_T_466, _vc_sel_T_467) node _vc_sel_T_477 = or(_vc_sel_T_476, _vc_sel_T_468) node _vc_sel_T_478 = or(_vc_sel_T_477, _vc_sel_T_469) node _vc_sel_T_479 = or(_vc_sel_T_478, _vc_sel_T_470) node _vc_sel_T_480 = or(_vc_sel_T_479, _vc_sel_T_471) node _vc_sel_T_481 = or(_vc_sel_T_480, _vc_sel_T_472) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_473) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_474) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_475) wire _vc_sel_WIRE_27 : UInt<1> connect _vc_sel_WIRE_27, _vc_sel_T_484 connect _vc_sel_WIRE_22[4], _vc_sel_WIRE_27 node _vc_sel_T_485 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_486 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_487 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_488 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_495 = or(_vc_sel_T_485, _vc_sel_T_486) node _vc_sel_T_496 = or(_vc_sel_T_495, _vc_sel_T_487) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_488) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_489) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_490) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_491) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_492) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_493) node _vc_sel_T_503 = or(_vc_sel_T_502, _vc_sel_T_494) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_503 connect _vc_sel_WIRE_22[5], _vc_sel_WIRE_28 node _vc_sel_T_504 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_511 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_512 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_513 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_514 = or(_vc_sel_T_504, _vc_sel_T_505) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_506) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_507) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_508) node _vc_sel_T_518 = or(_vc_sel_T_517, _vc_sel_T_509) node _vc_sel_T_519 = or(_vc_sel_T_518, _vc_sel_T_510) node _vc_sel_T_520 = or(_vc_sel_T_519, _vc_sel_T_511) node _vc_sel_T_521 = or(_vc_sel_T_520, _vc_sel_T_512) node _vc_sel_T_522 = or(_vc_sel_T_521, _vc_sel_T_513) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_522 connect _vc_sel_WIRE_22[6], _vc_sel_WIRE_29 node _vc_sel_T_523 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_526 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_527 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_528 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_529 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_530 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_531 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_532 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_533 = or(_vc_sel_T_523, _vc_sel_T_524) node _vc_sel_T_534 = or(_vc_sel_T_533, _vc_sel_T_525) node _vc_sel_T_535 = or(_vc_sel_T_534, _vc_sel_T_526) node _vc_sel_T_536 = or(_vc_sel_T_535, _vc_sel_T_527) node _vc_sel_T_537 = or(_vc_sel_T_536, _vc_sel_T_528) node _vc_sel_T_538 = or(_vc_sel_T_537, _vc_sel_T_529) node _vc_sel_T_539 = or(_vc_sel_T_538, _vc_sel_T_530) node _vc_sel_T_540 = or(_vc_sel_T_539, _vc_sel_T_531) node _vc_sel_T_541 = or(_vc_sel_T_540, _vc_sel_T_532) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_541 connect _vc_sel_WIRE_22[7], _vc_sel_WIRE_30 node _vc_sel_T_542 = mux(_vc_sel_T, states[0].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_543 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_544 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_545 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_546 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_547 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_548 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_552 = or(_vc_sel_T_542, _vc_sel_T_543) node _vc_sel_T_553 = or(_vc_sel_T_552, _vc_sel_T_544) node _vc_sel_T_554 = or(_vc_sel_T_553, _vc_sel_T_545) node _vc_sel_T_555 = or(_vc_sel_T_554, _vc_sel_T_546) node _vc_sel_T_556 = or(_vc_sel_T_555, _vc_sel_T_547) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_548) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_549) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_550) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_551) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_560 connect _vc_sel_WIRE_22[8], _vc_sel_WIRE_31 node _vc_sel_T_561 = mux(_vc_sel_T, states[0].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_562 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_563 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_561, _vc_sel_T_562) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_563) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_564) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_565) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_566) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_567) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_568) node _vc_sel_T_578 = or(_vc_sel_T_577, _vc_sel_T_569) node _vc_sel_T_579 = or(_vc_sel_T_578, _vc_sel_T_570) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_579 connect _vc_sel_WIRE_22[9], _vc_sel_WIRE_32 connect vc_sel.`2`, _vc_sel_WIRE_22 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4]) node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8]) node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9]) node _channel_oh_T_16 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[2]) node _channel_oh_T_18 = or(_channel_oh_T_17, vc_sel.`2`[3]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`2`[4]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`2`[5]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`2`[6]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`2`[7]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`2`[8]) node channel_oh_2 = or(_channel_oh_T_23, vc_sel.`2`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2]) node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5]) node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8]) node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7]) node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8) node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0) node _virt_channel_T_12 = orr(virt_channel_hi_5) node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5) node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4) node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0) node _virt_channel_T_14 = orr(virt_channel_hi_6) node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2) node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19) node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_lo_hi_2 = cat(virt_channel_lo_hi_hi_2, vc_sel.`2`[2]) node virt_channel_lo_8 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[6], vc_sel.`2`[5]) node virt_channel_hi_hi_hi_2 = cat(vc_sel.`2`[9], vc_sel.`2`[8]) node virt_channel_hi_hi_2 = cat(virt_channel_hi_hi_hi_2, vc_sel.`2`[7]) node virt_channel_hi_8 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_22 = cat(virt_channel_hi_8, virt_channel_lo_8) node virt_channel_hi_9 = bits(_virt_channel_T_22, 9, 8) node virt_channel_lo_9 = bits(_virt_channel_T_22, 7, 0) node _virt_channel_T_23 = orr(virt_channel_hi_9) node _virt_channel_T_24 = or(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = cat(_virt_channel_T_23, _virt_channel_T_31) node _virt_channel_T_33 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_2, _virt_channel_T_32, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_33, _virt_channel_T_34) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_35) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_37 node _T_127 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_127 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`0`[8] invalidate states[0].vc_sel.`0`[9] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`1`[8] invalidate states[0].vc_sel.`1`[9] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`2`[8] invalidate states[0].vc_sel.`2`[9] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`0`[5] invalidate states[1].vc_sel.`0`[6] invalidate states[1].vc_sel.`0`[7] invalidate states[1].vc_sel.`0`[8] invalidate states[1].vc_sel.`0`[9] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].vc_sel.`1`[5] invalidate states[1].vc_sel.`1`[6] invalidate states[1].vc_sel.`1`[7] invalidate states[1].vc_sel.`1`[8] invalidate states[1].vc_sel.`1`[9] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`2`[3] invalidate states[1].vc_sel.`2`[4] invalidate states[1].vc_sel.`2`[5] invalidate states[1].vc_sel.`2`[6] invalidate states[1].vc_sel.`2`[7] invalidate states[1].vc_sel.`2`[8] invalidate states[1].vc_sel.`2`[9] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`0`[5] invalidate states[2].vc_sel.`0`[6] invalidate states[2].vc_sel.`0`[7] invalidate states[2].vc_sel.`0`[8] invalidate states[2].vc_sel.`0`[9] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].vc_sel.`1`[5] invalidate states[2].vc_sel.`1`[6] invalidate states[2].vc_sel.`1`[7] invalidate states[2].vc_sel.`1`[8] invalidate states[2].vc_sel.`1`[9] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`2`[3] invalidate states[2].vc_sel.`2`[4] invalidate states[2].vc_sel.`2`[5] invalidate states[2].vc_sel.`2`[6] invalidate states[2].vc_sel.`2`[7] invalidate states[2].vc_sel.`2`[8] invalidate states[2].vc_sel.`2`[9] invalidate states[2].g connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[2], UInt<1>(0h0) connect states[3].vc_sel.`0`[3], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[6], UInt<1>(0h0) connect states[3].vc_sel.`0`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[8], UInt<1>(0h0) connect states[3].vc_sel.`0`[9], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[8], UInt<1>(0h0) connect states[3].vc_sel.`1`[9], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[8], UInt<1>(0h0) connect states[3].vc_sel.`2`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[4], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[6], UInt<1>(0h0) connect states[4].vc_sel.`0`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[8], UInt<1>(0h0) connect states[4].vc_sel.`0`[9], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[8], UInt<1>(0h0) connect states[4].vc_sel.`1`[9], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[8], UInt<1>(0h0) connect states[4].vc_sel.`2`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) connect states[5].vc_sel.`0`[4], UInt<1>(0h0) connect states[5].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[6], UInt<1>(0h0) connect states[5].vc_sel.`0`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[8], UInt<1>(0h0) connect states[5].vc_sel.`0`[9], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`1`[5], UInt<1>(0h0) connect states[5].vc_sel.`1`[6], UInt<1>(0h0) connect states[5].vc_sel.`1`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[8], UInt<1>(0h0) connect states[5].vc_sel.`1`[9], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`2`[8], UInt<1>(0h0) connect states[5].vc_sel.`2`[9], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`0`[1], UInt<1>(0h0) connect states[6].vc_sel.`0`[2], UInt<1>(0h0) connect states[6].vc_sel.`0`[3], UInt<1>(0h0) connect states[6].vc_sel.`0`[4], UInt<1>(0h0) connect states[6].vc_sel.`0`[5], UInt<1>(0h0) connect states[6].vc_sel.`0`[6], UInt<1>(0h0) connect states[6].vc_sel.`0`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[8], UInt<1>(0h0) connect states[6].vc_sel.`0`[9], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`1`[5], UInt<1>(0h0) connect states[6].vc_sel.`1`[6], UInt<1>(0h0) connect states[6].vc_sel.`1`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[8], UInt<1>(0h0) connect states[6].vc_sel.`1`[9], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`2`[8], UInt<1>(0h0) connect states[6].vc_sel.`2`[9], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`0`[1], UInt<1>(0h0) connect states[7].vc_sel.`0`[2], UInt<1>(0h0) connect states[7].vc_sel.`0`[3], UInt<1>(0h0) connect states[7].vc_sel.`0`[4], UInt<1>(0h0) connect states[7].vc_sel.`0`[5], UInt<1>(0h0) connect states[7].vc_sel.`0`[6], UInt<1>(0h0) connect states[7].vc_sel.`0`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[8], UInt<1>(0h0) connect states[7].vc_sel.`0`[9], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`1`[5], UInt<1>(0h0) connect states[7].vc_sel.`1`[6], UInt<1>(0h0) connect states[7].vc_sel.`1`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[8], UInt<1>(0h0) connect states[7].vc_sel.`1`[9], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[8], UInt<1>(0h0) connect states[7].vc_sel.`2`[9], UInt<1>(0h0) connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`0`[8], UInt<1>(0h0) connect states[8].vc_sel.`0`[9], UInt<1>(0h0) connect states[8].vc_sel.`1`[0], UInt<1>(0h0) connect states[8].vc_sel.`1`[1], UInt<1>(0h0) connect states[8].vc_sel.`1`[2], UInt<1>(0h0) connect states[8].vc_sel.`1`[3], UInt<1>(0h0) connect states[8].vc_sel.`1`[4], UInt<1>(0h0) connect states[8].vc_sel.`1`[5], UInt<1>(0h0) connect states[8].vc_sel.`1`[6], UInt<1>(0h0) connect states[8].vc_sel.`1`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[8], UInt<1>(0h0) connect states[8].vc_sel.`1`[9], UInt<1>(0h0) connect states[8].vc_sel.`2`[0], UInt<1>(0h0) connect states[8].vc_sel.`2`[1], UInt<1>(0h0) connect states[8].vc_sel.`2`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`0`[2], UInt<1>(0h0) connect states[9].vc_sel.`0`[3], UInt<1>(0h0) connect states[9].vc_sel.`0`[4], UInt<1>(0h0) connect states[9].vc_sel.`0`[5], UInt<1>(0h0) connect states[9].vc_sel.`0`[6], UInt<1>(0h0) connect states[9].vc_sel.`0`[7], UInt<1>(0h0) connect states[9].vc_sel.`0`[8], UInt<1>(0h0) connect states[9].vc_sel.`0`[9], UInt<1>(0h0) connect states[9].vc_sel.`1`[0], UInt<1>(0h0) connect states[9].vc_sel.`1`[1], UInt<1>(0h0) connect states[9].vc_sel.`1`[2], UInt<1>(0h0) connect states[9].vc_sel.`1`[3], UInt<1>(0h0) connect states[9].vc_sel.`1`[4], UInt<1>(0h0) connect states[9].vc_sel.`1`[5], UInt<1>(0h0) connect states[9].vc_sel.`1`[6], UInt<1>(0h0) connect states[9].vc_sel.`1`[7], UInt<1>(0h0) connect states[9].vc_sel.`1`[8], UInt<1>(0h0) connect states[9].vc_sel.`1`[9], UInt<1>(0h0) connect states[9].vc_sel.`2`[0], UInt<1>(0h0) connect states[9].vc_sel.`2`[1], UInt<1>(0h0) node _T_128 = asUInt(reset) when _T_128 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)

module InputUnit_134( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_8, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_8; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, 3'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_24 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_228 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_229 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_24( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_228 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_229 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_12 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}} node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31) node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23) node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0) node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0) node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1) node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2) node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3) node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4) node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5) node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6) node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7) node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8) node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9) node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10) node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11) node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12) node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13) node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14) node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15) node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16) node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17) node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18) node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19) node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20) node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21) node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22) node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23) node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24) node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25) node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26) node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27) node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28) node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29) node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30) node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31) node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32) node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33) node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34) node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35) node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36) node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37) node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38) node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39) node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40) node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41) node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42) node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43) node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist) node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn) node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2) node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3) node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn) node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T) connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1 node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn) connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T) connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1 node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T) node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn) node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2) connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3 node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6) node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T) node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2) node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3) node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0) node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5) node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0) node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7) node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31) node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23) node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0) node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0) node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1) node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2) node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3) node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4) node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5) node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6) node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7) node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8) node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9) node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10) node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11) node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12) node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13) node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14) node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15) node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16) node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17) node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18) node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19) node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20) node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21) node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22) node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23) node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24) node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25) node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26) node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27) node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28) node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29) node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30) node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31) node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32) node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33) node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34) node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35) node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36) node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37) node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38) node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39) node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40) node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41) node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42) node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43) node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist) node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn) node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2) node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3) node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn) node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T) connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1 node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn) connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T) connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1 node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T) node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn) node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2) connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3 node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6) node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T) node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2) node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3) node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0) node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5) node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0) node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7) node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31) node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23) node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0) node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0) node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1) node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2) node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3) node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4) node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5) node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6) node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7) node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8) node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9) node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10) node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11) node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12) node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13) node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14) node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15) node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16) node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17) node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18) node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19) node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20) node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21) node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22) node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23) node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24) node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25) node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26) node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27) node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28) node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29) node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30) node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31) node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32) node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33) node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34) node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35) node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36) node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37) node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38) node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39) node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40) node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41) node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42) node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43) node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist) node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn) node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2) node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3) node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn) node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7) node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T) connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1 node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn) connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T) connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1 node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T) node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn) node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2) connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3 node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6) node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T) node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2) node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3) node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0) node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5) node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0) node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7) inst io_out_d_m1_resizer of RecFNToRecFN_216 connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_m2_resizer of RecFNToRecFN_217 connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_muladder of MulAddRecFN_e8_s24_76 connect io_out_d_muladder.io.op, UInt<1>(0h0) connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out connect io_out_d_muladder.io.c, io_out_d_self_rec wire io_out_d_out : { bits : UInt<32>} node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23) node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6) node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7) node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T) connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1 node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1) connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2 connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32) connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp) connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T) node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0) node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2) connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3 node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0) node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T) node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1) node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1) node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist) node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0) node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0) node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81)) node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1) node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2) node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf) node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5) node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0) node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T) node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1) node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut) node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut) connect io_out_d_out.bits, _io_out_d_out_bits_T connect io.out_d, io_out_d_out

module MacUnit_12( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [31:0] io_in_a_bits, // @[PE.scala:16:14] input [31:0] io_in_b_bits, // @[PE.scala:16:14] input [31:0] io_in_c_bits, // @[PE.scala:16:14] output [31:0] io_out_d_bits // @[PE.scala:16:14] ); wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7] wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7] wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23] wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7] wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] | _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] | _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] | _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7] wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN | io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 | _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] RecFNToRecFN_216 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_217 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_76 io_out_d_muladder ( // @[Arithmetic.scala:376:30] .io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_muladder_io_out) ); // @[Arithmetic.scala:376:30] assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module BoomDuplicatedDataArray : input clock : Clock input reset : Reset output io : { flip read : { valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>}}[1], flip write : { valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[8][1], s1_nacks : UInt<1>[1]} node waddr = shr(io.write.bits.addr, 4) node raddr = shr(io.read[0].bits.addr, 4) smem array_0_0 : UInt<64>[2] [256] node _T = bits(io.write.bits.way_en, 0, 0) node _T_1 = and(_T, io.write.valid) when _T_1 : node _data_T = bits(io.write.bits.data, 63, 0) node _data_T_1 = bits(io.write.bits.data, 127, 64) wire data : UInt<64>[2] connect data[0], _data_T connect data[1], _data_T_1 node _T_2 = bits(io.write.bits.wmask, 0, 0) node _T_3 = bits(io.write.bits.wmask, 1, 1) write mport MPORT = array_0_0[waddr], clock when _T_2 : connect MPORT[0], data[0] when _T_3 : connect MPORT[1], data[1] wire _io_resp_0_0_WIRE : UInt<8> invalidate _io_resp_0_0_WIRE when io.read[0].valid : connect _io_resp_0_0_WIRE, raddr read mport io_resp_0_0_MPORT = array_0_0[_io_resp_0_0_WIRE], clock node _io_resp_0_0_T = cat(io_resp_0_0_MPORT[1], io_resp_0_0_MPORT[0]) reg io_resp_0_0_REG : UInt, clock connect io_resp_0_0_REG, _io_resp_0_0_T connect io.resp[0][0], io_resp_0_0_REG smem array_1_0 : UInt<64>[2] [256] node _T_4 = bits(io.write.bits.way_en, 1, 1) node _T_5 = and(_T_4, io.write.valid) when _T_5 : node _data_T_2 = bits(io.write.bits.data, 63, 0) node _data_T_3 = bits(io.write.bits.data, 127, 64) wire data_1 : UInt<64>[2] connect data_1[0], _data_T_2 connect data_1[1], _data_T_3 node _T_6 = bits(io.write.bits.wmask, 0, 0) node _T_7 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_1 = array_1_0[waddr], clock when _T_6 : connect MPORT_1[0], data_1[0] when _T_7 : connect MPORT_1[1], data_1[1] wire _io_resp_0_1_WIRE : UInt<8> invalidate _io_resp_0_1_WIRE when io.read[0].valid : connect _io_resp_0_1_WIRE, raddr read mport io_resp_0_1_MPORT = array_1_0[_io_resp_0_1_WIRE], clock node _io_resp_0_1_T = cat(io_resp_0_1_MPORT[1], io_resp_0_1_MPORT[0]) reg io_resp_0_1_REG : UInt, clock connect io_resp_0_1_REG, _io_resp_0_1_T connect io.resp[0][1], io_resp_0_1_REG smem array_2_0 : UInt<64>[2] [256] node _T_8 = bits(io.write.bits.way_en, 2, 2) node _T_9 = and(_T_8, io.write.valid) when _T_9 : node _data_T_4 = bits(io.write.bits.data, 63, 0) node _data_T_5 = bits(io.write.bits.data, 127, 64) wire data_2 : UInt<64>[2] connect data_2[0], _data_T_4 connect data_2[1], _data_T_5 node _T_10 = bits(io.write.bits.wmask, 0, 0) node _T_11 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_2 = array_2_0[waddr], clock when _T_10 : connect MPORT_2[0], data_2[0] when _T_11 : connect MPORT_2[1], data_2[1] wire _io_resp_0_2_WIRE : UInt<8> invalidate _io_resp_0_2_WIRE when io.read[0].valid : connect _io_resp_0_2_WIRE, raddr read mport io_resp_0_2_MPORT = array_2_0[_io_resp_0_2_WIRE], clock node _io_resp_0_2_T = cat(io_resp_0_2_MPORT[1], io_resp_0_2_MPORT[0]) reg io_resp_0_2_REG : UInt, clock connect io_resp_0_2_REG, _io_resp_0_2_T connect io.resp[0][2], io_resp_0_2_REG smem array_3_0 : UInt<64>[2] [256] node _T_12 = bits(io.write.bits.way_en, 3, 3) node _T_13 = and(_T_12, io.write.valid) when _T_13 : node _data_T_6 = bits(io.write.bits.data, 63, 0) node _data_T_7 = bits(io.write.bits.data, 127, 64) wire data_3 : UInt<64>[2] connect data_3[0], _data_T_6 connect data_3[1], _data_T_7 node _T_14 = bits(io.write.bits.wmask, 0, 0) node _T_15 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_3 = array_3_0[waddr], clock when _T_14 : connect MPORT_3[0], data_3[0] when _T_15 : connect MPORT_3[1], data_3[1] wire _io_resp_0_3_WIRE : UInt<8> invalidate _io_resp_0_3_WIRE when io.read[0].valid : connect _io_resp_0_3_WIRE, raddr read mport io_resp_0_3_MPORT = array_3_0[_io_resp_0_3_WIRE], clock node _io_resp_0_3_T = cat(io_resp_0_3_MPORT[1], io_resp_0_3_MPORT[0]) reg io_resp_0_3_REG : UInt, clock connect io_resp_0_3_REG, _io_resp_0_3_T connect io.resp[0][3], io_resp_0_3_REG smem array_4_0 : UInt<64>[2] [256] node _T_16 = bits(io.write.bits.way_en, 4, 4) node _T_17 = and(_T_16, io.write.valid) when _T_17 : node _data_T_8 = bits(io.write.bits.data, 63, 0) node _data_T_9 = bits(io.write.bits.data, 127, 64) wire data_4 : UInt<64>[2] connect data_4[0], _data_T_8 connect data_4[1], _data_T_9 node _T_18 = bits(io.write.bits.wmask, 0, 0) node _T_19 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_4 = array_4_0[waddr], clock when _T_18 : connect MPORT_4[0], data_4[0] when _T_19 : connect MPORT_4[1], data_4[1] wire _io_resp_0_4_WIRE : UInt<8> invalidate _io_resp_0_4_WIRE when io.read[0].valid : connect _io_resp_0_4_WIRE, raddr read mport io_resp_0_4_MPORT = array_4_0[_io_resp_0_4_WIRE], clock node _io_resp_0_4_T = cat(io_resp_0_4_MPORT[1], io_resp_0_4_MPORT[0]) reg io_resp_0_4_REG : UInt, clock connect io_resp_0_4_REG, _io_resp_0_4_T connect io.resp[0][4], io_resp_0_4_REG smem array_5_0 : UInt<64>[2] [256] node _T_20 = bits(io.write.bits.way_en, 5, 5) node _T_21 = and(_T_20, io.write.valid) when _T_21 : node _data_T_10 = bits(io.write.bits.data, 63, 0) node _data_T_11 = bits(io.write.bits.data, 127, 64) wire data_5 : UInt<64>[2] connect data_5[0], _data_T_10 connect data_5[1], _data_T_11 node _T_22 = bits(io.write.bits.wmask, 0, 0) node _T_23 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_5 = array_5_0[waddr], clock when _T_22 : connect MPORT_5[0], data_5[0] when _T_23 : connect MPORT_5[1], data_5[1] wire _io_resp_0_5_WIRE : UInt<8> invalidate _io_resp_0_5_WIRE when io.read[0].valid : connect _io_resp_0_5_WIRE, raddr read mport io_resp_0_5_MPORT = array_5_0[_io_resp_0_5_WIRE], clock node _io_resp_0_5_T = cat(io_resp_0_5_MPORT[1], io_resp_0_5_MPORT[0]) reg io_resp_0_5_REG : UInt, clock connect io_resp_0_5_REG, _io_resp_0_5_T connect io.resp[0][5], io_resp_0_5_REG smem array_6_0 : UInt<64>[2] [256] node _T_24 = bits(io.write.bits.way_en, 6, 6) node _T_25 = and(_T_24, io.write.valid) when _T_25 : node _data_T_12 = bits(io.write.bits.data, 63, 0) node _data_T_13 = bits(io.write.bits.data, 127, 64) wire data_6 : UInt<64>[2] connect data_6[0], _data_T_12 connect data_6[1], _data_T_13 node _T_26 = bits(io.write.bits.wmask, 0, 0) node _T_27 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_6 = array_6_0[waddr], clock when _T_26 : connect MPORT_6[0], data_6[0] when _T_27 : connect MPORT_6[1], data_6[1] wire _io_resp_0_6_WIRE : UInt<8> invalidate _io_resp_0_6_WIRE when io.read[0].valid : connect _io_resp_0_6_WIRE, raddr read mport io_resp_0_6_MPORT = array_6_0[_io_resp_0_6_WIRE], clock node _io_resp_0_6_T = cat(io_resp_0_6_MPORT[1], io_resp_0_6_MPORT[0]) reg io_resp_0_6_REG : UInt, clock connect io_resp_0_6_REG, _io_resp_0_6_T connect io.resp[0][6], io_resp_0_6_REG smem array_7_0 : UInt<64>[2] [256] node _T_28 = bits(io.write.bits.way_en, 7, 7) node _T_29 = and(_T_28, io.write.valid) when _T_29 : node _data_T_14 = bits(io.write.bits.data, 63, 0) node _data_T_15 = bits(io.write.bits.data, 127, 64) wire data_7 : UInt<64>[2] connect data_7[0], _data_T_14 connect data_7[1], _data_T_15 node _T_30 = bits(io.write.bits.wmask, 0, 0) node _T_31 = bits(io.write.bits.wmask, 1, 1) write mport MPORT_7 = array_7_0[waddr], clock when _T_30 : connect MPORT_7[0], data_7[0] when _T_31 : connect MPORT_7[1], data_7[1] wire _io_resp_0_7_WIRE : UInt<8> invalidate _io_resp_0_7_WIRE when io.read[0].valid : connect _io_resp_0_7_WIRE, raddr read mport io_resp_0_7_MPORT = array_7_0[_io_resp_0_7_WIRE], clock node _io_resp_0_7_T = cat(io_resp_0_7_MPORT[1], io_resp_0_7_MPORT[0]) reg io_resp_0_7_REG : UInt, clock connect io_resp_0_7_REG, _io_resp_0_7_T connect io.resp[0][7], io_resp_0_7_REG connect io.s1_nacks[0], UInt<1>(0h0)

module BoomDuplicatedDataArray( // @[dcache.scala:281:7] input clock, // @[dcache.scala:281:7] input reset, // @[dcache.scala:281:7] input io_read_0_valid, // @[dcache.scala:270:14] input [7:0] io_read_0_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_read_0_bits_addr, // @[dcache.scala:270:14] input io_write_valid, // @[dcache.scala:270:14] input [7:0] io_write_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_write_bits_addr, // @[dcache.scala:270:14] input [1:0] io_write_bits_wmask, // @[dcache.scala:270:14] input [127:0] io_write_bits_data, // @[dcache.scala:270:14] output [127:0] io_resp_0_0, // @[dcache.scala:270:14] output [127:0] io_resp_0_1, // @[dcache.scala:270:14] output [127:0] io_resp_0_2, // @[dcache.scala:270:14] output [127:0] io_resp_0_3, // @[dcache.scala:270:14] output [127:0] io_resp_0_4, // @[dcache.scala:270:14] output [127:0] io_resp_0_5, // @[dcache.scala:270:14] output [127:0] io_resp_0_6, // @[dcache.scala:270:14] output [127:0] io_resp_0_7 // @[dcache.scala:270:14] ); wire io_read_0_valid_0 = io_read_0_valid; // @[dcache.scala:281:7] wire [7:0] io_read_0_bits_way_en_0 = io_read_0_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_read_0_bits_addr_0 = io_read_0_bits_addr; // @[dcache.scala:281:7] wire io_write_valid_0 = io_write_valid; // @[dcache.scala:281:7] wire [7:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_write_bits_addr_0 = io_write_bits_addr; // @[dcache.scala:281:7] wire [1:0] io_write_bits_wmask_0 = io_write_bits_wmask; // @[dcache.scala:281:7] wire [127:0] io_write_bits_data_0 = io_write_bits_data; // @[dcache.scala:281:7] wire io_s1_nacks_0 = 1'h0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_0_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_1_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_2_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_3_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_4_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_5_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_6_0; // @[dcache.scala:281:7] wire [127:0] io_resp_0_7_0; // @[dcache.scala:281:7] wire [7:0] waddr = io_write_bits_addr_0[11:4]; // @[dcache.scala:281:7, :284:34] wire [7:0] raddr = io_read_0_bits_addr_0[11:4]; // @[dcache.scala:281:7, :287:38] wire [7:0] _io_resp_0_0_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_1_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_2_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_3_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_4_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_5_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_6_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [7:0] _io_resp_0_7_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [63:0] data_0; // @[dcache.scala:296:27] wire [63:0] data_1; // @[dcache.scala:296:27] wire [63:0] _data_T = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_2 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_4 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_6 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_8 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_10 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_12 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_14 = io_write_bits_data_0[63:0]; // @[dcache.scala:281:7, :296:75] assign data_0 = _data_T; // @[dcache.scala:296:{27,75}] wire [63:0] _data_T_1 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_3 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_5 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_7 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_9 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_11 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_13 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_15 = io_write_bits_data_0[127:64]; // @[dcache.scala:281:7, :296:75] assign data_1 = _data_T_1; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_0_REG; // @[dcache.scala:302:33] assign io_resp_0_0_0 = io_resp_0_0_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_1_0; // @[dcache.scala:296:27] wire [63:0] data_1_1; // @[dcache.scala:296:27] assign data_1_0 = _data_T_2; // @[dcache.scala:296:{27,75}] assign data_1_1 = _data_T_3; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_1_REG; // @[dcache.scala:302:33] assign io_resp_0_1_0 = io_resp_0_1_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_2_0; // @[dcache.scala:296:27] wire [63:0] data_2_1; // @[dcache.scala:296:27] assign data_2_0 = _data_T_4; // @[dcache.scala:296:{27,75}] assign data_2_1 = _data_T_5; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_2_REG; // @[dcache.scala:302:33] assign io_resp_0_2_0 = io_resp_0_2_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_3_0; // @[dcache.scala:296:27] wire [63:0] data_3_1; // @[dcache.scala:296:27] assign data_3_0 = _data_T_6; // @[dcache.scala:296:{27,75}] assign data_3_1 = _data_T_7; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_3_REG; // @[dcache.scala:302:33] assign io_resp_0_3_0 = io_resp_0_3_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_4_0; // @[dcache.scala:296:27] wire [63:0] data_4_1; // @[dcache.scala:296:27] assign data_4_0 = _data_T_8; // @[dcache.scala:296:{27,75}] assign data_4_1 = _data_T_9; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_4_REG; // @[dcache.scala:302:33] assign io_resp_0_4_0 = io_resp_0_4_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_5_0; // @[dcache.scala:296:27] wire [63:0] data_5_1; // @[dcache.scala:296:27] assign data_5_0 = _data_T_10; // @[dcache.scala:296:{27,75}] assign data_5_1 = _data_T_11; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_5_REG; // @[dcache.scala:302:33] assign io_resp_0_5_0 = io_resp_0_5_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_6_0; // @[dcache.scala:296:27] wire [63:0] data_6_1; // @[dcache.scala:296:27] assign data_6_0 = _data_T_12; // @[dcache.scala:296:{27,75}] assign data_6_1 = _data_T_13; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_6_REG; // @[dcache.scala:302:33] assign io_resp_0_6_0 = io_resp_0_6_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_7_0; // @[dcache.scala:296:27] wire [63:0] data_7_1; // @[dcache.scala:296:27] assign data_7_0 = _data_T_14; // @[dcache.scala:296:{27,75}] assign data_7_1 = _data_T_15; // @[dcache.scala:296:{27,75}] reg [127:0] io_resp_0_7_REG; // @[dcache.scala:302:33] assign io_resp_0_7_0 = io_resp_0_7_REG; // @[dcache.scala:281:7, :302:33] wire [127:0] _io_resp_0_0_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_1_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_2_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_3_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_4_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_5_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_6_T; // @[dcache.scala:302:70] wire [127:0] _io_resp_0_7_T; // @[dcache.scala:302:70] always @(posedge clock) begin // @[dcache.scala:281:7] io_resp_0_0_REG <= _io_resp_0_0_T; // @[dcache.scala:302:{33,70}] io_resp_0_1_REG <= _io_resp_0_1_T; // @[dcache.scala:302:{33,70}] io_resp_0_2_REG <= _io_resp_0_2_T; // @[dcache.scala:302:{33,70}] io_resp_0_3_REG <= _io_resp_0_3_T; // @[dcache.scala:302:{33,70}] io_resp_0_4_REG <= _io_resp_0_4_T; // @[dcache.scala:302:{33,70}] io_resp_0_5_REG <= _io_resp_0_5_T; // @[dcache.scala:302:{33,70}] io_resp_0_6_REG <= _io_resp_0_6_T; // @[dcache.scala:302:{33,70}] io_resp_0_7_REG <= _io_resp_0_7_T; // @[dcache.scala:302:{33,70}] always @(posedge) array_0_0 array_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_0_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_0_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[0] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_1, data_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_1_0 array_1_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_1_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_1_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[1] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_1_1, data_1_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_2_0 array_2_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_2_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_2_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[2] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_2_1, data_2_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_3_0 array_3_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_3_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_3_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[3] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_3_1, data_3_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_4_0 array_4_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_4_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_4_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[4] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_4_1, data_4_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_5_0 array_5_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_5_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_5_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[5] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_5_1, data_5_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_6_0 array_6_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_6_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_6_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[6] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_6_1, data_6_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] array_7_0 array_7_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_7_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_io_resp_0_7_T), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[7] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data ({data_7_1, data_7_0}), // @[DescribedSRAM.scala:17:26] .W0_mask (io_write_bits_wmask_0) // @[dcache.scala:281:7] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0_0 = io_resp_0_0_0; // @[dcache.scala:281:7] assign io_resp_0_1 = io_resp_0_1_0; // @[dcache.scala:281:7] assign io_resp_0_2 = io_resp_0_2_0; // @[dcache.scala:281:7] assign io_resp_0_3 = io_resp_0_3_0; // @[dcache.scala:281:7] assign io_resp_0_4 = io_resp_0_4_0; // @[dcache.scala:281:7] assign io_resp_0_5 = io_resp_0_5_0; // @[dcache.scala:281:7] assign io_resp_0_6 = io_resp_0_6_0; // @[dcache.scala:281:7] assign io_resp_0_7 = io_resp_0_7_0; // @[dcache.scala:281:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf)) node _T_76 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_77 = and(_T_75, _T_76) node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_79 = and(_T_77, _T_78) node _T_80 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_81 = and(_T_79, _T_80) node _T_82 = or(_T_53, _T_60) node _T_83 = or(_T_82, _T_67) node _T_84 = or(_T_83, _T_74) node _T_85 = or(_T_84, _T_81) node _T_86 = or(_T_46, _T_85) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_86, UInt<1>(0h1), "") : assert_3

module NoCMonitor_44( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module MemReader : input clock : Clock input reset : Reset output io : { flip addr : UInt<21>, flip size : UInt<2>, flip signed : UInt<1>, data : UInt<32>, mem_addr : UInt<19>, flip mem_data : UInt<8>[4]} node s_offset = bits(io.addr, 1, 0) node _io_mem_addr_T = bits(io.addr, 20, 2) connect io.mem_addr, _io_mem_addr_T node shiftedVec_lo = cat(io.mem_data[2], io.mem_data[3]) node shiftedVec_hi = cat(io.mem_data[0], io.mem_data[1]) node _shiftedVec_T = cat(shiftedVec_hi, shiftedVec_lo) node _shiftedVec_T_1 = shl(s_offset, 3) node _shiftedVec_T_2 = dshr(_shiftedVec_T, _shiftedVec_T_1) node _shiftedVec_T_3 = bits(_shiftedVec_T_2, 31, 0) node _shiftedVec_T_4 = bits(_shiftedVec_T_3, 0, 0) node _shiftedVec_T_5 = bits(_shiftedVec_T_3, 1, 1) node _shiftedVec_T_6 = bits(_shiftedVec_T_3, 2, 2) node _shiftedVec_T_7 = bits(_shiftedVec_T_3, 3, 3) node _shiftedVec_T_8 = bits(_shiftedVec_T_3, 4, 4) node _shiftedVec_T_9 = bits(_shiftedVec_T_3, 5, 5) node _shiftedVec_T_10 = bits(_shiftedVec_T_3, 6, 6) node _shiftedVec_T_11 = bits(_shiftedVec_T_3, 7, 7) node _shiftedVec_T_12 = bits(_shiftedVec_T_3, 8, 8) node _shiftedVec_T_13 = bits(_shiftedVec_T_3, 9, 9) node _shiftedVec_T_14 = bits(_shiftedVec_T_3, 10, 10) node _shiftedVec_T_15 = bits(_shiftedVec_T_3, 11, 11) node _shiftedVec_T_16 = bits(_shiftedVec_T_3, 12, 12) node _shiftedVec_T_17 = bits(_shiftedVec_T_3, 13, 13) node _shiftedVec_T_18 = bits(_shiftedVec_T_3, 14, 14) node _shiftedVec_T_19 = bits(_shiftedVec_T_3, 15, 15) node _shiftedVec_T_20 = bits(_shiftedVec_T_3, 16, 16) node _shiftedVec_T_21 = bits(_shiftedVec_T_3, 17, 17) node _shiftedVec_T_22 = bits(_shiftedVec_T_3, 18, 18) node _shiftedVec_T_23 = bits(_shiftedVec_T_3, 19, 19) node _shiftedVec_T_24 = bits(_shiftedVec_T_3, 20, 20) node _shiftedVec_T_25 = bits(_shiftedVec_T_3, 21, 21) node _shiftedVec_T_26 = bits(_shiftedVec_T_3, 22, 22) node _shiftedVec_T_27 = bits(_shiftedVec_T_3, 23, 23) node _shiftedVec_T_28 = bits(_shiftedVec_T_3, 24, 24) node _shiftedVec_T_29 = bits(_shiftedVec_T_3, 25, 25) node _shiftedVec_T_30 = bits(_shiftedVec_T_3, 26, 26) node _shiftedVec_T_31 = bits(_shiftedVec_T_3, 27, 27) node _shiftedVec_T_32 = bits(_shiftedVec_T_3, 28, 28) node _shiftedVec_T_33 = bits(_shiftedVec_T_3, 29, 29) node _shiftedVec_T_34 = bits(_shiftedVec_T_3, 30, 30) node _shiftedVec_T_35 = bits(_shiftedVec_T_3, 31, 31) node shiftedVec_lo_lo = cat(_shiftedVec_T_29, _shiftedVec_T_28) node shiftedVec_lo_hi = cat(_shiftedVec_T_31, _shiftedVec_T_30) node shiftedVec_lo_1 = cat(shiftedVec_lo_hi, shiftedVec_lo_lo) node shiftedVec_hi_lo = cat(_shiftedVec_T_33, _shiftedVec_T_32) node shiftedVec_hi_hi = cat(_shiftedVec_T_35, _shiftedVec_T_34) node shiftedVec_hi_1 = cat(shiftedVec_hi_hi, shiftedVec_hi_lo) node _shiftedVec_T_36 = cat(shiftedVec_hi_1, shiftedVec_lo_1) node shiftedVec_lo_lo_1 = cat(_shiftedVec_T_21, _shiftedVec_T_20) node shiftedVec_lo_hi_1 = cat(_shiftedVec_T_23, _shiftedVec_T_22) node shiftedVec_lo_2 = cat(shiftedVec_lo_hi_1, shiftedVec_lo_lo_1) node shiftedVec_hi_lo_1 = cat(_shiftedVec_T_25, _shiftedVec_T_24) node shiftedVec_hi_hi_1 = cat(_shiftedVec_T_27, _shiftedVec_T_26) node shiftedVec_hi_2 = cat(shiftedVec_hi_hi_1, shiftedVec_hi_lo_1) node _shiftedVec_T_37 = cat(shiftedVec_hi_2, shiftedVec_lo_2) node shiftedVec_lo_lo_2 = cat(_shiftedVec_T_13, _shiftedVec_T_12) node shiftedVec_lo_hi_2 = cat(_shiftedVec_T_15, _shiftedVec_T_14) node shiftedVec_lo_3 = cat(shiftedVec_lo_hi_2, shiftedVec_lo_lo_2) node shiftedVec_hi_lo_2 = cat(_shiftedVec_T_17, _shiftedVec_T_16) node shiftedVec_hi_hi_2 = cat(_shiftedVec_T_19, _shiftedVec_T_18) node shiftedVec_hi_3 = cat(shiftedVec_hi_hi_2, shiftedVec_hi_lo_2) node _shiftedVec_T_38 = cat(shiftedVec_hi_3, shiftedVec_lo_3) node shiftedVec_lo_lo_3 = cat(_shiftedVec_T_5, _shiftedVec_T_4) node shiftedVec_lo_hi_3 = cat(_shiftedVec_T_7, _shiftedVec_T_6) node shiftedVec_lo_4 = cat(shiftedVec_lo_hi_3, shiftedVec_lo_lo_3) node shiftedVec_hi_lo_3 = cat(_shiftedVec_T_9, _shiftedVec_T_8) node shiftedVec_hi_hi_3 = cat(_shiftedVec_T_11, _shiftedVec_T_10) node shiftedVec_hi_4 = cat(shiftedVec_hi_hi_3, shiftedVec_hi_lo_3) node _shiftedVec_T_39 = cat(shiftedVec_hi_4, shiftedVec_lo_4) wire shiftedVec : UInt<8>[4] connect shiftedVec[0], _shiftedVec_T_36 connect shiftedVec[1], _shiftedVec_T_37 connect shiftedVec[2], _shiftedVec_T_38 connect shiftedVec[3], _shiftedVec_T_39 node _bytes_T = eq(UInt<1>(0h0), io.size) node _bytes_T_1 = mux(_bytes_T, UInt<1>(0h0), UInt<2>(0h3)) node _bytes_T_2 = eq(UInt<1>(0h1), io.size) node _bytes_T_3 = mux(_bytes_T_2, UInt<1>(0h1), _bytes_T_1) node _bytes_T_4 = eq(UInt<2>(0h2), io.size) node bytes = mux(_bytes_T_4, UInt<2>(0h3), _bytes_T_3) node _sign_T = sub(UInt<2>(0h3), bytes) node _sign_T_1 = tail(_sign_T, 1) node sign = bits(shiftedVec[_sign_T_1], 7, 7) node _masks_mask_T = dshl(UInt<8>(0h1f), bytes) node masks_mask = bits(_masks_mask_T, 7, 4) node _masks_maskWithOffset_T = dshl(masks_mask, UInt<1>(0h0)) node masks_maskWithOffset = bits(_masks_maskWithOffset_T, 3, 0) node masks_3 = bits(masks_maskWithOffset, 0, 0) node masks_2 = bits(masks_maskWithOffset, 1, 1) node masks_1 = bits(masks_maskWithOffset, 2, 2) node masks_0 = bits(masks_maskWithOffset, 3, 3) node _maskedVec_T = and(sign, io.signed) node _maskedVec_T_1 = mux(masks_0, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_2 = not(_maskedVec_T_1) node _maskedVec_T_3 = or(shiftedVec[0], _maskedVec_T_2) node _maskedVec_T_4 = mux(masks_0, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_5 = and(shiftedVec[0], _maskedVec_T_4) node maskedVec_0 = mux(_maskedVec_T, _maskedVec_T_3, _maskedVec_T_5) node _maskedVec_T_6 = and(sign, io.signed) node _maskedVec_T_7 = mux(masks_1, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_8 = not(_maskedVec_T_7) node _maskedVec_T_9 = or(shiftedVec[1], _maskedVec_T_8) node _maskedVec_T_10 = mux(masks_1, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_11 = and(shiftedVec[1], _maskedVec_T_10) node maskedVec_1 = mux(_maskedVec_T_6, _maskedVec_T_9, _maskedVec_T_11) node _maskedVec_T_12 = and(sign, io.signed) node _maskedVec_T_13 = mux(masks_2, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_14 = not(_maskedVec_T_13) node _maskedVec_T_15 = or(shiftedVec[2], _maskedVec_T_14) node _maskedVec_T_16 = mux(masks_2, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_17 = and(shiftedVec[2], _maskedVec_T_16) node maskedVec_2 = mux(_maskedVec_T_12, _maskedVec_T_15, _maskedVec_T_17) node _maskedVec_T_18 = and(sign, io.signed) node _maskedVec_T_19 = mux(masks_3, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_20 = not(_maskedVec_T_19) node _maskedVec_T_21 = or(shiftedVec[3], _maskedVec_T_20) node _maskedVec_T_22 = mux(masks_3, UInt<8>(0hff), UInt<8>(0h0)) node _maskedVec_T_23 = and(shiftedVec[3], _maskedVec_T_22) node maskedVec_3 = mux(_maskedVec_T_18, _maskedVec_T_21, _maskedVec_T_23) node io_data_lo = cat(maskedVec_2, maskedVec_3) node io_data_hi = cat(maskedVec_0, maskedVec_1) node _io_data_T = cat(io_data_hi, io_data_lo) connect io.data, _io_data_T

module MemReader( // @[memory.scala:89:13] input clock, // @[memory.scala:89:13] input reset, // @[memory.scala:89:13] input [20:0] io_addr, // @[memory.scala:90:21] input [1:0] io_size, // @[memory.scala:90:21] input io_signed, // @[memory.scala:90:21] output [31:0] io_data, // @[memory.scala:90:21] output [18:0] io_mem_addr, // @[memory.scala:90:21] input [7:0] io_mem_data_0, // @[memory.scala:90:21] input [7:0] io_mem_data_1, // @[memory.scala:90:21] input [7:0] io_mem_data_2, // @[memory.scala:90:21] input [7:0] io_mem_data_3 // @[memory.scala:90:21] ); wire [20:0] io_addr_0 = io_addr; // @[memory.scala:89:13] wire [1:0] io_size_0 = io_size; // @[memory.scala:89:13] wire io_signed_0 = io_signed; // @[memory.scala:89:13] wire [7:0] io_mem_data_0_0 = io_mem_data_0; // @[memory.scala:89:13] wire [7:0] io_mem_data_1_0 = io_mem_data_1; // @[memory.scala:89:13] wire [7:0] io_mem_data_2_0 = io_mem_data_2; // @[memory.scala:89:13] wire [7:0] io_mem_data_3_0 = io_mem_data_3; // @[memory.scala:89:13] wire [31:0] _io_data_T; // @[memory.scala:117:24] wire [18:0] _io_mem_addr_T; // @[memory.scala:105:32] wire [31:0] io_data_0; // @[memory.scala:89:13] wire [18:0] io_mem_addr_0; // @[memory.scala:89:13] wire [1:0] s_offset = io_addr_0[1:0]; // @[memory.scala:89:13, :100:46] assign _io_mem_addr_T = io_addr_0[20:2]; // @[memory.scala:89:13, :105:32] assign io_mem_addr_0 = _io_mem_addr_T; // @[memory.scala:89:13, :105:32] wire [15:0] shiftedVec_lo = {io_mem_data_2_0, io_mem_data_3_0}; // @[memory.scala:89:13, :107:40] wire [15:0] shiftedVec_hi = {io_mem_data_0_0, io_mem_data_1_0}; // @[memory.scala:89:13, :107:40] wire [31:0] _shiftedVec_T = {shiftedVec_hi, shiftedVec_lo}; // @[memory.scala:107:40] wire [4:0] _shiftedVec_T_1 = {s_offset, 3'h0}; // @[memory.scala:100:46, :107:63] wire [31:0] _shiftedVec_T_2 = _shiftedVec_T >> _shiftedVec_T_1; // @[memory.scala:107:{40,50,63}] wire [31:0] _shiftedVec_T_3 = _shiftedVec_T_2; // @[memory.scala:84:54, :107:50] wire _shiftedVec_T_4 = _shiftedVec_T_3[0]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_5 = _shiftedVec_T_3[1]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_6 = _shiftedVec_T_3[2]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_7 = _shiftedVec_T_3[3]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_8 = _shiftedVec_T_3[4]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_9 = _shiftedVec_T_3[5]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_10 = _shiftedVec_T_3[6]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_11 = _shiftedVec_T_3[7]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_12 = _shiftedVec_T_3[8]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_13 = _shiftedVec_T_3[9]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_14 = _shiftedVec_T_3[10]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_15 = _shiftedVec_T_3[11]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_16 = _shiftedVec_T_3[12]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_17 = _shiftedVec_T_3[13]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_18 = _shiftedVec_T_3[14]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_19 = _shiftedVec_T_3[15]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_20 = _shiftedVec_T_3[16]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_21 = _shiftedVec_T_3[17]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_22 = _shiftedVec_T_3[18]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_23 = _shiftedVec_T_3[19]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_24 = _shiftedVec_T_3[20]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_25 = _shiftedVec_T_3[21]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_26 = _shiftedVec_T_3[22]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_27 = _shiftedVec_T_3[23]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_28 = _shiftedVec_T_3[24]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_29 = _shiftedVec_T_3[25]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_30 = _shiftedVec_T_3[26]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_31 = _shiftedVec_T_3[27]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_32 = _shiftedVec_T_3[28]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_33 = _shiftedVec_T_3[29]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_34 = _shiftedVec_T_3[30]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_35 = _shiftedVec_T_3[31]; // @[memory.scala:84:{54,62}] wire [1:0] shiftedVec_lo_lo = {_shiftedVec_T_29, _shiftedVec_T_28}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi = {_shiftedVec_T_31, _shiftedVec_T_30}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_1 = {shiftedVec_lo_hi, shiftedVec_lo_lo}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo = {_shiftedVec_T_33, _shiftedVec_T_32}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi = {_shiftedVec_T_35, _shiftedVec_T_34}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_1 = {shiftedVec_hi_hi, shiftedVec_hi_lo}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_36 = {shiftedVec_hi_1, shiftedVec_lo_1}; // @[memory.scala:84:106] wire [7:0] shiftedVec_0 = _shiftedVec_T_36; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_1 = {_shiftedVec_T_21, _shiftedVec_T_20}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_1 = {_shiftedVec_T_23, _shiftedVec_T_22}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_2 = {shiftedVec_lo_hi_1, shiftedVec_lo_lo_1}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_1 = {_shiftedVec_T_25, _shiftedVec_T_24}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_1 = {_shiftedVec_T_27, _shiftedVec_T_26}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_2 = {shiftedVec_hi_hi_1, shiftedVec_hi_lo_1}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_37 = {shiftedVec_hi_2, shiftedVec_lo_2}; // @[memory.scala:84:106] wire [7:0] shiftedVec_1 = _shiftedVec_T_37; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_2 = {_shiftedVec_T_13, _shiftedVec_T_12}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_2 = {_shiftedVec_T_15, _shiftedVec_T_14}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_3 = {shiftedVec_lo_hi_2, shiftedVec_lo_lo_2}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_2 = {_shiftedVec_T_17, _shiftedVec_T_16}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_2 = {_shiftedVec_T_19, _shiftedVec_T_18}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_3 = {shiftedVec_hi_hi_2, shiftedVec_hi_lo_2}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_38 = {shiftedVec_hi_3, shiftedVec_lo_3}; // @[memory.scala:84:106] wire [7:0] shiftedVec_2 = _shiftedVec_T_38; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_3 = {_shiftedVec_T_5, _shiftedVec_T_4}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_3 = {_shiftedVec_T_7, _shiftedVec_T_6}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_4 = {shiftedVec_lo_hi_3, shiftedVec_lo_lo_3}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_3 = {_shiftedVec_T_9, _shiftedVec_T_8}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_3 = {_shiftedVec_T_11, _shiftedVec_T_10}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_4 = {shiftedVec_hi_hi_3, shiftedVec_hi_lo_3}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_39 = {shiftedVec_hi_4, shiftedVec_lo_4}; // @[memory.scala:84:106] wire [7:0] shiftedVec_3 = _shiftedVec_T_39; // @[memory.scala:84:{47,106}] wire _bytes_T = io_size_0 == 2'h0; // @[memory.scala:76:62, :89:13] wire [1:0] _bytes_T_1 = _bytes_T ? 2'h0 : 2'h3; // @[memory.scala:76:62] wire _bytes_T_2 = io_size_0 == 2'h1; // @[memory.scala:76:62, :89:13] wire [1:0] _bytes_T_3 = _bytes_T_2 ? 2'h1 : _bytes_T_1; // @[memory.scala:76:62] wire _bytes_T_4 = io_size_0 == 2'h2; // @[memory.scala:76:62, :89:13] wire [1:0] bytes = _bytes_T_4 ? 2'h3 : _bytes_T_3; // @[memory.scala:76:62] wire [2:0] _sign_T = 3'h3 - {1'h0, bytes}; // @[memory.scala:76:62, :111:36] wire [1:0] _sign_T_1 = _sign_T[1:0]; // @[memory.scala:111:36] wire [3:0][7:0] _GEN = {{shiftedVec_3}, {shiftedVec_2}, {shiftedVec_1}, {shiftedVec_0}}; // @[memory.scala:84:47, :111:50] wire sign = _GEN[_sign_T_1][7]; // @[memory.scala:111:{36,50}] wire [10:0] _masks_mask_T = 11'h1F << bytes; // @[memory.scala:76:62, :79:38] wire [3:0] masks_mask = _masks_mask_T[7:4]; // @[memory.scala:79:{38,53}] wire [4:0] _masks_maskWithOffset_T = {1'h0, masks_mask}; // @[memory.scala:76:62, :79:53, :80:34] wire [3:0] masks_maskWithOffset = _masks_maskWithOffset_T[3:0]; // @[memory.scala:80:{34,55}] wire masks_3 = masks_maskWithOffset[0]; // @[memory.scala:80:55, :81:22] wire masks_2 = masks_maskWithOffset[1]; // @[memory.scala:80:55, :81:22] wire masks_1 = masks_maskWithOffset[2]; // @[memory.scala:80:55, :81:22] wire masks_0 = masks_maskWithOffset[3]; // @[memory.scala:80:55, :81:22] wire _GEN_0 = sign & io_signed_0; // @[memory.scala:89:13, :111:50, :114:22] wire _maskedVec_T; // @[memory.scala:114:22] assign _maskedVec_T = _GEN_0; // @[memory.scala:114:22] wire _maskedVec_T_6; // @[memory.scala:114:22] assign _maskedVec_T_6 = _GEN_0; // @[memory.scala:114:22] wire _maskedVec_T_12; // @[memory.scala:114:22] assign _maskedVec_T_12 = _GEN_0; // @[memory.scala:114:22] wire _maskedVec_T_18; // @[memory.scala:114:22] assign _maskedVec_T_18 = _GEN_0; // @[memory.scala:114:22] wire [7:0] _GEN_1 = {8{masks_0}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_1; // @[memory.scala:114:47] assign _maskedVec_T_1 = _GEN_1; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_4; // @[memory.scala:114:69] assign _maskedVec_T_4 = _GEN_1; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_2 = ~_maskedVec_T_1; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_3 = shiftedVec_0 | _maskedVec_T_2; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_5 = shiftedVec_0 & _maskedVec_T_4; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_0 = _maskedVec_T ? _maskedVec_T_3 : _maskedVec_T_5; // @[memory.scala:114:{16,22,40,63}] wire [7:0] _GEN_2 = {8{masks_1}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_7; // @[memory.scala:114:47] assign _maskedVec_T_7 = _GEN_2; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_10; // @[memory.scala:114:69] assign _maskedVec_T_10 = _GEN_2; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_8 = ~_maskedVec_T_7; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_9 = shiftedVec_1 | _maskedVec_T_8; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_11 = shiftedVec_1 & _maskedVec_T_10; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_1 = _maskedVec_T_6 ? _maskedVec_T_9 : _maskedVec_T_11; // @[memory.scala:114:{16,22,40,63}] wire [7:0] _GEN_3 = {8{masks_2}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_13; // @[memory.scala:114:47] assign _maskedVec_T_13 = _GEN_3; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_16; // @[memory.scala:114:69] assign _maskedVec_T_16 = _GEN_3; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_14 = ~_maskedVec_T_13; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_15 = shiftedVec_2 | _maskedVec_T_14; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_17 = shiftedVec_2 & _maskedVec_T_16; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_2 = _maskedVec_T_12 ? _maskedVec_T_15 : _maskedVec_T_17; // @[memory.scala:114:{16,22,40,63}] wire [7:0] _GEN_4 = {8{masks_3}}; // @[memory.scala:81:22, :114:47] wire [7:0] _maskedVec_T_19; // @[memory.scala:114:47] assign _maskedVec_T_19 = _GEN_4; // @[memory.scala:114:47] wire [7:0] _maskedVec_T_22; // @[memory.scala:114:69] assign _maskedVec_T_22 = _GEN_4; // @[memory.scala:114:{47,69}] wire [7:0] _maskedVec_T_20 = ~_maskedVec_T_19; // @[memory.scala:114:{42,47}] wire [7:0] _maskedVec_T_21 = shiftedVec_3 | _maskedVec_T_20; // @[memory.scala:84:47, :114:{40,42}] wire [7:0] _maskedVec_T_23 = shiftedVec_3 & _maskedVec_T_22; // @[memory.scala:84:47, :114:{63,69}] wire [7:0] maskedVec_3 = _maskedVec_T_18 ? _maskedVec_T_21 : _maskedVec_T_23; // @[memory.scala:114:{16,22,40,63}] wire [15:0] io_data_lo = {maskedVec_2, maskedVec_3}; // @[memory.scala:114:16, :117:24] wire [15:0] io_data_hi = {maskedVec_0, maskedVec_1}; // @[memory.scala:114:16, :117:24] assign _io_data_T = {io_data_hi, io_data_lo}; // @[memory.scala:117:24] assign io_data_0 = _io_data_T; // @[memory.scala:89:13, :117:24] assign io_data = io_data_0; // @[memory.scala:89:13] assign io_mem_addr = io_mem_addr_0; // @[memory.scala:89:13] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_188 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_188( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_36 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_327 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_36( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_327 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_51 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync

module IntSyncSyncCrossingSink_n1x1_51( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Router_31 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_85 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_11 of InputUnit_85 connect input_unit_0_from_11.clock, clock connect input_unit_0_from_11.reset, reset inst ingress_unit_1_from_12 of IngressUnit_48 connect ingress_unit_1_from_12.clock, clock connect ingress_unit_1_from_12.reset, reset inst output_unit_0_to_14 of OutputUnit_85 connect output_unit_0_to_14.clock, clock connect output_unit_0_to_14.reset, reset inst egress_unit_1_to_12 of EgressUnit_40 connect egress_unit_1_to_12.clock, clock connect egress_unit_1_to_12.reset, reset inst switch of Switch_31 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_31 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_31 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_31 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_3 connect input_unit_0_from_11.io.in, destNodesIn connect ingress_unit_1_from_12.io.in, ingressNodesIn.flit connect output_unit_0_to_14.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_14.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_14.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_12.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_12.io.out.valid connect egress_unit_1_to_12.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_11.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_12.io.router_req connect input_unit_0_from_11.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_12.io.router_resp, route_computer.io.resp.`1` connect vc_allocator.io.req.`0`, input_unit_0_from_11.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_12.io.vcalloc_req connect input_unit_0_from_11.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_12.io.vcalloc_resp, vc_allocator.io.resp.`1` connect output_unit_0_to_14.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_12.io.allocs, vc_allocator.io.out_allocs.`1` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_14.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_14.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_14.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_14.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_14.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_14.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_14.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_14.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_14.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_14.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_14.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_14.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_12.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_12.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_12.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_12.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_12.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_12.io.channel_status[0].occupied connect input_unit_0_from_11.io.out_credit_available.`0`[0], output_unit_0_to_14.io.credit_available[0] connect input_unit_0_from_11.io.out_credit_available.`0`[1], output_unit_0_to_14.io.credit_available[1] connect input_unit_0_from_11.io.out_credit_available.`1`[0], egress_unit_1_to_12.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[0], output_unit_0_to_14.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[1], output_unit_0_to_14.io.credit_available[1] connect ingress_unit_1_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_12.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_11.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_12.io.salloc_req[0] connect output_unit_0_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_14.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_14.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect egress_unit_1_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_11.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_12.io.out[0] connect output_unit_0_to_14.io.in, switch.io.out.`0` connect egress_unit_1_to_12.io.in, switch.io.out.`1` connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0] connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0] connect input_unit_0_from_11.io.block, UInt<1>(0h0) connect ingress_unit_1_from_12.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_11.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_12.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_11.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_12.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_57 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 11 15 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i12 15 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d 15 e12 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20

module Router_31( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_12_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_12_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_12_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_14_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_14_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_11_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_11_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_11_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_12_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module LCG_4 : input clock : Clock input reset : Reset output io : { out : UInt<5>, flip inc : UInt<1>} inst outs_lcg of LCG16_5 connect outs_lcg.clock, clock connect outs_lcg.reset, reset connect outs_lcg.io.inc, io.inc connect io.out, outs_lcg.io.out

module LCG_4( // @[LCG.scala:30:7] input clock, // @[LCG.scala:30:7] input reset, // @[LCG.scala:30:7] output [4:0] io_out // @[LCG.scala:31:14] ); wire [15:0] _outs_lcg_io_out; // @[LCG.scala:43:21] wire io_inc = 1'h1; // @[LCG.scala:30:7, :31:14, :43:21] wire [4:0] io_out_0; // @[LCG.scala:30:7] assign io_out_0 = _outs_lcg_io_out[4:0]; // @[LCG.scala:30:7, :38:10, :43:21] LCG16_5 outs_lcg ( // @[LCG.scala:43:21] .clock (clock), .reset (reset), .io_out (_outs_lcg_io_out) ); // @[LCG.scala:43:21] assign io_out = io_out_0; // @[LCG.scala:30:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_3 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e11_s53_3( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DatPath : input clock : Clock input reset : Reset output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip imem : { flip req : { valid : UInt<1>, bits : { pc : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<32>, inst : UInt<32>}}, debug : { if_pc : UInt<32>, if_inst : UInt<32>}, imiss : UInt<1>, flip exe_kill : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ctl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}, dat : { br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, inst_misaligned : UInt<1>, data_misaligned : UInt<1>, wb_hazard_stall : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt} invalidate io.hartid invalidate io.interrupt.meip invalidate io.interrupt.msip invalidate io.interrupt.mtip invalidate io.interrupt.debug invalidate io.dat.csr_interrupt invalidate io.dat.csr_eret invalidate io.dat.wb_hazard_stall invalidate io.dat.data_misaligned invalidate io.dat.inst_misaligned invalidate io.dat.br_ltu invalidate io.dat.br_lt invalidate io.dat.br_eq invalidate io.ctl.exception_cause invalidate io.ctl.exception invalidate io.ctl.dmem_typ invalidate io.ctl.dmem_fcn invalidate io.ctl.dmem_val invalidate io.ctl.csr_cmd invalidate io.ctl.bypassable invalidate io.ctl.rf_wen invalidate io.ctl.wb_sel invalidate io.ctl.alu_fun invalidate io.ctl.op2_sel invalidate io.ctl.op1_sel invalidate io.ctl.brjmp_sel invalidate io.ctl.pc_sel invalidate io.ctl.exe_kill invalidate io.dmem.resp.bits.data invalidate io.dmem.resp.valid invalidate io.dmem.req.bits.typ invalidate io.dmem.req.bits.fcn invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.addr invalidate io.dmem.req.valid invalidate io.dmem.req.ready invalidate io.imem.exe_kill invalidate io.imem.imiss invalidate io.imem.debug.if_inst invalidate io.imem.debug.if_pc invalidate io.imem.resp.bits.inst invalidate io.imem.resp.bits.pc invalidate io.imem.resp.valid invalidate io.imem.resp.ready invalidate io.imem.req.bits.pc invalidate io.imem.req.valid invalidate io.ddpath.resetpc invalidate io.ddpath.rdata invalidate io.ddpath.validreq invalidate io.ddpath.wdata invalidate io.ddpath.addr wire tval_data_ma : UInt<32> wire tval_inst_ma : UInt<32> regreset wb_reg_inst : UInt<32>, clock, reset, UInt<32>(0h4033) regreset wb_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg wb_reg_ctrl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}, clock reg wb_reg_pc : UInt<32>, clock reg wb_reg_alu : UInt<32>, clock reg wb_reg_csr_addr : UInt<12>, clock reg wb_reg_wbaddr : UInt<5>, clock reg wb_reg_target_pc : UInt<32>, clock regreset wb_reg_mem : UInt<1>, clock, reset, UInt<1>(0h0) wire wb_hazard_stall : UInt<1> wire wb_dmiss_stall : UInt<1> wire exe_brjmp_target : UInt<32> wire exe_jump_reg_target : UInt<32> wire exception_target : UInt<32> node _io_imem_resp_ready_T = eq(wb_hazard_stall, UInt<1>(0h0)) node _io_imem_resp_ready_T_1 = eq(wb_dmiss_stall, UInt<1>(0h0)) node _io_imem_resp_ready_T_2 = and(_io_imem_resp_ready_T, _io_imem_resp_ready_T_1) connect io.imem.resp.ready, _io_imem_resp_ready_T_2 node _take_pc_T = eq(io.ctl.pc_sel, UInt<3>(0h4)) node _take_pc_T_1 = eq(io.ctl.pc_sel, UInt<3>(0h3)) node _take_pc_T_2 = mux(_take_pc_T_1, exe_jump_reg_target, exe_brjmp_target) node take_pc = mux(_take_pc_T, exception_target, _take_pc_T_2) node _io_dat_inst_misaligned_T = bits(exe_brjmp_target, 1, 0) node _io_dat_inst_misaligned_T_1 = orr(_io_dat_inst_misaligned_T) node _io_dat_inst_misaligned_T_2 = eq(io.ctl.pc_sel, UInt<3>(0h1)) node _io_dat_inst_misaligned_T_3 = eq(io.ctl.pc_sel, UInt<3>(0h2)) node _io_dat_inst_misaligned_T_4 = or(_io_dat_inst_misaligned_T_2, _io_dat_inst_misaligned_T_3) node _io_dat_inst_misaligned_T_5 = and(_io_dat_inst_misaligned_T_1, _io_dat_inst_misaligned_T_4) node _io_dat_inst_misaligned_T_6 = bits(exe_jump_reg_target, 1, 0) node _io_dat_inst_misaligned_T_7 = orr(_io_dat_inst_misaligned_T_6) node _io_dat_inst_misaligned_T_8 = eq(io.ctl.pc_sel, UInt<3>(0h3)) node _io_dat_inst_misaligned_T_9 = and(_io_dat_inst_misaligned_T_7, _io_dat_inst_misaligned_T_8) node _io_dat_inst_misaligned_T_10 = or(_io_dat_inst_misaligned_T_5, _io_dat_inst_misaligned_T_9) node _io_dat_inst_misaligned_T_11 = and(_io_dat_inst_misaligned_T_10, io.imem.resp.valid) connect io.dat.inst_misaligned, _io_dat_inst_misaligned_T_11 node _exe_target_pc_T = eq(io.ctl.pc_sel, UInt<3>(0h3)) node exe_target_pc = mux(_exe_target_pc_T, exe_jump_reg_target, exe_brjmp_target) connect io.imem.req.bits.pc, take_pc node exe_rs1_addr = bits(io.imem.resp.bits.inst, 19, 15) node exe_rs2_addr = bits(io.imem.resp.bits.inst, 24, 20) node exe_wbaddr = bits(io.imem.resp.bits.inst, 11, 7) wire wb_wbdata : UInt<32> connect io.dat.wb_hazard_stall, wb_hazard_stall node _wb_hazard_stall_T = eq(wb_reg_wbaddr, exe_rs1_addr) node _wb_hazard_stall_T_1 = neq(exe_rs1_addr, UInt<1>(0h0)) node _wb_hazard_stall_T_2 = and(_wb_hazard_stall_T, _wb_hazard_stall_T_1) node _wb_hazard_stall_T_3 = and(_wb_hazard_stall_T_2, wb_reg_ctrl.rf_wen) node _wb_hazard_stall_T_4 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0)) node _wb_hazard_stall_T_5 = and(_wb_hazard_stall_T_3, _wb_hazard_stall_T_4) node _wb_hazard_stall_T_6 = eq(wb_reg_wbaddr, exe_rs2_addr) node _wb_hazard_stall_T_7 = neq(exe_rs2_addr, UInt<1>(0h0)) node _wb_hazard_stall_T_8 = and(_wb_hazard_stall_T_6, _wb_hazard_stall_T_7) node _wb_hazard_stall_T_9 = and(_wb_hazard_stall_T_8, wb_reg_ctrl.rf_wen) node _wb_hazard_stall_T_10 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0)) node _wb_hazard_stall_T_11 = and(_wb_hazard_stall_T_9, _wb_hazard_stall_T_10) node _wb_hazard_stall_T_12 = or(_wb_hazard_stall_T_5, _wb_hazard_stall_T_11) connect wb_hazard_stall, _wb_hazard_stall_T_12 cmem regfile : UInt<32> [32] infer mport io_ddpath_rdata_MPORT = regfile[io.ddpath.addr], clock connect io.ddpath.rdata, io_ddpath_rdata_MPORT when io.ddpath.validreq : infer mport MPORT = regfile[io.ddpath.addr], clock connect MPORT, io.ddpath.wdata node _T = neq(wb_reg_wbaddr, UInt<1>(0h0)) node _T_1 = and(wb_reg_ctrl.rf_wen, _T) node _T_2 = eq(wb_dmiss_stall, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(io.ctl.exception, UInt<1>(0h0)) node _T_5 = and(_T_3, _T_4) when _T_5 : infer mport MPORT_1 = regfile[wb_reg_wbaddr], clock connect MPORT_1, wb_wbdata node _rf_rs1_data_T = neq(exe_rs1_addr, UInt<1>(0h0)) infer mport rf_rs1_data_MPORT = regfile[exe_rs1_addr], clock node rf_rs1_data = mux(_rf_rs1_data_T, rf_rs1_data_MPORT, UInt<32>(0h0)) node _rf_rs2_data_T = neq(exe_rs2_addr, UInt<1>(0h0)) infer mport rf_rs2_data_MPORT = regfile[exe_rs2_addr], clock node rf_rs2_data = mux(_rf_rs2_data_T, rf_rs2_data_MPORT, UInt<32>(0h0)) node imm_i = bits(io.imem.resp.bits.inst, 31, 20) node _imm_s_T = bits(io.imem.resp.bits.inst, 31, 25) node _imm_s_T_1 = bits(io.imem.resp.bits.inst, 11, 7) node imm_s = cat(_imm_s_T, _imm_s_T_1) node _imm_b_T = bits(io.imem.resp.bits.inst, 31, 31) node _imm_b_T_1 = bits(io.imem.resp.bits.inst, 7, 7) node _imm_b_T_2 = bits(io.imem.resp.bits.inst, 30, 25) node _imm_b_T_3 = bits(io.imem.resp.bits.inst, 11, 8) node imm_b_lo = cat(_imm_b_T_2, _imm_b_T_3) node imm_b_hi = cat(_imm_b_T, _imm_b_T_1) node imm_b = cat(imm_b_hi, imm_b_lo) node _imm_u_T = bits(io.imem.resp.bits.inst, 31, 12) node _imm_u_T_1 = mux(UInt<1>(0h0), UInt<12>(0hfff), UInt<12>(0h0)) node imm_u = cat(_imm_u_T, _imm_u_T_1) node _imm_j_T = bits(io.imem.resp.bits.inst, 31, 31) node _imm_j_T_1 = bits(io.imem.resp.bits.inst, 19, 12) node _imm_j_T_2 = bits(io.imem.resp.bits.inst, 20, 20) node _imm_j_T_3 = bits(io.imem.resp.bits.inst, 30, 21) node imm_j_lo = cat(_imm_j_T_2, _imm_j_T_3) node imm_j_hi = cat(_imm_j_T, _imm_j_T_1) node imm_j = cat(imm_j_hi, imm_j_lo) node imm_z = bits(io.imem.resp.bits.inst, 19, 15) node _imm_i_sext_T = bits(imm_i, 11, 11) node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) node _imm_s_sext_T = bits(imm_s, 11, 11) node _imm_s_sext_T_1 = mux(_imm_s_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_s_sext = cat(_imm_s_sext_T_1, imm_s) node _imm_b_sext_T = bits(imm_b, 11, 11) node _imm_b_sext_T_1 = mux(_imm_b_sext_T, UInt<19>(0h7ffff), UInt<19>(0h0)) node imm_b_sext_hi = cat(_imm_b_sext_T_1, imm_b) node imm_b_sext = cat(imm_b_sext_hi, UInt<1>(0h0)) node _imm_j_sext_T = bits(imm_j, 19, 19) node _imm_j_sext_T_1 = mux(_imm_j_sext_T, UInt<11>(0h7ff), UInt<11>(0h0)) node imm_j_sext_hi = cat(_imm_j_sext_T_1, imm_j) node imm_j_sext = cat(imm_j_sext_hi, UInt<1>(0h0)) node _exe_rs1_data_T = eq(wb_reg_wbaddr, exe_rs1_addr) node _exe_rs1_data_T_1 = neq(exe_rs1_addr, UInt<1>(0h0)) node _exe_rs1_data_T_2 = and(_exe_rs1_data_T, _exe_rs1_data_T_1) node _exe_rs1_data_T_3 = and(_exe_rs1_data_T_2, wb_reg_ctrl.rf_wen) node _exe_rs1_data_T_4 = and(_exe_rs1_data_T_3, wb_reg_ctrl.bypassable) node exe_rs1_data = mux(_exe_rs1_data_T_4, wb_reg_alu, rf_rs1_data) node _exe_rs2_data_T = eq(wb_reg_wbaddr, exe_rs2_addr) node _exe_rs2_data_T_1 = neq(exe_rs2_addr, UInt<1>(0h0)) node _exe_rs2_data_T_2 = and(_exe_rs2_data_T, _exe_rs2_data_T_1) node _exe_rs2_data_T_3 = and(_exe_rs2_data_T_2, wb_reg_ctrl.rf_wen) node _exe_rs2_data_T_4 = and(_exe_rs2_data_T_3, wb_reg_ctrl.bypassable) node exe_rs2_data = mux(_exe_rs2_data_T_4, wb_reg_alu, rf_rs2_data) node _exe_alu_op1_T = eq(io.ctl.op1_sel, UInt<2>(0h2)) node _exe_alu_op1_T_1 = eq(io.ctl.op1_sel, UInt<2>(0h1)) node _exe_alu_op1_T_2 = mux(_exe_alu_op1_T_1, imm_u, exe_rs1_data) node exe_alu_op1 = mux(_exe_alu_op1_T, imm_z, _exe_alu_op1_T_2) node _exe_alu_op2_T = eq(io.ctl.op2_sel, UInt<2>(0h1)) node _exe_alu_op2_T_1 = eq(io.ctl.op2_sel, UInt<2>(0h3)) node _exe_alu_op2_T_2 = eq(io.ctl.op2_sel, UInt<2>(0h2)) node _exe_alu_op2_T_3 = mux(_exe_alu_op2_T_2, imm_s_sext, exe_rs2_data) node _exe_alu_op2_T_4 = mux(_exe_alu_op2_T_1, io.imem.resp.bits.pc, _exe_alu_op2_T_3) node exe_alu_op2 = mux(_exe_alu_op2_T, imm_i_sext, _exe_alu_op2_T_4) inst alu of ALU connect alu.clock, clock connect alu.reset, reset connect alu.io.in1, exe_alu_op1 connect alu.io.in2, exe_alu_op2 connect alu.io.fn, io.ctl.alu_fun node imm_brjmp = mux(io.ctl.brjmp_sel, imm_j_sext, imm_b_sext) node _exe_brjmp_target_T = add(io.imem.resp.bits.pc, imm_brjmp) node _exe_brjmp_target_T_1 = tail(_exe_brjmp_target_T, 1) connect exe_brjmp_target, _exe_brjmp_target_T_1 node _exe_jump_reg_target_T = not(UInt<32>(0h1)) node _exe_jump_reg_target_T_1 = and(alu.io.adder_out, _exe_jump_reg_target_T) connect exe_jump_reg_target, _exe_jump_reg_target_T_1 node _io_dat_br_eq_T = eq(exe_rs1_data, exe_rs2_data) connect io.dat.br_eq, _io_dat_br_eq_T node _io_dat_br_lt_T = asSInt(exe_rs1_data) node _io_dat_br_lt_T_1 = asSInt(exe_rs2_data) node _io_dat_br_lt_T_2 = lt(_io_dat_br_lt_T, _io_dat_br_lt_T_1) connect io.dat.br_lt, _io_dat_br_lt_T_2 node _io_dat_br_ltu_T = lt(exe_rs1_data, exe_rs2_data) connect io.dat.br_ltu, _io_dat_br_ltu_T node mem_address_low = bits(alu.io.out, 2, 0) wire misaligned_mask : UInt<3> node _misaligned_mask_T = sub(io.ctl.dmem_typ, UInt<1>(0h1)) node _misaligned_mask_T_1 = tail(_misaligned_mask_T, 1) node _misaligned_mask_T_2 = bits(_misaligned_mask_T_1, 1, 0) node _misaligned_mask_T_3 = dshl(UInt<3>(0h7), _misaligned_mask_T_2) node _misaligned_mask_T_4 = not(_misaligned_mask_T_3) connect misaligned_mask, _misaligned_mask_T_4 node _io_dat_data_misaligned_T = and(misaligned_mask, mem_address_low) node _io_dat_data_misaligned_T_1 = orr(_io_dat_data_misaligned_T) node _io_dat_data_misaligned_T_2 = and(_io_dat_data_misaligned_T_1, io.ctl.dmem_val) connect io.dat.data_misaligned, _io_dat_data_misaligned_T_2 node _io_dmem_req_valid_T = eq(io.dat.data_misaligned, UInt<1>(0h0)) node _io_dmem_req_valid_T_1 = and(io.ctl.dmem_val, _io_dmem_req_valid_T) node _io_dmem_req_valid_T_2 = eq(wb_hazard_stall, UInt<1>(0h0)) node _io_dmem_req_valid_T_3 = and(_io_dmem_req_valid_T_1, _io_dmem_req_valid_T_2) connect io.dmem.req.valid, _io_dmem_req_valid_T_3 node _io_dmem_req_bits_fcn_T = eq(wb_hazard_stall, UInt<1>(0h0)) node _io_dmem_req_bits_fcn_T_1 = and(io.ctl.dmem_fcn, _io_dmem_req_bits_fcn_T) node _io_dmem_req_bits_fcn_T_2 = and(_io_dmem_req_bits_fcn_T_1, io.imem.resp.valid) connect io.dmem.req.bits.fcn, _io_dmem_req_bits_fcn_T_2 connect io.dmem.req.bits.typ, io.ctl.dmem_typ connect io.dmem.req.bits.addr, alu.io.out connect io.dmem.req.bits.data, exe_rs2_data node _wb_dmiss_stall_T = eq(io.dmem.req.ready, UInt<1>(0h0)) node _wb_dmiss_stall_T_1 = and(_wb_dmiss_stall_T, io.dmem.req.valid) node _wb_dmiss_stall_T_2 = eq(io.dmem.resp.valid, UInt<1>(0h0)) node _wb_dmiss_stall_T_3 = and(wb_reg_mem, _wb_dmiss_stall_T_2) node _wb_dmiss_stall_T_4 = or(_wb_dmiss_stall_T_1, _wb_dmiss_stall_T_3) connect wb_dmiss_stall, _wb_dmiss_stall_T_4 node _T_6 = eq(wb_dmiss_stall, UInt<1>(0h0)) when _T_6 : node _T_7 = or(wb_hazard_stall, io.ctl.exe_kill) node _T_8 = eq(io.imem.resp.valid, UInt<1>(0h0)) node _T_9 = or(_T_7, _T_8) when _T_9 : connect wb_reg_inst, UInt<32>(0h4033) connect wb_reg_valid, UInt<1>(0h0) connect wb_reg_ctrl.rf_wen, UInt<1>(0h0) connect wb_reg_ctrl.csr_cmd, UInt<3>(0h0) connect wb_reg_ctrl.dmem_val, UInt<1>(0h0) connect wb_reg_ctrl.exception, UInt<1>(0h0) connect wb_reg_mem, UInt<1>(0h0) else : connect wb_reg_inst, io.imem.resp.bits.inst connect wb_reg_valid, io.imem.resp.valid connect wb_reg_ctrl, io.ctl connect wb_reg_pc, io.imem.resp.bits.pc connect wb_reg_alu, alu.io.out connect wb_reg_wbaddr, exe_wbaddr node _wb_reg_csr_addr_T = bits(io.imem.resp.bits.inst, 31, 20) connect wb_reg_csr_addr, _wb_reg_csr_addr_T connect wb_reg_target_pc, exe_target_pc connect wb_reg_mem, io.dmem.req.valid wire _hits_WIRE : UInt<1>[1] connect _hits_WIRE[0], UInt<1>(0h0) wire hits : UInt<1>[1] connect hits, _hits_WIRE inst csr of CSRFile connect csr.clock, clock connect csr.reset, reset invalidate csr.io.fiom invalidate csr.io.scontext invalidate csr.io.mcontext invalidate csr.io.trace[0].tval invalidate csr.io.trace[0].cause invalidate csr.io.trace[0].interrupt invalidate csr.io.trace[0].exception invalidate csr.io.trace[0].priv invalidate csr.io.trace[0].insn invalidate csr.io.trace[0].iaddr invalidate csr.io.trace[0].valid invalidate csr.io.inst[0] invalidate csr.io.inhibit_cycle invalidate csr.io.csrw_counter invalidate csr.io.interrupt_cause invalidate csr.io.interrupt invalidate csr.io.rocc_interrupt invalidate csr.io.fcsr_flags.bits invalidate csr.io.fcsr_flags.valid invalidate csr.io.fcsr_rm invalidate csr.io.time invalidate csr.io.gva invalidate csr.io.mhtinst_read_pseudo invalidate csr.io.htval invalidate csr.io.tval invalidate csr.io.pc invalidate csr.io.cause invalidate csr.io.retire invalidate csr.io.exception invalidate csr.io.evec invalidate csr.io.vsatp.ppn invalidate csr.io.vsatp.asid invalidate csr.io.vsatp.mode invalidate csr.io.hgatp.ppn invalidate csr.io.hgatp.asid invalidate csr.io.hgatp.mode invalidate csr.io.ptbr.ppn invalidate csr.io.ptbr.asid invalidate csr.io.ptbr.mode invalidate csr.io.gstatus.uie invalidate csr.io.gstatus.sie invalidate csr.io.gstatus.hie invalidate csr.io.gstatus.mie invalidate csr.io.gstatus.upie invalidate csr.io.gstatus.spie invalidate csr.io.gstatus.ube invalidate csr.io.gstatus.mpie invalidate csr.io.gstatus.spp invalidate csr.io.gstatus.vs invalidate csr.io.gstatus.mpp invalidate csr.io.gstatus.fs invalidate csr.io.gstatus.xs invalidate csr.io.gstatus.mprv invalidate csr.io.gstatus.sum invalidate csr.io.gstatus.mxr invalidate csr.io.gstatus.tvm invalidate csr.io.gstatus.tw invalidate csr.io.gstatus.tsr invalidate csr.io.gstatus.zero1 invalidate csr.io.gstatus.sd_rv32 invalidate csr.io.gstatus.uxl invalidate csr.io.gstatus.sxl invalidate csr.io.gstatus.sbe invalidate csr.io.gstatus.mbe invalidate csr.io.gstatus.gva invalidate csr.io.gstatus.mpv invalidate csr.io.gstatus.zero2 invalidate csr.io.gstatus.sd invalidate csr.io.gstatus.v invalidate csr.io.gstatus.prv invalidate csr.io.gstatus.dv invalidate csr.io.gstatus.dprv invalidate csr.io.gstatus.isa invalidate csr.io.gstatus.wfi invalidate csr.io.gstatus.cease invalidate csr.io.gstatus.debug invalidate csr.io.hstatus.zero1 invalidate csr.io.hstatus.vsbe invalidate csr.io.hstatus.gva invalidate csr.io.hstatus.spv invalidate csr.io.hstatus.spvp invalidate csr.io.hstatus.hu invalidate csr.io.hstatus.zero2 invalidate csr.io.hstatus.vgein invalidate csr.io.hstatus.zero3 invalidate csr.io.hstatus.vtvm invalidate csr.io.hstatus.vtw invalidate csr.io.hstatus.vtsr invalidate csr.io.hstatus.zero5 invalidate csr.io.hstatus.vsxl invalidate csr.io.hstatus.zero6 invalidate csr.io.status.uie invalidate csr.io.status.sie invalidate csr.io.status.hie invalidate csr.io.status.mie invalidate csr.io.status.upie invalidate csr.io.status.spie invalidate csr.io.status.ube invalidate csr.io.status.mpie invalidate csr.io.status.spp invalidate csr.io.status.vs invalidate csr.io.status.mpp invalidate csr.io.status.fs invalidate csr.io.status.xs invalidate csr.io.status.mprv invalidate csr.io.status.sum invalidate csr.io.status.mxr invalidate csr.io.status.tvm invalidate csr.io.status.tw invalidate csr.io.status.tsr invalidate csr.io.status.zero1 invalidate csr.io.status.sd_rv32 invalidate csr.io.status.uxl invalidate csr.io.status.sxl invalidate csr.io.status.sbe invalidate csr.io.status.mbe invalidate csr.io.status.gva invalidate csr.io.status.mpv invalidate csr.io.status.zero2 invalidate csr.io.status.sd invalidate csr.io.status.v invalidate csr.io.status.prv invalidate csr.io.status.dv invalidate csr.io.status.dprv invalidate csr.io.status.isa invalidate csr.io.status.wfi invalidate csr.io.status.cease invalidate csr.io.status.debug invalidate csr.io.singleStep invalidate csr.io.eret invalidate csr.io.rw_stall invalidate csr.io.csr_stall invalidate csr.io.decode[0].virtual_system_illegal invalidate csr.io.decode[0].virtual_access_illegal invalidate csr.io.decode[0].system_illegal invalidate csr.io.decode[0].write_flush invalidate csr.io.decode[0].write_illegal invalidate csr.io.decode[0].read_illegal invalidate csr.io.decode[0].rocc_illegal invalidate csr.io.decode[0].vector_csr invalidate csr.io.decode[0].fp_csr invalidate csr.io.decode[0].vector_illegal invalidate csr.io.decode[0].fp_illegal invalidate csr.io.decode[0].inst invalidate csr.io.rw.wdata invalidate csr.io.rw.rdata invalidate csr.io.rw.cmd invalidate csr.io.rw.addr invalidate csr.io.hartid invalidate csr.io.interrupts.meip invalidate csr.io.interrupts.msip invalidate csr.io.interrupts.mtip invalidate csr.io.interrupts.debug invalidate csr.io.ungated_clock node _csr_io_decode_0_inst_T = shl(wb_reg_csr_addr, 20) connect csr.io.decode[0].inst, _csr_io_decode_0_inst_T node _csr_io_rw_addr_T = bits(wb_reg_inst, 31, 20) connect csr.io.rw.addr, _csr_io_rw_addr_T connect csr.io.rw.wdata, wb_reg_alu node _csr_io_rw_cmd_T = mux(wb_dmiss_stall, UInt<3>(0h0), wb_reg_ctrl.csr_cmd) connect csr.io.rw.cmd, _csr_io_rw_cmd_T node _csr_io_retire_T = eq(io.ctl.exception, UInt<1>(0h0)) node _csr_io_retire_T_1 = and(wb_reg_valid, _csr_io_retire_T) connect csr.io.retire, _csr_io_retire_T_1 connect csr.io.exception, io.ctl.exception connect csr.io.pc, wb_reg_pc connect exception_target, csr.io.evec connect io.dat.csr_eret, csr.io.eret connect tval_data_ma, wb_reg_alu connect tval_inst_ma, wb_reg_target_pc node _csr_io_tval_T = eq(io.ctl.exception_cause, UInt<2>(0h2)) node _csr_io_tval_T_1 = eq(io.ctl.exception_cause, UInt<1>(0h0)) node _csr_io_tval_T_2 = eq(io.ctl.exception_cause, UInt<3>(0h6)) node _csr_io_tval_T_3 = eq(io.ctl.exception_cause, UInt<3>(0h4)) node _csr_io_tval_T_4 = mux(_csr_io_tval_T_3, tval_data_ma, UInt<1>(0h0)) node _csr_io_tval_T_5 = mux(_csr_io_tval_T_2, tval_data_ma, _csr_io_tval_T_4) node _csr_io_tval_T_6 = mux(_csr_io_tval_T_1, tval_inst_ma, _csr_io_tval_T_5) node _csr_io_tval_T_7 = mux(_csr_io_tval_T, wb_reg_inst, _csr_io_tval_T_6) connect csr.io.tval, _csr_io_tval_T_7 regreset reg_interrupt_flag : UInt<1>, clock, reset, UInt<1>(0h0) connect reg_interrupt_flag, csr.io.interrupt node _interrupt_edge_T = eq(reg_interrupt_flag, UInt<1>(0h0)) node interrupt_edge = and(csr.io.interrupt, _interrupt_edge_T) connect csr.io.interrupts.meip, io.interrupt.meip connect csr.io.interrupts.msip, io.interrupt.msip connect csr.io.interrupts.mtip, io.interrupt.mtip connect csr.io.interrupts.debug, io.interrupt.debug connect csr.io.hartid, io.hartid connect io.dat.csr_interrupt, interrupt_edge node _csr_io_cause_T = mux(io.ctl.exception, io.ctl.exception_cause, csr.io.interrupt_cause) connect csr.io.cause, _csr_io_cause_T connect csr.io.ungated_clock, clock node _wb_wbdata_T = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h0)) node _wb_wbdata_T_1 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h1)) node _wb_wbdata_T_2 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h2)) node _wb_wbdata_T_3 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h3)) node _wb_wbdata_T_4 = mux(_wb_wbdata_T_3, csr.io.rw.rdata, wb_reg_alu) node _wb_wbdata_T_5 = mux(_wb_wbdata_T_2, io.imem.resp.bits.pc, _wb_wbdata_T_4) node _wb_wbdata_T_6 = mux(_wb_wbdata_T_1, io.dmem.resp.bits.data, _wb_wbdata_T_5) node _wb_wbdata_T_7 = mux(_wb_wbdata_T, wb_reg_alu, _wb_wbdata_T_6) connect wb_wbdata, _wb_wbdata_T_7 node _debug_wb_inst_T = or(wb_hazard_stall, io.ctl.exe_kill) node _debug_wb_inst_T_1 = eq(io.imem.resp.valid, UInt<1>(0h0)) node _debug_wb_inst_T_2 = or(_debug_wb_inst_T, _debug_wb_inst_T_1) node _debug_wb_inst_T_3 = mux(_debug_wb_inst_T_2, UInt<32>(0h4033), io.imem.resp.bits.inst) reg debug_wb_inst : UInt, clock connect debug_wb_inst, _debug_wb_inst_T_3 node _T_10 = bits(csr.io.time, 31, 0) reg REG : UInt, clock connect REG, exe_rs1_addr reg REG_1 : UInt, clock connect REG_1, exe_alu_op1 reg REG_2 : UInt, clock connect REG_2, exe_rs2_addr reg REG_3 : UInt, clock connect REG_3, exe_alu_op2 node _T_11 = mux(io.ctl.exe_kill, UInt<8>(0h4b), UInt<8>(0h20)) node _T_12 = mux(wb_hazard_stall, UInt<8>(0h48), _T_11) node _T_13 = eq(UInt<3>(0h1), io.ctl.pc_sel) node _T_14 = mux(_T_13, UInt<8>(0h42), UInt<8>(0h3f)) node _T_15 = eq(UInt<3>(0h2), io.ctl.pc_sel) node _T_16 = mux(_T_15, UInt<8>(0h4a), _T_14) node _T_17 = eq(UInt<3>(0h3), io.ctl.pc_sel) node _T_18 = mux(_T_17, UInt<8>(0h52), _T_16) node _T_19 = eq(UInt<3>(0h4), io.ctl.pc_sel) node _T_20 = mux(_T_19, UInt<8>(0h45), _T_18) node _T_21 = eq(UInt<3>(0h0), io.ctl.pc_sel) node _T_22 = mux(_T_21, UInt<8>(0h20), _T_20) node _T_23 = mux(csr.io.exception, UInt<8>(0h58), UInt<8>(0h20)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Cyc= %d [%d] pc=[%x] W[r%d=%x][%d] Op1=[r%d][%x] Op2=[r%d][%x] inst=[%x] %c%c%c DASM(%x)\n", _T_10, csr.io.retire, wb_reg_pc, wb_reg_wbaddr, wb_wbdata, wb_reg_ctrl.rf_wen, REG, REG_1, REG_2, REG_3, debug_wb_inst, _T_12, _T_22, _T_23, debug_wb_inst) : printf

module DatPath( // @[dpath.scala:50:7] input clock, // @[dpath.scala:50:7] input reset, // @[dpath.scala:50:7] output [31:0] io_ddpath_rdata, // @[dpath.scala:52:15] output [31:0] io_imem_req_bits_pc, // @[dpath.scala:52:15] output io_imem_resp_ready, // @[dpath.scala:52:15] input io_imem_resp_valid, // @[dpath.scala:52:15] input [31:0] io_imem_resp_bits_pc, // @[dpath.scala:52:15] input [31:0] io_imem_resp_bits_inst, // @[dpath.scala:52:15] input [31:0] io_imem_debug_if_pc, // @[dpath.scala:52:15] input [31:0] io_imem_debug_if_inst, // @[dpath.scala:52:15] input io_dmem_req_ready, // @[dpath.scala:52:15] output io_dmem_req_valid, // @[dpath.scala:52:15] output [31:0] io_dmem_req_bits_addr, // @[dpath.scala:52:15] output [31:0] io_dmem_req_bits_data, // @[dpath.scala:52:15] output io_dmem_req_bits_fcn, // @[dpath.scala:52:15] output [2:0] io_dmem_req_bits_typ, // @[dpath.scala:52:15] input io_dmem_resp_valid, // @[dpath.scala:52:15] input [31:0] io_dmem_resp_bits_data, // @[dpath.scala:52:15] input io_ctl_exe_kill, // @[dpath.scala:52:15] input [2:0] io_ctl_pc_sel, // @[dpath.scala:52:15] input io_ctl_brjmp_sel, // @[dpath.scala:52:15] input [1:0] io_ctl_op1_sel, // @[dpath.scala:52:15] input [1:0] io_ctl_op2_sel, // @[dpath.scala:52:15] input [3:0] io_ctl_alu_fun, // @[dpath.scala:52:15] input [1:0] io_ctl_wb_sel, // @[dpath.scala:52:15] input io_ctl_rf_wen, // @[dpath.scala:52:15] input io_ctl_bypassable, // @[dpath.scala:52:15] input [2:0] io_ctl_csr_cmd, // @[dpath.scala:52:15] input io_ctl_dmem_val, // @[dpath.scala:52:15] input io_ctl_dmem_fcn, // @[dpath.scala:52:15] input [2:0] io_ctl_dmem_typ, // @[dpath.scala:52:15] input io_ctl_exception, // @[dpath.scala:52:15] input [31:0] io_ctl_exception_cause, // @[dpath.scala:52:15] output io_dat_br_eq, // @[dpath.scala:52:15] output io_dat_br_lt, // @[dpath.scala:52:15] output io_dat_br_ltu, // @[dpath.scala:52:15] output io_dat_inst_misaligned, // @[dpath.scala:52:15] output io_dat_data_misaligned, // @[dpath.scala:52:15] output io_dat_wb_hazard_stall, // @[dpath.scala:52:15] output io_dat_csr_eret, // @[dpath.scala:52:15] output io_dat_csr_interrupt, // @[dpath.scala:52:15] input io_interrupt_debug, // @[dpath.scala:52:15] input io_interrupt_mtip, // @[dpath.scala:52:15] input io_interrupt_msip, // @[dpath.scala:52:15] input io_interrupt_meip, // @[dpath.scala:52:15] input io_hartid // @[dpath.scala:52:15] ); wire [31:0] _csr_io_rw_rdata; // @[dpath.scala:259:20] wire [31:0] _csr_io_time; // @[dpath.scala:259:20] wire _csr_io_interrupt; // @[dpath.scala:259:20] wire [31:0] _csr_io_interrupt_cause; // @[dpath.scala:259:20] wire [31:0] _alu_io_out; // @[dpath.scala:190:20] wire [31:0] _alu_io_adder_out; // @[dpath.scala:190:20] wire [31:0] _regfile_ext_R0_data; // @[dpath.scala:135:21] wire [31:0] _regfile_ext_R1_data; // @[dpath.scala:135:21] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[dpath.scala:50:7] wire [31:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[dpath.scala:50:7] wire [31:0] io_imem_resp_bits_inst_0 = io_imem_resp_bits_inst; // @[dpath.scala:50:7] wire [31:0] io_imem_debug_if_pc_0 = io_imem_debug_if_pc; // @[dpath.scala:50:7] wire [31:0] io_imem_debug_if_inst_0 = io_imem_debug_if_inst; // @[dpath.scala:50:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[dpath.scala:50:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[dpath.scala:50:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[dpath.scala:50:7] wire io_ctl_exe_kill_0 = io_ctl_exe_kill; // @[dpath.scala:50:7] wire [2:0] io_ctl_pc_sel_0 = io_ctl_pc_sel; // @[dpath.scala:50:7] wire io_ctl_brjmp_sel_0 = io_ctl_brjmp_sel; // @[dpath.scala:50:7] wire [1:0] io_ctl_op1_sel_0 = io_ctl_op1_sel; // @[dpath.scala:50:7] wire [1:0] io_ctl_op2_sel_0 = io_ctl_op2_sel; // @[dpath.scala:50:7] wire [3:0] io_ctl_alu_fun_0 = io_ctl_alu_fun; // @[dpath.scala:50:7] wire [1:0] io_ctl_wb_sel_0 = io_ctl_wb_sel; // @[dpath.scala:50:7] wire io_ctl_rf_wen_0 = io_ctl_rf_wen; // @[dpath.scala:50:7] wire io_ctl_bypassable_0 = io_ctl_bypassable; // @[dpath.scala:50:7] wire [2:0] io_ctl_csr_cmd_0 = io_ctl_csr_cmd; // @[dpath.scala:50:7] wire io_ctl_dmem_val_0 = io_ctl_dmem_val; // @[dpath.scala:50:7] wire io_ctl_dmem_fcn_0 = io_ctl_dmem_fcn; // @[dpath.scala:50:7] wire [2:0] io_ctl_dmem_typ_0 = io_ctl_dmem_typ; // @[dpath.scala:50:7] wire io_ctl_exception_0 = io_ctl_exception; // @[dpath.scala:50:7] wire [31:0] io_ctl_exception_cause_0 = io_ctl_exception_cause; // @[dpath.scala:50:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[dpath.scala:50:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[dpath.scala:50:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[dpath.scala:50:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[dpath.scala:50:7] wire io_hartid_0 = io_hartid; // @[dpath.scala:50:7] wire [4:0] io_ddpath_addr = 5'h0; // @[dpath.scala:50:7] wire [31:0] io_ddpath_wdata = 32'h0; // @[dpath.scala:50:7] wire io_ddpath_validreq = 1'h0; // @[dpath.scala:50:7] wire io_ddpath_resetpc = 1'h0; // @[dpath.scala:50:7] wire io_imem_req_valid = 1'h0; // @[dpath.scala:50:7] wire io_imem_imiss = 1'h0; // @[dpath.scala:50:7] wire io_imem_exe_kill = 1'h0; // @[dpath.scala:50:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire [31:0] _exe_jump_reg_target_T = 32'hFFFFFFFE; // @[dpath.scala:201:46] wire [11:0] _imm_u_T_1 = 12'h0; // @[dpath.scala:157:42] wire [31:0] take_pc; // @[dpath.scala:83:21] wire _io_imem_resp_ready_T_2; // @[dpath.scala:80:43] wire _io_dmem_req_valid_T_3; // @[dpath.scala:217:72] wire [31:0] exe_rs2_data; // @[Mux.scala:126:16] wire _io_dmem_req_bits_fcn_T_2; // @[dpath.scala:221:67] wire [2:0] io_dmem_req_bits_typ_0 = io_ctl_dmem_typ_0; // @[dpath.scala:50:7] wire _io_dat_br_eq_T; // @[dpath.scala:205:35] wire _io_dat_br_lt_T_2; // @[dpath.scala:206:42] wire _io_dat_br_ltu_T; // @[dpath.scala:207:42] wire _io_dat_inst_misaligned_T_11; // @[dpath.scala:91:91] wire _io_dat_data_misaligned_T_2; // @[dpath.scala:214:70] wire wb_hazard_stall; // @[dpath.scala:71:31] wire interrupt_edge; // @[dpath.scala:284:42] wire [31:0] io_ddpath_rdata_0; // @[dpath.scala:50:7] wire [31:0] io_imem_req_bits_pc_0; // @[dpath.scala:50:7] wire io_imem_resp_ready_0; // @[dpath.scala:50:7] wire [31:0] io_dmem_req_bits_addr_0; // @[dpath.scala:50:7] wire [31:0] io_dmem_req_bits_data_0; // @[dpath.scala:50:7] wire io_dmem_req_bits_fcn_0; // @[dpath.scala:50:7] wire io_dmem_req_valid_0; // @[dpath.scala:50:7] wire io_dat_br_eq_0; // @[dpath.scala:50:7] wire io_dat_br_lt_0; // @[dpath.scala:50:7] wire io_dat_br_ltu_0; // @[dpath.scala:50:7] wire io_dat_inst_misaligned_0; // @[dpath.scala:50:7] wire io_dat_data_misaligned_0; // @[dpath.scala:50:7] wire io_dat_wb_hazard_stall_0; // @[dpath.scala:50:7] wire io_dat_csr_eret_0; // @[dpath.scala:50:7] wire io_dat_csr_interrupt_0; // @[dpath.scala:50:7] wire [31:0] tval_data_ma; // @[dpath.scala:56:27] wire [31:0] tval_inst_ma; // @[dpath.scala:57:27] reg [31:0] wb_reg_inst; // @[dpath.scala:61:34] reg wb_reg_valid; // @[dpath.scala:62:34] reg wb_reg_ctrl_exe_kill; // @[dpath.scala:63:30] reg [2:0] wb_reg_ctrl_pc_sel; // @[dpath.scala:63:30] reg wb_reg_ctrl_brjmp_sel; // @[dpath.scala:63:30] reg [1:0] wb_reg_ctrl_op1_sel; // @[dpath.scala:63:30] reg [1:0] wb_reg_ctrl_op2_sel; // @[dpath.scala:63:30] reg [3:0] wb_reg_ctrl_alu_fun; // @[dpath.scala:63:30] reg [1:0] wb_reg_ctrl_wb_sel; // @[dpath.scala:63:30] reg wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30] reg wb_reg_ctrl_bypassable; // @[dpath.scala:63:30] reg [2:0] wb_reg_ctrl_csr_cmd; // @[dpath.scala:63:30] reg wb_reg_ctrl_dmem_val; // @[dpath.scala:63:30] reg wb_reg_ctrl_dmem_fcn; // @[dpath.scala:63:30] reg [2:0] wb_reg_ctrl_dmem_typ; // @[dpath.scala:63:30] reg wb_reg_ctrl_exception; // @[dpath.scala:63:30] reg [31:0] wb_reg_ctrl_exception_cause; // @[dpath.scala:63:30] reg [31:0] wb_reg_pc; // @[dpath.scala:64:30] reg [31:0] wb_reg_alu; // @[dpath.scala:65:30] assign tval_data_ma = wb_reg_alu; // @[dpath.scala:56:27, :65:30] reg [11:0] wb_reg_csr_addr; // @[dpath.scala:66:30] reg [4:0] wb_reg_wbaddr; // @[dpath.scala:67:30] reg [31:0] wb_reg_target_pc; // @[dpath.scala:68:30] assign tval_inst_ma = wb_reg_target_pc; // @[dpath.scala:57:27, :68:30] reg wb_reg_mem; // @[dpath.scala:69:34] wire _wb_hazard_stall_T_12; // @[dpath.scala:128:136] assign io_dat_wb_hazard_stall_0 = wb_hazard_stall; // @[dpath.scala:50:7, :71:31] wire _wb_dmiss_stall_T_4; // @[dpath.scala:227:64] wire wb_dmiss_stall; // @[dpath.scala:72:31] wire [31:0] _exe_brjmp_target_T_1; // @[dpath.scala:200:31] wire [31:0] exe_brjmp_target; // @[dpath.scala:76:34] wire [31:0] _exe_jump_reg_target_T_1; // @[dpath.scala:201:44] wire [31:0] exe_jump_reg_target; // @[dpath.scala:77:34] wire [31:0] exception_target; // @[dpath.scala:78:34] wire _io_imem_resp_ready_T = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26] wire _io_imem_resp_ready_T_1 = ~wb_dmiss_stall; // @[dpath.scala:72:31, :80:46] assign _io_imem_resp_ready_T_2 = _io_imem_resp_ready_T & _io_imem_resp_ready_T_1; // @[dpath.scala:80:{26,43,46}] assign io_imem_resp_ready_0 = _io_imem_resp_ready_T_2; // @[dpath.scala:50:7, :80:43] wire _take_pc_T = io_ctl_pc_sel_0 == 3'h4; // @[dpath.scala:50:7, :83:36] wire _T_17 = io_ctl_pc_sel_0 == 3'h3; // @[dpath.scala:50:7, :84:36] wire _take_pc_T_1; // @[dpath.scala:84:36] assign _take_pc_T_1 = _T_17; // @[dpath.scala:84:36] wire _io_dat_inst_misaligned_T_8; // @[dpath.scala:91:79] assign _io_dat_inst_misaligned_T_8 = _T_17; // @[dpath.scala:84:36, :91:79] wire _exe_target_pc_T; // @[dpath.scala:93:43] assign _exe_target_pc_T = _T_17; // @[dpath.scala:84:36, :93:43] wire [31:0] _take_pc_T_2 = _take_pc_T_1 ? exe_jump_reg_target : exe_brjmp_target; // @[dpath.scala:76:34, :77:34, :84:{21,36}] assign take_pc = _take_pc_T ? exception_target : _take_pc_T_2; // @[dpath.scala:78:34, :83:{21,36}, :84:21] assign io_imem_req_bits_pc_0 = take_pc; // @[dpath.scala:50:7, :83:21] wire [1:0] _io_dat_inst_misaligned_T = exe_brjmp_target[1:0]; // @[dpath.scala:76:34, :90:48] wire _io_dat_inst_misaligned_T_1 = |_io_dat_inst_misaligned_T; // @[dpath.scala:90:{48,55}] wire _io_dat_inst_misaligned_T_2 = io_ctl_pc_sel_0 == 3'h1; // @[dpath.scala:50:7, :90:80] wire _io_dat_inst_misaligned_T_3 = io_ctl_pc_sel_0 == 3'h2; // @[dpath.scala:50:7, :90:107] wire _io_dat_inst_misaligned_T_4 = _io_dat_inst_misaligned_T_2 | _io_dat_inst_misaligned_T_3; // @[dpath.scala:90:{80,90,107}] wire _io_dat_inst_misaligned_T_5 = _io_dat_inst_misaligned_T_1 & _io_dat_inst_misaligned_T_4; // @[dpath.scala:90:{55,62,90}] wire [1:0] _io_dat_inst_misaligned_T_6 = exe_jump_reg_target[1:0]; // @[dpath.scala:77:34, :91:51] wire _io_dat_inst_misaligned_T_7 = |_io_dat_inst_misaligned_T_6; // @[dpath.scala:91:{51,58}] wire _io_dat_inst_misaligned_T_9 = _io_dat_inst_misaligned_T_7 & _io_dat_inst_misaligned_T_8; // @[dpath.scala:91:{58,62,79}] wire _io_dat_inst_misaligned_T_10 = _io_dat_inst_misaligned_T_5 | _io_dat_inst_misaligned_T_9; // @[dpath.scala:90:{62,118}, :91:62] assign _io_dat_inst_misaligned_T_11 = _io_dat_inst_misaligned_T_10 & io_imem_resp_valid_0; // @[dpath.scala:50:7, :90:118, :91:91] assign io_dat_inst_misaligned_0 = _io_dat_inst_misaligned_T_11; // @[dpath.scala:50:7, :91:91] wire [31:0] exe_target_pc = _exe_target_pc_T ? exe_jump_reg_target : exe_brjmp_target; // @[dpath.scala:76:34, :77:34, :93:{27,43}] wire [4:0] exe_rs1_addr = io_imem_resp_bits_inst_0[19:15]; // @[dpath.scala:50:7, :105:31] wire [4:0] imm_z = io_imem_resp_bits_inst_0[19:15]; // @[dpath.scala:50:7, :105:31, :159:24] wire [4:0] exe_rs2_addr = io_imem_resp_bits_inst_0[24:20]; // @[dpath.scala:50:7, :106:31] wire [4:0] exe_wbaddr = io_imem_resp_bits_inst_0[11:7]; // @[dpath.scala:50:7, :107:31] wire [4:0] _imm_s_T_1 = io_imem_resp_bits_inst_0[11:7]; // @[dpath.scala:50:7, :107:31, :155:46] wire [31:0] _wb_wbdata_T_7; // @[Mux.scala:126:16] wire [31:0] wb_wbdata; // @[dpath.scala:109:27] wire _GEN = wb_reg_wbaddr == exe_rs1_addr; // @[dpath.scala:67:30, :105:31, :128:42] wire _wb_hazard_stall_T; // @[dpath.scala:128:42] assign _wb_hazard_stall_T = _GEN; // @[dpath.scala:128:42] wire _exe_rs1_data_T; // @[dpath.scala:171:44] assign _exe_rs1_data_T = _GEN; // @[dpath.scala:128:42, :171:44] wire _wb_hazard_stall_T_1 = |exe_rs1_addr; // @[dpath.scala:105:31, :128:77] wire _wb_hazard_stall_T_2 = _wb_hazard_stall_T & _wb_hazard_stall_T_1; // @[dpath.scala:128:{42,60,77}] wire _wb_hazard_stall_T_3 = _wb_hazard_stall_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :128:{60,86}] wire _wb_hazard_stall_T_4 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :128:111] wire _wb_hazard_stall_T_5 = _wb_hazard_stall_T_3 & _wb_hazard_stall_T_4; // @[dpath.scala:128:{86,108,111}] wire _GEN_0 = wb_reg_wbaddr == exe_rs2_addr; // @[dpath.scala:67:30, :106:31, :129:42] wire _wb_hazard_stall_T_6; // @[dpath.scala:129:42] assign _wb_hazard_stall_T_6 = _GEN_0; // @[dpath.scala:129:42] wire _exe_rs2_data_T; // @[dpath.scala:174:44] assign _exe_rs2_data_T = _GEN_0; // @[dpath.scala:129:42, :174:44] wire _wb_hazard_stall_T_7 = |exe_rs2_addr; // @[dpath.scala:106:31, :129:77] wire _wb_hazard_stall_T_8 = _wb_hazard_stall_T_6 & _wb_hazard_stall_T_7; // @[dpath.scala:129:{42,60,77}] wire _wb_hazard_stall_T_9 = _wb_hazard_stall_T_8 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :129:{60,86}] wire _wb_hazard_stall_T_10 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :128:111, :129:111] wire _wb_hazard_stall_T_11 = _wb_hazard_stall_T_9 & _wb_hazard_stall_T_10; // @[dpath.scala:129:{86,108,111}] assign _wb_hazard_stall_T_12 = _wb_hazard_stall_T_5 | _wb_hazard_stall_T_11; // @[dpath.scala:128:{108,136}, :129:108] assign wb_hazard_stall = _wb_hazard_stall_T_12; // @[dpath.scala:71:31, :128:136] wire _rf_rs1_data_T = |exe_rs1_addr; // @[dpath.scala:105:31, :128:77, :149:40] wire [31:0] rf_rs1_data = _rf_rs1_data_T ? _regfile_ext_R1_data : 32'h0; // @[dpath.scala:135:21, :149:{25,40}] wire _rf_rs2_data_T = |exe_rs2_addr; // @[dpath.scala:106:31, :129:77, :150:40] wire [31:0] rf_rs2_data = _rf_rs2_data_T ? _regfile_ext_R0_data : 32'h0; // @[dpath.scala:135:21, :150:{25,40}] wire [11:0] imm_i = io_imem_resp_bits_inst_0[31:20]; // @[dpath.scala:50:7, :154:24] wire [11:0] _wb_reg_csr_addr_T = io_imem_resp_bits_inst_0[31:20]; // @[dpath.scala:50:7, :154:24, :249:37] wire [6:0] _imm_s_T = io_imem_resp_bits_inst_0[31:25]; // @[dpath.scala:50:7, :155:28] wire [11:0] imm_s = {_imm_s_T, _imm_s_T_1}; // @[dpath.scala:155:{19,28,46}] wire _imm_b_T = io_imem_resp_bits_inst_0[31]; // @[dpath.scala:50:7, :156:28] wire _imm_j_T = io_imem_resp_bits_inst_0[31]; // @[dpath.scala:50:7, :156:28, :158:28] wire _imm_b_T_1 = io_imem_resp_bits_inst_0[7]; // @[dpath.scala:50:7, :156:42] wire [5:0] _imm_b_T_2 = io_imem_resp_bits_inst_0[30:25]; // @[dpath.scala:50:7, :156:55] wire [3:0] _imm_b_T_3 = io_imem_resp_bits_inst_0[11:8]; // @[dpath.scala:50:7, :156:72] wire [9:0] imm_b_lo = {_imm_b_T_2, _imm_b_T_3}; // @[dpath.scala:156:{19,55,72}] wire [1:0] imm_b_hi = {_imm_b_T, _imm_b_T_1}; // @[dpath.scala:156:{19,28,42}] wire [11:0] imm_b = {imm_b_hi, imm_b_lo}; // @[dpath.scala:156:19] wire [19:0] _imm_u_T = io_imem_resp_bits_inst_0[31:12]; // @[dpath.scala:50:7, :157:28] wire [31:0] imm_u = {_imm_u_T, 12'h0}; // @[dpath.scala:157:{19,28}] wire [7:0] _imm_j_T_1 = io_imem_resp_bits_inst_0[19:12]; // @[dpath.scala:50:7, :158:42] wire _imm_j_T_2 = io_imem_resp_bits_inst_0[20]; // @[dpath.scala:50:7, :158:59] wire [9:0] _imm_j_T_3 = io_imem_resp_bits_inst_0[30:21]; // @[dpath.scala:50:7, :158:73] wire [10:0] imm_j_lo = {_imm_j_T_2, _imm_j_T_3}; // @[dpath.scala:158:{19,59,73}] wire [8:0] imm_j_hi = {_imm_j_T, _imm_j_T_1}; // @[dpath.scala:158:{19,28,42}] wire [19:0] imm_j = {imm_j_hi, imm_j_lo}; // @[dpath.scala:158:19] wire _imm_i_sext_T = imm_i[11]; // @[dpath.scala:154:24, :162:38] wire [19:0] _imm_i_sext_T_1 = {20{_imm_i_sext_T}}; // @[dpath.scala:162:{29,38}] wire [31:0] imm_i_sext = {_imm_i_sext_T_1, imm_i}; // @[dpath.scala:154:24, :162:{24,29}] wire _imm_s_sext_T = imm_s[11]; // @[dpath.scala:155:19, :163:38] wire [19:0] _imm_s_sext_T_1 = {20{_imm_s_sext_T}}; // @[dpath.scala:163:{29,38}] wire [31:0] imm_s_sext = {_imm_s_sext_T_1, imm_s}; // @[dpath.scala:155:19, :163:{24,29}] wire _imm_b_sext_T = imm_b[11]; // @[dpath.scala:156:19, :164:38] wire [18:0] _imm_b_sext_T_1 = {19{_imm_b_sext_T}}; // @[dpath.scala:164:{29,38}] wire [30:0] imm_b_sext_hi = {_imm_b_sext_T_1, imm_b}; // @[dpath.scala:156:19, :164:{24,29}] wire [31:0] imm_b_sext = {imm_b_sext_hi, 1'h0}; // @[dpath.scala:164:24] wire _imm_j_sext_T = imm_j[19]; // @[dpath.scala:158:19, :165:38] wire [10:0] _imm_j_sext_T_1 = {11{_imm_j_sext_T}}; // @[dpath.scala:165:{29,38}] wire [30:0] imm_j_sext_hi = {_imm_j_sext_T_1, imm_j}; // @[dpath.scala:158:19, :165:{24,29}] wire [31:0] imm_j_sext = {imm_j_sext_hi, 1'h0}; // @[dpath.scala:165:24] wire _exe_rs1_data_T_1 = |exe_rs1_addr; // @[dpath.scala:105:31, :128:77, :171:79] wire _exe_rs1_data_T_2 = _exe_rs1_data_T & _exe_rs1_data_T_1; // @[dpath.scala:171:{44,62,79}] wire _exe_rs1_data_T_3 = _exe_rs1_data_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :171:{62,88}] wire _exe_rs1_data_T_4 = _exe_rs1_data_T_3 & wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :171:{88,110}] wire [31:0] exe_rs1_data = _exe_rs1_data_T_4 ? wb_reg_alu : rf_rs1_data; // @[Mux.scala:126:16] wire [31:0] _io_dat_br_lt_T = exe_rs1_data; // @[Mux.scala:126:16] wire _exe_rs2_data_T_1 = |exe_rs2_addr; // @[dpath.scala:106:31, :129:77, :174:79] wire _exe_rs2_data_T_2 = _exe_rs2_data_T & _exe_rs2_data_T_1; // @[dpath.scala:174:{44,62,79}] wire _exe_rs2_data_T_3 = _exe_rs2_data_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :174:{62,88}] wire _exe_rs2_data_T_4 = _exe_rs2_data_T_3 & wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :174:{88,110}] assign exe_rs2_data = _exe_rs2_data_T_4 ? wb_reg_alu : rf_rs2_data; // @[Mux.scala:126:16] assign io_dmem_req_bits_data_0 = exe_rs2_data; // @[Mux.scala:126:16] wire [31:0] _io_dat_br_lt_T_1 = exe_rs2_data; // @[Mux.scala:126:16] wire _exe_alu_op1_T = io_ctl_op1_sel_0 == 2'h2; // @[dpath.scala:50:7, :179:41] wire _exe_alu_op1_T_1 = io_ctl_op1_sel_0 == 2'h1; // @[dpath.scala:50:7, :180:41] wire [31:0] _exe_alu_op1_T_2 = _exe_alu_op1_T_1 ? imm_u : exe_rs1_data; // @[Mux.scala:126:16] wire [31:0] exe_alu_op1 = _exe_alu_op1_T ? {27'h0, imm_z} : _exe_alu_op1_T_2; // @[dpath.scala:159:24, :179:{25,41}, :180:25] wire _exe_alu_op2_T = io_ctl_op2_sel_0 == 2'h1; // @[dpath.scala:50:7, :183:41] wire _exe_alu_op2_T_1 = &io_ctl_op2_sel_0; // @[dpath.scala:50:7, :184:41] wire _exe_alu_op2_T_2 = io_ctl_op2_sel_0 == 2'h2; // @[dpath.scala:50:7, :185:41] wire [31:0] _exe_alu_op2_T_3 = _exe_alu_op2_T_2 ? imm_s_sext : exe_rs2_data; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op2_T_4 = _exe_alu_op2_T_1 ? io_imem_resp_bits_pc_0 : _exe_alu_op2_T_3; // @[dpath.scala:50:7, :184:{25,41}, :185:25] wire [31:0] exe_alu_op2 = _exe_alu_op2_T ? imm_i_sext : _exe_alu_op2_T_4; // @[dpath.scala:162:24, :183:{25,41}, :184:25] wire [31:0] imm_brjmp = io_ctl_brjmp_sel_0 ? imm_j_sext : imm_b_sext; // @[dpath.scala:50:7, :164:24, :165:24, :199:23] wire [32:0] _exe_brjmp_target_T = {1'h0, io_imem_resp_bits_pc_0} + {1'h0, imm_brjmp}; // @[dpath.scala:50:7, :199:23, :200:31] assign _exe_brjmp_target_T_1 = _exe_brjmp_target_T[31:0]; // @[dpath.scala:200:31] assign exe_brjmp_target = _exe_brjmp_target_T_1; // @[dpath.scala:76:34, :200:31] assign _exe_jump_reg_target_T_1 = _alu_io_adder_out & 32'hFFFFFFFE; // @[dpath.scala:190:20, :201:44] assign exe_jump_reg_target = _exe_jump_reg_target_T_1; // @[dpath.scala:77:34, :201:44] assign _io_dat_br_eq_T = exe_rs1_data == exe_rs2_data; // @[Mux.scala:126:16] assign io_dat_br_eq_0 = _io_dat_br_eq_T; // @[dpath.scala:50:7, :205:35] assign _io_dat_br_lt_T_2 = $signed(_io_dat_br_lt_T) < $signed(_io_dat_br_lt_T_1); // @[dpath.scala:206:{35,42,57}] assign io_dat_br_lt_0 = _io_dat_br_lt_T_2; // @[dpath.scala:50:7, :206:42] assign _io_dat_br_ltu_T = exe_rs1_data < exe_rs2_data; // @[Mux.scala:126:16] assign io_dat_br_ltu_0 = _io_dat_br_ltu_T; // @[dpath.scala:50:7, :207:42] wire [2:0] mem_address_low = _alu_io_out[2:0]; // @[dpath.scala:190:20, :211:37] wire [2:0] misaligned_mask; // @[dpath.scala:212:30] wire [3:0] _misaligned_mask_T = {1'h0, io_ctl_dmem_typ_0} - 4'h1; // @[dpath.scala:50:7, :213:54] wire [2:0] _misaligned_mask_T_1 = _misaligned_mask_T[2:0]; // @[dpath.scala:213:54] wire [1:0] _misaligned_mask_T_2 = _misaligned_mask_T_1[1:0]; // @[dpath.scala:213:{54,60}] wire [5:0] _misaligned_mask_T_3 = 6'h7 << _misaligned_mask_T_2; // @[dpath.scala:213:{34,60}] wire [5:0] _misaligned_mask_T_4 = ~_misaligned_mask_T_3; // @[dpath.scala:213:{23,34}] assign misaligned_mask = _misaligned_mask_T_4[2:0]; // @[dpath.scala:212:30, :213:{20,23}] wire [2:0] _io_dat_data_misaligned_T = misaligned_mask & mem_address_low; // @[dpath.scala:211:37, :212:30, :214:47] wire _io_dat_data_misaligned_T_1 = |_io_dat_data_misaligned_T; // @[dpath.scala:214:{47,66}] assign _io_dat_data_misaligned_T_2 = _io_dat_data_misaligned_T_1 & io_ctl_dmem_val_0; // @[dpath.scala:50:7, :214:{66,70}] assign io_dat_data_misaligned_0 = _io_dat_data_misaligned_T_2; // @[dpath.scala:50:7, :214:70] wire _io_dmem_req_valid_T = ~io_dat_data_misaligned_0; // @[dpath.scala:50:7, :217:48] wire _io_dmem_req_valid_T_1 = io_ctl_dmem_val_0 & _io_dmem_req_valid_T; // @[dpath.scala:50:7, :217:{45,48}] wire _io_dmem_req_valid_T_2 = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26, :217:75] assign _io_dmem_req_valid_T_3 = _io_dmem_req_valid_T_1 & _io_dmem_req_valid_T_2; // @[dpath.scala:217:{45,72,75}] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T_3; // @[dpath.scala:50:7, :217:72] wire _io_dmem_req_bits_fcn_T = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26, :221:50] wire _io_dmem_req_bits_fcn_T_1 = io_ctl_dmem_fcn_0 & _io_dmem_req_bits_fcn_T; // @[dpath.scala:50:7, :221:{48,50}] assign _io_dmem_req_bits_fcn_T_2 = _io_dmem_req_bits_fcn_T_1 & io_imem_resp_valid_0; // @[dpath.scala:50:7, :221:{48,67}] assign io_dmem_req_bits_fcn_0 = _io_dmem_req_bits_fcn_T_2; // @[dpath.scala:50:7, :221:67] wire _wb_dmiss_stall_T = ~io_dmem_req_ready_0; // @[dpath.scala:50:7, :227:23] wire _wb_dmiss_stall_T_1 = _wb_dmiss_stall_T & io_dmem_req_valid_0; // @[dpath.scala:50:7, :227:{23,42}] wire _wb_dmiss_stall_T_2 = ~io_dmem_resp_valid_0; // @[dpath.scala:50:7, :227:82] wire _wb_dmiss_stall_T_3 = wb_reg_mem & _wb_dmiss_stall_T_2; // @[dpath.scala:69:34, :227:{79,82}] assign _wb_dmiss_stall_T_4 = _wb_dmiss_stall_T_1 | _wb_dmiss_stall_T_3; // @[dpath.scala:227:{42,64,79}] assign wb_dmiss_stall = _wb_dmiss_stall_T_4; // @[dpath.scala:72:31, :227:64] wire [31:0] _csr_io_decode_0_inst_T = {wb_reg_csr_addr, 20'h0}; // @[dpath.scala:66:30, :261:47] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[dpath.scala:61:34, :262:35] wire [2:0] _csr_io_rw_cmd_T = wb_dmiss_stall ? 3'h0 : wb_reg_ctrl_csr_cmd; // @[dpath.scala:63:30, :72:31, :264:27] wire _csr_io_retire_T = ~io_ctl_exception_0; // @[dpath.scala:50:7, :144:78, :267:40] wire _csr_io_retire_T_1 = wb_reg_valid & _csr_io_retire_T; // @[dpath.scala:62:34, :267:{37,40}] wire _csr_io_tval_T = io_ctl_exception_cause_0 == 32'h2; // @[dpath.scala:50:7, :276:43] wire _csr_io_tval_T_1 = io_ctl_exception_cause_0 == 32'h0; // @[dpath.scala:50:7, :277:43] wire _csr_io_tval_T_2 = io_ctl_exception_cause_0 == 32'h6; // @[dpath.scala:50:7, :278:43] wire _csr_io_tval_T_3 = io_ctl_exception_cause_0 == 32'h4; // @[dpath.scala:50:7, :279:43] wire [31:0] _csr_io_tval_T_4 = _csr_io_tval_T_3 ? tval_data_ma : 32'h0; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_5 = _csr_io_tval_T_2 ? tval_data_ma : _csr_io_tval_T_4; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_6 = _csr_io_tval_T_1 ? tval_inst_ma : _csr_io_tval_T_5; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_7 = _csr_io_tval_T ? wb_reg_inst : _csr_io_tval_T_6; // @[Mux.scala:126:16] reg reg_interrupt_flag; // @[dpath.scala:283:36] wire _interrupt_edge_T = ~reg_interrupt_flag; // @[dpath.scala:283:36, :284:45] assign interrupt_edge = _csr_io_interrupt & _interrupt_edge_T; // @[dpath.scala:259:20, :284:{42,45}] assign io_dat_csr_interrupt_0 = interrupt_edge; // @[dpath.scala:50:7, :284:42] wire [31:0] _csr_io_cause_T = io_ctl_exception_0 ? io_ctl_exception_cause_0 : _csr_io_interrupt_cause; // @[dpath.scala:50:7, :259:20, :289:23] wire _wb_wbdata_T = wb_reg_ctrl_wb_sel == 2'h0; // @[dpath.scala:63:30, :301:39] wire _wb_wbdata_T_1 = wb_reg_ctrl_wb_sel == 2'h1; // @[dpath.scala:63:30, :302:39] wire _wb_wbdata_T_2 = wb_reg_ctrl_wb_sel == 2'h2; // @[dpath.scala:63:30, :303:39] wire _wb_wbdata_T_3 = &wb_reg_ctrl_wb_sel; // @[dpath.scala:63:30, :304:39] wire [31:0] _wb_wbdata_T_4 = _wb_wbdata_T_3 ? _csr_io_rw_rdata : wb_reg_alu; // @[Mux.scala:126:16] wire [31:0] _wb_wbdata_T_5 = _wb_wbdata_T_2 ? io_imem_resp_bits_pc_0 : _wb_wbdata_T_4; // @[Mux.scala:126:16] wire [31:0] _wb_wbdata_T_6 = _wb_wbdata_T_1 ? io_dmem_resp_bits_data_0 : _wb_wbdata_T_5; // @[Mux.scala:126:16] assign _wb_wbdata_T_7 = _wb_wbdata_T ? wb_reg_alu : _wb_wbdata_T_6; // @[Mux.scala:126:16] assign wb_wbdata = _wb_wbdata_T_7; // @[Mux.scala:126:16] wire _debug_wb_inst_T = wb_hazard_stall | io_ctl_exe_kill_0; // @[dpath.scala:50:7, :71:31, :310:53] wire _debug_wb_inst_T_1 = ~io_imem_resp_valid_0; // @[dpath.scala:50:7, :310:75] wire _debug_wb_inst_T_2 = _debug_wb_inst_T | _debug_wb_inst_T_1; // @[dpath.scala:310:{53,72,75}] wire [31:0] _debug_wb_inst_T_3 = _debug_wb_inst_T_2 ? 32'h4033 : io_imem_resp_bits_inst_0; // @[dpath.scala:50:7, :310:{35,72}] reg [31:0] debug_wb_inst; // @[dpath.scala:310:31] reg [4:0] REG; // @[dpath.scala:319:14] reg [31:0] REG_1; // @[dpath.scala:320:14] reg [4:0] REG_2; // @[dpath.scala:321:14] reg [31:0] REG_3; // @[dpath.scala:322:14]

Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_22 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `4` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `3` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<14> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_5_1, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_2, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_lo = cat(_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = shl(UInt<4>(0hf), 4) node _decoded_T_1 = xor(UInt<8>(0hff), _decoded_T) node _decoded_T_2 = shr(decoded_plaOutput, 4) node _decoded_T_3 = and(_decoded_T_2, _decoded_T_1) node _decoded_T_4 = bits(decoded_plaOutput, 3, 0) node _decoded_T_5 = shl(_decoded_T_4, 4) node _decoded_T_6 = not(_decoded_T_1) node _decoded_T_7 = and(_decoded_T_5, _decoded_T_6) node _decoded_T_8 = or(_decoded_T_3, _decoded_T_7) node _decoded_T_9 = bits(_decoded_T_1, 5, 0) node _decoded_T_10 = shl(_decoded_T_9, 2) node _decoded_T_11 = xor(_decoded_T_1, _decoded_T_10) node _decoded_T_12 = shr(_decoded_T_8, 2) node _decoded_T_13 = and(_decoded_T_12, _decoded_T_11) node _decoded_T_14 = bits(_decoded_T_8, 5, 0) node _decoded_T_15 = shl(_decoded_T_14, 2) node _decoded_T_16 = not(_decoded_T_11) node _decoded_T_17 = and(_decoded_T_15, _decoded_T_16) node _decoded_T_18 = or(_decoded_T_13, _decoded_T_17) node _decoded_T_19 = bits(_decoded_T_11, 6, 0) node _decoded_T_20 = shl(_decoded_T_19, 1) node _decoded_T_21 = xor(_decoded_T_11, _decoded_T_20) node _decoded_T_22 = shr(_decoded_T_18, 1) node _decoded_T_23 = and(_decoded_T_22, _decoded_T_21) node _decoded_T_24 = bits(_decoded_T_18, 6, 0) node _decoded_T_25 = shl(_decoded_T_24, 1) node _decoded_T_26 = not(_decoded_T_21) node _decoded_T_27 = and(_decoded_T_25, _decoded_T_26) node decoded = or(_decoded_T_23, _decoded_T_27) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_3_0_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`3`[0], _io_resp_0_vc_sel_3_0_T node _io_resp_0_vc_sel_3_1_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`3`[1], _io_resp_0_vc_sel_3_1_T connect io.resp.`0`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<14> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_3 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_2_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 7, 7) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_9, _decoded_invMatrixOutputs_T_8) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_13, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_15, _decoded_invMatrixOutputs_T_14) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_28 = shl(UInt<4>(0hf), 4) node _decoded_T_29 = xor(UInt<8>(0hff), _decoded_T_28) node _decoded_T_30 = shr(decoded_plaOutput_1, 4) node _decoded_T_31 = and(_decoded_T_30, _decoded_T_29) node _decoded_T_32 = bits(decoded_plaOutput_1, 3, 0) node _decoded_T_33 = shl(_decoded_T_32, 4) node _decoded_T_34 = not(_decoded_T_29) node _decoded_T_35 = and(_decoded_T_33, _decoded_T_34) node _decoded_T_36 = or(_decoded_T_31, _decoded_T_35) node _decoded_T_37 = bits(_decoded_T_29, 5, 0) node _decoded_T_38 = shl(_decoded_T_37, 2) node _decoded_T_39 = xor(_decoded_T_29, _decoded_T_38) node _decoded_T_40 = shr(_decoded_T_36, 2) node _decoded_T_41 = and(_decoded_T_40, _decoded_T_39) node _decoded_T_42 = bits(_decoded_T_36, 5, 0) node _decoded_T_43 = shl(_decoded_T_42, 2) node _decoded_T_44 = not(_decoded_T_39) node _decoded_T_45 = and(_decoded_T_43, _decoded_T_44) node _decoded_T_46 = or(_decoded_T_41, _decoded_T_45) node _decoded_T_47 = bits(_decoded_T_39, 6, 0) node _decoded_T_48 = shl(_decoded_T_47, 1) node _decoded_T_49 = xor(_decoded_T_39, _decoded_T_48) node _decoded_T_50 = shr(_decoded_T_46, 1) node _decoded_T_51 = and(_decoded_T_50, _decoded_T_49) node _decoded_T_52 = bits(_decoded_T_46, 6, 0) node _decoded_T_53 = shl(_decoded_T_52, 1) node _decoded_T_54 = not(_decoded_T_49) node _decoded_T_55 = and(_decoded_T_53, _decoded_T_54) node decoded_1 = or(_decoded_T_51, _decoded_T_55) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_3_0_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`3`[0], _io_resp_1_vc_sel_3_0_T node _io_resp_1_vc_sel_3_1_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`3`[1], _io_resp_1_vc_sel_3_1_T connect io.resp.`1`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<14> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_2, 12, 12) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_plaInput_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_2, 12, 12) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_plaInput_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_2, 12, 12) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_9) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_2_2_2) node _decoded_orMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_8 = orr(_decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_lo_2 = cat(_decoded_orMatrixOutputs_T_6, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_8, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_2, 7, 7) node decoded_invMatrixOutputs_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20) node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_56 = shl(UInt<4>(0hf), 4) node _decoded_T_57 = xor(UInt<8>(0hff), _decoded_T_56) node _decoded_T_58 = shr(decoded_plaOutput_2, 4) node _decoded_T_59 = and(_decoded_T_58, _decoded_T_57) node _decoded_T_60 = bits(decoded_plaOutput_2, 3, 0) node _decoded_T_61 = shl(_decoded_T_60, 4) node _decoded_T_62 = not(_decoded_T_57) node _decoded_T_63 = and(_decoded_T_61, _decoded_T_62) node _decoded_T_64 = or(_decoded_T_59, _decoded_T_63) node _decoded_T_65 = bits(_decoded_T_57, 5, 0) node _decoded_T_66 = shl(_decoded_T_65, 2) node _decoded_T_67 = xor(_decoded_T_57, _decoded_T_66) node _decoded_T_68 = shr(_decoded_T_64, 2) node _decoded_T_69 = and(_decoded_T_68, _decoded_T_67) node _decoded_T_70 = bits(_decoded_T_64, 5, 0) node _decoded_T_71 = shl(_decoded_T_70, 2) node _decoded_T_72 = not(_decoded_T_67) node _decoded_T_73 = and(_decoded_T_71, _decoded_T_72) node _decoded_T_74 = or(_decoded_T_69, _decoded_T_73) node _decoded_T_75 = bits(_decoded_T_67, 6, 0) node _decoded_T_76 = shl(_decoded_T_75, 1) node _decoded_T_77 = xor(_decoded_T_67, _decoded_T_76) node _decoded_T_78 = shr(_decoded_T_74, 1) node _decoded_T_79 = and(_decoded_T_78, _decoded_T_77) node _decoded_T_80 = bits(_decoded_T_74, 6, 0) node _decoded_T_81 = shl(_decoded_T_80, 1) node _decoded_T_82 = not(_decoded_T_77) node _decoded_T_83 = and(_decoded_T_81, _decoded_T_82) node decoded_2 = or(_decoded_T_79, _decoded_T_83) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_3_0_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`3`[0], _io_resp_2_vc_sel_3_0_T node _io_resp_2_vc_sel_3_1_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`3`[1], _io_resp_2_vc_sel_3_1_T connect io.resp.`2`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h1) node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id) node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node) node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id) node _addr_T_3 = cat(addr_hi_3, addr_lo_3) node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3) wire decoded_plaInput_3 : UInt<14> node decoded_invInputs_3 = not(decoded_plaInput_3) wire decoded_plaOutput_3 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_plaInput_3, 12, 12) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_0_2_3) node decoded_orMatrixOutputs_lo_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_3 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3) node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_3, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_3, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_3, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_3, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_3, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_3, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_3, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_3, 7, 7) node decoded_invMatrixOutputs_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_25, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_27, _decoded_invMatrixOutputs_T_26) node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3) node decoded_invMatrixOutputs_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_31, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3) node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3) connect decoded_plaOutput_3, decoded_invMatrixOutputs_3 connect decoded_plaInput_3, addr_3 node _decoded_T_84 = shl(UInt<4>(0hf), 4) node _decoded_T_85 = xor(UInt<8>(0hff), _decoded_T_84) node _decoded_T_86 = shr(decoded_plaOutput_3, 4) node _decoded_T_87 = and(_decoded_T_86, _decoded_T_85) node _decoded_T_88 = bits(decoded_plaOutput_3, 3, 0) node _decoded_T_89 = shl(_decoded_T_88, 4) node _decoded_T_90 = not(_decoded_T_85) node _decoded_T_91 = and(_decoded_T_89, _decoded_T_90) node _decoded_T_92 = or(_decoded_T_87, _decoded_T_91) node _decoded_T_93 = bits(_decoded_T_85, 5, 0) node _decoded_T_94 = shl(_decoded_T_93, 2) node _decoded_T_95 = xor(_decoded_T_85, _decoded_T_94) node _decoded_T_96 = shr(_decoded_T_92, 2) node _decoded_T_97 = and(_decoded_T_96, _decoded_T_95) node _decoded_T_98 = bits(_decoded_T_92, 5, 0) node _decoded_T_99 = shl(_decoded_T_98, 2) node _decoded_T_100 = not(_decoded_T_95) node _decoded_T_101 = and(_decoded_T_99, _decoded_T_100) node _decoded_T_102 = or(_decoded_T_97, _decoded_T_101) node _decoded_T_103 = bits(_decoded_T_95, 6, 0) node _decoded_T_104 = shl(_decoded_T_103, 1) node _decoded_T_105 = xor(_decoded_T_95, _decoded_T_104) node _decoded_T_106 = shr(_decoded_T_102, 1) node _decoded_T_107 = and(_decoded_T_106, _decoded_T_105) node _decoded_T_108 = bits(_decoded_T_102, 6, 0) node _decoded_T_109 = shl(_decoded_T_108, 1) node _decoded_T_110 = not(_decoded_T_105) node _decoded_T_111 = and(_decoded_T_109, _decoded_T_110) node decoded_3 = or(_decoded_T_107, _decoded_T_111) node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0) connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1) connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 2, 2) connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 3, 3) connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T node _io_resp_3_vc_sel_2_0_T = bits(decoded_3, 4, 4) connect io.resp.`3`.vc_sel.`2`[0], _io_resp_3_vc_sel_2_0_T node _io_resp_3_vc_sel_2_1_T = bits(decoded_3, 5, 5) connect io.resp.`3`.vc_sel.`2`[1], _io_resp_3_vc_sel_2_1_T node _io_resp_3_vc_sel_3_0_T = bits(decoded_3, 6, 6) connect io.resp.`3`.vc_sel.`3`[0], _io_resp_3_vc_sel_3_0_T node _io_resp_3_vc_sel_3_1_T = bits(decoded_3, 7, 7) connect io.resp.`3`.vc_sel.`3`[1], _io_resp_3_vc_sel_3_1_T connect io.resp.`3`.vc_sel.`4`[0], UInt<1>(0h0) connect io.req.`4`.ready, UInt<1>(0h1) node addr_lo_4 = cat(io.req.`4`.bits.flow.egress_node, io.req.`4`.bits.flow.egress_node_id) node addr_hi_hi_4 = cat(io.req.`4`.bits.flow.vnet_id, io.req.`4`.bits.flow.ingress_node) node addr_hi_4 = cat(addr_hi_hi_4, io.req.`4`.bits.flow.ingress_node_id) node _addr_T_4 = cat(addr_hi_4, addr_lo_4) node addr_4 = cat(io.req.`4`.bits.src_virt_id, _addr_T_4) wire decoded_plaInput_4 : UInt<14> node decoded_invInputs_4 = not(decoded_plaInput_4) wire decoded_plaOutput_4 : UInt<8> node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_4 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_13) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_1_2_3 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_2_2_3 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_plaInput_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_16) node _decoded_orMatrixOutputs_T_10 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_11 = orr(decoded_andMatrixOutputs_3_2_1) node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_0_2_4, decoded_andMatrixOutputs_1_2_3) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_5, decoded_andMatrixOutputs_2_2_3) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node _decoded_orMatrixOutputs_T_14 = orr(decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_hi_hi_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_4) node decoded_orMatrixOutputs_4 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_4, 0, 0) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_4, 1, 1) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_4, 2, 2) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_4, 3, 3) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_4, 4, 4) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_4, 5, 5) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_4, 6, 6) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_4, 7, 7) node decoded_invMatrixOutputs_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_33, _decoded_invMatrixOutputs_T_32) node decoded_invMatrixOutputs_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_4, decoded_invMatrixOutputs_lo_lo_4) node decoded_invMatrixOutputs_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_37, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_39, _decoded_invMatrixOutputs_T_38) node decoded_invMatrixOutputs_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_4, decoded_invMatrixOutputs_hi_lo_4) node decoded_invMatrixOutputs_4 = cat(decoded_invMatrixOutputs_hi_4, decoded_invMatrixOutputs_lo_4) connect decoded_plaOutput_4, decoded_invMatrixOutputs_4 connect decoded_plaInput_4, addr_4 node _decoded_T_112 = shl(UInt<4>(0hf), 4) node _decoded_T_113 = xor(UInt<8>(0hff), _decoded_T_112) node _decoded_T_114 = shr(decoded_plaOutput_4, 4) node _decoded_T_115 = and(_decoded_T_114, _decoded_T_113) node _decoded_T_116 = bits(decoded_plaOutput_4, 3, 0) node _decoded_T_117 = shl(_decoded_T_116, 4) node _decoded_T_118 = not(_decoded_T_113) node _decoded_T_119 = and(_decoded_T_117, _decoded_T_118) node _decoded_T_120 = or(_decoded_T_115, _decoded_T_119) node _decoded_T_121 = bits(_decoded_T_113, 5, 0) node _decoded_T_122 = shl(_decoded_T_121, 2) node _decoded_T_123 = xor(_decoded_T_113, _decoded_T_122) node _decoded_T_124 = shr(_decoded_T_120, 2) node _decoded_T_125 = and(_decoded_T_124, _decoded_T_123) node _decoded_T_126 = bits(_decoded_T_120, 5, 0) node _decoded_T_127 = shl(_decoded_T_126, 2) node _decoded_T_128 = not(_decoded_T_123) node _decoded_T_129 = and(_decoded_T_127, _decoded_T_128) node _decoded_T_130 = or(_decoded_T_125, _decoded_T_129) node _decoded_T_131 = bits(_decoded_T_123, 6, 0) node _decoded_T_132 = shl(_decoded_T_131, 1) node _decoded_T_133 = xor(_decoded_T_123, _decoded_T_132) node _decoded_T_134 = shr(_decoded_T_130, 1) node _decoded_T_135 = and(_decoded_T_134, _decoded_T_133) node _decoded_T_136 = bits(_decoded_T_130, 6, 0) node _decoded_T_137 = shl(_decoded_T_136, 1) node _decoded_T_138 = not(_decoded_T_133) node _decoded_T_139 = and(_decoded_T_137, _decoded_T_138) node decoded_4 = or(_decoded_T_135, _decoded_T_139) node _io_resp_4_vc_sel_0_0_T = bits(decoded_4, 0, 0) connect io.resp.`4`.vc_sel.`0`[0], _io_resp_4_vc_sel_0_0_T node _io_resp_4_vc_sel_0_1_T = bits(decoded_4, 1, 1) connect io.resp.`4`.vc_sel.`0`[1], _io_resp_4_vc_sel_0_1_T node _io_resp_4_vc_sel_1_0_T = bits(decoded_4, 2, 2) connect io.resp.`4`.vc_sel.`1`[0], _io_resp_4_vc_sel_1_0_T node _io_resp_4_vc_sel_1_1_T = bits(decoded_4, 3, 3) connect io.resp.`4`.vc_sel.`1`[1], _io_resp_4_vc_sel_1_1_T node _io_resp_4_vc_sel_2_0_T = bits(decoded_4, 4, 4) connect io.resp.`4`.vc_sel.`2`[0], _io_resp_4_vc_sel_2_0_T node _io_resp_4_vc_sel_2_1_T = bits(decoded_4, 5, 5) connect io.resp.`4`.vc_sel.`2`[1], _io_resp_4_vc_sel_2_1_T node _io_resp_4_vc_sel_3_0_T = bits(decoded_4, 6, 6) connect io.resp.`4`.vc_sel.`3`[0], _io_resp_4_vc_sel_3_0_T node _io_resp_4_vc_sel_3_1_T = bits(decoded_4, 7, 7) connect io.resp.`4`.vc_sel.`3`[1], _io_resp_4_vc_sel_3_1_T connect io.resp.`4`.vc_sel.`4`[0], UInt<1>(0h0) extmodule plusarg_reader_48 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20

module RouteComputer_22( // @[RouteComputer.scala:29:7] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14] ); wire [12:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [12:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [12:0] decoded_invInputs_2 = ~{io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [3:0] _GEN = ~io_req_4_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_4_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_4_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_3_1 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_1 = &{_GEN_0[0], _GEN_0[1], io_req_4_bits_flow_egress_node[0], io_req_4_bits_flow_egress_node[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_1 = |{&{_GEN_0[1], _GEN[1], _GEN[2], _GEN[3]}, &{_GEN_0[0], _GEN[1], io_req_4_bits_flow_egress_node[2]}, &{_GEN_0[0], _GEN[1], io_req_4_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_1 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], _GEN[2], _GEN[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_3_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_1 = &{~(io_req_3_bits_flow_egress_node_id[0]), io_req_3_bits_flow_vnet_id}; // @[pla.scala:78:21, :98:{53,70}] assign io_resp_2_vc_sel_3_0 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], decoded_invInputs_2[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_0 = |{&{decoded_invInputs_2[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], decoded_invInputs_2[12]}, &{decoded_invInputs_2[0], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[11], decoded_invInputs_2[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_3_0 = &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_3_1 = &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_1 = &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_3_0 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_169 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_169( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_99 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_99 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_99( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_99 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_ScratchpadBank : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_53 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a28d64s4k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_109 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLFragmenter_ScratchpadBank( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [3:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [27:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]

Generate the Verilog code corresponding to this FIRRTL code module Tile_111 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_367 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_111( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_367 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_88 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_88( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_58 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_6 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_120 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_121 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_58 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_61 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_61( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_32 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h1), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h1), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h1), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h1), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h1), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_64 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_65 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_5 : input clock : Clock input reset : Reset output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[10]} cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [28] wire _heads_WIRE : UInt<5>[10] connect _heads_WIRE[0], UInt<5>(0h0) connect _heads_WIRE[1], UInt<5>(0h4) connect _heads_WIRE[2], UInt<5>(0h0) connect _heads_WIRE[3], UInt<5>(0h8) connect _heads_WIRE[4], UInt<5>(0hc) connect _heads_WIRE[5], UInt<5>(0h10) connect _heads_WIRE[6], UInt<5>(0h0) connect _heads_WIRE[7], UInt<5>(0h0) connect _heads_WIRE[8], UInt<5>(0h14) connect _heads_WIRE[9], UInt<5>(0h18) regreset heads : UInt<5>[10], clock, reset, _heads_WIRE wire _tails_WIRE : UInt<5>[10] connect _tails_WIRE[0], UInt<5>(0h0) connect _tails_WIRE[1], UInt<5>(0h4) connect _tails_WIRE[2], UInt<5>(0h0) connect _tails_WIRE[3], UInt<5>(0h8) connect _tails_WIRE[4], UInt<5>(0hc) connect _tails_WIRE[5], UInt<5>(0h10) connect _tails_WIRE[6], UInt<5>(0h0) connect _tails_WIRE[7], UInt<5>(0h0) connect _tails_WIRE[8], UInt<5>(0h14) connect _tails_WIRE[9], UInt<5>(0h18) regreset tails : UInt<5>[10], clock, reset, _tails_WIRE node empty_0 = eq(heads[0], tails[0]) node empty_1 = eq(heads[1], tails[1]) node empty_2 = eq(heads[2], tails[2]) node empty_3 = eq(heads[3], tails[3]) node empty_4 = eq(heads[4], tails[4]) node empty_5 = eq(heads[5], tails[5]) node empty_6 = eq(heads[6], tails[6]) node empty_7 = eq(heads[7], tails[7]) node empty_8 = eq(heads[8], tails[8]) node empty_9 = eq(heads[9], tails[9]) inst qs_0 of Queue1_BaseFlit_50 connect qs_0.clock, clock connect qs_0.reset, reset inst qs_1 of Queue1_BaseFlit_51 connect qs_1.clock, clock connect qs_1.reset, reset inst qs_2 of Queue1_BaseFlit_52 connect qs_2.clock, clock connect qs_2.reset, reset inst qs_3 of Queue1_BaseFlit_53 connect qs_3.clock, clock connect qs_3.reset, reset inst qs_4 of Queue1_BaseFlit_54 connect qs_4.clock, clock connect qs_4.reset, reset inst qs_5 of Queue1_BaseFlit_55 connect qs_5.clock, clock connect qs_5.reset, reset inst qs_6 of Queue1_BaseFlit_56 connect qs_6.clock, clock connect qs_6.reset, reset inst qs_7 of Queue1_BaseFlit_57 connect qs_7.clock, clock connect qs_7.reset, reset inst qs_8 of Queue1_BaseFlit_58 connect qs_8.clock, clock connect qs_8.reset, reset inst qs_9 of Queue1_BaseFlit_59 connect qs_9.clock, clock connect qs_9.reset, reset connect qs_0.io.enq.valid, UInt<1>(0h0) connect qs_1.io.enq.valid, UInt<1>(0h0) connect qs_2.io.enq.valid, UInt<1>(0h0) connect qs_3.io.enq.valid, UInt<1>(0h0) connect qs_4.io.enq.valid, UInt<1>(0h0) connect qs_5.io.enq.valid, UInt<1>(0h0) connect qs_6.io.enq.valid, UInt<1>(0h0) connect qs_7.io.enq.valid, UInt<1>(0h0) connect qs_8.io.enq.valid, UInt<1>(0h0) connect qs_9.io.enq.valid, UInt<1>(0h0) invalidate qs_0.io.enq.bits.payload invalidate qs_0.io.enq.bits.tail invalidate qs_0.io.enq.bits.head invalidate qs_1.io.enq.bits.payload invalidate qs_1.io.enq.bits.tail invalidate qs_1.io.enq.bits.head invalidate qs_2.io.enq.bits.payload invalidate qs_2.io.enq.bits.tail invalidate qs_2.io.enq.bits.head invalidate qs_3.io.enq.bits.payload invalidate qs_3.io.enq.bits.tail invalidate qs_3.io.enq.bits.head invalidate qs_4.io.enq.bits.payload invalidate qs_4.io.enq.bits.tail invalidate qs_4.io.enq.bits.head invalidate qs_5.io.enq.bits.payload invalidate qs_5.io.enq.bits.tail invalidate qs_5.io.enq.bits.head invalidate qs_6.io.enq.bits.payload invalidate qs_6.io.enq.bits.tail invalidate qs_6.io.enq.bits.head invalidate qs_7.io.enq.bits.payload invalidate qs_7.io.enq.bits.tail invalidate qs_7.io.enq.bits.head invalidate qs_8.io.enq.bits.payload invalidate qs_8.io.enq.bits.tail invalidate qs_8.io.enq.bits.head invalidate qs_9.io.enq.bits.payload invalidate qs_9.io.enq.bits.tail invalidate qs_9.io.enq.bits.head node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id) wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} node _direct_to_q_T = bits(vc_sel, 0, 0) node _direct_to_q_T_1 = bits(vc_sel, 1, 1) node _direct_to_q_T_2 = bits(vc_sel, 2, 2) node _direct_to_q_T_3 = bits(vc_sel, 3, 3) node _direct_to_q_T_4 = bits(vc_sel, 4, 4) node _direct_to_q_T_5 = bits(vc_sel, 5, 5) node _direct_to_q_T_6 = bits(vc_sel, 6, 6) node _direct_to_q_T_7 = bits(vc_sel, 7, 7) node _direct_to_q_T_8 = bits(vc_sel, 8, 8) node _direct_to_q_T_9 = bits(vc_sel, 9, 9) node _direct_to_q_T_10 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_11 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_12 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_13 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_14 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_15 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_16 = mux(_direct_to_q_T_6, qs_6.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_17 = mux(_direct_to_q_T_7, qs_7.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_18 = mux(_direct_to_q_T_8, qs_8.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_19 = mux(_direct_to_q_T_9, qs_9.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_20 = or(_direct_to_q_T_10, _direct_to_q_T_11) node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_12) node _direct_to_q_T_22 = or(_direct_to_q_T_21, _direct_to_q_T_13) node _direct_to_q_T_23 = or(_direct_to_q_T_22, _direct_to_q_T_14) node _direct_to_q_T_24 = or(_direct_to_q_T_23, _direct_to_q_T_15) node _direct_to_q_T_25 = or(_direct_to_q_T_24, _direct_to_q_T_16) node _direct_to_q_T_26 = or(_direct_to_q_T_25, _direct_to_q_T_17) node _direct_to_q_T_27 = or(_direct_to_q_T_26, _direct_to_q_T_18) node _direct_to_q_T_28 = or(_direct_to_q_T_27, _direct_to_q_T_19) wire _direct_to_q_WIRE : UInt<1> connect _direct_to_q_WIRE, _direct_to_q_T_28 node _direct_to_q_T_29 = bits(vc_sel, 0, 0) node _direct_to_q_T_30 = bits(vc_sel, 1, 1) node _direct_to_q_T_31 = bits(vc_sel, 2, 2) node _direct_to_q_T_32 = bits(vc_sel, 3, 3) node _direct_to_q_T_33 = bits(vc_sel, 4, 4) node _direct_to_q_T_34 = bits(vc_sel, 5, 5) node _direct_to_q_T_35 = bits(vc_sel, 6, 6) node _direct_to_q_T_36 = bits(vc_sel, 7, 7) node _direct_to_q_T_37 = bits(vc_sel, 8, 8) node _direct_to_q_T_38 = bits(vc_sel, 9, 9) node _direct_to_q_T_39 = mux(_direct_to_q_T_29, empty_0, UInt<1>(0h0)) node _direct_to_q_T_40 = mux(_direct_to_q_T_30, empty_1, UInt<1>(0h0)) node _direct_to_q_T_41 = mux(_direct_to_q_T_31, empty_2, UInt<1>(0h0)) node _direct_to_q_T_42 = mux(_direct_to_q_T_32, empty_3, UInt<1>(0h0)) node _direct_to_q_T_43 = mux(_direct_to_q_T_33, empty_4, UInt<1>(0h0)) node _direct_to_q_T_44 = mux(_direct_to_q_T_34, empty_5, UInt<1>(0h0)) node _direct_to_q_T_45 = mux(_direct_to_q_T_35, empty_6, UInt<1>(0h0)) node _direct_to_q_T_46 = mux(_direct_to_q_T_36, empty_7, UInt<1>(0h0)) node _direct_to_q_T_47 = mux(_direct_to_q_T_37, empty_8, UInt<1>(0h0)) node _direct_to_q_T_48 = mux(_direct_to_q_T_38, empty_9, UInt<1>(0h0)) node _direct_to_q_T_49 = or(_direct_to_q_T_39, _direct_to_q_T_40) node _direct_to_q_T_50 = or(_direct_to_q_T_49, _direct_to_q_T_41) node _direct_to_q_T_51 = or(_direct_to_q_T_50, _direct_to_q_T_42) node _direct_to_q_T_52 = or(_direct_to_q_T_51, _direct_to_q_T_43) node _direct_to_q_T_53 = or(_direct_to_q_T_52, _direct_to_q_T_44) node _direct_to_q_T_54 = or(_direct_to_q_T_53, _direct_to_q_T_45) node _direct_to_q_T_55 = or(_direct_to_q_T_54, _direct_to_q_T_46) node _direct_to_q_T_56 = or(_direct_to_q_T_55, _direct_to_q_T_47) node _direct_to_q_T_57 = or(_direct_to_q_T_56, _direct_to_q_T_48) wire _direct_to_q_WIRE_1 : UInt<1> connect _direct_to_q_WIRE_1, _direct_to_q_T_57 node _direct_to_q_T_58 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1) node direct_to_q = and(_direct_to_q_T_58, UInt<1>(0h1)) connect flit.head, io.enq[0].bits.head connect flit.tail, io.enq[0].bits.tail connect flit.payload, io.enq[0].bits.payload node _T = eq(direct_to_q, UInt<1>(0h0)) node _T_1 = and(io.enq[0].valid, _T) when _T_1 : write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock connect MPORT, flit node _tails_T = bits(vc_sel, 0, 0) node _tails_T_1 = bits(vc_sel, 1, 1) node _tails_T_2 = bits(vc_sel, 2, 2) node _tails_T_3 = bits(vc_sel, 3, 3) node _tails_T_4 = bits(vc_sel, 4, 4) node _tails_T_5 = bits(vc_sel, 5, 5) node _tails_T_6 = bits(vc_sel, 6, 6) node _tails_T_7 = bits(vc_sel, 7, 7) node _tails_T_8 = bits(vc_sel, 8, 8) node _tails_T_9 = bits(vc_sel, 9, 9) node _tails_T_10 = mux(_tails_T, UInt<2>(0h3), UInt<1>(0h0)) node _tails_T_11 = mux(_tails_T_1, UInt<3>(0h7), UInt<1>(0h0)) node _tails_T_12 = mux(_tails_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_13 = mux(_tails_T_3, UInt<4>(0hb), UInt<1>(0h0)) node _tails_T_14 = mux(_tails_T_4, UInt<4>(0hf), UInt<1>(0h0)) node _tails_T_15 = mux(_tails_T_5, UInt<5>(0h13), UInt<1>(0h0)) node _tails_T_16 = mux(_tails_T_6, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_17 = mux(_tails_T_7, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_18 = mux(_tails_T_8, UInt<5>(0h17), UInt<1>(0h0)) node _tails_T_19 = mux(_tails_T_9, UInt<5>(0h1b), UInt<1>(0h0)) node _tails_T_20 = or(_tails_T_10, _tails_T_11) node _tails_T_21 = or(_tails_T_20, _tails_T_12) node _tails_T_22 = or(_tails_T_21, _tails_T_13) node _tails_T_23 = or(_tails_T_22, _tails_T_14) node _tails_T_24 = or(_tails_T_23, _tails_T_15) node _tails_T_25 = or(_tails_T_24, _tails_T_16) node _tails_T_26 = or(_tails_T_25, _tails_T_17) node _tails_T_27 = or(_tails_T_26, _tails_T_18) node _tails_T_28 = or(_tails_T_27, _tails_T_19) wire _tails_WIRE_1 : UInt<5> connect _tails_WIRE_1, _tails_T_28 node _tails_T_29 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1) node _tails_T_30 = bits(vc_sel, 0, 0) node _tails_T_31 = bits(vc_sel, 1, 1) node _tails_T_32 = bits(vc_sel, 2, 2) node _tails_T_33 = bits(vc_sel, 3, 3) node _tails_T_34 = bits(vc_sel, 4, 4) node _tails_T_35 = bits(vc_sel, 5, 5) node _tails_T_36 = bits(vc_sel, 6, 6) node _tails_T_37 = bits(vc_sel, 7, 7) node _tails_T_38 = bits(vc_sel, 8, 8) node _tails_T_39 = bits(vc_sel, 9, 9) node _tails_T_40 = mux(_tails_T_30, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_41 = mux(_tails_T_31, UInt<3>(0h4), UInt<1>(0h0)) node _tails_T_42 = mux(_tails_T_32, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_43 = mux(_tails_T_33, UInt<4>(0h8), UInt<1>(0h0)) node _tails_T_44 = mux(_tails_T_34, UInt<4>(0hc), UInt<1>(0h0)) node _tails_T_45 = mux(_tails_T_35, UInt<5>(0h10), UInt<1>(0h0)) node _tails_T_46 = mux(_tails_T_36, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_47 = mux(_tails_T_37, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_48 = mux(_tails_T_38, UInt<5>(0h14), UInt<1>(0h0)) node _tails_T_49 = mux(_tails_T_39, UInt<5>(0h18), UInt<1>(0h0)) node _tails_T_50 = or(_tails_T_40, _tails_T_41) node _tails_T_51 = or(_tails_T_50, _tails_T_42) node _tails_T_52 = or(_tails_T_51, _tails_T_43) node _tails_T_53 = or(_tails_T_52, _tails_T_44) node _tails_T_54 = or(_tails_T_53, _tails_T_45) node _tails_T_55 = or(_tails_T_54, _tails_T_46) node _tails_T_56 = or(_tails_T_55, _tails_T_47) node _tails_T_57 = or(_tails_T_56, _tails_T_48) node _tails_T_58 = or(_tails_T_57, _tails_T_49) wire _tails_WIRE_2 : UInt<5> connect _tails_WIRE_2, _tails_T_58 node _tails_T_59 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1)) node _tails_T_60 = tail(_tails_T_59, 1) node _tails_T_61 = mux(_tails_T_29, _tails_WIRE_2, _tails_T_60) connect tails[io.enq[0].bits.virt_channel_id], _tails_T_61 else : node _T_2 = and(io.enq[0].valid, direct_to_q) when _T_2 : node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0)) when _T_3 : connect qs_0.io.enq.valid, UInt<1>(0h1) connect qs_0.io.enq.bits.payload, flit.payload connect qs_0.io.enq.bits.tail, flit.tail connect qs_0.io.enq.bits.head, flit.head node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1)) when _T_4 : connect qs_1.io.enq.valid, UInt<1>(0h1) connect qs_1.io.enq.bits.payload, flit.payload connect qs_1.io.enq.bits.tail, flit.tail connect qs_1.io.enq.bits.head, flit.head node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2)) when _T_5 : connect qs_2.io.enq.valid, UInt<1>(0h1) connect qs_2.io.enq.bits.payload, flit.payload connect qs_2.io.enq.bits.tail, flit.tail connect qs_2.io.enq.bits.head, flit.head node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3)) when _T_6 : connect qs_3.io.enq.valid, UInt<1>(0h1) connect qs_3.io.enq.bits.payload, flit.payload connect qs_3.io.enq.bits.tail, flit.tail connect qs_3.io.enq.bits.head, flit.head node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4)) when _T_7 : connect qs_4.io.enq.valid, UInt<1>(0h1) connect qs_4.io.enq.bits.payload, flit.payload connect qs_4.io.enq.bits.tail, flit.tail connect qs_4.io.enq.bits.head, flit.head node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5)) when _T_8 : connect qs_5.io.enq.valid, UInt<1>(0h1) connect qs_5.io.enq.bits.payload, flit.payload connect qs_5.io.enq.bits.tail, flit.tail connect qs_5.io.enq.bits.head, flit.head node _T_9 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h6)) when _T_9 : connect qs_6.io.enq.valid, UInt<1>(0h1) connect qs_6.io.enq.bits.payload, flit.payload connect qs_6.io.enq.bits.tail, flit.tail connect qs_6.io.enq.bits.head, flit.head node _T_10 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h7)) when _T_10 : connect qs_7.io.enq.valid, UInt<1>(0h1) connect qs_7.io.enq.bits.payload, flit.payload connect qs_7.io.enq.bits.tail, flit.tail connect qs_7.io.enq.bits.head, flit.head node _T_11 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h8)) when _T_11 : connect qs_8.io.enq.valid, UInt<1>(0h1) connect qs_8.io.enq.bits.payload, flit.payload connect qs_8.io.enq.bits.tail, flit.tail connect qs_8.io.enq.bits.head, flit.head node _T_12 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h9)) when _T_12 : connect qs_9.io.enq.valid, UInt<1>(0h1) connect qs_9.io.enq.bits.payload, flit.payload connect qs_9.io.enq.bits.tail, flit.tail connect qs_9.io.enq.bits.head, flit.head node _can_to_q_T = eq(empty_0, UInt<1>(0h0)) node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready) node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0)) node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready) node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0)) node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready) node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0)) node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready) node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0)) node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready) node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0)) node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready) node _can_to_q_T_6 = eq(empty_6, UInt<1>(0h0)) node can_to_q_6 = and(_can_to_q_T_6, qs_6.io.enq.ready) node _can_to_q_T_7 = eq(empty_7, UInt<1>(0h0)) node can_to_q_7 = and(_can_to_q_T_7, qs_7.io.enq.ready) node _can_to_q_T_8 = eq(empty_8, UInt<1>(0h0)) node can_to_q_8 = and(_can_to_q_T_8, qs_8.io.enq.ready) node _can_to_q_T_9 = eq(empty_9, UInt<1>(0h0)) node can_to_q_9 = and(_can_to_q_T_9, qs_9.io.enq.ready) node _to_q_oh_enc_T = mux(can_to_q_9, UInt<10>(0h200), UInt<10>(0h0)) node _to_q_oh_enc_T_1 = mux(can_to_q_8, UInt<10>(0h100), _to_q_oh_enc_T) node _to_q_oh_enc_T_2 = mux(can_to_q_7, UInt<10>(0h80), _to_q_oh_enc_T_1) node _to_q_oh_enc_T_3 = mux(can_to_q_6, UInt<10>(0h40), _to_q_oh_enc_T_2) node _to_q_oh_enc_T_4 = mux(can_to_q_5, UInt<10>(0h20), _to_q_oh_enc_T_3) node _to_q_oh_enc_T_5 = mux(can_to_q_4, UInt<10>(0h10), _to_q_oh_enc_T_4) node _to_q_oh_enc_T_6 = mux(can_to_q_3, UInt<10>(0h8), _to_q_oh_enc_T_5) node _to_q_oh_enc_T_7 = mux(can_to_q_2, UInt<10>(0h4), _to_q_oh_enc_T_6) node _to_q_oh_enc_T_8 = mux(can_to_q_1, UInt<10>(0h2), _to_q_oh_enc_T_7) node to_q_oh_enc = mux(can_to_q_0, UInt<10>(0h1), _to_q_oh_enc_T_8) node to_q_oh_0 = bits(to_q_oh_enc, 0, 0) node to_q_oh_1 = bits(to_q_oh_enc, 1, 1) node to_q_oh_2 = bits(to_q_oh_enc, 2, 2) node to_q_oh_3 = bits(to_q_oh_enc, 3, 3) node to_q_oh_4 = bits(to_q_oh_enc, 4, 4) node to_q_oh_5 = bits(to_q_oh_enc, 5, 5) node to_q_oh_6 = bits(to_q_oh_enc, 6, 6) node to_q_oh_7 = bits(to_q_oh_enc, 7, 7) node to_q_oh_8 = bits(to_q_oh_enc, 8, 8) node to_q_oh_9 = bits(to_q_oh_enc, 9, 9) node to_q_lo_lo = cat(to_q_oh_1, to_q_oh_0) node to_q_lo_hi_hi = cat(to_q_oh_4, to_q_oh_3) node to_q_lo_hi = cat(to_q_lo_hi_hi, to_q_oh_2) node to_q_lo = cat(to_q_lo_hi, to_q_lo_lo) node to_q_hi_lo = cat(to_q_oh_6, to_q_oh_5) node to_q_hi_hi_hi = cat(to_q_oh_9, to_q_oh_8) node to_q_hi_hi = cat(to_q_hi_hi_hi, to_q_oh_7) node to_q_hi = cat(to_q_hi_hi, to_q_hi_lo) node _to_q_T = cat(to_q_hi, to_q_lo) node to_q_hi_1 = bits(_to_q_T, 9, 8) node to_q_lo_1 = bits(_to_q_T, 7, 0) node _to_q_T_1 = orr(to_q_hi_1) node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1) node to_q_hi_2 = bits(_to_q_T_2, 7, 4) node to_q_lo_2 = bits(_to_q_T_2, 3, 0) node _to_q_T_3 = orr(to_q_hi_2) node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2) node to_q_hi_3 = bits(_to_q_T_4, 3, 2) node to_q_lo_3 = bits(_to_q_T_4, 1, 0) node _to_q_T_5 = orr(to_q_hi_3) node _to_q_T_6 = or(to_q_hi_3, to_q_lo_3) node _to_q_T_7 = bits(_to_q_T_6, 1, 1) node _to_q_T_8 = cat(_to_q_T_5, _to_q_T_7) node _to_q_T_9 = cat(_to_q_T_3, _to_q_T_8) node to_q = cat(_to_q_T_1, _to_q_T_9) node _T_13 = or(can_to_q_0, can_to_q_1) node _T_14 = or(_T_13, can_to_q_2) node _T_15 = or(_T_14, can_to_q_3) node _T_16 = or(_T_15, can_to_q_4) node _T_17 = or(_T_16, can_to_q_5) node _T_18 = or(_T_17, can_to_q_6) node _T_19 = or(_T_18, can_to_q_7) node _T_20 = or(_T_19, can_to_q_8) node _T_21 = or(_T_20, can_to_q_9) when _T_21 : node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0)) node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0)) node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0)) node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0)) node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0)) node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0)) node _head_T_6 = mux(to_q_oh_6, heads[6], UInt<1>(0h0)) node _head_T_7 = mux(to_q_oh_7, heads[7], UInt<1>(0h0)) node _head_T_8 = mux(to_q_oh_8, heads[8], UInt<1>(0h0)) node _head_T_9 = mux(to_q_oh_9, heads[9], UInt<1>(0h0)) node _head_T_10 = or(_head_T, _head_T_1) node _head_T_11 = or(_head_T_10, _head_T_2) node _head_T_12 = or(_head_T_11, _head_T_3) node _head_T_13 = or(_head_T_12, _head_T_4) node _head_T_14 = or(_head_T_13, _head_T_5) node _head_T_15 = or(_head_T_14, _head_T_6) node _head_T_16 = or(_head_T_15, _head_T_7) node _head_T_17 = or(_head_T_16, _head_T_8) node _head_T_18 = or(_head_T_17, _head_T_9) wire head : UInt<5> connect head, _head_T_18 node _heads_T = mux(to_q_oh_0, UInt<2>(0h3), UInt<1>(0h0)) node _heads_T_1 = mux(to_q_oh_1, UInt<3>(0h7), UInt<1>(0h0)) node _heads_T_2 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_3 = mux(to_q_oh_3, UInt<4>(0hb), UInt<1>(0h0)) node _heads_T_4 = mux(to_q_oh_4, UInt<4>(0hf), UInt<1>(0h0)) node _heads_T_5 = mux(to_q_oh_5, UInt<5>(0h13), UInt<1>(0h0)) node _heads_T_6 = mux(to_q_oh_6, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_7 = mux(to_q_oh_7, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_8 = mux(to_q_oh_8, UInt<5>(0h17), UInt<1>(0h0)) node _heads_T_9 = mux(to_q_oh_9, UInt<5>(0h1b), UInt<1>(0h0)) node _heads_T_10 = or(_heads_T, _heads_T_1) node _heads_T_11 = or(_heads_T_10, _heads_T_2) node _heads_T_12 = or(_heads_T_11, _heads_T_3) node _heads_T_13 = or(_heads_T_12, _heads_T_4) node _heads_T_14 = or(_heads_T_13, _heads_T_5) node _heads_T_15 = or(_heads_T_14, _heads_T_6) node _heads_T_16 = or(_heads_T_15, _heads_T_7) node _heads_T_17 = or(_heads_T_16, _heads_T_8) node _heads_T_18 = or(_heads_T_17, _heads_T_9) wire _heads_WIRE_1 : UInt<5> connect _heads_WIRE_1, _heads_T_18 node _heads_T_19 = eq(head, _heads_WIRE_1) node _heads_T_20 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_21 = mux(to_q_oh_1, UInt<3>(0h4), UInt<1>(0h0)) node _heads_T_22 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_23 = mux(to_q_oh_3, UInt<4>(0h8), UInt<1>(0h0)) node _heads_T_24 = mux(to_q_oh_4, UInt<4>(0hc), UInt<1>(0h0)) node _heads_T_25 = mux(to_q_oh_5, UInt<5>(0h10), UInt<1>(0h0)) node _heads_T_26 = mux(to_q_oh_6, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_27 = mux(to_q_oh_7, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_28 = mux(to_q_oh_8, UInt<5>(0h14), UInt<1>(0h0)) node _heads_T_29 = mux(to_q_oh_9, UInt<5>(0h18), UInt<1>(0h0)) node _heads_T_30 = or(_heads_T_20, _heads_T_21) node _heads_T_31 = or(_heads_T_30, _heads_T_22) node _heads_T_32 = or(_heads_T_31, _heads_T_23) node _heads_T_33 = or(_heads_T_32, _heads_T_24) node _heads_T_34 = or(_heads_T_33, _heads_T_25) node _heads_T_35 = or(_heads_T_34, _heads_T_26) node _heads_T_36 = or(_heads_T_35, _heads_T_27) node _heads_T_37 = or(_heads_T_36, _heads_T_28) node _heads_T_38 = or(_heads_T_37, _heads_T_29) wire _heads_WIRE_2 : UInt<5> connect _heads_WIRE_2, _heads_T_38 node _heads_T_39 = add(head, UInt<1>(0h1)) node _heads_T_40 = tail(_heads_T_39, 1) node _heads_T_41 = mux(_heads_T_19, _heads_WIRE_2, _heads_T_40) connect heads[to_q], _heads_T_41 when to_q_oh_0 : connect qs_0.io.enq.valid, UInt<1>(0h1) read mport qs_0_io_enq_bits_MPORT = mem[head], clock connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head when to_q_oh_1 : connect qs_1.io.enq.valid, UInt<1>(0h1) read mport qs_1_io_enq_bits_MPORT = mem[head], clock connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head when to_q_oh_2 : connect qs_2.io.enq.valid, UInt<1>(0h1) read mport qs_2_io_enq_bits_MPORT = mem[head], clock connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head when to_q_oh_3 : connect qs_3.io.enq.valid, UInt<1>(0h1) read mport qs_3_io_enq_bits_MPORT = mem[head], clock connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head when to_q_oh_4 : connect qs_4.io.enq.valid, UInt<1>(0h1) read mport qs_4_io_enq_bits_MPORT = mem[head], clock connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head when to_q_oh_5 : connect qs_5.io.enq.valid, UInt<1>(0h1) read mport qs_5_io_enq_bits_MPORT = mem[head], clock connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head when to_q_oh_6 : connect qs_6.io.enq.valid, UInt<1>(0h1) read mport qs_6_io_enq_bits_MPORT = mem[head], clock connect qs_6.io.enq.bits.payload, qs_6_io_enq_bits_MPORT.payload connect qs_6.io.enq.bits.tail, qs_6_io_enq_bits_MPORT.tail connect qs_6.io.enq.bits.head, qs_6_io_enq_bits_MPORT.head when to_q_oh_7 : connect qs_7.io.enq.valid, UInt<1>(0h1) read mport qs_7_io_enq_bits_MPORT = mem[head], clock connect qs_7.io.enq.bits.payload, qs_7_io_enq_bits_MPORT.payload connect qs_7.io.enq.bits.tail, qs_7_io_enq_bits_MPORT.tail connect qs_7.io.enq.bits.head, qs_7_io_enq_bits_MPORT.head when to_q_oh_8 : connect qs_8.io.enq.valid, UInt<1>(0h1) read mport qs_8_io_enq_bits_MPORT = mem[head], clock connect qs_8.io.enq.bits.payload, qs_8_io_enq_bits_MPORT.payload connect qs_8.io.enq.bits.tail, qs_8_io_enq_bits_MPORT.tail connect qs_8.io.enq.bits.head, qs_8_io_enq_bits_MPORT.head when to_q_oh_9 : connect qs_9.io.enq.valid, UInt<1>(0h1) read mport qs_9_io_enq_bits_MPORT = mem[head], clock connect qs_9.io.enq.bits.payload, qs_9_io_enq_bits_MPORT.payload connect qs_9.io.enq.bits.tail, qs_9_io_enq_bits_MPORT.tail connect qs_9.io.enq.bits.head, qs_9_io_enq_bits_MPORT.head connect io.deq[0].bits, qs_0.io.deq.bits connect io.deq[0].valid, qs_0.io.deq.valid connect qs_0.io.deq.ready, io.deq[0].ready connect io.deq[1].bits, qs_1.io.deq.bits connect io.deq[1].valid, qs_1.io.deq.valid connect qs_1.io.deq.ready, io.deq[1].ready connect io.deq[2].bits, qs_2.io.deq.bits connect io.deq[2].valid, qs_2.io.deq.valid connect qs_2.io.deq.ready, io.deq[2].ready connect io.deq[3].bits, qs_3.io.deq.bits connect io.deq[3].valid, qs_3.io.deq.valid connect qs_3.io.deq.ready, io.deq[3].ready connect io.deq[4].bits, qs_4.io.deq.bits connect io.deq[4].valid, qs_4.io.deq.valid connect qs_4.io.deq.ready, io.deq[4].ready connect io.deq[5].bits, qs_5.io.deq.bits connect io.deq[5].valid, qs_5.io.deq.valid connect qs_5.io.deq.ready, io.deq[5].ready connect io.deq[6].bits, qs_6.io.deq.bits connect io.deq[6].valid, qs_6.io.deq.valid connect qs_6.io.deq.ready, io.deq[6].ready connect io.deq[7].bits, qs_7.io.deq.bits connect io.deq[7].valid, qs_7.io.deq.valid connect qs_7.io.deq.ready, io.deq[7].ready connect io.deq[8].bits, qs_8.io.deq.bits connect io.deq[8].valid, qs_8.io.deq.valid connect qs_8.io.deq.ready, io.deq[8].ready connect io.deq[9].bits, qs_9.io.deq.bits connect io.deq[9].valid, qs_9.io.deq.valid connect qs_9.io.deq.ready, io.deq[9].ready

module InputBuffer_5( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [3:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] input io_deq_0_ready, // @[InputUnit.scala:51:14] output io_deq_0_valid, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] input io_deq_1_ready, // @[InputUnit.scala:51:14] output io_deq_1_valid, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] input io_deq_4_ready, // @[InputUnit.scala:51:14] output io_deq_4_valid, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] input io_deq_5_ready, // @[InputUnit.scala:51:14] output io_deq_5_valid, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] input io_deq_8_ready, // @[InputUnit.scala:51:14] output io_deq_8_valid, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] input io_deq_9_ready, // @[InputUnit.scala:51:14] output io_deq_9_valid, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] reg [4:0] heads_0; // @[InputUnit.scala:86:24] reg [4:0] heads_1; // @[InputUnit.scala:86:24] reg [4:0] heads_2; // @[InputUnit.scala:86:24] reg [4:0] heads_3; // @[InputUnit.scala:86:24] reg [4:0] heads_4; // @[InputUnit.scala:86:24] reg [4:0] heads_5; // @[InputUnit.scala:86:24] reg [4:0] heads_6; // @[InputUnit.scala:86:24] reg [4:0] heads_7; // @[InputUnit.scala:86:24] reg [4:0] heads_8; // @[InputUnit.scala:86:24] reg [4:0] heads_9; // @[InputUnit.scala:86:24] reg [4:0] tails_0; // @[InputUnit.scala:87:24] reg [4:0] tails_1; // @[InputUnit.scala:87:24] reg [4:0] tails_2; // @[InputUnit.scala:87:24] reg [4:0] tails_3; // @[InputUnit.scala:87:24] reg [4:0] tails_4; // @[InputUnit.scala:87:24] reg [4:0] tails_5; // @[InputUnit.scala:87:24] reg [4:0] tails_6; // @[InputUnit.scala:87:24] reg [4:0] tails_7; // @[InputUnit.scala:87:24] reg [4:0] tails_8; // @[InputUnit.scala:87:24] reg [4:0] tails_9; // @[InputUnit.scala:87:24] wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 4'h0; // @[Mux.scala:32:36] wire _tails_T_31 = io_enq_0_bits_virt_channel_id == 4'h1; // @[Mux.scala:32:36] wire _tails_T_32 = io_enq_0_bits_virt_channel_id == 4'h2; // @[Mux.scala:32:36] wire _tails_T_33 = io_enq_0_bits_virt_channel_id == 4'h3; // @[Mux.scala:32:36] wire _tails_T_34 = io_enq_0_bits_virt_channel_id == 4'h4; // @[Mux.scala:32:36] wire _tails_T_35 = io_enq_0_bits_virt_channel_id == 4'h5; // @[Mux.scala:32:36] wire _tails_T_36 = io_enq_0_bits_virt_channel_id == 4'h6; // @[Mux.scala:32:36] wire _tails_T_37 = io_enq_0_bits_virt_channel_id == 4'h7; // @[Mux.scala:32:36] wire _tails_T_38 = io_enq_0_bits_virt_channel_id == 4'h8; // @[Mux.scala:32:36] wire _tails_T_39 = io_enq_0_bits_virt_channel_id == 4'h9; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_30 & _qs_0_io_enq_ready | _tails_T_31 & _qs_1_io_enq_ready | _tails_T_32 & _qs_2_io_enq_ready | _tails_T_33 & _qs_3_io_enq_ready | _tails_T_34 & _qs_4_io_enq_ready | _tails_T_35 & _qs_5_io_enq_ready | _tails_T_36 & _qs_6_io_enq_ready | _tails_T_37 & _qs_7_io_enq_ready | _tails_T_38 & _qs_8_io_enq_ready | _tails_T_39 & _qs_9_io_enq_ready) & (_tails_T_30 & heads_0 == tails_0 | _tails_T_31 & heads_1 == tails_1 | _tails_T_32 & heads_2 == tails_2 | _tails_T_33 & heads_3 == tails_3 | _tails_T_34 & heads_4 == tails_4 | _tails_T_35 & heads_5 == tails_5 | _tails_T_36 & heads_6 == tails_6 | _tails_T_37 & heads_7 == tails_7 | _tails_T_38 & heads_8 == tails_8 | _tails_T_39 & heads_9 == tails_9); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [15:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 4'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 4'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 4'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 4'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 4'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 4'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 4'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 4'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 4'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 4'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [9:0] to_q_oh_enc = can_to_q_0 ? 10'h1 : can_to_q_1 ? 10'h2 : can_to_q_2 ? 10'h4 : can_to_q_3 ? 10'h8 : can_to_q_4 ? 10'h10 : can_to_q_5 ? 10'h20 : can_to_q_6 ? 10'h40 : can_to_q_7 ? 10'h80 : can_to_q_8 ? 10'h100 : {can_to_q_9, 9'h0}; // @[Mux.scala:50:70] wire _GEN_11 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7 | can_to_q_8 | can_to_q_9; // @[package.scala:81:59] wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) | (to_q_oh_enc[1] ? heads_1 : 5'h0) | (to_q_oh_enc[2] ? heads_2 : 5'h0) | (to_q_oh_enc[3] ? heads_3 : 5'h0) | (to_q_oh_enc[4] ? heads_4 : 5'h0) | (to_q_oh_enc[5] ? heads_5 : 5'h0) | (to_q_oh_enc[6] ? heads_6 : 5'h0) | (to_q_oh_enc[7] ? heads_7 : 5'h0) | (to_q_oh_enc[8] ? heads_8 : 5'h0) | (to_q_oh_enc[9] ? heads_9 : 5'h0); // @[OneHot.scala:83:30] wire _GEN_12 = _GEN_11 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_13 = _GEN_11 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_14 = _GEN_11 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_15 = _GEN_11 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_16 = _GEN_11 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_17 = _GEN_11 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_18 = _GEN_11 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_19 = _GEN_11 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_20 = _GEN_11 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_21 = _GEN_11 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire [4:0] _tails_T_61 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_30}}} | {3{_tails_T_31}}} | (_tails_T_33 ? 4'hB : 4'h0) | {4{_tails_T_34}}} | (_tails_T_35 ? 5'h13 : 5'h0) | (_tails_T_38 ? 5'h17 : 5'h0) | (_tails_T_39 ? 5'h1B : 5'h0)) ? {_tails_T_35, {_tails_T_33, _tails_T_31, 2'h0} | (_tails_T_34 ? 4'hC : 4'h0)} | (_tails_T_38 ? 5'h14 : 5'h0) | (_tails_T_39 ? 5'h18 : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36] wire [6:0] _to_q_T_2 = {6'h0, to_q_oh_enc[9]} | to_q_oh_enc[7:1]; // @[OneHot.scala:31:18, :32:28] wire [2:0] _to_q_T_4 = _to_q_T_2[6:4] | _to_q_T_2[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_6 = _to_q_T_4[2] | _to_q_T_4[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] to_q = {|(to_q_oh_enc[9:8]), |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [4:0] _heads_T_41 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[0]}}} | {3{to_q_oh_enc[1]}}} | (to_q_oh_enc[3] ? 4'hB : 4'h0) | {4{to_q_oh_enc[4]}}} | (to_q_oh_enc[5] ? 5'h13 : 5'h0) | (to_q_oh_enc[8] ? 5'h17 : 5'h0) | (to_q_oh_enc[9] ? 5'h1B : 5'h0)) ? {to_q_oh_enc[5], {to_q_oh_enc[3], to_q_oh_enc[1], 2'h0} | (to_q_oh_enc[4] ? 4'hC : 4'h0)} | (to_q_oh_enc[8] ? 5'h14 : 5'h0) | (to_q_oh_enc[9] ? 5'h18 : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 5'h0; // @[InputUnit.scala:86:24] heads_1 <= 5'h4; // @[InputUnit.scala:86:24] heads_2 <= 5'h0; // @[InputUnit.scala:86:24] heads_3 <= 5'h8; // @[InputUnit.scala:86:24] heads_4 <= 5'hC; // @[InputUnit.scala:86:24] heads_5 <= 5'h10; // @[InputUnit.scala:86:24] heads_6 <= 5'h0; // @[InputUnit.scala:86:24] heads_7 <= 5'h0; // @[InputUnit.scala:86:24] heads_8 <= 5'h14; // @[InputUnit.scala:86:24] heads_9 <= 5'h18; // @[InputUnit.scala:86:24] tails_0 <= 5'h0; // @[InputUnit.scala:87:24] tails_1 <= 5'h4; // @[InputUnit.scala:87:24] tails_2 <= 5'h0; // @[InputUnit.scala:87:24] tails_3 <= 5'h8; // @[InputUnit.scala:87:24] tails_4 <= 5'hC; // @[InputUnit.scala:87:24] tails_5 <= 5'h10; // @[InputUnit.scala:87:24] tails_6 <= 5'h0; // @[InputUnit.scala:87:24] tails_7 <= 5'h0; // @[InputUnit.scala:87:24] tails_8 <= 5'h14; // @[InputUnit.scala:87:24] tails_9 <= 5'h18; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_11 & {to_q_oh_enc[9:8], |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6} == 5'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 12, 0) node _source_ok_T = shr(io.in.a.bits.source, 13) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<13>(0h100f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits = bits(_uncommonBits_T, 12, 0) node _T_4 = shr(io.in.a.bits.source, 13) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<13>(0h100f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 12, 0) node _T_24 = shr(io.in.a.bits.source, 13) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<13>(0h100f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 12, 0) node _T_86 = shr(io.in.a.bits.source, 13) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<13>(0h100f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 12, 0) node _T_152 = shr(io.in.a.bits.source, 13) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<13>(0h100f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 12, 0) node _T_199 = shr(io.in.a.bits.source, 13) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<13>(0h100f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 12, 0) node _T_240 = shr(io.in.a.bits.source, 13) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<13>(0h100f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 12, 0) node _T_283 = shr(io.in.a.bits.source, 13) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<13>(0h100f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 12, 0) node _T_321 = shr(io.in.a.bits.source, 13) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<13>(0h100f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 12, 0) node _T_359 = shr(io.in.a.bits.source, 13) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<13>(0h100f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<13>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 12, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 13) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<13>(0h100f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<13>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<13>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4112>, clock, reset, UInt<4112>(0h0) regreset inflight_opcodes : UInt<16448>, clock, reset, UInt<16448>(0h0) regreset inflight_sizes : UInt<16448>, clock, reset, UInt<16448>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4112> connect a_set, UInt<4112>(0h0) wire a_set_wo_ready : UInt<4112> connect a_set_wo_ready, UInt<4112>(0h0) wire a_opcodes_set : UInt<16448> connect a_opcodes_set, UInt<16448>(0h0) wire a_sizes_set : UInt<16448> connect a_sizes_set, UInt<16448>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4112> connect d_clr, UInt<4112>(0h0) wire d_clr_wo_ready : UInt<4112> connect d_clr_wo_ready, UInt<4112>(0h0) wire d_opcodes_clr : UInt<16448> connect d_opcodes_clr, UInt<16448>(0h0) wire d_sizes_clr : UInt<16448> connect d_sizes_clr, UInt<16448>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_128 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4112>, clock, reset, UInt<4112>(0h0) regreset inflight_opcodes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0) regreset inflight_sizes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<13>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<13>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4112> connect c_set, UInt<4112>(0h0) wire c_set_wo_ready : UInt<4112> connect c_set_wo_ready, UInt<4112>(0h0) wire c_opcodes_set : UInt<16448> connect c_opcodes_set, UInt<16448>(0h0) wire c_sizes_set : UInt<16448> connect c_sizes_set, UInt<16448>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<13>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<13>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<13>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<13>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4112> connect d_clr_1, UInt<4112>(0h0) wire d_clr_wo_ready_1 : UInt<4112> connect d_clr_wo_ready_1, UInt<4112>(0h0) wire d_opcodes_clr_1 : UInt<16448> connect d_opcodes_clr_1, UInt<16448>(0h0) wire d_sizes_clr_1 : UInt<16448> connect d_sizes_clr_1, UInt<16448>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<13>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<13>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<13>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<13>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_129 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<13>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_131 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32

module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52] wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79] wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77] wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35] wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35] wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34] wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34] wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34] wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [12:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [12:0] source_1; // @[Monitor.scala:541:22] reg [4111:0] inflight; // @[Monitor.scala:614:27] reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [4111:0] a_set; // @[Monitor.scala:626:34] wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [8191:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4111:0] d_clr; // @[Monitor.scala:664:34] wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4111:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [16447:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [16447:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4111:0] inflight_1; // @[Monitor.scala:726:35] wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [4111:0] d_clr_1; // @[Monitor.scala:774:34] wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113] wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_238 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_255 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_238( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_255 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_83 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_83( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_30 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_30( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_413 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_157 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_413( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_157 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain : output auto : { flip plic_int_in : UInt<1>[2], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_1 : { sync : UInt<1>[1]}, int_in_clock_xing_out_0 : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst plic of TLPLIC connect plic.clock, childClock connect plic.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_3 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x1_4 connect intsource_1.clock, childClock connect intsource_1.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[1]} invalidate intInClockXingOut.sync[0] wire intInClockXingIn : { sync : UInt<1>[1]} invalidate intInClockXingIn.sync[0] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 connect intsource.auto.in[0], plic.auto.int_out_0[0] connect intsource_1.auto.in[0], plic.auto.int_out_1[0] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect plic.auto.in, auto.plic_in connect plic.auto.int_in[0], auto.plic_int_in[0] connect plic.auto.int_in[1], auto.plic_int_in[1] connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_105 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_106 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module PLICClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25] input auto_plic_int_in_1, // @[LazyModuleImp.scala:107:25] output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46] TLPLIC plic ( // @[Plic.scala:367:46] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_int_in_0 (auto_plic_int_in_0), .auto_int_in_1 (auto_plic_int_in_1), .auto_int_out_1_0 (_plic_auto_int_out_1_0), .auto_int_out_0_0 (_plic_auto_int_out_0_0), .auto_in_a_ready (auto_plic_in_a_ready), .auto_in_a_valid (auto_plic_in_a_valid), .auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode), .auto_in_a_bits_param (auto_plic_in_a_bits_param), .auto_in_a_bits_size (auto_plic_in_a_bits_size), .auto_in_a_bits_source (auto_plic_in_a_bits_source), .auto_in_a_bits_address (auto_plic_in_a_bits_address), .auto_in_a_bits_mask (auto_plic_in_a_bits_mask), .auto_in_a_bits_data (auto_plic_in_a_bits_data), .auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt), .auto_in_d_ready (auto_plic_in_d_ready), .auto_in_d_valid (auto_plic_in_d_valid), .auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode), .auto_in_d_bits_size (auto_plic_in_d_bits_size), .auto_in_d_bits_source (auto_plic_in_d_bits_source), .auto_in_d_bits_data (auto_plic_in_d_bits_data) ); // @[Plic.scala:367:46] IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46] .auto_out_sync_0 (auto_int_in_clock_xing_out_0_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46] .auto_out_sync_0 (auto_int_in_clock_xing_out_1_sync_0) ); // @[Crossing.scala:29:31] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_90 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_181 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_182 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_183 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_184 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_90( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_240 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_240( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_15 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_15( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_113 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_114 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_9 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_9 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_9 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_19 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulAddRecFN_e8_s24_9( // @[MulAddRecFN.scala:300:7] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = 48'h0; // @[MulAddRecFN.scala:327:45] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [48:0] mulAddResult = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_9 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_9 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_19 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_97 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_97( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_35 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_70 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_71 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_35( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<6>, vc_free : UInt<6>}} wire _in_flight_WIRE : UInt<1>[6] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) regreset in_flight : UInt<1>[6], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_41 = and(_T_39, _T_40) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_47 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_54 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_61 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_68 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_89 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_96 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_153 = and(_T_151, _T_152) node _T_154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_159 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_160 = and(_T_158, _T_159) node _T_161 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_166 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_167 = and(_T_165, _T_166) node _T_168 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_173 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_174 = and(_T_172, _T_173) node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_180 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_187 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_188 = and(_T_186, _T_187) node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_194 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_201 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_206 = and(_T_204, _T_205) node _T_207 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_208 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_250 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_255 = and(_T_253, _T_254) node _T_256 = or(_T_17, _T_24) node _T_257 = or(_T_256, _T_31) node _T_258 = or(_T_257, _T_38) node _T_259 = or(_T_258, _T_45) node _T_260 = or(_T_259, _T_52) node _T_261 = or(_T_260, _T_59) node _T_262 = or(_T_261, _T_66) node _T_263 = or(_T_262, _T_73) node _T_264 = or(_T_263, _T_80) node _T_265 = or(_T_264, _T_87) node _T_266 = or(_T_265, _T_94) node _T_267 = or(_T_266, _T_101) node _T_268 = or(_T_267, _T_108) node _T_269 = or(_T_268, _T_115) node _T_270 = or(_T_269, _T_122) node _T_271 = or(_T_270, _T_129) node _T_272 = or(_T_271, _T_136) node _T_273 = or(_T_272, _T_143) node _T_274 = or(_T_273, _T_150) node _T_275 = or(_T_274, _T_157) node _T_276 = or(_T_275, _T_164) node _T_277 = or(_T_276, _T_171) node _T_278 = or(_T_277, _T_178) node _T_279 = or(_T_278, _T_185) node _T_280 = or(_T_279, _T_192) node _T_281 = or(_T_280, _T_199) node _T_282 = or(_T_281, _T_206) node _T_283 = or(_T_282, _T_213) node _T_284 = or(_T_283, _T_220) node _T_285 = or(_T_284, _T_227) node _T_286 = or(_T_285, _T_234) node _T_287 = or(_T_286, _T_241) node _T_288 = or(_T_287, _T_248) node _T_289 = or(_T_288, _T_255) node _T_290 = or(_T_10, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_290, UInt<1>(0h1), "") : assert_2 node _T_294 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_295 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_296 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_303 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_310 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_313 = and(_T_311, _T_312) node _T_314 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_315 = and(_T_313, _T_314) node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_320 = and(_T_318, _T_319) node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_325 = and(_T_323, _T_324) node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_329 = and(_T_327, _T_328) node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_339 = and(_T_337, _T_338) node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_346 = and(_T_344, _T_345) node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_350 = and(_T_348, _T_349) node _T_351 = or(_T_301, _T_308) node _T_352 = or(_T_351, _T_315) node _T_353 = or(_T_352, _T_322) node _T_354 = or(_T_353, _T_329) node _T_355 = or(_T_354, _T_336) node _T_356 = or(_T_355, _T_343) node _T_357 = or(_T_356, _T_350) node _T_358 = or(_T_294, _T_357) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_358, UInt<1>(0h1), "") : assert_3 node _T_362 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_363 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_364 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_369 = and(_T_367, _T_368) node _T_370 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_371 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_376 = and(_T_374, _T_375) node _T_377 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_378 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_385 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_392 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_399 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_400 = and(_T_398, _T_399) node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_404 = and(_T_402, _T_403) node _T_405 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_406 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_411 = and(_T_409, _T_410) node _T_412 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_413 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_418 = and(_T_416, _T_417) node _T_419 = or(_T_369, _T_376) node _T_420 = or(_T_419, _T_383) node _T_421 = or(_T_420, _T_390) node _T_422 = or(_T_421, _T_397) node _T_423 = or(_T_422, _T_404) node _T_424 = or(_T_423, _T_411) node _T_425 = or(_T_424, _T_418) node _T_426 = or(_T_362, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_426, UInt<1>(0h1), "") : assert_4 node _T_430 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_461 = and(_T_459, _T_460) node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_467 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_474 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_475 = and(_T_473, _T_474) node _T_476 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_479 = and(_T_477, _T_478) node _T_480 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_481 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_484 = and(_T_482, _T_483) node _T_485 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_488 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(_T_437, _T_444) node _T_495 = or(_T_494, _T_451) node _T_496 = or(_T_495, _T_458) node _T_497 = or(_T_496, _T_465) node _T_498 = or(_T_497, _T_472) node _T_499 = or(_T_498, _T_479) node _T_500 = or(_T_499, _T_486) node _T_501 = or(_T_500, _T_493) node _T_502 = or(_T_430, _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_502, UInt<1>(0h1), "") : assert_5 node _T_506 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_508 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_509 = and(_T_507, _T_508) node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_511 = and(_T_509, _T_510) node _T_512 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_515 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_516 = and(_T_514, _T_515) node _T_517 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_522 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_523 = and(_T_521, _T_522) node _T_524 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_525 = and(_T_523, _T_524) node _T_526 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_529 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_536 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_539 = and(_T_537, _T_538) node _T_540 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_543 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _T_547 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_548 = and(_T_546, _T_547) node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_550 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_553 = and(_T_551, _T_552) node _T_554 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_557 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_560 = and(_T_558, _T_559) node _T_561 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_564 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(_T_513, _T_520) node _T_571 = or(_T_570, _T_527) node _T_572 = or(_T_571, _T_534) node _T_573 = or(_T_572, _T_541) node _T_574 = or(_T_573, _T_548) node _T_575 = or(_T_574, _T_555) node _T_576 = or(_T_575, _T_562) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_506, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_578, UInt<1>(0h1), "") : assert_6

module NoCMonitor_12( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module FetchBuffer : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<40>, next_pc : UInt<40>, next_fetch : UInt<40>, edge_inst : UInt<1>[2], insts : UInt<32>[8], exp_insts : UInt<32>[8], pcs : UInt<40>[8], sfbs : UInt<1>[8], sfb_masks : UInt<16>[8], sfb_dests : UInt<5>[8], shadowable_mask : UInt<1>[8], shadowed_mask : UInt<1>[8], cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_type : UInt<3>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ftq_idx : UInt<5>, mask : UInt<8>, br_mask : UInt<8>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[2], xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, bp_debug_if_oh : UInt<1>[8], bp_xcpt_if_oh : UInt<1>[8], end_half : { valid : UInt<1>, bits : UInt<16>}, bpd_meta : UInt[2], fsrc : UInt<3>, tsrc : UInt<3>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3]}}, flip clear : UInt<1>} reg fb_uop_ram : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[24], clock wire deq_vec : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3][8] regreset head : UInt<8>, clock, reset, UInt<8>(0h1) regreset tail : UInt<24>, clock, reset, UInt<24>(0h1) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node _might_hit_head_T = bits(tail, 22, 0) node _might_hit_head_T_1 = bits(tail, 23, 23) node _might_hit_head_T_2 = cat(_might_hit_head_T, _might_hit_head_T_1) node _might_hit_head_T_3 = bits(_might_hit_head_T_2, 0, 0) node _might_hit_head_T_4 = bits(_might_hit_head_T_2, 1, 1) node _might_hit_head_T_5 = bits(_might_hit_head_T_2, 2, 2) node _might_hit_head_T_6 = bits(_might_hit_head_T_2, 3, 3) node _might_hit_head_T_7 = bits(_might_hit_head_T_2, 4, 4) node _might_hit_head_T_8 = bits(_might_hit_head_T_2, 5, 5) node _might_hit_head_T_9 = bits(_might_hit_head_T_2, 6, 6) node _might_hit_head_T_10 = bits(_might_hit_head_T_2, 7, 7) node _might_hit_head_T_11 = bits(_might_hit_head_T_2, 8, 8) node _might_hit_head_T_12 = bits(_might_hit_head_T_2, 9, 9) node _might_hit_head_T_13 = bits(_might_hit_head_T_2, 10, 10) node _might_hit_head_T_14 = bits(_might_hit_head_T_2, 11, 11) node _might_hit_head_T_15 = bits(_might_hit_head_T_2, 12, 12) node _might_hit_head_T_16 = bits(_might_hit_head_T_2, 13, 13) node _might_hit_head_T_17 = bits(_might_hit_head_T_2, 14, 14) node _might_hit_head_T_18 = bits(_might_hit_head_T_2, 15, 15) node _might_hit_head_T_19 = bits(_might_hit_head_T_2, 16, 16) node _might_hit_head_T_20 = bits(_might_hit_head_T_2, 17, 17) node _might_hit_head_T_21 = bits(_might_hit_head_T_2, 18, 18) node _might_hit_head_T_22 = bits(_might_hit_head_T_2, 19, 19) node _might_hit_head_T_23 = bits(_might_hit_head_T_2, 20, 20) node _might_hit_head_T_24 = bits(_might_hit_head_T_2, 21, 21) node _might_hit_head_T_25 = bits(_might_hit_head_T_2, 22, 22) node _might_hit_head_T_26 = bits(_might_hit_head_T_2, 23, 23) wire _might_hit_head_WIRE : UInt<1>[8] connect _might_hit_head_WIRE[0], _might_hit_head_T_3 connect _might_hit_head_WIRE[1], _might_hit_head_T_6 connect _might_hit_head_WIRE[2], _might_hit_head_T_9 connect _might_hit_head_WIRE[3], _might_hit_head_T_12 connect _might_hit_head_WIRE[4], _might_hit_head_T_15 connect _might_hit_head_WIRE[5], _might_hit_head_T_18 connect _might_hit_head_WIRE[6], _might_hit_head_T_21 connect _might_hit_head_WIRE[7], _might_hit_head_T_24 node might_hit_head_lo_lo = cat(_might_hit_head_WIRE[1], _might_hit_head_WIRE[0]) node might_hit_head_lo_hi = cat(_might_hit_head_WIRE[3], _might_hit_head_WIRE[2]) node might_hit_head_lo = cat(might_hit_head_lo_hi, might_hit_head_lo_lo) node might_hit_head_hi_lo = cat(_might_hit_head_WIRE[5], _might_hit_head_WIRE[4]) node might_hit_head_hi_hi = cat(_might_hit_head_WIRE[7], _might_hit_head_WIRE[6]) node might_hit_head_hi = cat(might_hit_head_hi_hi, might_hit_head_hi_lo) node _might_hit_head_T_27 = cat(might_hit_head_hi, might_hit_head_lo) node _might_hit_head_T_28 = bits(tail, 21, 0) node _might_hit_head_T_29 = bits(tail, 23, 22) node _might_hit_head_T_30 = cat(_might_hit_head_T_28, _might_hit_head_T_29) node _might_hit_head_T_31 = bits(_might_hit_head_T_30, 0, 0) node _might_hit_head_T_32 = bits(_might_hit_head_T_30, 1, 1) node _might_hit_head_T_33 = bits(_might_hit_head_T_30, 2, 2) node _might_hit_head_T_34 = bits(_might_hit_head_T_30, 3, 3) node _might_hit_head_T_35 = bits(_might_hit_head_T_30, 4, 4) node _might_hit_head_T_36 = bits(_might_hit_head_T_30, 5, 5) node _might_hit_head_T_37 = bits(_might_hit_head_T_30, 6, 6) node _might_hit_head_T_38 = bits(_might_hit_head_T_30, 7, 7) node _might_hit_head_T_39 = bits(_might_hit_head_T_30, 8, 8) node _might_hit_head_T_40 = bits(_might_hit_head_T_30, 9, 9) node _might_hit_head_T_41 = bits(_might_hit_head_T_30, 10, 10) node _might_hit_head_T_42 = bits(_might_hit_head_T_30, 11, 11) node _might_hit_head_T_43 = bits(_might_hit_head_T_30, 12, 12) node _might_hit_head_T_44 = bits(_might_hit_head_T_30, 13, 13) node _might_hit_head_T_45 = bits(_might_hit_head_T_30, 14, 14) node _might_hit_head_T_46 = bits(_might_hit_head_T_30, 15, 15) node _might_hit_head_T_47 = bits(_might_hit_head_T_30, 16, 16) node _might_hit_head_T_48 = bits(_might_hit_head_T_30, 17, 17) node _might_hit_head_T_49 = bits(_might_hit_head_T_30, 18, 18) node _might_hit_head_T_50 = bits(_might_hit_head_T_30, 19, 19) node _might_hit_head_T_51 = bits(_might_hit_head_T_30, 20, 20) node _might_hit_head_T_52 = bits(_might_hit_head_T_30, 21, 21) node _might_hit_head_T_53 = bits(_might_hit_head_T_30, 22, 22) node _might_hit_head_T_54 = bits(_might_hit_head_T_30, 23, 23) wire _might_hit_head_WIRE_1 : UInt<1>[8] connect _might_hit_head_WIRE_1[0], _might_hit_head_T_31 connect _might_hit_head_WIRE_1[1], _might_hit_head_T_34 connect _might_hit_head_WIRE_1[2], _might_hit_head_T_37 connect _might_hit_head_WIRE_1[3], _might_hit_head_T_40 connect _might_hit_head_WIRE_1[4], _might_hit_head_T_43 connect _might_hit_head_WIRE_1[5], _might_hit_head_T_46 connect _might_hit_head_WIRE_1[6], _might_hit_head_T_49 connect _might_hit_head_WIRE_1[7], _might_hit_head_T_52 node might_hit_head_lo_lo_1 = cat(_might_hit_head_WIRE_1[1], _might_hit_head_WIRE_1[0]) node might_hit_head_lo_hi_1 = cat(_might_hit_head_WIRE_1[3], _might_hit_head_WIRE_1[2]) node might_hit_head_lo_1 = cat(might_hit_head_lo_hi_1, might_hit_head_lo_lo_1) node might_hit_head_hi_lo_1 = cat(_might_hit_head_WIRE_1[5], _might_hit_head_WIRE_1[4]) node might_hit_head_hi_hi_1 = cat(_might_hit_head_WIRE_1[7], _might_hit_head_WIRE_1[6]) node might_hit_head_hi_1 = cat(might_hit_head_hi_hi_1, might_hit_head_hi_lo_1) node _might_hit_head_T_55 = cat(might_hit_head_hi_1, might_hit_head_lo_1) node _might_hit_head_T_56 = bits(tail, 20, 0) node _might_hit_head_T_57 = bits(tail, 23, 21) node _might_hit_head_T_58 = cat(_might_hit_head_T_56, _might_hit_head_T_57) node _might_hit_head_T_59 = bits(_might_hit_head_T_58, 0, 0) node _might_hit_head_T_60 = bits(_might_hit_head_T_58, 1, 1) node _might_hit_head_T_61 = bits(_might_hit_head_T_58, 2, 2) node _might_hit_head_T_62 = bits(_might_hit_head_T_58, 3, 3) node _might_hit_head_T_63 = bits(_might_hit_head_T_58, 4, 4) node _might_hit_head_T_64 = bits(_might_hit_head_T_58, 5, 5) node _might_hit_head_T_65 = bits(_might_hit_head_T_58, 6, 6) node _might_hit_head_T_66 = bits(_might_hit_head_T_58, 7, 7) node _might_hit_head_T_67 = bits(_might_hit_head_T_58, 8, 8) node _might_hit_head_T_68 = bits(_might_hit_head_T_58, 9, 9) node _might_hit_head_T_69 = bits(_might_hit_head_T_58, 10, 10) node _might_hit_head_T_70 = bits(_might_hit_head_T_58, 11, 11) node _might_hit_head_T_71 = bits(_might_hit_head_T_58, 12, 12) node _might_hit_head_T_72 = bits(_might_hit_head_T_58, 13, 13) node _might_hit_head_T_73 = bits(_might_hit_head_T_58, 14, 14) node _might_hit_head_T_74 = bits(_might_hit_head_T_58, 15, 15) node _might_hit_head_T_75 = bits(_might_hit_head_T_58, 16, 16) node _might_hit_head_T_76 = bits(_might_hit_head_T_58, 17, 17) node _might_hit_head_T_77 = bits(_might_hit_head_T_58, 18, 18) node _might_hit_head_T_78 = bits(_might_hit_head_T_58, 19, 19) node _might_hit_head_T_79 = bits(_might_hit_head_T_58, 20, 20) node _might_hit_head_T_80 = bits(_might_hit_head_T_58, 21, 21) node _might_hit_head_T_81 = bits(_might_hit_head_T_58, 22, 22) node _might_hit_head_T_82 = bits(_might_hit_head_T_58, 23, 23) wire _might_hit_head_WIRE_2 : UInt<1>[8] connect _might_hit_head_WIRE_2[0], _might_hit_head_T_59 connect _might_hit_head_WIRE_2[1], _might_hit_head_T_62 connect _might_hit_head_WIRE_2[2], _might_hit_head_T_65 connect _might_hit_head_WIRE_2[3], _might_hit_head_T_68 connect _might_hit_head_WIRE_2[4], _might_hit_head_T_71 connect _might_hit_head_WIRE_2[5], _might_hit_head_T_74 connect _might_hit_head_WIRE_2[6], _might_hit_head_T_77 connect _might_hit_head_WIRE_2[7], _might_hit_head_T_80 node might_hit_head_lo_lo_2 = cat(_might_hit_head_WIRE_2[1], _might_hit_head_WIRE_2[0]) node might_hit_head_lo_hi_2 = cat(_might_hit_head_WIRE_2[3], _might_hit_head_WIRE_2[2]) node might_hit_head_lo_2 = cat(might_hit_head_lo_hi_2, might_hit_head_lo_lo_2) node might_hit_head_hi_lo_2 = cat(_might_hit_head_WIRE_2[5], _might_hit_head_WIRE_2[4]) node might_hit_head_hi_hi_2 = cat(_might_hit_head_WIRE_2[7], _might_hit_head_WIRE_2[6]) node might_hit_head_hi_2 = cat(might_hit_head_hi_hi_2, might_hit_head_hi_lo_2) node _might_hit_head_T_83 = cat(might_hit_head_hi_2, might_hit_head_lo_2) node _might_hit_head_T_84 = bits(tail, 19, 0) node _might_hit_head_T_85 = bits(tail, 23, 20) node _might_hit_head_T_86 = cat(_might_hit_head_T_84, _might_hit_head_T_85) node _might_hit_head_T_87 = bits(_might_hit_head_T_86, 0, 0) node _might_hit_head_T_88 = bits(_might_hit_head_T_86, 1, 1) node _might_hit_head_T_89 = bits(_might_hit_head_T_86, 2, 2) node _might_hit_head_T_90 = bits(_might_hit_head_T_86, 3, 3) node _might_hit_head_T_91 = bits(_might_hit_head_T_86, 4, 4) node _might_hit_head_T_92 = bits(_might_hit_head_T_86, 5, 5) node _might_hit_head_T_93 = bits(_might_hit_head_T_86, 6, 6) node _might_hit_head_T_94 = bits(_might_hit_head_T_86, 7, 7) node _might_hit_head_T_95 = bits(_might_hit_head_T_86, 8, 8) node _might_hit_head_T_96 = bits(_might_hit_head_T_86, 9, 9) node _might_hit_head_T_97 = bits(_might_hit_head_T_86, 10, 10) node _might_hit_head_T_98 = bits(_might_hit_head_T_86, 11, 11) node _might_hit_head_T_99 = bits(_might_hit_head_T_86, 12, 12) node _might_hit_head_T_100 = bits(_might_hit_head_T_86, 13, 13) node _might_hit_head_T_101 = bits(_might_hit_head_T_86, 14, 14) node _might_hit_head_T_102 = bits(_might_hit_head_T_86, 15, 15) node _might_hit_head_T_103 = bits(_might_hit_head_T_86, 16, 16) node _might_hit_head_T_104 = bits(_might_hit_head_T_86, 17, 17) node _might_hit_head_T_105 = bits(_might_hit_head_T_86, 18, 18) node _might_hit_head_T_106 = bits(_might_hit_head_T_86, 19, 19) node _might_hit_head_T_107 = bits(_might_hit_head_T_86, 20, 20) node _might_hit_head_T_108 = bits(_might_hit_head_T_86, 21, 21) node _might_hit_head_T_109 = bits(_might_hit_head_T_86, 22, 22) node _might_hit_head_T_110 = bits(_might_hit_head_T_86, 23, 23) wire _might_hit_head_WIRE_3 : UInt<1>[8] connect _might_hit_head_WIRE_3[0], _might_hit_head_T_87 connect _might_hit_head_WIRE_3[1], _might_hit_head_T_90 connect _might_hit_head_WIRE_3[2], _might_hit_head_T_93 connect _might_hit_head_WIRE_3[3], _might_hit_head_T_96 connect _might_hit_head_WIRE_3[4], _might_hit_head_T_99 connect _might_hit_head_WIRE_3[5], _might_hit_head_T_102 connect _might_hit_head_WIRE_3[6], _might_hit_head_T_105 connect _might_hit_head_WIRE_3[7], _might_hit_head_T_108 node might_hit_head_lo_lo_3 = cat(_might_hit_head_WIRE_3[1], _might_hit_head_WIRE_3[0]) node might_hit_head_lo_hi_3 = cat(_might_hit_head_WIRE_3[3], _might_hit_head_WIRE_3[2]) node might_hit_head_lo_3 = cat(might_hit_head_lo_hi_3, might_hit_head_lo_lo_3) node might_hit_head_hi_lo_3 = cat(_might_hit_head_WIRE_3[5], _might_hit_head_WIRE_3[4]) node might_hit_head_hi_hi_3 = cat(_might_hit_head_WIRE_3[7], _might_hit_head_WIRE_3[6]) node might_hit_head_hi_3 = cat(might_hit_head_hi_hi_3, might_hit_head_hi_lo_3) node _might_hit_head_T_111 = cat(might_hit_head_hi_3, might_hit_head_lo_3) node _might_hit_head_T_112 = bits(tail, 18, 0) node _might_hit_head_T_113 = bits(tail, 23, 19) node _might_hit_head_T_114 = cat(_might_hit_head_T_112, _might_hit_head_T_113) node _might_hit_head_T_115 = bits(_might_hit_head_T_114, 0, 0) node _might_hit_head_T_116 = bits(_might_hit_head_T_114, 1, 1) node _might_hit_head_T_117 = bits(_might_hit_head_T_114, 2, 2) node _might_hit_head_T_118 = bits(_might_hit_head_T_114, 3, 3) node _might_hit_head_T_119 = bits(_might_hit_head_T_114, 4, 4) node _might_hit_head_T_120 = bits(_might_hit_head_T_114, 5, 5) node _might_hit_head_T_121 = bits(_might_hit_head_T_114, 6, 6) node _might_hit_head_T_122 = bits(_might_hit_head_T_114, 7, 7) node _might_hit_head_T_123 = bits(_might_hit_head_T_114, 8, 8) node _might_hit_head_T_124 = bits(_might_hit_head_T_114, 9, 9) node _might_hit_head_T_125 = bits(_might_hit_head_T_114, 10, 10) node _might_hit_head_T_126 = bits(_might_hit_head_T_114, 11, 11) node _might_hit_head_T_127 = bits(_might_hit_head_T_114, 12, 12) node _might_hit_head_T_128 = bits(_might_hit_head_T_114, 13, 13) node _might_hit_head_T_129 = bits(_might_hit_head_T_114, 14, 14) node _might_hit_head_T_130 = bits(_might_hit_head_T_114, 15, 15) node _might_hit_head_T_131 = bits(_might_hit_head_T_114, 16, 16) node _might_hit_head_T_132 = bits(_might_hit_head_T_114, 17, 17) node _might_hit_head_T_133 = bits(_might_hit_head_T_114, 18, 18) node _might_hit_head_T_134 = bits(_might_hit_head_T_114, 19, 19) node _might_hit_head_T_135 = bits(_might_hit_head_T_114, 20, 20) node _might_hit_head_T_136 = bits(_might_hit_head_T_114, 21, 21) node _might_hit_head_T_137 = bits(_might_hit_head_T_114, 22, 22) node _might_hit_head_T_138 = bits(_might_hit_head_T_114, 23, 23) wire _might_hit_head_WIRE_4 : UInt<1>[8] connect _might_hit_head_WIRE_4[0], _might_hit_head_T_115 connect _might_hit_head_WIRE_4[1], _might_hit_head_T_118 connect _might_hit_head_WIRE_4[2], _might_hit_head_T_121 connect _might_hit_head_WIRE_4[3], _might_hit_head_T_124 connect _might_hit_head_WIRE_4[4], _might_hit_head_T_127 connect _might_hit_head_WIRE_4[5], _might_hit_head_T_130 connect _might_hit_head_WIRE_4[6], _might_hit_head_T_133 connect _might_hit_head_WIRE_4[7], _might_hit_head_T_136 node might_hit_head_lo_lo_4 = cat(_might_hit_head_WIRE_4[1], _might_hit_head_WIRE_4[0]) node might_hit_head_lo_hi_4 = cat(_might_hit_head_WIRE_4[3], _might_hit_head_WIRE_4[2]) node might_hit_head_lo_4 = cat(might_hit_head_lo_hi_4, might_hit_head_lo_lo_4) node might_hit_head_hi_lo_4 = cat(_might_hit_head_WIRE_4[5], _might_hit_head_WIRE_4[4]) node might_hit_head_hi_hi_4 = cat(_might_hit_head_WIRE_4[7], _might_hit_head_WIRE_4[6]) node might_hit_head_hi_4 = cat(might_hit_head_hi_hi_4, might_hit_head_hi_lo_4) node _might_hit_head_T_139 = cat(might_hit_head_hi_4, might_hit_head_lo_4) node _might_hit_head_T_140 = bits(tail, 17, 0) node _might_hit_head_T_141 = bits(tail, 23, 18) node _might_hit_head_T_142 = cat(_might_hit_head_T_140, _might_hit_head_T_141) node _might_hit_head_T_143 = bits(_might_hit_head_T_142, 0, 0) node _might_hit_head_T_144 = bits(_might_hit_head_T_142, 1, 1) node _might_hit_head_T_145 = bits(_might_hit_head_T_142, 2, 2) node _might_hit_head_T_146 = bits(_might_hit_head_T_142, 3, 3) node _might_hit_head_T_147 = bits(_might_hit_head_T_142, 4, 4) node _might_hit_head_T_148 = bits(_might_hit_head_T_142, 5, 5) node _might_hit_head_T_149 = bits(_might_hit_head_T_142, 6, 6) node _might_hit_head_T_150 = bits(_might_hit_head_T_142, 7, 7) node _might_hit_head_T_151 = bits(_might_hit_head_T_142, 8, 8) node _might_hit_head_T_152 = bits(_might_hit_head_T_142, 9, 9) node _might_hit_head_T_153 = bits(_might_hit_head_T_142, 10, 10) node _might_hit_head_T_154 = bits(_might_hit_head_T_142, 11, 11) node _might_hit_head_T_155 = bits(_might_hit_head_T_142, 12, 12) node _might_hit_head_T_156 = bits(_might_hit_head_T_142, 13, 13) node _might_hit_head_T_157 = bits(_might_hit_head_T_142, 14, 14) node _might_hit_head_T_158 = bits(_might_hit_head_T_142, 15, 15) node _might_hit_head_T_159 = bits(_might_hit_head_T_142, 16, 16) node _might_hit_head_T_160 = bits(_might_hit_head_T_142, 17, 17) node _might_hit_head_T_161 = bits(_might_hit_head_T_142, 18, 18) node _might_hit_head_T_162 = bits(_might_hit_head_T_142, 19, 19) node _might_hit_head_T_163 = bits(_might_hit_head_T_142, 20, 20) node _might_hit_head_T_164 = bits(_might_hit_head_T_142, 21, 21) node _might_hit_head_T_165 = bits(_might_hit_head_T_142, 22, 22) node _might_hit_head_T_166 = bits(_might_hit_head_T_142, 23, 23) wire _might_hit_head_WIRE_5 : UInt<1>[8] connect _might_hit_head_WIRE_5[0], _might_hit_head_T_143 connect _might_hit_head_WIRE_5[1], _might_hit_head_T_146 connect _might_hit_head_WIRE_5[2], _might_hit_head_T_149 connect _might_hit_head_WIRE_5[3], _might_hit_head_T_152 connect _might_hit_head_WIRE_5[4], _might_hit_head_T_155 connect _might_hit_head_WIRE_5[5], _might_hit_head_T_158 connect _might_hit_head_WIRE_5[6], _might_hit_head_T_161 connect _might_hit_head_WIRE_5[7], _might_hit_head_T_164 node might_hit_head_lo_lo_5 = cat(_might_hit_head_WIRE_5[1], _might_hit_head_WIRE_5[0]) node might_hit_head_lo_hi_5 = cat(_might_hit_head_WIRE_5[3], _might_hit_head_WIRE_5[2]) node might_hit_head_lo_5 = cat(might_hit_head_lo_hi_5, might_hit_head_lo_lo_5) node might_hit_head_hi_lo_5 = cat(_might_hit_head_WIRE_5[5], _might_hit_head_WIRE_5[4]) node might_hit_head_hi_hi_5 = cat(_might_hit_head_WIRE_5[7], _might_hit_head_WIRE_5[6]) node might_hit_head_hi_5 = cat(might_hit_head_hi_hi_5, might_hit_head_hi_lo_5) node _might_hit_head_T_167 = cat(might_hit_head_hi_5, might_hit_head_lo_5) node _might_hit_head_T_168 = bits(tail, 16, 0) node _might_hit_head_T_169 = bits(tail, 23, 17) node _might_hit_head_T_170 = cat(_might_hit_head_T_168, _might_hit_head_T_169) node _might_hit_head_T_171 = bits(_might_hit_head_T_170, 0, 0) node _might_hit_head_T_172 = bits(_might_hit_head_T_170, 1, 1) node _might_hit_head_T_173 = bits(_might_hit_head_T_170, 2, 2) node _might_hit_head_T_174 = bits(_might_hit_head_T_170, 3, 3) node _might_hit_head_T_175 = bits(_might_hit_head_T_170, 4, 4) node _might_hit_head_T_176 = bits(_might_hit_head_T_170, 5, 5) node _might_hit_head_T_177 = bits(_might_hit_head_T_170, 6, 6) node _might_hit_head_T_178 = bits(_might_hit_head_T_170, 7, 7) node _might_hit_head_T_179 = bits(_might_hit_head_T_170, 8, 8) node _might_hit_head_T_180 = bits(_might_hit_head_T_170, 9, 9) node _might_hit_head_T_181 = bits(_might_hit_head_T_170, 10, 10) node _might_hit_head_T_182 = bits(_might_hit_head_T_170, 11, 11) node _might_hit_head_T_183 = bits(_might_hit_head_T_170, 12, 12) node _might_hit_head_T_184 = bits(_might_hit_head_T_170, 13, 13) node _might_hit_head_T_185 = bits(_might_hit_head_T_170, 14, 14) node _might_hit_head_T_186 = bits(_might_hit_head_T_170, 15, 15) node _might_hit_head_T_187 = bits(_might_hit_head_T_170, 16, 16) node _might_hit_head_T_188 = bits(_might_hit_head_T_170, 17, 17) node _might_hit_head_T_189 = bits(_might_hit_head_T_170, 18, 18) node _might_hit_head_T_190 = bits(_might_hit_head_T_170, 19, 19) node _might_hit_head_T_191 = bits(_might_hit_head_T_170, 20, 20) node _might_hit_head_T_192 = bits(_might_hit_head_T_170, 21, 21) node _might_hit_head_T_193 = bits(_might_hit_head_T_170, 22, 22) node _might_hit_head_T_194 = bits(_might_hit_head_T_170, 23, 23) wire _might_hit_head_WIRE_6 : UInt<1>[8] connect _might_hit_head_WIRE_6[0], _might_hit_head_T_171 connect _might_hit_head_WIRE_6[1], _might_hit_head_T_174 connect _might_hit_head_WIRE_6[2], _might_hit_head_T_177 connect _might_hit_head_WIRE_6[3], _might_hit_head_T_180 connect _might_hit_head_WIRE_6[4], _might_hit_head_T_183 connect _might_hit_head_WIRE_6[5], _might_hit_head_T_186 connect _might_hit_head_WIRE_6[6], _might_hit_head_T_189 connect _might_hit_head_WIRE_6[7], _might_hit_head_T_192 node might_hit_head_lo_lo_6 = cat(_might_hit_head_WIRE_6[1], _might_hit_head_WIRE_6[0]) node might_hit_head_lo_hi_6 = cat(_might_hit_head_WIRE_6[3], _might_hit_head_WIRE_6[2]) node might_hit_head_lo_6 = cat(might_hit_head_lo_hi_6, might_hit_head_lo_lo_6) node might_hit_head_hi_lo_6 = cat(_might_hit_head_WIRE_6[5], _might_hit_head_WIRE_6[4]) node might_hit_head_hi_hi_6 = cat(_might_hit_head_WIRE_6[7], _might_hit_head_WIRE_6[6]) node might_hit_head_hi_6 = cat(might_hit_head_hi_hi_6, might_hit_head_hi_lo_6) node _might_hit_head_T_195 = cat(might_hit_head_hi_6, might_hit_head_lo_6) node _might_hit_head_T_196 = and(head, _might_hit_head_T_27) node _might_hit_head_T_197 = and(head, _might_hit_head_T_55) node _might_hit_head_T_198 = and(head, _might_hit_head_T_83) node _might_hit_head_T_199 = and(head, _might_hit_head_T_111) node _might_hit_head_T_200 = and(head, _might_hit_head_T_139) node _might_hit_head_T_201 = and(head, _might_hit_head_T_167) node _might_hit_head_T_202 = and(head, _might_hit_head_T_195) node _might_hit_head_T_203 = or(_might_hit_head_T_196, _might_hit_head_T_197) node _might_hit_head_T_204 = or(_might_hit_head_T_203, _might_hit_head_T_198) node _might_hit_head_T_205 = or(_might_hit_head_T_204, _might_hit_head_T_199) node _might_hit_head_T_206 = or(_might_hit_head_T_205, _might_hit_head_T_200) node _might_hit_head_T_207 = or(_might_hit_head_T_206, _might_hit_head_T_201) node _might_hit_head_T_208 = or(_might_hit_head_T_207, _might_hit_head_T_202) node might_hit_head = orr(_might_hit_head_T_208) node _at_head_T = bits(tail, 0, 0) node _at_head_T_1 = bits(tail, 1, 1) node _at_head_T_2 = bits(tail, 2, 2) node _at_head_T_3 = bits(tail, 3, 3) node _at_head_T_4 = bits(tail, 4, 4) node _at_head_T_5 = bits(tail, 5, 5) node _at_head_T_6 = bits(tail, 6, 6) node _at_head_T_7 = bits(tail, 7, 7) node _at_head_T_8 = bits(tail, 8, 8) node _at_head_T_9 = bits(tail, 9, 9) node _at_head_T_10 = bits(tail, 10, 10) node _at_head_T_11 = bits(tail, 11, 11) node _at_head_T_12 = bits(tail, 12, 12) node _at_head_T_13 = bits(tail, 13, 13) node _at_head_T_14 = bits(tail, 14, 14) node _at_head_T_15 = bits(tail, 15, 15) node _at_head_T_16 = bits(tail, 16, 16) node _at_head_T_17 = bits(tail, 17, 17) node _at_head_T_18 = bits(tail, 18, 18) node _at_head_T_19 = bits(tail, 19, 19) node _at_head_T_20 = bits(tail, 20, 20) node _at_head_T_21 = bits(tail, 21, 21) node _at_head_T_22 = bits(tail, 22, 22) node _at_head_T_23 = bits(tail, 23, 23) wire _at_head_WIRE : UInt<1>[8] connect _at_head_WIRE[0], _at_head_T connect _at_head_WIRE[1], _at_head_T_3 connect _at_head_WIRE[2], _at_head_T_6 connect _at_head_WIRE[3], _at_head_T_9 connect _at_head_WIRE[4], _at_head_T_12 connect _at_head_WIRE[5], _at_head_T_15 connect _at_head_WIRE[6], _at_head_T_18 connect _at_head_WIRE[7], _at_head_T_21 node at_head_lo_lo = cat(_at_head_WIRE[1], _at_head_WIRE[0]) node at_head_lo_hi = cat(_at_head_WIRE[3], _at_head_WIRE[2]) node at_head_lo = cat(at_head_lo_hi, at_head_lo_lo) node at_head_hi_lo = cat(_at_head_WIRE[5], _at_head_WIRE[4]) node at_head_hi_hi = cat(_at_head_WIRE[7], _at_head_WIRE[6]) node at_head_hi = cat(at_head_hi_hi, at_head_hi_lo) node _at_head_T_24 = cat(at_head_hi, at_head_lo) node _at_head_T_25 = and(_at_head_T_24, head) node at_head = orr(_at_head_T_25) node _do_enq_T = and(at_head, maybe_full) node _do_enq_T_1 = or(_do_enq_T, might_hit_head) node do_enq = eq(_do_enq_T_1, UInt<1>(0h0)) connect io.enq.ready, do_enq wire in_mask : UInt<1>[8] wire in_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[8] node _pc_T = not(io.enq.bits.pc) node _pc_T_1 = or(_pc_T, UInt<3>(0h7)) node _pc_T_2 = not(_pc_T_1) node _pc_T_3 = add(_pc_T_2, UInt<1>(0h0)) node pc = tail(_pc_T_3, 1) invalidate in_uops[0].debug_tsrc invalidate in_uops[0].debug_fsrc invalidate in_uops[0].bp_xcpt_if invalidate in_uops[0].bp_debug_if invalidate in_uops[0].xcpt_ma_if invalidate in_uops[0].xcpt_ae_if invalidate in_uops[0].xcpt_pf_if invalidate in_uops[0].fp_typ invalidate in_uops[0].fp_rm invalidate in_uops[0].fp_val invalidate in_uops[0].fcn_op invalidate in_uops[0].fcn_dw invalidate in_uops[0].frs3_en invalidate in_uops[0].lrs2_rtype invalidate in_uops[0].lrs1_rtype invalidate in_uops[0].dst_rtype invalidate in_uops[0].lrs3 invalidate in_uops[0].lrs2 invalidate in_uops[0].lrs1 invalidate in_uops[0].ldst invalidate in_uops[0].ldst_is_rs1 invalidate in_uops[0].csr_cmd invalidate in_uops[0].flush_on_commit invalidate in_uops[0].is_unique invalidate in_uops[0].uses_stq invalidate in_uops[0].uses_ldq invalidate in_uops[0].mem_signed invalidate in_uops[0].mem_size invalidate in_uops[0].mem_cmd invalidate in_uops[0].exc_cause invalidate in_uops[0].exception invalidate in_uops[0].stale_pdst invalidate in_uops[0].ppred_busy invalidate in_uops[0].prs3_busy invalidate in_uops[0].prs2_busy invalidate in_uops[0].prs1_busy invalidate in_uops[0].ppred invalidate in_uops[0].prs3 invalidate in_uops[0].prs2 invalidate in_uops[0].prs1 invalidate in_uops[0].pdst invalidate in_uops[0].rxq_idx invalidate in_uops[0].stq_idx invalidate in_uops[0].ldq_idx invalidate in_uops[0].rob_idx invalidate in_uops[0].fp_ctrl.vec invalidate in_uops[0].fp_ctrl.wflags invalidate in_uops[0].fp_ctrl.sqrt invalidate in_uops[0].fp_ctrl.div invalidate in_uops[0].fp_ctrl.fma invalidate in_uops[0].fp_ctrl.fastpipe invalidate in_uops[0].fp_ctrl.toint invalidate in_uops[0].fp_ctrl.fromint invalidate in_uops[0].fp_ctrl.typeTagOut invalidate in_uops[0].fp_ctrl.typeTagIn invalidate in_uops[0].fp_ctrl.swap23 invalidate in_uops[0].fp_ctrl.swap12 invalidate in_uops[0].fp_ctrl.ren3 invalidate in_uops[0].fp_ctrl.ren2 invalidate in_uops[0].fp_ctrl.ren1 invalidate in_uops[0].fp_ctrl.wen invalidate in_uops[0].fp_ctrl.ldst invalidate in_uops[0].op2_sel invalidate in_uops[0].op1_sel invalidate in_uops[0].imm_packed invalidate in_uops[0].pimm invalidate in_uops[0].imm_sel invalidate in_uops[0].imm_rename invalidate in_uops[0].taken invalidate in_uops[0].pc_lob invalidate in_uops[0].edge_inst invalidate in_uops[0].ftq_idx invalidate in_uops[0].is_mov invalidate in_uops[0].is_rocc invalidate in_uops[0].is_sys_pc2epc invalidate in_uops[0].is_eret invalidate in_uops[0].is_amo invalidate in_uops[0].is_sfence invalidate in_uops[0].is_fencei invalidate in_uops[0].is_fence invalidate in_uops[0].is_sfb invalidate in_uops[0].br_type invalidate in_uops[0].br_tag invalidate in_uops[0].br_mask invalidate in_uops[0].dis_col_sel invalidate in_uops[0].iw_p3_bypass_hint invalidate in_uops[0].iw_p2_bypass_hint invalidate in_uops[0].iw_p1_bypass_hint invalidate in_uops[0].iw_p2_speculative_child invalidate in_uops[0].iw_p1_speculative_child invalidate in_uops[0].iw_issued_partial_dgen invalidate in_uops[0].iw_issued_partial_agen invalidate in_uops[0].iw_issued invalidate in_uops[0].fu_code[0] invalidate in_uops[0].fu_code[1] invalidate in_uops[0].fu_code[2] invalidate in_uops[0].fu_code[3] invalidate in_uops[0].fu_code[4] invalidate in_uops[0].fu_code[5] invalidate in_uops[0].fu_code[6] invalidate in_uops[0].fu_code[7] invalidate in_uops[0].fu_code[8] invalidate in_uops[0].fu_code[9] invalidate in_uops[0].iq_type[0] invalidate in_uops[0].iq_type[1] invalidate in_uops[0].iq_type[2] invalidate in_uops[0].iq_type[3] invalidate in_uops[0].debug_pc invalidate in_uops[0].is_rvc invalidate in_uops[0].debug_inst invalidate in_uops[0].inst node _in_mask_0_T = bits(io.enq.bits.mask, 0, 0) node _in_mask_0_T_1 = and(io.enq.valid, _in_mask_0_T) connect in_mask[0], _in_mask_0_T_1 connect in_uops[0].edge_inst, UInt<1>(0h0) connect in_uops[0].debug_pc, pc connect in_uops[0].pc_lob, pc node _in_uops_0_is_sfb_T = or(io.enq.bits.sfbs[0], io.enq.bits.shadowed_mask[0]) connect in_uops[0].is_sfb, _in_uops_0_is_sfb_T when io.enq.bits.edge_inst[0] : node _in_uops_0_debug_pc_T = not(io.enq.bits.pc) node _in_uops_0_debug_pc_T_1 = or(_in_uops_0_debug_pc_T, UInt<3>(0h7)) node _in_uops_0_debug_pc_T_2 = not(_in_uops_0_debug_pc_T_1) node _in_uops_0_debug_pc_T_3 = add(_in_uops_0_debug_pc_T_2, UInt<1>(0h0)) node _in_uops_0_debug_pc_T_4 = tail(_in_uops_0_debug_pc_T_3, 1) node _in_uops_0_debug_pc_T_5 = sub(_in_uops_0_debug_pc_T_4, UInt<2>(0h2)) node _in_uops_0_debug_pc_T_6 = tail(_in_uops_0_debug_pc_T_5, 1) connect in_uops[0].debug_pc, _in_uops_0_debug_pc_T_6 node _in_uops_0_pc_lob_T = not(io.enq.bits.pc) node _in_uops_0_pc_lob_T_1 = or(_in_uops_0_pc_lob_T, UInt<3>(0h7)) node _in_uops_0_pc_lob_T_2 = not(_in_uops_0_pc_lob_T_1) node _in_uops_0_pc_lob_T_3 = add(_in_uops_0_pc_lob_T_2, UInt<1>(0h0)) node _in_uops_0_pc_lob_T_4 = tail(_in_uops_0_pc_lob_T_3, 1) connect in_uops[0].pc_lob, _in_uops_0_pc_lob_T_4 connect in_uops[0].edge_inst, UInt<1>(0h1) connect in_uops[0].ftq_idx, io.enq.bits.ftq_idx connect in_uops[0].inst, io.enq.bits.exp_insts[0] connect in_uops[0].debug_inst, io.enq.bits.insts[0] node _in_uops_0_is_rvc_T = bits(io.enq.bits.insts[0], 1, 0) node _in_uops_0_is_rvc_T_1 = neq(_in_uops_0_is_rvc_T, UInt<2>(0h3)) connect in_uops[0].is_rvc, _in_uops_0_is_rvc_T_1 node _in_uops_0_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<1>(0h0)) node _in_uops_0_taken_T_1 = and(_in_uops_0_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[0].taken, _in_uops_0_taken_T_1 connect in_uops[0].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[0].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[0].bp_debug_if, io.enq.bits.bp_debug_if_oh[0] connect in_uops[0].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[0] connect in_uops[0].debug_fsrc, io.enq.bits.fsrc node _pc_T_4 = not(io.enq.bits.pc) node _pc_T_5 = or(_pc_T_4, UInt<3>(0h7)) node _pc_T_6 = not(_pc_T_5) node _pc_T_7 = add(_pc_T_6, UInt<2>(0h2)) node pc_1 = tail(_pc_T_7, 1) invalidate in_uops[1].debug_tsrc invalidate in_uops[1].debug_fsrc invalidate in_uops[1].bp_xcpt_if invalidate in_uops[1].bp_debug_if invalidate in_uops[1].xcpt_ma_if invalidate in_uops[1].xcpt_ae_if invalidate in_uops[1].xcpt_pf_if invalidate in_uops[1].fp_typ invalidate in_uops[1].fp_rm invalidate in_uops[1].fp_val invalidate in_uops[1].fcn_op invalidate in_uops[1].fcn_dw invalidate in_uops[1].frs3_en invalidate in_uops[1].lrs2_rtype invalidate in_uops[1].lrs1_rtype invalidate in_uops[1].dst_rtype invalidate in_uops[1].lrs3 invalidate in_uops[1].lrs2 invalidate in_uops[1].lrs1 invalidate in_uops[1].ldst invalidate in_uops[1].ldst_is_rs1 invalidate in_uops[1].csr_cmd invalidate in_uops[1].flush_on_commit invalidate in_uops[1].is_unique invalidate in_uops[1].uses_stq invalidate in_uops[1].uses_ldq invalidate in_uops[1].mem_signed invalidate in_uops[1].mem_size invalidate in_uops[1].mem_cmd invalidate in_uops[1].exc_cause invalidate in_uops[1].exception invalidate in_uops[1].stale_pdst invalidate in_uops[1].ppred_busy invalidate in_uops[1].prs3_busy invalidate in_uops[1].prs2_busy invalidate in_uops[1].prs1_busy invalidate in_uops[1].ppred invalidate in_uops[1].prs3 invalidate in_uops[1].prs2 invalidate in_uops[1].prs1 invalidate in_uops[1].pdst invalidate in_uops[1].rxq_idx invalidate in_uops[1].stq_idx invalidate in_uops[1].ldq_idx invalidate in_uops[1].rob_idx invalidate in_uops[1].fp_ctrl.vec invalidate in_uops[1].fp_ctrl.wflags invalidate in_uops[1].fp_ctrl.sqrt invalidate in_uops[1].fp_ctrl.div invalidate in_uops[1].fp_ctrl.fma invalidate in_uops[1].fp_ctrl.fastpipe invalidate in_uops[1].fp_ctrl.toint invalidate in_uops[1].fp_ctrl.fromint invalidate in_uops[1].fp_ctrl.typeTagOut invalidate in_uops[1].fp_ctrl.typeTagIn invalidate in_uops[1].fp_ctrl.swap23 invalidate in_uops[1].fp_ctrl.swap12 invalidate in_uops[1].fp_ctrl.ren3 invalidate in_uops[1].fp_ctrl.ren2 invalidate in_uops[1].fp_ctrl.ren1 invalidate in_uops[1].fp_ctrl.wen invalidate in_uops[1].fp_ctrl.ldst invalidate in_uops[1].op2_sel invalidate in_uops[1].op1_sel invalidate in_uops[1].imm_packed invalidate in_uops[1].pimm invalidate in_uops[1].imm_sel invalidate in_uops[1].imm_rename invalidate in_uops[1].taken invalidate in_uops[1].pc_lob invalidate in_uops[1].edge_inst invalidate in_uops[1].ftq_idx invalidate in_uops[1].is_mov invalidate in_uops[1].is_rocc invalidate in_uops[1].is_sys_pc2epc invalidate in_uops[1].is_eret invalidate in_uops[1].is_amo invalidate in_uops[1].is_sfence invalidate in_uops[1].is_fencei invalidate in_uops[1].is_fence invalidate in_uops[1].is_sfb invalidate in_uops[1].br_type invalidate in_uops[1].br_tag invalidate in_uops[1].br_mask invalidate in_uops[1].dis_col_sel invalidate in_uops[1].iw_p3_bypass_hint invalidate in_uops[1].iw_p2_bypass_hint invalidate in_uops[1].iw_p1_bypass_hint invalidate in_uops[1].iw_p2_speculative_child invalidate in_uops[1].iw_p1_speculative_child invalidate in_uops[1].iw_issued_partial_dgen invalidate in_uops[1].iw_issued_partial_agen invalidate in_uops[1].iw_issued invalidate in_uops[1].fu_code[0] invalidate in_uops[1].fu_code[1] invalidate in_uops[1].fu_code[2] invalidate in_uops[1].fu_code[3] invalidate in_uops[1].fu_code[4] invalidate in_uops[1].fu_code[5] invalidate in_uops[1].fu_code[6] invalidate in_uops[1].fu_code[7] invalidate in_uops[1].fu_code[8] invalidate in_uops[1].fu_code[9] invalidate in_uops[1].iq_type[0] invalidate in_uops[1].iq_type[1] invalidate in_uops[1].iq_type[2] invalidate in_uops[1].iq_type[3] invalidate in_uops[1].debug_pc invalidate in_uops[1].is_rvc invalidate in_uops[1].debug_inst invalidate in_uops[1].inst node _in_mask_1_T = bits(io.enq.bits.mask, 1, 1) node _in_mask_1_T_1 = and(io.enq.valid, _in_mask_1_T) connect in_mask[1], _in_mask_1_T_1 connect in_uops[1].edge_inst, UInt<1>(0h0) connect in_uops[1].debug_pc, pc_1 connect in_uops[1].pc_lob, pc_1 node _in_uops_1_is_sfb_T = or(io.enq.bits.sfbs[1], io.enq.bits.shadowed_mask[1]) connect in_uops[1].is_sfb, _in_uops_1_is_sfb_T connect in_uops[1].ftq_idx, io.enq.bits.ftq_idx connect in_uops[1].inst, io.enq.bits.exp_insts[1] connect in_uops[1].debug_inst, io.enq.bits.insts[1] node _in_uops_1_is_rvc_T = bits(io.enq.bits.insts[1], 1, 0) node _in_uops_1_is_rvc_T_1 = neq(_in_uops_1_is_rvc_T, UInt<2>(0h3)) connect in_uops[1].is_rvc, _in_uops_1_is_rvc_T_1 node _in_uops_1_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<1>(0h1)) node _in_uops_1_taken_T_1 = and(_in_uops_1_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[1].taken, _in_uops_1_taken_T_1 connect in_uops[1].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[1].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[1].bp_debug_if, io.enq.bits.bp_debug_if_oh[1] connect in_uops[1].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[1] connect in_uops[1].debug_fsrc, io.enq.bits.fsrc node _pc_T_8 = not(io.enq.bits.pc) node _pc_T_9 = or(_pc_T_8, UInt<3>(0h7)) node _pc_T_10 = not(_pc_T_9) node _pc_T_11 = add(_pc_T_10, UInt<3>(0h4)) node pc_2 = tail(_pc_T_11, 1) invalidate in_uops[2].debug_tsrc invalidate in_uops[2].debug_fsrc invalidate in_uops[2].bp_xcpt_if invalidate in_uops[2].bp_debug_if invalidate in_uops[2].xcpt_ma_if invalidate in_uops[2].xcpt_ae_if invalidate in_uops[2].xcpt_pf_if invalidate in_uops[2].fp_typ invalidate in_uops[2].fp_rm invalidate in_uops[2].fp_val invalidate in_uops[2].fcn_op invalidate in_uops[2].fcn_dw invalidate in_uops[2].frs3_en invalidate in_uops[2].lrs2_rtype invalidate in_uops[2].lrs1_rtype invalidate in_uops[2].dst_rtype invalidate in_uops[2].lrs3 invalidate in_uops[2].lrs2 invalidate in_uops[2].lrs1 invalidate in_uops[2].ldst invalidate in_uops[2].ldst_is_rs1 invalidate in_uops[2].csr_cmd invalidate in_uops[2].flush_on_commit invalidate in_uops[2].is_unique invalidate in_uops[2].uses_stq invalidate in_uops[2].uses_ldq invalidate in_uops[2].mem_signed invalidate in_uops[2].mem_size invalidate in_uops[2].mem_cmd invalidate in_uops[2].exc_cause invalidate in_uops[2].exception invalidate in_uops[2].stale_pdst invalidate in_uops[2].ppred_busy invalidate in_uops[2].prs3_busy invalidate in_uops[2].prs2_busy invalidate in_uops[2].prs1_busy invalidate in_uops[2].ppred invalidate in_uops[2].prs3 invalidate in_uops[2].prs2 invalidate in_uops[2].prs1 invalidate in_uops[2].pdst invalidate in_uops[2].rxq_idx invalidate in_uops[2].stq_idx invalidate in_uops[2].ldq_idx invalidate in_uops[2].rob_idx invalidate in_uops[2].fp_ctrl.vec invalidate in_uops[2].fp_ctrl.wflags invalidate in_uops[2].fp_ctrl.sqrt invalidate in_uops[2].fp_ctrl.div invalidate in_uops[2].fp_ctrl.fma invalidate in_uops[2].fp_ctrl.fastpipe invalidate in_uops[2].fp_ctrl.toint invalidate in_uops[2].fp_ctrl.fromint invalidate in_uops[2].fp_ctrl.typeTagOut invalidate in_uops[2].fp_ctrl.typeTagIn invalidate in_uops[2].fp_ctrl.swap23 invalidate in_uops[2].fp_ctrl.swap12 invalidate in_uops[2].fp_ctrl.ren3 invalidate in_uops[2].fp_ctrl.ren2 invalidate in_uops[2].fp_ctrl.ren1 invalidate in_uops[2].fp_ctrl.wen invalidate in_uops[2].fp_ctrl.ldst invalidate in_uops[2].op2_sel invalidate in_uops[2].op1_sel invalidate in_uops[2].imm_packed invalidate in_uops[2].pimm invalidate in_uops[2].imm_sel invalidate in_uops[2].imm_rename invalidate in_uops[2].taken invalidate in_uops[2].pc_lob invalidate in_uops[2].edge_inst invalidate in_uops[2].ftq_idx invalidate in_uops[2].is_mov invalidate in_uops[2].is_rocc invalidate in_uops[2].is_sys_pc2epc invalidate in_uops[2].is_eret invalidate in_uops[2].is_amo invalidate in_uops[2].is_sfence invalidate in_uops[2].is_fencei invalidate in_uops[2].is_fence invalidate in_uops[2].is_sfb invalidate in_uops[2].br_type invalidate in_uops[2].br_tag invalidate in_uops[2].br_mask invalidate in_uops[2].dis_col_sel invalidate in_uops[2].iw_p3_bypass_hint invalidate in_uops[2].iw_p2_bypass_hint invalidate in_uops[2].iw_p1_bypass_hint invalidate in_uops[2].iw_p2_speculative_child invalidate in_uops[2].iw_p1_speculative_child invalidate in_uops[2].iw_issued_partial_dgen invalidate in_uops[2].iw_issued_partial_agen invalidate in_uops[2].iw_issued invalidate in_uops[2].fu_code[0] invalidate in_uops[2].fu_code[1] invalidate in_uops[2].fu_code[2] invalidate in_uops[2].fu_code[3] invalidate in_uops[2].fu_code[4] invalidate in_uops[2].fu_code[5] invalidate in_uops[2].fu_code[6] invalidate in_uops[2].fu_code[7] invalidate in_uops[2].fu_code[8] invalidate in_uops[2].fu_code[9] invalidate in_uops[2].iq_type[0] invalidate in_uops[2].iq_type[1] invalidate in_uops[2].iq_type[2] invalidate in_uops[2].iq_type[3] invalidate in_uops[2].debug_pc invalidate in_uops[2].is_rvc invalidate in_uops[2].debug_inst invalidate in_uops[2].inst node _in_mask_2_T = bits(io.enq.bits.mask, 2, 2) node _in_mask_2_T_1 = and(io.enq.valid, _in_mask_2_T) connect in_mask[2], _in_mask_2_T_1 connect in_uops[2].edge_inst, UInt<1>(0h0) connect in_uops[2].debug_pc, pc_2 connect in_uops[2].pc_lob, pc_2 node _in_uops_2_is_sfb_T = or(io.enq.bits.sfbs[2], io.enq.bits.shadowed_mask[2]) connect in_uops[2].is_sfb, _in_uops_2_is_sfb_T connect in_uops[2].ftq_idx, io.enq.bits.ftq_idx connect in_uops[2].inst, io.enq.bits.exp_insts[2] connect in_uops[2].debug_inst, io.enq.bits.insts[2] node _in_uops_2_is_rvc_T = bits(io.enq.bits.insts[2], 1, 0) node _in_uops_2_is_rvc_T_1 = neq(_in_uops_2_is_rvc_T, UInt<2>(0h3)) connect in_uops[2].is_rvc, _in_uops_2_is_rvc_T_1 node _in_uops_2_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<2>(0h2)) node _in_uops_2_taken_T_1 = and(_in_uops_2_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[2].taken, _in_uops_2_taken_T_1 connect in_uops[2].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[2].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[2].bp_debug_if, io.enq.bits.bp_debug_if_oh[2] connect in_uops[2].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[2] connect in_uops[2].debug_fsrc, io.enq.bits.fsrc node _pc_T_12 = not(io.enq.bits.pc) node _pc_T_13 = or(_pc_T_12, UInt<3>(0h7)) node _pc_T_14 = not(_pc_T_13) node _pc_T_15 = add(_pc_T_14, UInt<3>(0h6)) node pc_3 = tail(_pc_T_15, 1) invalidate in_uops[3].debug_tsrc invalidate in_uops[3].debug_fsrc invalidate in_uops[3].bp_xcpt_if invalidate in_uops[3].bp_debug_if invalidate in_uops[3].xcpt_ma_if invalidate in_uops[3].xcpt_ae_if invalidate in_uops[3].xcpt_pf_if invalidate in_uops[3].fp_typ invalidate in_uops[3].fp_rm invalidate in_uops[3].fp_val invalidate in_uops[3].fcn_op invalidate in_uops[3].fcn_dw invalidate in_uops[3].frs3_en invalidate in_uops[3].lrs2_rtype invalidate in_uops[3].lrs1_rtype invalidate in_uops[3].dst_rtype invalidate in_uops[3].lrs3 invalidate in_uops[3].lrs2 invalidate in_uops[3].lrs1 invalidate in_uops[3].ldst invalidate in_uops[3].ldst_is_rs1 invalidate in_uops[3].csr_cmd invalidate in_uops[3].flush_on_commit invalidate in_uops[3].is_unique invalidate in_uops[3].uses_stq invalidate in_uops[3].uses_ldq invalidate in_uops[3].mem_signed invalidate in_uops[3].mem_size invalidate in_uops[3].mem_cmd invalidate in_uops[3].exc_cause invalidate in_uops[3].exception invalidate in_uops[3].stale_pdst invalidate in_uops[3].ppred_busy invalidate in_uops[3].prs3_busy invalidate in_uops[3].prs2_busy invalidate in_uops[3].prs1_busy invalidate in_uops[3].ppred invalidate in_uops[3].prs3 invalidate in_uops[3].prs2 invalidate in_uops[3].prs1 invalidate in_uops[3].pdst invalidate in_uops[3].rxq_idx invalidate in_uops[3].stq_idx invalidate in_uops[3].ldq_idx invalidate in_uops[3].rob_idx invalidate in_uops[3].fp_ctrl.vec invalidate in_uops[3].fp_ctrl.wflags invalidate in_uops[3].fp_ctrl.sqrt invalidate in_uops[3].fp_ctrl.div invalidate in_uops[3].fp_ctrl.fma invalidate in_uops[3].fp_ctrl.fastpipe invalidate in_uops[3].fp_ctrl.toint invalidate in_uops[3].fp_ctrl.fromint invalidate in_uops[3].fp_ctrl.typeTagOut invalidate in_uops[3].fp_ctrl.typeTagIn invalidate in_uops[3].fp_ctrl.swap23 invalidate in_uops[3].fp_ctrl.swap12 invalidate in_uops[3].fp_ctrl.ren3 invalidate in_uops[3].fp_ctrl.ren2 invalidate in_uops[3].fp_ctrl.ren1 invalidate in_uops[3].fp_ctrl.wen invalidate in_uops[3].fp_ctrl.ldst invalidate in_uops[3].op2_sel invalidate in_uops[3].op1_sel invalidate in_uops[3].imm_packed invalidate in_uops[3].pimm invalidate in_uops[3].imm_sel invalidate in_uops[3].imm_rename invalidate in_uops[3].taken invalidate in_uops[3].pc_lob invalidate in_uops[3].edge_inst invalidate in_uops[3].ftq_idx invalidate in_uops[3].is_mov invalidate in_uops[3].is_rocc invalidate in_uops[3].is_sys_pc2epc invalidate in_uops[3].is_eret invalidate in_uops[3].is_amo invalidate in_uops[3].is_sfence invalidate in_uops[3].is_fencei invalidate in_uops[3].is_fence invalidate in_uops[3].is_sfb invalidate in_uops[3].br_type invalidate in_uops[3].br_tag invalidate in_uops[3].br_mask invalidate in_uops[3].dis_col_sel invalidate in_uops[3].iw_p3_bypass_hint invalidate in_uops[3].iw_p2_bypass_hint invalidate in_uops[3].iw_p1_bypass_hint invalidate in_uops[3].iw_p2_speculative_child invalidate in_uops[3].iw_p1_speculative_child invalidate in_uops[3].iw_issued_partial_dgen invalidate in_uops[3].iw_issued_partial_agen invalidate in_uops[3].iw_issued invalidate in_uops[3].fu_code[0] invalidate in_uops[3].fu_code[1] invalidate in_uops[3].fu_code[2] invalidate in_uops[3].fu_code[3] invalidate in_uops[3].fu_code[4] invalidate in_uops[3].fu_code[5] invalidate in_uops[3].fu_code[6] invalidate in_uops[3].fu_code[7] invalidate in_uops[3].fu_code[8] invalidate in_uops[3].fu_code[9] invalidate in_uops[3].iq_type[0] invalidate in_uops[3].iq_type[1] invalidate in_uops[3].iq_type[2] invalidate in_uops[3].iq_type[3] invalidate in_uops[3].debug_pc invalidate in_uops[3].is_rvc invalidate in_uops[3].debug_inst invalidate in_uops[3].inst node _in_mask_3_T = bits(io.enq.bits.mask, 3, 3) node _in_mask_3_T_1 = and(io.enq.valid, _in_mask_3_T) connect in_mask[3], _in_mask_3_T_1 connect in_uops[3].edge_inst, UInt<1>(0h0) connect in_uops[3].debug_pc, pc_3 connect in_uops[3].pc_lob, pc_3 node _in_uops_3_is_sfb_T = or(io.enq.bits.sfbs[3], io.enq.bits.shadowed_mask[3]) connect in_uops[3].is_sfb, _in_uops_3_is_sfb_T connect in_uops[3].ftq_idx, io.enq.bits.ftq_idx connect in_uops[3].inst, io.enq.bits.exp_insts[3] connect in_uops[3].debug_inst, io.enq.bits.insts[3] node _in_uops_3_is_rvc_T = bits(io.enq.bits.insts[3], 1, 0) node _in_uops_3_is_rvc_T_1 = neq(_in_uops_3_is_rvc_T, UInt<2>(0h3)) connect in_uops[3].is_rvc, _in_uops_3_is_rvc_T_1 node _in_uops_3_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<2>(0h3)) node _in_uops_3_taken_T_1 = and(_in_uops_3_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[3].taken, _in_uops_3_taken_T_1 connect in_uops[3].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[3].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[3].bp_debug_if, io.enq.bits.bp_debug_if_oh[3] connect in_uops[3].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[3] connect in_uops[3].debug_fsrc, io.enq.bits.fsrc node _pc_T_16 = not(io.enq.bits.pc) node _pc_T_17 = or(_pc_T_16, UInt<3>(0h7)) node _pc_T_18 = not(_pc_T_17) node _pc_T_19 = add(_pc_T_18, UInt<4>(0h8)) node pc_4 = tail(_pc_T_19, 1) invalidate in_uops[4].debug_tsrc invalidate in_uops[4].debug_fsrc invalidate in_uops[4].bp_xcpt_if invalidate in_uops[4].bp_debug_if invalidate in_uops[4].xcpt_ma_if invalidate in_uops[4].xcpt_ae_if invalidate in_uops[4].xcpt_pf_if invalidate in_uops[4].fp_typ invalidate in_uops[4].fp_rm invalidate in_uops[4].fp_val invalidate in_uops[4].fcn_op invalidate in_uops[4].fcn_dw invalidate in_uops[4].frs3_en invalidate in_uops[4].lrs2_rtype invalidate in_uops[4].lrs1_rtype invalidate in_uops[4].dst_rtype invalidate in_uops[4].lrs3 invalidate in_uops[4].lrs2 invalidate in_uops[4].lrs1 invalidate in_uops[4].ldst invalidate in_uops[4].ldst_is_rs1 invalidate in_uops[4].csr_cmd invalidate in_uops[4].flush_on_commit invalidate in_uops[4].is_unique invalidate in_uops[4].uses_stq invalidate in_uops[4].uses_ldq invalidate in_uops[4].mem_signed invalidate in_uops[4].mem_size invalidate in_uops[4].mem_cmd invalidate in_uops[4].exc_cause invalidate in_uops[4].exception invalidate in_uops[4].stale_pdst invalidate in_uops[4].ppred_busy invalidate in_uops[4].prs3_busy invalidate in_uops[4].prs2_busy invalidate in_uops[4].prs1_busy invalidate in_uops[4].ppred invalidate in_uops[4].prs3 invalidate in_uops[4].prs2 invalidate in_uops[4].prs1 invalidate in_uops[4].pdst invalidate in_uops[4].rxq_idx invalidate in_uops[4].stq_idx invalidate in_uops[4].ldq_idx invalidate in_uops[4].rob_idx invalidate in_uops[4].fp_ctrl.vec invalidate in_uops[4].fp_ctrl.wflags invalidate in_uops[4].fp_ctrl.sqrt invalidate in_uops[4].fp_ctrl.div invalidate in_uops[4].fp_ctrl.fma invalidate in_uops[4].fp_ctrl.fastpipe invalidate in_uops[4].fp_ctrl.toint invalidate in_uops[4].fp_ctrl.fromint invalidate in_uops[4].fp_ctrl.typeTagOut invalidate in_uops[4].fp_ctrl.typeTagIn invalidate in_uops[4].fp_ctrl.swap23 invalidate in_uops[4].fp_ctrl.swap12 invalidate in_uops[4].fp_ctrl.ren3 invalidate in_uops[4].fp_ctrl.ren2 invalidate in_uops[4].fp_ctrl.ren1 invalidate in_uops[4].fp_ctrl.wen invalidate in_uops[4].fp_ctrl.ldst invalidate in_uops[4].op2_sel invalidate in_uops[4].op1_sel invalidate in_uops[4].imm_packed invalidate in_uops[4].pimm invalidate in_uops[4].imm_sel invalidate in_uops[4].imm_rename invalidate in_uops[4].taken invalidate in_uops[4].pc_lob invalidate in_uops[4].edge_inst invalidate in_uops[4].ftq_idx invalidate in_uops[4].is_mov invalidate in_uops[4].is_rocc invalidate in_uops[4].is_sys_pc2epc invalidate in_uops[4].is_eret invalidate in_uops[4].is_amo invalidate in_uops[4].is_sfence invalidate in_uops[4].is_fencei invalidate in_uops[4].is_fence invalidate in_uops[4].is_sfb invalidate in_uops[4].br_type invalidate in_uops[4].br_tag invalidate in_uops[4].br_mask invalidate in_uops[4].dis_col_sel invalidate in_uops[4].iw_p3_bypass_hint invalidate in_uops[4].iw_p2_bypass_hint invalidate in_uops[4].iw_p1_bypass_hint invalidate in_uops[4].iw_p2_speculative_child invalidate in_uops[4].iw_p1_speculative_child invalidate in_uops[4].iw_issued_partial_dgen invalidate in_uops[4].iw_issued_partial_agen invalidate in_uops[4].iw_issued invalidate in_uops[4].fu_code[0] invalidate in_uops[4].fu_code[1] invalidate in_uops[4].fu_code[2] invalidate in_uops[4].fu_code[3] invalidate in_uops[4].fu_code[4] invalidate in_uops[4].fu_code[5] invalidate in_uops[4].fu_code[6] invalidate in_uops[4].fu_code[7] invalidate in_uops[4].fu_code[8] invalidate in_uops[4].fu_code[9] invalidate in_uops[4].iq_type[0] invalidate in_uops[4].iq_type[1] invalidate in_uops[4].iq_type[2] invalidate in_uops[4].iq_type[3] invalidate in_uops[4].debug_pc invalidate in_uops[4].is_rvc invalidate in_uops[4].debug_inst invalidate in_uops[4].inst node _in_mask_4_T = bits(io.enq.bits.mask, 4, 4) node _in_mask_4_T_1 = and(io.enq.valid, _in_mask_4_T) connect in_mask[4], _in_mask_4_T_1 connect in_uops[4].edge_inst, UInt<1>(0h0) connect in_uops[4].debug_pc, pc_4 connect in_uops[4].pc_lob, pc_4 node _in_uops_4_is_sfb_T = or(io.enq.bits.sfbs[4], io.enq.bits.shadowed_mask[4]) connect in_uops[4].is_sfb, _in_uops_4_is_sfb_T when io.enq.bits.edge_inst[1] : node _in_uops_4_debug_pc_T = not(io.enq.bits.pc) node _in_uops_4_debug_pc_T_1 = or(_in_uops_4_debug_pc_T, UInt<3>(0h7)) node _in_uops_4_debug_pc_T_2 = not(_in_uops_4_debug_pc_T_1) node _in_uops_4_debug_pc_T_3 = add(_in_uops_4_debug_pc_T_2, UInt<4>(0h8)) node _in_uops_4_debug_pc_T_4 = tail(_in_uops_4_debug_pc_T_3, 1) node _in_uops_4_debug_pc_T_5 = sub(_in_uops_4_debug_pc_T_4, UInt<2>(0h2)) node _in_uops_4_debug_pc_T_6 = tail(_in_uops_4_debug_pc_T_5, 1) connect in_uops[4].debug_pc, _in_uops_4_debug_pc_T_6 node _in_uops_4_pc_lob_T = not(io.enq.bits.pc) node _in_uops_4_pc_lob_T_1 = or(_in_uops_4_pc_lob_T, UInt<3>(0h7)) node _in_uops_4_pc_lob_T_2 = not(_in_uops_4_pc_lob_T_1) node _in_uops_4_pc_lob_T_3 = add(_in_uops_4_pc_lob_T_2, UInt<4>(0h8)) node _in_uops_4_pc_lob_T_4 = tail(_in_uops_4_pc_lob_T_3, 1) connect in_uops[4].pc_lob, _in_uops_4_pc_lob_T_4 connect in_uops[4].edge_inst, UInt<1>(0h1) connect in_uops[4].ftq_idx, io.enq.bits.ftq_idx connect in_uops[4].inst, io.enq.bits.exp_insts[4] connect in_uops[4].debug_inst, io.enq.bits.insts[4] node _in_uops_4_is_rvc_T = bits(io.enq.bits.insts[4], 1, 0) node _in_uops_4_is_rvc_T_1 = neq(_in_uops_4_is_rvc_T, UInt<2>(0h3)) connect in_uops[4].is_rvc, _in_uops_4_is_rvc_T_1 node _in_uops_4_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h4)) node _in_uops_4_taken_T_1 = and(_in_uops_4_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[4].taken, _in_uops_4_taken_T_1 connect in_uops[4].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[4].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[4].bp_debug_if, io.enq.bits.bp_debug_if_oh[4] connect in_uops[4].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[4] connect in_uops[4].debug_fsrc, io.enq.bits.fsrc node _pc_T_20 = not(io.enq.bits.pc) node _pc_T_21 = or(_pc_T_20, UInt<3>(0h7)) node _pc_T_22 = not(_pc_T_21) node _pc_T_23 = add(_pc_T_22, UInt<4>(0ha)) node pc_5 = tail(_pc_T_23, 1) invalidate in_uops[5].debug_tsrc invalidate in_uops[5].debug_fsrc invalidate in_uops[5].bp_xcpt_if invalidate in_uops[5].bp_debug_if invalidate in_uops[5].xcpt_ma_if invalidate in_uops[5].xcpt_ae_if invalidate in_uops[5].xcpt_pf_if invalidate in_uops[5].fp_typ invalidate in_uops[5].fp_rm invalidate in_uops[5].fp_val invalidate in_uops[5].fcn_op invalidate in_uops[5].fcn_dw invalidate in_uops[5].frs3_en invalidate in_uops[5].lrs2_rtype invalidate in_uops[5].lrs1_rtype invalidate in_uops[5].dst_rtype invalidate in_uops[5].lrs3 invalidate in_uops[5].lrs2 invalidate in_uops[5].lrs1 invalidate in_uops[5].ldst invalidate in_uops[5].ldst_is_rs1 invalidate in_uops[5].csr_cmd invalidate in_uops[5].flush_on_commit invalidate in_uops[5].is_unique invalidate in_uops[5].uses_stq invalidate in_uops[5].uses_ldq invalidate in_uops[5].mem_signed invalidate in_uops[5].mem_size invalidate in_uops[5].mem_cmd invalidate in_uops[5].exc_cause invalidate in_uops[5].exception invalidate in_uops[5].stale_pdst invalidate in_uops[5].ppred_busy invalidate in_uops[5].prs3_busy invalidate in_uops[5].prs2_busy invalidate in_uops[5].prs1_busy invalidate in_uops[5].ppred invalidate in_uops[5].prs3 invalidate in_uops[5].prs2 invalidate in_uops[5].prs1 invalidate in_uops[5].pdst invalidate in_uops[5].rxq_idx invalidate in_uops[5].stq_idx invalidate in_uops[5].ldq_idx invalidate in_uops[5].rob_idx invalidate in_uops[5].fp_ctrl.vec invalidate in_uops[5].fp_ctrl.wflags invalidate in_uops[5].fp_ctrl.sqrt invalidate in_uops[5].fp_ctrl.div invalidate in_uops[5].fp_ctrl.fma invalidate in_uops[5].fp_ctrl.fastpipe invalidate in_uops[5].fp_ctrl.toint invalidate in_uops[5].fp_ctrl.fromint invalidate in_uops[5].fp_ctrl.typeTagOut invalidate in_uops[5].fp_ctrl.typeTagIn invalidate in_uops[5].fp_ctrl.swap23 invalidate in_uops[5].fp_ctrl.swap12 invalidate in_uops[5].fp_ctrl.ren3 invalidate in_uops[5].fp_ctrl.ren2 invalidate in_uops[5].fp_ctrl.ren1 invalidate in_uops[5].fp_ctrl.wen invalidate in_uops[5].fp_ctrl.ldst invalidate in_uops[5].op2_sel invalidate in_uops[5].op1_sel invalidate in_uops[5].imm_packed invalidate in_uops[5].pimm invalidate in_uops[5].imm_sel invalidate in_uops[5].imm_rename invalidate in_uops[5].taken invalidate in_uops[5].pc_lob invalidate in_uops[5].edge_inst invalidate in_uops[5].ftq_idx invalidate in_uops[5].is_mov invalidate in_uops[5].is_rocc invalidate in_uops[5].is_sys_pc2epc invalidate in_uops[5].is_eret invalidate in_uops[5].is_amo invalidate in_uops[5].is_sfence invalidate in_uops[5].is_fencei invalidate in_uops[5].is_fence invalidate in_uops[5].is_sfb invalidate in_uops[5].br_type invalidate in_uops[5].br_tag invalidate in_uops[5].br_mask invalidate in_uops[5].dis_col_sel invalidate in_uops[5].iw_p3_bypass_hint invalidate in_uops[5].iw_p2_bypass_hint invalidate in_uops[5].iw_p1_bypass_hint invalidate in_uops[5].iw_p2_speculative_child invalidate in_uops[5].iw_p1_speculative_child invalidate in_uops[5].iw_issued_partial_dgen invalidate in_uops[5].iw_issued_partial_agen invalidate in_uops[5].iw_issued invalidate in_uops[5].fu_code[0] invalidate in_uops[5].fu_code[1] invalidate in_uops[5].fu_code[2] invalidate in_uops[5].fu_code[3] invalidate in_uops[5].fu_code[4] invalidate in_uops[5].fu_code[5] invalidate in_uops[5].fu_code[6] invalidate in_uops[5].fu_code[7] invalidate in_uops[5].fu_code[8] invalidate in_uops[5].fu_code[9] invalidate in_uops[5].iq_type[0] invalidate in_uops[5].iq_type[1] invalidate in_uops[5].iq_type[2] invalidate in_uops[5].iq_type[3] invalidate in_uops[5].debug_pc invalidate in_uops[5].is_rvc invalidate in_uops[5].debug_inst invalidate in_uops[5].inst node _in_mask_5_T = bits(io.enq.bits.mask, 5, 5) node _in_mask_5_T_1 = and(io.enq.valid, _in_mask_5_T) connect in_mask[5], _in_mask_5_T_1 connect in_uops[5].edge_inst, UInt<1>(0h0) connect in_uops[5].debug_pc, pc_5 connect in_uops[5].pc_lob, pc_5 node _in_uops_5_is_sfb_T = or(io.enq.bits.sfbs[5], io.enq.bits.shadowed_mask[5]) connect in_uops[5].is_sfb, _in_uops_5_is_sfb_T connect in_uops[5].ftq_idx, io.enq.bits.ftq_idx connect in_uops[5].inst, io.enq.bits.exp_insts[5] connect in_uops[5].debug_inst, io.enq.bits.insts[5] node _in_uops_5_is_rvc_T = bits(io.enq.bits.insts[5], 1, 0) node _in_uops_5_is_rvc_T_1 = neq(_in_uops_5_is_rvc_T, UInt<2>(0h3)) connect in_uops[5].is_rvc, _in_uops_5_is_rvc_T_1 node _in_uops_5_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h5)) node _in_uops_5_taken_T_1 = and(_in_uops_5_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[5].taken, _in_uops_5_taken_T_1 connect in_uops[5].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[5].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[5].bp_debug_if, io.enq.bits.bp_debug_if_oh[5] connect in_uops[5].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[5] connect in_uops[5].debug_fsrc, io.enq.bits.fsrc node _pc_T_24 = not(io.enq.bits.pc) node _pc_T_25 = or(_pc_T_24, UInt<3>(0h7)) node _pc_T_26 = not(_pc_T_25) node _pc_T_27 = add(_pc_T_26, UInt<4>(0hc)) node pc_6 = tail(_pc_T_27, 1) invalidate in_uops[6].debug_tsrc invalidate in_uops[6].debug_fsrc invalidate in_uops[6].bp_xcpt_if invalidate in_uops[6].bp_debug_if invalidate in_uops[6].xcpt_ma_if invalidate in_uops[6].xcpt_ae_if invalidate in_uops[6].xcpt_pf_if invalidate in_uops[6].fp_typ invalidate in_uops[6].fp_rm invalidate in_uops[6].fp_val invalidate in_uops[6].fcn_op invalidate in_uops[6].fcn_dw invalidate in_uops[6].frs3_en invalidate in_uops[6].lrs2_rtype invalidate in_uops[6].lrs1_rtype invalidate in_uops[6].dst_rtype invalidate in_uops[6].lrs3 invalidate in_uops[6].lrs2 invalidate in_uops[6].lrs1 invalidate in_uops[6].ldst invalidate in_uops[6].ldst_is_rs1 invalidate in_uops[6].csr_cmd invalidate in_uops[6].flush_on_commit invalidate in_uops[6].is_unique invalidate in_uops[6].uses_stq invalidate in_uops[6].uses_ldq invalidate in_uops[6].mem_signed invalidate in_uops[6].mem_size invalidate in_uops[6].mem_cmd invalidate in_uops[6].exc_cause invalidate in_uops[6].exception invalidate in_uops[6].stale_pdst invalidate in_uops[6].ppred_busy invalidate in_uops[6].prs3_busy invalidate in_uops[6].prs2_busy invalidate in_uops[6].prs1_busy invalidate in_uops[6].ppred invalidate in_uops[6].prs3 invalidate in_uops[6].prs2 invalidate in_uops[6].prs1 invalidate in_uops[6].pdst invalidate in_uops[6].rxq_idx invalidate in_uops[6].stq_idx invalidate in_uops[6].ldq_idx invalidate in_uops[6].rob_idx invalidate in_uops[6].fp_ctrl.vec invalidate in_uops[6].fp_ctrl.wflags invalidate in_uops[6].fp_ctrl.sqrt invalidate in_uops[6].fp_ctrl.div invalidate in_uops[6].fp_ctrl.fma invalidate in_uops[6].fp_ctrl.fastpipe invalidate in_uops[6].fp_ctrl.toint invalidate in_uops[6].fp_ctrl.fromint invalidate in_uops[6].fp_ctrl.typeTagOut invalidate in_uops[6].fp_ctrl.typeTagIn invalidate in_uops[6].fp_ctrl.swap23 invalidate in_uops[6].fp_ctrl.swap12 invalidate in_uops[6].fp_ctrl.ren3 invalidate in_uops[6].fp_ctrl.ren2 invalidate in_uops[6].fp_ctrl.ren1 invalidate in_uops[6].fp_ctrl.wen invalidate in_uops[6].fp_ctrl.ldst invalidate in_uops[6].op2_sel invalidate in_uops[6].op1_sel invalidate in_uops[6].imm_packed invalidate in_uops[6].pimm invalidate in_uops[6].imm_sel invalidate in_uops[6].imm_rename invalidate in_uops[6].taken invalidate in_uops[6].pc_lob invalidate in_uops[6].edge_inst invalidate in_uops[6].ftq_idx invalidate in_uops[6].is_mov invalidate in_uops[6].is_rocc invalidate in_uops[6].is_sys_pc2epc invalidate in_uops[6].is_eret invalidate in_uops[6].is_amo invalidate in_uops[6].is_sfence invalidate in_uops[6].is_fencei invalidate in_uops[6].is_fence invalidate in_uops[6].is_sfb invalidate in_uops[6].br_type invalidate in_uops[6].br_tag invalidate in_uops[6].br_mask invalidate in_uops[6].dis_col_sel invalidate in_uops[6].iw_p3_bypass_hint invalidate in_uops[6].iw_p2_bypass_hint invalidate in_uops[6].iw_p1_bypass_hint invalidate in_uops[6].iw_p2_speculative_child invalidate in_uops[6].iw_p1_speculative_child invalidate in_uops[6].iw_issued_partial_dgen invalidate in_uops[6].iw_issued_partial_agen invalidate in_uops[6].iw_issued invalidate in_uops[6].fu_code[0] invalidate in_uops[6].fu_code[1] invalidate in_uops[6].fu_code[2] invalidate in_uops[6].fu_code[3] invalidate in_uops[6].fu_code[4] invalidate in_uops[6].fu_code[5] invalidate in_uops[6].fu_code[6] invalidate in_uops[6].fu_code[7] invalidate in_uops[6].fu_code[8] invalidate in_uops[6].fu_code[9] invalidate in_uops[6].iq_type[0] invalidate in_uops[6].iq_type[1] invalidate in_uops[6].iq_type[2] invalidate in_uops[6].iq_type[3] invalidate in_uops[6].debug_pc invalidate in_uops[6].is_rvc invalidate in_uops[6].debug_inst invalidate in_uops[6].inst node _in_mask_6_T = bits(io.enq.bits.mask, 6, 6) node _in_mask_6_T_1 = and(io.enq.valid, _in_mask_6_T) connect in_mask[6], _in_mask_6_T_1 connect in_uops[6].edge_inst, UInt<1>(0h0) connect in_uops[6].debug_pc, pc_6 connect in_uops[6].pc_lob, pc_6 node _in_uops_6_is_sfb_T = or(io.enq.bits.sfbs[6], io.enq.bits.shadowed_mask[6]) connect in_uops[6].is_sfb, _in_uops_6_is_sfb_T connect in_uops[6].ftq_idx, io.enq.bits.ftq_idx connect in_uops[6].inst, io.enq.bits.exp_insts[6] connect in_uops[6].debug_inst, io.enq.bits.insts[6] node _in_uops_6_is_rvc_T = bits(io.enq.bits.insts[6], 1, 0) node _in_uops_6_is_rvc_T_1 = neq(_in_uops_6_is_rvc_T, UInt<2>(0h3)) connect in_uops[6].is_rvc, _in_uops_6_is_rvc_T_1 node _in_uops_6_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h6)) node _in_uops_6_taken_T_1 = and(_in_uops_6_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[6].taken, _in_uops_6_taken_T_1 connect in_uops[6].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[6].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[6].bp_debug_if, io.enq.bits.bp_debug_if_oh[6] connect in_uops[6].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[6] connect in_uops[6].debug_fsrc, io.enq.bits.fsrc node _pc_T_28 = not(io.enq.bits.pc) node _pc_T_29 = or(_pc_T_28, UInt<3>(0h7)) node _pc_T_30 = not(_pc_T_29) node _pc_T_31 = add(_pc_T_30, UInt<4>(0he)) node pc_7 = tail(_pc_T_31, 1) invalidate in_uops[7].debug_tsrc invalidate in_uops[7].debug_fsrc invalidate in_uops[7].bp_xcpt_if invalidate in_uops[7].bp_debug_if invalidate in_uops[7].xcpt_ma_if invalidate in_uops[7].xcpt_ae_if invalidate in_uops[7].xcpt_pf_if invalidate in_uops[7].fp_typ invalidate in_uops[7].fp_rm invalidate in_uops[7].fp_val invalidate in_uops[7].fcn_op invalidate in_uops[7].fcn_dw invalidate in_uops[7].frs3_en invalidate in_uops[7].lrs2_rtype invalidate in_uops[7].lrs1_rtype invalidate in_uops[7].dst_rtype invalidate in_uops[7].lrs3 invalidate in_uops[7].lrs2 invalidate in_uops[7].lrs1 invalidate in_uops[7].ldst invalidate in_uops[7].ldst_is_rs1 invalidate in_uops[7].csr_cmd invalidate in_uops[7].flush_on_commit invalidate in_uops[7].is_unique invalidate in_uops[7].uses_stq invalidate in_uops[7].uses_ldq invalidate in_uops[7].mem_signed invalidate in_uops[7].mem_size invalidate in_uops[7].mem_cmd invalidate in_uops[7].exc_cause invalidate in_uops[7].exception invalidate in_uops[7].stale_pdst invalidate in_uops[7].ppred_busy invalidate in_uops[7].prs3_busy invalidate in_uops[7].prs2_busy invalidate in_uops[7].prs1_busy invalidate in_uops[7].ppred invalidate in_uops[7].prs3 invalidate in_uops[7].prs2 invalidate in_uops[7].prs1 invalidate in_uops[7].pdst invalidate in_uops[7].rxq_idx invalidate in_uops[7].stq_idx invalidate in_uops[7].ldq_idx invalidate in_uops[7].rob_idx invalidate in_uops[7].fp_ctrl.vec invalidate in_uops[7].fp_ctrl.wflags invalidate in_uops[7].fp_ctrl.sqrt invalidate in_uops[7].fp_ctrl.div invalidate in_uops[7].fp_ctrl.fma invalidate in_uops[7].fp_ctrl.fastpipe invalidate in_uops[7].fp_ctrl.toint invalidate in_uops[7].fp_ctrl.fromint invalidate in_uops[7].fp_ctrl.typeTagOut invalidate in_uops[7].fp_ctrl.typeTagIn invalidate in_uops[7].fp_ctrl.swap23 invalidate in_uops[7].fp_ctrl.swap12 invalidate in_uops[7].fp_ctrl.ren3 invalidate in_uops[7].fp_ctrl.ren2 invalidate in_uops[7].fp_ctrl.ren1 invalidate in_uops[7].fp_ctrl.wen invalidate in_uops[7].fp_ctrl.ldst invalidate in_uops[7].op2_sel invalidate in_uops[7].op1_sel invalidate in_uops[7].imm_packed invalidate in_uops[7].pimm invalidate in_uops[7].imm_sel invalidate in_uops[7].imm_rename invalidate in_uops[7].taken invalidate in_uops[7].pc_lob invalidate in_uops[7].edge_inst invalidate in_uops[7].ftq_idx invalidate in_uops[7].is_mov invalidate in_uops[7].is_rocc invalidate in_uops[7].is_sys_pc2epc invalidate in_uops[7].is_eret invalidate in_uops[7].is_amo invalidate in_uops[7].is_sfence invalidate in_uops[7].is_fencei invalidate in_uops[7].is_fence invalidate in_uops[7].is_sfb invalidate in_uops[7].br_type invalidate in_uops[7].br_tag invalidate in_uops[7].br_mask invalidate in_uops[7].dis_col_sel invalidate in_uops[7].iw_p3_bypass_hint invalidate in_uops[7].iw_p2_bypass_hint invalidate in_uops[7].iw_p1_bypass_hint invalidate in_uops[7].iw_p2_speculative_child invalidate in_uops[7].iw_p1_speculative_child invalidate in_uops[7].iw_issued_partial_dgen invalidate in_uops[7].iw_issued_partial_agen invalidate in_uops[7].iw_issued invalidate in_uops[7].fu_code[0] invalidate in_uops[7].fu_code[1] invalidate in_uops[7].fu_code[2] invalidate in_uops[7].fu_code[3] invalidate in_uops[7].fu_code[4] invalidate in_uops[7].fu_code[5] invalidate in_uops[7].fu_code[6] invalidate in_uops[7].fu_code[7] invalidate in_uops[7].fu_code[8] invalidate in_uops[7].fu_code[9] invalidate in_uops[7].iq_type[0] invalidate in_uops[7].iq_type[1] invalidate in_uops[7].iq_type[2] invalidate in_uops[7].iq_type[3] invalidate in_uops[7].debug_pc invalidate in_uops[7].is_rvc invalidate in_uops[7].debug_inst invalidate in_uops[7].inst node _in_mask_7_T = bits(io.enq.bits.mask, 7, 7) node _in_mask_7_T_1 = and(io.enq.valid, _in_mask_7_T) connect in_mask[7], _in_mask_7_T_1 connect in_uops[7].edge_inst, UInt<1>(0h0) connect in_uops[7].debug_pc, pc_7 connect in_uops[7].pc_lob, pc_7 node _in_uops_7_is_sfb_T = or(io.enq.bits.sfbs[7], io.enq.bits.shadowed_mask[7]) connect in_uops[7].is_sfb, _in_uops_7_is_sfb_T connect in_uops[7].ftq_idx, io.enq.bits.ftq_idx connect in_uops[7].inst, io.enq.bits.exp_insts[7] connect in_uops[7].debug_inst, io.enq.bits.insts[7] node _in_uops_7_is_rvc_T = bits(io.enq.bits.insts[7], 1, 0) node _in_uops_7_is_rvc_T_1 = neq(_in_uops_7_is_rvc_T, UInt<2>(0h3)) connect in_uops[7].is_rvc, _in_uops_7_is_rvc_T_1 node _in_uops_7_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<3>(0h7)) node _in_uops_7_taken_T_1 = and(_in_uops_7_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[7].taken, _in_uops_7_taken_T_1 connect in_uops[7].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[7].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[7].bp_debug_if, io.enq.bits.bp_debug_if_oh[7] connect in_uops[7].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[7] connect in_uops[7].debug_fsrc, io.enq.bits.fsrc wire enq_idxs : UInt<24>[8] connect enq_idxs[0], tail node _T = bits(tail, 22, 0) node _T_1 = bits(tail, 23, 23) node _T_2 = cat(_T, _T_1) node _T_3 = mux(in_mask[0], _T_2, tail) connect enq_idxs[1], _T_3 node _T_4 = bits(_T_3, 22, 0) node _T_5 = bits(_T_3, 23, 23) node _T_6 = cat(_T_4, _T_5) node _T_7 = mux(in_mask[1], _T_6, _T_3) connect enq_idxs[2], _T_7 node _T_8 = bits(_T_7, 22, 0) node _T_9 = bits(_T_7, 23, 23) node _T_10 = cat(_T_8, _T_9) node _T_11 = mux(in_mask[2], _T_10, _T_7) connect enq_idxs[3], _T_11 node _T_12 = bits(_T_11, 22, 0) node _T_13 = bits(_T_11, 23, 23) node _T_14 = cat(_T_12, _T_13) node _T_15 = mux(in_mask[3], _T_14, _T_11) connect enq_idxs[4], _T_15 node _T_16 = bits(_T_15, 22, 0) node _T_17 = bits(_T_15, 23, 23) node _T_18 = cat(_T_16, _T_17) node _T_19 = mux(in_mask[4], _T_18, _T_15) connect enq_idxs[5], _T_19 node _T_20 = bits(_T_19, 22, 0) node _T_21 = bits(_T_19, 23, 23) node _T_22 = cat(_T_20, _T_21) node _T_23 = mux(in_mask[5], _T_22, _T_19) connect enq_idxs[6], _T_23 node _T_24 = bits(_T_23, 22, 0) node _T_25 = bits(_T_23, 23, 23) node _T_26 = cat(_T_24, _T_25) node _T_27 = mux(in_mask[6], _T_26, _T_23) connect enq_idxs[7], _T_27 node _T_28 = bits(_T_27, 22, 0) node _T_29 = bits(_T_27, 23, 23) node _T_30 = cat(_T_28, _T_29) node _T_31 = mux(in_mask[7], _T_30, _T_27) node _T_32 = and(do_enq, in_mask[0]) node _T_33 = bits(enq_idxs[0], 0, 0) node _T_34 = and(_T_32, _T_33) when _T_34 : connect fb_uop_ram[0], in_uops[0] node _T_35 = and(do_enq, in_mask[0]) node _T_36 = bits(enq_idxs[0], 1, 1) node _T_37 = and(_T_35, _T_36) when _T_37 : connect fb_uop_ram[1], in_uops[0] node _T_38 = and(do_enq, in_mask[0]) node _T_39 = bits(enq_idxs[0], 2, 2) node _T_40 = and(_T_38, _T_39) when _T_40 : connect fb_uop_ram[2], in_uops[0] node _T_41 = and(do_enq, in_mask[0]) node _T_42 = bits(enq_idxs[0], 3, 3) node _T_43 = and(_T_41, _T_42) when _T_43 : connect fb_uop_ram[3], in_uops[0] node _T_44 = and(do_enq, in_mask[0]) node _T_45 = bits(enq_idxs[0], 4, 4) node _T_46 = and(_T_44, _T_45) when _T_46 : connect fb_uop_ram[4], in_uops[0] node _T_47 = and(do_enq, in_mask[0]) node _T_48 = bits(enq_idxs[0], 5, 5) node _T_49 = and(_T_47, _T_48) when _T_49 : connect fb_uop_ram[5], in_uops[0] node _T_50 = and(do_enq, in_mask[0]) node _T_51 = bits(enq_idxs[0], 6, 6) node _T_52 = and(_T_50, _T_51) when _T_52 : connect fb_uop_ram[6], in_uops[0] node _T_53 = and(do_enq, in_mask[0]) node _T_54 = bits(enq_idxs[0], 7, 7) node _T_55 = and(_T_53, _T_54) when _T_55 : connect fb_uop_ram[7], in_uops[0] node _T_56 = and(do_enq, in_mask[0]) node _T_57 = bits(enq_idxs[0], 8, 8) node _T_58 = and(_T_56, _T_57) when _T_58 : connect fb_uop_ram[8], in_uops[0] node _T_59 = and(do_enq, in_mask[0]) node _T_60 = bits(enq_idxs[0], 9, 9) node _T_61 = and(_T_59, _T_60) when _T_61 : connect fb_uop_ram[9], in_uops[0] node _T_62 = and(do_enq, in_mask[0]) node _T_63 = bits(enq_idxs[0], 10, 10) node _T_64 = and(_T_62, _T_63) when _T_64 : connect fb_uop_ram[10], in_uops[0] node _T_65 = and(do_enq, in_mask[0]) node _T_66 = bits(enq_idxs[0], 11, 11) node _T_67 = and(_T_65, _T_66) when _T_67 : connect fb_uop_ram[11], in_uops[0] node _T_68 = and(do_enq, in_mask[0]) node _T_69 = bits(enq_idxs[0], 12, 12) node _T_70 = and(_T_68, _T_69) when _T_70 : connect fb_uop_ram[12], in_uops[0] node _T_71 = and(do_enq, in_mask[0]) node _T_72 = bits(enq_idxs[0], 13, 13) node _T_73 = and(_T_71, _T_72) when _T_73 : connect fb_uop_ram[13], in_uops[0] node _T_74 = and(do_enq, in_mask[0]) node _T_75 = bits(enq_idxs[0], 14, 14) node _T_76 = and(_T_74, _T_75) when _T_76 : connect fb_uop_ram[14], in_uops[0] node _T_77 = and(do_enq, in_mask[0]) node _T_78 = bits(enq_idxs[0], 15, 15) node _T_79 = and(_T_77, _T_78) when _T_79 : connect fb_uop_ram[15], in_uops[0] node _T_80 = and(do_enq, in_mask[0]) node _T_81 = bits(enq_idxs[0], 16, 16) node _T_82 = and(_T_80, _T_81) when _T_82 : connect fb_uop_ram[16], in_uops[0] node _T_83 = and(do_enq, in_mask[0]) node _T_84 = bits(enq_idxs[0], 17, 17) node _T_85 = and(_T_83, _T_84) when _T_85 : connect fb_uop_ram[17], in_uops[0] node _T_86 = and(do_enq, in_mask[0]) node _T_87 = bits(enq_idxs[0], 18, 18) node _T_88 = and(_T_86, _T_87) when _T_88 : connect fb_uop_ram[18], in_uops[0] node _T_89 = and(do_enq, in_mask[0]) node _T_90 = bits(enq_idxs[0], 19, 19) node _T_91 = and(_T_89, _T_90) when _T_91 : connect fb_uop_ram[19], in_uops[0] node _T_92 = and(do_enq, in_mask[0]) node _T_93 = bits(enq_idxs[0], 20, 20) node _T_94 = and(_T_92, _T_93) when _T_94 : connect fb_uop_ram[20], in_uops[0] node _T_95 = and(do_enq, in_mask[0]) node _T_96 = bits(enq_idxs[0], 21, 21) node _T_97 = and(_T_95, _T_96) when _T_97 : connect fb_uop_ram[21], in_uops[0] node _T_98 = and(do_enq, in_mask[0]) node _T_99 = bits(enq_idxs[0], 22, 22) node _T_100 = and(_T_98, _T_99) when _T_100 : connect fb_uop_ram[22], in_uops[0] node _T_101 = and(do_enq, in_mask[0]) node _T_102 = bits(enq_idxs[0], 23, 23) node _T_103 = and(_T_101, _T_102) when _T_103 : connect fb_uop_ram[23], in_uops[0] node _T_104 = and(do_enq, in_mask[1]) node _T_105 = bits(enq_idxs[1], 0, 0) node _T_106 = and(_T_104, _T_105) when _T_106 : connect fb_uop_ram[0], in_uops[1] node _T_107 = and(do_enq, in_mask[1]) node _T_108 = bits(enq_idxs[1], 1, 1) node _T_109 = and(_T_107, _T_108) when _T_109 : connect fb_uop_ram[1], in_uops[1] node _T_110 = and(do_enq, in_mask[1]) node _T_111 = bits(enq_idxs[1], 2, 2) node _T_112 = and(_T_110, _T_111) when _T_112 : connect fb_uop_ram[2], in_uops[1] node _T_113 = and(do_enq, in_mask[1]) node _T_114 = bits(enq_idxs[1], 3, 3) node _T_115 = and(_T_113, _T_114) when _T_115 : connect fb_uop_ram[3], in_uops[1] node _T_116 = and(do_enq, in_mask[1]) node _T_117 = bits(enq_idxs[1], 4, 4) node _T_118 = and(_T_116, _T_117) when _T_118 : connect fb_uop_ram[4], in_uops[1] node _T_119 = and(do_enq, in_mask[1]) node _T_120 = bits(enq_idxs[1], 5, 5) node _T_121 = and(_T_119, _T_120) when _T_121 : connect fb_uop_ram[5], in_uops[1] node _T_122 = and(do_enq, in_mask[1]) node _T_123 = bits(enq_idxs[1], 6, 6) node _T_124 = and(_T_122, _T_123) when _T_124 : connect fb_uop_ram[6], in_uops[1] node _T_125 = and(do_enq, in_mask[1]) node _T_126 = bits(enq_idxs[1], 7, 7) node _T_127 = and(_T_125, _T_126) when _T_127 : connect fb_uop_ram[7], in_uops[1] node _T_128 = and(do_enq, in_mask[1]) node _T_129 = bits(enq_idxs[1], 8, 8) node _T_130 = and(_T_128, _T_129) when _T_130 : connect fb_uop_ram[8], in_uops[1] node _T_131 = and(do_enq, in_mask[1]) node _T_132 = bits(enq_idxs[1], 9, 9) node _T_133 = and(_T_131, _T_132) when _T_133 : connect fb_uop_ram[9], in_uops[1] node _T_134 = and(do_enq, in_mask[1]) node _T_135 = bits(enq_idxs[1], 10, 10) node _T_136 = and(_T_134, _T_135) when _T_136 : connect fb_uop_ram[10], in_uops[1] node _T_137 = and(do_enq, in_mask[1]) node _T_138 = bits(enq_idxs[1], 11, 11) node _T_139 = and(_T_137, _T_138) when _T_139 : connect fb_uop_ram[11], in_uops[1] node _T_140 = and(do_enq, in_mask[1]) node _T_141 = bits(enq_idxs[1], 12, 12) node _T_142 = and(_T_140, _T_141) when _T_142 : connect fb_uop_ram[12], in_uops[1] node _T_143 = and(do_enq, in_mask[1]) node _T_144 = bits(enq_idxs[1], 13, 13) node _T_145 = and(_T_143, _T_144) when _T_145 : connect fb_uop_ram[13], in_uops[1] node _T_146 = and(do_enq, in_mask[1]) node _T_147 = bits(enq_idxs[1], 14, 14) node _T_148 = and(_T_146, _T_147) when _T_148 : connect fb_uop_ram[14], in_uops[1] node _T_149 = and(do_enq, in_mask[1]) node _T_150 = bits(enq_idxs[1], 15, 15) node _T_151 = and(_T_149, _T_150) when _T_151 : connect fb_uop_ram[15], in_uops[1] node _T_152 = and(do_enq, in_mask[1]) node _T_153 = bits(enq_idxs[1], 16, 16) node _T_154 = and(_T_152, _T_153) when _T_154 : connect fb_uop_ram[16], in_uops[1] node _T_155 = and(do_enq, in_mask[1]) node _T_156 = bits(enq_idxs[1], 17, 17) node _T_157 = and(_T_155, _T_156) when _T_157 : connect fb_uop_ram[17], in_uops[1] node _T_158 = and(do_enq, in_mask[1]) node _T_159 = bits(enq_idxs[1], 18, 18) node _T_160 = and(_T_158, _T_159) when _T_160 : connect fb_uop_ram[18], in_uops[1] node _T_161 = and(do_enq, in_mask[1]) node _T_162 = bits(enq_idxs[1], 19, 19) node _T_163 = and(_T_161, _T_162) when _T_163 : connect fb_uop_ram[19], in_uops[1] node _T_164 = and(do_enq, in_mask[1]) node _T_165 = bits(enq_idxs[1], 20, 20) node _T_166 = and(_T_164, _T_165) when _T_166 : connect fb_uop_ram[20], in_uops[1] node _T_167 = and(do_enq, in_mask[1]) node _T_168 = bits(enq_idxs[1], 21, 21) node _T_169 = and(_T_167, _T_168) when _T_169 : connect fb_uop_ram[21], in_uops[1] node _T_170 = and(do_enq, in_mask[1]) node _T_171 = bits(enq_idxs[1], 22, 22) node _T_172 = and(_T_170, _T_171) when _T_172 : connect fb_uop_ram[22], in_uops[1] node _T_173 = and(do_enq, in_mask[1]) node _T_174 = bits(enq_idxs[1], 23, 23) node _T_175 = and(_T_173, _T_174) when _T_175 : connect fb_uop_ram[23], in_uops[1] node _T_176 = and(do_enq, in_mask[2]) node _T_177 = bits(enq_idxs[2], 0, 0) node _T_178 = and(_T_176, _T_177) when _T_178 : connect fb_uop_ram[0], in_uops[2] node _T_179 = and(do_enq, in_mask[2]) node _T_180 = bits(enq_idxs[2], 1, 1) node _T_181 = and(_T_179, _T_180) when _T_181 : connect fb_uop_ram[1], in_uops[2] node _T_182 = and(do_enq, in_mask[2]) node _T_183 = bits(enq_idxs[2], 2, 2) node _T_184 = and(_T_182, _T_183) when _T_184 : connect fb_uop_ram[2], in_uops[2] node _T_185 = and(do_enq, in_mask[2]) node _T_186 = bits(enq_idxs[2], 3, 3) node _T_187 = and(_T_185, _T_186) when _T_187 : connect fb_uop_ram[3], in_uops[2] node _T_188 = and(do_enq, in_mask[2]) node _T_189 = bits(enq_idxs[2], 4, 4) node _T_190 = and(_T_188, _T_189) when _T_190 : connect fb_uop_ram[4], in_uops[2] node _T_191 = and(do_enq, in_mask[2]) node _T_192 = bits(enq_idxs[2], 5, 5) node _T_193 = and(_T_191, _T_192) when _T_193 : connect fb_uop_ram[5], in_uops[2] node _T_194 = and(do_enq, in_mask[2]) node _T_195 = bits(enq_idxs[2], 6, 6) node _T_196 = and(_T_194, _T_195) when _T_196 : connect fb_uop_ram[6], in_uops[2] node _T_197 = and(do_enq, in_mask[2]) node _T_198 = bits(enq_idxs[2], 7, 7) node _T_199 = and(_T_197, _T_198) when _T_199 : connect fb_uop_ram[7], in_uops[2] node _T_200 = and(do_enq, in_mask[2]) node _T_201 = bits(enq_idxs[2], 8, 8) node _T_202 = and(_T_200, _T_201) when _T_202 : connect fb_uop_ram[8], in_uops[2] node _T_203 = and(do_enq, in_mask[2]) node _T_204 = bits(enq_idxs[2], 9, 9) node _T_205 = and(_T_203, _T_204) when _T_205 : connect fb_uop_ram[9], in_uops[2] node _T_206 = and(do_enq, in_mask[2]) node _T_207 = bits(enq_idxs[2], 10, 10) node _T_208 = and(_T_206, _T_207) when _T_208 : connect fb_uop_ram[10], in_uops[2] node _T_209 = and(do_enq, in_mask[2]) node _T_210 = bits(enq_idxs[2], 11, 11) node _T_211 = and(_T_209, _T_210) when _T_211 : connect fb_uop_ram[11], in_uops[2] node _T_212 = and(do_enq, in_mask[2]) node _T_213 = bits(enq_idxs[2], 12, 12) node _T_214 = and(_T_212, _T_213) when _T_214 : connect fb_uop_ram[12], in_uops[2] node _T_215 = and(do_enq, in_mask[2]) node _T_216 = bits(enq_idxs[2], 13, 13) node _T_217 = and(_T_215, _T_216) when _T_217 : connect fb_uop_ram[13], in_uops[2] node _T_218 = and(do_enq, in_mask[2]) node _T_219 = bits(enq_idxs[2], 14, 14) node _T_220 = and(_T_218, _T_219) when _T_220 : connect fb_uop_ram[14], in_uops[2] node _T_221 = and(do_enq, in_mask[2]) node _T_222 = bits(enq_idxs[2], 15, 15) node _T_223 = and(_T_221, _T_222) when _T_223 : connect fb_uop_ram[15], in_uops[2] node _T_224 = and(do_enq, in_mask[2]) node _T_225 = bits(enq_idxs[2], 16, 16) node _T_226 = and(_T_224, _T_225) when _T_226 : connect fb_uop_ram[16], in_uops[2] node _T_227 = and(do_enq, in_mask[2]) node _T_228 = bits(enq_idxs[2], 17, 17) node _T_229 = and(_T_227, _T_228) when _T_229 : connect fb_uop_ram[17], in_uops[2] node _T_230 = and(do_enq, in_mask[2]) node _T_231 = bits(enq_idxs[2], 18, 18) node _T_232 = and(_T_230, _T_231) when _T_232 : connect fb_uop_ram[18], in_uops[2] node _T_233 = and(do_enq, in_mask[2]) node _T_234 = bits(enq_idxs[2], 19, 19) node _T_235 = and(_T_233, _T_234) when _T_235 : connect fb_uop_ram[19], in_uops[2] node _T_236 = and(do_enq, in_mask[2]) node _T_237 = bits(enq_idxs[2], 20, 20) node _T_238 = and(_T_236, _T_237) when _T_238 : connect fb_uop_ram[20], in_uops[2] node _T_239 = and(do_enq, in_mask[2]) node _T_240 = bits(enq_idxs[2], 21, 21) node _T_241 = and(_T_239, _T_240) when _T_241 : connect fb_uop_ram[21], in_uops[2] node _T_242 = and(do_enq, in_mask[2]) node _T_243 = bits(enq_idxs[2], 22, 22) node _T_244 = and(_T_242, _T_243) when _T_244 : connect fb_uop_ram[22], in_uops[2] node _T_245 = and(do_enq, in_mask[2]) node _T_246 = bits(enq_idxs[2], 23, 23) node _T_247 = and(_T_245, _T_246) when _T_247 : connect fb_uop_ram[23], in_uops[2] node _T_248 = and(do_enq, in_mask[3]) node _T_249 = bits(enq_idxs[3], 0, 0) node _T_250 = and(_T_248, _T_249) when _T_250 : connect fb_uop_ram[0], in_uops[3] node _T_251 = and(do_enq, in_mask[3]) node _T_252 = bits(enq_idxs[3], 1, 1) node _T_253 = and(_T_251, _T_252) when _T_253 : connect fb_uop_ram[1], in_uops[3] node _T_254 = and(do_enq, in_mask[3]) node _T_255 = bits(enq_idxs[3], 2, 2) node _T_256 = and(_T_254, _T_255) when _T_256 : connect fb_uop_ram[2], in_uops[3] node _T_257 = and(do_enq, in_mask[3]) node _T_258 = bits(enq_idxs[3], 3, 3) node _T_259 = and(_T_257, _T_258) when _T_259 : connect fb_uop_ram[3], in_uops[3] node _T_260 = and(do_enq, in_mask[3]) node _T_261 = bits(enq_idxs[3], 4, 4) node _T_262 = and(_T_260, _T_261) when _T_262 : connect fb_uop_ram[4], in_uops[3] node _T_263 = and(do_enq, in_mask[3]) node _T_264 = bits(enq_idxs[3], 5, 5) node _T_265 = and(_T_263, _T_264) when _T_265 : connect fb_uop_ram[5], in_uops[3] node _T_266 = and(do_enq, in_mask[3]) node _T_267 = bits(enq_idxs[3], 6, 6) node _T_268 = and(_T_266, _T_267) when _T_268 : connect fb_uop_ram[6], in_uops[3] node _T_269 = and(do_enq, in_mask[3]) node _T_270 = bits(enq_idxs[3], 7, 7) node _T_271 = and(_T_269, _T_270) when _T_271 : connect fb_uop_ram[7], in_uops[3] node _T_272 = and(do_enq, in_mask[3]) node _T_273 = bits(enq_idxs[3], 8, 8) node _T_274 = and(_T_272, _T_273) when _T_274 : connect fb_uop_ram[8], in_uops[3] node _T_275 = and(do_enq, in_mask[3]) node _T_276 = bits(enq_idxs[3], 9, 9) node _T_277 = and(_T_275, _T_276) when _T_277 : connect fb_uop_ram[9], in_uops[3] node _T_278 = and(do_enq, in_mask[3]) node _T_279 = bits(enq_idxs[3], 10, 10) node _T_280 = and(_T_278, _T_279) when _T_280 : connect fb_uop_ram[10], in_uops[3] node _T_281 = and(do_enq, in_mask[3]) node _T_282 = bits(enq_idxs[3], 11, 11) node _T_283 = and(_T_281, _T_282) when _T_283 : connect fb_uop_ram[11], in_uops[3] node _T_284 = and(do_enq, in_mask[3]) node _T_285 = bits(enq_idxs[3], 12, 12) node _T_286 = and(_T_284, _T_285) when _T_286 : connect fb_uop_ram[12], in_uops[3] node _T_287 = and(do_enq, in_mask[3]) node _T_288 = bits(enq_idxs[3], 13, 13) node _T_289 = and(_T_287, _T_288) when _T_289 : connect fb_uop_ram[13], in_uops[3] node _T_290 = and(do_enq, in_mask[3]) node _T_291 = bits(enq_idxs[3], 14, 14) node _T_292 = and(_T_290, _T_291) when _T_292 : connect fb_uop_ram[14], in_uops[3] node _T_293 = and(do_enq, in_mask[3]) node _T_294 = bits(enq_idxs[3], 15, 15) node _T_295 = and(_T_293, _T_294) when _T_295 : connect fb_uop_ram[15], in_uops[3] node _T_296 = and(do_enq, in_mask[3]) node _T_297 = bits(enq_idxs[3], 16, 16) node _T_298 = and(_T_296, _T_297) when _T_298 : connect fb_uop_ram[16], in_uops[3] node _T_299 = and(do_enq, in_mask[3]) node _T_300 = bits(enq_idxs[3], 17, 17) node _T_301 = and(_T_299, _T_300) when _T_301 : connect fb_uop_ram[17], in_uops[3] node _T_302 = and(do_enq, in_mask[3]) node _T_303 = bits(enq_idxs[3], 18, 18) node _T_304 = and(_T_302, _T_303) when _T_304 : connect fb_uop_ram[18], in_uops[3] node _T_305 = and(do_enq, in_mask[3]) node _T_306 = bits(enq_idxs[3], 19, 19) node _T_307 = and(_T_305, _T_306) when _T_307 : connect fb_uop_ram[19], in_uops[3] node _T_308 = and(do_enq, in_mask[3]) node _T_309 = bits(enq_idxs[3], 20, 20) node _T_310 = and(_T_308, _T_309) when _T_310 : connect fb_uop_ram[20], in_uops[3] node _T_311 = and(do_enq, in_mask[3]) node _T_312 = bits(enq_idxs[3], 21, 21) node _T_313 = and(_T_311, _T_312) when _T_313 : connect fb_uop_ram[21], in_uops[3] node _T_314 = and(do_enq, in_mask[3]) node _T_315 = bits(enq_idxs[3], 22, 22) node _T_316 = and(_T_314, _T_315) when _T_316 : connect fb_uop_ram[22], in_uops[3] node _T_317 = and(do_enq, in_mask[3]) node _T_318 = bits(enq_idxs[3], 23, 23) node _T_319 = and(_T_317, _T_318) when _T_319 : connect fb_uop_ram[23], in_uops[3] node _T_320 = and(do_enq, in_mask[4]) node _T_321 = bits(enq_idxs[4], 0, 0) node _T_322 = and(_T_320, _T_321) when _T_322 : connect fb_uop_ram[0], in_uops[4] node _T_323 = and(do_enq, in_mask[4]) node _T_324 = bits(enq_idxs[4], 1, 1) node _T_325 = and(_T_323, _T_324) when _T_325 : connect fb_uop_ram[1], in_uops[4] node _T_326 = and(do_enq, in_mask[4]) node _T_327 = bits(enq_idxs[4], 2, 2) node _T_328 = and(_T_326, _T_327) when _T_328 : connect fb_uop_ram[2], in_uops[4] node _T_329 = and(do_enq, in_mask[4]) node _T_330 = bits(enq_idxs[4], 3, 3) node _T_331 = and(_T_329, _T_330) when _T_331 : connect fb_uop_ram[3], in_uops[4] node _T_332 = and(do_enq, in_mask[4]) node _T_333 = bits(enq_idxs[4], 4, 4) node _T_334 = and(_T_332, _T_333) when _T_334 : connect fb_uop_ram[4], in_uops[4] node _T_335 = and(do_enq, in_mask[4]) node _T_336 = bits(enq_idxs[4], 5, 5) node _T_337 = and(_T_335, _T_336) when _T_337 : connect fb_uop_ram[5], in_uops[4] node _T_338 = and(do_enq, in_mask[4]) node _T_339 = bits(enq_idxs[4], 6, 6) node _T_340 = and(_T_338, _T_339) when _T_340 : connect fb_uop_ram[6], in_uops[4] node _T_341 = and(do_enq, in_mask[4]) node _T_342 = bits(enq_idxs[4], 7, 7) node _T_343 = and(_T_341, _T_342) when _T_343 : connect fb_uop_ram[7], in_uops[4] node _T_344 = and(do_enq, in_mask[4]) node _T_345 = bits(enq_idxs[4], 8, 8) node _T_346 = and(_T_344, _T_345) when _T_346 : connect fb_uop_ram[8], in_uops[4] node _T_347 = and(do_enq, in_mask[4]) node _T_348 = bits(enq_idxs[4], 9, 9) node _T_349 = and(_T_347, _T_348) when _T_349 : connect fb_uop_ram[9], in_uops[4] node _T_350 = and(do_enq, in_mask[4]) node _T_351 = bits(enq_idxs[4], 10, 10) node _T_352 = and(_T_350, _T_351) when _T_352 : connect fb_uop_ram[10], in_uops[4] node _T_353 = and(do_enq, in_mask[4]) node _T_354 = bits(enq_idxs[4], 11, 11) node _T_355 = and(_T_353, _T_354) when _T_355 : connect fb_uop_ram[11], in_uops[4] node _T_356 = and(do_enq, in_mask[4]) node _T_357 = bits(enq_idxs[4], 12, 12) node _T_358 = and(_T_356, _T_357) when _T_358 : connect fb_uop_ram[12], in_uops[4] node _T_359 = and(do_enq, in_mask[4]) node _T_360 = bits(enq_idxs[4], 13, 13) node _T_361 = and(_T_359, _T_360) when _T_361 : connect fb_uop_ram[13], in_uops[4] node _T_362 = and(do_enq, in_mask[4]) node _T_363 = bits(enq_idxs[4], 14, 14) node _T_364 = and(_T_362, _T_363) when _T_364 : connect fb_uop_ram[14], in_uops[4] node _T_365 = and(do_enq, in_mask[4]) node _T_366 = bits(enq_idxs[4], 15, 15) node _T_367 = and(_T_365, _T_366) when _T_367 : connect fb_uop_ram[15], in_uops[4] node _T_368 = and(do_enq, in_mask[4]) node _T_369 = bits(enq_idxs[4], 16, 16) node _T_370 = and(_T_368, _T_369) when _T_370 : connect fb_uop_ram[16], in_uops[4] node _T_371 = and(do_enq, in_mask[4]) node _T_372 = bits(enq_idxs[4], 17, 17) node _T_373 = and(_T_371, _T_372) when _T_373 : connect fb_uop_ram[17], in_uops[4] node _T_374 = and(do_enq, in_mask[4]) node _T_375 = bits(enq_idxs[4], 18, 18) node _T_376 = and(_T_374, _T_375) when _T_376 : connect fb_uop_ram[18], in_uops[4] node _T_377 = and(do_enq, in_mask[4]) node _T_378 = bits(enq_idxs[4], 19, 19) node _T_379 = and(_T_377, _T_378) when _T_379 : connect fb_uop_ram[19], in_uops[4] node _T_380 = and(do_enq, in_mask[4]) node _T_381 = bits(enq_idxs[4], 20, 20) node _T_382 = and(_T_380, _T_381) when _T_382 : connect fb_uop_ram[20], in_uops[4] node _T_383 = and(do_enq, in_mask[4]) node _T_384 = bits(enq_idxs[4], 21, 21) node _T_385 = and(_T_383, _T_384) when _T_385 : connect fb_uop_ram[21], in_uops[4] node _T_386 = and(do_enq, in_mask[4]) node _T_387 = bits(enq_idxs[4], 22, 22) node _T_388 = and(_T_386, _T_387) when _T_388 : connect fb_uop_ram[22], in_uops[4] node _T_389 = and(do_enq, in_mask[4]) node _T_390 = bits(enq_idxs[4], 23, 23) node _T_391 = and(_T_389, _T_390) when _T_391 : connect fb_uop_ram[23], in_uops[4] node _T_392 = and(do_enq, in_mask[5]) node _T_393 = bits(enq_idxs[5], 0, 0) node _T_394 = and(_T_392, _T_393) when _T_394 : connect fb_uop_ram[0], in_uops[5] node _T_395 = and(do_enq, in_mask[5]) node _T_396 = bits(enq_idxs[5], 1, 1) node _T_397 = and(_T_395, _T_396) when _T_397 : connect fb_uop_ram[1], in_uops[5] node _T_398 = and(do_enq, in_mask[5]) node _T_399 = bits(enq_idxs[5], 2, 2) node _T_400 = and(_T_398, _T_399) when _T_400 : connect fb_uop_ram[2], in_uops[5] node _T_401 = and(do_enq, in_mask[5]) node _T_402 = bits(enq_idxs[5], 3, 3) node _T_403 = and(_T_401, _T_402) when _T_403 : connect fb_uop_ram[3], in_uops[5] node _T_404 = and(do_enq, in_mask[5]) node _T_405 = bits(enq_idxs[5], 4, 4) node _T_406 = and(_T_404, _T_405) when _T_406 : connect fb_uop_ram[4], in_uops[5] node _T_407 = and(do_enq, in_mask[5]) node _T_408 = bits(enq_idxs[5], 5, 5) node _T_409 = and(_T_407, _T_408) when _T_409 : connect fb_uop_ram[5], in_uops[5] node _T_410 = and(do_enq, in_mask[5]) node _T_411 = bits(enq_idxs[5], 6, 6) node _T_412 = and(_T_410, _T_411) when _T_412 : connect fb_uop_ram[6], in_uops[5] node _T_413 = and(do_enq, in_mask[5]) node _T_414 = bits(enq_idxs[5], 7, 7) node _T_415 = and(_T_413, _T_414) when _T_415 : connect fb_uop_ram[7], in_uops[5] node _T_416 = and(do_enq, in_mask[5]) node _T_417 = bits(enq_idxs[5], 8, 8) node _T_418 = and(_T_416, _T_417) when _T_418 : connect fb_uop_ram[8], in_uops[5] node _T_419 = and(do_enq, in_mask[5]) node _T_420 = bits(enq_idxs[5], 9, 9) node _T_421 = and(_T_419, _T_420) when _T_421 : connect fb_uop_ram[9], in_uops[5] node _T_422 = and(do_enq, in_mask[5]) node _T_423 = bits(enq_idxs[5], 10, 10) node _T_424 = and(_T_422, _T_423) when _T_424 : connect fb_uop_ram[10], in_uops[5] node _T_425 = and(do_enq, in_mask[5]) node _T_426 = bits(enq_idxs[5], 11, 11) node _T_427 = and(_T_425, _T_426) when _T_427 : connect fb_uop_ram[11], in_uops[5] node _T_428 = and(do_enq, in_mask[5]) node _T_429 = bits(enq_idxs[5], 12, 12) node _T_430 = and(_T_428, _T_429) when _T_430 : connect fb_uop_ram[12], in_uops[5] node _T_431 = and(do_enq, in_mask[5]) node _T_432 = bits(enq_idxs[5], 13, 13) node _T_433 = and(_T_431, _T_432) when _T_433 : connect fb_uop_ram[13], in_uops[5] node _T_434 = and(do_enq, in_mask[5]) node _T_435 = bits(enq_idxs[5], 14, 14) node _T_436 = and(_T_434, _T_435) when _T_436 : connect fb_uop_ram[14], in_uops[5] node _T_437 = and(do_enq, in_mask[5]) node _T_438 = bits(enq_idxs[5], 15, 15) node _T_439 = and(_T_437, _T_438) when _T_439 : connect fb_uop_ram[15], in_uops[5] node _T_440 = and(do_enq, in_mask[5]) node _T_441 = bits(enq_idxs[5], 16, 16) node _T_442 = and(_T_440, _T_441) when _T_442 : connect fb_uop_ram[16], in_uops[5] node _T_443 = and(do_enq, in_mask[5]) node _T_444 = bits(enq_idxs[5], 17, 17) node _T_445 = and(_T_443, _T_444) when _T_445 : connect fb_uop_ram[17], in_uops[5] node _T_446 = and(do_enq, in_mask[5]) node _T_447 = bits(enq_idxs[5], 18, 18) node _T_448 = and(_T_446, _T_447) when _T_448 : connect fb_uop_ram[18], in_uops[5] node _T_449 = and(do_enq, in_mask[5]) node _T_450 = bits(enq_idxs[5], 19, 19) node _T_451 = and(_T_449, _T_450) when _T_451 : connect fb_uop_ram[19], in_uops[5] node _T_452 = and(do_enq, in_mask[5]) node _T_453 = bits(enq_idxs[5], 20, 20) node _T_454 = and(_T_452, _T_453) when _T_454 : connect fb_uop_ram[20], in_uops[5] node _T_455 = and(do_enq, in_mask[5]) node _T_456 = bits(enq_idxs[5], 21, 21) node _T_457 = and(_T_455, _T_456) when _T_457 : connect fb_uop_ram[21], in_uops[5] node _T_458 = and(do_enq, in_mask[5]) node _T_459 = bits(enq_idxs[5], 22, 22) node _T_460 = and(_T_458, _T_459) when _T_460 : connect fb_uop_ram[22], in_uops[5] node _T_461 = and(do_enq, in_mask[5]) node _T_462 = bits(enq_idxs[5], 23, 23) node _T_463 = and(_T_461, _T_462) when _T_463 : connect fb_uop_ram[23], in_uops[5] node _T_464 = and(do_enq, in_mask[6]) node _T_465 = bits(enq_idxs[6], 0, 0) node _T_466 = and(_T_464, _T_465) when _T_466 : connect fb_uop_ram[0], in_uops[6] node _T_467 = and(do_enq, in_mask[6]) node _T_468 = bits(enq_idxs[6], 1, 1) node _T_469 = and(_T_467, _T_468) when _T_469 : connect fb_uop_ram[1], in_uops[6] node _T_470 = and(do_enq, in_mask[6]) node _T_471 = bits(enq_idxs[6], 2, 2) node _T_472 = and(_T_470, _T_471) when _T_472 : connect fb_uop_ram[2], in_uops[6] node _T_473 = and(do_enq, in_mask[6]) node _T_474 = bits(enq_idxs[6], 3, 3) node _T_475 = and(_T_473, _T_474) when _T_475 : connect fb_uop_ram[3], in_uops[6] node _T_476 = and(do_enq, in_mask[6]) node _T_477 = bits(enq_idxs[6], 4, 4) node _T_478 = and(_T_476, _T_477) when _T_478 : connect fb_uop_ram[4], in_uops[6] node _T_479 = and(do_enq, in_mask[6]) node _T_480 = bits(enq_idxs[6], 5, 5) node _T_481 = and(_T_479, _T_480) when _T_481 : connect fb_uop_ram[5], in_uops[6] node _T_482 = and(do_enq, in_mask[6]) node _T_483 = bits(enq_idxs[6], 6, 6) node _T_484 = and(_T_482, _T_483) when _T_484 : connect fb_uop_ram[6], in_uops[6] node _T_485 = and(do_enq, in_mask[6]) node _T_486 = bits(enq_idxs[6], 7, 7) node _T_487 = and(_T_485, _T_486) when _T_487 : connect fb_uop_ram[7], in_uops[6] node _T_488 = and(do_enq, in_mask[6]) node _T_489 = bits(enq_idxs[6], 8, 8) node _T_490 = and(_T_488, _T_489) when _T_490 : connect fb_uop_ram[8], in_uops[6] node _T_491 = and(do_enq, in_mask[6]) node _T_492 = bits(enq_idxs[6], 9, 9) node _T_493 = and(_T_491, _T_492) when _T_493 : connect fb_uop_ram[9], in_uops[6] node _T_494 = and(do_enq, in_mask[6]) node _T_495 = bits(enq_idxs[6], 10, 10) node _T_496 = and(_T_494, _T_495) when _T_496 : connect fb_uop_ram[10], in_uops[6] node _T_497 = and(do_enq, in_mask[6]) node _T_498 = bits(enq_idxs[6], 11, 11) node _T_499 = and(_T_497, _T_498) when _T_499 : connect fb_uop_ram[11], in_uops[6] node _T_500 = and(do_enq, in_mask[6]) node _T_501 = bits(enq_idxs[6], 12, 12) node _T_502 = and(_T_500, _T_501) when _T_502 : connect fb_uop_ram[12], in_uops[6] node _T_503 = and(do_enq, in_mask[6]) node _T_504 = bits(enq_idxs[6], 13, 13) node _T_505 = and(_T_503, _T_504) when _T_505 : connect fb_uop_ram[13], in_uops[6] node _T_506 = and(do_enq, in_mask[6]) node _T_507 = bits(enq_idxs[6], 14, 14) node _T_508 = and(_T_506, _T_507) when _T_508 : connect fb_uop_ram[14], in_uops[6] node _T_509 = and(do_enq, in_mask[6]) node _T_510 = bits(enq_idxs[6], 15, 15) node _T_511 = and(_T_509, _T_510) when _T_511 : connect fb_uop_ram[15], in_uops[6] node _T_512 = and(do_enq, in_mask[6]) node _T_513 = bits(enq_idxs[6], 16, 16) node _T_514 = and(_T_512, _T_513) when _T_514 : connect fb_uop_ram[16], in_uops[6] node _T_515 = and(do_enq, in_mask[6]) node _T_516 = bits(enq_idxs[6], 17, 17) node _T_517 = and(_T_515, _T_516) when _T_517 : connect fb_uop_ram[17], in_uops[6] node _T_518 = and(do_enq, in_mask[6]) node _T_519 = bits(enq_idxs[6], 18, 18) node _T_520 = and(_T_518, _T_519) when _T_520 : connect fb_uop_ram[18], in_uops[6] node _T_521 = and(do_enq, in_mask[6]) node _T_522 = bits(enq_idxs[6], 19, 19) node _T_523 = and(_T_521, _T_522) when _T_523 : connect fb_uop_ram[19], in_uops[6] node _T_524 = and(do_enq, in_mask[6]) node _T_525 = bits(enq_idxs[6], 20, 20) node _T_526 = and(_T_524, _T_525) when _T_526 : connect fb_uop_ram[20], in_uops[6] node _T_527 = and(do_enq, in_mask[6]) node _T_528 = bits(enq_idxs[6], 21, 21) node _T_529 = and(_T_527, _T_528) when _T_529 : connect fb_uop_ram[21], in_uops[6] node _T_530 = and(do_enq, in_mask[6]) node _T_531 = bits(enq_idxs[6], 22, 22) node _T_532 = and(_T_530, _T_531) when _T_532 : connect fb_uop_ram[22], in_uops[6] node _T_533 = and(do_enq, in_mask[6]) node _T_534 = bits(enq_idxs[6], 23, 23) node _T_535 = and(_T_533, _T_534) when _T_535 : connect fb_uop_ram[23], in_uops[6] node _T_536 = and(do_enq, in_mask[7]) node _T_537 = bits(enq_idxs[7], 0, 0) node _T_538 = and(_T_536, _T_537) when _T_538 : connect fb_uop_ram[0], in_uops[7] node _T_539 = and(do_enq, in_mask[7]) node _T_540 = bits(enq_idxs[7], 1, 1) node _T_541 = and(_T_539, _T_540) when _T_541 : connect fb_uop_ram[1], in_uops[7] node _T_542 = and(do_enq, in_mask[7]) node _T_543 = bits(enq_idxs[7], 2, 2) node _T_544 = and(_T_542, _T_543) when _T_544 : connect fb_uop_ram[2], in_uops[7] node _T_545 = and(do_enq, in_mask[7]) node _T_546 = bits(enq_idxs[7], 3, 3) node _T_547 = and(_T_545, _T_546) when _T_547 : connect fb_uop_ram[3], in_uops[7] node _T_548 = and(do_enq, in_mask[7]) node _T_549 = bits(enq_idxs[7], 4, 4) node _T_550 = and(_T_548, _T_549) when _T_550 : connect fb_uop_ram[4], in_uops[7] node _T_551 = and(do_enq, in_mask[7]) node _T_552 = bits(enq_idxs[7], 5, 5) node _T_553 = and(_T_551, _T_552) when _T_553 : connect fb_uop_ram[5], in_uops[7] node _T_554 = and(do_enq, in_mask[7]) node _T_555 = bits(enq_idxs[7], 6, 6) node _T_556 = and(_T_554, _T_555) when _T_556 : connect fb_uop_ram[6], in_uops[7] node _T_557 = and(do_enq, in_mask[7]) node _T_558 = bits(enq_idxs[7], 7, 7) node _T_559 = and(_T_557, _T_558) when _T_559 : connect fb_uop_ram[7], in_uops[7] node _T_560 = and(do_enq, in_mask[7]) node _T_561 = bits(enq_idxs[7], 8, 8) node _T_562 = and(_T_560, _T_561) when _T_562 : connect fb_uop_ram[8], in_uops[7] node _T_563 = and(do_enq, in_mask[7]) node _T_564 = bits(enq_idxs[7], 9, 9) node _T_565 = and(_T_563, _T_564) when _T_565 : connect fb_uop_ram[9], in_uops[7] node _T_566 = and(do_enq, in_mask[7]) node _T_567 = bits(enq_idxs[7], 10, 10) node _T_568 = and(_T_566, _T_567) when _T_568 : connect fb_uop_ram[10], in_uops[7] node _T_569 = and(do_enq, in_mask[7]) node _T_570 = bits(enq_idxs[7], 11, 11) node _T_571 = and(_T_569, _T_570) when _T_571 : connect fb_uop_ram[11], in_uops[7] node _T_572 = and(do_enq, in_mask[7]) node _T_573 = bits(enq_idxs[7], 12, 12) node _T_574 = and(_T_572, _T_573) when _T_574 : connect fb_uop_ram[12], in_uops[7] node _T_575 = and(do_enq, in_mask[7]) node _T_576 = bits(enq_idxs[7], 13, 13) node _T_577 = and(_T_575, _T_576) when _T_577 : connect fb_uop_ram[13], in_uops[7] node _T_578 = and(do_enq, in_mask[7]) node _T_579 = bits(enq_idxs[7], 14, 14) node _T_580 = and(_T_578, _T_579) when _T_580 : connect fb_uop_ram[14], in_uops[7] node _T_581 = and(do_enq, in_mask[7]) node _T_582 = bits(enq_idxs[7], 15, 15) node _T_583 = and(_T_581, _T_582) when _T_583 : connect fb_uop_ram[15], in_uops[7] node _T_584 = and(do_enq, in_mask[7]) node _T_585 = bits(enq_idxs[7], 16, 16) node _T_586 = and(_T_584, _T_585) when _T_586 : connect fb_uop_ram[16], in_uops[7] node _T_587 = and(do_enq, in_mask[7]) node _T_588 = bits(enq_idxs[7], 17, 17) node _T_589 = and(_T_587, _T_588) when _T_589 : connect fb_uop_ram[17], in_uops[7] node _T_590 = and(do_enq, in_mask[7]) node _T_591 = bits(enq_idxs[7], 18, 18) node _T_592 = and(_T_590, _T_591) when _T_592 : connect fb_uop_ram[18], in_uops[7] node _T_593 = and(do_enq, in_mask[7]) node _T_594 = bits(enq_idxs[7], 19, 19) node _T_595 = and(_T_593, _T_594) when _T_595 : connect fb_uop_ram[19], in_uops[7] node _T_596 = and(do_enq, in_mask[7]) node _T_597 = bits(enq_idxs[7], 20, 20) node _T_598 = and(_T_596, _T_597) when _T_598 : connect fb_uop_ram[20], in_uops[7] node _T_599 = and(do_enq, in_mask[7]) node _T_600 = bits(enq_idxs[7], 21, 21) node _T_601 = and(_T_599, _T_600) when _T_601 : connect fb_uop_ram[21], in_uops[7] node _T_602 = and(do_enq, in_mask[7]) node _T_603 = bits(enq_idxs[7], 22, 22) node _T_604 = and(_T_602, _T_603) when _T_604 : connect fb_uop_ram[22], in_uops[7] node _T_605 = and(do_enq, in_mask[7]) node _T_606 = bits(enq_idxs[7], 23, 23) node _T_607 = and(_T_605, _T_606) when _T_607 : connect fb_uop_ram[23], in_uops[7] node _tail_collisions_T = bits(head, 0, 0) node _tail_collisions_T_1 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_2 = or(_tail_collisions_T_1, UInt<1>(0h0)) node _tail_collisions_T_3 = and(_tail_collisions_T, _tail_collisions_T_2) node _tail_collisions_T_4 = bits(head, 0, 0) node _tail_collisions_T_5 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_6 = or(_tail_collisions_T_5, UInt<1>(0h1)) node _tail_collisions_T_7 = and(_tail_collisions_T_4, _tail_collisions_T_6) node _tail_collisions_T_8 = bits(head, 0, 0) node _tail_collisions_T_9 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_10 = or(_tail_collisions_T_9, UInt<1>(0h1)) node _tail_collisions_T_11 = and(_tail_collisions_T_8, _tail_collisions_T_10) node _tail_collisions_T_12 = bits(head, 1, 1) node _tail_collisions_T_13 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_14 = or(_tail_collisions_T_13, UInt<1>(0h0)) node _tail_collisions_T_15 = and(_tail_collisions_T_12, _tail_collisions_T_14) node _tail_collisions_T_16 = bits(head, 1, 1) node _tail_collisions_T_17 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_18 = or(_tail_collisions_T_17, UInt<1>(0h1)) node _tail_collisions_T_19 = and(_tail_collisions_T_16, _tail_collisions_T_18) node _tail_collisions_T_20 = bits(head, 1, 1) node _tail_collisions_T_21 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_22 = or(_tail_collisions_T_21, UInt<1>(0h1)) node _tail_collisions_T_23 = and(_tail_collisions_T_20, _tail_collisions_T_22) node _tail_collisions_T_24 = bits(head, 2, 2) node _tail_collisions_T_25 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_26 = or(_tail_collisions_T_25, UInt<1>(0h0)) node _tail_collisions_T_27 = and(_tail_collisions_T_24, _tail_collisions_T_26) node _tail_collisions_T_28 = bits(head, 2, 2) node _tail_collisions_T_29 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_30 = or(_tail_collisions_T_29, UInt<1>(0h1)) node _tail_collisions_T_31 = and(_tail_collisions_T_28, _tail_collisions_T_30) node _tail_collisions_T_32 = bits(head, 2, 2) node _tail_collisions_T_33 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_34 = or(_tail_collisions_T_33, UInt<1>(0h1)) node _tail_collisions_T_35 = and(_tail_collisions_T_32, _tail_collisions_T_34) node _tail_collisions_T_36 = bits(head, 3, 3) node _tail_collisions_T_37 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_38 = or(_tail_collisions_T_37, UInt<1>(0h0)) node _tail_collisions_T_39 = and(_tail_collisions_T_36, _tail_collisions_T_38) node _tail_collisions_T_40 = bits(head, 3, 3) node _tail_collisions_T_41 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_42 = or(_tail_collisions_T_41, UInt<1>(0h1)) node _tail_collisions_T_43 = and(_tail_collisions_T_40, _tail_collisions_T_42) node _tail_collisions_T_44 = bits(head, 3, 3) node _tail_collisions_T_45 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_46 = or(_tail_collisions_T_45, UInt<1>(0h1)) node _tail_collisions_T_47 = and(_tail_collisions_T_44, _tail_collisions_T_46) node _tail_collisions_T_48 = bits(head, 4, 4) node _tail_collisions_T_49 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_50 = or(_tail_collisions_T_49, UInt<1>(0h0)) node _tail_collisions_T_51 = and(_tail_collisions_T_48, _tail_collisions_T_50) node _tail_collisions_T_52 = bits(head, 4, 4) node _tail_collisions_T_53 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_54 = or(_tail_collisions_T_53, UInt<1>(0h1)) node _tail_collisions_T_55 = and(_tail_collisions_T_52, _tail_collisions_T_54) node _tail_collisions_T_56 = bits(head, 4, 4) node _tail_collisions_T_57 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_58 = or(_tail_collisions_T_57, UInt<1>(0h1)) node _tail_collisions_T_59 = and(_tail_collisions_T_56, _tail_collisions_T_58) node _tail_collisions_T_60 = bits(head, 5, 5) node _tail_collisions_T_61 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_62 = or(_tail_collisions_T_61, UInt<1>(0h0)) node _tail_collisions_T_63 = and(_tail_collisions_T_60, _tail_collisions_T_62) node _tail_collisions_T_64 = bits(head, 5, 5) node _tail_collisions_T_65 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_66 = or(_tail_collisions_T_65, UInt<1>(0h1)) node _tail_collisions_T_67 = and(_tail_collisions_T_64, _tail_collisions_T_66) node _tail_collisions_T_68 = bits(head, 5, 5) node _tail_collisions_T_69 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_70 = or(_tail_collisions_T_69, UInt<1>(0h1)) node _tail_collisions_T_71 = and(_tail_collisions_T_68, _tail_collisions_T_70) node _tail_collisions_T_72 = bits(head, 6, 6) node _tail_collisions_T_73 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_74 = or(_tail_collisions_T_73, UInt<1>(0h0)) node _tail_collisions_T_75 = and(_tail_collisions_T_72, _tail_collisions_T_74) node _tail_collisions_T_76 = bits(head, 6, 6) node _tail_collisions_T_77 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_78 = or(_tail_collisions_T_77, UInt<1>(0h1)) node _tail_collisions_T_79 = and(_tail_collisions_T_76, _tail_collisions_T_78) node _tail_collisions_T_80 = bits(head, 6, 6) node _tail_collisions_T_81 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_82 = or(_tail_collisions_T_81, UInt<1>(0h1)) node _tail_collisions_T_83 = and(_tail_collisions_T_80, _tail_collisions_T_82) node _tail_collisions_T_84 = bits(head, 7, 7) node _tail_collisions_T_85 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_86 = or(_tail_collisions_T_85, UInt<1>(0h0)) node _tail_collisions_T_87 = and(_tail_collisions_T_84, _tail_collisions_T_86) node _tail_collisions_T_88 = bits(head, 7, 7) node _tail_collisions_T_89 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_90 = or(_tail_collisions_T_89, UInt<1>(0h1)) node _tail_collisions_T_91 = and(_tail_collisions_T_88, _tail_collisions_T_90) node _tail_collisions_T_92 = bits(head, 7, 7) node _tail_collisions_T_93 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_94 = or(_tail_collisions_T_93, UInt<1>(0h1)) node _tail_collisions_T_95 = and(_tail_collisions_T_92, _tail_collisions_T_94) wire _tail_collisions_WIRE : UInt<1>[24] connect _tail_collisions_WIRE[0], _tail_collisions_T_3 connect _tail_collisions_WIRE[1], _tail_collisions_T_7 connect _tail_collisions_WIRE[2], _tail_collisions_T_11 connect _tail_collisions_WIRE[3], _tail_collisions_T_15 connect _tail_collisions_WIRE[4], _tail_collisions_T_19 connect _tail_collisions_WIRE[5], _tail_collisions_T_23 connect _tail_collisions_WIRE[6], _tail_collisions_T_27 connect _tail_collisions_WIRE[7], _tail_collisions_T_31 connect _tail_collisions_WIRE[8], _tail_collisions_T_35 connect _tail_collisions_WIRE[9], _tail_collisions_T_39 connect _tail_collisions_WIRE[10], _tail_collisions_T_43 connect _tail_collisions_WIRE[11], _tail_collisions_T_47 connect _tail_collisions_WIRE[12], _tail_collisions_T_51 connect _tail_collisions_WIRE[13], _tail_collisions_T_55 connect _tail_collisions_WIRE[14], _tail_collisions_T_59 connect _tail_collisions_WIRE[15], _tail_collisions_T_63 connect _tail_collisions_WIRE[16], _tail_collisions_T_67 connect _tail_collisions_WIRE[17], _tail_collisions_T_71 connect _tail_collisions_WIRE[18], _tail_collisions_T_75 connect _tail_collisions_WIRE[19], _tail_collisions_T_79 connect _tail_collisions_WIRE[20], _tail_collisions_T_83 connect _tail_collisions_WIRE[21], _tail_collisions_T_87 connect _tail_collisions_WIRE[22], _tail_collisions_T_91 connect _tail_collisions_WIRE[23], _tail_collisions_T_95 node tail_collisions_lo_lo_lo_hi = cat(_tail_collisions_WIRE[2], _tail_collisions_WIRE[1]) node tail_collisions_lo_lo_lo = cat(tail_collisions_lo_lo_lo_hi, _tail_collisions_WIRE[0]) node tail_collisions_lo_lo_hi_hi = cat(_tail_collisions_WIRE[5], _tail_collisions_WIRE[4]) node tail_collisions_lo_lo_hi = cat(tail_collisions_lo_lo_hi_hi, _tail_collisions_WIRE[3]) node tail_collisions_lo_lo = cat(tail_collisions_lo_lo_hi, tail_collisions_lo_lo_lo) node tail_collisions_lo_hi_lo_hi = cat(_tail_collisions_WIRE[8], _tail_collisions_WIRE[7]) node tail_collisions_lo_hi_lo = cat(tail_collisions_lo_hi_lo_hi, _tail_collisions_WIRE[6]) node tail_collisions_lo_hi_hi_hi = cat(_tail_collisions_WIRE[11], _tail_collisions_WIRE[10]) node tail_collisions_lo_hi_hi = cat(tail_collisions_lo_hi_hi_hi, _tail_collisions_WIRE[9]) node tail_collisions_lo_hi = cat(tail_collisions_lo_hi_hi, tail_collisions_lo_hi_lo) node tail_collisions_lo = cat(tail_collisions_lo_hi, tail_collisions_lo_lo) node tail_collisions_hi_lo_lo_hi = cat(_tail_collisions_WIRE[14], _tail_collisions_WIRE[13]) node tail_collisions_hi_lo_lo = cat(tail_collisions_hi_lo_lo_hi, _tail_collisions_WIRE[12]) node tail_collisions_hi_lo_hi_hi = cat(_tail_collisions_WIRE[17], _tail_collisions_WIRE[16]) node tail_collisions_hi_lo_hi = cat(tail_collisions_hi_lo_hi_hi, _tail_collisions_WIRE[15]) node tail_collisions_hi_lo = cat(tail_collisions_hi_lo_hi, tail_collisions_hi_lo_lo) node tail_collisions_hi_hi_lo_hi = cat(_tail_collisions_WIRE[20], _tail_collisions_WIRE[19]) node tail_collisions_hi_hi_lo = cat(tail_collisions_hi_hi_lo_hi, _tail_collisions_WIRE[18]) node tail_collisions_hi_hi_hi_hi = cat(_tail_collisions_WIRE[23], _tail_collisions_WIRE[22]) node tail_collisions_hi_hi_hi = cat(tail_collisions_hi_hi_hi_hi, _tail_collisions_WIRE[21]) node tail_collisions_hi_hi = cat(tail_collisions_hi_hi_hi, tail_collisions_hi_hi_lo) node tail_collisions_hi = cat(tail_collisions_hi_hi, tail_collisions_hi_lo) node _tail_collisions_T_96 = cat(tail_collisions_hi, tail_collisions_lo) node tail_collisions = and(_tail_collisions_T_96, tail) node _slot_will_hit_tail_T = bits(tail_collisions, 2, 0) node _slot_will_hit_tail_T_1 = bits(tail_collisions, 5, 3) node _slot_will_hit_tail_T_2 = bits(tail_collisions, 8, 6) node _slot_will_hit_tail_T_3 = bits(tail_collisions, 11, 9) node _slot_will_hit_tail_T_4 = bits(tail_collisions, 14, 12) node _slot_will_hit_tail_T_5 = bits(tail_collisions, 17, 15) node _slot_will_hit_tail_T_6 = bits(tail_collisions, 20, 18) node _slot_will_hit_tail_T_7 = bits(tail_collisions, 23, 21) node _slot_will_hit_tail_T_8 = or(_slot_will_hit_tail_T, _slot_will_hit_tail_T_1) node _slot_will_hit_tail_T_9 = or(_slot_will_hit_tail_T_8, _slot_will_hit_tail_T_2) node _slot_will_hit_tail_T_10 = or(_slot_will_hit_tail_T_9, _slot_will_hit_tail_T_3) node _slot_will_hit_tail_T_11 = or(_slot_will_hit_tail_T_10, _slot_will_hit_tail_T_4) node _slot_will_hit_tail_T_12 = or(_slot_will_hit_tail_T_11, _slot_will_hit_tail_T_5) node _slot_will_hit_tail_T_13 = or(_slot_will_hit_tail_T_12, _slot_will_hit_tail_T_6) node slot_will_hit_tail = or(_slot_will_hit_tail_T_13, _slot_will_hit_tail_T_7) node will_hit_tail = orr(slot_will_hit_tail) node _do_deq_T = eq(will_hit_tail, UInt<1>(0h0)) node do_deq = and(io.deq.ready, _do_deq_T) node _deq_valids_T = dshl(slot_will_hit_tail, UInt<1>(0h0)) node _deq_valids_T_1 = bits(_deq_valids_T, 2, 0) node _deq_valids_T_2 = dshl(slot_will_hit_tail, UInt<1>(0h1)) node _deq_valids_T_3 = bits(_deq_valids_T_2, 2, 0) node _deq_valids_T_4 = dshl(slot_will_hit_tail, UInt<2>(0h2)) node _deq_valids_T_5 = bits(_deq_valids_T_4, 2, 0) node _deq_valids_T_6 = or(_deq_valids_T_1, _deq_valids_T_3) node _deq_valids_T_7 = or(_deq_valids_T_6, _deq_valids_T_5) node _deq_valids_T_8 = not(_deq_valids_T_7) node deq_valids_0 = bits(_deq_valids_T_8, 0, 0) node deq_valids_1 = bits(_deq_valids_T_8, 1, 1) node deq_valids_2 = bits(_deq_valids_T_8, 2, 2) connect deq_vec[0][0], fb_uop_ram[0] connect deq_vec[0][1], fb_uop_ram[1] connect deq_vec[0][2], fb_uop_ram[2] connect deq_vec[1][0], fb_uop_ram[3] connect deq_vec[1][1], fb_uop_ram[4] connect deq_vec[1][2], fb_uop_ram[5] connect deq_vec[2][0], fb_uop_ram[6] connect deq_vec[2][1], fb_uop_ram[7] connect deq_vec[2][2], fb_uop_ram[8] connect deq_vec[3][0], fb_uop_ram[9] connect deq_vec[3][1], fb_uop_ram[10] connect deq_vec[3][2], fb_uop_ram[11] connect deq_vec[4][0], fb_uop_ram[12] connect deq_vec[4][1], fb_uop_ram[13] connect deq_vec[4][2], fb_uop_ram[14] connect deq_vec[5][0], fb_uop_ram[15] connect deq_vec[5][1], fb_uop_ram[16] connect deq_vec[5][2], fb_uop_ram[17] connect deq_vec[6][0], fb_uop_ram[18] connect deq_vec[6][1], fb_uop_ram[19] connect deq_vec[6][2], fb_uop_ram[20] connect deq_vec[7][0], fb_uop_ram[21] connect deq_vec[7][1], fb_uop_ram[22] connect deq_vec[7][2], fb_uop_ram[23] connect io.deq.bits.uops[0].valid, deq_valids_0 connect io.deq.bits.uops[1].valid, deq_valids_1 connect io.deq.bits.uops[2].valid, deq_valids_2 node _T_608 = bits(head, 0, 0) node _T_609 = bits(head, 1, 1) node _T_610 = bits(head, 2, 2) node _T_611 = bits(head, 3, 3) node _T_612 = bits(head, 4, 4) node _T_613 = bits(head, 5, 5) node _T_614 = bits(head, 6, 6) node _T_615 = bits(head, 7, 7) wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3] wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_616 = mux(_T_608, deq_vec[0][0].debug_tsrc, UInt<1>(0h0)) node _T_617 = mux(_T_609, deq_vec[1][0].debug_tsrc, UInt<1>(0h0)) node _T_618 = mux(_T_610, deq_vec[2][0].debug_tsrc, UInt<1>(0h0)) node _T_619 = mux(_T_611, deq_vec[3][0].debug_tsrc, UInt<1>(0h0)) node _T_620 = mux(_T_612, deq_vec[4][0].debug_tsrc, UInt<1>(0h0)) node _T_621 = mux(_T_613, deq_vec[5][0].debug_tsrc, UInt<1>(0h0)) node _T_622 = mux(_T_614, deq_vec[6][0].debug_tsrc, UInt<1>(0h0)) node _T_623 = mux(_T_615, deq_vec[7][0].debug_tsrc, UInt<1>(0h0)) node _T_624 = or(_T_616, _T_617) node _T_625 = or(_T_624, _T_618) node _T_626 = or(_T_625, _T_619) node _T_627 = or(_T_626, _T_620) node _T_628 = or(_T_627, _T_621) node _T_629 = or(_T_628, _T_622) node _T_630 = or(_T_629, _T_623) wire _WIRE_2 : UInt<3> connect _WIRE_2, _T_630 connect _WIRE_1.debug_tsrc, _WIRE_2 node _T_631 = mux(_T_608, deq_vec[0][0].debug_fsrc, UInt<1>(0h0)) node _T_632 = mux(_T_609, deq_vec[1][0].debug_fsrc, UInt<1>(0h0)) node _T_633 = mux(_T_610, deq_vec[2][0].debug_fsrc, UInt<1>(0h0)) node _T_634 = mux(_T_611, deq_vec[3][0].debug_fsrc, UInt<1>(0h0)) node _T_635 = mux(_T_612, deq_vec[4][0].debug_fsrc, UInt<1>(0h0)) node _T_636 = mux(_T_613, deq_vec[5][0].debug_fsrc, UInt<1>(0h0)) node _T_637 = mux(_T_614, deq_vec[6][0].debug_fsrc, UInt<1>(0h0)) node _T_638 = mux(_T_615, deq_vec[7][0].debug_fsrc, UInt<1>(0h0)) node _T_639 = or(_T_631, _T_632) node _T_640 = or(_T_639, _T_633) node _T_641 = or(_T_640, _T_634) node _T_642 = or(_T_641, _T_635) node _T_643 = or(_T_642, _T_636) node _T_644 = or(_T_643, _T_637) node _T_645 = or(_T_644, _T_638) wire _WIRE_3 : UInt<3> connect _WIRE_3, _T_645 connect _WIRE_1.debug_fsrc, _WIRE_3 node _T_646 = mux(_T_608, deq_vec[0][0].bp_xcpt_if, UInt<1>(0h0)) node _T_647 = mux(_T_609, deq_vec[1][0].bp_xcpt_if, UInt<1>(0h0)) node _T_648 = mux(_T_610, deq_vec[2][0].bp_xcpt_if, UInt<1>(0h0)) node _T_649 = mux(_T_611, deq_vec[3][0].bp_xcpt_if, UInt<1>(0h0)) node _T_650 = mux(_T_612, deq_vec[4][0].bp_xcpt_if, UInt<1>(0h0)) node _T_651 = mux(_T_613, deq_vec[5][0].bp_xcpt_if, UInt<1>(0h0)) node _T_652 = mux(_T_614, deq_vec[6][0].bp_xcpt_if, UInt<1>(0h0)) node _T_653 = mux(_T_615, deq_vec[7][0].bp_xcpt_if, UInt<1>(0h0)) node _T_654 = or(_T_646, _T_647) node _T_655 = or(_T_654, _T_648) node _T_656 = or(_T_655, _T_649) node _T_657 = or(_T_656, _T_650) node _T_658 = or(_T_657, _T_651) node _T_659 = or(_T_658, _T_652) node _T_660 = or(_T_659, _T_653) wire _WIRE_4 : UInt<1> connect _WIRE_4, _T_660 connect _WIRE_1.bp_xcpt_if, _WIRE_4 node _T_661 = mux(_T_608, deq_vec[0][0].bp_debug_if, UInt<1>(0h0)) node _T_662 = mux(_T_609, deq_vec[1][0].bp_debug_if, UInt<1>(0h0)) node _T_663 = mux(_T_610, deq_vec[2][0].bp_debug_if, UInt<1>(0h0)) node _T_664 = mux(_T_611, deq_vec[3][0].bp_debug_if, UInt<1>(0h0)) node _T_665 = mux(_T_612, deq_vec[4][0].bp_debug_if, UInt<1>(0h0)) node _T_666 = mux(_T_613, deq_vec[5][0].bp_debug_if, UInt<1>(0h0)) node _T_667 = mux(_T_614, deq_vec[6][0].bp_debug_if, UInt<1>(0h0)) node _T_668 = mux(_T_615, deq_vec[7][0].bp_debug_if, UInt<1>(0h0)) node _T_669 = or(_T_661, _T_662) node _T_670 = or(_T_669, _T_663) node _T_671 = or(_T_670, _T_664) node _T_672 = or(_T_671, _T_665) node _T_673 = or(_T_672, _T_666) node _T_674 = or(_T_673, _T_667) node _T_675 = or(_T_674, _T_668) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_675 connect _WIRE_1.bp_debug_if, _WIRE_5 node _T_676 = mux(_T_608, deq_vec[0][0].xcpt_ma_if, UInt<1>(0h0)) node _T_677 = mux(_T_609, deq_vec[1][0].xcpt_ma_if, UInt<1>(0h0)) node _T_678 = mux(_T_610, deq_vec[2][0].xcpt_ma_if, UInt<1>(0h0)) node _T_679 = mux(_T_611, deq_vec[3][0].xcpt_ma_if, UInt<1>(0h0)) node _T_680 = mux(_T_612, deq_vec[4][0].xcpt_ma_if, UInt<1>(0h0)) node _T_681 = mux(_T_613, deq_vec[5][0].xcpt_ma_if, UInt<1>(0h0)) node _T_682 = mux(_T_614, deq_vec[6][0].xcpt_ma_if, UInt<1>(0h0)) node _T_683 = mux(_T_615, deq_vec[7][0].xcpt_ma_if, UInt<1>(0h0)) node _T_684 = or(_T_676, _T_677) node _T_685 = or(_T_684, _T_678) node _T_686 = or(_T_685, _T_679) node _T_687 = or(_T_686, _T_680) node _T_688 = or(_T_687, _T_681) node _T_689 = or(_T_688, _T_682) node _T_690 = or(_T_689, _T_683) wire _WIRE_6 : UInt<1> connect _WIRE_6, _T_690 connect _WIRE_1.xcpt_ma_if, _WIRE_6 node _T_691 = mux(_T_608, deq_vec[0][0].xcpt_ae_if, UInt<1>(0h0)) node _T_692 = mux(_T_609, deq_vec[1][0].xcpt_ae_if, UInt<1>(0h0)) node _T_693 = mux(_T_610, deq_vec[2][0].xcpt_ae_if, UInt<1>(0h0)) node _T_694 = mux(_T_611, deq_vec[3][0].xcpt_ae_if, UInt<1>(0h0)) node _T_695 = mux(_T_612, deq_vec[4][0].xcpt_ae_if, UInt<1>(0h0)) node _T_696 = mux(_T_613, deq_vec[5][0].xcpt_ae_if, UInt<1>(0h0)) node _T_697 = mux(_T_614, deq_vec[6][0].xcpt_ae_if, UInt<1>(0h0)) node _T_698 = mux(_T_615, deq_vec[7][0].xcpt_ae_if, UInt<1>(0h0)) node _T_699 = or(_T_691, _T_692) node _T_700 = or(_T_699, _T_693) node _T_701 = or(_T_700, _T_694) node _T_702 = or(_T_701, _T_695) node _T_703 = or(_T_702, _T_696) node _T_704 = or(_T_703, _T_697) node _T_705 = or(_T_704, _T_698) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_705 connect _WIRE_1.xcpt_ae_if, _WIRE_7 node _T_706 = mux(_T_608, deq_vec[0][0].xcpt_pf_if, UInt<1>(0h0)) node _T_707 = mux(_T_609, deq_vec[1][0].xcpt_pf_if, UInt<1>(0h0)) node _T_708 = mux(_T_610, deq_vec[2][0].xcpt_pf_if, UInt<1>(0h0)) node _T_709 = mux(_T_611, deq_vec[3][0].xcpt_pf_if, UInt<1>(0h0)) node _T_710 = mux(_T_612, deq_vec[4][0].xcpt_pf_if, UInt<1>(0h0)) node _T_711 = mux(_T_613, deq_vec[5][0].xcpt_pf_if, UInt<1>(0h0)) node _T_712 = mux(_T_614, deq_vec[6][0].xcpt_pf_if, UInt<1>(0h0)) node _T_713 = mux(_T_615, deq_vec[7][0].xcpt_pf_if, UInt<1>(0h0)) node _T_714 = or(_T_706, _T_707) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = or(_T_717, _T_711) node _T_719 = or(_T_718, _T_712) node _T_720 = or(_T_719, _T_713) wire _WIRE_8 : UInt<1> connect _WIRE_8, _T_720 connect _WIRE_1.xcpt_pf_if, _WIRE_8 node _T_721 = mux(_T_608, deq_vec[0][0].fp_typ, UInt<1>(0h0)) node _T_722 = mux(_T_609, deq_vec[1][0].fp_typ, UInt<1>(0h0)) node _T_723 = mux(_T_610, deq_vec[2][0].fp_typ, UInt<1>(0h0)) node _T_724 = mux(_T_611, deq_vec[3][0].fp_typ, UInt<1>(0h0)) node _T_725 = mux(_T_612, deq_vec[4][0].fp_typ, UInt<1>(0h0)) node _T_726 = mux(_T_613, deq_vec[5][0].fp_typ, UInt<1>(0h0)) node _T_727 = mux(_T_614, deq_vec[6][0].fp_typ, UInt<1>(0h0)) node _T_728 = mux(_T_615, deq_vec[7][0].fp_typ, UInt<1>(0h0)) node _T_729 = or(_T_721, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = or(_T_732, _T_726) node _T_734 = or(_T_733, _T_727) node _T_735 = or(_T_734, _T_728) wire _WIRE_9 : UInt<2> connect _WIRE_9, _T_735 connect _WIRE_1.fp_typ, _WIRE_9 node _T_736 = mux(_T_608, deq_vec[0][0].fp_rm, UInt<1>(0h0)) node _T_737 = mux(_T_609, deq_vec[1][0].fp_rm, UInt<1>(0h0)) node _T_738 = mux(_T_610, deq_vec[2][0].fp_rm, UInt<1>(0h0)) node _T_739 = mux(_T_611, deq_vec[3][0].fp_rm, UInt<1>(0h0)) node _T_740 = mux(_T_612, deq_vec[4][0].fp_rm, UInt<1>(0h0)) node _T_741 = mux(_T_613, deq_vec[5][0].fp_rm, UInt<1>(0h0)) node _T_742 = mux(_T_614, deq_vec[6][0].fp_rm, UInt<1>(0h0)) node _T_743 = mux(_T_615, deq_vec[7][0].fp_rm, UInt<1>(0h0)) node _T_744 = or(_T_736, _T_737) node _T_745 = or(_T_744, _T_738) node _T_746 = or(_T_745, _T_739) node _T_747 = or(_T_746, _T_740) node _T_748 = or(_T_747, _T_741) node _T_749 = or(_T_748, _T_742) node _T_750 = or(_T_749, _T_743) wire _WIRE_10 : UInt<3> connect _WIRE_10, _T_750 connect _WIRE_1.fp_rm, _WIRE_10 node _T_751 = mux(_T_608, deq_vec[0][0].fp_val, UInt<1>(0h0)) node _T_752 = mux(_T_609, deq_vec[1][0].fp_val, UInt<1>(0h0)) node _T_753 = mux(_T_610, deq_vec[2][0].fp_val, UInt<1>(0h0)) node _T_754 = mux(_T_611, deq_vec[3][0].fp_val, UInt<1>(0h0)) node _T_755 = mux(_T_612, deq_vec[4][0].fp_val, UInt<1>(0h0)) node _T_756 = mux(_T_613, deq_vec[5][0].fp_val, UInt<1>(0h0)) node _T_757 = mux(_T_614, deq_vec[6][0].fp_val, UInt<1>(0h0)) node _T_758 = mux(_T_615, deq_vec[7][0].fp_val, UInt<1>(0h0)) node _T_759 = or(_T_751, _T_752) node _T_760 = or(_T_759, _T_753) node _T_761 = or(_T_760, _T_754) node _T_762 = or(_T_761, _T_755) node _T_763 = or(_T_762, _T_756) node _T_764 = or(_T_763, _T_757) node _T_765 = or(_T_764, _T_758) wire _WIRE_11 : UInt<1> connect _WIRE_11, _T_765 connect _WIRE_1.fp_val, _WIRE_11 node _T_766 = mux(_T_608, deq_vec[0][0].fcn_op, UInt<1>(0h0)) node _T_767 = mux(_T_609, deq_vec[1][0].fcn_op, UInt<1>(0h0)) node _T_768 = mux(_T_610, deq_vec[2][0].fcn_op, UInt<1>(0h0)) node _T_769 = mux(_T_611, deq_vec[3][0].fcn_op, UInt<1>(0h0)) node _T_770 = mux(_T_612, deq_vec[4][0].fcn_op, UInt<1>(0h0)) node _T_771 = mux(_T_613, deq_vec[5][0].fcn_op, UInt<1>(0h0)) node _T_772 = mux(_T_614, deq_vec[6][0].fcn_op, UInt<1>(0h0)) node _T_773 = mux(_T_615, deq_vec[7][0].fcn_op, UInt<1>(0h0)) node _T_774 = or(_T_766, _T_767) node _T_775 = or(_T_774, _T_768) node _T_776 = or(_T_775, _T_769) node _T_777 = or(_T_776, _T_770) node _T_778 = or(_T_777, _T_771) node _T_779 = or(_T_778, _T_772) node _T_780 = or(_T_779, _T_773) wire _WIRE_12 : UInt<5> connect _WIRE_12, _T_780 connect _WIRE_1.fcn_op, _WIRE_12 node _T_781 = mux(_T_608, deq_vec[0][0].fcn_dw, UInt<1>(0h0)) node _T_782 = mux(_T_609, deq_vec[1][0].fcn_dw, UInt<1>(0h0)) node _T_783 = mux(_T_610, deq_vec[2][0].fcn_dw, UInt<1>(0h0)) node _T_784 = mux(_T_611, deq_vec[3][0].fcn_dw, UInt<1>(0h0)) node _T_785 = mux(_T_612, deq_vec[4][0].fcn_dw, UInt<1>(0h0)) node _T_786 = mux(_T_613, deq_vec[5][0].fcn_dw, UInt<1>(0h0)) node _T_787 = mux(_T_614, deq_vec[6][0].fcn_dw, UInt<1>(0h0)) node _T_788 = mux(_T_615, deq_vec[7][0].fcn_dw, UInt<1>(0h0)) node _T_789 = or(_T_781, _T_782) node _T_790 = or(_T_789, _T_783) node _T_791 = or(_T_790, _T_784) node _T_792 = or(_T_791, _T_785) node _T_793 = or(_T_792, _T_786) node _T_794 = or(_T_793, _T_787) node _T_795 = or(_T_794, _T_788) wire _WIRE_13 : UInt<1> connect _WIRE_13, _T_795 connect _WIRE_1.fcn_dw, _WIRE_13 node _T_796 = mux(_T_608, deq_vec[0][0].frs3_en, UInt<1>(0h0)) node _T_797 = mux(_T_609, deq_vec[1][0].frs3_en, UInt<1>(0h0)) node _T_798 = mux(_T_610, deq_vec[2][0].frs3_en, UInt<1>(0h0)) node _T_799 = mux(_T_611, deq_vec[3][0].frs3_en, UInt<1>(0h0)) node _T_800 = mux(_T_612, deq_vec[4][0].frs3_en, UInt<1>(0h0)) node _T_801 = mux(_T_613, deq_vec[5][0].frs3_en, UInt<1>(0h0)) node _T_802 = mux(_T_614, deq_vec[6][0].frs3_en, UInt<1>(0h0)) node _T_803 = mux(_T_615, deq_vec[7][0].frs3_en, UInt<1>(0h0)) node _T_804 = or(_T_796, _T_797) node _T_805 = or(_T_804, _T_798) node _T_806 = or(_T_805, _T_799) node _T_807 = or(_T_806, _T_800) node _T_808 = or(_T_807, _T_801) node _T_809 = or(_T_808, _T_802) node _T_810 = or(_T_809, _T_803) wire _WIRE_14 : UInt<1> connect _WIRE_14, _T_810 connect _WIRE_1.frs3_en, _WIRE_14 node _T_811 = mux(_T_608, deq_vec[0][0].lrs2_rtype, UInt<1>(0h0)) node _T_812 = mux(_T_609, deq_vec[1][0].lrs2_rtype, UInt<1>(0h0)) node _T_813 = mux(_T_610, deq_vec[2][0].lrs2_rtype, UInt<1>(0h0)) node _T_814 = mux(_T_611, deq_vec[3][0].lrs2_rtype, UInt<1>(0h0)) node _T_815 = mux(_T_612, deq_vec[4][0].lrs2_rtype, UInt<1>(0h0)) node _T_816 = mux(_T_613, deq_vec[5][0].lrs2_rtype, UInt<1>(0h0)) node _T_817 = mux(_T_614, deq_vec[6][0].lrs2_rtype, UInt<1>(0h0)) node _T_818 = mux(_T_615, deq_vec[7][0].lrs2_rtype, UInt<1>(0h0)) node _T_819 = or(_T_811, _T_812) node _T_820 = or(_T_819, _T_813) node _T_821 = or(_T_820, _T_814) node _T_822 = or(_T_821, _T_815) node _T_823 = or(_T_822, _T_816) node _T_824 = or(_T_823, _T_817) node _T_825 = or(_T_824, _T_818) wire _WIRE_15 : UInt<2> connect _WIRE_15, _T_825 connect _WIRE_1.lrs2_rtype, _WIRE_15 node _T_826 = mux(_T_608, deq_vec[0][0].lrs1_rtype, UInt<1>(0h0)) node _T_827 = mux(_T_609, deq_vec[1][0].lrs1_rtype, UInt<1>(0h0)) node _T_828 = mux(_T_610, deq_vec[2][0].lrs1_rtype, UInt<1>(0h0)) node _T_829 = mux(_T_611, deq_vec[3][0].lrs1_rtype, UInt<1>(0h0)) node _T_830 = mux(_T_612, deq_vec[4][0].lrs1_rtype, UInt<1>(0h0)) node _T_831 = mux(_T_613, deq_vec[5][0].lrs1_rtype, UInt<1>(0h0)) node _T_832 = mux(_T_614, deq_vec[6][0].lrs1_rtype, UInt<1>(0h0)) node _T_833 = mux(_T_615, deq_vec[7][0].lrs1_rtype, UInt<1>(0h0)) node _T_834 = or(_T_826, _T_827) node _T_835 = or(_T_834, _T_828) node _T_836 = or(_T_835, _T_829) node _T_837 = or(_T_836, _T_830) node _T_838 = or(_T_837, _T_831) node _T_839 = or(_T_838, _T_832) node _T_840 = or(_T_839, _T_833) wire _WIRE_16 : UInt<2> connect _WIRE_16, _T_840 connect _WIRE_1.lrs1_rtype, _WIRE_16 node _T_841 = mux(_T_608, deq_vec[0][0].dst_rtype, UInt<1>(0h0)) node _T_842 = mux(_T_609, deq_vec[1][0].dst_rtype, UInt<1>(0h0)) node _T_843 = mux(_T_610, deq_vec[2][0].dst_rtype, UInt<1>(0h0)) node _T_844 = mux(_T_611, deq_vec[3][0].dst_rtype, UInt<1>(0h0)) node _T_845 = mux(_T_612, deq_vec[4][0].dst_rtype, UInt<1>(0h0)) node _T_846 = mux(_T_613, deq_vec[5][0].dst_rtype, UInt<1>(0h0)) node _T_847 = mux(_T_614, deq_vec[6][0].dst_rtype, UInt<1>(0h0)) node _T_848 = mux(_T_615, deq_vec[7][0].dst_rtype, UInt<1>(0h0)) node _T_849 = or(_T_841, _T_842) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = or(_T_853, _T_847) node _T_855 = or(_T_854, _T_848) wire _WIRE_17 : UInt<2> connect _WIRE_17, _T_855 connect _WIRE_1.dst_rtype, _WIRE_17 node _T_856 = mux(_T_608, deq_vec[0][0].lrs3, UInt<1>(0h0)) node _T_857 = mux(_T_609, deq_vec[1][0].lrs3, UInt<1>(0h0)) node _T_858 = mux(_T_610, deq_vec[2][0].lrs3, UInt<1>(0h0)) node _T_859 = mux(_T_611, deq_vec[3][0].lrs3, UInt<1>(0h0)) node _T_860 = mux(_T_612, deq_vec[4][0].lrs3, UInt<1>(0h0)) node _T_861 = mux(_T_613, deq_vec[5][0].lrs3, UInt<1>(0h0)) node _T_862 = mux(_T_614, deq_vec[6][0].lrs3, UInt<1>(0h0)) node _T_863 = mux(_T_615, deq_vec[7][0].lrs3, UInt<1>(0h0)) node _T_864 = or(_T_856, _T_857) node _T_865 = or(_T_864, _T_858) node _T_866 = or(_T_865, _T_859) node _T_867 = or(_T_866, _T_860) node _T_868 = or(_T_867, _T_861) node _T_869 = or(_T_868, _T_862) node _T_870 = or(_T_869, _T_863) wire _WIRE_18 : UInt<6> connect _WIRE_18, _T_870 connect _WIRE_1.lrs3, _WIRE_18 node _T_871 = mux(_T_608, deq_vec[0][0].lrs2, UInt<1>(0h0)) node _T_872 = mux(_T_609, deq_vec[1][0].lrs2, UInt<1>(0h0)) node _T_873 = mux(_T_610, deq_vec[2][0].lrs2, UInt<1>(0h0)) node _T_874 = mux(_T_611, deq_vec[3][0].lrs2, UInt<1>(0h0)) node _T_875 = mux(_T_612, deq_vec[4][0].lrs2, UInt<1>(0h0)) node _T_876 = mux(_T_613, deq_vec[5][0].lrs2, UInt<1>(0h0)) node _T_877 = mux(_T_614, deq_vec[6][0].lrs2, UInt<1>(0h0)) node _T_878 = mux(_T_615, deq_vec[7][0].lrs2, UInt<1>(0h0)) node _T_879 = or(_T_871, _T_872) node _T_880 = or(_T_879, _T_873) node _T_881 = or(_T_880, _T_874) node _T_882 = or(_T_881, _T_875) node _T_883 = or(_T_882, _T_876) node _T_884 = or(_T_883, _T_877) node _T_885 = or(_T_884, _T_878) wire _WIRE_19 : UInt<6> connect _WIRE_19, _T_885 connect _WIRE_1.lrs2, _WIRE_19 node _T_886 = mux(_T_608, deq_vec[0][0].lrs1, UInt<1>(0h0)) node _T_887 = mux(_T_609, deq_vec[1][0].lrs1, UInt<1>(0h0)) node _T_888 = mux(_T_610, deq_vec[2][0].lrs1, UInt<1>(0h0)) node _T_889 = mux(_T_611, deq_vec[3][0].lrs1, UInt<1>(0h0)) node _T_890 = mux(_T_612, deq_vec[4][0].lrs1, UInt<1>(0h0)) node _T_891 = mux(_T_613, deq_vec[5][0].lrs1, UInt<1>(0h0)) node _T_892 = mux(_T_614, deq_vec[6][0].lrs1, UInt<1>(0h0)) node _T_893 = mux(_T_615, deq_vec[7][0].lrs1, UInt<1>(0h0)) node _T_894 = or(_T_886, _T_887) node _T_895 = or(_T_894, _T_888) node _T_896 = or(_T_895, _T_889) node _T_897 = or(_T_896, _T_890) node _T_898 = or(_T_897, _T_891) node _T_899 = or(_T_898, _T_892) node _T_900 = or(_T_899, _T_893) wire _WIRE_20 : UInt<6> connect _WIRE_20, _T_900 connect _WIRE_1.lrs1, _WIRE_20 node _T_901 = mux(_T_608, deq_vec[0][0].ldst, UInt<1>(0h0)) node _T_902 = mux(_T_609, deq_vec[1][0].ldst, UInt<1>(0h0)) node _T_903 = mux(_T_610, deq_vec[2][0].ldst, UInt<1>(0h0)) node _T_904 = mux(_T_611, deq_vec[3][0].ldst, UInt<1>(0h0)) node _T_905 = mux(_T_612, deq_vec[4][0].ldst, UInt<1>(0h0)) node _T_906 = mux(_T_613, deq_vec[5][0].ldst, UInt<1>(0h0)) node _T_907 = mux(_T_614, deq_vec[6][0].ldst, UInt<1>(0h0)) node _T_908 = mux(_T_615, deq_vec[7][0].ldst, UInt<1>(0h0)) node _T_909 = or(_T_901, _T_902) node _T_910 = or(_T_909, _T_903) node _T_911 = or(_T_910, _T_904) node _T_912 = or(_T_911, _T_905) node _T_913 = or(_T_912, _T_906) node _T_914 = or(_T_913, _T_907) node _T_915 = or(_T_914, _T_908) wire _WIRE_21 : UInt<6> connect _WIRE_21, _T_915 connect _WIRE_1.ldst, _WIRE_21 node _T_916 = mux(_T_608, deq_vec[0][0].ldst_is_rs1, UInt<1>(0h0)) node _T_917 = mux(_T_609, deq_vec[1][0].ldst_is_rs1, UInt<1>(0h0)) node _T_918 = mux(_T_610, deq_vec[2][0].ldst_is_rs1, UInt<1>(0h0)) node _T_919 = mux(_T_611, deq_vec[3][0].ldst_is_rs1, UInt<1>(0h0)) node _T_920 = mux(_T_612, deq_vec[4][0].ldst_is_rs1, UInt<1>(0h0)) node _T_921 = mux(_T_613, deq_vec[5][0].ldst_is_rs1, UInt<1>(0h0)) node _T_922 = mux(_T_614, deq_vec[6][0].ldst_is_rs1, UInt<1>(0h0)) node _T_923 = mux(_T_615, deq_vec[7][0].ldst_is_rs1, UInt<1>(0h0)) node _T_924 = or(_T_916, _T_917) node _T_925 = or(_T_924, _T_918) node _T_926 = or(_T_925, _T_919) node _T_927 = or(_T_926, _T_920) node _T_928 = or(_T_927, _T_921) node _T_929 = or(_T_928, _T_922) node _T_930 = or(_T_929, _T_923) wire _WIRE_22 : UInt<1> connect _WIRE_22, _T_930 connect _WIRE_1.ldst_is_rs1, _WIRE_22 node _T_931 = mux(_T_608, deq_vec[0][0].csr_cmd, UInt<1>(0h0)) node _T_932 = mux(_T_609, deq_vec[1][0].csr_cmd, UInt<1>(0h0)) node _T_933 = mux(_T_610, deq_vec[2][0].csr_cmd, UInt<1>(0h0)) node _T_934 = mux(_T_611, deq_vec[3][0].csr_cmd, UInt<1>(0h0)) node _T_935 = mux(_T_612, deq_vec[4][0].csr_cmd, UInt<1>(0h0)) node _T_936 = mux(_T_613, deq_vec[5][0].csr_cmd, UInt<1>(0h0)) node _T_937 = mux(_T_614, deq_vec[6][0].csr_cmd, UInt<1>(0h0)) node _T_938 = mux(_T_615, deq_vec[7][0].csr_cmd, UInt<1>(0h0)) node _T_939 = or(_T_931, _T_932) node _T_940 = or(_T_939, _T_933) node _T_941 = or(_T_940, _T_934) node _T_942 = or(_T_941, _T_935) node _T_943 = or(_T_942, _T_936) node _T_944 = or(_T_943, _T_937) node _T_945 = or(_T_944, _T_938) wire _WIRE_23 : UInt<3> connect _WIRE_23, _T_945 connect _WIRE_1.csr_cmd, _WIRE_23 node _T_946 = mux(_T_608, deq_vec[0][0].flush_on_commit, UInt<1>(0h0)) node _T_947 = mux(_T_609, deq_vec[1][0].flush_on_commit, UInt<1>(0h0)) node _T_948 = mux(_T_610, deq_vec[2][0].flush_on_commit, UInt<1>(0h0)) node _T_949 = mux(_T_611, deq_vec[3][0].flush_on_commit, UInt<1>(0h0)) node _T_950 = mux(_T_612, deq_vec[4][0].flush_on_commit, UInt<1>(0h0)) node _T_951 = mux(_T_613, deq_vec[5][0].flush_on_commit, UInt<1>(0h0)) node _T_952 = mux(_T_614, deq_vec[6][0].flush_on_commit, UInt<1>(0h0)) node _T_953 = mux(_T_615, deq_vec[7][0].flush_on_commit, UInt<1>(0h0)) node _T_954 = or(_T_946, _T_947) node _T_955 = or(_T_954, _T_948) node _T_956 = or(_T_955, _T_949) node _T_957 = or(_T_956, _T_950) node _T_958 = or(_T_957, _T_951) node _T_959 = or(_T_958, _T_952) node _T_960 = or(_T_959, _T_953) wire _WIRE_24 : UInt<1> connect _WIRE_24, _T_960 connect _WIRE_1.flush_on_commit, _WIRE_24 node _T_961 = mux(_T_608, deq_vec[0][0].is_unique, UInt<1>(0h0)) node _T_962 = mux(_T_609, deq_vec[1][0].is_unique, UInt<1>(0h0)) node _T_963 = mux(_T_610, deq_vec[2][0].is_unique, UInt<1>(0h0)) node _T_964 = mux(_T_611, deq_vec[3][0].is_unique, UInt<1>(0h0)) node _T_965 = mux(_T_612, deq_vec[4][0].is_unique, UInt<1>(0h0)) node _T_966 = mux(_T_613, deq_vec[5][0].is_unique, UInt<1>(0h0)) node _T_967 = mux(_T_614, deq_vec[6][0].is_unique, UInt<1>(0h0)) node _T_968 = mux(_T_615, deq_vec[7][0].is_unique, UInt<1>(0h0)) node _T_969 = or(_T_961, _T_962) node _T_970 = or(_T_969, _T_963) node _T_971 = or(_T_970, _T_964) node _T_972 = or(_T_971, _T_965) node _T_973 = or(_T_972, _T_966) node _T_974 = or(_T_973, _T_967) node _T_975 = or(_T_974, _T_968) wire _WIRE_25 : UInt<1> connect _WIRE_25, _T_975 connect _WIRE_1.is_unique, _WIRE_25 node _T_976 = mux(_T_608, deq_vec[0][0].uses_stq, UInt<1>(0h0)) node _T_977 = mux(_T_609, deq_vec[1][0].uses_stq, UInt<1>(0h0)) node _T_978 = mux(_T_610, deq_vec[2][0].uses_stq, UInt<1>(0h0)) node _T_979 = mux(_T_611, deq_vec[3][0].uses_stq, UInt<1>(0h0)) node _T_980 = mux(_T_612, deq_vec[4][0].uses_stq, UInt<1>(0h0)) node _T_981 = mux(_T_613, deq_vec[5][0].uses_stq, UInt<1>(0h0)) node _T_982 = mux(_T_614, deq_vec[6][0].uses_stq, UInt<1>(0h0)) node _T_983 = mux(_T_615, deq_vec[7][0].uses_stq, UInt<1>(0h0)) node _T_984 = or(_T_976, _T_977) node _T_985 = or(_T_984, _T_978) node _T_986 = or(_T_985, _T_979) node _T_987 = or(_T_986, _T_980) node _T_988 = or(_T_987, _T_981) node _T_989 = or(_T_988, _T_982) node _T_990 = or(_T_989, _T_983) wire _WIRE_26 : UInt<1> connect _WIRE_26, _T_990 connect _WIRE_1.uses_stq, _WIRE_26 node _T_991 = mux(_T_608, deq_vec[0][0].uses_ldq, UInt<1>(0h0)) node _T_992 = mux(_T_609, deq_vec[1][0].uses_ldq, UInt<1>(0h0)) node _T_993 = mux(_T_610, deq_vec[2][0].uses_ldq, UInt<1>(0h0)) node _T_994 = mux(_T_611, deq_vec[3][0].uses_ldq, UInt<1>(0h0)) node _T_995 = mux(_T_612, deq_vec[4][0].uses_ldq, UInt<1>(0h0)) node _T_996 = mux(_T_613, deq_vec[5][0].uses_ldq, UInt<1>(0h0)) node _T_997 = mux(_T_614, deq_vec[6][0].uses_ldq, UInt<1>(0h0)) node _T_998 = mux(_T_615, deq_vec[7][0].uses_ldq, UInt<1>(0h0)) node _T_999 = or(_T_991, _T_992) node _T_1000 = or(_T_999, _T_993) node _T_1001 = or(_T_1000, _T_994) node _T_1002 = or(_T_1001, _T_995) node _T_1003 = or(_T_1002, _T_996) node _T_1004 = or(_T_1003, _T_997) node _T_1005 = or(_T_1004, _T_998) wire _WIRE_27 : UInt<1> connect _WIRE_27, _T_1005 connect _WIRE_1.uses_ldq, _WIRE_27 node _T_1006 = mux(_T_608, deq_vec[0][0].mem_signed, UInt<1>(0h0)) node _T_1007 = mux(_T_609, deq_vec[1][0].mem_signed, UInt<1>(0h0)) node _T_1008 = mux(_T_610, deq_vec[2][0].mem_signed, UInt<1>(0h0)) node _T_1009 = mux(_T_611, deq_vec[3][0].mem_signed, UInt<1>(0h0)) node _T_1010 = mux(_T_612, deq_vec[4][0].mem_signed, UInt<1>(0h0)) node _T_1011 = mux(_T_613, deq_vec[5][0].mem_signed, UInt<1>(0h0)) node _T_1012 = mux(_T_614, deq_vec[6][0].mem_signed, UInt<1>(0h0)) node _T_1013 = mux(_T_615, deq_vec[7][0].mem_signed, UInt<1>(0h0)) node _T_1014 = or(_T_1006, _T_1007) node _T_1015 = or(_T_1014, _T_1008) node _T_1016 = or(_T_1015, _T_1009) node _T_1017 = or(_T_1016, _T_1010) node _T_1018 = or(_T_1017, _T_1011) node _T_1019 = or(_T_1018, _T_1012) node _T_1020 = or(_T_1019, _T_1013) wire _WIRE_28 : UInt<1> connect _WIRE_28, _T_1020 connect _WIRE_1.mem_signed, _WIRE_28 node _T_1021 = mux(_T_608, deq_vec[0][0].mem_size, UInt<1>(0h0)) node _T_1022 = mux(_T_609, deq_vec[1][0].mem_size, UInt<1>(0h0)) node _T_1023 = mux(_T_610, deq_vec[2][0].mem_size, UInt<1>(0h0)) node _T_1024 = mux(_T_611, deq_vec[3][0].mem_size, UInt<1>(0h0)) node _T_1025 = mux(_T_612, deq_vec[4][0].mem_size, UInt<1>(0h0)) node _T_1026 = mux(_T_613, deq_vec[5][0].mem_size, UInt<1>(0h0)) node _T_1027 = mux(_T_614, deq_vec[6][0].mem_size, UInt<1>(0h0)) node _T_1028 = mux(_T_615, deq_vec[7][0].mem_size, UInt<1>(0h0)) node _T_1029 = or(_T_1021, _T_1022) node _T_1030 = or(_T_1029, _T_1023) node _T_1031 = or(_T_1030, _T_1024) node _T_1032 = or(_T_1031, _T_1025) node _T_1033 = or(_T_1032, _T_1026) node _T_1034 = or(_T_1033, _T_1027) node _T_1035 = or(_T_1034, _T_1028) wire _WIRE_29 : UInt<2> connect _WIRE_29, _T_1035 connect _WIRE_1.mem_size, _WIRE_29 node _T_1036 = mux(_T_608, deq_vec[0][0].mem_cmd, UInt<1>(0h0)) node _T_1037 = mux(_T_609, deq_vec[1][0].mem_cmd, UInt<1>(0h0)) node _T_1038 = mux(_T_610, deq_vec[2][0].mem_cmd, UInt<1>(0h0)) node _T_1039 = mux(_T_611, deq_vec[3][0].mem_cmd, UInt<1>(0h0)) node _T_1040 = mux(_T_612, deq_vec[4][0].mem_cmd, UInt<1>(0h0)) node _T_1041 = mux(_T_613, deq_vec[5][0].mem_cmd, UInt<1>(0h0)) node _T_1042 = mux(_T_614, deq_vec[6][0].mem_cmd, UInt<1>(0h0)) node _T_1043 = mux(_T_615, deq_vec[7][0].mem_cmd, UInt<1>(0h0)) node _T_1044 = or(_T_1036, _T_1037) node _T_1045 = or(_T_1044, _T_1038) node _T_1046 = or(_T_1045, _T_1039) node _T_1047 = or(_T_1046, _T_1040) node _T_1048 = or(_T_1047, _T_1041) node _T_1049 = or(_T_1048, _T_1042) node _T_1050 = or(_T_1049, _T_1043) wire _WIRE_30 : UInt<5> connect _WIRE_30, _T_1050 connect _WIRE_1.mem_cmd, _WIRE_30 node _T_1051 = mux(_T_608, deq_vec[0][0].exc_cause, UInt<1>(0h0)) node _T_1052 = mux(_T_609, deq_vec[1][0].exc_cause, UInt<1>(0h0)) node _T_1053 = mux(_T_610, deq_vec[2][0].exc_cause, UInt<1>(0h0)) node _T_1054 = mux(_T_611, deq_vec[3][0].exc_cause, UInt<1>(0h0)) node _T_1055 = mux(_T_612, deq_vec[4][0].exc_cause, UInt<1>(0h0)) node _T_1056 = mux(_T_613, deq_vec[5][0].exc_cause, UInt<1>(0h0)) node _T_1057 = mux(_T_614, deq_vec[6][0].exc_cause, UInt<1>(0h0)) node _T_1058 = mux(_T_615, deq_vec[7][0].exc_cause, UInt<1>(0h0)) node _T_1059 = or(_T_1051, _T_1052) node _T_1060 = or(_T_1059, _T_1053) node _T_1061 = or(_T_1060, _T_1054) node _T_1062 = or(_T_1061, _T_1055) node _T_1063 = or(_T_1062, _T_1056) node _T_1064 = or(_T_1063, _T_1057) node _T_1065 = or(_T_1064, _T_1058) wire _WIRE_31 : UInt<64> connect _WIRE_31, _T_1065 connect _WIRE_1.exc_cause, _WIRE_31 node _T_1066 = mux(_T_608, deq_vec[0][0].exception, UInt<1>(0h0)) node _T_1067 = mux(_T_609, deq_vec[1][0].exception, UInt<1>(0h0)) node _T_1068 = mux(_T_610, deq_vec[2][0].exception, UInt<1>(0h0)) node _T_1069 = mux(_T_611, deq_vec[3][0].exception, UInt<1>(0h0)) node _T_1070 = mux(_T_612, deq_vec[4][0].exception, UInt<1>(0h0)) node _T_1071 = mux(_T_613, deq_vec[5][0].exception, UInt<1>(0h0)) node _T_1072 = mux(_T_614, deq_vec[6][0].exception, UInt<1>(0h0)) node _T_1073 = mux(_T_615, deq_vec[7][0].exception, UInt<1>(0h0)) node _T_1074 = or(_T_1066, _T_1067) node _T_1075 = or(_T_1074, _T_1068) node _T_1076 = or(_T_1075, _T_1069) node _T_1077 = or(_T_1076, _T_1070) node _T_1078 = or(_T_1077, _T_1071) node _T_1079 = or(_T_1078, _T_1072) node _T_1080 = or(_T_1079, _T_1073) wire _WIRE_32 : UInt<1> connect _WIRE_32, _T_1080 connect _WIRE_1.exception, _WIRE_32 node _T_1081 = mux(_T_608, deq_vec[0][0].stale_pdst, UInt<1>(0h0)) node _T_1082 = mux(_T_609, deq_vec[1][0].stale_pdst, UInt<1>(0h0)) node _T_1083 = mux(_T_610, deq_vec[2][0].stale_pdst, UInt<1>(0h0)) node _T_1084 = mux(_T_611, deq_vec[3][0].stale_pdst, UInt<1>(0h0)) node _T_1085 = mux(_T_612, deq_vec[4][0].stale_pdst, UInt<1>(0h0)) node _T_1086 = mux(_T_613, deq_vec[5][0].stale_pdst, UInt<1>(0h0)) node _T_1087 = mux(_T_614, deq_vec[6][0].stale_pdst, UInt<1>(0h0)) node _T_1088 = mux(_T_615, deq_vec[7][0].stale_pdst, UInt<1>(0h0)) node _T_1089 = or(_T_1081, _T_1082) node _T_1090 = or(_T_1089, _T_1083) node _T_1091 = or(_T_1090, _T_1084) node _T_1092 = or(_T_1091, _T_1085) node _T_1093 = or(_T_1092, _T_1086) node _T_1094 = or(_T_1093, _T_1087) node _T_1095 = or(_T_1094, _T_1088) wire _WIRE_33 : UInt<7> connect _WIRE_33, _T_1095 connect _WIRE_1.stale_pdst, _WIRE_33 node _T_1096 = mux(_T_608, deq_vec[0][0].ppred_busy, UInt<1>(0h0)) node _T_1097 = mux(_T_609, deq_vec[1][0].ppred_busy, UInt<1>(0h0)) node _T_1098 = mux(_T_610, deq_vec[2][0].ppred_busy, UInt<1>(0h0)) node _T_1099 = mux(_T_611, deq_vec[3][0].ppred_busy, UInt<1>(0h0)) node _T_1100 = mux(_T_612, deq_vec[4][0].ppred_busy, UInt<1>(0h0)) node _T_1101 = mux(_T_613, deq_vec[5][0].ppred_busy, UInt<1>(0h0)) node _T_1102 = mux(_T_614, deq_vec[6][0].ppred_busy, UInt<1>(0h0)) node _T_1103 = mux(_T_615, deq_vec[7][0].ppred_busy, UInt<1>(0h0)) node _T_1104 = or(_T_1096, _T_1097) node _T_1105 = or(_T_1104, _T_1098) node _T_1106 = or(_T_1105, _T_1099) node _T_1107 = or(_T_1106, _T_1100) node _T_1108 = or(_T_1107, _T_1101) node _T_1109 = or(_T_1108, _T_1102) node _T_1110 = or(_T_1109, _T_1103) wire _WIRE_34 : UInt<1> connect _WIRE_34, _T_1110 connect _WIRE_1.ppred_busy, _WIRE_34 node _T_1111 = mux(_T_608, deq_vec[0][0].prs3_busy, UInt<1>(0h0)) node _T_1112 = mux(_T_609, deq_vec[1][0].prs3_busy, UInt<1>(0h0)) node _T_1113 = mux(_T_610, deq_vec[2][0].prs3_busy, UInt<1>(0h0)) node _T_1114 = mux(_T_611, deq_vec[3][0].prs3_busy, UInt<1>(0h0)) node _T_1115 = mux(_T_612, deq_vec[4][0].prs3_busy, UInt<1>(0h0)) node _T_1116 = mux(_T_613, deq_vec[5][0].prs3_busy, UInt<1>(0h0)) node _T_1117 = mux(_T_614, deq_vec[6][0].prs3_busy, UInt<1>(0h0)) node _T_1118 = mux(_T_615, deq_vec[7][0].prs3_busy, UInt<1>(0h0)) node _T_1119 = or(_T_1111, _T_1112) node _T_1120 = or(_T_1119, _T_1113) node _T_1121 = or(_T_1120, _T_1114) node _T_1122 = or(_T_1121, _T_1115) node _T_1123 = or(_T_1122, _T_1116) node _T_1124 = or(_T_1123, _T_1117) node _T_1125 = or(_T_1124, _T_1118) wire _WIRE_35 : UInt<1> connect _WIRE_35, _T_1125 connect _WIRE_1.prs3_busy, _WIRE_35 node _T_1126 = mux(_T_608, deq_vec[0][0].prs2_busy, UInt<1>(0h0)) node _T_1127 = mux(_T_609, deq_vec[1][0].prs2_busy, UInt<1>(0h0)) node _T_1128 = mux(_T_610, deq_vec[2][0].prs2_busy, UInt<1>(0h0)) node _T_1129 = mux(_T_611, deq_vec[3][0].prs2_busy, UInt<1>(0h0)) node _T_1130 = mux(_T_612, deq_vec[4][0].prs2_busy, UInt<1>(0h0)) node _T_1131 = mux(_T_613, deq_vec[5][0].prs2_busy, UInt<1>(0h0)) node _T_1132 = mux(_T_614, deq_vec[6][0].prs2_busy, UInt<1>(0h0)) node _T_1133 = mux(_T_615, deq_vec[7][0].prs2_busy, UInt<1>(0h0)) node _T_1134 = or(_T_1126, _T_1127) node _T_1135 = or(_T_1134, _T_1128) node _T_1136 = or(_T_1135, _T_1129) node _T_1137 = or(_T_1136, _T_1130) node _T_1138 = or(_T_1137, _T_1131) node _T_1139 = or(_T_1138, _T_1132) node _T_1140 = or(_T_1139, _T_1133) wire _WIRE_36 : UInt<1> connect _WIRE_36, _T_1140 connect _WIRE_1.prs2_busy, _WIRE_36 node _T_1141 = mux(_T_608, deq_vec[0][0].prs1_busy, UInt<1>(0h0)) node _T_1142 = mux(_T_609, deq_vec[1][0].prs1_busy, UInt<1>(0h0)) node _T_1143 = mux(_T_610, deq_vec[2][0].prs1_busy, UInt<1>(0h0)) node _T_1144 = mux(_T_611, deq_vec[3][0].prs1_busy, UInt<1>(0h0)) node _T_1145 = mux(_T_612, deq_vec[4][0].prs1_busy, UInt<1>(0h0)) node _T_1146 = mux(_T_613, deq_vec[5][0].prs1_busy, UInt<1>(0h0)) node _T_1147 = mux(_T_614, deq_vec[6][0].prs1_busy, UInt<1>(0h0)) node _T_1148 = mux(_T_615, deq_vec[7][0].prs1_busy, UInt<1>(0h0)) node _T_1149 = or(_T_1141, _T_1142) node _T_1150 = or(_T_1149, _T_1143) node _T_1151 = or(_T_1150, _T_1144) node _T_1152 = or(_T_1151, _T_1145) node _T_1153 = or(_T_1152, _T_1146) node _T_1154 = or(_T_1153, _T_1147) node _T_1155 = or(_T_1154, _T_1148) wire _WIRE_37 : UInt<1> connect _WIRE_37, _T_1155 connect _WIRE_1.prs1_busy, _WIRE_37 node _T_1156 = mux(_T_608, deq_vec[0][0].ppred, UInt<1>(0h0)) node _T_1157 = mux(_T_609, deq_vec[1][0].ppred, UInt<1>(0h0)) node _T_1158 = mux(_T_610, deq_vec[2][0].ppred, UInt<1>(0h0)) node _T_1159 = mux(_T_611, deq_vec[3][0].ppred, UInt<1>(0h0)) node _T_1160 = mux(_T_612, deq_vec[4][0].ppred, UInt<1>(0h0)) node _T_1161 = mux(_T_613, deq_vec[5][0].ppred, UInt<1>(0h0)) node _T_1162 = mux(_T_614, deq_vec[6][0].ppred, UInt<1>(0h0)) node _T_1163 = mux(_T_615, deq_vec[7][0].ppred, UInt<1>(0h0)) node _T_1164 = or(_T_1156, _T_1157) node _T_1165 = or(_T_1164, _T_1158) node _T_1166 = or(_T_1165, _T_1159) node _T_1167 = or(_T_1166, _T_1160) node _T_1168 = or(_T_1167, _T_1161) node _T_1169 = or(_T_1168, _T_1162) node _T_1170 = or(_T_1169, _T_1163) wire _WIRE_38 : UInt<5> connect _WIRE_38, _T_1170 connect _WIRE_1.ppred, _WIRE_38 node _T_1171 = mux(_T_608, deq_vec[0][0].prs3, UInt<1>(0h0)) node _T_1172 = mux(_T_609, deq_vec[1][0].prs3, UInt<1>(0h0)) node _T_1173 = mux(_T_610, deq_vec[2][0].prs3, UInt<1>(0h0)) node _T_1174 = mux(_T_611, deq_vec[3][0].prs3, UInt<1>(0h0)) node _T_1175 = mux(_T_612, deq_vec[4][0].prs3, UInt<1>(0h0)) node _T_1176 = mux(_T_613, deq_vec[5][0].prs3, UInt<1>(0h0)) node _T_1177 = mux(_T_614, deq_vec[6][0].prs3, UInt<1>(0h0)) node _T_1178 = mux(_T_615, deq_vec[7][0].prs3, UInt<1>(0h0)) node _T_1179 = or(_T_1171, _T_1172) node _T_1180 = or(_T_1179, _T_1173) node _T_1181 = or(_T_1180, _T_1174) node _T_1182 = or(_T_1181, _T_1175) node _T_1183 = or(_T_1182, _T_1176) node _T_1184 = or(_T_1183, _T_1177) node _T_1185 = or(_T_1184, _T_1178) wire _WIRE_39 : UInt<7> connect _WIRE_39, _T_1185 connect _WIRE_1.prs3, _WIRE_39 node _T_1186 = mux(_T_608, deq_vec[0][0].prs2, UInt<1>(0h0)) node _T_1187 = mux(_T_609, deq_vec[1][0].prs2, UInt<1>(0h0)) node _T_1188 = mux(_T_610, deq_vec[2][0].prs2, UInt<1>(0h0)) node _T_1189 = mux(_T_611, deq_vec[3][0].prs2, UInt<1>(0h0)) node _T_1190 = mux(_T_612, deq_vec[4][0].prs2, UInt<1>(0h0)) node _T_1191 = mux(_T_613, deq_vec[5][0].prs2, UInt<1>(0h0)) node _T_1192 = mux(_T_614, deq_vec[6][0].prs2, UInt<1>(0h0)) node _T_1193 = mux(_T_615, deq_vec[7][0].prs2, UInt<1>(0h0)) node _T_1194 = or(_T_1186, _T_1187) node _T_1195 = or(_T_1194, _T_1188) node _T_1196 = or(_T_1195, _T_1189) node _T_1197 = or(_T_1196, _T_1190) node _T_1198 = or(_T_1197, _T_1191) node _T_1199 = or(_T_1198, _T_1192) node _T_1200 = or(_T_1199, _T_1193) wire _WIRE_40 : UInt<7> connect _WIRE_40, _T_1200 connect _WIRE_1.prs2, _WIRE_40 node _T_1201 = mux(_T_608, deq_vec[0][0].prs1, UInt<1>(0h0)) node _T_1202 = mux(_T_609, deq_vec[1][0].prs1, UInt<1>(0h0)) node _T_1203 = mux(_T_610, deq_vec[2][0].prs1, UInt<1>(0h0)) node _T_1204 = mux(_T_611, deq_vec[3][0].prs1, UInt<1>(0h0)) node _T_1205 = mux(_T_612, deq_vec[4][0].prs1, UInt<1>(0h0)) node _T_1206 = mux(_T_613, deq_vec[5][0].prs1, UInt<1>(0h0)) node _T_1207 = mux(_T_614, deq_vec[6][0].prs1, UInt<1>(0h0)) node _T_1208 = mux(_T_615, deq_vec[7][0].prs1, UInt<1>(0h0)) node _T_1209 = or(_T_1201, _T_1202) node _T_1210 = or(_T_1209, _T_1203) node _T_1211 = or(_T_1210, _T_1204) node _T_1212 = or(_T_1211, _T_1205) node _T_1213 = or(_T_1212, _T_1206) node _T_1214 = or(_T_1213, _T_1207) node _T_1215 = or(_T_1214, _T_1208) wire _WIRE_41 : UInt<7> connect _WIRE_41, _T_1215 connect _WIRE_1.prs1, _WIRE_41 node _T_1216 = mux(_T_608, deq_vec[0][0].pdst, UInt<1>(0h0)) node _T_1217 = mux(_T_609, deq_vec[1][0].pdst, UInt<1>(0h0)) node _T_1218 = mux(_T_610, deq_vec[2][0].pdst, UInt<1>(0h0)) node _T_1219 = mux(_T_611, deq_vec[3][0].pdst, UInt<1>(0h0)) node _T_1220 = mux(_T_612, deq_vec[4][0].pdst, UInt<1>(0h0)) node _T_1221 = mux(_T_613, deq_vec[5][0].pdst, UInt<1>(0h0)) node _T_1222 = mux(_T_614, deq_vec[6][0].pdst, UInt<1>(0h0)) node _T_1223 = mux(_T_615, deq_vec[7][0].pdst, UInt<1>(0h0)) node _T_1224 = or(_T_1216, _T_1217) node _T_1225 = or(_T_1224, _T_1218) node _T_1226 = or(_T_1225, _T_1219) node _T_1227 = or(_T_1226, _T_1220) node _T_1228 = or(_T_1227, _T_1221) node _T_1229 = or(_T_1228, _T_1222) node _T_1230 = or(_T_1229, _T_1223) wire _WIRE_42 : UInt<7> connect _WIRE_42, _T_1230 connect _WIRE_1.pdst, _WIRE_42 node _T_1231 = mux(_T_608, deq_vec[0][0].rxq_idx, UInt<1>(0h0)) node _T_1232 = mux(_T_609, deq_vec[1][0].rxq_idx, UInt<1>(0h0)) node _T_1233 = mux(_T_610, deq_vec[2][0].rxq_idx, UInt<1>(0h0)) node _T_1234 = mux(_T_611, deq_vec[3][0].rxq_idx, UInt<1>(0h0)) node _T_1235 = mux(_T_612, deq_vec[4][0].rxq_idx, UInt<1>(0h0)) node _T_1236 = mux(_T_613, deq_vec[5][0].rxq_idx, UInt<1>(0h0)) node _T_1237 = mux(_T_614, deq_vec[6][0].rxq_idx, UInt<1>(0h0)) node _T_1238 = mux(_T_615, deq_vec[7][0].rxq_idx, UInt<1>(0h0)) node _T_1239 = or(_T_1231, _T_1232) node _T_1240 = or(_T_1239, _T_1233) node _T_1241 = or(_T_1240, _T_1234) node _T_1242 = or(_T_1241, _T_1235) node _T_1243 = or(_T_1242, _T_1236) node _T_1244 = or(_T_1243, _T_1237) node _T_1245 = or(_T_1244, _T_1238) wire _WIRE_43 : UInt<2> connect _WIRE_43, _T_1245 connect _WIRE_1.rxq_idx, _WIRE_43 node _T_1246 = mux(_T_608, deq_vec[0][0].stq_idx, UInt<1>(0h0)) node _T_1247 = mux(_T_609, deq_vec[1][0].stq_idx, UInt<1>(0h0)) node _T_1248 = mux(_T_610, deq_vec[2][0].stq_idx, UInt<1>(0h0)) node _T_1249 = mux(_T_611, deq_vec[3][0].stq_idx, UInt<1>(0h0)) node _T_1250 = mux(_T_612, deq_vec[4][0].stq_idx, UInt<1>(0h0)) node _T_1251 = mux(_T_613, deq_vec[5][0].stq_idx, UInt<1>(0h0)) node _T_1252 = mux(_T_614, deq_vec[6][0].stq_idx, UInt<1>(0h0)) node _T_1253 = mux(_T_615, deq_vec[7][0].stq_idx, UInt<1>(0h0)) node _T_1254 = or(_T_1246, _T_1247) node _T_1255 = or(_T_1254, _T_1248) node _T_1256 = or(_T_1255, _T_1249) node _T_1257 = or(_T_1256, _T_1250) node _T_1258 = or(_T_1257, _T_1251) node _T_1259 = or(_T_1258, _T_1252) node _T_1260 = or(_T_1259, _T_1253) wire _WIRE_44 : UInt<5> connect _WIRE_44, _T_1260 connect _WIRE_1.stq_idx, _WIRE_44 node _T_1261 = mux(_T_608, deq_vec[0][0].ldq_idx, UInt<1>(0h0)) node _T_1262 = mux(_T_609, deq_vec[1][0].ldq_idx, UInt<1>(0h0)) node _T_1263 = mux(_T_610, deq_vec[2][0].ldq_idx, UInt<1>(0h0)) node _T_1264 = mux(_T_611, deq_vec[3][0].ldq_idx, UInt<1>(0h0)) node _T_1265 = mux(_T_612, deq_vec[4][0].ldq_idx, UInt<1>(0h0)) node _T_1266 = mux(_T_613, deq_vec[5][0].ldq_idx, UInt<1>(0h0)) node _T_1267 = mux(_T_614, deq_vec[6][0].ldq_idx, UInt<1>(0h0)) node _T_1268 = mux(_T_615, deq_vec[7][0].ldq_idx, UInt<1>(0h0)) node _T_1269 = or(_T_1261, _T_1262) node _T_1270 = or(_T_1269, _T_1263) node _T_1271 = or(_T_1270, _T_1264) node _T_1272 = or(_T_1271, _T_1265) node _T_1273 = or(_T_1272, _T_1266) node _T_1274 = or(_T_1273, _T_1267) node _T_1275 = or(_T_1274, _T_1268) wire _WIRE_45 : UInt<5> connect _WIRE_45, _T_1275 connect _WIRE_1.ldq_idx, _WIRE_45 node _T_1276 = mux(_T_608, deq_vec[0][0].rob_idx, UInt<1>(0h0)) node _T_1277 = mux(_T_609, deq_vec[1][0].rob_idx, UInt<1>(0h0)) node _T_1278 = mux(_T_610, deq_vec[2][0].rob_idx, UInt<1>(0h0)) node _T_1279 = mux(_T_611, deq_vec[3][0].rob_idx, UInt<1>(0h0)) node _T_1280 = mux(_T_612, deq_vec[4][0].rob_idx, UInt<1>(0h0)) node _T_1281 = mux(_T_613, deq_vec[5][0].rob_idx, UInt<1>(0h0)) node _T_1282 = mux(_T_614, deq_vec[6][0].rob_idx, UInt<1>(0h0)) node _T_1283 = mux(_T_615, deq_vec[7][0].rob_idx, UInt<1>(0h0)) node _T_1284 = or(_T_1276, _T_1277) node _T_1285 = or(_T_1284, _T_1278) node _T_1286 = or(_T_1285, _T_1279) node _T_1287 = or(_T_1286, _T_1280) node _T_1288 = or(_T_1287, _T_1281) node _T_1289 = or(_T_1288, _T_1282) node _T_1290 = or(_T_1289, _T_1283) wire _WIRE_46 : UInt<7> connect _WIRE_46, _T_1290 connect _WIRE_1.rob_idx, _WIRE_46 wire _WIRE_47 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_1291 = mux(_T_608, deq_vec[0][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1292 = mux(_T_609, deq_vec[1][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1293 = mux(_T_610, deq_vec[2][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1294 = mux(_T_611, deq_vec[3][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1295 = mux(_T_612, deq_vec[4][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1296 = mux(_T_613, deq_vec[5][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1297 = mux(_T_614, deq_vec[6][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1298 = mux(_T_615, deq_vec[7][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_1299 = or(_T_1291, _T_1292) node _T_1300 = or(_T_1299, _T_1293) node _T_1301 = or(_T_1300, _T_1294) node _T_1302 = or(_T_1301, _T_1295) node _T_1303 = or(_T_1302, _T_1296) node _T_1304 = or(_T_1303, _T_1297) node _T_1305 = or(_T_1304, _T_1298) wire _WIRE_48 : UInt<1> connect _WIRE_48, _T_1305 connect _WIRE_47.vec, _WIRE_48 node _T_1306 = mux(_T_608, deq_vec[0][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1307 = mux(_T_609, deq_vec[1][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1308 = mux(_T_610, deq_vec[2][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1309 = mux(_T_611, deq_vec[3][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1310 = mux(_T_612, deq_vec[4][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1311 = mux(_T_613, deq_vec[5][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1312 = mux(_T_614, deq_vec[6][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1313 = mux(_T_615, deq_vec[7][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_1314 = or(_T_1306, _T_1307) node _T_1315 = or(_T_1314, _T_1308) node _T_1316 = or(_T_1315, _T_1309) node _T_1317 = or(_T_1316, _T_1310) node _T_1318 = or(_T_1317, _T_1311) node _T_1319 = or(_T_1318, _T_1312) node _T_1320 = or(_T_1319, _T_1313) wire _WIRE_49 : UInt<1> connect _WIRE_49, _T_1320 connect _WIRE_47.wflags, _WIRE_49 node _T_1321 = mux(_T_608, deq_vec[0][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1322 = mux(_T_609, deq_vec[1][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1323 = mux(_T_610, deq_vec[2][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1324 = mux(_T_611, deq_vec[3][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1325 = mux(_T_612, deq_vec[4][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1326 = mux(_T_613, deq_vec[5][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1327 = mux(_T_614, deq_vec[6][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1328 = mux(_T_615, deq_vec[7][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_1329 = or(_T_1321, _T_1322) node _T_1330 = or(_T_1329, _T_1323) node _T_1331 = or(_T_1330, _T_1324) node _T_1332 = or(_T_1331, _T_1325) node _T_1333 = or(_T_1332, _T_1326) node _T_1334 = or(_T_1333, _T_1327) node _T_1335 = or(_T_1334, _T_1328) wire _WIRE_50 : UInt<1> connect _WIRE_50, _T_1335 connect _WIRE_47.sqrt, _WIRE_50 node _T_1336 = mux(_T_608, deq_vec[0][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1337 = mux(_T_609, deq_vec[1][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1338 = mux(_T_610, deq_vec[2][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1339 = mux(_T_611, deq_vec[3][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1340 = mux(_T_612, deq_vec[4][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1341 = mux(_T_613, deq_vec[5][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1342 = mux(_T_614, deq_vec[6][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1343 = mux(_T_615, deq_vec[7][0].fp_ctrl.div, UInt<1>(0h0)) node _T_1344 = or(_T_1336, _T_1337) node _T_1345 = or(_T_1344, _T_1338) node _T_1346 = or(_T_1345, _T_1339) node _T_1347 = or(_T_1346, _T_1340) node _T_1348 = or(_T_1347, _T_1341) node _T_1349 = or(_T_1348, _T_1342) node _T_1350 = or(_T_1349, _T_1343) wire _WIRE_51 : UInt<1> connect _WIRE_51, _T_1350 connect _WIRE_47.div, _WIRE_51 node _T_1351 = mux(_T_608, deq_vec[0][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1352 = mux(_T_609, deq_vec[1][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1353 = mux(_T_610, deq_vec[2][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1354 = mux(_T_611, deq_vec[3][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1355 = mux(_T_612, deq_vec[4][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1356 = mux(_T_613, deq_vec[5][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1357 = mux(_T_614, deq_vec[6][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1358 = mux(_T_615, deq_vec[7][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_1359 = or(_T_1351, _T_1352) node _T_1360 = or(_T_1359, _T_1353) node _T_1361 = or(_T_1360, _T_1354) node _T_1362 = or(_T_1361, _T_1355) node _T_1363 = or(_T_1362, _T_1356) node _T_1364 = or(_T_1363, _T_1357) node _T_1365 = or(_T_1364, _T_1358) wire _WIRE_52 : UInt<1> connect _WIRE_52, _T_1365 connect _WIRE_47.fma, _WIRE_52 node _T_1366 = mux(_T_608, deq_vec[0][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1367 = mux(_T_609, deq_vec[1][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1368 = mux(_T_610, deq_vec[2][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1369 = mux(_T_611, deq_vec[3][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1370 = mux(_T_612, deq_vec[4][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1371 = mux(_T_613, deq_vec[5][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1372 = mux(_T_614, deq_vec[6][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1373 = mux(_T_615, deq_vec[7][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_1374 = or(_T_1366, _T_1367) node _T_1375 = or(_T_1374, _T_1368) node _T_1376 = or(_T_1375, _T_1369) node _T_1377 = or(_T_1376, _T_1370) node _T_1378 = or(_T_1377, _T_1371) node _T_1379 = or(_T_1378, _T_1372) node _T_1380 = or(_T_1379, _T_1373) wire _WIRE_53 : UInt<1> connect _WIRE_53, _T_1380 connect _WIRE_47.fastpipe, _WIRE_53 node _T_1381 = mux(_T_608, deq_vec[0][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1382 = mux(_T_609, deq_vec[1][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1383 = mux(_T_610, deq_vec[2][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1384 = mux(_T_611, deq_vec[3][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1385 = mux(_T_612, deq_vec[4][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1386 = mux(_T_613, deq_vec[5][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1387 = mux(_T_614, deq_vec[6][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1388 = mux(_T_615, deq_vec[7][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_1389 = or(_T_1381, _T_1382) node _T_1390 = or(_T_1389, _T_1383) node _T_1391 = or(_T_1390, _T_1384) node _T_1392 = or(_T_1391, _T_1385) node _T_1393 = or(_T_1392, _T_1386) node _T_1394 = or(_T_1393, _T_1387) node _T_1395 = or(_T_1394, _T_1388) wire _WIRE_54 : UInt<1> connect _WIRE_54, _T_1395 connect _WIRE_47.toint, _WIRE_54 node _T_1396 = mux(_T_608, deq_vec[0][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1397 = mux(_T_609, deq_vec[1][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1398 = mux(_T_610, deq_vec[2][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1399 = mux(_T_611, deq_vec[3][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1400 = mux(_T_612, deq_vec[4][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1401 = mux(_T_613, deq_vec[5][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1402 = mux(_T_614, deq_vec[6][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1403 = mux(_T_615, deq_vec[7][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1404 = or(_T_1396, _T_1397) node _T_1405 = or(_T_1404, _T_1398) node _T_1406 = or(_T_1405, _T_1399) node _T_1407 = or(_T_1406, _T_1400) node _T_1408 = or(_T_1407, _T_1401) node _T_1409 = or(_T_1408, _T_1402) node _T_1410 = or(_T_1409, _T_1403) wire _WIRE_55 : UInt<1> connect _WIRE_55, _T_1410 connect _WIRE_47.fromint, _WIRE_55 node _T_1411 = mux(_T_608, deq_vec[0][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1412 = mux(_T_609, deq_vec[1][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1413 = mux(_T_610, deq_vec[2][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1414 = mux(_T_611, deq_vec[3][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1415 = mux(_T_612, deq_vec[4][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1416 = mux(_T_613, deq_vec[5][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1417 = mux(_T_614, deq_vec[6][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1418 = mux(_T_615, deq_vec[7][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1419 = or(_T_1411, _T_1412) node _T_1420 = or(_T_1419, _T_1413) node _T_1421 = or(_T_1420, _T_1414) node _T_1422 = or(_T_1421, _T_1415) node _T_1423 = or(_T_1422, _T_1416) node _T_1424 = or(_T_1423, _T_1417) node _T_1425 = or(_T_1424, _T_1418) wire _WIRE_56 : UInt<2> connect _WIRE_56, _T_1425 connect _WIRE_47.typeTagOut, _WIRE_56 node _T_1426 = mux(_T_608, deq_vec[0][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1427 = mux(_T_609, deq_vec[1][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1428 = mux(_T_610, deq_vec[2][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1429 = mux(_T_611, deq_vec[3][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1430 = mux(_T_612, deq_vec[4][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1431 = mux(_T_613, deq_vec[5][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1432 = mux(_T_614, deq_vec[6][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1433 = mux(_T_615, deq_vec[7][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1434 = or(_T_1426, _T_1427) node _T_1435 = or(_T_1434, _T_1428) node _T_1436 = or(_T_1435, _T_1429) node _T_1437 = or(_T_1436, _T_1430) node _T_1438 = or(_T_1437, _T_1431) node _T_1439 = or(_T_1438, _T_1432) node _T_1440 = or(_T_1439, _T_1433) wire _WIRE_57 : UInt<2> connect _WIRE_57, _T_1440 connect _WIRE_47.typeTagIn, _WIRE_57 node _T_1441 = mux(_T_608, deq_vec[0][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1442 = mux(_T_609, deq_vec[1][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1443 = mux(_T_610, deq_vec[2][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1444 = mux(_T_611, deq_vec[3][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1445 = mux(_T_612, deq_vec[4][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1446 = mux(_T_613, deq_vec[5][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1447 = mux(_T_614, deq_vec[6][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1448 = mux(_T_615, deq_vec[7][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1449 = or(_T_1441, _T_1442) node _T_1450 = or(_T_1449, _T_1443) node _T_1451 = or(_T_1450, _T_1444) node _T_1452 = or(_T_1451, _T_1445) node _T_1453 = or(_T_1452, _T_1446) node _T_1454 = or(_T_1453, _T_1447) node _T_1455 = or(_T_1454, _T_1448) wire _WIRE_58 : UInt<1> connect _WIRE_58, _T_1455 connect _WIRE_47.swap23, _WIRE_58 node _T_1456 = mux(_T_608, deq_vec[0][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1457 = mux(_T_609, deq_vec[1][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1458 = mux(_T_610, deq_vec[2][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1459 = mux(_T_611, deq_vec[3][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1460 = mux(_T_612, deq_vec[4][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1461 = mux(_T_613, deq_vec[5][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1462 = mux(_T_614, deq_vec[6][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1463 = mux(_T_615, deq_vec[7][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1464 = or(_T_1456, _T_1457) node _T_1465 = or(_T_1464, _T_1458) node _T_1466 = or(_T_1465, _T_1459) node _T_1467 = or(_T_1466, _T_1460) node _T_1468 = or(_T_1467, _T_1461) node _T_1469 = or(_T_1468, _T_1462) node _T_1470 = or(_T_1469, _T_1463) wire _WIRE_59 : UInt<1> connect _WIRE_59, _T_1470 connect _WIRE_47.swap12, _WIRE_59 node _T_1471 = mux(_T_608, deq_vec[0][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1472 = mux(_T_609, deq_vec[1][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1473 = mux(_T_610, deq_vec[2][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1474 = mux(_T_611, deq_vec[3][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1475 = mux(_T_612, deq_vec[4][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1476 = mux(_T_613, deq_vec[5][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1477 = mux(_T_614, deq_vec[6][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1478 = mux(_T_615, deq_vec[7][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1479 = or(_T_1471, _T_1472) node _T_1480 = or(_T_1479, _T_1473) node _T_1481 = or(_T_1480, _T_1474) node _T_1482 = or(_T_1481, _T_1475) node _T_1483 = or(_T_1482, _T_1476) node _T_1484 = or(_T_1483, _T_1477) node _T_1485 = or(_T_1484, _T_1478) wire _WIRE_60 : UInt<1> connect _WIRE_60, _T_1485 connect _WIRE_47.ren3, _WIRE_60 node _T_1486 = mux(_T_608, deq_vec[0][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1487 = mux(_T_609, deq_vec[1][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1488 = mux(_T_610, deq_vec[2][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1489 = mux(_T_611, deq_vec[3][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1490 = mux(_T_612, deq_vec[4][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1491 = mux(_T_613, deq_vec[5][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1492 = mux(_T_614, deq_vec[6][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1493 = mux(_T_615, deq_vec[7][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1494 = or(_T_1486, _T_1487) node _T_1495 = or(_T_1494, _T_1488) node _T_1496 = or(_T_1495, _T_1489) node _T_1497 = or(_T_1496, _T_1490) node _T_1498 = or(_T_1497, _T_1491) node _T_1499 = or(_T_1498, _T_1492) node _T_1500 = or(_T_1499, _T_1493) wire _WIRE_61 : UInt<1> connect _WIRE_61, _T_1500 connect _WIRE_47.ren2, _WIRE_61 node _T_1501 = mux(_T_608, deq_vec[0][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1502 = mux(_T_609, deq_vec[1][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1503 = mux(_T_610, deq_vec[2][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1504 = mux(_T_611, deq_vec[3][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1505 = mux(_T_612, deq_vec[4][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1506 = mux(_T_613, deq_vec[5][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1507 = mux(_T_614, deq_vec[6][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1508 = mux(_T_615, deq_vec[7][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1509 = or(_T_1501, _T_1502) node _T_1510 = or(_T_1509, _T_1503) node _T_1511 = or(_T_1510, _T_1504) node _T_1512 = or(_T_1511, _T_1505) node _T_1513 = or(_T_1512, _T_1506) node _T_1514 = or(_T_1513, _T_1507) node _T_1515 = or(_T_1514, _T_1508) wire _WIRE_62 : UInt<1> connect _WIRE_62, _T_1515 connect _WIRE_47.ren1, _WIRE_62 node _T_1516 = mux(_T_608, deq_vec[0][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1517 = mux(_T_609, deq_vec[1][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1518 = mux(_T_610, deq_vec[2][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1519 = mux(_T_611, deq_vec[3][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1520 = mux(_T_612, deq_vec[4][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1521 = mux(_T_613, deq_vec[5][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1522 = mux(_T_614, deq_vec[6][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1523 = mux(_T_615, deq_vec[7][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1524 = or(_T_1516, _T_1517) node _T_1525 = or(_T_1524, _T_1518) node _T_1526 = or(_T_1525, _T_1519) node _T_1527 = or(_T_1526, _T_1520) node _T_1528 = or(_T_1527, _T_1521) node _T_1529 = or(_T_1528, _T_1522) node _T_1530 = or(_T_1529, _T_1523) wire _WIRE_63 : UInt<1> connect _WIRE_63, _T_1530 connect _WIRE_47.wen, _WIRE_63 node _T_1531 = mux(_T_608, deq_vec[0][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1532 = mux(_T_609, deq_vec[1][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1533 = mux(_T_610, deq_vec[2][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1534 = mux(_T_611, deq_vec[3][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1535 = mux(_T_612, deq_vec[4][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1536 = mux(_T_613, deq_vec[5][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1537 = mux(_T_614, deq_vec[6][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1538 = mux(_T_615, deq_vec[7][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1539 = or(_T_1531, _T_1532) node _T_1540 = or(_T_1539, _T_1533) node _T_1541 = or(_T_1540, _T_1534) node _T_1542 = or(_T_1541, _T_1535) node _T_1543 = or(_T_1542, _T_1536) node _T_1544 = or(_T_1543, _T_1537) node _T_1545 = or(_T_1544, _T_1538) wire _WIRE_64 : UInt<1> connect _WIRE_64, _T_1545 connect _WIRE_47.ldst, _WIRE_64 connect _WIRE_1.fp_ctrl, _WIRE_47 node _T_1546 = mux(_T_608, deq_vec[0][0].op2_sel, UInt<1>(0h0)) node _T_1547 = mux(_T_609, deq_vec[1][0].op2_sel, UInt<1>(0h0)) node _T_1548 = mux(_T_610, deq_vec[2][0].op2_sel, UInt<1>(0h0)) node _T_1549 = mux(_T_611, deq_vec[3][0].op2_sel, UInt<1>(0h0)) node _T_1550 = mux(_T_612, deq_vec[4][0].op2_sel, UInt<1>(0h0)) node _T_1551 = mux(_T_613, deq_vec[5][0].op2_sel, UInt<1>(0h0)) node _T_1552 = mux(_T_614, deq_vec[6][0].op2_sel, UInt<1>(0h0)) node _T_1553 = mux(_T_615, deq_vec[7][0].op2_sel, UInt<1>(0h0)) node _T_1554 = or(_T_1546, _T_1547) node _T_1555 = or(_T_1554, _T_1548) node _T_1556 = or(_T_1555, _T_1549) node _T_1557 = or(_T_1556, _T_1550) node _T_1558 = or(_T_1557, _T_1551) node _T_1559 = or(_T_1558, _T_1552) node _T_1560 = or(_T_1559, _T_1553) wire _WIRE_65 : UInt<3> connect _WIRE_65, _T_1560 connect _WIRE_1.op2_sel, _WIRE_65 node _T_1561 = mux(_T_608, deq_vec[0][0].op1_sel, UInt<1>(0h0)) node _T_1562 = mux(_T_609, deq_vec[1][0].op1_sel, UInt<1>(0h0)) node _T_1563 = mux(_T_610, deq_vec[2][0].op1_sel, UInt<1>(0h0)) node _T_1564 = mux(_T_611, deq_vec[3][0].op1_sel, UInt<1>(0h0)) node _T_1565 = mux(_T_612, deq_vec[4][0].op1_sel, UInt<1>(0h0)) node _T_1566 = mux(_T_613, deq_vec[5][0].op1_sel, UInt<1>(0h0)) node _T_1567 = mux(_T_614, deq_vec[6][0].op1_sel, UInt<1>(0h0)) node _T_1568 = mux(_T_615, deq_vec[7][0].op1_sel, UInt<1>(0h0)) node _T_1569 = or(_T_1561, _T_1562) node _T_1570 = or(_T_1569, _T_1563) node _T_1571 = or(_T_1570, _T_1564) node _T_1572 = or(_T_1571, _T_1565) node _T_1573 = or(_T_1572, _T_1566) node _T_1574 = or(_T_1573, _T_1567) node _T_1575 = or(_T_1574, _T_1568) wire _WIRE_66 : UInt<2> connect _WIRE_66, _T_1575 connect _WIRE_1.op1_sel, _WIRE_66 node _T_1576 = mux(_T_608, deq_vec[0][0].imm_packed, UInt<1>(0h0)) node _T_1577 = mux(_T_609, deq_vec[1][0].imm_packed, UInt<1>(0h0)) node _T_1578 = mux(_T_610, deq_vec[2][0].imm_packed, UInt<1>(0h0)) node _T_1579 = mux(_T_611, deq_vec[3][0].imm_packed, UInt<1>(0h0)) node _T_1580 = mux(_T_612, deq_vec[4][0].imm_packed, UInt<1>(0h0)) node _T_1581 = mux(_T_613, deq_vec[5][0].imm_packed, UInt<1>(0h0)) node _T_1582 = mux(_T_614, deq_vec[6][0].imm_packed, UInt<1>(0h0)) node _T_1583 = mux(_T_615, deq_vec[7][0].imm_packed, UInt<1>(0h0)) node _T_1584 = or(_T_1576, _T_1577) node _T_1585 = or(_T_1584, _T_1578) node _T_1586 = or(_T_1585, _T_1579) node _T_1587 = or(_T_1586, _T_1580) node _T_1588 = or(_T_1587, _T_1581) node _T_1589 = or(_T_1588, _T_1582) node _T_1590 = or(_T_1589, _T_1583) wire _WIRE_67 : UInt<20> connect _WIRE_67, _T_1590 connect _WIRE_1.imm_packed, _WIRE_67 node _T_1591 = mux(_T_608, deq_vec[0][0].pimm, UInt<1>(0h0)) node _T_1592 = mux(_T_609, deq_vec[1][0].pimm, UInt<1>(0h0)) node _T_1593 = mux(_T_610, deq_vec[2][0].pimm, UInt<1>(0h0)) node _T_1594 = mux(_T_611, deq_vec[3][0].pimm, UInt<1>(0h0)) node _T_1595 = mux(_T_612, deq_vec[4][0].pimm, UInt<1>(0h0)) node _T_1596 = mux(_T_613, deq_vec[5][0].pimm, UInt<1>(0h0)) node _T_1597 = mux(_T_614, deq_vec[6][0].pimm, UInt<1>(0h0)) node _T_1598 = mux(_T_615, deq_vec[7][0].pimm, UInt<1>(0h0)) node _T_1599 = or(_T_1591, _T_1592) node _T_1600 = or(_T_1599, _T_1593) node _T_1601 = or(_T_1600, _T_1594) node _T_1602 = or(_T_1601, _T_1595) node _T_1603 = or(_T_1602, _T_1596) node _T_1604 = or(_T_1603, _T_1597) node _T_1605 = or(_T_1604, _T_1598) wire _WIRE_68 : UInt<5> connect _WIRE_68, _T_1605 connect _WIRE_1.pimm, _WIRE_68 node _T_1606 = mux(_T_608, deq_vec[0][0].imm_sel, UInt<1>(0h0)) node _T_1607 = mux(_T_609, deq_vec[1][0].imm_sel, UInt<1>(0h0)) node _T_1608 = mux(_T_610, deq_vec[2][0].imm_sel, UInt<1>(0h0)) node _T_1609 = mux(_T_611, deq_vec[3][0].imm_sel, UInt<1>(0h0)) node _T_1610 = mux(_T_612, deq_vec[4][0].imm_sel, UInt<1>(0h0)) node _T_1611 = mux(_T_613, deq_vec[5][0].imm_sel, UInt<1>(0h0)) node _T_1612 = mux(_T_614, deq_vec[6][0].imm_sel, UInt<1>(0h0)) node _T_1613 = mux(_T_615, deq_vec[7][0].imm_sel, UInt<1>(0h0)) node _T_1614 = or(_T_1606, _T_1607) node _T_1615 = or(_T_1614, _T_1608) node _T_1616 = or(_T_1615, _T_1609) node _T_1617 = or(_T_1616, _T_1610) node _T_1618 = or(_T_1617, _T_1611) node _T_1619 = or(_T_1618, _T_1612) node _T_1620 = or(_T_1619, _T_1613) wire _WIRE_69 : UInt<3> connect _WIRE_69, _T_1620 connect _WIRE_1.imm_sel, _WIRE_69 node _T_1621 = mux(_T_608, deq_vec[0][0].imm_rename, UInt<1>(0h0)) node _T_1622 = mux(_T_609, deq_vec[1][0].imm_rename, UInt<1>(0h0)) node _T_1623 = mux(_T_610, deq_vec[2][0].imm_rename, UInt<1>(0h0)) node _T_1624 = mux(_T_611, deq_vec[3][0].imm_rename, UInt<1>(0h0)) node _T_1625 = mux(_T_612, deq_vec[4][0].imm_rename, UInt<1>(0h0)) node _T_1626 = mux(_T_613, deq_vec[5][0].imm_rename, UInt<1>(0h0)) node _T_1627 = mux(_T_614, deq_vec[6][0].imm_rename, UInt<1>(0h0)) node _T_1628 = mux(_T_615, deq_vec[7][0].imm_rename, UInt<1>(0h0)) node _T_1629 = or(_T_1621, _T_1622) node _T_1630 = or(_T_1629, _T_1623) node _T_1631 = or(_T_1630, _T_1624) node _T_1632 = or(_T_1631, _T_1625) node _T_1633 = or(_T_1632, _T_1626) node _T_1634 = or(_T_1633, _T_1627) node _T_1635 = or(_T_1634, _T_1628) wire _WIRE_70 : UInt<1> connect _WIRE_70, _T_1635 connect _WIRE_1.imm_rename, _WIRE_70 node _T_1636 = mux(_T_608, deq_vec[0][0].taken, UInt<1>(0h0)) node _T_1637 = mux(_T_609, deq_vec[1][0].taken, UInt<1>(0h0)) node _T_1638 = mux(_T_610, deq_vec[2][0].taken, UInt<1>(0h0)) node _T_1639 = mux(_T_611, deq_vec[3][0].taken, UInt<1>(0h0)) node _T_1640 = mux(_T_612, deq_vec[4][0].taken, UInt<1>(0h0)) node _T_1641 = mux(_T_613, deq_vec[5][0].taken, UInt<1>(0h0)) node _T_1642 = mux(_T_614, deq_vec[6][0].taken, UInt<1>(0h0)) node _T_1643 = mux(_T_615, deq_vec[7][0].taken, UInt<1>(0h0)) node _T_1644 = or(_T_1636, _T_1637) node _T_1645 = or(_T_1644, _T_1638) node _T_1646 = or(_T_1645, _T_1639) node _T_1647 = or(_T_1646, _T_1640) node _T_1648 = or(_T_1647, _T_1641) node _T_1649 = or(_T_1648, _T_1642) node _T_1650 = or(_T_1649, _T_1643) wire _WIRE_71 : UInt<1> connect _WIRE_71, _T_1650 connect _WIRE_1.taken, _WIRE_71 node _T_1651 = mux(_T_608, deq_vec[0][0].pc_lob, UInt<1>(0h0)) node _T_1652 = mux(_T_609, deq_vec[1][0].pc_lob, UInt<1>(0h0)) node _T_1653 = mux(_T_610, deq_vec[2][0].pc_lob, UInt<1>(0h0)) node _T_1654 = mux(_T_611, deq_vec[3][0].pc_lob, UInt<1>(0h0)) node _T_1655 = mux(_T_612, deq_vec[4][0].pc_lob, UInt<1>(0h0)) node _T_1656 = mux(_T_613, deq_vec[5][0].pc_lob, UInt<1>(0h0)) node _T_1657 = mux(_T_614, deq_vec[6][0].pc_lob, UInt<1>(0h0)) node _T_1658 = mux(_T_615, deq_vec[7][0].pc_lob, UInt<1>(0h0)) node _T_1659 = or(_T_1651, _T_1652) node _T_1660 = or(_T_1659, _T_1653) node _T_1661 = or(_T_1660, _T_1654) node _T_1662 = or(_T_1661, _T_1655) node _T_1663 = or(_T_1662, _T_1656) node _T_1664 = or(_T_1663, _T_1657) node _T_1665 = or(_T_1664, _T_1658) wire _WIRE_72 : UInt<6> connect _WIRE_72, _T_1665 connect _WIRE_1.pc_lob, _WIRE_72 node _T_1666 = mux(_T_608, deq_vec[0][0].edge_inst, UInt<1>(0h0)) node _T_1667 = mux(_T_609, deq_vec[1][0].edge_inst, UInt<1>(0h0)) node _T_1668 = mux(_T_610, deq_vec[2][0].edge_inst, UInt<1>(0h0)) node _T_1669 = mux(_T_611, deq_vec[3][0].edge_inst, UInt<1>(0h0)) node _T_1670 = mux(_T_612, deq_vec[4][0].edge_inst, UInt<1>(0h0)) node _T_1671 = mux(_T_613, deq_vec[5][0].edge_inst, UInt<1>(0h0)) node _T_1672 = mux(_T_614, deq_vec[6][0].edge_inst, UInt<1>(0h0)) node _T_1673 = mux(_T_615, deq_vec[7][0].edge_inst, UInt<1>(0h0)) node _T_1674 = or(_T_1666, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = or(_T_1675, _T_1669) node _T_1677 = or(_T_1676, _T_1670) node _T_1678 = or(_T_1677, _T_1671) node _T_1679 = or(_T_1678, _T_1672) node _T_1680 = or(_T_1679, _T_1673) wire _WIRE_73 : UInt<1> connect _WIRE_73, _T_1680 connect _WIRE_1.edge_inst, _WIRE_73 node _T_1681 = mux(_T_608, deq_vec[0][0].ftq_idx, UInt<1>(0h0)) node _T_1682 = mux(_T_609, deq_vec[1][0].ftq_idx, UInt<1>(0h0)) node _T_1683 = mux(_T_610, deq_vec[2][0].ftq_idx, UInt<1>(0h0)) node _T_1684 = mux(_T_611, deq_vec[3][0].ftq_idx, UInt<1>(0h0)) node _T_1685 = mux(_T_612, deq_vec[4][0].ftq_idx, UInt<1>(0h0)) node _T_1686 = mux(_T_613, deq_vec[5][0].ftq_idx, UInt<1>(0h0)) node _T_1687 = mux(_T_614, deq_vec[6][0].ftq_idx, UInt<1>(0h0)) node _T_1688 = mux(_T_615, deq_vec[7][0].ftq_idx, UInt<1>(0h0)) node _T_1689 = or(_T_1681, _T_1682) node _T_1690 = or(_T_1689, _T_1683) node _T_1691 = or(_T_1690, _T_1684) node _T_1692 = or(_T_1691, _T_1685) node _T_1693 = or(_T_1692, _T_1686) node _T_1694 = or(_T_1693, _T_1687) node _T_1695 = or(_T_1694, _T_1688) wire _WIRE_74 : UInt<5> connect _WIRE_74, _T_1695 connect _WIRE_1.ftq_idx, _WIRE_74 node _T_1696 = mux(_T_608, deq_vec[0][0].is_mov, UInt<1>(0h0)) node _T_1697 = mux(_T_609, deq_vec[1][0].is_mov, UInt<1>(0h0)) node _T_1698 = mux(_T_610, deq_vec[2][0].is_mov, UInt<1>(0h0)) node _T_1699 = mux(_T_611, deq_vec[3][0].is_mov, UInt<1>(0h0)) node _T_1700 = mux(_T_612, deq_vec[4][0].is_mov, UInt<1>(0h0)) node _T_1701 = mux(_T_613, deq_vec[5][0].is_mov, UInt<1>(0h0)) node _T_1702 = mux(_T_614, deq_vec[6][0].is_mov, UInt<1>(0h0)) node _T_1703 = mux(_T_615, deq_vec[7][0].is_mov, UInt<1>(0h0)) node _T_1704 = or(_T_1696, _T_1697) node _T_1705 = or(_T_1704, _T_1698) node _T_1706 = or(_T_1705, _T_1699) node _T_1707 = or(_T_1706, _T_1700) node _T_1708 = or(_T_1707, _T_1701) node _T_1709 = or(_T_1708, _T_1702) node _T_1710 = or(_T_1709, _T_1703) wire _WIRE_75 : UInt<1> connect _WIRE_75, _T_1710 connect _WIRE_1.is_mov, _WIRE_75 node _T_1711 = mux(_T_608, deq_vec[0][0].is_rocc, UInt<1>(0h0)) node _T_1712 = mux(_T_609, deq_vec[1][0].is_rocc, UInt<1>(0h0)) node _T_1713 = mux(_T_610, deq_vec[2][0].is_rocc, UInt<1>(0h0)) node _T_1714 = mux(_T_611, deq_vec[3][0].is_rocc, UInt<1>(0h0)) node _T_1715 = mux(_T_612, deq_vec[4][0].is_rocc, UInt<1>(0h0)) node _T_1716 = mux(_T_613, deq_vec[5][0].is_rocc, UInt<1>(0h0)) node _T_1717 = mux(_T_614, deq_vec[6][0].is_rocc, UInt<1>(0h0)) node _T_1718 = mux(_T_615, deq_vec[7][0].is_rocc, UInt<1>(0h0)) node _T_1719 = or(_T_1711, _T_1712) node _T_1720 = or(_T_1719, _T_1713) node _T_1721 = or(_T_1720, _T_1714) node _T_1722 = or(_T_1721, _T_1715) node _T_1723 = or(_T_1722, _T_1716) node _T_1724 = or(_T_1723, _T_1717) node _T_1725 = or(_T_1724, _T_1718) wire _WIRE_76 : UInt<1> connect _WIRE_76, _T_1725 connect _WIRE_1.is_rocc, _WIRE_76 node _T_1726 = mux(_T_608, deq_vec[0][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1727 = mux(_T_609, deq_vec[1][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1728 = mux(_T_610, deq_vec[2][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1729 = mux(_T_611, deq_vec[3][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1730 = mux(_T_612, deq_vec[4][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1731 = mux(_T_613, deq_vec[5][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1732 = mux(_T_614, deq_vec[6][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1733 = mux(_T_615, deq_vec[7][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1734 = or(_T_1726, _T_1727) node _T_1735 = or(_T_1734, _T_1728) node _T_1736 = or(_T_1735, _T_1729) node _T_1737 = or(_T_1736, _T_1730) node _T_1738 = or(_T_1737, _T_1731) node _T_1739 = or(_T_1738, _T_1732) node _T_1740 = or(_T_1739, _T_1733) wire _WIRE_77 : UInt<1> connect _WIRE_77, _T_1740 connect _WIRE_1.is_sys_pc2epc, _WIRE_77 node _T_1741 = mux(_T_608, deq_vec[0][0].is_eret, UInt<1>(0h0)) node _T_1742 = mux(_T_609, deq_vec[1][0].is_eret, UInt<1>(0h0)) node _T_1743 = mux(_T_610, deq_vec[2][0].is_eret, UInt<1>(0h0)) node _T_1744 = mux(_T_611, deq_vec[3][0].is_eret, UInt<1>(0h0)) node _T_1745 = mux(_T_612, deq_vec[4][0].is_eret, UInt<1>(0h0)) node _T_1746 = mux(_T_613, deq_vec[5][0].is_eret, UInt<1>(0h0)) node _T_1747 = mux(_T_614, deq_vec[6][0].is_eret, UInt<1>(0h0)) node _T_1748 = mux(_T_615, deq_vec[7][0].is_eret, UInt<1>(0h0)) node _T_1749 = or(_T_1741, _T_1742) node _T_1750 = or(_T_1749, _T_1743) node _T_1751 = or(_T_1750, _T_1744) node _T_1752 = or(_T_1751, _T_1745) node _T_1753 = or(_T_1752, _T_1746) node _T_1754 = or(_T_1753, _T_1747) node _T_1755 = or(_T_1754, _T_1748) wire _WIRE_78 : UInt<1> connect _WIRE_78, _T_1755 connect _WIRE_1.is_eret, _WIRE_78 node _T_1756 = mux(_T_608, deq_vec[0][0].is_amo, UInt<1>(0h0)) node _T_1757 = mux(_T_609, deq_vec[1][0].is_amo, UInt<1>(0h0)) node _T_1758 = mux(_T_610, deq_vec[2][0].is_amo, UInt<1>(0h0)) node _T_1759 = mux(_T_611, deq_vec[3][0].is_amo, UInt<1>(0h0)) node _T_1760 = mux(_T_612, deq_vec[4][0].is_amo, UInt<1>(0h0)) node _T_1761 = mux(_T_613, deq_vec[5][0].is_amo, UInt<1>(0h0)) node _T_1762 = mux(_T_614, deq_vec[6][0].is_amo, UInt<1>(0h0)) node _T_1763 = mux(_T_615, deq_vec[7][0].is_amo, UInt<1>(0h0)) node _T_1764 = or(_T_1756, _T_1757) node _T_1765 = or(_T_1764, _T_1758) node _T_1766 = or(_T_1765, _T_1759) node _T_1767 = or(_T_1766, _T_1760) node _T_1768 = or(_T_1767, _T_1761) node _T_1769 = or(_T_1768, _T_1762) node _T_1770 = or(_T_1769, _T_1763) wire _WIRE_79 : UInt<1> connect _WIRE_79, _T_1770 connect _WIRE_1.is_amo, _WIRE_79 node _T_1771 = mux(_T_608, deq_vec[0][0].is_sfence, UInt<1>(0h0)) node _T_1772 = mux(_T_609, deq_vec[1][0].is_sfence, UInt<1>(0h0)) node _T_1773 = mux(_T_610, deq_vec[2][0].is_sfence, UInt<1>(0h0)) node _T_1774 = mux(_T_611, deq_vec[3][0].is_sfence, UInt<1>(0h0)) node _T_1775 = mux(_T_612, deq_vec[4][0].is_sfence, UInt<1>(0h0)) node _T_1776 = mux(_T_613, deq_vec[5][0].is_sfence, UInt<1>(0h0)) node _T_1777 = mux(_T_614, deq_vec[6][0].is_sfence, UInt<1>(0h0)) node _T_1778 = mux(_T_615, deq_vec[7][0].is_sfence, UInt<1>(0h0)) node _T_1779 = or(_T_1771, _T_1772) node _T_1780 = or(_T_1779, _T_1773) node _T_1781 = or(_T_1780, _T_1774) node _T_1782 = or(_T_1781, _T_1775) node _T_1783 = or(_T_1782, _T_1776) node _T_1784 = or(_T_1783, _T_1777) node _T_1785 = or(_T_1784, _T_1778) wire _WIRE_80 : UInt<1> connect _WIRE_80, _T_1785 connect _WIRE_1.is_sfence, _WIRE_80 node _T_1786 = mux(_T_608, deq_vec[0][0].is_fencei, UInt<1>(0h0)) node _T_1787 = mux(_T_609, deq_vec[1][0].is_fencei, UInt<1>(0h0)) node _T_1788 = mux(_T_610, deq_vec[2][0].is_fencei, UInt<1>(0h0)) node _T_1789 = mux(_T_611, deq_vec[3][0].is_fencei, UInt<1>(0h0)) node _T_1790 = mux(_T_612, deq_vec[4][0].is_fencei, UInt<1>(0h0)) node _T_1791 = mux(_T_613, deq_vec[5][0].is_fencei, UInt<1>(0h0)) node _T_1792 = mux(_T_614, deq_vec[6][0].is_fencei, UInt<1>(0h0)) node _T_1793 = mux(_T_615, deq_vec[7][0].is_fencei, UInt<1>(0h0)) node _T_1794 = or(_T_1786, _T_1787) node _T_1795 = or(_T_1794, _T_1788) node _T_1796 = or(_T_1795, _T_1789) node _T_1797 = or(_T_1796, _T_1790) node _T_1798 = or(_T_1797, _T_1791) node _T_1799 = or(_T_1798, _T_1792) node _T_1800 = or(_T_1799, _T_1793) wire _WIRE_81 : UInt<1> connect _WIRE_81, _T_1800 connect _WIRE_1.is_fencei, _WIRE_81 node _T_1801 = mux(_T_608, deq_vec[0][0].is_fence, UInt<1>(0h0)) node _T_1802 = mux(_T_609, deq_vec[1][0].is_fence, UInt<1>(0h0)) node _T_1803 = mux(_T_610, deq_vec[2][0].is_fence, UInt<1>(0h0)) node _T_1804 = mux(_T_611, deq_vec[3][0].is_fence, UInt<1>(0h0)) node _T_1805 = mux(_T_612, deq_vec[4][0].is_fence, UInt<1>(0h0)) node _T_1806 = mux(_T_613, deq_vec[5][0].is_fence, UInt<1>(0h0)) node _T_1807 = mux(_T_614, deq_vec[6][0].is_fence, UInt<1>(0h0)) node _T_1808 = mux(_T_615, deq_vec[7][0].is_fence, UInt<1>(0h0)) node _T_1809 = or(_T_1801, _T_1802) node _T_1810 = or(_T_1809, _T_1803) node _T_1811 = or(_T_1810, _T_1804) node _T_1812 = or(_T_1811, _T_1805) node _T_1813 = or(_T_1812, _T_1806) node _T_1814 = or(_T_1813, _T_1807) node _T_1815 = or(_T_1814, _T_1808) wire _WIRE_82 : UInt<1> connect _WIRE_82, _T_1815 connect _WIRE_1.is_fence, _WIRE_82 node _T_1816 = mux(_T_608, deq_vec[0][0].is_sfb, UInt<1>(0h0)) node _T_1817 = mux(_T_609, deq_vec[1][0].is_sfb, UInt<1>(0h0)) node _T_1818 = mux(_T_610, deq_vec[2][0].is_sfb, UInt<1>(0h0)) node _T_1819 = mux(_T_611, deq_vec[3][0].is_sfb, UInt<1>(0h0)) node _T_1820 = mux(_T_612, deq_vec[4][0].is_sfb, UInt<1>(0h0)) node _T_1821 = mux(_T_613, deq_vec[5][0].is_sfb, UInt<1>(0h0)) node _T_1822 = mux(_T_614, deq_vec[6][0].is_sfb, UInt<1>(0h0)) node _T_1823 = mux(_T_615, deq_vec[7][0].is_sfb, UInt<1>(0h0)) node _T_1824 = or(_T_1816, _T_1817) node _T_1825 = or(_T_1824, _T_1818) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = or(_T_1828, _T_1822) node _T_1830 = or(_T_1829, _T_1823) wire _WIRE_83 : UInt<1> connect _WIRE_83, _T_1830 connect _WIRE_1.is_sfb, _WIRE_83 node _T_1831 = mux(_T_608, deq_vec[0][0].br_type, UInt<1>(0h0)) node _T_1832 = mux(_T_609, deq_vec[1][0].br_type, UInt<1>(0h0)) node _T_1833 = mux(_T_610, deq_vec[2][0].br_type, UInt<1>(0h0)) node _T_1834 = mux(_T_611, deq_vec[3][0].br_type, UInt<1>(0h0)) node _T_1835 = mux(_T_612, deq_vec[4][0].br_type, UInt<1>(0h0)) node _T_1836 = mux(_T_613, deq_vec[5][0].br_type, UInt<1>(0h0)) node _T_1837 = mux(_T_614, deq_vec[6][0].br_type, UInt<1>(0h0)) node _T_1838 = mux(_T_615, deq_vec[7][0].br_type, UInt<1>(0h0)) node _T_1839 = or(_T_1831, _T_1832) node _T_1840 = or(_T_1839, _T_1833) node _T_1841 = or(_T_1840, _T_1834) node _T_1842 = or(_T_1841, _T_1835) node _T_1843 = or(_T_1842, _T_1836) node _T_1844 = or(_T_1843, _T_1837) node _T_1845 = or(_T_1844, _T_1838) wire _WIRE_84 : UInt<4> connect _WIRE_84, _T_1845 connect _WIRE_1.br_type, _WIRE_84 node _T_1846 = mux(_T_608, deq_vec[0][0].br_tag, UInt<1>(0h0)) node _T_1847 = mux(_T_609, deq_vec[1][0].br_tag, UInt<1>(0h0)) node _T_1848 = mux(_T_610, deq_vec[2][0].br_tag, UInt<1>(0h0)) node _T_1849 = mux(_T_611, deq_vec[3][0].br_tag, UInt<1>(0h0)) node _T_1850 = mux(_T_612, deq_vec[4][0].br_tag, UInt<1>(0h0)) node _T_1851 = mux(_T_613, deq_vec[5][0].br_tag, UInt<1>(0h0)) node _T_1852 = mux(_T_614, deq_vec[6][0].br_tag, UInt<1>(0h0)) node _T_1853 = mux(_T_615, deq_vec[7][0].br_tag, UInt<1>(0h0)) node _T_1854 = or(_T_1846, _T_1847) node _T_1855 = or(_T_1854, _T_1848) node _T_1856 = or(_T_1855, _T_1849) node _T_1857 = or(_T_1856, _T_1850) node _T_1858 = or(_T_1857, _T_1851) node _T_1859 = or(_T_1858, _T_1852) node _T_1860 = or(_T_1859, _T_1853) wire _WIRE_85 : UInt<4> connect _WIRE_85, _T_1860 connect _WIRE_1.br_tag, _WIRE_85 node _T_1861 = mux(_T_608, deq_vec[0][0].br_mask, UInt<1>(0h0)) node _T_1862 = mux(_T_609, deq_vec[1][0].br_mask, UInt<1>(0h0)) node _T_1863 = mux(_T_610, deq_vec[2][0].br_mask, UInt<1>(0h0)) node _T_1864 = mux(_T_611, deq_vec[3][0].br_mask, UInt<1>(0h0)) node _T_1865 = mux(_T_612, deq_vec[4][0].br_mask, UInt<1>(0h0)) node _T_1866 = mux(_T_613, deq_vec[5][0].br_mask, UInt<1>(0h0)) node _T_1867 = mux(_T_614, deq_vec[6][0].br_mask, UInt<1>(0h0)) node _T_1868 = mux(_T_615, deq_vec[7][0].br_mask, UInt<1>(0h0)) node _T_1869 = or(_T_1861, _T_1862) node _T_1870 = or(_T_1869, _T_1863) node _T_1871 = or(_T_1870, _T_1864) node _T_1872 = or(_T_1871, _T_1865) node _T_1873 = or(_T_1872, _T_1866) node _T_1874 = or(_T_1873, _T_1867) node _T_1875 = or(_T_1874, _T_1868) wire _WIRE_86 : UInt<16> connect _WIRE_86, _T_1875 connect _WIRE_1.br_mask, _WIRE_86 node _T_1876 = mux(_T_608, deq_vec[0][0].dis_col_sel, UInt<1>(0h0)) node _T_1877 = mux(_T_609, deq_vec[1][0].dis_col_sel, UInt<1>(0h0)) node _T_1878 = mux(_T_610, deq_vec[2][0].dis_col_sel, UInt<1>(0h0)) node _T_1879 = mux(_T_611, deq_vec[3][0].dis_col_sel, UInt<1>(0h0)) node _T_1880 = mux(_T_612, deq_vec[4][0].dis_col_sel, UInt<1>(0h0)) node _T_1881 = mux(_T_613, deq_vec[5][0].dis_col_sel, UInt<1>(0h0)) node _T_1882 = mux(_T_614, deq_vec[6][0].dis_col_sel, UInt<1>(0h0)) node _T_1883 = mux(_T_615, deq_vec[7][0].dis_col_sel, UInt<1>(0h0)) node _T_1884 = or(_T_1876, _T_1877) node _T_1885 = or(_T_1884, _T_1878) node _T_1886 = or(_T_1885, _T_1879) node _T_1887 = or(_T_1886, _T_1880) node _T_1888 = or(_T_1887, _T_1881) node _T_1889 = or(_T_1888, _T_1882) node _T_1890 = or(_T_1889, _T_1883) wire _WIRE_87 : UInt<3> connect _WIRE_87, _T_1890 connect _WIRE_1.dis_col_sel, _WIRE_87 node _T_1891 = mux(_T_608, deq_vec[0][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1892 = mux(_T_609, deq_vec[1][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1893 = mux(_T_610, deq_vec[2][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1894 = mux(_T_611, deq_vec[3][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1895 = mux(_T_612, deq_vec[4][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1896 = mux(_T_613, deq_vec[5][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1897 = mux(_T_614, deq_vec[6][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1898 = mux(_T_615, deq_vec[7][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1899 = or(_T_1891, _T_1892) node _T_1900 = or(_T_1899, _T_1893) node _T_1901 = or(_T_1900, _T_1894) node _T_1902 = or(_T_1901, _T_1895) node _T_1903 = or(_T_1902, _T_1896) node _T_1904 = or(_T_1903, _T_1897) node _T_1905 = or(_T_1904, _T_1898) wire _WIRE_88 : UInt<1> connect _WIRE_88, _T_1905 connect _WIRE_1.iw_p3_bypass_hint, _WIRE_88 node _T_1906 = mux(_T_608, deq_vec[0][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1907 = mux(_T_609, deq_vec[1][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1908 = mux(_T_610, deq_vec[2][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1909 = mux(_T_611, deq_vec[3][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1910 = mux(_T_612, deq_vec[4][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1911 = mux(_T_613, deq_vec[5][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1912 = mux(_T_614, deq_vec[6][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1913 = mux(_T_615, deq_vec[7][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1914 = or(_T_1906, _T_1907) node _T_1915 = or(_T_1914, _T_1908) node _T_1916 = or(_T_1915, _T_1909) node _T_1917 = or(_T_1916, _T_1910) node _T_1918 = or(_T_1917, _T_1911) node _T_1919 = or(_T_1918, _T_1912) node _T_1920 = or(_T_1919, _T_1913) wire _WIRE_89 : UInt<1> connect _WIRE_89, _T_1920 connect _WIRE_1.iw_p2_bypass_hint, _WIRE_89 node _T_1921 = mux(_T_608, deq_vec[0][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1922 = mux(_T_609, deq_vec[1][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1923 = mux(_T_610, deq_vec[2][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1924 = mux(_T_611, deq_vec[3][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1925 = mux(_T_612, deq_vec[4][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1926 = mux(_T_613, deq_vec[5][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1927 = mux(_T_614, deq_vec[6][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1928 = mux(_T_615, deq_vec[7][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1929 = or(_T_1921, _T_1922) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = or(_T_1930, _T_1924) node _T_1932 = or(_T_1931, _T_1925) node _T_1933 = or(_T_1932, _T_1926) node _T_1934 = or(_T_1933, _T_1927) node _T_1935 = or(_T_1934, _T_1928) wire _WIRE_90 : UInt<1> connect _WIRE_90, _T_1935 connect _WIRE_1.iw_p1_bypass_hint, _WIRE_90 node _T_1936 = mux(_T_608, deq_vec[0][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1937 = mux(_T_609, deq_vec[1][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1938 = mux(_T_610, deq_vec[2][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1939 = mux(_T_611, deq_vec[3][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1940 = mux(_T_612, deq_vec[4][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1941 = mux(_T_613, deq_vec[5][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1942 = mux(_T_614, deq_vec[6][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1943 = mux(_T_615, deq_vec[7][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1944 = or(_T_1936, _T_1937) node _T_1945 = or(_T_1944, _T_1938) node _T_1946 = or(_T_1945, _T_1939) node _T_1947 = or(_T_1946, _T_1940) node _T_1948 = or(_T_1947, _T_1941) node _T_1949 = or(_T_1948, _T_1942) node _T_1950 = or(_T_1949, _T_1943) wire _WIRE_91 : UInt<3> connect _WIRE_91, _T_1950 connect _WIRE_1.iw_p2_speculative_child, _WIRE_91 node _T_1951 = mux(_T_608, deq_vec[0][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1952 = mux(_T_609, deq_vec[1][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1953 = mux(_T_610, deq_vec[2][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1954 = mux(_T_611, deq_vec[3][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1955 = mux(_T_612, deq_vec[4][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1956 = mux(_T_613, deq_vec[5][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1957 = mux(_T_614, deq_vec[6][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1958 = mux(_T_615, deq_vec[7][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1959 = or(_T_1951, _T_1952) node _T_1960 = or(_T_1959, _T_1953) node _T_1961 = or(_T_1960, _T_1954) node _T_1962 = or(_T_1961, _T_1955) node _T_1963 = or(_T_1962, _T_1956) node _T_1964 = or(_T_1963, _T_1957) node _T_1965 = or(_T_1964, _T_1958) wire _WIRE_92 : UInt<3> connect _WIRE_92, _T_1965 connect _WIRE_1.iw_p1_speculative_child, _WIRE_92 node _T_1966 = mux(_T_608, deq_vec[0][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1967 = mux(_T_609, deq_vec[1][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1968 = mux(_T_610, deq_vec[2][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1969 = mux(_T_611, deq_vec[3][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1970 = mux(_T_612, deq_vec[4][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1971 = mux(_T_613, deq_vec[5][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1972 = mux(_T_614, deq_vec[6][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1973 = mux(_T_615, deq_vec[7][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1974 = or(_T_1966, _T_1967) node _T_1975 = or(_T_1974, _T_1968) node _T_1976 = or(_T_1975, _T_1969) node _T_1977 = or(_T_1976, _T_1970) node _T_1978 = or(_T_1977, _T_1971) node _T_1979 = or(_T_1978, _T_1972) node _T_1980 = or(_T_1979, _T_1973) wire _WIRE_93 : UInt<1> connect _WIRE_93, _T_1980 connect _WIRE_1.iw_issued_partial_dgen, _WIRE_93 node _T_1981 = mux(_T_608, deq_vec[0][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1982 = mux(_T_609, deq_vec[1][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1983 = mux(_T_610, deq_vec[2][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1984 = mux(_T_611, deq_vec[3][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1985 = mux(_T_612, deq_vec[4][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1986 = mux(_T_613, deq_vec[5][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1987 = mux(_T_614, deq_vec[6][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1988 = mux(_T_615, deq_vec[7][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1989 = or(_T_1981, _T_1982) node _T_1990 = or(_T_1989, _T_1983) node _T_1991 = or(_T_1990, _T_1984) node _T_1992 = or(_T_1991, _T_1985) node _T_1993 = or(_T_1992, _T_1986) node _T_1994 = or(_T_1993, _T_1987) node _T_1995 = or(_T_1994, _T_1988) wire _WIRE_94 : UInt<1> connect _WIRE_94, _T_1995 connect _WIRE_1.iw_issued_partial_agen, _WIRE_94 node _T_1996 = mux(_T_608, deq_vec[0][0].iw_issued, UInt<1>(0h0)) node _T_1997 = mux(_T_609, deq_vec[1][0].iw_issued, UInt<1>(0h0)) node _T_1998 = mux(_T_610, deq_vec[2][0].iw_issued, UInt<1>(0h0)) node _T_1999 = mux(_T_611, deq_vec[3][0].iw_issued, UInt<1>(0h0)) node _T_2000 = mux(_T_612, deq_vec[4][0].iw_issued, UInt<1>(0h0)) node _T_2001 = mux(_T_613, deq_vec[5][0].iw_issued, UInt<1>(0h0)) node _T_2002 = mux(_T_614, deq_vec[6][0].iw_issued, UInt<1>(0h0)) node _T_2003 = mux(_T_615, deq_vec[7][0].iw_issued, UInt<1>(0h0)) node _T_2004 = or(_T_1996, _T_1997) node _T_2005 = or(_T_2004, _T_1998) node _T_2006 = or(_T_2005, _T_1999) node _T_2007 = or(_T_2006, _T_2000) node _T_2008 = or(_T_2007, _T_2001) node _T_2009 = or(_T_2008, _T_2002) node _T_2010 = or(_T_2009, _T_2003) wire _WIRE_95 : UInt<1> connect _WIRE_95, _T_2010 connect _WIRE_1.iw_issued, _WIRE_95 wire _WIRE_96 : UInt<1>[10] node _T_2011 = mux(_T_608, deq_vec[0][0].fu_code[0], UInt<1>(0h0)) node _T_2012 = mux(_T_609, deq_vec[1][0].fu_code[0], UInt<1>(0h0)) node _T_2013 = mux(_T_610, deq_vec[2][0].fu_code[0], UInt<1>(0h0)) node _T_2014 = mux(_T_611, deq_vec[3][0].fu_code[0], UInt<1>(0h0)) node _T_2015 = mux(_T_612, deq_vec[4][0].fu_code[0], UInt<1>(0h0)) node _T_2016 = mux(_T_613, deq_vec[5][0].fu_code[0], UInt<1>(0h0)) node _T_2017 = mux(_T_614, deq_vec[6][0].fu_code[0], UInt<1>(0h0)) node _T_2018 = mux(_T_615, deq_vec[7][0].fu_code[0], UInt<1>(0h0)) node _T_2019 = or(_T_2011, _T_2012) node _T_2020 = or(_T_2019, _T_2013) node _T_2021 = or(_T_2020, _T_2014) node _T_2022 = or(_T_2021, _T_2015) node _T_2023 = or(_T_2022, _T_2016) node _T_2024 = or(_T_2023, _T_2017) node _T_2025 = or(_T_2024, _T_2018) wire _WIRE_97 : UInt<1> connect _WIRE_97, _T_2025 connect _WIRE_96[0], _WIRE_97 node _T_2026 = mux(_T_608, deq_vec[0][0].fu_code[1], UInt<1>(0h0)) node _T_2027 = mux(_T_609, deq_vec[1][0].fu_code[1], UInt<1>(0h0)) node _T_2028 = mux(_T_610, deq_vec[2][0].fu_code[1], UInt<1>(0h0)) node _T_2029 = mux(_T_611, deq_vec[3][0].fu_code[1], UInt<1>(0h0)) node _T_2030 = mux(_T_612, deq_vec[4][0].fu_code[1], UInt<1>(0h0)) node _T_2031 = mux(_T_613, deq_vec[5][0].fu_code[1], UInt<1>(0h0)) node _T_2032 = mux(_T_614, deq_vec[6][0].fu_code[1], UInt<1>(0h0)) node _T_2033 = mux(_T_615, deq_vec[7][0].fu_code[1], UInt<1>(0h0)) node _T_2034 = or(_T_2026, _T_2027) node _T_2035 = or(_T_2034, _T_2028) node _T_2036 = or(_T_2035, _T_2029) node _T_2037 = or(_T_2036, _T_2030) node _T_2038 = or(_T_2037, _T_2031) node _T_2039 = or(_T_2038, _T_2032) node _T_2040 = or(_T_2039, _T_2033) wire _WIRE_98 : UInt<1> connect _WIRE_98, _T_2040 connect _WIRE_96[1], _WIRE_98 node _T_2041 = mux(_T_608, deq_vec[0][0].fu_code[2], UInt<1>(0h0)) node _T_2042 = mux(_T_609, deq_vec[1][0].fu_code[2], UInt<1>(0h0)) node _T_2043 = mux(_T_610, deq_vec[2][0].fu_code[2], UInt<1>(0h0)) node _T_2044 = mux(_T_611, deq_vec[3][0].fu_code[2], UInt<1>(0h0)) node _T_2045 = mux(_T_612, deq_vec[4][0].fu_code[2], UInt<1>(0h0)) node _T_2046 = mux(_T_613, deq_vec[5][0].fu_code[2], UInt<1>(0h0)) node _T_2047 = mux(_T_614, deq_vec[6][0].fu_code[2], UInt<1>(0h0)) node _T_2048 = mux(_T_615, deq_vec[7][0].fu_code[2], UInt<1>(0h0)) node _T_2049 = or(_T_2041, _T_2042) node _T_2050 = or(_T_2049, _T_2043) node _T_2051 = or(_T_2050, _T_2044) node _T_2052 = or(_T_2051, _T_2045) node _T_2053 = or(_T_2052, _T_2046) node _T_2054 = or(_T_2053, _T_2047) node _T_2055 = or(_T_2054, _T_2048) wire _WIRE_99 : UInt<1> connect _WIRE_99, _T_2055 connect _WIRE_96[2], _WIRE_99 node _T_2056 = mux(_T_608, deq_vec[0][0].fu_code[3], UInt<1>(0h0)) node _T_2057 = mux(_T_609, deq_vec[1][0].fu_code[3], UInt<1>(0h0)) node _T_2058 = mux(_T_610, deq_vec[2][0].fu_code[3], UInt<1>(0h0)) node _T_2059 = mux(_T_611, deq_vec[3][0].fu_code[3], UInt<1>(0h0)) node _T_2060 = mux(_T_612, deq_vec[4][0].fu_code[3], UInt<1>(0h0)) node _T_2061 = mux(_T_613, deq_vec[5][0].fu_code[3], UInt<1>(0h0)) node _T_2062 = mux(_T_614, deq_vec[6][0].fu_code[3], UInt<1>(0h0)) node _T_2063 = mux(_T_615, deq_vec[7][0].fu_code[3], UInt<1>(0h0)) node _T_2064 = or(_T_2056, _T_2057) node _T_2065 = or(_T_2064, _T_2058) node _T_2066 = or(_T_2065, _T_2059) node _T_2067 = or(_T_2066, _T_2060) node _T_2068 = or(_T_2067, _T_2061) node _T_2069 = or(_T_2068, _T_2062) node _T_2070 = or(_T_2069, _T_2063) wire _WIRE_100 : UInt<1> connect _WIRE_100, _T_2070 connect _WIRE_96[3], _WIRE_100 node _T_2071 = mux(_T_608, deq_vec[0][0].fu_code[4], UInt<1>(0h0)) node _T_2072 = mux(_T_609, deq_vec[1][0].fu_code[4], UInt<1>(0h0)) node _T_2073 = mux(_T_610, deq_vec[2][0].fu_code[4], UInt<1>(0h0)) node _T_2074 = mux(_T_611, deq_vec[3][0].fu_code[4], UInt<1>(0h0)) node _T_2075 = mux(_T_612, deq_vec[4][0].fu_code[4], UInt<1>(0h0)) node _T_2076 = mux(_T_613, deq_vec[5][0].fu_code[4], UInt<1>(0h0)) node _T_2077 = mux(_T_614, deq_vec[6][0].fu_code[4], UInt<1>(0h0)) node _T_2078 = mux(_T_615, deq_vec[7][0].fu_code[4], UInt<1>(0h0)) node _T_2079 = or(_T_2071, _T_2072) node _T_2080 = or(_T_2079, _T_2073) node _T_2081 = or(_T_2080, _T_2074) node _T_2082 = or(_T_2081, _T_2075) node _T_2083 = or(_T_2082, _T_2076) node _T_2084 = or(_T_2083, _T_2077) node _T_2085 = or(_T_2084, _T_2078) wire _WIRE_101 : UInt<1> connect _WIRE_101, _T_2085 connect _WIRE_96[4], _WIRE_101 node _T_2086 = mux(_T_608, deq_vec[0][0].fu_code[5], UInt<1>(0h0)) node _T_2087 = mux(_T_609, deq_vec[1][0].fu_code[5], UInt<1>(0h0)) node _T_2088 = mux(_T_610, deq_vec[2][0].fu_code[5], UInt<1>(0h0)) node _T_2089 = mux(_T_611, deq_vec[3][0].fu_code[5], UInt<1>(0h0)) node _T_2090 = mux(_T_612, deq_vec[4][0].fu_code[5], UInt<1>(0h0)) node _T_2091 = mux(_T_613, deq_vec[5][0].fu_code[5], UInt<1>(0h0)) node _T_2092 = mux(_T_614, deq_vec[6][0].fu_code[5], UInt<1>(0h0)) node _T_2093 = mux(_T_615, deq_vec[7][0].fu_code[5], UInt<1>(0h0)) node _T_2094 = or(_T_2086, _T_2087) node _T_2095 = or(_T_2094, _T_2088) node _T_2096 = or(_T_2095, _T_2089) node _T_2097 = or(_T_2096, _T_2090) node _T_2098 = or(_T_2097, _T_2091) node _T_2099 = or(_T_2098, _T_2092) node _T_2100 = or(_T_2099, _T_2093) wire _WIRE_102 : UInt<1> connect _WIRE_102, _T_2100 connect _WIRE_96[5], _WIRE_102 node _T_2101 = mux(_T_608, deq_vec[0][0].fu_code[6], UInt<1>(0h0)) node _T_2102 = mux(_T_609, deq_vec[1][0].fu_code[6], UInt<1>(0h0)) node _T_2103 = mux(_T_610, deq_vec[2][0].fu_code[6], UInt<1>(0h0)) node _T_2104 = mux(_T_611, deq_vec[3][0].fu_code[6], UInt<1>(0h0)) node _T_2105 = mux(_T_612, deq_vec[4][0].fu_code[6], UInt<1>(0h0)) node _T_2106 = mux(_T_613, deq_vec[5][0].fu_code[6], UInt<1>(0h0)) node _T_2107 = mux(_T_614, deq_vec[6][0].fu_code[6], UInt<1>(0h0)) node _T_2108 = mux(_T_615, deq_vec[7][0].fu_code[6], UInt<1>(0h0)) node _T_2109 = or(_T_2101, _T_2102) node _T_2110 = or(_T_2109, _T_2103) node _T_2111 = or(_T_2110, _T_2104) node _T_2112 = or(_T_2111, _T_2105) node _T_2113 = or(_T_2112, _T_2106) node _T_2114 = or(_T_2113, _T_2107) node _T_2115 = or(_T_2114, _T_2108) wire _WIRE_103 : UInt<1> connect _WIRE_103, _T_2115 connect _WIRE_96[6], _WIRE_103 node _T_2116 = mux(_T_608, deq_vec[0][0].fu_code[7], UInt<1>(0h0)) node _T_2117 = mux(_T_609, deq_vec[1][0].fu_code[7], UInt<1>(0h0)) node _T_2118 = mux(_T_610, deq_vec[2][0].fu_code[7], UInt<1>(0h0)) node _T_2119 = mux(_T_611, deq_vec[3][0].fu_code[7], UInt<1>(0h0)) node _T_2120 = mux(_T_612, deq_vec[4][0].fu_code[7], UInt<1>(0h0)) node _T_2121 = mux(_T_613, deq_vec[5][0].fu_code[7], UInt<1>(0h0)) node _T_2122 = mux(_T_614, deq_vec[6][0].fu_code[7], UInt<1>(0h0)) node _T_2123 = mux(_T_615, deq_vec[7][0].fu_code[7], UInt<1>(0h0)) node _T_2124 = or(_T_2116, _T_2117) node _T_2125 = or(_T_2124, _T_2118) node _T_2126 = or(_T_2125, _T_2119) node _T_2127 = or(_T_2126, _T_2120) node _T_2128 = or(_T_2127, _T_2121) node _T_2129 = or(_T_2128, _T_2122) node _T_2130 = or(_T_2129, _T_2123) wire _WIRE_104 : UInt<1> connect _WIRE_104, _T_2130 connect _WIRE_96[7], _WIRE_104 node _T_2131 = mux(_T_608, deq_vec[0][0].fu_code[8], UInt<1>(0h0)) node _T_2132 = mux(_T_609, deq_vec[1][0].fu_code[8], UInt<1>(0h0)) node _T_2133 = mux(_T_610, deq_vec[2][0].fu_code[8], UInt<1>(0h0)) node _T_2134 = mux(_T_611, deq_vec[3][0].fu_code[8], UInt<1>(0h0)) node _T_2135 = mux(_T_612, deq_vec[4][0].fu_code[8], UInt<1>(0h0)) node _T_2136 = mux(_T_613, deq_vec[5][0].fu_code[8], UInt<1>(0h0)) node _T_2137 = mux(_T_614, deq_vec[6][0].fu_code[8], UInt<1>(0h0)) node _T_2138 = mux(_T_615, deq_vec[7][0].fu_code[8], UInt<1>(0h0)) node _T_2139 = or(_T_2131, _T_2132) node _T_2140 = or(_T_2139, _T_2133) node _T_2141 = or(_T_2140, _T_2134) node _T_2142 = or(_T_2141, _T_2135) node _T_2143 = or(_T_2142, _T_2136) node _T_2144 = or(_T_2143, _T_2137) node _T_2145 = or(_T_2144, _T_2138) wire _WIRE_105 : UInt<1> connect _WIRE_105, _T_2145 connect _WIRE_96[8], _WIRE_105 node _T_2146 = mux(_T_608, deq_vec[0][0].fu_code[9], UInt<1>(0h0)) node _T_2147 = mux(_T_609, deq_vec[1][0].fu_code[9], UInt<1>(0h0)) node _T_2148 = mux(_T_610, deq_vec[2][0].fu_code[9], UInt<1>(0h0)) node _T_2149 = mux(_T_611, deq_vec[3][0].fu_code[9], UInt<1>(0h0)) node _T_2150 = mux(_T_612, deq_vec[4][0].fu_code[9], UInt<1>(0h0)) node _T_2151 = mux(_T_613, deq_vec[5][0].fu_code[9], UInt<1>(0h0)) node _T_2152 = mux(_T_614, deq_vec[6][0].fu_code[9], UInt<1>(0h0)) node _T_2153 = mux(_T_615, deq_vec[7][0].fu_code[9], UInt<1>(0h0)) node _T_2154 = or(_T_2146, _T_2147) node _T_2155 = or(_T_2154, _T_2148) node _T_2156 = or(_T_2155, _T_2149) node _T_2157 = or(_T_2156, _T_2150) node _T_2158 = or(_T_2157, _T_2151) node _T_2159 = or(_T_2158, _T_2152) node _T_2160 = or(_T_2159, _T_2153) wire _WIRE_106 : UInt<1> connect _WIRE_106, _T_2160 connect _WIRE_96[9], _WIRE_106 connect _WIRE_1.fu_code, _WIRE_96 wire _WIRE_107 : UInt<1>[4] node _T_2161 = mux(_T_608, deq_vec[0][0].iq_type[0], UInt<1>(0h0)) node _T_2162 = mux(_T_609, deq_vec[1][0].iq_type[0], UInt<1>(0h0)) node _T_2163 = mux(_T_610, deq_vec[2][0].iq_type[0], UInt<1>(0h0)) node _T_2164 = mux(_T_611, deq_vec[3][0].iq_type[0], UInt<1>(0h0)) node _T_2165 = mux(_T_612, deq_vec[4][0].iq_type[0], UInt<1>(0h0)) node _T_2166 = mux(_T_613, deq_vec[5][0].iq_type[0], UInt<1>(0h0)) node _T_2167 = mux(_T_614, deq_vec[6][0].iq_type[0], UInt<1>(0h0)) node _T_2168 = mux(_T_615, deq_vec[7][0].iq_type[0], UInt<1>(0h0)) node _T_2169 = or(_T_2161, _T_2162) node _T_2170 = or(_T_2169, _T_2163) node _T_2171 = or(_T_2170, _T_2164) node _T_2172 = or(_T_2171, _T_2165) node _T_2173 = or(_T_2172, _T_2166) node _T_2174 = or(_T_2173, _T_2167) node _T_2175 = or(_T_2174, _T_2168) wire _WIRE_108 : UInt<1> connect _WIRE_108, _T_2175 connect _WIRE_107[0], _WIRE_108 node _T_2176 = mux(_T_608, deq_vec[0][0].iq_type[1], UInt<1>(0h0)) node _T_2177 = mux(_T_609, deq_vec[1][0].iq_type[1], UInt<1>(0h0)) node _T_2178 = mux(_T_610, deq_vec[2][0].iq_type[1], UInt<1>(0h0)) node _T_2179 = mux(_T_611, deq_vec[3][0].iq_type[1], UInt<1>(0h0)) node _T_2180 = mux(_T_612, deq_vec[4][0].iq_type[1], UInt<1>(0h0)) node _T_2181 = mux(_T_613, deq_vec[5][0].iq_type[1], UInt<1>(0h0)) node _T_2182 = mux(_T_614, deq_vec[6][0].iq_type[1], UInt<1>(0h0)) node _T_2183 = mux(_T_615, deq_vec[7][0].iq_type[1], UInt<1>(0h0)) node _T_2184 = or(_T_2176, _T_2177) node _T_2185 = or(_T_2184, _T_2178) node _T_2186 = or(_T_2185, _T_2179) node _T_2187 = or(_T_2186, _T_2180) node _T_2188 = or(_T_2187, _T_2181) node _T_2189 = or(_T_2188, _T_2182) node _T_2190 = or(_T_2189, _T_2183) wire _WIRE_109 : UInt<1> connect _WIRE_109, _T_2190 connect _WIRE_107[1], _WIRE_109 node _T_2191 = mux(_T_608, deq_vec[0][0].iq_type[2], UInt<1>(0h0)) node _T_2192 = mux(_T_609, deq_vec[1][0].iq_type[2], UInt<1>(0h0)) node _T_2193 = mux(_T_610, deq_vec[2][0].iq_type[2], UInt<1>(0h0)) node _T_2194 = mux(_T_611, deq_vec[3][0].iq_type[2], UInt<1>(0h0)) node _T_2195 = mux(_T_612, deq_vec[4][0].iq_type[2], UInt<1>(0h0)) node _T_2196 = mux(_T_613, deq_vec[5][0].iq_type[2], UInt<1>(0h0)) node _T_2197 = mux(_T_614, deq_vec[6][0].iq_type[2], UInt<1>(0h0)) node _T_2198 = mux(_T_615, deq_vec[7][0].iq_type[2], UInt<1>(0h0)) node _T_2199 = or(_T_2191, _T_2192) node _T_2200 = or(_T_2199, _T_2193) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = or(_T_2201, _T_2195) node _T_2203 = or(_T_2202, _T_2196) node _T_2204 = or(_T_2203, _T_2197) node _T_2205 = or(_T_2204, _T_2198) wire _WIRE_110 : UInt<1> connect _WIRE_110, _T_2205 connect _WIRE_107[2], _WIRE_110 node _T_2206 = mux(_T_608, deq_vec[0][0].iq_type[3], UInt<1>(0h0)) node _T_2207 = mux(_T_609, deq_vec[1][0].iq_type[3], UInt<1>(0h0)) node _T_2208 = mux(_T_610, deq_vec[2][0].iq_type[3], UInt<1>(0h0)) node _T_2209 = mux(_T_611, deq_vec[3][0].iq_type[3], UInt<1>(0h0)) node _T_2210 = mux(_T_612, deq_vec[4][0].iq_type[3], UInt<1>(0h0)) node _T_2211 = mux(_T_613, deq_vec[5][0].iq_type[3], UInt<1>(0h0)) node _T_2212 = mux(_T_614, deq_vec[6][0].iq_type[3], UInt<1>(0h0)) node _T_2213 = mux(_T_615, deq_vec[7][0].iq_type[3], UInt<1>(0h0)) node _T_2214 = or(_T_2206, _T_2207) node _T_2215 = or(_T_2214, _T_2208) node _T_2216 = or(_T_2215, _T_2209) node _T_2217 = or(_T_2216, _T_2210) node _T_2218 = or(_T_2217, _T_2211) node _T_2219 = or(_T_2218, _T_2212) node _T_2220 = or(_T_2219, _T_2213) wire _WIRE_111 : UInt<1> connect _WIRE_111, _T_2220 connect _WIRE_107[3], _WIRE_111 connect _WIRE_1.iq_type, _WIRE_107 node _T_2221 = mux(_T_608, deq_vec[0][0].debug_pc, UInt<1>(0h0)) node _T_2222 = mux(_T_609, deq_vec[1][0].debug_pc, UInt<1>(0h0)) node _T_2223 = mux(_T_610, deq_vec[2][0].debug_pc, UInt<1>(0h0)) node _T_2224 = mux(_T_611, deq_vec[3][0].debug_pc, UInt<1>(0h0)) node _T_2225 = mux(_T_612, deq_vec[4][0].debug_pc, UInt<1>(0h0)) node _T_2226 = mux(_T_613, deq_vec[5][0].debug_pc, UInt<1>(0h0)) node _T_2227 = mux(_T_614, deq_vec[6][0].debug_pc, UInt<1>(0h0)) node _T_2228 = mux(_T_615, deq_vec[7][0].debug_pc, UInt<1>(0h0)) node _T_2229 = or(_T_2221, _T_2222) node _T_2230 = or(_T_2229, _T_2223) node _T_2231 = or(_T_2230, _T_2224) node _T_2232 = or(_T_2231, _T_2225) node _T_2233 = or(_T_2232, _T_2226) node _T_2234 = or(_T_2233, _T_2227) node _T_2235 = or(_T_2234, _T_2228) wire _WIRE_112 : UInt<40> connect _WIRE_112, _T_2235 connect _WIRE_1.debug_pc, _WIRE_112 node _T_2236 = mux(_T_608, deq_vec[0][0].is_rvc, UInt<1>(0h0)) node _T_2237 = mux(_T_609, deq_vec[1][0].is_rvc, UInt<1>(0h0)) node _T_2238 = mux(_T_610, deq_vec[2][0].is_rvc, UInt<1>(0h0)) node _T_2239 = mux(_T_611, deq_vec[3][0].is_rvc, UInt<1>(0h0)) node _T_2240 = mux(_T_612, deq_vec[4][0].is_rvc, UInt<1>(0h0)) node _T_2241 = mux(_T_613, deq_vec[5][0].is_rvc, UInt<1>(0h0)) node _T_2242 = mux(_T_614, deq_vec[6][0].is_rvc, UInt<1>(0h0)) node _T_2243 = mux(_T_615, deq_vec[7][0].is_rvc, UInt<1>(0h0)) node _T_2244 = or(_T_2236, _T_2237) node _T_2245 = or(_T_2244, _T_2238) node _T_2246 = or(_T_2245, _T_2239) node _T_2247 = or(_T_2246, _T_2240) node _T_2248 = or(_T_2247, _T_2241) node _T_2249 = or(_T_2248, _T_2242) node _T_2250 = or(_T_2249, _T_2243) wire _WIRE_113 : UInt<1> connect _WIRE_113, _T_2250 connect _WIRE_1.is_rvc, _WIRE_113 node _T_2251 = mux(_T_608, deq_vec[0][0].debug_inst, UInt<1>(0h0)) node _T_2252 = mux(_T_609, deq_vec[1][0].debug_inst, UInt<1>(0h0)) node _T_2253 = mux(_T_610, deq_vec[2][0].debug_inst, UInt<1>(0h0)) node _T_2254 = mux(_T_611, deq_vec[3][0].debug_inst, UInt<1>(0h0)) node _T_2255 = mux(_T_612, deq_vec[4][0].debug_inst, UInt<1>(0h0)) node _T_2256 = mux(_T_613, deq_vec[5][0].debug_inst, UInt<1>(0h0)) node _T_2257 = mux(_T_614, deq_vec[6][0].debug_inst, UInt<1>(0h0)) node _T_2258 = mux(_T_615, deq_vec[7][0].debug_inst, UInt<1>(0h0)) node _T_2259 = or(_T_2251, _T_2252) node _T_2260 = or(_T_2259, _T_2253) node _T_2261 = or(_T_2260, _T_2254) node _T_2262 = or(_T_2261, _T_2255) node _T_2263 = or(_T_2262, _T_2256) node _T_2264 = or(_T_2263, _T_2257) node _T_2265 = or(_T_2264, _T_2258) wire _WIRE_114 : UInt<32> connect _WIRE_114, _T_2265 connect _WIRE_1.debug_inst, _WIRE_114 node _T_2266 = mux(_T_608, deq_vec[0][0].inst, UInt<1>(0h0)) node _T_2267 = mux(_T_609, deq_vec[1][0].inst, UInt<1>(0h0)) node _T_2268 = mux(_T_610, deq_vec[2][0].inst, UInt<1>(0h0)) node _T_2269 = mux(_T_611, deq_vec[3][0].inst, UInt<1>(0h0)) node _T_2270 = mux(_T_612, deq_vec[4][0].inst, UInt<1>(0h0)) node _T_2271 = mux(_T_613, deq_vec[5][0].inst, UInt<1>(0h0)) node _T_2272 = mux(_T_614, deq_vec[6][0].inst, UInt<1>(0h0)) node _T_2273 = mux(_T_615, deq_vec[7][0].inst, UInt<1>(0h0)) node _T_2274 = or(_T_2266, _T_2267) node _T_2275 = or(_T_2274, _T_2268) node _T_2276 = or(_T_2275, _T_2269) node _T_2277 = or(_T_2276, _T_2270) node _T_2278 = or(_T_2277, _T_2271) node _T_2279 = or(_T_2278, _T_2272) node _T_2280 = or(_T_2279, _T_2273) wire _WIRE_115 : UInt<32> connect _WIRE_115, _T_2280 connect _WIRE_1.inst, _WIRE_115 connect _WIRE[0], _WIRE_1 wire _WIRE_116 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_2281 = mux(_T_608, deq_vec[0][1].debug_tsrc, UInt<1>(0h0)) node _T_2282 = mux(_T_609, deq_vec[1][1].debug_tsrc, UInt<1>(0h0)) node _T_2283 = mux(_T_610, deq_vec[2][1].debug_tsrc, UInt<1>(0h0)) node _T_2284 = mux(_T_611, deq_vec[3][1].debug_tsrc, UInt<1>(0h0)) node _T_2285 = mux(_T_612, deq_vec[4][1].debug_tsrc, UInt<1>(0h0)) node _T_2286 = mux(_T_613, deq_vec[5][1].debug_tsrc, UInt<1>(0h0)) node _T_2287 = mux(_T_614, deq_vec[6][1].debug_tsrc, UInt<1>(0h0)) node _T_2288 = mux(_T_615, deq_vec[7][1].debug_tsrc, UInt<1>(0h0)) node _T_2289 = or(_T_2281, _T_2282) node _T_2290 = or(_T_2289, _T_2283) node _T_2291 = or(_T_2290, _T_2284) node _T_2292 = or(_T_2291, _T_2285) node _T_2293 = or(_T_2292, _T_2286) node _T_2294 = or(_T_2293, _T_2287) node _T_2295 = or(_T_2294, _T_2288) wire _WIRE_117 : UInt<3> connect _WIRE_117, _T_2295 connect _WIRE_116.debug_tsrc, _WIRE_117 node _T_2296 = mux(_T_608, deq_vec[0][1].debug_fsrc, UInt<1>(0h0)) node _T_2297 = mux(_T_609, deq_vec[1][1].debug_fsrc, UInt<1>(0h0)) node _T_2298 = mux(_T_610, deq_vec[2][1].debug_fsrc, UInt<1>(0h0)) node _T_2299 = mux(_T_611, deq_vec[3][1].debug_fsrc, UInt<1>(0h0)) node _T_2300 = mux(_T_612, deq_vec[4][1].debug_fsrc, UInt<1>(0h0)) node _T_2301 = mux(_T_613, deq_vec[5][1].debug_fsrc, UInt<1>(0h0)) node _T_2302 = mux(_T_614, deq_vec[6][1].debug_fsrc, UInt<1>(0h0)) node _T_2303 = mux(_T_615, deq_vec[7][1].debug_fsrc, UInt<1>(0h0)) node _T_2304 = or(_T_2296, _T_2297) node _T_2305 = or(_T_2304, _T_2298) node _T_2306 = or(_T_2305, _T_2299) node _T_2307 = or(_T_2306, _T_2300) node _T_2308 = or(_T_2307, _T_2301) node _T_2309 = or(_T_2308, _T_2302) node _T_2310 = or(_T_2309, _T_2303) wire _WIRE_118 : UInt<3> connect _WIRE_118, _T_2310 connect _WIRE_116.debug_fsrc, _WIRE_118 node _T_2311 = mux(_T_608, deq_vec[0][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2312 = mux(_T_609, deq_vec[1][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2313 = mux(_T_610, deq_vec[2][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2314 = mux(_T_611, deq_vec[3][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2315 = mux(_T_612, deq_vec[4][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2316 = mux(_T_613, deq_vec[5][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2317 = mux(_T_614, deq_vec[6][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2318 = mux(_T_615, deq_vec[7][1].bp_xcpt_if, UInt<1>(0h0)) node _T_2319 = or(_T_2311, _T_2312) node _T_2320 = or(_T_2319, _T_2313) node _T_2321 = or(_T_2320, _T_2314) node _T_2322 = or(_T_2321, _T_2315) node _T_2323 = or(_T_2322, _T_2316) node _T_2324 = or(_T_2323, _T_2317) node _T_2325 = or(_T_2324, _T_2318) wire _WIRE_119 : UInt<1> connect _WIRE_119, _T_2325 connect _WIRE_116.bp_xcpt_if, _WIRE_119 node _T_2326 = mux(_T_608, deq_vec[0][1].bp_debug_if, UInt<1>(0h0)) node _T_2327 = mux(_T_609, deq_vec[1][1].bp_debug_if, UInt<1>(0h0)) node _T_2328 = mux(_T_610, deq_vec[2][1].bp_debug_if, UInt<1>(0h0)) node _T_2329 = mux(_T_611, deq_vec[3][1].bp_debug_if, UInt<1>(0h0)) node _T_2330 = mux(_T_612, deq_vec[4][1].bp_debug_if, UInt<1>(0h0)) node _T_2331 = mux(_T_613, deq_vec[5][1].bp_debug_if, UInt<1>(0h0)) node _T_2332 = mux(_T_614, deq_vec[6][1].bp_debug_if, UInt<1>(0h0)) node _T_2333 = mux(_T_615, deq_vec[7][1].bp_debug_if, UInt<1>(0h0)) node _T_2334 = or(_T_2326, _T_2327) node _T_2335 = or(_T_2334, _T_2328) node _T_2336 = or(_T_2335, _T_2329) node _T_2337 = or(_T_2336, _T_2330) node _T_2338 = or(_T_2337, _T_2331) node _T_2339 = or(_T_2338, _T_2332) node _T_2340 = or(_T_2339, _T_2333) wire _WIRE_120 : UInt<1> connect _WIRE_120, _T_2340 connect _WIRE_116.bp_debug_if, _WIRE_120 node _T_2341 = mux(_T_608, deq_vec[0][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2342 = mux(_T_609, deq_vec[1][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2343 = mux(_T_610, deq_vec[2][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2344 = mux(_T_611, deq_vec[3][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2345 = mux(_T_612, deq_vec[4][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2346 = mux(_T_613, deq_vec[5][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2347 = mux(_T_614, deq_vec[6][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2348 = mux(_T_615, deq_vec[7][1].xcpt_ma_if, UInt<1>(0h0)) node _T_2349 = or(_T_2341, _T_2342) node _T_2350 = or(_T_2349, _T_2343) node _T_2351 = or(_T_2350, _T_2344) node _T_2352 = or(_T_2351, _T_2345) node _T_2353 = or(_T_2352, _T_2346) node _T_2354 = or(_T_2353, _T_2347) node _T_2355 = or(_T_2354, _T_2348) wire _WIRE_121 : UInt<1> connect _WIRE_121, _T_2355 connect _WIRE_116.xcpt_ma_if, _WIRE_121 node _T_2356 = mux(_T_608, deq_vec[0][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2357 = mux(_T_609, deq_vec[1][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2358 = mux(_T_610, deq_vec[2][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2359 = mux(_T_611, deq_vec[3][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2360 = mux(_T_612, deq_vec[4][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2361 = mux(_T_613, deq_vec[5][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2362 = mux(_T_614, deq_vec[6][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2363 = mux(_T_615, deq_vec[7][1].xcpt_ae_if, UInt<1>(0h0)) node _T_2364 = or(_T_2356, _T_2357) node _T_2365 = or(_T_2364, _T_2358) node _T_2366 = or(_T_2365, _T_2359) node _T_2367 = or(_T_2366, _T_2360) node _T_2368 = or(_T_2367, _T_2361) node _T_2369 = or(_T_2368, _T_2362) node _T_2370 = or(_T_2369, _T_2363) wire _WIRE_122 : UInt<1> connect _WIRE_122, _T_2370 connect _WIRE_116.xcpt_ae_if, _WIRE_122 node _T_2371 = mux(_T_608, deq_vec[0][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2372 = mux(_T_609, deq_vec[1][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2373 = mux(_T_610, deq_vec[2][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2374 = mux(_T_611, deq_vec[3][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2375 = mux(_T_612, deq_vec[4][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2376 = mux(_T_613, deq_vec[5][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2377 = mux(_T_614, deq_vec[6][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2378 = mux(_T_615, deq_vec[7][1].xcpt_pf_if, UInt<1>(0h0)) node _T_2379 = or(_T_2371, _T_2372) node _T_2380 = or(_T_2379, _T_2373) node _T_2381 = or(_T_2380, _T_2374) node _T_2382 = or(_T_2381, _T_2375) node _T_2383 = or(_T_2382, _T_2376) node _T_2384 = or(_T_2383, _T_2377) node _T_2385 = or(_T_2384, _T_2378) wire _WIRE_123 : UInt<1> connect _WIRE_123, _T_2385 connect _WIRE_116.xcpt_pf_if, _WIRE_123 node _T_2386 = mux(_T_608, deq_vec[0][1].fp_typ, UInt<1>(0h0)) node _T_2387 = mux(_T_609, deq_vec[1][1].fp_typ, UInt<1>(0h0)) node _T_2388 = mux(_T_610, deq_vec[2][1].fp_typ, UInt<1>(0h0)) node _T_2389 = mux(_T_611, deq_vec[3][1].fp_typ, UInt<1>(0h0)) node _T_2390 = mux(_T_612, deq_vec[4][1].fp_typ, UInt<1>(0h0)) node _T_2391 = mux(_T_613, deq_vec[5][1].fp_typ, UInt<1>(0h0)) node _T_2392 = mux(_T_614, deq_vec[6][1].fp_typ, UInt<1>(0h0)) node _T_2393 = mux(_T_615, deq_vec[7][1].fp_typ, UInt<1>(0h0)) node _T_2394 = or(_T_2386, _T_2387) node _T_2395 = or(_T_2394, _T_2388) node _T_2396 = or(_T_2395, _T_2389) node _T_2397 = or(_T_2396, _T_2390) node _T_2398 = or(_T_2397, _T_2391) node _T_2399 = or(_T_2398, _T_2392) node _T_2400 = or(_T_2399, _T_2393) wire _WIRE_124 : UInt<2> connect _WIRE_124, _T_2400 connect _WIRE_116.fp_typ, _WIRE_124 node _T_2401 = mux(_T_608, deq_vec[0][1].fp_rm, UInt<1>(0h0)) node _T_2402 = mux(_T_609, deq_vec[1][1].fp_rm, UInt<1>(0h0)) node _T_2403 = mux(_T_610, deq_vec[2][1].fp_rm, UInt<1>(0h0)) node _T_2404 = mux(_T_611, deq_vec[3][1].fp_rm, UInt<1>(0h0)) node _T_2405 = mux(_T_612, deq_vec[4][1].fp_rm, UInt<1>(0h0)) node _T_2406 = mux(_T_613, deq_vec[5][1].fp_rm, UInt<1>(0h0)) node _T_2407 = mux(_T_614, deq_vec[6][1].fp_rm, UInt<1>(0h0)) node _T_2408 = mux(_T_615, deq_vec[7][1].fp_rm, UInt<1>(0h0)) node _T_2409 = or(_T_2401, _T_2402) node _T_2410 = or(_T_2409, _T_2403) node _T_2411 = or(_T_2410, _T_2404) node _T_2412 = or(_T_2411, _T_2405) node _T_2413 = or(_T_2412, _T_2406) node _T_2414 = or(_T_2413, _T_2407) node _T_2415 = or(_T_2414, _T_2408) wire _WIRE_125 : UInt<3> connect _WIRE_125, _T_2415 connect _WIRE_116.fp_rm, _WIRE_125 node _T_2416 = mux(_T_608, deq_vec[0][1].fp_val, UInt<1>(0h0)) node _T_2417 = mux(_T_609, deq_vec[1][1].fp_val, UInt<1>(0h0)) node _T_2418 = mux(_T_610, deq_vec[2][1].fp_val, UInt<1>(0h0)) node _T_2419 = mux(_T_611, deq_vec[3][1].fp_val, UInt<1>(0h0)) node _T_2420 = mux(_T_612, deq_vec[4][1].fp_val, UInt<1>(0h0)) node _T_2421 = mux(_T_613, deq_vec[5][1].fp_val, UInt<1>(0h0)) node _T_2422 = mux(_T_614, deq_vec[6][1].fp_val, UInt<1>(0h0)) node _T_2423 = mux(_T_615, deq_vec[7][1].fp_val, UInt<1>(0h0)) node _T_2424 = or(_T_2416, _T_2417) node _T_2425 = or(_T_2424, _T_2418) node _T_2426 = or(_T_2425, _T_2419) node _T_2427 = or(_T_2426, _T_2420) node _T_2428 = or(_T_2427, _T_2421) node _T_2429 = or(_T_2428, _T_2422) node _T_2430 = or(_T_2429, _T_2423) wire _WIRE_126 : UInt<1> connect _WIRE_126, _T_2430 connect _WIRE_116.fp_val, _WIRE_126 node _T_2431 = mux(_T_608, deq_vec[0][1].fcn_op, UInt<1>(0h0)) node _T_2432 = mux(_T_609, deq_vec[1][1].fcn_op, UInt<1>(0h0)) node _T_2433 = mux(_T_610, deq_vec[2][1].fcn_op, UInt<1>(0h0)) node _T_2434 = mux(_T_611, deq_vec[3][1].fcn_op, UInt<1>(0h0)) node _T_2435 = mux(_T_612, deq_vec[4][1].fcn_op, UInt<1>(0h0)) node _T_2436 = mux(_T_613, deq_vec[5][1].fcn_op, UInt<1>(0h0)) node _T_2437 = mux(_T_614, deq_vec[6][1].fcn_op, UInt<1>(0h0)) node _T_2438 = mux(_T_615, deq_vec[7][1].fcn_op, UInt<1>(0h0)) node _T_2439 = or(_T_2431, _T_2432) node _T_2440 = or(_T_2439, _T_2433) node _T_2441 = or(_T_2440, _T_2434) node _T_2442 = or(_T_2441, _T_2435) node _T_2443 = or(_T_2442, _T_2436) node _T_2444 = or(_T_2443, _T_2437) node _T_2445 = or(_T_2444, _T_2438) wire _WIRE_127 : UInt<5> connect _WIRE_127, _T_2445 connect _WIRE_116.fcn_op, _WIRE_127 node _T_2446 = mux(_T_608, deq_vec[0][1].fcn_dw, UInt<1>(0h0)) node _T_2447 = mux(_T_609, deq_vec[1][1].fcn_dw, UInt<1>(0h0)) node _T_2448 = mux(_T_610, deq_vec[2][1].fcn_dw, UInt<1>(0h0)) node _T_2449 = mux(_T_611, deq_vec[3][1].fcn_dw, UInt<1>(0h0)) node _T_2450 = mux(_T_612, deq_vec[4][1].fcn_dw, UInt<1>(0h0)) node _T_2451 = mux(_T_613, deq_vec[5][1].fcn_dw, UInt<1>(0h0)) node _T_2452 = mux(_T_614, deq_vec[6][1].fcn_dw, UInt<1>(0h0)) node _T_2453 = mux(_T_615, deq_vec[7][1].fcn_dw, UInt<1>(0h0)) node _T_2454 = or(_T_2446, _T_2447) node _T_2455 = or(_T_2454, _T_2448) node _T_2456 = or(_T_2455, _T_2449) node _T_2457 = or(_T_2456, _T_2450) node _T_2458 = or(_T_2457, _T_2451) node _T_2459 = or(_T_2458, _T_2452) node _T_2460 = or(_T_2459, _T_2453) wire _WIRE_128 : UInt<1> connect _WIRE_128, _T_2460 connect _WIRE_116.fcn_dw, _WIRE_128 node _T_2461 = mux(_T_608, deq_vec[0][1].frs3_en, UInt<1>(0h0)) node _T_2462 = mux(_T_609, deq_vec[1][1].frs3_en, UInt<1>(0h0)) node _T_2463 = mux(_T_610, deq_vec[2][1].frs3_en, UInt<1>(0h0)) node _T_2464 = mux(_T_611, deq_vec[3][1].frs3_en, UInt<1>(0h0)) node _T_2465 = mux(_T_612, deq_vec[4][1].frs3_en, UInt<1>(0h0)) node _T_2466 = mux(_T_613, deq_vec[5][1].frs3_en, UInt<1>(0h0)) node _T_2467 = mux(_T_614, deq_vec[6][1].frs3_en, UInt<1>(0h0)) node _T_2468 = mux(_T_615, deq_vec[7][1].frs3_en, UInt<1>(0h0)) node _T_2469 = or(_T_2461, _T_2462) node _T_2470 = or(_T_2469, _T_2463) node _T_2471 = or(_T_2470, _T_2464) node _T_2472 = or(_T_2471, _T_2465) node _T_2473 = or(_T_2472, _T_2466) node _T_2474 = or(_T_2473, _T_2467) node _T_2475 = or(_T_2474, _T_2468) wire _WIRE_129 : UInt<1> connect _WIRE_129, _T_2475 connect _WIRE_116.frs3_en, _WIRE_129 node _T_2476 = mux(_T_608, deq_vec[0][1].lrs2_rtype, UInt<1>(0h0)) node _T_2477 = mux(_T_609, deq_vec[1][1].lrs2_rtype, UInt<1>(0h0)) node _T_2478 = mux(_T_610, deq_vec[2][1].lrs2_rtype, UInt<1>(0h0)) node _T_2479 = mux(_T_611, deq_vec[3][1].lrs2_rtype, UInt<1>(0h0)) node _T_2480 = mux(_T_612, deq_vec[4][1].lrs2_rtype, UInt<1>(0h0)) node _T_2481 = mux(_T_613, deq_vec[5][1].lrs2_rtype, UInt<1>(0h0)) node _T_2482 = mux(_T_614, deq_vec[6][1].lrs2_rtype, UInt<1>(0h0)) node _T_2483 = mux(_T_615, deq_vec[7][1].lrs2_rtype, UInt<1>(0h0)) node _T_2484 = or(_T_2476, _T_2477) node _T_2485 = or(_T_2484, _T_2478) node _T_2486 = or(_T_2485, _T_2479) node _T_2487 = or(_T_2486, _T_2480) node _T_2488 = or(_T_2487, _T_2481) node _T_2489 = or(_T_2488, _T_2482) node _T_2490 = or(_T_2489, _T_2483) wire _WIRE_130 : UInt<2> connect _WIRE_130, _T_2490 connect _WIRE_116.lrs2_rtype, _WIRE_130 node _T_2491 = mux(_T_608, deq_vec[0][1].lrs1_rtype, UInt<1>(0h0)) node _T_2492 = mux(_T_609, deq_vec[1][1].lrs1_rtype, UInt<1>(0h0)) node _T_2493 = mux(_T_610, deq_vec[2][1].lrs1_rtype, UInt<1>(0h0)) node _T_2494 = mux(_T_611, deq_vec[3][1].lrs1_rtype, UInt<1>(0h0)) node _T_2495 = mux(_T_612, deq_vec[4][1].lrs1_rtype, UInt<1>(0h0)) node _T_2496 = mux(_T_613, deq_vec[5][1].lrs1_rtype, UInt<1>(0h0)) node _T_2497 = mux(_T_614, deq_vec[6][1].lrs1_rtype, UInt<1>(0h0)) node _T_2498 = mux(_T_615, deq_vec[7][1].lrs1_rtype, UInt<1>(0h0)) node _T_2499 = or(_T_2491, _T_2492) node _T_2500 = or(_T_2499, _T_2493) node _T_2501 = or(_T_2500, _T_2494) node _T_2502 = or(_T_2501, _T_2495) node _T_2503 = or(_T_2502, _T_2496) node _T_2504 = or(_T_2503, _T_2497) node _T_2505 = or(_T_2504, _T_2498) wire _WIRE_131 : UInt<2> connect _WIRE_131, _T_2505 connect _WIRE_116.lrs1_rtype, _WIRE_131 node _T_2506 = mux(_T_608, deq_vec[0][1].dst_rtype, UInt<1>(0h0)) node _T_2507 = mux(_T_609, deq_vec[1][1].dst_rtype, UInt<1>(0h0)) node _T_2508 = mux(_T_610, deq_vec[2][1].dst_rtype, UInt<1>(0h0)) node _T_2509 = mux(_T_611, deq_vec[3][1].dst_rtype, UInt<1>(0h0)) node _T_2510 = mux(_T_612, deq_vec[4][1].dst_rtype, UInt<1>(0h0)) node _T_2511 = mux(_T_613, deq_vec[5][1].dst_rtype, UInt<1>(0h0)) node _T_2512 = mux(_T_614, deq_vec[6][1].dst_rtype, UInt<1>(0h0)) node _T_2513 = mux(_T_615, deq_vec[7][1].dst_rtype, UInt<1>(0h0)) node _T_2514 = or(_T_2506, _T_2507) node _T_2515 = or(_T_2514, _T_2508) node _T_2516 = or(_T_2515, _T_2509) node _T_2517 = or(_T_2516, _T_2510) node _T_2518 = or(_T_2517, _T_2511) node _T_2519 = or(_T_2518, _T_2512) node _T_2520 = or(_T_2519, _T_2513) wire _WIRE_132 : UInt<2> connect _WIRE_132, _T_2520 connect _WIRE_116.dst_rtype, _WIRE_132 node _T_2521 = mux(_T_608, deq_vec[0][1].lrs3, UInt<1>(0h0)) node _T_2522 = mux(_T_609, deq_vec[1][1].lrs3, UInt<1>(0h0)) node _T_2523 = mux(_T_610, deq_vec[2][1].lrs3, UInt<1>(0h0)) node _T_2524 = mux(_T_611, deq_vec[3][1].lrs3, UInt<1>(0h0)) node _T_2525 = mux(_T_612, deq_vec[4][1].lrs3, UInt<1>(0h0)) node _T_2526 = mux(_T_613, deq_vec[5][1].lrs3, UInt<1>(0h0)) node _T_2527 = mux(_T_614, deq_vec[6][1].lrs3, UInt<1>(0h0)) node _T_2528 = mux(_T_615, deq_vec[7][1].lrs3, UInt<1>(0h0)) node _T_2529 = or(_T_2521, _T_2522) node _T_2530 = or(_T_2529, _T_2523) node _T_2531 = or(_T_2530, _T_2524) node _T_2532 = or(_T_2531, _T_2525) node _T_2533 = or(_T_2532, _T_2526) node _T_2534 = or(_T_2533, _T_2527) node _T_2535 = or(_T_2534, _T_2528) wire _WIRE_133 : UInt<6> connect _WIRE_133, _T_2535 connect _WIRE_116.lrs3, _WIRE_133 node _T_2536 = mux(_T_608, deq_vec[0][1].lrs2, UInt<1>(0h0)) node _T_2537 = mux(_T_609, deq_vec[1][1].lrs2, UInt<1>(0h0)) node _T_2538 = mux(_T_610, deq_vec[2][1].lrs2, UInt<1>(0h0)) node _T_2539 = mux(_T_611, deq_vec[3][1].lrs2, UInt<1>(0h0)) node _T_2540 = mux(_T_612, deq_vec[4][1].lrs2, UInt<1>(0h0)) node _T_2541 = mux(_T_613, deq_vec[5][1].lrs2, UInt<1>(0h0)) node _T_2542 = mux(_T_614, deq_vec[6][1].lrs2, UInt<1>(0h0)) node _T_2543 = mux(_T_615, deq_vec[7][1].lrs2, UInt<1>(0h0)) node _T_2544 = or(_T_2536, _T_2537) node _T_2545 = or(_T_2544, _T_2538) node _T_2546 = or(_T_2545, _T_2539) node _T_2547 = or(_T_2546, _T_2540) node _T_2548 = or(_T_2547, _T_2541) node _T_2549 = or(_T_2548, _T_2542) node _T_2550 = or(_T_2549, _T_2543) wire _WIRE_134 : UInt<6> connect _WIRE_134, _T_2550 connect _WIRE_116.lrs2, _WIRE_134 node _T_2551 = mux(_T_608, deq_vec[0][1].lrs1, UInt<1>(0h0)) node _T_2552 = mux(_T_609, deq_vec[1][1].lrs1, UInt<1>(0h0)) node _T_2553 = mux(_T_610, deq_vec[2][1].lrs1, UInt<1>(0h0)) node _T_2554 = mux(_T_611, deq_vec[3][1].lrs1, UInt<1>(0h0)) node _T_2555 = mux(_T_612, deq_vec[4][1].lrs1, UInt<1>(0h0)) node _T_2556 = mux(_T_613, deq_vec[5][1].lrs1, UInt<1>(0h0)) node _T_2557 = mux(_T_614, deq_vec[6][1].lrs1, UInt<1>(0h0)) node _T_2558 = mux(_T_615, deq_vec[7][1].lrs1, UInt<1>(0h0)) node _T_2559 = or(_T_2551, _T_2552) node _T_2560 = or(_T_2559, _T_2553) node _T_2561 = or(_T_2560, _T_2554) node _T_2562 = or(_T_2561, _T_2555) node _T_2563 = or(_T_2562, _T_2556) node _T_2564 = or(_T_2563, _T_2557) node _T_2565 = or(_T_2564, _T_2558) wire _WIRE_135 : UInt<6> connect _WIRE_135, _T_2565 connect _WIRE_116.lrs1, _WIRE_135 node _T_2566 = mux(_T_608, deq_vec[0][1].ldst, UInt<1>(0h0)) node _T_2567 = mux(_T_609, deq_vec[1][1].ldst, UInt<1>(0h0)) node _T_2568 = mux(_T_610, deq_vec[2][1].ldst, UInt<1>(0h0)) node _T_2569 = mux(_T_611, deq_vec[3][1].ldst, UInt<1>(0h0)) node _T_2570 = mux(_T_612, deq_vec[4][1].ldst, UInt<1>(0h0)) node _T_2571 = mux(_T_613, deq_vec[5][1].ldst, UInt<1>(0h0)) node _T_2572 = mux(_T_614, deq_vec[6][1].ldst, UInt<1>(0h0)) node _T_2573 = mux(_T_615, deq_vec[7][1].ldst, UInt<1>(0h0)) node _T_2574 = or(_T_2566, _T_2567) node _T_2575 = or(_T_2574, _T_2568) node _T_2576 = or(_T_2575, _T_2569) node _T_2577 = or(_T_2576, _T_2570) node _T_2578 = or(_T_2577, _T_2571) node _T_2579 = or(_T_2578, _T_2572) node _T_2580 = or(_T_2579, _T_2573) wire _WIRE_136 : UInt<6> connect _WIRE_136, _T_2580 connect _WIRE_116.ldst, _WIRE_136 node _T_2581 = mux(_T_608, deq_vec[0][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2582 = mux(_T_609, deq_vec[1][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2583 = mux(_T_610, deq_vec[2][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2584 = mux(_T_611, deq_vec[3][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2585 = mux(_T_612, deq_vec[4][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2586 = mux(_T_613, deq_vec[5][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2587 = mux(_T_614, deq_vec[6][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2588 = mux(_T_615, deq_vec[7][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2589 = or(_T_2581, _T_2582) node _T_2590 = or(_T_2589, _T_2583) node _T_2591 = or(_T_2590, _T_2584) node _T_2592 = or(_T_2591, _T_2585) node _T_2593 = or(_T_2592, _T_2586) node _T_2594 = or(_T_2593, _T_2587) node _T_2595 = or(_T_2594, _T_2588) wire _WIRE_137 : UInt<1> connect _WIRE_137, _T_2595 connect _WIRE_116.ldst_is_rs1, _WIRE_137 node _T_2596 = mux(_T_608, deq_vec[0][1].csr_cmd, UInt<1>(0h0)) node _T_2597 = mux(_T_609, deq_vec[1][1].csr_cmd, UInt<1>(0h0)) node _T_2598 = mux(_T_610, deq_vec[2][1].csr_cmd, UInt<1>(0h0)) node _T_2599 = mux(_T_611, deq_vec[3][1].csr_cmd, UInt<1>(0h0)) node _T_2600 = mux(_T_612, deq_vec[4][1].csr_cmd, UInt<1>(0h0)) node _T_2601 = mux(_T_613, deq_vec[5][1].csr_cmd, UInt<1>(0h0)) node _T_2602 = mux(_T_614, deq_vec[6][1].csr_cmd, UInt<1>(0h0)) node _T_2603 = mux(_T_615, deq_vec[7][1].csr_cmd, UInt<1>(0h0)) node _T_2604 = or(_T_2596, _T_2597) node _T_2605 = or(_T_2604, _T_2598) node _T_2606 = or(_T_2605, _T_2599) node _T_2607 = or(_T_2606, _T_2600) node _T_2608 = or(_T_2607, _T_2601) node _T_2609 = or(_T_2608, _T_2602) node _T_2610 = or(_T_2609, _T_2603) wire _WIRE_138 : UInt<3> connect _WIRE_138, _T_2610 connect _WIRE_116.csr_cmd, _WIRE_138 node _T_2611 = mux(_T_608, deq_vec[0][1].flush_on_commit, UInt<1>(0h0)) node _T_2612 = mux(_T_609, deq_vec[1][1].flush_on_commit, UInt<1>(0h0)) node _T_2613 = mux(_T_610, deq_vec[2][1].flush_on_commit, UInt<1>(0h0)) node _T_2614 = mux(_T_611, deq_vec[3][1].flush_on_commit, UInt<1>(0h0)) node _T_2615 = mux(_T_612, deq_vec[4][1].flush_on_commit, UInt<1>(0h0)) node _T_2616 = mux(_T_613, deq_vec[5][1].flush_on_commit, UInt<1>(0h0)) node _T_2617 = mux(_T_614, deq_vec[6][1].flush_on_commit, UInt<1>(0h0)) node _T_2618 = mux(_T_615, deq_vec[7][1].flush_on_commit, UInt<1>(0h0)) node _T_2619 = or(_T_2611, _T_2612) node _T_2620 = or(_T_2619, _T_2613) node _T_2621 = or(_T_2620, _T_2614) node _T_2622 = or(_T_2621, _T_2615) node _T_2623 = or(_T_2622, _T_2616) node _T_2624 = or(_T_2623, _T_2617) node _T_2625 = or(_T_2624, _T_2618) wire _WIRE_139 : UInt<1> connect _WIRE_139, _T_2625 connect _WIRE_116.flush_on_commit, _WIRE_139 node _T_2626 = mux(_T_608, deq_vec[0][1].is_unique, UInt<1>(0h0)) node _T_2627 = mux(_T_609, deq_vec[1][1].is_unique, UInt<1>(0h0)) node _T_2628 = mux(_T_610, deq_vec[2][1].is_unique, UInt<1>(0h0)) node _T_2629 = mux(_T_611, deq_vec[3][1].is_unique, UInt<1>(0h0)) node _T_2630 = mux(_T_612, deq_vec[4][1].is_unique, UInt<1>(0h0)) node _T_2631 = mux(_T_613, deq_vec[5][1].is_unique, UInt<1>(0h0)) node _T_2632 = mux(_T_614, deq_vec[6][1].is_unique, UInt<1>(0h0)) node _T_2633 = mux(_T_615, deq_vec[7][1].is_unique, UInt<1>(0h0)) node _T_2634 = or(_T_2626, _T_2627) node _T_2635 = or(_T_2634, _T_2628) node _T_2636 = or(_T_2635, _T_2629) node _T_2637 = or(_T_2636, _T_2630) node _T_2638 = or(_T_2637, _T_2631) node _T_2639 = or(_T_2638, _T_2632) node _T_2640 = or(_T_2639, _T_2633) wire _WIRE_140 : UInt<1> connect _WIRE_140, _T_2640 connect _WIRE_116.is_unique, _WIRE_140 node _T_2641 = mux(_T_608, deq_vec[0][1].uses_stq, UInt<1>(0h0)) node _T_2642 = mux(_T_609, deq_vec[1][1].uses_stq, UInt<1>(0h0)) node _T_2643 = mux(_T_610, deq_vec[2][1].uses_stq, UInt<1>(0h0)) node _T_2644 = mux(_T_611, deq_vec[3][1].uses_stq, UInt<1>(0h0)) node _T_2645 = mux(_T_612, deq_vec[4][1].uses_stq, UInt<1>(0h0)) node _T_2646 = mux(_T_613, deq_vec[5][1].uses_stq, UInt<1>(0h0)) node _T_2647 = mux(_T_614, deq_vec[6][1].uses_stq, UInt<1>(0h0)) node _T_2648 = mux(_T_615, deq_vec[7][1].uses_stq, UInt<1>(0h0)) node _T_2649 = or(_T_2641, _T_2642) node _T_2650 = or(_T_2649, _T_2643) node _T_2651 = or(_T_2650, _T_2644) node _T_2652 = or(_T_2651, _T_2645) node _T_2653 = or(_T_2652, _T_2646) node _T_2654 = or(_T_2653, _T_2647) node _T_2655 = or(_T_2654, _T_2648) wire _WIRE_141 : UInt<1> connect _WIRE_141, _T_2655 connect _WIRE_116.uses_stq, _WIRE_141 node _T_2656 = mux(_T_608, deq_vec[0][1].uses_ldq, UInt<1>(0h0)) node _T_2657 = mux(_T_609, deq_vec[1][1].uses_ldq, UInt<1>(0h0)) node _T_2658 = mux(_T_610, deq_vec[2][1].uses_ldq, UInt<1>(0h0)) node _T_2659 = mux(_T_611, deq_vec[3][1].uses_ldq, UInt<1>(0h0)) node _T_2660 = mux(_T_612, deq_vec[4][1].uses_ldq, UInt<1>(0h0)) node _T_2661 = mux(_T_613, deq_vec[5][1].uses_ldq, UInt<1>(0h0)) node _T_2662 = mux(_T_614, deq_vec[6][1].uses_ldq, UInt<1>(0h0)) node _T_2663 = mux(_T_615, deq_vec[7][1].uses_ldq, UInt<1>(0h0)) node _T_2664 = or(_T_2656, _T_2657) node _T_2665 = or(_T_2664, _T_2658) node _T_2666 = or(_T_2665, _T_2659) node _T_2667 = or(_T_2666, _T_2660) node _T_2668 = or(_T_2667, _T_2661) node _T_2669 = or(_T_2668, _T_2662) node _T_2670 = or(_T_2669, _T_2663) wire _WIRE_142 : UInt<1> connect _WIRE_142, _T_2670 connect _WIRE_116.uses_ldq, _WIRE_142 node _T_2671 = mux(_T_608, deq_vec[0][1].mem_signed, UInt<1>(0h0)) node _T_2672 = mux(_T_609, deq_vec[1][1].mem_signed, UInt<1>(0h0)) node _T_2673 = mux(_T_610, deq_vec[2][1].mem_signed, UInt<1>(0h0)) node _T_2674 = mux(_T_611, deq_vec[3][1].mem_signed, UInt<1>(0h0)) node _T_2675 = mux(_T_612, deq_vec[4][1].mem_signed, UInt<1>(0h0)) node _T_2676 = mux(_T_613, deq_vec[5][1].mem_signed, UInt<1>(0h0)) node _T_2677 = mux(_T_614, deq_vec[6][1].mem_signed, UInt<1>(0h0)) node _T_2678 = mux(_T_615, deq_vec[7][1].mem_signed, UInt<1>(0h0)) node _T_2679 = or(_T_2671, _T_2672) node _T_2680 = or(_T_2679, _T_2673) node _T_2681 = or(_T_2680, _T_2674) node _T_2682 = or(_T_2681, _T_2675) node _T_2683 = or(_T_2682, _T_2676) node _T_2684 = or(_T_2683, _T_2677) node _T_2685 = or(_T_2684, _T_2678) wire _WIRE_143 : UInt<1> connect _WIRE_143, _T_2685 connect _WIRE_116.mem_signed, _WIRE_143 node _T_2686 = mux(_T_608, deq_vec[0][1].mem_size, UInt<1>(0h0)) node _T_2687 = mux(_T_609, deq_vec[1][1].mem_size, UInt<1>(0h0)) node _T_2688 = mux(_T_610, deq_vec[2][1].mem_size, UInt<1>(0h0)) node _T_2689 = mux(_T_611, deq_vec[3][1].mem_size, UInt<1>(0h0)) node _T_2690 = mux(_T_612, deq_vec[4][1].mem_size, UInt<1>(0h0)) node _T_2691 = mux(_T_613, deq_vec[5][1].mem_size, UInt<1>(0h0)) node _T_2692 = mux(_T_614, deq_vec[6][1].mem_size, UInt<1>(0h0)) node _T_2693 = mux(_T_615, deq_vec[7][1].mem_size, UInt<1>(0h0)) node _T_2694 = or(_T_2686, _T_2687) node _T_2695 = or(_T_2694, _T_2688) node _T_2696 = or(_T_2695, _T_2689) node _T_2697 = or(_T_2696, _T_2690) node _T_2698 = or(_T_2697, _T_2691) node _T_2699 = or(_T_2698, _T_2692) node _T_2700 = or(_T_2699, _T_2693) wire _WIRE_144 : UInt<2> connect _WIRE_144, _T_2700 connect _WIRE_116.mem_size, _WIRE_144 node _T_2701 = mux(_T_608, deq_vec[0][1].mem_cmd, UInt<1>(0h0)) node _T_2702 = mux(_T_609, deq_vec[1][1].mem_cmd, UInt<1>(0h0)) node _T_2703 = mux(_T_610, deq_vec[2][1].mem_cmd, UInt<1>(0h0)) node _T_2704 = mux(_T_611, deq_vec[3][1].mem_cmd, UInt<1>(0h0)) node _T_2705 = mux(_T_612, deq_vec[4][1].mem_cmd, UInt<1>(0h0)) node _T_2706 = mux(_T_613, deq_vec[5][1].mem_cmd, UInt<1>(0h0)) node _T_2707 = mux(_T_614, deq_vec[6][1].mem_cmd, UInt<1>(0h0)) node _T_2708 = mux(_T_615, deq_vec[7][1].mem_cmd, UInt<1>(0h0)) node _T_2709 = or(_T_2701, _T_2702) node _T_2710 = or(_T_2709, _T_2703) node _T_2711 = or(_T_2710, _T_2704) node _T_2712 = or(_T_2711, _T_2705) node _T_2713 = or(_T_2712, _T_2706) node _T_2714 = or(_T_2713, _T_2707) node _T_2715 = or(_T_2714, _T_2708) wire _WIRE_145 : UInt<5> connect _WIRE_145, _T_2715 connect _WIRE_116.mem_cmd, _WIRE_145 node _T_2716 = mux(_T_608, deq_vec[0][1].exc_cause, UInt<1>(0h0)) node _T_2717 = mux(_T_609, deq_vec[1][1].exc_cause, UInt<1>(0h0)) node _T_2718 = mux(_T_610, deq_vec[2][1].exc_cause, UInt<1>(0h0)) node _T_2719 = mux(_T_611, deq_vec[3][1].exc_cause, UInt<1>(0h0)) node _T_2720 = mux(_T_612, deq_vec[4][1].exc_cause, UInt<1>(0h0)) node _T_2721 = mux(_T_613, deq_vec[5][1].exc_cause, UInt<1>(0h0)) node _T_2722 = mux(_T_614, deq_vec[6][1].exc_cause, UInt<1>(0h0)) node _T_2723 = mux(_T_615, deq_vec[7][1].exc_cause, UInt<1>(0h0)) node _T_2724 = or(_T_2716, _T_2717) node _T_2725 = or(_T_2724, _T_2718) node _T_2726 = or(_T_2725, _T_2719) node _T_2727 = or(_T_2726, _T_2720) node _T_2728 = or(_T_2727, _T_2721) node _T_2729 = or(_T_2728, _T_2722) node _T_2730 = or(_T_2729, _T_2723) wire _WIRE_146 : UInt<64> connect _WIRE_146, _T_2730 connect _WIRE_116.exc_cause, _WIRE_146 node _T_2731 = mux(_T_608, deq_vec[0][1].exception, UInt<1>(0h0)) node _T_2732 = mux(_T_609, deq_vec[1][1].exception, UInt<1>(0h0)) node _T_2733 = mux(_T_610, deq_vec[2][1].exception, UInt<1>(0h0)) node _T_2734 = mux(_T_611, deq_vec[3][1].exception, UInt<1>(0h0)) node _T_2735 = mux(_T_612, deq_vec[4][1].exception, UInt<1>(0h0)) node _T_2736 = mux(_T_613, deq_vec[5][1].exception, UInt<1>(0h0)) node _T_2737 = mux(_T_614, deq_vec[6][1].exception, UInt<1>(0h0)) node _T_2738 = mux(_T_615, deq_vec[7][1].exception, UInt<1>(0h0)) node _T_2739 = or(_T_2731, _T_2732) node _T_2740 = or(_T_2739, _T_2733) node _T_2741 = or(_T_2740, _T_2734) node _T_2742 = or(_T_2741, _T_2735) node _T_2743 = or(_T_2742, _T_2736) node _T_2744 = or(_T_2743, _T_2737) node _T_2745 = or(_T_2744, _T_2738) wire _WIRE_147 : UInt<1> connect _WIRE_147, _T_2745 connect _WIRE_116.exception, _WIRE_147 node _T_2746 = mux(_T_608, deq_vec[0][1].stale_pdst, UInt<1>(0h0)) node _T_2747 = mux(_T_609, deq_vec[1][1].stale_pdst, UInt<1>(0h0)) node _T_2748 = mux(_T_610, deq_vec[2][1].stale_pdst, UInt<1>(0h0)) node _T_2749 = mux(_T_611, deq_vec[3][1].stale_pdst, UInt<1>(0h0)) node _T_2750 = mux(_T_612, deq_vec[4][1].stale_pdst, UInt<1>(0h0)) node _T_2751 = mux(_T_613, deq_vec[5][1].stale_pdst, UInt<1>(0h0)) node _T_2752 = mux(_T_614, deq_vec[6][1].stale_pdst, UInt<1>(0h0)) node _T_2753 = mux(_T_615, deq_vec[7][1].stale_pdst, UInt<1>(0h0)) node _T_2754 = or(_T_2746, _T_2747) node _T_2755 = or(_T_2754, _T_2748) node _T_2756 = or(_T_2755, _T_2749) node _T_2757 = or(_T_2756, _T_2750) node _T_2758 = or(_T_2757, _T_2751) node _T_2759 = or(_T_2758, _T_2752) node _T_2760 = or(_T_2759, _T_2753) wire _WIRE_148 : UInt<7> connect _WIRE_148, _T_2760 connect _WIRE_116.stale_pdst, _WIRE_148 node _T_2761 = mux(_T_608, deq_vec[0][1].ppred_busy, UInt<1>(0h0)) node _T_2762 = mux(_T_609, deq_vec[1][1].ppred_busy, UInt<1>(0h0)) node _T_2763 = mux(_T_610, deq_vec[2][1].ppred_busy, UInt<1>(0h0)) node _T_2764 = mux(_T_611, deq_vec[3][1].ppred_busy, UInt<1>(0h0)) node _T_2765 = mux(_T_612, deq_vec[4][1].ppred_busy, UInt<1>(0h0)) node _T_2766 = mux(_T_613, deq_vec[5][1].ppred_busy, UInt<1>(0h0)) node _T_2767 = mux(_T_614, deq_vec[6][1].ppred_busy, UInt<1>(0h0)) node _T_2768 = mux(_T_615, deq_vec[7][1].ppred_busy, UInt<1>(0h0)) node _T_2769 = or(_T_2761, _T_2762) node _T_2770 = or(_T_2769, _T_2763) node _T_2771 = or(_T_2770, _T_2764) node _T_2772 = or(_T_2771, _T_2765) node _T_2773 = or(_T_2772, _T_2766) node _T_2774 = or(_T_2773, _T_2767) node _T_2775 = or(_T_2774, _T_2768) wire _WIRE_149 : UInt<1> connect _WIRE_149, _T_2775 connect _WIRE_116.ppred_busy, _WIRE_149 node _T_2776 = mux(_T_608, deq_vec[0][1].prs3_busy, UInt<1>(0h0)) node _T_2777 = mux(_T_609, deq_vec[1][1].prs3_busy, UInt<1>(0h0)) node _T_2778 = mux(_T_610, deq_vec[2][1].prs3_busy, UInt<1>(0h0)) node _T_2779 = mux(_T_611, deq_vec[3][1].prs3_busy, UInt<1>(0h0)) node _T_2780 = mux(_T_612, deq_vec[4][1].prs3_busy, UInt<1>(0h0)) node _T_2781 = mux(_T_613, deq_vec[5][1].prs3_busy, UInt<1>(0h0)) node _T_2782 = mux(_T_614, deq_vec[6][1].prs3_busy, UInt<1>(0h0)) node _T_2783 = mux(_T_615, deq_vec[7][1].prs3_busy, UInt<1>(0h0)) node _T_2784 = or(_T_2776, _T_2777) node _T_2785 = or(_T_2784, _T_2778) node _T_2786 = or(_T_2785, _T_2779) node _T_2787 = or(_T_2786, _T_2780) node _T_2788 = or(_T_2787, _T_2781) node _T_2789 = or(_T_2788, _T_2782) node _T_2790 = or(_T_2789, _T_2783) wire _WIRE_150 : UInt<1> connect _WIRE_150, _T_2790 connect _WIRE_116.prs3_busy, _WIRE_150 node _T_2791 = mux(_T_608, deq_vec[0][1].prs2_busy, UInt<1>(0h0)) node _T_2792 = mux(_T_609, deq_vec[1][1].prs2_busy, UInt<1>(0h0)) node _T_2793 = mux(_T_610, deq_vec[2][1].prs2_busy, UInt<1>(0h0)) node _T_2794 = mux(_T_611, deq_vec[3][1].prs2_busy, UInt<1>(0h0)) node _T_2795 = mux(_T_612, deq_vec[4][1].prs2_busy, UInt<1>(0h0)) node _T_2796 = mux(_T_613, deq_vec[5][1].prs2_busy, UInt<1>(0h0)) node _T_2797 = mux(_T_614, deq_vec[6][1].prs2_busy, UInt<1>(0h0)) node _T_2798 = mux(_T_615, deq_vec[7][1].prs2_busy, UInt<1>(0h0)) node _T_2799 = or(_T_2791, _T_2792) node _T_2800 = or(_T_2799, _T_2793) node _T_2801 = or(_T_2800, _T_2794) node _T_2802 = or(_T_2801, _T_2795) node _T_2803 = or(_T_2802, _T_2796) node _T_2804 = or(_T_2803, _T_2797) node _T_2805 = or(_T_2804, _T_2798) wire _WIRE_151 : UInt<1> connect _WIRE_151, _T_2805 connect _WIRE_116.prs2_busy, _WIRE_151 node _T_2806 = mux(_T_608, deq_vec[0][1].prs1_busy, UInt<1>(0h0)) node _T_2807 = mux(_T_609, deq_vec[1][1].prs1_busy, UInt<1>(0h0)) node _T_2808 = mux(_T_610, deq_vec[2][1].prs1_busy, UInt<1>(0h0)) node _T_2809 = mux(_T_611, deq_vec[3][1].prs1_busy, UInt<1>(0h0)) node _T_2810 = mux(_T_612, deq_vec[4][1].prs1_busy, UInt<1>(0h0)) node _T_2811 = mux(_T_613, deq_vec[5][1].prs1_busy, UInt<1>(0h0)) node _T_2812 = mux(_T_614, deq_vec[6][1].prs1_busy, UInt<1>(0h0)) node _T_2813 = mux(_T_615, deq_vec[7][1].prs1_busy, UInt<1>(0h0)) node _T_2814 = or(_T_2806, _T_2807) node _T_2815 = or(_T_2814, _T_2808) node _T_2816 = or(_T_2815, _T_2809) node _T_2817 = or(_T_2816, _T_2810) node _T_2818 = or(_T_2817, _T_2811) node _T_2819 = or(_T_2818, _T_2812) node _T_2820 = or(_T_2819, _T_2813) wire _WIRE_152 : UInt<1> connect _WIRE_152, _T_2820 connect _WIRE_116.prs1_busy, _WIRE_152 node _T_2821 = mux(_T_608, deq_vec[0][1].ppred, UInt<1>(0h0)) node _T_2822 = mux(_T_609, deq_vec[1][1].ppred, UInt<1>(0h0)) node _T_2823 = mux(_T_610, deq_vec[2][1].ppred, UInt<1>(0h0)) node _T_2824 = mux(_T_611, deq_vec[3][1].ppred, UInt<1>(0h0)) node _T_2825 = mux(_T_612, deq_vec[4][1].ppred, UInt<1>(0h0)) node _T_2826 = mux(_T_613, deq_vec[5][1].ppred, UInt<1>(0h0)) node _T_2827 = mux(_T_614, deq_vec[6][1].ppred, UInt<1>(0h0)) node _T_2828 = mux(_T_615, deq_vec[7][1].ppred, UInt<1>(0h0)) node _T_2829 = or(_T_2821, _T_2822) node _T_2830 = or(_T_2829, _T_2823) node _T_2831 = or(_T_2830, _T_2824) node _T_2832 = or(_T_2831, _T_2825) node _T_2833 = or(_T_2832, _T_2826) node _T_2834 = or(_T_2833, _T_2827) node _T_2835 = or(_T_2834, _T_2828) wire _WIRE_153 : UInt<5> connect _WIRE_153, _T_2835 connect _WIRE_116.ppred, _WIRE_153 node _T_2836 = mux(_T_608, deq_vec[0][1].prs3, UInt<1>(0h0)) node _T_2837 = mux(_T_609, deq_vec[1][1].prs3, UInt<1>(0h0)) node _T_2838 = mux(_T_610, deq_vec[2][1].prs3, UInt<1>(0h0)) node _T_2839 = mux(_T_611, deq_vec[3][1].prs3, UInt<1>(0h0)) node _T_2840 = mux(_T_612, deq_vec[4][1].prs3, UInt<1>(0h0)) node _T_2841 = mux(_T_613, deq_vec[5][1].prs3, UInt<1>(0h0)) node _T_2842 = mux(_T_614, deq_vec[6][1].prs3, UInt<1>(0h0)) node _T_2843 = mux(_T_615, deq_vec[7][1].prs3, UInt<1>(0h0)) node _T_2844 = or(_T_2836, _T_2837) node _T_2845 = or(_T_2844, _T_2838) node _T_2846 = or(_T_2845, _T_2839) node _T_2847 = or(_T_2846, _T_2840) node _T_2848 = or(_T_2847, _T_2841) node _T_2849 = or(_T_2848, _T_2842) node _T_2850 = or(_T_2849, _T_2843) wire _WIRE_154 : UInt<7> connect _WIRE_154, _T_2850 connect _WIRE_116.prs3, _WIRE_154 node _T_2851 = mux(_T_608, deq_vec[0][1].prs2, UInt<1>(0h0)) node _T_2852 = mux(_T_609, deq_vec[1][1].prs2, UInt<1>(0h0)) node _T_2853 = mux(_T_610, deq_vec[2][1].prs2, UInt<1>(0h0)) node _T_2854 = mux(_T_611, deq_vec[3][1].prs2, UInt<1>(0h0)) node _T_2855 = mux(_T_612, deq_vec[4][1].prs2, UInt<1>(0h0)) node _T_2856 = mux(_T_613, deq_vec[5][1].prs2, UInt<1>(0h0)) node _T_2857 = mux(_T_614, deq_vec[6][1].prs2, UInt<1>(0h0)) node _T_2858 = mux(_T_615, deq_vec[7][1].prs2, UInt<1>(0h0)) node _T_2859 = or(_T_2851, _T_2852) node _T_2860 = or(_T_2859, _T_2853) node _T_2861 = or(_T_2860, _T_2854) node _T_2862 = or(_T_2861, _T_2855) node _T_2863 = or(_T_2862, _T_2856) node _T_2864 = or(_T_2863, _T_2857) node _T_2865 = or(_T_2864, _T_2858) wire _WIRE_155 : UInt<7> connect _WIRE_155, _T_2865 connect _WIRE_116.prs2, _WIRE_155 node _T_2866 = mux(_T_608, deq_vec[0][1].prs1, UInt<1>(0h0)) node _T_2867 = mux(_T_609, deq_vec[1][1].prs1, UInt<1>(0h0)) node _T_2868 = mux(_T_610, deq_vec[2][1].prs1, UInt<1>(0h0)) node _T_2869 = mux(_T_611, deq_vec[3][1].prs1, UInt<1>(0h0)) node _T_2870 = mux(_T_612, deq_vec[4][1].prs1, UInt<1>(0h0)) node _T_2871 = mux(_T_613, deq_vec[5][1].prs1, UInt<1>(0h0)) node _T_2872 = mux(_T_614, deq_vec[6][1].prs1, UInt<1>(0h0)) node _T_2873 = mux(_T_615, deq_vec[7][1].prs1, UInt<1>(0h0)) node _T_2874 = or(_T_2866, _T_2867) node _T_2875 = or(_T_2874, _T_2868) node _T_2876 = or(_T_2875, _T_2869) node _T_2877 = or(_T_2876, _T_2870) node _T_2878 = or(_T_2877, _T_2871) node _T_2879 = or(_T_2878, _T_2872) node _T_2880 = or(_T_2879, _T_2873) wire _WIRE_156 : UInt<7> connect _WIRE_156, _T_2880 connect _WIRE_116.prs1, _WIRE_156 node _T_2881 = mux(_T_608, deq_vec[0][1].pdst, UInt<1>(0h0)) node _T_2882 = mux(_T_609, deq_vec[1][1].pdst, UInt<1>(0h0)) node _T_2883 = mux(_T_610, deq_vec[2][1].pdst, UInt<1>(0h0)) node _T_2884 = mux(_T_611, deq_vec[3][1].pdst, UInt<1>(0h0)) node _T_2885 = mux(_T_612, deq_vec[4][1].pdst, UInt<1>(0h0)) node _T_2886 = mux(_T_613, deq_vec[5][1].pdst, UInt<1>(0h0)) node _T_2887 = mux(_T_614, deq_vec[6][1].pdst, UInt<1>(0h0)) node _T_2888 = mux(_T_615, deq_vec[7][1].pdst, UInt<1>(0h0)) node _T_2889 = or(_T_2881, _T_2882) node _T_2890 = or(_T_2889, _T_2883) node _T_2891 = or(_T_2890, _T_2884) node _T_2892 = or(_T_2891, _T_2885) node _T_2893 = or(_T_2892, _T_2886) node _T_2894 = or(_T_2893, _T_2887) node _T_2895 = or(_T_2894, _T_2888) wire _WIRE_157 : UInt<7> connect _WIRE_157, _T_2895 connect _WIRE_116.pdst, _WIRE_157 node _T_2896 = mux(_T_608, deq_vec[0][1].rxq_idx, UInt<1>(0h0)) node _T_2897 = mux(_T_609, deq_vec[1][1].rxq_idx, UInt<1>(0h0)) node _T_2898 = mux(_T_610, deq_vec[2][1].rxq_idx, UInt<1>(0h0)) node _T_2899 = mux(_T_611, deq_vec[3][1].rxq_idx, UInt<1>(0h0)) node _T_2900 = mux(_T_612, deq_vec[4][1].rxq_idx, UInt<1>(0h0)) node _T_2901 = mux(_T_613, deq_vec[5][1].rxq_idx, UInt<1>(0h0)) node _T_2902 = mux(_T_614, deq_vec[6][1].rxq_idx, UInt<1>(0h0)) node _T_2903 = mux(_T_615, deq_vec[7][1].rxq_idx, UInt<1>(0h0)) node _T_2904 = or(_T_2896, _T_2897) node _T_2905 = or(_T_2904, _T_2898) node _T_2906 = or(_T_2905, _T_2899) node _T_2907 = or(_T_2906, _T_2900) node _T_2908 = or(_T_2907, _T_2901) node _T_2909 = or(_T_2908, _T_2902) node _T_2910 = or(_T_2909, _T_2903) wire _WIRE_158 : UInt<2> connect _WIRE_158, _T_2910 connect _WIRE_116.rxq_idx, _WIRE_158 node _T_2911 = mux(_T_608, deq_vec[0][1].stq_idx, UInt<1>(0h0)) node _T_2912 = mux(_T_609, deq_vec[1][1].stq_idx, UInt<1>(0h0)) node _T_2913 = mux(_T_610, deq_vec[2][1].stq_idx, UInt<1>(0h0)) node _T_2914 = mux(_T_611, deq_vec[3][1].stq_idx, UInt<1>(0h0)) node _T_2915 = mux(_T_612, deq_vec[4][1].stq_idx, UInt<1>(0h0)) node _T_2916 = mux(_T_613, deq_vec[5][1].stq_idx, UInt<1>(0h0)) node _T_2917 = mux(_T_614, deq_vec[6][1].stq_idx, UInt<1>(0h0)) node _T_2918 = mux(_T_615, deq_vec[7][1].stq_idx, UInt<1>(0h0)) node _T_2919 = or(_T_2911, _T_2912) node _T_2920 = or(_T_2919, _T_2913) node _T_2921 = or(_T_2920, _T_2914) node _T_2922 = or(_T_2921, _T_2915) node _T_2923 = or(_T_2922, _T_2916) node _T_2924 = or(_T_2923, _T_2917) node _T_2925 = or(_T_2924, _T_2918) wire _WIRE_159 : UInt<5> connect _WIRE_159, _T_2925 connect _WIRE_116.stq_idx, _WIRE_159 node _T_2926 = mux(_T_608, deq_vec[0][1].ldq_idx, UInt<1>(0h0)) node _T_2927 = mux(_T_609, deq_vec[1][1].ldq_idx, UInt<1>(0h0)) node _T_2928 = mux(_T_610, deq_vec[2][1].ldq_idx, UInt<1>(0h0)) node _T_2929 = mux(_T_611, deq_vec[3][1].ldq_idx, UInt<1>(0h0)) node _T_2930 = mux(_T_612, deq_vec[4][1].ldq_idx, UInt<1>(0h0)) node _T_2931 = mux(_T_613, deq_vec[5][1].ldq_idx, UInt<1>(0h0)) node _T_2932 = mux(_T_614, deq_vec[6][1].ldq_idx, UInt<1>(0h0)) node _T_2933 = mux(_T_615, deq_vec[7][1].ldq_idx, UInt<1>(0h0)) node _T_2934 = or(_T_2926, _T_2927) node _T_2935 = or(_T_2934, _T_2928) node _T_2936 = or(_T_2935, _T_2929) node _T_2937 = or(_T_2936, _T_2930) node _T_2938 = or(_T_2937, _T_2931) node _T_2939 = or(_T_2938, _T_2932) node _T_2940 = or(_T_2939, _T_2933) wire _WIRE_160 : UInt<5> connect _WIRE_160, _T_2940 connect _WIRE_116.ldq_idx, _WIRE_160 node _T_2941 = mux(_T_608, deq_vec[0][1].rob_idx, UInt<1>(0h0)) node _T_2942 = mux(_T_609, deq_vec[1][1].rob_idx, UInt<1>(0h0)) node _T_2943 = mux(_T_610, deq_vec[2][1].rob_idx, UInt<1>(0h0)) node _T_2944 = mux(_T_611, deq_vec[3][1].rob_idx, UInt<1>(0h0)) node _T_2945 = mux(_T_612, deq_vec[4][1].rob_idx, UInt<1>(0h0)) node _T_2946 = mux(_T_613, deq_vec[5][1].rob_idx, UInt<1>(0h0)) node _T_2947 = mux(_T_614, deq_vec[6][1].rob_idx, UInt<1>(0h0)) node _T_2948 = mux(_T_615, deq_vec[7][1].rob_idx, UInt<1>(0h0)) node _T_2949 = or(_T_2941, _T_2942) node _T_2950 = or(_T_2949, _T_2943) node _T_2951 = or(_T_2950, _T_2944) node _T_2952 = or(_T_2951, _T_2945) node _T_2953 = or(_T_2952, _T_2946) node _T_2954 = or(_T_2953, _T_2947) node _T_2955 = or(_T_2954, _T_2948) wire _WIRE_161 : UInt<7> connect _WIRE_161, _T_2955 connect _WIRE_116.rob_idx, _WIRE_161 wire _WIRE_162 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_2956 = mux(_T_608, deq_vec[0][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2957 = mux(_T_609, deq_vec[1][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2958 = mux(_T_610, deq_vec[2][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2959 = mux(_T_611, deq_vec[3][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2960 = mux(_T_612, deq_vec[4][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2961 = mux(_T_613, deq_vec[5][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2962 = mux(_T_614, deq_vec[6][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2963 = mux(_T_615, deq_vec[7][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2964 = or(_T_2956, _T_2957) node _T_2965 = or(_T_2964, _T_2958) node _T_2966 = or(_T_2965, _T_2959) node _T_2967 = or(_T_2966, _T_2960) node _T_2968 = or(_T_2967, _T_2961) node _T_2969 = or(_T_2968, _T_2962) node _T_2970 = or(_T_2969, _T_2963) wire _WIRE_163 : UInt<1> connect _WIRE_163, _T_2970 connect _WIRE_162.vec, _WIRE_163 node _T_2971 = mux(_T_608, deq_vec[0][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2972 = mux(_T_609, deq_vec[1][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2973 = mux(_T_610, deq_vec[2][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2974 = mux(_T_611, deq_vec[3][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2975 = mux(_T_612, deq_vec[4][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2976 = mux(_T_613, deq_vec[5][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2977 = mux(_T_614, deq_vec[6][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2978 = mux(_T_615, deq_vec[7][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2979 = or(_T_2971, _T_2972) node _T_2980 = or(_T_2979, _T_2973) node _T_2981 = or(_T_2980, _T_2974) node _T_2982 = or(_T_2981, _T_2975) node _T_2983 = or(_T_2982, _T_2976) node _T_2984 = or(_T_2983, _T_2977) node _T_2985 = or(_T_2984, _T_2978) wire _WIRE_164 : UInt<1> connect _WIRE_164, _T_2985 connect _WIRE_162.wflags, _WIRE_164 node _T_2986 = mux(_T_608, deq_vec[0][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2987 = mux(_T_609, deq_vec[1][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2988 = mux(_T_610, deq_vec[2][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2989 = mux(_T_611, deq_vec[3][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2990 = mux(_T_612, deq_vec[4][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2991 = mux(_T_613, deq_vec[5][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2992 = mux(_T_614, deq_vec[6][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2993 = mux(_T_615, deq_vec[7][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2994 = or(_T_2986, _T_2987) node _T_2995 = or(_T_2994, _T_2988) node _T_2996 = or(_T_2995, _T_2989) node _T_2997 = or(_T_2996, _T_2990) node _T_2998 = or(_T_2997, _T_2991) node _T_2999 = or(_T_2998, _T_2992) node _T_3000 = or(_T_2999, _T_2993) wire _WIRE_165 : UInt<1> connect _WIRE_165, _T_3000 connect _WIRE_162.sqrt, _WIRE_165 node _T_3001 = mux(_T_608, deq_vec[0][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3002 = mux(_T_609, deq_vec[1][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3003 = mux(_T_610, deq_vec[2][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3004 = mux(_T_611, deq_vec[3][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3005 = mux(_T_612, deq_vec[4][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3006 = mux(_T_613, deq_vec[5][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3007 = mux(_T_614, deq_vec[6][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3008 = mux(_T_615, deq_vec[7][1].fp_ctrl.div, UInt<1>(0h0)) node _T_3009 = or(_T_3001, _T_3002) node _T_3010 = or(_T_3009, _T_3003) node _T_3011 = or(_T_3010, _T_3004) node _T_3012 = or(_T_3011, _T_3005) node _T_3013 = or(_T_3012, _T_3006) node _T_3014 = or(_T_3013, _T_3007) node _T_3015 = or(_T_3014, _T_3008) wire _WIRE_166 : UInt<1> connect _WIRE_166, _T_3015 connect _WIRE_162.div, _WIRE_166 node _T_3016 = mux(_T_608, deq_vec[0][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3017 = mux(_T_609, deq_vec[1][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3018 = mux(_T_610, deq_vec[2][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3019 = mux(_T_611, deq_vec[3][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3020 = mux(_T_612, deq_vec[4][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3021 = mux(_T_613, deq_vec[5][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3022 = mux(_T_614, deq_vec[6][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3023 = mux(_T_615, deq_vec[7][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_3024 = or(_T_3016, _T_3017) node _T_3025 = or(_T_3024, _T_3018) node _T_3026 = or(_T_3025, _T_3019) node _T_3027 = or(_T_3026, _T_3020) node _T_3028 = or(_T_3027, _T_3021) node _T_3029 = or(_T_3028, _T_3022) node _T_3030 = or(_T_3029, _T_3023) wire _WIRE_167 : UInt<1> connect _WIRE_167, _T_3030 connect _WIRE_162.fma, _WIRE_167 node _T_3031 = mux(_T_608, deq_vec[0][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3032 = mux(_T_609, deq_vec[1][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3033 = mux(_T_610, deq_vec[2][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3034 = mux(_T_611, deq_vec[3][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3035 = mux(_T_612, deq_vec[4][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3036 = mux(_T_613, deq_vec[5][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3037 = mux(_T_614, deq_vec[6][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3038 = mux(_T_615, deq_vec[7][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_3039 = or(_T_3031, _T_3032) node _T_3040 = or(_T_3039, _T_3033) node _T_3041 = or(_T_3040, _T_3034) node _T_3042 = or(_T_3041, _T_3035) node _T_3043 = or(_T_3042, _T_3036) node _T_3044 = or(_T_3043, _T_3037) node _T_3045 = or(_T_3044, _T_3038) wire _WIRE_168 : UInt<1> connect _WIRE_168, _T_3045 connect _WIRE_162.fastpipe, _WIRE_168 node _T_3046 = mux(_T_608, deq_vec[0][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3047 = mux(_T_609, deq_vec[1][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3048 = mux(_T_610, deq_vec[2][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3049 = mux(_T_611, deq_vec[3][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3050 = mux(_T_612, deq_vec[4][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3051 = mux(_T_613, deq_vec[5][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3052 = mux(_T_614, deq_vec[6][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3053 = mux(_T_615, deq_vec[7][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_3054 = or(_T_3046, _T_3047) node _T_3055 = or(_T_3054, _T_3048) node _T_3056 = or(_T_3055, _T_3049) node _T_3057 = or(_T_3056, _T_3050) node _T_3058 = or(_T_3057, _T_3051) node _T_3059 = or(_T_3058, _T_3052) node _T_3060 = or(_T_3059, _T_3053) wire _WIRE_169 : UInt<1> connect _WIRE_169, _T_3060 connect _WIRE_162.toint, _WIRE_169 node _T_3061 = mux(_T_608, deq_vec[0][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3062 = mux(_T_609, deq_vec[1][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3063 = mux(_T_610, deq_vec[2][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3064 = mux(_T_611, deq_vec[3][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3065 = mux(_T_612, deq_vec[4][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3066 = mux(_T_613, deq_vec[5][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3067 = mux(_T_614, deq_vec[6][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3068 = mux(_T_615, deq_vec[7][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_3069 = or(_T_3061, _T_3062) node _T_3070 = or(_T_3069, _T_3063) node _T_3071 = or(_T_3070, _T_3064) node _T_3072 = or(_T_3071, _T_3065) node _T_3073 = or(_T_3072, _T_3066) node _T_3074 = or(_T_3073, _T_3067) node _T_3075 = or(_T_3074, _T_3068) wire _WIRE_170 : UInt<1> connect _WIRE_170, _T_3075 connect _WIRE_162.fromint, _WIRE_170 node _T_3076 = mux(_T_608, deq_vec[0][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3077 = mux(_T_609, deq_vec[1][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3078 = mux(_T_610, deq_vec[2][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3079 = mux(_T_611, deq_vec[3][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3080 = mux(_T_612, deq_vec[4][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3081 = mux(_T_613, deq_vec[5][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3082 = mux(_T_614, deq_vec[6][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3083 = mux(_T_615, deq_vec[7][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_3084 = or(_T_3076, _T_3077) node _T_3085 = or(_T_3084, _T_3078) node _T_3086 = or(_T_3085, _T_3079) node _T_3087 = or(_T_3086, _T_3080) node _T_3088 = or(_T_3087, _T_3081) node _T_3089 = or(_T_3088, _T_3082) node _T_3090 = or(_T_3089, _T_3083) wire _WIRE_171 : UInt<2> connect _WIRE_171, _T_3090 connect _WIRE_162.typeTagOut, _WIRE_171 node _T_3091 = mux(_T_608, deq_vec[0][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3092 = mux(_T_609, deq_vec[1][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3093 = mux(_T_610, deq_vec[2][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3094 = mux(_T_611, deq_vec[3][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3095 = mux(_T_612, deq_vec[4][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3096 = mux(_T_613, deq_vec[5][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3097 = mux(_T_614, deq_vec[6][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3098 = mux(_T_615, deq_vec[7][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_3099 = or(_T_3091, _T_3092) node _T_3100 = or(_T_3099, _T_3093) node _T_3101 = or(_T_3100, _T_3094) node _T_3102 = or(_T_3101, _T_3095) node _T_3103 = or(_T_3102, _T_3096) node _T_3104 = or(_T_3103, _T_3097) node _T_3105 = or(_T_3104, _T_3098) wire _WIRE_172 : UInt<2> connect _WIRE_172, _T_3105 connect _WIRE_162.typeTagIn, _WIRE_172 node _T_3106 = mux(_T_608, deq_vec[0][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3107 = mux(_T_609, deq_vec[1][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3108 = mux(_T_610, deq_vec[2][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3109 = mux(_T_611, deq_vec[3][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3110 = mux(_T_612, deq_vec[4][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3111 = mux(_T_613, deq_vec[5][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3112 = mux(_T_614, deq_vec[6][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3113 = mux(_T_615, deq_vec[7][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_3114 = or(_T_3106, _T_3107) node _T_3115 = or(_T_3114, _T_3108) node _T_3116 = or(_T_3115, _T_3109) node _T_3117 = or(_T_3116, _T_3110) node _T_3118 = or(_T_3117, _T_3111) node _T_3119 = or(_T_3118, _T_3112) node _T_3120 = or(_T_3119, _T_3113) wire _WIRE_173 : UInt<1> connect _WIRE_173, _T_3120 connect _WIRE_162.swap23, _WIRE_173 node _T_3121 = mux(_T_608, deq_vec[0][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3122 = mux(_T_609, deq_vec[1][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3123 = mux(_T_610, deq_vec[2][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3124 = mux(_T_611, deq_vec[3][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3125 = mux(_T_612, deq_vec[4][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3126 = mux(_T_613, deq_vec[5][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3127 = mux(_T_614, deq_vec[6][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3128 = mux(_T_615, deq_vec[7][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_3129 = or(_T_3121, _T_3122) node _T_3130 = or(_T_3129, _T_3123) node _T_3131 = or(_T_3130, _T_3124) node _T_3132 = or(_T_3131, _T_3125) node _T_3133 = or(_T_3132, _T_3126) node _T_3134 = or(_T_3133, _T_3127) node _T_3135 = or(_T_3134, _T_3128) wire _WIRE_174 : UInt<1> connect _WIRE_174, _T_3135 connect _WIRE_162.swap12, _WIRE_174 node _T_3136 = mux(_T_608, deq_vec[0][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3137 = mux(_T_609, deq_vec[1][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3138 = mux(_T_610, deq_vec[2][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3139 = mux(_T_611, deq_vec[3][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3140 = mux(_T_612, deq_vec[4][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3141 = mux(_T_613, deq_vec[5][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3142 = mux(_T_614, deq_vec[6][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3143 = mux(_T_615, deq_vec[7][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_3144 = or(_T_3136, _T_3137) node _T_3145 = or(_T_3144, _T_3138) node _T_3146 = or(_T_3145, _T_3139) node _T_3147 = or(_T_3146, _T_3140) node _T_3148 = or(_T_3147, _T_3141) node _T_3149 = or(_T_3148, _T_3142) node _T_3150 = or(_T_3149, _T_3143) wire _WIRE_175 : UInt<1> connect _WIRE_175, _T_3150 connect _WIRE_162.ren3, _WIRE_175 node _T_3151 = mux(_T_608, deq_vec[0][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3152 = mux(_T_609, deq_vec[1][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3153 = mux(_T_610, deq_vec[2][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3154 = mux(_T_611, deq_vec[3][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3155 = mux(_T_612, deq_vec[4][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3156 = mux(_T_613, deq_vec[5][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3157 = mux(_T_614, deq_vec[6][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3158 = mux(_T_615, deq_vec[7][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_3159 = or(_T_3151, _T_3152) node _T_3160 = or(_T_3159, _T_3153) node _T_3161 = or(_T_3160, _T_3154) node _T_3162 = or(_T_3161, _T_3155) node _T_3163 = or(_T_3162, _T_3156) node _T_3164 = or(_T_3163, _T_3157) node _T_3165 = or(_T_3164, _T_3158) wire _WIRE_176 : UInt<1> connect _WIRE_176, _T_3165 connect _WIRE_162.ren2, _WIRE_176 node _T_3166 = mux(_T_608, deq_vec[0][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3167 = mux(_T_609, deq_vec[1][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3168 = mux(_T_610, deq_vec[2][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3169 = mux(_T_611, deq_vec[3][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3170 = mux(_T_612, deq_vec[4][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3171 = mux(_T_613, deq_vec[5][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3172 = mux(_T_614, deq_vec[6][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3173 = mux(_T_615, deq_vec[7][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_3174 = or(_T_3166, _T_3167) node _T_3175 = or(_T_3174, _T_3168) node _T_3176 = or(_T_3175, _T_3169) node _T_3177 = or(_T_3176, _T_3170) node _T_3178 = or(_T_3177, _T_3171) node _T_3179 = or(_T_3178, _T_3172) node _T_3180 = or(_T_3179, _T_3173) wire _WIRE_177 : UInt<1> connect _WIRE_177, _T_3180 connect _WIRE_162.ren1, _WIRE_177 node _T_3181 = mux(_T_608, deq_vec[0][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3182 = mux(_T_609, deq_vec[1][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3183 = mux(_T_610, deq_vec[2][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3184 = mux(_T_611, deq_vec[3][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3185 = mux(_T_612, deq_vec[4][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3186 = mux(_T_613, deq_vec[5][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3187 = mux(_T_614, deq_vec[6][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3188 = mux(_T_615, deq_vec[7][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_3189 = or(_T_3181, _T_3182) node _T_3190 = or(_T_3189, _T_3183) node _T_3191 = or(_T_3190, _T_3184) node _T_3192 = or(_T_3191, _T_3185) node _T_3193 = or(_T_3192, _T_3186) node _T_3194 = or(_T_3193, _T_3187) node _T_3195 = or(_T_3194, _T_3188) wire _WIRE_178 : UInt<1> connect _WIRE_178, _T_3195 connect _WIRE_162.wen, _WIRE_178 node _T_3196 = mux(_T_608, deq_vec[0][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3197 = mux(_T_609, deq_vec[1][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3198 = mux(_T_610, deq_vec[2][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3199 = mux(_T_611, deq_vec[3][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3200 = mux(_T_612, deq_vec[4][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3201 = mux(_T_613, deq_vec[5][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3202 = mux(_T_614, deq_vec[6][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3203 = mux(_T_615, deq_vec[7][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_3204 = or(_T_3196, _T_3197) node _T_3205 = or(_T_3204, _T_3198) node _T_3206 = or(_T_3205, _T_3199) node _T_3207 = or(_T_3206, _T_3200) node _T_3208 = or(_T_3207, _T_3201) node _T_3209 = or(_T_3208, _T_3202) node _T_3210 = or(_T_3209, _T_3203) wire _WIRE_179 : UInt<1> connect _WIRE_179, _T_3210 connect _WIRE_162.ldst, _WIRE_179 connect _WIRE_116.fp_ctrl, _WIRE_162 node _T_3211 = mux(_T_608, deq_vec[0][1].op2_sel, UInt<1>(0h0)) node _T_3212 = mux(_T_609, deq_vec[1][1].op2_sel, UInt<1>(0h0)) node _T_3213 = mux(_T_610, deq_vec[2][1].op2_sel, UInt<1>(0h0)) node _T_3214 = mux(_T_611, deq_vec[3][1].op2_sel, UInt<1>(0h0)) node _T_3215 = mux(_T_612, deq_vec[4][1].op2_sel, UInt<1>(0h0)) node _T_3216 = mux(_T_613, deq_vec[5][1].op2_sel, UInt<1>(0h0)) node _T_3217 = mux(_T_614, deq_vec[6][1].op2_sel, UInt<1>(0h0)) node _T_3218 = mux(_T_615, deq_vec[7][1].op2_sel, UInt<1>(0h0)) node _T_3219 = or(_T_3211, _T_3212) node _T_3220 = or(_T_3219, _T_3213) node _T_3221 = or(_T_3220, _T_3214) node _T_3222 = or(_T_3221, _T_3215) node _T_3223 = or(_T_3222, _T_3216) node _T_3224 = or(_T_3223, _T_3217) node _T_3225 = or(_T_3224, _T_3218) wire _WIRE_180 : UInt<3> connect _WIRE_180, _T_3225 connect _WIRE_116.op2_sel, _WIRE_180 node _T_3226 = mux(_T_608, deq_vec[0][1].op1_sel, UInt<1>(0h0)) node _T_3227 = mux(_T_609, deq_vec[1][1].op1_sel, UInt<1>(0h0)) node _T_3228 = mux(_T_610, deq_vec[2][1].op1_sel, UInt<1>(0h0)) node _T_3229 = mux(_T_611, deq_vec[3][1].op1_sel, UInt<1>(0h0)) node _T_3230 = mux(_T_612, deq_vec[4][1].op1_sel, UInt<1>(0h0)) node _T_3231 = mux(_T_613, deq_vec[5][1].op1_sel, UInt<1>(0h0)) node _T_3232 = mux(_T_614, deq_vec[6][1].op1_sel, UInt<1>(0h0)) node _T_3233 = mux(_T_615, deq_vec[7][1].op1_sel, UInt<1>(0h0)) node _T_3234 = or(_T_3226, _T_3227) node _T_3235 = or(_T_3234, _T_3228) node _T_3236 = or(_T_3235, _T_3229) node _T_3237 = or(_T_3236, _T_3230) node _T_3238 = or(_T_3237, _T_3231) node _T_3239 = or(_T_3238, _T_3232) node _T_3240 = or(_T_3239, _T_3233) wire _WIRE_181 : UInt<2> connect _WIRE_181, _T_3240 connect _WIRE_116.op1_sel, _WIRE_181 node _T_3241 = mux(_T_608, deq_vec[0][1].imm_packed, UInt<1>(0h0)) node _T_3242 = mux(_T_609, deq_vec[1][1].imm_packed, UInt<1>(0h0)) node _T_3243 = mux(_T_610, deq_vec[2][1].imm_packed, UInt<1>(0h0)) node _T_3244 = mux(_T_611, deq_vec[3][1].imm_packed, UInt<1>(0h0)) node _T_3245 = mux(_T_612, deq_vec[4][1].imm_packed, UInt<1>(0h0)) node _T_3246 = mux(_T_613, deq_vec[5][1].imm_packed, UInt<1>(0h0)) node _T_3247 = mux(_T_614, deq_vec[6][1].imm_packed, UInt<1>(0h0)) node _T_3248 = mux(_T_615, deq_vec[7][1].imm_packed, UInt<1>(0h0)) node _T_3249 = or(_T_3241, _T_3242) node _T_3250 = or(_T_3249, _T_3243) node _T_3251 = or(_T_3250, _T_3244) node _T_3252 = or(_T_3251, _T_3245) node _T_3253 = or(_T_3252, _T_3246) node _T_3254 = or(_T_3253, _T_3247) node _T_3255 = or(_T_3254, _T_3248) wire _WIRE_182 : UInt<20> connect _WIRE_182, _T_3255 connect _WIRE_116.imm_packed, _WIRE_182 node _T_3256 = mux(_T_608, deq_vec[0][1].pimm, UInt<1>(0h0)) node _T_3257 = mux(_T_609, deq_vec[1][1].pimm, UInt<1>(0h0)) node _T_3258 = mux(_T_610, deq_vec[2][1].pimm, UInt<1>(0h0)) node _T_3259 = mux(_T_611, deq_vec[3][1].pimm, UInt<1>(0h0)) node _T_3260 = mux(_T_612, deq_vec[4][1].pimm, UInt<1>(0h0)) node _T_3261 = mux(_T_613, deq_vec[5][1].pimm, UInt<1>(0h0)) node _T_3262 = mux(_T_614, deq_vec[6][1].pimm, UInt<1>(0h0)) node _T_3263 = mux(_T_615, deq_vec[7][1].pimm, UInt<1>(0h0)) node _T_3264 = or(_T_3256, _T_3257) node _T_3265 = or(_T_3264, _T_3258) node _T_3266 = or(_T_3265, _T_3259) node _T_3267 = or(_T_3266, _T_3260) node _T_3268 = or(_T_3267, _T_3261) node _T_3269 = or(_T_3268, _T_3262) node _T_3270 = or(_T_3269, _T_3263) wire _WIRE_183 : UInt<5> connect _WIRE_183, _T_3270 connect _WIRE_116.pimm, _WIRE_183 node _T_3271 = mux(_T_608, deq_vec[0][1].imm_sel, UInt<1>(0h0)) node _T_3272 = mux(_T_609, deq_vec[1][1].imm_sel, UInt<1>(0h0)) node _T_3273 = mux(_T_610, deq_vec[2][1].imm_sel, UInt<1>(0h0)) node _T_3274 = mux(_T_611, deq_vec[3][1].imm_sel, UInt<1>(0h0)) node _T_3275 = mux(_T_612, deq_vec[4][1].imm_sel, UInt<1>(0h0)) node _T_3276 = mux(_T_613, deq_vec[5][1].imm_sel, UInt<1>(0h0)) node _T_3277 = mux(_T_614, deq_vec[6][1].imm_sel, UInt<1>(0h0)) node _T_3278 = mux(_T_615, deq_vec[7][1].imm_sel, UInt<1>(0h0)) node _T_3279 = or(_T_3271, _T_3272) node _T_3280 = or(_T_3279, _T_3273) node _T_3281 = or(_T_3280, _T_3274) node _T_3282 = or(_T_3281, _T_3275) node _T_3283 = or(_T_3282, _T_3276) node _T_3284 = or(_T_3283, _T_3277) node _T_3285 = or(_T_3284, _T_3278) wire _WIRE_184 : UInt<3> connect _WIRE_184, _T_3285 connect _WIRE_116.imm_sel, _WIRE_184 node _T_3286 = mux(_T_608, deq_vec[0][1].imm_rename, UInt<1>(0h0)) node _T_3287 = mux(_T_609, deq_vec[1][1].imm_rename, UInt<1>(0h0)) node _T_3288 = mux(_T_610, deq_vec[2][1].imm_rename, UInt<1>(0h0)) node _T_3289 = mux(_T_611, deq_vec[3][1].imm_rename, UInt<1>(0h0)) node _T_3290 = mux(_T_612, deq_vec[4][1].imm_rename, UInt<1>(0h0)) node _T_3291 = mux(_T_613, deq_vec[5][1].imm_rename, UInt<1>(0h0)) node _T_3292 = mux(_T_614, deq_vec[6][1].imm_rename, UInt<1>(0h0)) node _T_3293 = mux(_T_615, deq_vec[7][1].imm_rename, UInt<1>(0h0)) node _T_3294 = or(_T_3286, _T_3287) node _T_3295 = or(_T_3294, _T_3288) node _T_3296 = or(_T_3295, _T_3289) node _T_3297 = or(_T_3296, _T_3290) node _T_3298 = or(_T_3297, _T_3291) node _T_3299 = or(_T_3298, _T_3292) node _T_3300 = or(_T_3299, _T_3293) wire _WIRE_185 : UInt<1> connect _WIRE_185, _T_3300 connect _WIRE_116.imm_rename, _WIRE_185 node _T_3301 = mux(_T_608, deq_vec[0][1].taken, UInt<1>(0h0)) node _T_3302 = mux(_T_609, deq_vec[1][1].taken, UInt<1>(0h0)) node _T_3303 = mux(_T_610, deq_vec[2][1].taken, UInt<1>(0h0)) node _T_3304 = mux(_T_611, deq_vec[3][1].taken, UInt<1>(0h0)) node _T_3305 = mux(_T_612, deq_vec[4][1].taken, UInt<1>(0h0)) node _T_3306 = mux(_T_613, deq_vec[5][1].taken, UInt<1>(0h0)) node _T_3307 = mux(_T_614, deq_vec[6][1].taken, UInt<1>(0h0)) node _T_3308 = mux(_T_615, deq_vec[7][1].taken, UInt<1>(0h0)) node _T_3309 = or(_T_3301, _T_3302) node _T_3310 = or(_T_3309, _T_3303) node _T_3311 = or(_T_3310, _T_3304) node _T_3312 = or(_T_3311, _T_3305) node _T_3313 = or(_T_3312, _T_3306) node _T_3314 = or(_T_3313, _T_3307) node _T_3315 = or(_T_3314, _T_3308) wire _WIRE_186 : UInt<1> connect _WIRE_186, _T_3315 connect _WIRE_116.taken, _WIRE_186 node _T_3316 = mux(_T_608, deq_vec[0][1].pc_lob, UInt<1>(0h0)) node _T_3317 = mux(_T_609, deq_vec[1][1].pc_lob, UInt<1>(0h0)) node _T_3318 = mux(_T_610, deq_vec[2][1].pc_lob, UInt<1>(0h0)) node _T_3319 = mux(_T_611, deq_vec[3][1].pc_lob, UInt<1>(0h0)) node _T_3320 = mux(_T_612, deq_vec[4][1].pc_lob, UInt<1>(0h0)) node _T_3321 = mux(_T_613, deq_vec[5][1].pc_lob, UInt<1>(0h0)) node _T_3322 = mux(_T_614, deq_vec[6][1].pc_lob, UInt<1>(0h0)) node _T_3323 = mux(_T_615, deq_vec[7][1].pc_lob, UInt<1>(0h0)) node _T_3324 = or(_T_3316, _T_3317) node _T_3325 = or(_T_3324, _T_3318) node _T_3326 = or(_T_3325, _T_3319) node _T_3327 = or(_T_3326, _T_3320) node _T_3328 = or(_T_3327, _T_3321) node _T_3329 = or(_T_3328, _T_3322) node _T_3330 = or(_T_3329, _T_3323) wire _WIRE_187 : UInt<6> connect _WIRE_187, _T_3330 connect _WIRE_116.pc_lob, _WIRE_187 node _T_3331 = mux(_T_608, deq_vec[0][1].edge_inst, UInt<1>(0h0)) node _T_3332 = mux(_T_609, deq_vec[1][1].edge_inst, UInt<1>(0h0)) node _T_3333 = mux(_T_610, deq_vec[2][1].edge_inst, UInt<1>(0h0)) node _T_3334 = mux(_T_611, deq_vec[3][1].edge_inst, UInt<1>(0h0)) node _T_3335 = mux(_T_612, deq_vec[4][1].edge_inst, UInt<1>(0h0)) node _T_3336 = mux(_T_613, deq_vec[5][1].edge_inst, UInt<1>(0h0)) node _T_3337 = mux(_T_614, deq_vec[6][1].edge_inst, UInt<1>(0h0)) node _T_3338 = mux(_T_615, deq_vec[7][1].edge_inst, UInt<1>(0h0)) node _T_3339 = or(_T_3331, _T_3332) node _T_3340 = or(_T_3339, _T_3333) node _T_3341 = or(_T_3340, _T_3334) node _T_3342 = or(_T_3341, _T_3335) node _T_3343 = or(_T_3342, _T_3336) node _T_3344 = or(_T_3343, _T_3337) node _T_3345 = or(_T_3344, _T_3338) wire _WIRE_188 : UInt<1> connect _WIRE_188, _T_3345 connect _WIRE_116.edge_inst, _WIRE_188 node _T_3346 = mux(_T_608, deq_vec[0][1].ftq_idx, UInt<1>(0h0)) node _T_3347 = mux(_T_609, deq_vec[1][1].ftq_idx, UInt<1>(0h0)) node _T_3348 = mux(_T_610, deq_vec[2][1].ftq_idx, UInt<1>(0h0)) node _T_3349 = mux(_T_611, deq_vec[3][1].ftq_idx, UInt<1>(0h0)) node _T_3350 = mux(_T_612, deq_vec[4][1].ftq_idx, UInt<1>(0h0)) node _T_3351 = mux(_T_613, deq_vec[5][1].ftq_idx, UInt<1>(0h0)) node _T_3352 = mux(_T_614, deq_vec[6][1].ftq_idx, UInt<1>(0h0)) node _T_3353 = mux(_T_615, deq_vec[7][1].ftq_idx, UInt<1>(0h0)) node _T_3354 = or(_T_3346, _T_3347) node _T_3355 = or(_T_3354, _T_3348) node _T_3356 = or(_T_3355, _T_3349) node _T_3357 = or(_T_3356, _T_3350) node _T_3358 = or(_T_3357, _T_3351) node _T_3359 = or(_T_3358, _T_3352) node _T_3360 = or(_T_3359, _T_3353) wire _WIRE_189 : UInt<5> connect _WIRE_189, _T_3360 connect _WIRE_116.ftq_idx, _WIRE_189 node _T_3361 = mux(_T_608, deq_vec[0][1].is_mov, UInt<1>(0h0)) node _T_3362 = mux(_T_609, deq_vec[1][1].is_mov, UInt<1>(0h0)) node _T_3363 = mux(_T_610, deq_vec[2][1].is_mov, UInt<1>(0h0)) node _T_3364 = mux(_T_611, deq_vec[3][1].is_mov, UInt<1>(0h0)) node _T_3365 = mux(_T_612, deq_vec[4][1].is_mov, UInt<1>(0h0)) node _T_3366 = mux(_T_613, deq_vec[5][1].is_mov, UInt<1>(0h0)) node _T_3367 = mux(_T_614, deq_vec[6][1].is_mov, UInt<1>(0h0)) node _T_3368 = mux(_T_615, deq_vec[7][1].is_mov, UInt<1>(0h0)) node _T_3369 = or(_T_3361, _T_3362) node _T_3370 = or(_T_3369, _T_3363) node _T_3371 = or(_T_3370, _T_3364) node _T_3372 = or(_T_3371, _T_3365) node _T_3373 = or(_T_3372, _T_3366) node _T_3374 = or(_T_3373, _T_3367) node _T_3375 = or(_T_3374, _T_3368) wire _WIRE_190 : UInt<1> connect _WIRE_190, _T_3375 connect _WIRE_116.is_mov, _WIRE_190 node _T_3376 = mux(_T_608, deq_vec[0][1].is_rocc, UInt<1>(0h0)) node _T_3377 = mux(_T_609, deq_vec[1][1].is_rocc, UInt<1>(0h0)) node _T_3378 = mux(_T_610, deq_vec[2][1].is_rocc, UInt<1>(0h0)) node _T_3379 = mux(_T_611, deq_vec[3][1].is_rocc, UInt<1>(0h0)) node _T_3380 = mux(_T_612, deq_vec[4][1].is_rocc, UInt<1>(0h0)) node _T_3381 = mux(_T_613, deq_vec[5][1].is_rocc, UInt<1>(0h0)) node _T_3382 = mux(_T_614, deq_vec[6][1].is_rocc, UInt<1>(0h0)) node _T_3383 = mux(_T_615, deq_vec[7][1].is_rocc, UInt<1>(0h0)) node _T_3384 = or(_T_3376, _T_3377) node _T_3385 = or(_T_3384, _T_3378) node _T_3386 = or(_T_3385, _T_3379) node _T_3387 = or(_T_3386, _T_3380) node _T_3388 = or(_T_3387, _T_3381) node _T_3389 = or(_T_3388, _T_3382) node _T_3390 = or(_T_3389, _T_3383) wire _WIRE_191 : UInt<1> connect _WIRE_191, _T_3390 connect _WIRE_116.is_rocc, _WIRE_191 node _T_3391 = mux(_T_608, deq_vec[0][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3392 = mux(_T_609, deq_vec[1][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3393 = mux(_T_610, deq_vec[2][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3394 = mux(_T_611, deq_vec[3][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3395 = mux(_T_612, deq_vec[4][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3396 = mux(_T_613, deq_vec[5][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3397 = mux(_T_614, deq_vec[6][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3398 = mux(_T_615, deq_vec[7][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_3399 = or(_T_3391, _T_3392) node _T_3400 = or(_T_3399, _T_3393) node _T_3401 = or(_T_3400, _T_3394) node _T_3402 = or(_T_3401, _T_3395) node _T_3403 = or(_T_3402, _T_3396) node _T_3404 = or(_T_3403, _T_3397) node _T_3405 = or(_T_3404, _T_3398) wire _WIRE_192 : UInt<1> connect _WIRE_192, _T_3405 connect _WIRE_116.is_sys_pc2epc, _WIRE_192 node _T_3406 = mux(_T_608, deq_vec[0][1].is_eret, UInt<1>(0h0)) node _T_3407 = mux(_T_609, deq_vec[1][1].is_eret, UInt<1>(0h0)) node _T_3408 = mux(_T_610, deq_vec[2][1].is_eret, UInt<1>(0h0)) node _T_3409 = mux(_T_611, deq_vec[3][1].is_eret, UInt<1>(0h0)) node _T_3410 = mux(_T_612, deq_vec[4][1].is_eret, UInt<1>(0h0)) node _T_3411 = mux(_T_613, deq_vec[5][1].is_eret, UInt<1>(0h0)) node _T_3412 = mux(_T_614, deq_vec[6][1].is_eret, UInt<1>(0h0)) node _T_3413 = mux(_T_615, deq_vec[7][1].is_eret, UInt<1>(0h0)) node _T_3414 = or(_T_3406, _T_3407) node _T_3415 = or(_T_3414, _T_3408) node _T_3416 = or(_T_3415, _T_3409) node _T_3417 = or(_T_3416, _T_3410) node _T_3418 = or(_T_3417, _T_3411) node _T_3419 = or(_T_3418, _T_3412) node _T_3420 = or(_T_3419, _T_3413) wire _WIRE_193 : UInt<1> connect _WIRE_193, _T_3420 connect _WIRE_116.is_eret, _WIRE_193 node _T_3421 = mux(_T_608, deq_vec[0][1].is_amo, UInt<1>(0h0)) node _T_3422 = mux(_T_609, deq_vec[1][1].is_amo, UInt<1>(0h0)) node _T_3423 = mux(_T_610, deq_vec[2][1].is_amo, UInt<1>(0h0)) node _T_3424 = mux(_T_611, deq_vec[3][1].is_amo, UInt<1>(0h0)) node _T_3425 = mux(_T_612, deq_vec[4][1].is_amo, UInt<1>(0h0)) node _T_3426 = mux(_T_613, deq_vec[5][1].is_amo, UInt<1>(0h0)) node _T_3427 = mux(_T_614, deq_vec[6][1].is_amo, UInt<1>(0h0)) node _T_3428 = mux(_T_615, deq_vec[7][1].is_amo, UInt<1>(0h0)) node _T_3429 = or(_T_3421, _T_3422) node _T_3430 = or(_T_3429, _T_3423) node _T_3431 = or(_T_3430, _T_3424) node _T_3432 = or(_T_3431, _T_3425) node _T_3433 = or(_T_3432, _T_3426) node _T_3434 = or(_T_3433, _T_3427) node _T_3435 = or(_T_3434, _T_3428) wire _WIRE_194 : UInt<1> connect _WIRE_194, _T_3435 connect _WIRE_116.is_amo, _WIRE_194 node _T_3436 = mux(_T_608, deq_vec[0][1].is_sfence, UInt<1>(0h0)) node _T_3437 = mux(_T_609, deq_vec[1][1].is_sfence, UInt<1>(0h0)) node _T_3438 = mux(_T_610, deq_vec[2][1].is_sfence, UInt<1>(0h0)) node _T_3439 = mux(_T_611, deq_vec[3][1].is_sfence, UInt<1>(0h0)) node _T_3440 = mux(_T_612, deq_vec[4][1].is_sfence, UInt<1>(0h0)) node _T_3441 = mux(_T_613, deq_vec[5][1].is_sfence, UInt<1>(0h0)) node _T_3442 = mux(_T_614, deq_vec[6][1].is_sfence, UInt<1>(0h0)) node _T_3443 = mux(_T_615, deq_vec[7][1].is_sfence, UInt<1>(0h0)) node _T_3444 = or(_T_3436, _T_3437) node _T_3445 = or(_T_3444, _T_3438) node _T_3446 = or(_T_3445, _T_3439) node _T_3447 = or(_T_3446, _T_3440) node _T_3448 = or(_T_3447, _T_3441) node _T_3449 = or(_T_3448, _T_3442) node _T_3450 = or(_T_3449, _T_3443) wire _WIRE_195 : UInt<1> connect _WIRE_195, _T_3450 connect _WIRE_116.is_sfence, _WIRE_195 node _T_3451 = mux(_T_608, deq_vec[0][1].is_fencei, UInt<1>(0h0)) node _T_3452 = mux(_T_609, deq_vec[1][1].is_fencei, UInt<1>(0h0)) node _T_3453 = mux(_T_610, deq_vec[2][1].is_fencei, UInt<1>(0h0)) node _T_3454 = mux(_T_611, deq_vec[3][1].is_fencei, UInt<1>(0h0)) node _T_3455 = mux(_T_612, deq_vec[4][1].is_fencei, UInt<1>(0h0)) node _T_3456 = mux(_T_613, deq_vec[5][1].is_fencei, UInt<1>(0h0)) node _T_3457 = mux(_T_614, deq_vec[6][1].is_fencei, UInt<1>(0h0)) node _T_3458 = mux(_T_615, deq_vec[7][1].is_fencei, UInt<1>(0h0)) node _T_3459 = or(_T_3451, _T_3452) node _T_3460 = or(_T_3459, _T_3453) node _T_3461 = or(_T_3460, _T_3454) node _T_3462 = or(_T_3461, _T_3455) node _T_3463 = or(_T_3462, _T_3456) node _T_3464 = or(_T_3463, _T_3457) node _T_3465 = or(_T_3464, _T_3458) wire _WIRE_196 : UInt<1> connect _WIRE_196, _T_3465 connect _WIRE_116.is_fencei, _WIRE_196 node _T_3466 = mux(_T_608, deq_vec[0][1].is_fence, UInt<1>(0h0)) node _T_3467 = mux(_T_609, deq_vec[1][1].is_fence, UInt<1>(0h0)) node _T_3468 = mux(_T_610, deq_vec[2][1].is_fence, UInt<1>(0h0)) node _T_3469 = mux(_T_611, deq_vec[3][1].is_fence, UInt<1>(0h0)) node _T_3470 = mux(_T_612, deq_vec[4][1].is_fence, UInt<1>(0h0)) node _T_3471 = mux(_T_613, deq_vec[5][1].is_fence, UInt<1>(0h0)) node _T_3472 = mux(_T_614, deq_vec[6][1].is_fence, UInt<1>(0h0)) node _T_3473 = mux(_T_615, deq_vec[7][1].is_fence, UInt<1>(0h0)) node _T_3474 = or(_T_3466, _T_3467) node _T_3475 = or(_T_3474, _T_3468) node _T_3476 = or(_T_3475, _T_3469) node _T_3477 = or(_T_3476, _T_3470) node _T_3478 = or(_T_3477, _T_3471) node _T_3479 = or(_T_3478, _T_3472) node _T_3480 = or(_T_3479, _T_3473) wire _WIRE_197 : UInt<1> connect _WIRE_197, _T_3480 connect _WIRE_116.is_fence, _WIRE_197 node _T_3481 = mux(_T_608, deq_vec[0][1].is_sfb, UInt<1>(0h0)) node _T_3482 = mux(_T_609, deq_vec[1][1].is_sfb, UInt<1>(0h0)) node _T_3483 = mux(_T_610, deq_vec[2][1].is_sfb, UInt<1>(0h0)) node _T_3484 = mux(_T_611, deq_vec[3][1].is_sfb, UInt<1>(0h0)) node _T_3485 = mux(_T_612, deq_vec[4][1].is_sfb, UInt<1>(0h0)) node _T_3486 = mux(_T_613, deq_vec[5][1].is_sfb, UInt<1>(0h0)) node _T_3487 = mux(_T_614, deq_vec[6][1].is_sfb, UInt<1>(0h0)) node _T_3488 = mux(_T_615, deq_vec[7][1].is_sfb, UInt<1>(0h0)) node _T_3489 = or(_T_3481, _T_3482) node _T_3490 = or(_T_3489, _T_3483) node _T_3491 = or(_T_3490, _T_3484) node _T_3492 = or(_T_3491, _T_3485) node _T_3493 = or(_T_3492, _T_3486) node _T_3494 = or(_T_3493, _T_3487) node _T_3495 = or(_T_3494, _T_3488) wire _WIRE_198 : UInt<1> connect _WIRE_198, _T_3495 connect _WIRE_116.is_sfb, _WIRE_198 node _T_3496 = mux(_T_608, deq_vec[0][1].br_type, UInt<1>(0h0)) node _T_3497 = mux(_T_609, deq_vec[1][1].br_type, UInt<1>(0h0)) node _T_3498 = mux(_T_610, deq_vec[2][1].br_type, UInt<1>(0h0)) node _T_3499 = mux(_T_611, deq_vec[3][1].br_type, UInt<1>(0h0)) node _T_3500 = mux(_T_612, deq_vec[4][1].br_type, UInt<1>(0h0)) node _T_3501 = mux(_T_613, deq_vec[5][1].br_type, UInt<1>(0h0)) node _T_3502 = mux(_T_614, deq_vec[6][1].br_type, UInt<1>(0h0)) node _T_3503 = mux(_T_615, deq_vec[7][1].br_type, UInt<1>(0h0)) node _T_3504 = or(_T_3496, _T_3497) node _T_3505 = or(_T_3504, _T_3498) node _T_3506 = or(_T_3505, _T_3499) node _T_3507 = or(_T_3506, _T_3500) node _T_3508 = or(_T_3507, _T_3501) node _T_3509 = or(_T_3508, _T_3502) node _T_3510 = or(_T_3509, _T_3503) wire _WIRE_199 : UInt<4> connect _WIRE_199, _T_3510 connect _WIRE_116.br_type, _WIRE_199 node _T_3511 = mux(_T_608, deq_vec[0][1].br_tag, UInt<1>(0h0)) node _T_3512 = mux(_T_609, deq_vec[1][1].br_tag, UInt<1>(0h0)) node _T_3513 = mux(_T_610, deq_vec[2][1].br_tag, UInt<1>(0h0)) node _T_3514 = mux(_T_611, deq_vec[3][1].br_tag, UInt<1>(0h0)) node _T_3515 = mux(_T_612, deq_vec[4][1].br_tag, UInt<1>(0h0)) node _T_3516 = mux(_T_613, deq_vec[5][1].br_tag, UInt<1>(0h0)) node _T_3517 = mux(_T_614, deq_vec[6][1].br_tag, UInt<1>(0h0)) node _T_3518 = mux(_T_615, deq_vec[7][1].br_tag, UInt<1>(0h0)) node _T_3519 = or(_T_3511, _T_3512) node _T_3520 = or(_T_3519, _T_3513) node _T_3521 = or(_T_3520, _T_3514) node _T_3522 = or(_T_3521, _T_3515) node _T_3523 = or(_T_3522, _T_3516) node _T_3524 = or(_T_3523, _T_3517) node _T_3525 = or(_T_3524, _T_3518) wire _WIRE_200 : UInt<4> connect _WIRE_200, _T_3525 connect _WIRE_116.br_tag, _WIRE_200 node _T_3526 = mux(_T_608, deq_vec[0][1].br_mask, UInt<1>(0h0)) node _T_3527 = mux(_T_609, deq_vec[1][1].br_mask, UInt<1>(0h0)) node _T_3528 = mux(_T_610, deq_vec[2][1].br_mask, UInt<1>(0h0)) node _T_3529 = mux(_T_611, deq_vec[3][1].br_mask, UInt<1>(0h0)) node _T_3530 = mux(_T_612, deq_vec[4][1].br_mask, UInt<1>(0h0)) node _T_3531 = mux(_T_613, deq_vec[5][1].br_mask, UInt<1>(0h0)) node _T_3532 = mux(_T_614, deq_vec[6][1].br_mask, UInt<1>(0h0)) node _T_3533 = mux(_T_615, deq_vec[7][1].br_mask, UInt<1>(0h0)) node _T_3534 = or(_T_3526, _T_3527) node _T_3535 = or(_T_3534, _T_3528) node _T_3536 = or(_T_3535, _T_3529) node _T_3537 = or(_T_3536, _T_3530) node _T_3538 = or(_T_3537, _T_3531) node _T_3539 = or(_T_3538, _T_3532) node _T_3540 = or(_T_3539, _T_3533) wire _WIRE_201 : UInt<16> connect _WIRE_201, _T_3540 connect _WIRE_116.br_mask, _WIRE_201 node _T_3541 = mux(_T_608, deq_vec[0][1].dis_col_sel, UInt<1>(0h0)) node _T_3542 = mux(_T_609, deq_vec[1][1].dis_col_sel, UInt<1>(0h0)) node _T_3543 = mux(_T_610, deq_vec[2][1].dis_col_sel, UInt<1>(0h0)) node _T_3544 = mux(_T_611, deq_vec[3][1].dis_col_sel, UInt<1>(0h0)) node _T_3545 = mux(_T_612, deq_vec[4][1].dis_col_sel, UInt<1>(0h0)) node _T_3546 = mux(_T_613, deq_vec[5][1].dis_col_sel, UInt<1>(0h0)) node _T_3547 = mux(_T_614, deq_vec[6][1].dis_col_sel, UInt<1>(0h0)) node _T_3548 = mux(_T_615, deq_vec[7][1].dis_col_sel, UInt<1>(0h0)) node _T_3549 = or(_T_3541, _T_3542) node _T_3550 = or(_T_3549, _T_3543) node _T_3551 = or(_T_3550, _T_3544) node _T_3552 = or(_T_3551, _T_3545) node _T_3553 = or(_T_3552, _T_3546) node _T_3554 = or(_T_3553, _T_3547) node _T_3555 = or(_T_3554, _T_3548) wire _WIRE_202 : UInt<3> connect _WIRE_202, _T_3555 connect _WIRE_116.dis_col_sel, _WIRE_202 node _T_3556 = mux(_T_608, deq_vec[0][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3557 = mux(_T_609, deq_vec[1][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3558 = mux(_T_610, deq_vec[2][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3559 = mux(_T_611, deq_vec[3][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3560 = mux(_T_612, deq_vec[4][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3561 = mux(_T_613, deq_vec[5][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3562 = mux(_T_614, deq_vec[6][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3563 = mux(_T_615, deq_vec[7][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3564 = or(_T_3556, _T_3557) node _T_3565 = or(_T_3564, _T_3558) node _T_3566 = or(_T_3565, _T_3559) node _T_3567 = or(_T_3566, _T_3560) node _T_3568 = or(_T_3567, _T_3561) node _T_3569 = or(_T_3568, _T_3562) node _T_3570 = or(_T_3569, _T_3563) wire _WIRE_203 : UInt<1> connect _WIRE_203, _T_3570 connect _WIRE_116.iw_p3_bypass_hint, _WIRE_203 node _T_3571 = mux(_T_608, deq_vec[0][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3572 = mux(_T_609, deq_vec[1][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3573 = mux(_T_610, deq_vec[2][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3574 = mux(_T_611, deq_vec[3][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3575 = mux(_T_612, deq_vec[4][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3576 = mux(_T_613, deq_vec[5][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3577 = mux(_T_614, deq_vec[6][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3578 = mux(_T_615, deq_vec[7][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3579 = or(_T_3571, _T_3572) node _T_3580 = or(_T_3579, _T_3573) node _T_3581 = or(_T_3580, _T_3574) node _T_3582 = or(_T_3581, _T_3575) node _T_3583 = or(_T_3582, _T_3576) node _T_3584 = or(_T_3583, _T_3577) node _T_3585 = or(_T_3584, _T_3578) wire _WIRE_204 : UInt<1> connect _WIRE_204, _T_3585 connect _WIRE_116.iw_p2_bypass_hint, _WIRE_204 node _T_3586 = mux(_T_608, deq_vec[0][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3587 = mux(_T_609, deq_vec[1][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3588 = mux(_T_610, deq_vec[2][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3589 = mux(_T_611, deq_vec[3][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3590 = mux(_T_612, deq_vec[4][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3591 = mux(_T_613, deq_vec[5][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3592 = mux(_T_614, deq_vec[6][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3593 = mux(_T_615, deq_vec[7][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3594 = or(_T_3586, _T_3587) node _T_3595 = or(_T_3594, _T_3588) node _T_3596 = or(_T_3595, _T_3589) node _T_3597 = or(_T_3596, _T_3590) node _T_3598 = or(_T_3597, _T_3591) node _T_3599 = or(_T_3598, _T_3592) node _T_3600 = or(_T_3599, _T_3593) wire _WIRE_205 : UInt<1> connect _WIRE_205, _T_3600 connect _WIRE_116.iw_p1_bypass_hint, _WIRE_205 node _T_3601 = mux(_T_608, deq_vec[0][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3602 = mux(_T_609, deq_vec[1][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3603 = mux(_T_610, deq_vec[2][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3604 = mux(_T_611, deq_vec[3][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3605 = mux(_T_612, deq_vec[4][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3606 = mux(_T_613, deq_vec[5][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3607 = mux(_T_614, deq_vec[6][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3608 = mux(_T_615, deq_vec[7][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3609 = or(_T_3601, _T_3602) node _T_3610 = or(_T_3609, _T_3603) node _T_3611 = or(_T_3610, _T_3604) node _T_3612 = or(_T_3611, _T_3605) node _T_3613 = or(_T_3612, _T_3606) node _T_3614 = or(_T_3613, _T_3607) node _T_3615 = or(_T_3614, _T_3608) wire _WIRE_206 : UInt<3> connect _WIRE_206, _T_3615 connect _WIRE_116.iw_p2_speculative_child, _WIRE_206 node _T_3616 = mux(_T_608, deq_vec[0][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3617 = mux(_T_609, deq_vec[1][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3618 = mux(_T_610, deq_vec[2][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3619 = mux(_T_611, deq_vec[3][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3620 = mux(_T_612, deq_vec[4][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3621 = mux(_T_613, deq_vec[5][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3622 = mux(_T_614, deq_vec[6][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3623 = mux(_T_615, deq_vec[7][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3624 = or(_T_3616, _T_3617) node _T_3625 = or(_T_3624, _T_3618) node _T_3626 = or(_T_3625, _T_3619) node _T_3627 = or(_T_3626, _T_3620) node _T_3628 = or(_T_3627, _T_3621) node _T_3629 = or(_T_3628, _T_3622) node _T_3630 = or(_T_3629, _T_3623) wire _WIRE_207 : UInt<3> connect _WIRE_207, _T_3630 connect _WIRE_116.iw_p1_speculative_child, _WIRE_207 node _T_3631 = mux(_T_608, deq_vec[0][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3632 = mux(_T_609, deq_vec[1][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3633 = mux(_T_610, deq_vec[2][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3634 = mux(_T_611, deq_vec[3][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3635 = mux(_T_612, deq_vec[4][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3636 = mux(_T_613, deq_vec[5][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3637 = mux(_T_614, deq_vec[6][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3638 = mux(_T_615, deq_vec[7][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3639 = or(_T_3631, _T_3632) node _T_3640 = or(_T_3639, _T_3633) node _T_3641 = or(_T_3640, _T_3634) node _T_3642 = or(_T_3641, _T_3635) node _T_3643 = or(_T_3642, _T_3636) node _T_3644 = or(_T_3643, _T_3637) node _T_3645 = or(_T_3644, _T_3638) wire _WIRE_208 : UInt<1> connect _WIRE_208, _T_3645 connect _WIRE_116.iw_issued_partial_dgen, _WIRE_208 node _T_3646 = mux(_T_608, deq_vec[0][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3647 = mux(_T_609, deq_vec[1][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3648 = mux(_T_610, deq_vec[2][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3649 = mux(_T_611, deq_vec[3][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3650 = mux(_T_612, deq_vec[4][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3651 = mux(_T_613, deq_vec[5][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3652 = mux(_T_614, deq_vec[6][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3653 = mux(_T_615, deq_vec[7][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3654 = or(_T_3646, _T_3647) node _T_3655 = or(_T_3654, _T_3648) node _T_3656 = or(_T_3655, _T_3649) node _T_3657 = or(_T_3656, _T_3650) node _T_3658 = or(_T_3657, _T_3651) node _T_3659 = or(_T_3658, _T_3652) node _T_3660 = or(_T_3659, _T_3653) wire _WIRE_209 : UInt<1> connect _WIRE_209, _T_3660 connect _WIRE_116.iw_issued_partial_agen, _WIRE_209 node _T_3661 = mux(_T_608, deq_vec[0][1].iw_issued, UInt<1>(0h0)) node _T_3662 = mux(_T_609, deq_vec[1][1].iw_issued, UInt<1>(0h0)) node _T_3663 = mux(_T_610, deq_vec[2][1].iw_issued, UInt<1>(0h0)) node _T_3664 = mux(_T_611, deq_vec[3][1].iw_issued, UInt<1>(0h0)) node _T_3665 = mux(_T_612, deq_vec[4][1].iw_issued, UInt<1>(0h0)) node _T_3666 = mux(_T_613, deq_vec[5][1].iw_issued, UInt<1>(0h0)) node _T_3667 = mux(_T_614, deq_vec[6][1].iw_issued, UInt<1>(0h0)) node _T_3668 = mux(_T_615, deq_vec[7][1].iw_issued, UInt<1>(0h0)) node _T_3669 = or(_T_3661, _T_3662) node _T_3670 = or(_T_3669, _T_3663) node _T_3671 = or(_T_3670, _T_3664) node _T_3672 = or(_T_3671, _T_3665) node _T_3673 = or(_T_3672, _T_3666) node _T_3674 = or(_T_3673, _T_3667) node _T_3675 = or(_T_3674, _T_3668) wire _WIRE_210 : UInt<1> connect _WIRE_210, _T_3675 connect _WIRE_116.iw_issued, _WIRE_210 wire _WIRE_211 : UInt<1>[10] node _T_3676 = mux(_T_608, deq_vec[0][1].fu_code[0], UInt<1>(0h0)) node _T_3677 = mux(_T_609, deq_vec[1][1].fu_code[0], UInt<1>(0h0)) node _T_3678 = mux(_T_610, deq_vec[2][1].fu_code[0], UInt<1>(0h0)) node _T_3679 = mux(_T_611, deq_vec[3][1].fu_code[0], UInt<1>(0h0)) node _T_3680 = mux(_T_612, deq_vec[4][1].fu_code[0], UInt<1>(0h0)) node _T_3681 = mux(_T_613, deq_vec[5][1].fu_code[0], UInt<1>(0h0)) node _T_3682 = mux(_T_614, deq_vec[6][1].fu_code[0], UInt<1>(0h0)) node _T_3683 = mux(_T_615, deq_vec[7][1].fu_code[0], UInt<1>(0h0)) node _T_3684 = or(_T_3676, _T_3677) node _T_3685 = or(_T_3684, _T_3678) node _T_3686 = or(_T_3685, _T_3679) node _T_3687 = or(_T_3686, _T_3680) node _T_3688 = or(_T_3687, _T_3681) node _T_3689 = or(_T_3688, _T_3682) node _T_3690 = or(_T_3689, _T_3683) wire _WIRE_212 : UInt<1> connect _WIRE_212, _T_3690 connect _WIRE_211[0], _WIRE_212 node _T_3691 = mux(_T_608, deq_vec[0][1].fu_code[1], UInt<1>(0h0)) node _T_3692 = mux(_T_609, deq_vec[1][1].fu_code[1], UInt<1>(0h0)) node _T_3693 = mux(_T_610, deq_vec[2][1].fu_code[1], UInt<1>(0h0)) node _T_3694 = mux(_T_611, deq_vec[3][1].fu_code[1], UInt<1>(0h0)) node _T_3695 = mux(_T_612, deq_vec[4][1].fu_code[1], UInt<1>(0h0)) node _T_3696 = mux(_T_613, deq_vec[5][1].fu_code[1], UInt<1>(0h0)) node _T_3697 = mux(_T_614, deq_vec[6][1].fu_code[1], UInt<1>(0h0)) node _T_3698 = mux(_T_615, deq_vec[7][1].fu_code[1], UInt<1>(0h0)) node _T_3699 = or(_T_3691, _T_3692) node _T_3700 = or(_T_3699, _T_3693) node _T_3701 = or(_T_3700, _T_3694) node _T_3702 = or(_T_3701, _T_3695) node _T_3703 = or(_T_3702, _T_3696) node _T_3704 = or(_T_3703, _T_3697) node _T_3705 = or(_T_3704, _T_3698) wire _WIRE_213 : UInt<1> connect _WIRE_213, _T_3705 connect _WIRE_211[1], _WIRE_213 node _T_3706 = mux(_T_608, deq_vec[0][1].fu_code[2], UInt<1>(0h0)) node _T_3707 = mux(_T_609, deq_vec[1][1].fu_code[2], UInt<1>(0h0)) node _T_3708 = mux(_T_610, deq_vec[2][1].fu_code[2], UInt<1>(0h0)) node _T_3709 = mux(_T_611, deq_vec[3][1].fu_code[2], UInt<1>(0h0)) node _T_3710 = mux(_T_612, deq_vec[4][1].fu_code[2], UInt<1>(0h0)) node _T_3711 = mux(_T_613, deq_vec[5][1].fu_code[2], UInt<1>(0h0)) node _T_3712 = mux(_T_614, deq_vec[6][1].fu_code[2], UInt<1>(0h0)) node _T_3713 = mux(_T_615, deq_vec[7][1].fu_code[2], UInt<1>(0h0)) node _T_3714 = or(_T_3706, _T_3707) node _T_3715 = or(_T_3714, _T_3708) node _T_3716 = or(_T_3715, _T_3709) node _T_3717 = or(_T_3716, _T_3710) node _T_3718 = or(_T_3717, _T_3711) node _T_3719 = or(_T_3718, _T_3712) node _T_3720 = or(_T_3719, _T_3713) wire _WIRE_214 : UInt<1> connect _WIRE_214, _T_3720 connect _WIRE_211[2], _WIRE_214 node _T_3721 = mux(_T_608, deq_vec[0][1].fu_code[3], UInt<1>(0h0)) node _T_3722 = mux(_T_609, deq_vec[1][1].fu_code[3], UInt<1>(0h0)) node _T_3723 = mux(_T_610, deq_vec[2][1].fu_code[3], UInt<1>(0h0)) node _T_3724 = mux(_T_611, deq_vec[3][1].fu_code[3], UInt<1>(0h0)) node _T_3725 = mux(_T_612, deq_vec[4][1].fu_code[3], UInt<1>(0h0)) node _T_3726 = mux(_T_613, deq_vec[5][1].fu_code[3], UInt<1>(0h0)) node _T_3727 = mux(_T_614, deq_vec[6][1].fu_code[3], UInt<1>(0h0)) node _T_3728 = mux(_T_615, deq_vec[7][1].fu_code[3], UInt<1>(0h0)) node _T_3729 = or(_T_3721, _T_3722) node _T_3730 = or(_T_3729, _T_3723) node _T_3731 = or(_T_3730, _T_3724) node _T_3732 = or(_T_3731, _T_3725) node _T_3733 = or(_T_3732, _T_3726) node _T_3734 = or(_T_3733, _T_3727) node _T_3735 = or(_T_3734, _T_3728) wire _WIRE_215 : UInt<1> connect _WIRE_215, _T_3735 connect _WIRE_211[3], _WIRE_215 node _T_3736 = mux(_T_608, deq_vec[0][1].fu_code[4], UInt<1>(0h0)) node _T_3737 = mux(_T_609, deq_vec[1][1].fu_code[4], UInt<1>(0h0)) node _T_3738 = mux(_T_610, deq_vec[2][1].fu_code[4], UInt<1>(0h0)) node _T_3739 = mux(_T_611, deq_vec[3][1].fu_code[4], UInt<1>(0h0)) node _T_3740 = mux(_T_612, deq_vec[4][1].fu_code[4], UInt<1>(0h0)) node _T_3741 = mux(_T_613, deq_vec[5][1].fu_code[4], UInt<1>(0h0)) node _T_3742 = mux(_T_614, deq_vec[6][1].fu_code[4], UInt<1>(0h0)) node _T_3743 = mux(_T_615, deq_vec[7][1].fu_code[4], UInt<1>(0h0)) node _T_3744 = or(_T_3736, _T_3737) node _T_3745 = or(_T_3744, _T_3738) node _T_3746 = or(_T_3745, _T_3739) node _T_3747 = or(_T_3746, _T_3740) node _T_3748 = or(_T_3747, _T_3741) node _T_3749 = or(_T_3748, _T_3742) node _T_3750 = or(_T_3749, _T_3743) wire _WIRE_216 : UInt<1> connect _WIRE_216, _T_3750 connect _WIRE_211[4], _WIRE_216 node _T_3751 = mux(_T_608, deq_vec[0][1].fu_code[5], UInt<1>(0h0)) node _T_3752 = mux(_T_609, deq_vec[1][1].fu_code[5], UInt<1>(0h0)) node _T_3753 = mux(_T_610, deq_vec[2][1].fu_code[5], UInt<1>(0h0)) node _T_3754 = mux(_T_611, deq_vec[3][1].fu_code[5], UInt<1>(0h0)) node _T_3755 = mux(_T_612, deq_vec[4][1].fu_code[5], UInt<1>(0h0)) node _T_3756 = mux(_T_613, deq_vec[5][1].fu_code[5], UInt<1>(0h0)) node _T_3757 = mux(_T_614, deq_vec[6][1].fu_code[5], UInt<1>(0h0)) node _T_3758 = mux(_T_615, deq_vec[7][1].fu_code[5], UInt<1>(0h0)) node _T_3759 = or(_T_3751, _T_3752) node _T_3760 = or(_T_3759, _T_3753) node _T_3761 = or(_T_3760, _T_3754) node _T_3762 = or(_T_3761, _T_3755) node _T_3763 = or(_T_3762, _T_3756) node _T_3764 = or(_T_3763, _T_3757) node _T_3765 = or(_T_3764, _T_3758) wire _WIRE_217 : UInt<1> connect _WIRE_217, _T_3765 connect _WIRE_211[5], _WIRE_217 node _T_3766 = mux(_T_608, deq_vec[0][1].fu_code[6], UInt<1>(0h0)) node _T_3767 = mux(_T_609, deq_vec[1][1].fu_code[6], UInt<1>(0h0)) node _T_3768 = mux(_T_610, deq_vec[2][1].fu_code[6], UInt<1>(0h0)) node _T_3769 = mux(_T_611, deq_vec[3][1].fu_code[6], UInt<1>(0h0)) node _T_3770 = mux(_T_612, deq_vec[4][1].fu_code[6], UInt<1>(0h0)) node _T_3771 = mux(_T_613, deq_vec[5][1].fu_code[6], UInt<1>(0h0)) node _T_3772 = mux(_T_614, deq_vec[6][1].fu_code[6], UInt<1>(0h0)) node _T_3773 = mux(_T_615, deq_vec[7][1].fu_code[6], UInt<1>(0h0)) node _T_3774 = or(_T_3766, _T_3767) node _T_3775 = or(_T_3774, _T_3768) node _T_3776 = or(_T_3775, _T_3769) node _T_3777 = or(_T_3776, _T_3770) node _T_3778 = or(_T_3777, _T_3771) node _T_3779 = or(_T_3778, _T_3772) node _T_3780 = or(_T_3779, _T_3773) wire _WIRE_218 : UInt<1> connect _WIRE_218, _T_3780 connect _WIRE_211[6], _WIRE_218 node _T_3781 = mux(_T_608, deq_vec[0][1].fu_code[7], UInt<1>(0h0)) node _T_3782 = mux(_T_609, deq_vec[1][1].fu_code[7], UInt<1>(0h0)) node _T_3783 = mux(_T_610, deq_vec[2][1].fu_code[7], UInt<1>(0h0)) node _T_3784 = mux(_T_611, deq_vec[3][1].fu_code[7], UInt<1>(0h0)) node _T_3785 = mux(_T_612, deq_vec[4][1].fu_code[7], UInt<1>(0h0)) node _T_3786 = mux(_T_613, deq_vec[5][1].fu_code[7], UInt<1>(0h0)) node _T_3787 = mux(_T_614, deq_vec[6][1].fu_code[7], UInt<1>(0h0)) node _T_3788 = mux(_T_615, deq_vec[7][1].fu_code[7], UInt<1>(0h0)) node _T_3789 = or(_T_3781, _T_3782) node _T_3790 = or(_T_3789, _T_3783) node _T_3791 = or(_T_3790, _T_3784) node _T_3792 = or(_T_3791, _T_3785) node _T_3793 = or(_T_3792, _T_3786) node _T_3794 = or(_T_3793, _T_3787) node _T_3795 = or(_T_3794, _T_3788) wire _WIRE_219 : UInt<1> connect _WIRE_219, _T_3795 connect _WIRE_211[7], _WIRE_219 node _T_3796 = mux(_T_608, deq_vec[0][1].fu_code[8], UInt<1>(0h0)) node _T_3797 = mux(_T_609, deq_vec[1][1].fu_code[8], UInt<1>(0h0)) node _T_3798 = mux(_T_610, deq_vec[2][1].fu_code[8], UInt<1>(0h0)) node _T_3799 = mux(_T_611, deq_vec[3][1].fu_code[8], UInt<1>(0h0)) node _T_3800 = mux(_T_612, deq_vec[4][1].fu_code[8], UInt<1>(0h0)) node _T_3801 = mux(_T_613, deq_vec[5][1].fu_code[8], UInt<1>(0h0)) node _T_3802 = mux(_T_614, deq_vec[6][1].fu_code[8], UInt<1>(0h0)) node _T_3803 = mux(_T_615, deq_vec[7][1].fu_code[8], UInt<1>(0h0)) node _T_3804 = or(_T_3796, _T_3797) node _T_3805 = or(_T_3804, _T_3798) node _T_3806 = or(_T_3805, _T_3799) node _T_3807 = or(_T_3806, _T_3800) node _T_3808 = or(_T_3807, _T_3801) node _T_3809 = or(_T_3808, _T_3802) node _T_3810 = or(_T_3809, _T_3803) wire _WIRE_220 : UInt<1> connect _WIRE_220, _T_3810 connect _WIRE_211[8], _WIRE_220 node _T_3811 = mux(_T_608, deq_vec[0][1].fu_code[9], UInt<1>(0h0)) node _T_3812 = mux(_T_609, deq_vec[1][1].fu_code[9], UInt<1>(0h0)) node _T_3813 = mux(_T_610, deq_vec[2][1].fu_code[9], UInt<1>(0h0)) node _T_3814 = mux(_T_611, deq_vec[3][1].fu_code[9], UInt<1>(0h0)) node _T_3815 = mux(_T_612, deq_vec[4][1].fu_code[9], UInt<1>(0h0)) node _T_3816 = mux(_T_613, deq_vec[5][1].fu_code[9], UInt<1>(0h0)) node _T_3817 = mux(_T_614, deq_vec[6][1].fu_code[9], UInt<1>(0h0)) node _T_3818 = mux(_T_615, deq_vec[7][1].fu_code[9], UInt<1>(0h0)) node _T_3819 = or(_T_3811, _T_3812) node _T_3820 = or(_T_3819, _T_3813) node _T_3821 = or(_T_3820, _T_3814) node _T_3822 = or(_T_3821, _T_3815) node _T_3823 = or(_T_3822, _T_3816) node _T_3824 = or(_T_3823, _T_3817) node _T_3825 = or(_T_3824, _T_3818) wire _WIRE_221 : UInt<1> connect _WIRE_221, _T_3825 connect _WIRE_211[9], _WIRE_221 connect _WIRE_116.fu_code, _WIRE_211 wire _WIRE_222 : UInt<1>[4] node _T_3826 = mux(_T_608, deq_vec[0][1].iq_type[0], UInt<1>(0h0)) node _T_3827 = mux(_T_609, deq_vec[1][1].iq_type[0], UInt<1>(0h0)) node _T_3828 = mux(_T_610, deq_vec[2][1].iq_type[0], UInt<1>(0h0)) node _T_3829 = mux(_T_611, deq_vec[3][1].iq_type[0], UInt<1>(0h0)) node _T_3830 = mux(_T_612, deq_vec[4][1].iq_type[0], UInt<1>(0h0)) node _T_3831 = mux(_T_613, deq_vec[5][1].iq_type[0], UInt<1>(0h0)) node _T_3832 = mux(_T_614, deq_vec[6][1].iq_type[0], UInt<1>(0h0)) node _T_3833 = mux(_T_615, deq_vec[7][1].iq_type[0], UInt<1>(0h0)) node _T_3834 = or(_T_3826, _T_3827) node _T_3835 = or(_T_3834, _T_3828) node _T_3836 = or(_T_3835, _T_3829) node _T_3837 = or(_T_3836, _T_3830) node _T_3838 = or(_T_3837, _T_3831) node _T_3839 = or(_T_3838, _T_3832) node _T_3840 = or(_T_3839, _T_3833) wire _WIRE_223 : UInt<1> connect _WIRE_223, _T_3840 connect _WIRE_222[0], _WIRE_223 node _T_3841 = mux(_T_608, deq_vec[0][1].iq_type[1], UInt<1>(0h0)) node _T_3842 = mux(_T_609, deq_vec[1][1].iq_type[1], UInt<1>(0h0)) node _T_3843 = mux(_T_610, deq_vec[2][1].iq_type[1], UInt<1>(0h0)) node _T_3844 = mux(_T_611, deq_vec[3][1].iq_type[1], UInt<1>(0h0)) node _T_3845 = mux(_T_612, deq_vec[4][1].iq_type[1], UInt<1>(0h0)) node _T_3846 = mux(_T_613, deq_vec[5][1].iq_type[1], UInt<1>(0h0)) node _T_3847 = mux(_T_614, deq_vec[6][1].iq_type[1], UInt<1>(0h0)) node _T_3848 = mux(_T_615, deq_vec[7][1].iq_type[1], UInt<1>(0h0)) node _T_3849 = or(_T_3841, _T_3842) node _T_3850 = or(_T_3849, _T_3843) node _T_3851 = or(_T_3850, _T_3844) node _T_3852 = or(_T_3851, _T_3845) node _T_3853 = or(_T_3852, _T_3846) node _T_3854 = or(_T_3853, _T_3847) node _T_3855 = or(_T_3854, _T_3848) wire _WIRE_224 : UInt<1> connect _WIRE_224, _T_3855 connect _WIRE_222[1], _WIRE_224 node _T_3856 = mux(_T_608, deq_vec[0][1].iq_type[2], UInt<1>(0h0)) node _T_3857 = mux(_T_609, deq_vec[1][1].iq_type[2], UInt<1>(0h0)) node _T_3858 = mux(_T_610, deq_vec[2][1].iq_type[2], UInt<1>(0h0)) node _T_3859 = mux(_T_611, deq_vec[3][1].iq_type[2], UInt<1>(0h0)) node _T_3860 = mux(_T_612, deq_vec[4][1].iq_type[2], UInt<1>(0h0)) node _T_3861 = mux(_T_613, deq_vec[5][1].iq_type[2], UInt<1>(0h0)) node _T_3862 = mux(_T_614, deq_vec[6][1].iq_type[2], UInt<1>(0h0)) node _T_3863 = mux(_T_615, deq_vec[7][1].iq_type[2], UInt<1>(0h0)) node _T_3864 = or(_T_3856, _T_3857) node _T_3865 = or(_T_3864, _T_3858) node _T_3866 = or(_T_3865, _T_3859) node _T_3867 = or(_T_3866, _T_3860) node _T_3868 = or(_T_3867, _T_3861) node _T_3869 = or(_T_3868, _T_3862) node _T_3870 = or(_T_3869, _T_3863) wire _WIRE_225 : UInt<1> connect _WIRE_225, _T_3870 connect _WIRE_222[2], _WIRE_225 node _T_3871 = mux(_T_608, deq_vec[0][1].iq_type[3], UInt<1>(0h0)) node _T_3872 = mux(_T_609, deq_vec[1][1].iq_type[3], UInt<1>(0h0)) node _T_3873 = mux(_T_610, deq_vec[2][1].iq_type[3], UInt<1>(0h0)) node _T_3874 = mux(_T_611, deq_vec[3][1].iq_type[3], UInt<1>(0h0)) node _T_3875 = mux(_T_612, deq_vec[4][1].iq_type[3], UInt<1>(0h0)) node _T_3876 = mux(_T_613, deq_vec[5][1].iq_type[3], UInt<1>(0h0)) node _T_3877 = mux(_T_614, deq_vec[6][1].iq_type[3], UInt<1>(0h0)) node _T_3878 = mux(_T_615, deq_vec[7][1].iq_type[3], UInt<1>(0h0)) node _T_3879 = or(_T_3871, _T_3872) node _T_3880 = or(_T_3879, _T_3873) node _T_3881 = or(_T_3880, _T_3874) node _T_3882 = or(_T_3881, _T_3875) node _T_3883 = or(_T_3882, _T_3876) node _T_3884 = or(_T_3883, _T_3877) node _T_3885 = or(_T_3884, _T_3878) wire _WIRE_226 : UInt<1> connect _WIRE_226, _T_3885 connect _WIRE_222[3], _WIRE_226 connect _WIRE_116.iq_type, _WIRE_222 node _T_3886 = mux(_T_608, deq_vec[0][1].debug_pc, UInt<1>(0h0)) node _T_3887 = mux(_T_609, deq_vec[1][1].debug_pc, UInt<1>(0h0)) node _T_3888 = mux(_T_610, deq_vec[2][1].debug_pc, UInt<1>(0h0)) node _T_3889 = mux(_T_611, deq_vec[3][1].debug_pc, UInt<1>(0h0)) node _T_3890 = mux(_T_612, deq_vec[4][1].debug_pc, UInt<1>(0h0)) node _T_3891 = mux(_T_613, deq_vec[5][1].debug_pc, UInt<1>(0h0)) node _T_3892 = mux(_T_614, deq_vec[6][1].debug_pc, UInt<1>(0h0)) node _T_3893 = mux(_T_615, deq_vec[7][1].debug_pc, UInt<1>(0h0)) node _T_3894 = or(_T_3886, _T_3887) node _T_3895 = or(_T_3894, _T_3888) node _T_3896 = or(_T_3895, _T_3889) node _T_3897 = or(_T_3896, _T_3890) node _T_3898 = or(_T_3897, _T_3891) node _T_3899 = or(_T_3898, _T_3892) node _T_3900 = or(_T_3899, _T_3893) wire _WIRE_227 : UInt<40> connect _WIRE_227, _T_3900 connect _WIRE_116.debug_pc, _WIRE_227 node _T_3901 = mux(_T_608, deq_vec[0][1].is_rvc, UInt<1>(0h0)) node _T_3902 = mux(_T_609, deq_vec[1][1].is_rvc, UInt<1>(0h0)) node _T_3903 = mux(_T_610, deq_vec[2][1].is_rvc, UInt<1>(0h0)) node _T_3904 = mux(_T_611, deq_vec[3][1].is_rvc, UInt<1>(0h0)) node _T_3905 = mux(_T_612, deq_vec[4][1].is_rvc, UInt<1>(0h0)) node _T_3906 = mux(_T_613, deq_vec[5][1].is_rvc, UInt<1>(0h0)) node _T_3907 = mux(_T_614, deq_vec[6][1].is_rvc, UInt<1>(0h0)) node _T_3908 = mux(_T_615, deq_vec[7][1].is_rvc, UInt<1>(0h0)) node _T_3909 = or(_T_3901, _T_3902) node _T_3910 = or(_T_3909, _T_3903) node _T_3911 = or(_T_3910, _T_3904) node _T_3912 = or(_T_3911, _T_3905) node _T_3913 = or(_T_3912, _T_3906) node _T_3914 = or(_T_3913, _T_3907) node _T_3915 = or(_T_3914, _T_3908) wire _WIRE_228 : UInt<1> connect _WIRE_228, _T_3915 connect _WIRE_116.is_rvc, _WIRE_228 node _T_3916 = mux(_T_608, deq_vec[0][1].debug_inst, UInt<1>(0h0)) node _T_3917 = mux(_T_609, deq_vec[1][1].debug_inst, UInt<1>(0h0)) node _T_3918 = mux(_T_610, deq_vec[2][1].debug_inst, UInt<1>(0h0)) node _T_3919 = mux(_T_611, deq_vec[3][1].debug_inst, UInt<1>(0h0)) node _T_3920 = mux(_T_612, deq_vec[4][1].debug_inst, UInt<1>(0h0)) node _T_3921 = mux(_T_613, deq_vec[5][1].debug_inst, UInt<1>(0h0)) node _T_3922 = mux(_T_614, deq_vec[6][1].debug_inst, UInt<1>(0h0)) node _T_3923 = mux(_T_615, deq_vec[7][1].debug_inst, UInt<1>(0h0)) node _T_3924 = or(_T_3916, _T_3917) node _T_3925 = or(_T_3924, _T_3918) node _T_3926 = or(_T_3925, _T_3919) node _T_3927 = or(_T_3926, _T_3920) node _T_3928 = or(_T_3927, _T_3921) node _T_3929 = or(_T_3928, _T_3922) node _T_3930 = or(_T_3929, _T_3923) wire _WIRE_229 : UInt<32> connect _WIRE_229, _T_3930 connect _WIRE_116.debug_inst, _WIRE_229 node _T_3931 = mux(_T_608, deq_vec[0][1].inst, UInt<1>(0h0)) node _T_3932 = mux(_T_609, deq_vec[1][1].inst, UInt<1>(0h0)) node _T_3933 = mux(_T_610, deq_vec[2][1].inst, UInt<1>(0h0)) node _T_3934 = mux(_T_611, deq_vec[3][1].inst, UInt<1>(0h0)) node _T_3935 = mux(_T_612, deq_vec[4][1].inst, UInt<1>(0h0)) node _T_3936 = mux(_T_613, deq_vec[5][1].inst, UInt<1>(0h0)) node _T_3937 = mux(_T_614, deq_vec[6][1].inst, UInt<1>(0h0)) node _T_3938 = mux(_T_615, deq_vec[7][1].inst, UInt<1>(0h0)) node _T_3939 = or(_T_3931, _T_3932) node _T_3940 = or(_T_3939, _T_3933) node _T_3941 = or(_T_3940, _T_3934) node _T_3942 = or(_T_3941, _T_3935) node _T_3943 = or(_T_3942, _T_3936) node _T_3944 = or(_T_3943, _T_3937) node _T_3945 = or(_T_3944, _T_3938) wire _WIRE_230 : UInt<32> connect _WIRE_230, _T_3945 connect _WIRE_116.inst, _WIRE_230 connect _WIRE[1], _WIRE_116 wire _WIRE_231 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_3946 = mux(_T_608, deq_vec[0][2].debug_tsrc, UInt<1>(0h0)) node _T_3947 = mux(_T_609, deq_vec[1][2].debug_tsrc, UInt<1>(0h0)) node _T_3948 = mux(_T_610, deq_vec[2][2].debug_tsrc, UInt<1>(0h0)) node _T_3949 = mux(_T_611, deq_vec[3][2].debug_tsrc, UInt<1>(0h0)) node _T_3950 = mux(_T_612, deq_vec[4][2].debug_tsrc, UInt<1>(0h0)) node _T_3951 = mux(_T_613, deq_vec[5][2].debug_tsrc, UInt<1>(0h0)) node _T_3952 = mux(_T_614, deq_vec[6][2].debug_tsrc, UInt<1>(0h0)) node _T_3953 = mux(_T_615, deq_vec[7][2].debug_tsrc, UInt<1>(0h0)) node _T_3954 = or(_T_3946, _T_3947) node _T_3955 = or(_T_3954, _T_3948) node _T_3956 = or(_T_3955, _T_3949) node _T_3957 = or(_T_3956, _T_3950) node _T_3958 = or(_T_3957, _T_3951) node _T_3959 = or(_T_3958, _T_3952) node _T_3960 = or(_T_3959, _T_3953) wire _WIRE_232 : UInt<3> connect _WIRE_232, _T_3960 connect _WIRE_231.debug_tsrc, _WIRE_232 node _T_3961 = mux(_T_608, deq_vec[0][2].debug_fsrc, UInt<1>(0h0)) node _T_3962 = mux(_T_609, deq_vec[1][2].debug_fsrc, UInt<1>(0h0)) node _T_3963 = mux(_T_610, deq_vec[2][2].debug_fsrc, UInt<1>(0h0)) node _T_3964 = mux(_T_611, deq_vec[3][2].debug_fsrc, UInt<1>(0h0)) node _T_3965 = mux(_T_612, deq_vec[4][2].debug_fsrc, UInt<1>(0h0)) node _T_3966 = mux(_T_613, deq_vec[5][2].debug_fsrc, UInt<1>(0h0)) node _T_3967 = mux(_T_614, deq_vec[6][2].debug_fsrc, UInt<1>(0h0)) node _T_3968 = mux(_T_615, deq_vec[7][2].debug_fsrc, UInt<1>(0h0)) node _T_3969 = or(_T_3961, _T_3962) node _T_3970 = or(_T_3969, _T_3963) node _T_3971 = or(_T_3970, _T_3964) node _T_3972 = or(_T_3971, _T_3965) node _T_3973 = or(_T_3972, _T_3966) node _T_3974 = or(_T_3973, _T_3967) node _T_3975 = or(_T_3974, _T_3968) wire _WIRE_233 : UInt<3> connect _WIRE_233, _T_3975 connect _WIRE_231.debug_fsrc, _WIRE_233 node _T_3976 = mux(_T_608, deq_vec[0][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3977 = mux(_T_609, deq_vec[1][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3978 = mux(_T_610, deq_vec[2][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3979 = mux(_T_611, deq_vec[3][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3980 = mux(_T_612, deq_vec[4][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3981 = mux(_T_613, deq_vec[5][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3982 = mux(_T_614, deq_vec[6][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3983 = mux(_T_615, deq_vec[7][2].bp_xcpt_if, UInt<1>(0h0)) node _T_3984 = or(_T_3976, _T_3977) node _T_3985 = or(_T_3984, _T_3978) node _T_3986 = or(_T_3985, _T_3979) node _T_3987 = or(_T_3986, _T_3980) node _T_3988 = or(_T_3987, _T_3981) node _T_3989 = or(_T_3988, _T_3982) node _T_3990 = or(_T_3989, _T_3983) wire _WIRE_234 : UInt<1> connect _WIRE_234, _T_3990 connect _WIRE_231.bp_xcpt_if, _WIRE_234 node _T_3991 = mux(_T_608, deq_vec[0][2].bp_debug_if, UInt<1>(0h0)) node _T_3992 = mux(_T_609, deq_vec[1][2].bp_debug_if, UInt<1>(0h0)) node _T_3993 = mux(_T_610, deq_vec[2][2].bp_debug_if, UInt<1>(0h0)) node _T_3994 = mux(_T_611, deq_vec[3][2].bp_debug_if, UInt<1>(0h0)) node _T_3995 = mux(_T_612, deq_vec[4][2].bp_debug_if, UInt<1>(0h0)) node _T_3996 = mux(_T_613, deq_vec[5][2].bp_debug_if, UInt<1>(0h0)) node _T_3997 = mux(_T_614, deq_vec[6][2].bp_debug_if, UInt<1>(0h0)) node _T_3998 = mux(_T_615, deq_vec[7][2].bp_debug_if, UInt<1>(0h0)) node _T_3999 = or(_T_3991, _T_3992) node _T_4000 = or(_T_3999, _T_3993) node _T_4001 = or(_T_4000, _T_3994) node _T_4002 = or(_T_4001, _T_3995) node _T_4003 = or(_T_4002, _T_3996) node _T_4004 = or(_T_4003, _T_3997) node _T_4005 = or(_T_4004, _T_3998) wire _WIRE_235 : UInt<1> connect _WIRE_235, _T_4005 connect _WIRE_231.bp_debug_if, _WIRE_235 node _T_4006 = mux(_T_608, deq_vec[0][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4007 = mux(_T_609, deq_vec[1][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4008 = mux(_T_610, deq_vec[2][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4009 = mux(_T_611, deq_vec[3][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4010 = mux(_T_612, deq_vec[4][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4011 = mux(_T_613, deq_vec[5][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4012 = mux(_T_614, deq_vec[6][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4013 = mux(_T_615, deq_vec[7][2].xcpt_ma_if, UInt<1>(0h0)) node _T_4014 = or(_T_4006, _T_4007) node _T_4015 = or(_T_4014, _T_4008) node _T_4016 = or(_T_4015, _T_4009) node _T_4017 = or(_T_4016, _T_4010) node _T_4018 = or(_T_4017, _T_4011) node _T_4019 = or(_T_4018, _T_4012) node _T_4020 = or(_T_4019, _T_4013) wire _WIRE_236 : UInt<1> connect _WIRE_236, _T_4020 connect _WIRE_231.xcpt_ma_if, _WIRE_236 node _T_4021 = mux(_T_608, deq_vec[0][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4022 = mux(_T_609, deq_vec[1][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4023 = mux(_T_610, deq_vec[2][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4024 = mux(_T_611, deq_vec[3][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4025 = mux(_T_612, deq_vec[4][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4026 = mux(_T_613, deq_vec[5][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4027 = mux(_T_614, deq_vec[6][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4028 = mux(_T_615, deq_vec[7][2].xcpt_ae_if, UInt<1>(0h0)) node _T_4029 = or(_T_4021, _T_4022) node _T_4030 = or(_T_4029, _T_4023) node _T_4031 = or(_T_4030, _T_4024) node _T_4032 = or(_T_4031, _T_4025) node _T_4033 = or(_T_4032, _T_4026) node _T_4034 = or(_T_4033, _T_4027) node _T_4035 = or(_T_4034, _T_4028) wire _WIRE_237 : UInt<1> connect _WIRE_237, _T_4035 connect _WIRE_231.xcpt_ae_if, _WIRE_237 node _T_4036 = mux(_T_608, deq_vec[0][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4037 = mux(_T_609, deq_vec[1][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4038 = mux(_T_610, deq_vec[2][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4039 = mux(_T_611, deq_vec[3][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4040 = mux(_T_612, deq_vec[4][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4041 = mux(_T_613, deq_vec[5][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4042 = mux(_T_614, deq_vec[6][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4043 = mux(_T_615, deq_vec[7][2].xcpt_pf_if, UInt<1>(0h0)) node _T_4044 = or(_T_4036, _T_4037) node _T_4045 = or(_T_4044, _T_4038) node _T_4046 = or(_T_4045, _T_4039) node _T_4047 = or(_T_4046, _T_4040) node _T_4048 = or(_T_4047, _T_4041) node _T_4049 = or(_T_4048, _T_4042) node _T_4050 = or(_T_4049, _T_4043) wire _WIRE_238 : UInt<1> connect _WIRE_238, _T_4050 connect _WIRE_231.xcpt_pf_if, _WIRE_238 node _T_4051 = mux(_T_608, deq_vec[0][2].fp_typ, UInt<1>(0h0)) node _T_4052 = mux(_T_609, deq_vec[1][2].fp_typ, UInt<1>(0h0)) node _T_4053 = mux(_T_610, deq_vec[2][2].fp_typ, UInt<1>(0h0)) node _T_4054 = mux(_T_611, deq_vec[3][2].fp_typ, UInt<1>(0h0)) node _T_4055 = mux(_T_612, deq_vec[4][2].fp_typ, UInt<1>(0h0)) node _T_4056 = mux(_T_613, deq_vec[5][2].fp_typ, UInt<1>(0h0)) node _T_4057 = mux(_T_614, deq_vec[6][2].fp_typ, UInt<1>(0h0)) node _T_4058 = mux(_T_615, deq_vec[7][2].fp_typ, UInt<1>(0h0)) node _T_4059 = or(_T_4051, _T_4052) node _T_4060 = or(_T_4059, _T_4053) node _T_4061 = or(_T_4060, _T_4054) node _T_4062 = or(_T_4061, _T_4055) node _T_4063 = or(_T_4062, _T_4056) node _T_4064 = or(_T_4063, _T_4057) node _T_4065 = or(_T_4064, _T_4058) wire _WIRE_239 : UInt<2> connect _WIRE_239, _T_4065 connect _WIRE_231.fp_typ, _WIRE_239 node _T_4066 = mux(_T_608, deq_vec[0][2].fp_rm, UInt<1>(0h0)) node _T_4067 = mux(_T_609, deq_vec[1][2].fp_rm, UInt<1>(0h0)) node _T_4068 = mux(_T_610, deq_vec[2][2].fp_rm, UInt<1>(0h0)) node _T_4069 = mux(_T_611, deq_vec[3][2].fp_rm, UInt<1>(0h0)) node _T_4070 = mux(_T_612, deq_vec[4][2].fp_rm, UInt<1>(0h0)) node _T_4071 = mux(_T_613, deq_vec[5][2].fp_rm, UInt<1>(0h0)) node _T_4072 = mux(_T_614, deq_vec[6][2].fp_rm, UInt<1>(0h0)) node _T_4073 = mux(_T_615, deq_vec[7][2].fp_rm, UInt<1>(0h0)) node _T_4074 = or(_T_4066, _T_4067) node _T_4075 = or(_T_4074, _T_4068) node _T_4076 = or(_T_4075, _T_4069) node _T_4077 = or(_T_4076, _T_4070) node _T_4078 = or(_T_4077, _T_4071) node _T_4079 = or(_T_4078, _T_4072) node _T_4080 = or(_T_4079, _T_4073) wire _WIRE_240 : UInt<3> connect _WIRE_240, _T_4080 connect _WIRE_231.fp_rm, _WIRE_240 node _T_4081 = mux(_T_608, deq_vec[0][2].fp_val, UInt<1>(0h0)) node _T_4082 = mux(_T_609, deq_vec[1][2].fp_val, UInt<1>(0h0)) node _T_4083 = mux(_T_610, deq_vec[2][2].fp_val, UInt<1>(0h0)) node _T_4084 = mux(_T_611, deq_vec[3][2].fp_val, UInt<1>(0h0)) node _T_4085 = mux(_T_612, deq_vec[4][2].fp_val, UInt<1>(0h0)) node _T_4086 = mux(_T_613, deq_vec[5][2].fp_val, UInt<1>(0h0)) node _T_4087 = mux(_T_614, deq_vec[6][2].fp_val, UInt<1>(0h0)) node _T_4088 = mux(_T_615, deq_vec[7][2].fp_val, UInt<1>(0h0)) node _T_4089 = or(_T_4081, _T_4082) node _T_4090 = or(_T_4089, _T_4083) node _T_4091 = or(_T_4090, _T_4084) node _T_4092 = or(_T_4091, _T_4085) node _T_4093 = or(_T_4092, _T_4086) node _T_4094 = or(_T_4093, _T_4087) node _T_4095 = or(_T_4094, _T_4088) wire _WIRE_241 : UInt<1> connect _WIRE_241, _T_4095 connect _WIRE_231.fp_val, _WIRE_241 node _T_4096 = mux(_T_608, deq_vec[0][2].fcn_op, UInt<1>(0h0)) node _T_4097 = mux(_T_609, deq_vec[1][2].fcn_op, UInt<1>(0h0)) node _T_4098 = mux(_T_610, deq_vec[2][2].fcn_op, UInt<1>(0h0)) node _T_4099 = mux(_T_611, deq_vec[3][2].fcn_op, UInt<1>(0h0)) node _T_4100 = mux(_T_612, deq_vec[4][2].fcn_op, UInt<1>(0h0)) node _T_4101 = mux(_T_613, deq_vec[5][2].fcn_op, UInt<1>(0h0)) node _T_4102 = mux(_T_614, deq_vec[6][2].fcn_op, UInt<1>(0h0)) node _T_4103 = mux(_T_615, deq_vec[7][2].fcn_op, UInt<1>(0h0)) node _T_4104 = or(_T_4096, _T_4097) node _T_4105 = or(_T_4104, _T_4098) node _T_4106 = or(_T_4105, _T_4099) node _T_4107 = or(_T_4106, _T_4100) node _T_4108 = or(_T_4107, _T_4101) node _T_4109 = or(_T_4108, _T_4102) node _T_4110 = or(_T_4109, _T_4103) wire _WIRE_242 : UInt<5> connect _WIRE_242, _T_4110 connect _WIRE_231.fcn_op, _WIRE_242 node _T_4111 = mux(_T_608, deq_vec[0][2].fcn_dw, UInt<1>(0h0)) node _T_4112 = mux(_T_609, deq_vec[1][2].fcn_dw, UInt<1>(0h0)) node _T_4113 = mux(_T_610, deq_vec[2][2].fcn_dw, UInt<1>(0h0)) node _T_4114 = mux(_T_611, deq_vec[3][2].fcn_dw, UInt<1>(0h0)) node _T_4115 = mux(_T_612, deq_vec[4][2].fcn_dw, UInt<1>(0h0)) node _T_4116 = mux(_T_613, deq_vec[5][2].fcn_dw, UInt<1>(0h0)) node _T_4117 = mux(_T_614, deq_vec[6][2].fcn_dw, UInt<1>(0h0)) node _T_4118 = mux(_T_615, deq_vec[7][2].fcn_dw, UInt<1>(0h0)) node _T_4119 = or(_T_4111, _T_4112) node _T_4120 = or(_T_4119, _T_4113) node _T_4121 = or(_T_4120, _T_4114) node _T_4122 = or(_T_4121, _T_4115) node _T_4123 = or(_T_4122, _T_4116) node _T_4124 = or(_T_4123, _T_4117) node _T_4125 = or(_T_4124, _T_4118) wire _WIRE_243 : UInt<1> connect _WIRE_243, _T_4125 connect _WIRE_231.fcn_dw, _WIRE_243 node _T_4126 = mux(_T_608, deq_vec[0][2].frs3_en, UInt<1>(0h0)) node _T_4127 = mux(_T_609, deq_vec[1][2].frs3_en, UInt<1>(0h0)) node _T_4128 = mux(_T_610, deq_vec[2][2].frs3_en, UInt<1>(0h0)) node _T_4129 = mux(_T_611, deq_vec[3][2].frs3_en, UInt<1>(0h0)) node _T_4130 = mux(_T_612, deq_vec[4][2].frs3_en, UInt<1>(0h0)) node _T_4131 = mux(_T_613, deq_vec[5][2].frs3_en, UInt<1>(0h0)) node _T_4132 = mux(_T_614, deq_vec[6][2].frs3_en, UInt<1>(0h0)) node _T_4133 = mux(_T_615, deq_vec[7][2].frs3_en, UInt<1>(0h0)) node _T_4134 = or(_T_4126, _T_4127) node _T_4135 = or(_T_4134, _T_4128) node _T_4136 = or(_T_4135, _T_4129) node _T_4137 = or(_T_4136, _T_4130) node _T_4138 = or(_T_4137, _T_4131) node _T_4139 = or(_T_4138, _T_4132) node _T_4140 = or(_T_4139, _T_4133) wire _WIRE_244 : UInt<1> connect _WIRE_244, _T_4140 connect _WIRE_231.frs3_en, _WIRE_244 node _T_4141 = mux(_T_608, deq_vec[0][2].lrs2_rtype, UInt<1>(0h0)) node _T_4142 = mux(_T_609, deq_vec[1][2].lrs2_rtype, UInt<1>(0h0)) node _T_4143 = mux(_T_610, deq_vec[2][2].lrs2_rtype, UInt<1>(0h0)) node _T_4144 = mux(_T_611, deq_vec[3][2].lrs2_rtype, UInt<1>(0h0)) node _T_4145 = mux(_T_612, deq_vec[4][2].lrs2_rtype, UInt<1>(0h0)) node _T_4146 = mux(_T_613, deq_vec[5][2].lrs2_rtype, UInt<1>(0h0)) node _T_4147 = mux(_T_614, deq_vec[6][2].lrs2_rtype, UInt<1>(0h0)) node _T_4148 = mux(_T_615, deq_vec[7][2].lrs2_rtype, UInt<1>(0h0)) node _T_4149 = or(_T_4141, _T_4142) node _T_4150 = or(_T_4149, _T_4143) node _T_4151 = or(_T_4150, _T_4144) node _T_4152 = or(_T_4151, _T_4145) node _T_4153 = or(_T_4152, _T_4146) node _T_4154 = or(_T_4153, _T_4147) node _T_4155 = or(_T_4154, _T_4148) wire _WIRE_245 : UInt<2> connect _WIRE_245, _T_4155 connect _WIRE_231.lrs2_rtype, _WIRE_245 node _T_4156 = mux(_T_608, deq_vec[0][2].lrs1_rtype, UInt<1>(0h0)) node _T_4157 = mux(_T_609, deq_vec[1][2].lrs1_rtype, UInt<1>(0h0)) node _T_4158 = mux(_T_610, deq_vec[2][2].lrs1_rtype, UInt<1>(0h0)) node _T_4159 = mux(_T_611, deq_vec[3][2].lrs1_rtype, UInt<1>(0h0)) node _T_4160 = mux(_T_612, deq_vec[4][2].lrs1_rtype, UInt<1>(0h0)) node _T_4161 = mux(_T_613, deq_vec[5][2].lrs1_rtype, UInt<1>(0h0)) node _T_4162 = mux(_T_614, deq_vec[6][2].lrs1_rtype, UInt<1>(0h0)) node _T_4163 = mux(_T_615, deq_vec[7][2].lrs1_rtype, UInt<1>(0h0)) node _T_4164 = or(_T_4156, _T_4157) node _T_4165 = or(_T_4164, _T_4158) node _T_4166 = or(_T_4165, _T_4159) node _T_4167 = or(_T_4166, _T_4160) node _T_4168 = or(_T_4167, _T_4161) node _T_4169 = or(_T_4168, _T_4162) node _T_4170 = or(_T_4169, _T_4163) wire _WIRE_246 : UInt<2> connect _WIRE_246, _T_4170 connect _WIRE_231.lrs1_rtype, _WIRE_246 node _T_4171 = mux(_T_608, deq_vec[0][2].dst_rtype, UInt<1>(0h0)) node _T_4172 = mux(_T_609, deq_vec[1][2].dst_rtype, UInt<1>(0h0)) node _T_4173 = mux(_T_610, deq_vec[2][2].dst_rtype, UInt<1>(0h0)) node _T_4174 = mux(_T_611, deq_vec[3][2].dst_rtype, UInt<1>(0h0)) node _T_4175 = mux(_T_612, deq_vec[4][2].dst_rtype, UInt<1>(0h0)) node _T_4176 = mux(_T_613, deq_vec[5][2].dst_rtype, UInt<1>(0h0)) node _T_4177 = mux(_T_614, deq_vec[6][2].dst_rtype, UInt<1>(0h0)) node _T_4178 = mux(_T_615, deq_vec[7][2].dst_rtype, UInt<1>(0h0)) node _T_4179 = or(_T_4171, _T_4172) node _T_4180 = or(_T_4179, _T_4173) node _T_4181 = or(_T_4180, _T_4174) node _T_4182 = or(_T_4181, _T_4175) node _T_4183 = or(_T_4182, _T_4176) node _T_4184 = or(_T_4183, _T_4177) node _T_4185 = or(_T_4184, _T_4178) wire _WIRE_247 : UInt<2> connect _WIRE_247, _T_4185 connect _WIRE_231.dst_rtype, _WIRE_247 node _T_4186 = mux(_T_608, deq_vec[0][2].lrs3, UInt<1>(0h0)) node _T_4187 = mux(_T_609, deq_vec[1][2].lrs3, UInt<1>(0h0)) node _T_4188 = mux(_T_610, deq_vec[2][2].lrs3, UInt<1>(0h0)) node _T_4189 = mux(_T_611, deq_vec[3][2].lrs3, UInt<1>(0h0)) node _T_4190 = mux(_T_612, deq_vec[4][2].lrs3, UInt<1>(0h0)) node _T_4191 = mux(_T_613, deq_vec[5][2].lrs3, UInt<1>(0h0)) node _T_4192 = mux(_T_614, deq_vec[6][2].lrs3, UInt<1>(0h0)) node _T_4193 = mux(_T_615, deq_vec[7][2].lrs3, UInt<1>(0h0)) node _T_4194 = or(_T_4186, _T_4187) node _T_4195 = or(_T_4194, _T_4188) node _T_4196 = or(_T_4195, _T_4189) node _T_4197 = or(_T_4196, _T_4190) node _T_4198 = or(_T_4197, _T_4191) node _T_4199 = or(_T_4198, _T_4192) node _T_4200 = or(_T_4199, _T_4193) wire _WIRE_248 : UInt<6> connect _WIRE_248, _T_4200 connect _WIRE_231.lrs3, _WIRE_248 node _T_4201 = mux(_T_608, deq_vec[0][2].lrs2, UInt<1>(0h0)) node _T_4202 = mux(_T_609, deq_vec[1][2].lrs2, UInt<1>(0h0)) node _T_4203 = mux(_T_610, deq_vec[2][2].lrs2, UInt<1>(0h0)) node _T_4204 = mux(_T_611, deq_vec[3][2].lrs2, UInt<1>(0h0)) node _T_4205 = mux(_T_612, deq_vec[4][2].lrs2, UInt<1>(0h0)) node _T_4206 = mux(_T_613, deq_vec[5][2].lrs2, UInt<1>(0h0)) node _T_4207 = mux(_T_614, deq_vec[6][2].lrs2, UInt<1>(0h0)) node _T_4208 = mux(_T_615, deq_vec[7][2].lrs2, UInt<1>(0h0)) node _T_4209 = or(_T_4201, _T_4202) node _T_4210 = or(_T_4209, _T_4203) node _T_4211 = or(_T_4210, _T_4204) node _T_4212 = or(_T_4211, _T_4205) node _T_4213 = or(_T_4212, _T_4206) node _T_4214 = or(_T_4213, _T_4207) node _T_4215 = or(_T_4214, _T_4208) wire _WIRE_249 : UInt<6> connect _WIRE_249, _T_4215 connect _WIRE_231.lrs2, _WIRE_249 node _T_4216 = mux(_T_608, deq_vec[0][2].lrs1, UInt<1>(0h0)) node _T_4217 = mux(_T_609, deq_vec[1][2].lrs1, UInt<1>(0h0)) node _T_4218 = mux(_T_610, deq_vec[2][2].lrs1, UInt<1>(0h0)) node _T_4219 = mux(_T_611, deq_vec[3][2].lrs1, UInt<1>(0h0)) node _T_4220 = mux(_T_612, deq_vec[4][2].lrs1, UInt<1>(0h0)) node _T_4221 = mux(_T_613, deq_vec[5][2].lrs1, UInt<1>(0h0)) node _T_4222 = mux(_T_614, deq_vec[6][2].lrs1, UInt<1>(0h0)) node _T_4223 = mux(_T_615, deq_vec[7][2].lrs1, UInt<1>(0h0)) node _T_4224 = or(_T_4216, _T_4217) node _T_4225 = or(_T_4224, _T_4218) node _T_4226 = or(_T_4225, _T_4219) node _T_4227 = or(_T_4226, _T_4220) node _T_4228 = or(_T_4227, _T_4221) node _T_4229 = or(_T_4228, _T_4222) node _T_4230 = or(_T_4229, _T_4223) wire _WIRE_250 : UInt<6> connect _WIRE_250, _T_4230 connect _WIRE_231.lrs1, _WIRE_250 node _T_4231 = mux(_T_608, deq_vec[0][2].ldst, UInt<1>(0h0)) node _T_4232 = mux(_T_609, deq_vec[1][2].ldst, UInt<1>(0h0)) node _T_4233 = mux(_T_610, deq_vec[2][2].ldst, UInt<1>(0h0)) node _T_4234 = mux(_T_611, deq_vec[3][2].ldst, UInt<1>(0h0)) node _T_4235 = mux(_T_612, deq_vec[4][2].ldst, UInt<1>(0h0)) node _T_4236 = mux(_T_613, deq_vec[5][2].ldst, UInt<1>(0h0)) node _T_4237 = mux(_T_614, deq_vec[6][2].ldst, UInt<1>(0h0)) node _T_4238 = mux(_T_615, deq_vec[7][2].ldst, UInt<1>(0h0)) node _T_4239 = or(_T_4231, _T_4232) node _T_4240 = or(_T_4239, _T_4233) node _T_4241 = or(_T_4240, _T_4234) node _T_4242 = or(_T_4241, _T_4235) node _T_4243 = or(_T_4242, _T_4236) node _T_4244 = or(_T_4243, _T_4237) node _T_4245 = or(_T_4244, _T_4238) wire _WIRE_251 : UInt<6> connect _WIRE_251, _T_4245 connect _WIRE_231.ldst, _WIRE_251 node _T_4246 = mux(_T_608, deq_vec[0][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4247 = mux(_T_609, deq_vec[1][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4248 = mux(_T_610, deq_vec[2][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4249 = mux(_T_611, deq_vec[3][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4250 = mux(_T_612, deq_vec[4][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4251 = mux(_T_613, deq_vec[5][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4252 = mux(_T_614, deq_vec[6][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4253 = mux(_T_615, deq_vec[7][2].ldst_is_rs1, UInt<1>(0h0)) node _T_4254 = or(_T_4246, _T_4247) node _T_4255 = or(_T_4254, _T_4248) node _T_4256 = or(_T_4255, _T_4249) node _T_4257 = or(_T_4256, _T_4250) node _T_4258 = or(_T_4257, _T_4251) node _T_4259 = or(_T_4258, _T_4252) node _T_4260 = or(_T_4259, _T_4253) wire _WIRE_252 : UInt<1> connect _WIRE_252, _T_4260 connect _WIRE_231.ldst_is_rs1, _WIRE_252 node _T_4261 = mux(_T_608, deq_vec[0][2].csr_cmd, UInt<1>(0h0)) node _T_4262 = mux(_T_609, deq_vec[1][2].csr_cmd, UInt<1>(0h0)) node _T_4263 = mux(_T_610, deq_vec[2][2].csr_cmd, UInt<1>(0h0)) node _T_4264 = mux(_T_611, deq_vec[3][2].csr_cmd, UInt<1>(0h0)) node _T_4265 = mux(_T_612, deq_vec[4][2].csr_cmd, UInt<1>(0h0)) node _T_4266 = mux(_T_613, deq_vec[5][2].csr_cmd, UInt<1>(0h0)) node _T_4267 = mux(_T_614, deq_vec[6][2].csr_cmd, UInt<1>(0h0)) node _T_4268 = mux(_T_615, deq_vec[7][2].csr_cmd, UInt<1>(0h0)) node _T_4269 = or(_T_4261, _T_4262) node _T_4270 = or(_T_4269, _T_4263) node _T_4271 = or(_T_4270, _T_4264) node _T_4272 = or(_T_4271, _T_4265) node _T_4273 = or(_T_4272, _T_4266) node _T_4274 = or(_T_4273, _T_4267) node _T_4275 = or(_T_4274, _T_4268) wire _WIRE_253 : UInt<3> connect _WIRE_253, _T_4275 connect _WIRE_231.csr_cmd, _WIRE_253 node _T_4276 = mux(_T_608, deq_vec[0][2].flush_on_commit, UInt<1>(0h0)) node _T_4277 = mux(_T_609, deq_vec[1][2].flush_on_commit, UInt<1>(0h0)) node _T_4278 = mux(_T_610, deq_vec[2][2].flush_on_commit, UInt<1>(0h0)) node _T_4279 = mux(_T_611, deq_vec[3][2].flush_on_commit, UInt<1>(0h0)) node _T_4280 = mux(_T_612, deq_vec[4][2].flush_on_commit, UInt<1>(0h0)) node _T_4281 = mux(_T_613, deq_vec[5][2].flush_on_commit, UInt<1>(0h0)) node _T_4282 = mux(_T_614, deq_vec[6][2].flush_on_commit, UInt<1>(0h0)) node _T_4283 = mux(_T_615, deq_vec[7][2].flush_on_commit, UInt<1>(0h0)) node _T_4284 = or(_T_4276, _T_4277) node _T_4285 = or(_T_4284, _T_4278) node _T_4286 = or(_T_4285, _T_4279) node _T_4287 = or(_T_4286, _T_4280) node _T_4288 = or(_T_4287, _T_4281) node _T_4289 = or(_T_4288, _T_4282) node _T_4290 = or(_T_4289, _T_4283) wire _WIRE_254 : UInt<1> connect _WIRE_254, _T_4290 connect _WIRE_231.flush_on_commit, _WIRE_254 node _T_4291 = mux(_T_608, deq_vec[0][2].is_unique, UInt<1>(0h0)) node _T_4292 = mux(_T_609, deq_vec[1][2].is_unique, UInt<1>(0h0)) node _T_4293 = mux(_T_610, deq_vec[2][2].is_unique, UInt<1>(0h0)) node _T_4294 = mux(_T_611, deq_vec[3][2].is_unique, UInt<1>(0h0)) node _T_4295 = mux(_T_612, deq_vec[4][2].is_unique, UInt<1>(0h0)) node _T_4296 = mux(_T_613, deq_vec[5][2].is_unique, UInt<1>(0h0)) node _T_4297 = mux(_T_614, deq_vec[6][2].is_unique, UInt<1>(0h0)) node _T_4298 = mux(_T_615, deq_vec[7][2].is_unique, UInt<1>(0h0)) node _T_4299 = or(_T_4291, _T_4292) node _T_4300 = or(_T_4299, _T_4293) node _T_4301 = or(_T_4300, _T_4294) node _T_4302 = or(_T_4301, _T_4295) node _T_4303 = or(_T_4302, _T_4296) node _T_4304 = or(_T_4303, _T_4297) node _T_4305 = or(_T_4304, _T_4298) wire _WIRE_255 : UInt<1> connect _WIRE_255, _T_4305 connect _WIRE_231.is_unique, _WIRE_255 node _T_4306 = mux(_T_608, deq_vec[0][2].uses_stq, UInt<1>(0h0)) node _T_4307 = mux(_T_609, deq_vec[1][2].uses_stq, UInt<1>(0h0)) node _T_4308 = mux(_T_610, deq_vec[2][2].uses_stq, UInt<1>(0h0)) node _T_4309 = mux(_T_611, deq_vec[3][2].uses_stq, UInt<1>(0h0)) node _T_4310 = mux(_T_612, deq_vec[4][2].uses_stq, UInt<1>(0h0)) node _T_4311 = mux(_T_613, deq_vec[5][2].uses_stq, UInt<1>(0h0)) node _T_4312 = mux(_T_614, deq_vec[6][2].uses_stq, UInt<1>(0h0)) node _T_4313 = mux(_T_615, deq_vec[7][2].uses_stq, UInt<1>(0h0)) node _T_4314 = or(_T_4306, _T_4307) node _T_4315 = or(_T_4314, _T_4308) node _T_4316 = or(_T_4315, _T_4309) node _T_4317 = or(_T_4316, _T_4310) node _T_4318 = or(_T_4317, _T_4311) node _T_4319 = or(_T_4318, _T_4312) node _T_4320 = or(_T_4319, _T_4313) wire _WIRE_256 : UInt<1> connect _WIRE_256, _T_4320 connect _WIRE_231.uses_stq, _WIRE_256 node _T_4321 = mux(_T_608, deq_vec[0][2].uses_ldq, UInt<1>(0h0)) node _T_4322 = mux(_T_609, deq_vec[1][2].uses_ldq, UInt<1>(0h0)) node _T_4323 = mux(_T_610, deq_vec[2][2].uses_ldq, UInt<1>(0h0)) node _T_4324 = mux(_T_611, deq_vec[3][2].uses_ldq, UInt<1>(0h0)) node _T_4325 = mux(_T_612, deq_vec[4][2].uses_ldq, UInt<1>(0h0)) node _T_4326 = mux(_T_613, deq_vec[5][2].uses_ldq, UInt<1>(0h0)) node _T_4327 = mux(_T_614, deq_vec[6][2].uses_ldq, UInt<1>(0h0)) node _T_4328 = mux(_T_615, deq_vec[7][2].uses_ldq, UInt<1>(0h0)) node _T_4329 = or(_T_4321, _T_4322) node _T_4330 = or(_T_4329, _T_4323) node _T_4331 = or(_T_4330, _T_4324) node _T_4332 = or(_T_4331, _T_4325) node _T_4333 = or(_T_4332, _T_4326) node _T_4334 = or(_T_4333, _T_4327) node _T_4335 = or(_T_4334, _T_4328) wire _WIRE_257 : UInt<1> connect _WIRE_257, _T_4335 connect _WIRE_231.uses_ldq, _WIRE_257 node _T_4336 = mux(_T_608, deq_vec[0][2].mem_signed, UInt<1>(0h0)) node _T_4337 = mux(_T_609, deq_vec[1][2].mem_signed, UInt<1>(0h0)) node _T_4338 = mux(_T_610, deq_vec[2][2].mem_signed, UInt<1>(0h0)) node _T_4339 = mux(_T_611, deq_vec[3][2].mem_signed, UInt<1>(0h0)) node _T_4340 = mux(_T_612, deq_vec[4][2].mem_signed, UInt<1>(0h0)) node _T_4341 = mux(_T_613, deq_vec[5][2].mem_signed, UInt<1>(0h0)) node _T_4342 = mux(_T_614, deq_vec[6][2].mem_signed, UInt<1>(0h0)) node _T_4343 = mux(_T_615, deq_vec[7][2].mem_signed, UInt<1>(0h0)) node _T_4344 = or(_T_4336, _T_4337) node _T_4345 = or(_T_4344, _T_4338) node _T_4346 = or(_T_4345, _T_4339) node _T_4347 = or(_T_4346, _T_4340) node _T_4348 = or(_T_4347, _T_4341) node _T_4349 = or(_T_4348, _T_4342) node _T_4350 = or(_T_4349, _T_4343) wire _WIRE_258 : UInt<1> connect _WIRE_258, _T_4350 connect _WIRE_231.mem_signed, _WIRE_258 node _T_4351 = mux(_T_608, deq_vec[0][2].mem_size, UInt<1>(0h0)) node _T_4352 = mux(_T_609, deq_vec[1][2].mem_size, UInt<1>(0h0)) node _T_4353 = mux(_T_610, deq_vec[2][2].mem_size, UInt<1>(0h0)) node _T_4354 = mux(_T_611, deq_vec[3][2].mem_size, UInt<1>(0h0)) node _T_4355 = mux(_T_612, deq_vec[4][2].mem_size, UInt<1>(0h0)) node _T_4356 = mux(_T_613, deq_vec[5][2].mem_size, UInt<1>(0h0)) node _T_4357 = mux(_T_614, deq_vec[6][2].mem_size, UInt<1>(0h0)) node _T_4358 = mux(_T_615, deq_vec[7][2].mem_size, UInt<1>(0h0)) node _T_4359 = or(_T_4351, _T_4352) node _T_4360 = or(_T_4359, _T_4353) node _T_4361 = or(_T_4360, _T_4354) node _T_4362 = or(_T_4361, _T_4355) node _T_4363 = or(_T_4362, _T_4356) node _T_4364 = or(_T_4363, _T_4357) node _T_4365 = or(_T_4364, _T_4358) wire _WIRE_259 : UInt<2> connect _WIRE_259, _T_4365 connect _WIRE_231.mem_size, _WIRE_259 node _T_4366 = mux(_T_608, deq_vec[0][2].mem_cmd, UInt<1>(0h0)) node _T_4367 = mux(_T_609, deq_vec[1][2].mem_cmd, UInt<1>(0h0)) node _T_4368 = mux(_T_610, deq_vec[2][2].mem_cmd, UInt<1>(0h0)) node _T_4369 = mux(_T_611, deq_vec[3][2].mem_cmd, UInt<1>(0h0)) node _T_4370 = mux(_T_612, deq_vec[4][2].mem_cmd, UInt<1>(0h0)) node _T_4371 = mux(_T_613, deq_vec[5][2].mem_cmd, UInt<1>(0h0)) node _T_4372 = mux(_T_614, deq_vec[6][2].mem_cmd, UInt<1>(0h0)) node _T_4373 = mux(_T_615, deq_vec[7][2].mem_cmd, UInt<1>(0h0)) node _T_4374 = or(_T_4366, _T_4367) node _T_4375 = or(_T_4374, _T_4368) node _T_4376 = or(_T_4375, _T_4369) node _T_4377 = or(_T_4376, _T_4370) node _T_4378 = or(_T_4377, _T_4371) node _T_4379 = or(_T_4378, _T_4372) node _T_4380 = or(_T_4379, _T_4373) wire _WIRE_260 : UInt<5> connect _WIRE_260, _T_4380 connect _WIRE_231.mem_cmd, _WIRE_260 node _T_4381 = mux(_T_608, deq_vec[0][2].exc_cause, UInt<1>(0h0)) node _T_4382 = mux(_T_609, deq_vec[1][2].exc_cause, UInt<1>(0h0)) node _T_4383 = mux(_T_610, deq_vec[2][2].exc_cause, UInt<1>(0h0)) node _T_4384 = mux(_T_611, deq_vec[3][2].exc_cause, UInt<1>(0h0)) node _T_4385 = mux(_T_612, deq_vec[4][2].exc_cause, UInt<1>(0h0)) node _T_4386 = mux(_T_613, deq_vec[5][2].exc_cause, UInt<1>(0h0)) node _T_4387 = mux(_T_614, deq_vec[6][2].exc_cause, UInt<1>(0h0)) node _T_4388 = mux(_T_615, deq_vec[7][2].exc_cause, UInt<1>(0h0)) node _T_4389 = or(_T_4381, _T_4382) node _T_4390 = or(_T_4389, _T_4383) node _T_4391 = or(_T_4390, _T_4384) node _T_4392 = or(_T_4391, _T_4385) node _T_4393 = or(_T_4392, _T_4386) node _T_4394 = or(_T_4393, _T_4387) node _T_4395 = or(_T_4394, _T_4388) wire _WIRE_261 : UInt<64> connect _WIRE_261, _T_4395 connect _WIRE_231.exc_cause, _WIRE_261 node _T_4396 = mux(_T_608, deq_vec[0][2].exception, UInt<1>(0h0)) node _T_4397 = mux(_T_609, deq_vec[1][2].exception, UInt<1>(0h0)) node _T_4398 = mux(_T_610, deq_vec[2][2].exception, UInt<1>(0h0)) node _T_4399 = mux(_T_611, deq_vec[3][2].exception, UInt<1>(0h0)) node _T_4400 = mux(_T_612, deq_vec[4][2].exception, UInt<1>(0h0)) node _T_4401 = mux(_T_613, deq_vec[5][2].exception, UInt<1>(0h0)) node _T_4402 = mux(_T_614, deq_vec[6][2].exception, UInt<1>(0h0)) node _T_4403 = mux(_T_615, deq_vec[7][2].exception, UInt<1>(0h0)) node _T_4404 = or(_T_4396, _T_4397) node _T_4405 = or(_T_4404, _T_4398) node _T_4406 = or(_T_4405, _T_4399) node _T_4407 = or(_T_4406, _T_4400) node _T_4408 = or(_T_4407, _T_4401) node _T_4409 = or(_T_4408, _T_4402) node _T_4410 = or(_T_4409, _T_4403) wire _WIRE_262 : UInt<1> connect _WIRE_262, _T_4410 connect _WIRE_231.exception, _WIRE_262 node _T_4411 = mux(_T_608, deq_vec[0][2].stale_pdst, UInt<1>(0h0)) node _T_4412 = mux(_T_609, deq_vec[1][2].stale_pdst, UInt<1>(0h0)) node _T_4413 = mux(_T_610, deq_vec[2][2].stale_pdst, UInt<1>(0h0)) node _T_4414 = mux(_T_611, deq_vec[3][2].stale_pdst, UInt<1>(0h0)) node _T_4415 = mux(_T_612, deq_vec[4][2].stale_pdst, UInt<1>(0h0)) node _T_4416 = mux(_T_613, deq_vec[5][2].stale_pdst, UInt<1>(0h0)) node _T_4417 = mux(_T_614, deq_vec[6][2].stale_pdst, UInt<1>(0h0)) node _T_4418 = mux(_T_615, deq_vec[7][2].stale_pdst, UInt<1>(0h0)) node _T_4419 = or(_T_4411, _T_4412) node _T_4420 = or(_T_4419, _T_4413) node _T_4421 = or(_T_4420, _T_4414) node _T_4422 = or(_T_4421, _T_4415) node _T_4423 = or(_T_4422, _T_4416) node _T_4424 = or(_T_4423, _T_4417) node _T_4425 = or(_T_4424, _T_4418) wire _WIRE_263 : UInt<7> connect _WIRE_263, _T_4425 connect _WIRE_231.stale_pdst, _WIRE_263 node _T_4426 = mux(_T_608, deq_vec[0][2].ppred_busy, UInt<1>(0h0)) node _T_4427 = mux(_T_609, deq_vec[1][2].ppred_busy, UInt<1>(0h0)) node _T_4428 = mux(_T_610, deq_vec[2][2].ppred_busy, UInt<1>(0h0)) node _T_4429 = mux(_T_611, deq_vec[3][2].ppred_busy, UInt<1>(0h0)) node _T_4430 = mux(_T_612, deq_vec[4][2].ppred_busy, UInt<1>(0h0)) node _T_4431 = mux(_T_613, deq_vec[5][2].ppred_busy, UInt<1>(0h0)) node _T_4432 = mux(_T_614, deq_vec[6][2].ppred_busy, UInt<1>(0h0)) node _T_4433 = mux(_T_615, deq_vec[7][2].ppred_busy, UInt<1>(0h0)) node _T_4434 = or(_T_4426, _T_4427) node _T_4435 = or(_T_4434, _T_4428) node _T_4436 = or(_T_4435, _T_4429) node _T_4437 = or(_T_4436, _T_4430) node _T_4438 = or(_T_4437, _T_4431) node _T_4439 = or(_T_4438, _T_4432) node _T_4440 = or(_T_4439, _T_4433) wire _WIRE_264 : UInt<1> connect _WIRE_264, _T_4440 connect _WIRE_231.ppred_busy, _WIRE_264 node _T_4441 = mux(_T_608, deq_vec[0][2].prs3_busy, UInt<1>(0h0)) node _T_4442 = mux(_T_609, deq_vec[1][2].prs3_busy, UInt<1>(0h0)) node _T_4443 = mux(_T_610, deq_vec[2][2].prs3_busy, UInt<1>(0h0)) node _T_4444 = mux(_T_611, deq_vec[3][2].prs3_busy, UInt<1>(0h0)) node _T_4445 = mux(_T_612, deq_vec[4][2].prs3_busy, UInt<1>(0h0)) node _T_4446 = mux(_T_613, deq_vec[5][2].prs3_busy, UInt<1>(0h0)) node _T_4447 = mux(_T_614, deq_vec[6][2].prs3_busy, UInt<1>(0h0)) node _T_4448 = mux(_T_615, deq_vec[7][2].prs3_busy, UInt<1>(0h0)) node _T_4449 = or(_T_4441, _T_4442) node _T_4450 = or(_T_4449, _T_4443) node _T_4451 = or(_T_4450, _T_4444) node _T_4452 = or(_T_4451, _T_4445) node _T_4453 = or(_T_4452, _T_4446) node _T_4454 = or(_T_4453, _T_4447) node _T_4455 = or(_T_4454, _T_4448) wire _WIRE_265 : UInt<1> connect _WIRE_265, _T_4455 connect _WIRE_231.prs3_busy, _WIRE_265 node _T_4456 = mux(_T_608, deq_vec[0][2].prs2_busy, UInt<1>(0h0)) node _T_4457 = mux(_T_609, deq_vec[1][2].prs2_busy, UInt<1>(0h0)) node _T_4458 = mux(_T_610, deq_vec[2][2].prs2_busy, UInt<1>(0h0)) node _T_4459 = mux(_T_611, deq_vec[3][2].prs2_busy, UInt<1>(0h0)) node _T_4460 = mux(_T_612, deq_vec[4][2].prs2_busy, UInt<1>(0h0)) node _T_4461 = mux(_T_613, deq_vec[5][2].prs2_busy, UInt<1>(0h0)) node _T_4462 = mux(_T_614, deq_vec[6][2].prs2_busy, UInt<1>(0h0)) node _T_4463 = mux(_T_615, deq_vec[7][2].prs2_busy, UInt<1>(0h0)) node _T_4464 = or(_T_4456, _T_4457) node _T_4465 = or(_T_4464, _T_4458) node _T_4466 = or(_T_4465, _T_4459) node _T_4467 = or(_T_4466, _T_4460) node _T_4468 = or(_T_4467, _T_4461) node _T_4469 = or(_T_4468, _T_4462) node _T_4470 = or(_T_4469, _T_4463) wire _WIRE_266 : UInt<1> connect _WIRE_266, _T_4470 connect _WIRE_231.prs2_busy, _WIRE_266 node _T_4471 = mux(_T_608, deq_vec[0][2].prs1_busy, UInt<1>(0h0)) node _T_4472 = mux(_T_609, deq_vec[1][2].prs1_busy, UInt<1>(0h0)) node _T_4473 = mux(_T_610, deq_vec[2][2].prs1_busy, UInt<1>(0h0)) node _T_4474 = mux(_T_611, deq_vec[3][2].prs1_busy, UInt<1>(0h0)) node _T_4475 = mux(_T_612, deq_vec[4][2].prs1_busy, UInt<1>(0h0)) node _T_4476 = mux(_T_613, deq_vec[5][2].prs1_busy, UInt<1>(0h0)) node _T_4477 = mux(_T_614, deq_vec[6][2].prs1_busy, UInt<1>(0h0)) node _T_4478 = mux(_T_615, deq_vec[7][2].prs1_busy, UInt<1>(0h0)) node _T_4479 = or(_T_4471, _T_4472) node _T_4480 = or(_T_4479, _T_4473) node _T_4481 = or(_T_4480, _T_4474) node _T_4482 = or(_T_4481, _T_4475) node _T_4483 = or(_T_4482, _T_4476) node _T_4484 = or(_T_4483, _T_4477) node _T_4485 = or(_T_4484, _T_4478) wire _WIRE_267 : UInt<1> connect _WIRE_267, _T_4485 connect _WIRE_231.prs1_busy, _WIRE_267 node _T_4486 = mux(_T_608, deq_vec[0][2].ppred, UInt<1>(0h0)) node _T_4487 = mux(_T_609, deq_vec[1][2].ppred, UInt<1>(0h0)) node _T_4488 = mux(_T_610, deq_vec[2][2].ppred, UInt<1>(0h0)) node _T_4489 = mux(_T_611, deq_vec[3][2].ppred, UInt<1>(0h0)) node _T_4490 = mux(_T_612, deq_vec[4][2].ppred, UInt<1>(0h0)) node _T_4491 = mux(_T_613, deq_vec[5][2].ppred, UInt<1>(0h0)) node _T_4492 = mux(_T_614, deq_vec[6][2].ppred, UInt<1>(0h0)) node _T_4493 = mux(_T_615, deq_vec[7][2].ppred, UInt<1>(0h0)) node _T_4494 = or(_T_4486, _T_4487) node _T_4495 = or(_T_4494, _T_4488) node _T_4496 = or(_T_4495, _T_4489) node _T_4497 = or(_T_4496, _T_4490) node _T_4498 = or(_T_4497, _T_4491) node _T_4499 = or(_T_4498, _T_4492) node _T_4500 = or(_T_4499, _T_4493) wire _WIRE_268 : UInt<5> connect _WIRE_268, _T_4500 connect _WIRE_231.ppred, _WIRE_268 node _T_4501 = mux(_T_608, deq_vec[0][2].prs3, UInt<1>(0h0)) node _T_4502 = mux(_T_609, deq_vec[1][2].prs3, UInt<1>(0h0)) node _T_4503 = mux(_T_610, deq_vec[2][2].prs3, UInt<1>(0h0)) node _T_4504 = mux(_T_611, deq_vec[3][2].prs3, UInt<1>(0h0)) node _T_4505 = mux(_T_612, deq_vec[4][2].prs3, UInt<1>(0h0)) node _T_4506 = mux(_T_613, deq_vec[5][2].prs3, UInt<1>(0h0)) node _T_4507 = mux(_T_614, deq_vec[6][2].prs3, UInt<1>(0h0)) node _T_4508 = mux(_T_615, deq_vec[7][2].prs3, UInt<1>(0h0)) node _T_4509 = or(_T_4501, _T_4502) node _T_4510 = or(_T_4509, _T_4503) node _T_4511 = or(_T_4510, _T_4504) node _T_4512 = or(_T_4511, _T_4505) node _T_4513 = or(_T_4512, _T_4506) node _T_4514 = or(_T_4513, _T_4507) node _T_4515 = or(_T_4514, _T_4508) wire _WIRE_269 : UInt<7> connect _WIRE_269, _T_4515 connect _WIRE_231.prs3, _WIRE_269 node _T_4516 = mux(_T_608, deq_vec[0][2].prs2, UInt<1>(0h0)) node _T_4517 = mux(_T_609, deq_vec[1][2].prs2, UInt<1>(0h0)) node _T_4518 = mux(_T_610, deq_vec[2][2].prs2, UInt<1>(0h0)) node _T_4519 = mux(_T_611, deq_vec[3][2].prs2, UInt<1>(0h0)) node _T_4520 = mux(_T_612, deq_vec[4][2].prs2, UInt<1>(0h0)) node _T_4521 = mux(_T_613, deq_vec[5][2].prs2, UInt<1>(0h0)) node _T_4522 = mux(_T_614, deq_vec[6][2].prs2, UInt<1>(0h0)) node _T_4523 = mux(_T_615, deq_vec[7][2].prs2, UInt<1>(0h0)) node _T_4524 = or(_T_4516, _T_4517) node _T_4525 = or(_T_4524, _T_4518) node _T_4526 = or(_T_4525, _T_4519) node _T_4527 = or(_T_4526, _T_4520) node _T_4528 = or(_T_4527, _T_4521) node _T_4529 = or(_T_4528, _T_4522) node _T_4530 = or(_T_4529, _T_4523) wire _WIRE_270 : UInt<7> connect _WIRE_270, _T_4530 connect _WIRE_231.prs2, _WIRE_270 node _T_4531 = mux(_T_608, deq_vec[0][2].prs1, UInt<1>(0h0)) node _T_4532 = mux(_T_609, deq_vec[1][2].prs1, UInt<1>(0h0)) node _T_4533 = mux(_T_610, deq_vec[2][2].prs1, UInt<1>(0h0)) node _T_4534 = mux(_T_611, deq_vec[3][2].prs1, UInt<1>(0h0)) node _T_4535 = mux(_T_612, deq_vec[4][2].prs1, UInt<1>(0h0)) node _T_4536 = mux(_T_613, deq_vec[5][2].prs1, UInt<1>(0h0)) node _T_4537 = mux(_T_614, deq_vec[6][2].prs1, UInt<1>(0h0)) node _T_4538 = mux(_T_615, deq_vec[7][2].prs1, UInt<1>(0h0)) node _T_4539 = or(_T_4531, _T_4532) node _T_4540 = or(_T_4539, _T_4533) node _T_4541 = or(_T_4540, _T_4534) node _T_4542 = or(_T_4541, _T_4535) node _T_4543 = or(_T_4542, _T_4536) node _T_4544 = or(_T_4543, _T_4537) node _T_4545 = or(_T_4544, _T_4538) wire _WIRE_271 : UInt<7> connect _WIRE_271, _T_4545 connect _WIRE_231.prs1, _WIRE_271 node _T_4546 = mux(_T_608, deq_vec[0][2].pdst, UInt<1>(0h0)) node _T_4547 = mux(_T_609, deq_vec[1][2].pdst, UInt<1>(0h0)) node _T_4548 = mux(_T_610, deq_vec[2][2].pdst, UInt<1>(0h0)) node _T_4549 = mux(_T_611, deq_vec[3][2].pdst, UInt<1>(0h0)) node _T_4550 = mux(_T_612, deq_vec[4][2].pdst, UInt<1>(0h0)) node _T_4551 = mux(_T_613, deq_vec[5][2].pdst, UInt<1>(0h0)) node _T_4552 = mux(_T_614, deq_vec[6][2].pdst, UInt<1>(0h0)) node _T_4553 = mux(_T_615, deq_vec[7][2].pdst, UInt<1>(0h0)) node _T_4554 = or(_T_4546, _T_4547) node _T_4555 = or(_T_4554, _T_4548) node _T_4556 = or(_T_4555, _T_4549) node _T_4557 = or(_T_4556, _T_4550) node _T_4558 = or(_T_4557, _T_4551) node _T_4559 = or(_T_4558, _T_4552) node _T_4560 = or(_T_4559, _T_4553) wire _WIRE_272 : UInt<7> connect _WIRE_272, _T_4560 connect _WIRE_231.pdst, _WIRE_272 node _T_4561 = mux(_T_608, deq_vec[0][2].rxq_idx, UInt<1>(0h0)) node _T_4562 = mux(_T_609, deq_vec[1][2].rxq_idx, UInt<1>(0h0)) node _T_4563 = mux(_T_610, deq_vec[2][2].rxq_idx, UInt<1>(0h0)) node _T_4564 = mux(_T_611, deq_vec[3][2].rxq_idx, UInt<1>(0h0)) node _T_4565 = mux(_T_612, deq_vec[4][2].rxq_idx, UInt<1>(0h0)) node _T_4566 = mux(_T_613, deq_vec[5][2].rxq_idx, UInt<1>(0h0)) node _T_4567 = mux(_T_614, deq_vec[6][2].rxq_idx, UInt<1>(0h0)) node _T_4568 = mux(_T_615, deq_vec[7][2].rxq_idx, UInt<1>(0h0)) node _T_4569 = or(_T_4561, _T_4562) node _T_4570 = or(_T_4569, _T_4563) node _T_4571 = or(_T_4570, _T_4564) node _T_4572 = or(_T_4571, _T_4565) node _T_4573 = or(_T_4572, _T_4566) node _T_4574 = or(_T_4573, _T_4567) node _T_4575 = or(_T_4574, _T_4568) wire _WIRE_273 : UInt<2> connect _WIRE_273, _T_4575 connect _WIRE_231.rxq_idx, _WIRE_273 node _T_4576 = mux(_T_608, deq_vec[0][2].stq_idx, UInt<1>(0h0)) node _T_4577 = mux(_T_609, deq_vec[1][2].stq_idx, UInt<1>(0h0)) node _T_4578 = mux(_T_610, deq_vec[2][2].stq_idx, UInt<1>(0h0)) node _T_4579 = mux(_T_611, deq_vec[3][2].stq_idx, UInt<1>(0h0)) node _T_4580 = mux(_T_612, deq_vec[4][2].stq_idx, UInt<1>(0h0)) node _T_4581 = mux(_T_613, deq_vec[5][2].stq_idx, UInt<1>(0h0)) node _T_4582 = mux(_T_614, deq_vec[6][2].stq_idx, UInt<1>(0h0)) node _T_4583 = mux(_T_615, deq_vec[7][2].stq_idx, UInt<1>(0h0)) node _T_4584 = or(_T_4576, _T_4577) node _T_4585 = or(_T_4584, _T_4578) node _T_4586 = or(_T_4585, _T_4579) node _T_4587 = or(_T_4586, _T_4580) node _T_4588 = or(_T_4587, _T_4581) node _T_4589 = or(_T_4588, _T_4582) node _T_4590 = or(_T_4589, _T_4583) wire _WIRE_274 : UInt<5> connect _WIRE_274, _T_4590 connect _WIRE_231.stq_idx, _WIRE_274 node _T_4591 = mux(_T_608, deq_vec[0][2].ldq_idx, UInt<1>(0h0)) node _T_4592 = mux(_T_609, deq_vec[1][2].ldq_idx, UInt<1>(0h0)) node _T_4593 = mux(_T_610, deq_vec[2][2].ldq_idx, UInt<1>(0h0)) node _T_4594 = mux(_T_611, deq_vec[3][2].ldq_idx, UInt<1>(0h0)) node _T_4595 = mux(_T_612, deq_vec[4][2].ldq_idx, UInt<1>(0h0)) node _T_4596 = mux(_T_613, deq_vec[5][2].ldq_idx, UInt<1>(0h0)) node _T_4597 = mux(_T_614, deq_vec[6][2].ldq_idx, UInt<1>(0h0)) node _T_4598 = mux(_T_615, deq_vec[7][2].ldq_idx, UInt<1>(0h0)) node _T_4599 = or(_T_4591, _T_4592) node _T_4600 = or(_T_4599, _T_4593) node _T_4601 = or(_T_4600, _T_4594) node _T_4602 = or(_T_4601, _T_4595) node _T_4603 = or(_T_4602, _T_4596) node _T_4604 = or(_T_4603, _T_4597) node _T_4605 = or(_T_4604, _T_4598) wire _WIRE_275 : UInt<5> connect _WIRE_275, _T_4605 connect _WIRE_231.ldq_idx, _WIRE_275 node _T_4606 = mux(_T_608, deq_vec[0][2].rob_idx, UInt<1>(0h0)) node _T_4607 = mux(_T_609, deq_vec[1][2].rob_idx, UInt<1>(0h0)) node _T_4608 = mux(_T_610, deq_vec[2][2].rob_idx, UInt<1>(0h0)) node _T_4609 = mux(_T_611, deq_vec[3][2].rob_idx, UInt<1>(0h0)) node _T_4610 = mux(_T_612, deq_vec[4][2].rob_idx, UInt<1>(0h0)) node _T_4611 = mux(_T_613, deq_vec[5][2].rob_idx, UInt<1>(0h0)) node _T_4612 = mux(_T_614, deq_vec[6][2].rob_idx, UInt<1>(0h0)) node _T_4613 = mux(_T_615, deq_vec[7][2].rob_idx, UInt<1>(0h0)) node _T_4614 = or(_T_4606, _T_4607) node _T_4615 = or(_T_4614, _T_4608) node _T_4616 = or(_T_4615, _T_4609) node _T_4617 = or(_T_4616, _T_4610) node _T_4618 = or(_T_4617, _T_4611) node _T_4619 = or(_T_4618, _T_4612) node _T_4620 = or(_T_4619, _T_4613) wire _WIRE_276 : UInt<7> connect _WIRE_276, _T_4620 connect _WIRE_231.rob_idx, _WIRE_276 wire _WIRE_277 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_4621 = mux(_T_608, deq_vec[0][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4622 = mux(_T_609, deq_vec[1][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4623 = mux(_T_610, deq_vec[2][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4624 = mux(_T_611, deq_vec[3][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4625 = mux(_T_612, deq_vec[4][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4626 = mux(_T_613, deq_vec[5][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4627 = mux(_T_614, deq_vec[6][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4628 = mux(_T_615, deq_vec[7][2].fp_ctrl.vec, UInt<1>(0h0)) node _T_4629 = or(_T_4621, _T_4622) node _T_4630 = or(_T_4629, _T_4623) node _T_4631 = or(_T_4630, _T_4624) node _T_4632 = or(_T_4631, _T_4625) node _T_4633 = or(_T_4632, _T_4626) node _T_4634 = or(_T_4633, _T_4627) node _T_4635 = or(_T_4634, _T_4628) wire _WIRE_278 : UInt<1> connect _WIRE_278, _T_4635 connect _WIRE_277.vec, _WIRE_278 node _T_4636 = mux(_T_608, deq_vec[0][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4637 = mux(_T_609, deq_vec[1][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4638 = mux(_T_610, deq_vec[2][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4639 = mux(_T_611, deq_vec[3][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4640 = mux(_T_612, deq_vec[4][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4641 = mux(_T_613, deq_vec[5][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4642 = mux(_T_614, deq_vec[6][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4643 = mux(_T_615, deq_vec[7][2].fp_ctrl.wflags, UInt<1>(0h0)) node _T_4644 = or(_T_4636, _T_4637) node _T_4645 = or(_T_4644, _T_4638) node _T_4646 = or(_T_4645, _T_4639) node _T_4647 = or(_T_4646, _T_4640) node _T_4648 = or(_T_4647, _T_4641) node _T_4649 = or(_T_4648, _T_4642) node _T_4650 = or(_T_4649, _T_4643) wire _WIRE_279 : UInt<1> connect _WIRE_279, _T_4650 connect _WIRE_277.wflags, _WIRE_279 node _T_4651 = mux(_T_608, deq_vec[0][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4652 = mux(_T_609, deq_vec[1][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4653 = mux(_T_610, deq_vec[2][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4654 = mux(_T_611, deq_vec[3][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4655 = mux(_T_612, deq_vec[4][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4656 = mux(_T_613, deq_vec[5][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4657 = mux(_T_614, deq_vec[6][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4658 = mux(_T_615, deq_vec[7][2].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_4659 = or(_T_4651, _T_4652) node _T_4660 = or(_T_4659, _T_4653) node _T_4661 = or(_T_4660, _T_4654) node _T_4662 = or(_T_4661, _T_4655) node _T_4663 = or(_T_4662, _T_4656) node _T_4664 = or(_T_4663, _T_4657) node _T_4665 = or(_T_4664, _T_4658) wire _WIRE_280 : UInt<1> connect _WIRE_280, _T_4665 connect _WIRE_277.sqrt, _WIRE_280 node _T_4666 = mux(_T_608, deq_vec[0][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4667 = mux(_T_609, deq_vec[1][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4668 = mux(_T_610, deq_vec[2][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4669 = mux(_T_611, deq_vec[3][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4670 = mux(_T_612, deq_vec[4][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4671 = mux(_T_613, deq_vec[5][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4672 = mux(_T_614, deq_vec[6][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4673 = mux(_T_615, deq_vec[7][2].fp_ctrl.div, UInt<1>(0h0)) node _T_4674 = or(_T_4666, _T_4667) node _T_4675 = or(_T_4674, _T_4668) node _T_4676 = or(_T_4675, _T_4669) node _T_4677 = or(_T_4676, _T_4670) node _T_4678 = or(_T_4677, _T_4671) node _T_4679 = or(_T_4678, _T_4672) node _T_4680 = or(_T_4679, _T_4673) wire _WIRE_281 : UInt<1> connect _WIRE_281, _T_4680 connect _WIRE_277.div, _WIRE_281 node _T_4681 = mux(_T_608, deq_vec[0][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4682 = mux(_T_609, deq_vec[1][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4683 = mux(_T_610, deq_vec[2][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4684 = mux(_T_611, deq_vec[3][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4685 = mux(_T_612, deq_vec[4][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4686 = mux(_T_613, deq_vec[5][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4687 = mux(_T_614, deq_vec[6][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4688 = mux(_T_615, deq_vec[7][2].fp_ctrl.fma, UInt<1>(0h0)) node _T_4689 = or(_T_4681, _T_4682) node _T_4690 = or(_T_4689, _T_4683) node _T_4691 = or(_T_4690, _T_4684) node _T_4692 = or(_T_4691, _T_4685) node _T_4693 = or(_T_4692, _T_4686) node _T_4694 = or(_T_4693, _T_4687) node _T_4695 = or(_T_4694, _T_4688) wire _WIRE_282 : UInt<1> connect _WIRE_282, _T_4695 connect _WIRE_277.fma, _WIRE_282 node _T_4696 = mux(_T_608, deq_vec[0][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4697 = mux(_T_609, deq_vec[1][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4698 = mux(_T_610, deq_vec[2][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4699 = mux(_T_611, deq_vec[3][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4700 = mux(_T_612, deq_vec[4][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4701 = mux(_T_613, deq_vec[5][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4702 = mux(_T_614, deq_vec[6][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4703 = mux(_T_615, deq_vec[7][2].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_4704 = or(_T_4696, _T_4697) node _T_4705 = or(_T_4704, _T_4698) node _T_4706 = or(_T_4705, _T_4699) node _T_4707 = or(_T_4706, _T_4700) node _T_4708 = or(_T_4707, _T_4701) node _T_4709 = or(_T_4708, _T_4702) node _T_4710 = or(_T_4709, _T_4703) wire _WIRE_283 : UInt<1> connect _WIRE_283, _T_4710 connect _WIRE_277.fastpipe, _WIRE_283 node _T_4711 = mux(_T_608, deq_vec[0][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4712 = mux(_T_609, deq_vec[1][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4713 = mux(_T_610, deq_vec[2][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4714 = mux(_T_611, deq_vec[3][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4715 = mux(_T_612, deq_vec[4][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4716 = mux(_T_613, deq_vec[5][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4717 = mux(_T_614, deq_vec[6][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4718 = mux(_T_615, deq_vec[7][2].fp_ctrl.toint, UInt<1>(0h0)) node _T_4719 = or(_T_4711, _T_4712) node _T_4720 = or(_T_4719, _T_4713) node _T_4721 = or(_T_4720, _T_4714) node _T_4722 = or(_T_4721, _T_4715) node _T_4723 = or(_T_4722, _T_4716) node _T_4724 = or(_T_4723, _T_4717) node _T_4725 = or(_T_4724, _T_4718) wire _WIRE_284 : UInt<1> connect _WIRE_284, _T_4725 connect _WIRE_277.toint, _WIRE_284 node _T_4726 = mux(_T_608, deq_vec[0][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4727 = mux(_T_609, deq_vec[1][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4728 = mux(_T_610, deq_vec[2][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4729 = mux(_T_611, deq_vec[3][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4730 = mux(_T_612, deq_vec[4][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4731 = mux(_T_613, deq_vec[5][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4732 = mux(_T_614, deq_vec[6][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4733 = mux(_T_615, deq_vec[7][2].fp_ctrl.fromint, UInt<1>(0h0)) node _T_4734 = or(_T_4726, _T_4727) node _T_4735 = or(_T_4734, _T_4728) node _T_4736 = or(_T_4735, _T_4729) node _T_4737 = or(_T_4736, _T_4730) node _T_4738 = or(_T_4737, _T_4731) node _T_4739 = or(_T_4738, _T_4732) node _T_4740 = or(_T_4739, _T_4733) wire _WIRE_285 : UInt<1> connect _WIRE_285, _T_4740 connect _WIRE_277.fromint, _WIRE_285 node _T_4741 = mux(_T_608, deq_vec[0][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4742 = mux(_T_609, deq_vec[1][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4743 = mux(_T_610, deq_vec[2][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4744 = mux(_T_611, deq_vec[3][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4745 = mux(_T_612, deq_vec[4][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4746 = mux(_T_613, deq_vec[5][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4747 = mux(_T_614, deq_vec[6][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4748 = mux(_T_615, deq_vec[7][2].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_4749 = or(_T_4741, _T_4742) node _T_4750 = or(_T_4749, _T_4743) node _T_4751 = or(_T_4750, _T_4744) node _T_4752 = or(_T_4751, _T_4745) node _T_4753 = or(_T_4752, _T_4746) node _T_4754 = or(_T_4753, _T_4747) node _T_4755 = or(_T_4754, _T_4748) wire _WIRE_286 : UInt<2> connect _WIRE_286, _T_4755 connect _WIRE_277.typeTagOut, _WIRE_286 node _T_4756 = mux(_T_608, deq_vec[0][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4757 = mux(_T_609, deq_vec[1][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4758 = mux(_T_610, deq_vec[2][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4759 = mux(_T_611, deq_vec[3][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4760 = mux(_T_612, deq_vec[4][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4761 = mux(_T_613, deq_vec[5][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4762 = mux(_T_614, deq_vec[6][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4763 = mux(_T_615, deq_vec[7][2].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_4764 = or(_T_4756, _T_4757) node _T_4765 = or(_T_4764, _T_4758) node _T_4766 = or(_T_4765, _T_4759) node _T_4767 = or(_T_4766, _T_4760) node _T_4768 = or(_T_4767, _T_4761) node _T_4769 = or(_T_4768, _T_4762) node _T_4770 = or(_T_4769, _T_4763) wire _WIRE_287 : UInt<2> connect _WIRE_287, _T_4770 connect _WIRE_277.typeTagIn, _WIRE_287 node _T_4771 = mux(_T_608, deq_vec[0][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4772 = mux(_T_609, deq_vec[1][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4773 = mux(_T_610, deq_vec[2][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4774 = mux(_T_611, deq_vec[3][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4775 = mux(_T_612, deq_vec[4][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4776 = mux(_T_613, deq_vec[5][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4777 = mux(_T_614, deq_vec[6][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4778 = mux(_T_615, deq_vec[7][2].fp_ctrl.swap23, UInt<1>(0h0)) node _T_4779 = or(_T_4771, _T_4772) node _T_4780 = or(_T_4779, _T_4773) node _T_4781 = or(_T_4780, _T_4774) node _T_4782 = or(_T_4781, _T_4775) node _T_4783 = or(_T_4782, _T_4776) node _T_4784 = or(_T_4783, _T_4777) node _T_4785 = or(_T_4784, _T_4778) wire _WIRE_288 : UInt<1> connect _WIRE_288, _T_4785 connect _WIRE_277.swap23, _WIRE_288 node _T_4786 = mux(_T_608, deq_vec[0][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4787 = mux(_T_609, deq_vec[1][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4788 = mux(_T_610, deq_vec[2][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4789 = mux(_T_611, deq_vec[3][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4790 = mux(_T_612, deq_vec[4][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4791 = mux(_T_613, deq_vec[5][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4792 = mux(_T_614, deq_vec[6][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4793 = mux(_T_615, deq_vec[7][2].fp_ctrl.swap12, UInt<1>(0h0)) node _T_4794 = or(_T_4786, _T_4787) node _T_4795 = or(_T_4794, _T_4788) node _T_4796 = or(_T_4795, _T_4789) node _T_4797 = or(_T_4796, _T_4790) node _T_4798 = or(_T_4797, _T_4791) node _T_4799 = or(_T_4798, _T_4792) node _T_4800 = or(_T_4799, _T_4793) wire _WIRE_289 : UInt<1> connect _WIRE_289, _T_4800 connect _WIRE_277.swap12, _WIRE_289 node _T_4801 = mux(_T_608, deq_vec[0][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4802 = mux(_T_609, deq_vec[1][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4803 = mux(_T_610, deq_vec[2][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4804 = mux(_T_611, deq_vec[3][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4805 = mux(_T_612, deq_vec[4][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4806 = mux(_T_613, deq_vec[5][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4807 = mux(_T_614, deq_vec[6][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4808 = mux(_T_615, deq_vec[7][2].fp_ctrl.ren3, UInt<1>(0h0)) node _T_4809 = or(_T_4801, _T_4802) node _T_4810 = or(_T_4809, _T_4803) node _T_4811 = or(_T_4810, _T_4804) node _T_4812 = or(_T_4811, _T_4805) node _T_4813 = or(_T_4812, _T_4806) node _T_4814 = or(_T_4813, _T_4807) node _T_4815 = or(_T_4814, _T_4808) wire _WIRE_290 : UInt<1> connect _WIRE_290, _T_4815 connect _WIRE_277.ren3, _WIRE_290 node _T_4816 = mux(_T_608, deq_vec[0][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4817 = mux(_T_609, deq_vec[1][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4818 = mux(_T_610, deq_vec[2][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4819 = mux(_T_611, deq_vec[3][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4820 = mux(_T_612, deq_vec[4][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4821 = mux(_T_613, deq_vec[5][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4822 = mux(_T_614, deq_vec[6][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4823 = mux(_T_615, deq_vec[7][2].fp_ctrl.ren2, UInt<1>(0h0)) node _T_4824 = or(_T_4816, _T_4817) node _T_4825 = or(_T_4824, _T_4818) node _T_4826 = or(_T_4825, _T_4819) node _T_4827 = or(_T_4826, _T_4820) node _T_4828 = or(_T_4827, _T_4821) node _T_4829 = or(_T_4828, _T_4822) node _T_4830 = or(_T_4829, _T_4823) wire _WIRE_291 : UInt<1> connect _WIRE_291, _T_4830 connect _WIRE_277.ren2, _WIRE_291 node _T_4831 = mux(_T_608, deq_vec[0][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4832 = mux(_T_609, deq_vec[1][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4833 = mux(_T_610, deq_vec[2][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4834 = mux(_T_611, deq_vec[3][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4835 = mux(_T_612, deq_vec[4][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4836 = mux(_T_613, deq_vec[5][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4837 = mux(_T_614, deq_vec[6][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4838 = mux(_T_615, deq_vec[7][2].fp_ctrl.ren1, UInt<1>(0h0)) node _T_4839 = or(_T_4831, _T_4832) node _T_4840 = or(_T_4839, _T_4833) node _T_4841 = or(_T_4840, _T_4834) node _T_4842 = or(_T_4841, _T_4835) node _T_4843 = or(_T_4842, _T_4836) node _T_4844 = or(_T_4843, _T_4837) node _T_4845 = or(_T_4844, _T_4838) wire _WIRE_292 : UInt<1> connect _WIRE_292, _T_4845 connect _WIRE_277.ren1, _WIRE_292 node _T_4846 = mux(_T_608, deq_vec[0][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4847 = mux(_T_609, deq_vec[1][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4848 = mux(_T_610, deq_vec[2][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4849 = mux(_T_611, deq_vec[3][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4850 = mux(_T_612, deq_vec[4][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4851 = mux(_T_613, deq_vec[5][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4852 = mux(_T_614, deq_vec[6][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4853 = mux(_T_615, deq_vec[7][2].fp_ctrl.wen, UInt<1>(0h0)) node _T_4854 = or(_T_4846, _T_4847) node _T_4855 = or(_T_4854, _T_4848) node _T_4856 = or(_T_4855, _T_4849) node _T_4857 = or(_T_4856, _T_4850) node _T_4858 = or(_T_4857, _T_4851) node _T_4859 = or(_T_4858, _T_4852) node _T_4860 = or(_T_4859, _T_4853) wire _WIRE_293 : UInt<1> connect _WIRE_293, _T_4860 connect _WIRE_277.wen, _WIRE_293 node _T_4861 = mux(_T_608, deq_vec[0][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4862 = mux(_T_609, deq_vec[1][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4863 = mux(_T_610, deq_vec[2][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4864 = mux(_T_611, deq_vec[3][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4865 = mux(_T_612, deq_vec[4][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4866 = mux(_T_613, deq_vec[5][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4867 = mux(_T_614, deq_vec[6][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4868 = mux(_T_615, deq_vec[7][2].fp_ctrl.ldst, UInt<1>(0h0)) node _T_4869 = or(_T_4861, _T_4862) node _T_4870 = or(_T_4869, _T_4863) node _T_4871 = or(_T_4870, _T_4864) node _T_4872 = or(_T_4871, _T_4865) node _T_4873 = or(_T_4872, _T_4866) node _T_4874 = or(_T_4873, _T_4867) node _T_4875 = or(_T_4874, _T_4868) wire _WIRE_294 : UInt<1> connect _WIRE_294, _T_4875 connect _WIRE_277.ldst, _WIRE_294 connect _WIRE_231.fp_ctrl, _WIRE_277 node _T_4876 = mux(_T_608, deq_vec[0][2].op2_sel, UInt<1>(0h0)) node _T_4877 = mux(_T_609, deq_vec[1][2].op2_sel, UInt<1>(0h0)) node _T_4878 = mux(_T_610, deq_vec[2][2].op2_sel, UInt<1>(0h0)) node _T_4879 = mux(_T_611, deq_vec[3][2].op2_sel, UInt<1>(0h0)) node _T_4880 = mux(_T_612, deq_vec[4][2].op2_sel, UInt<1>(0h0)) node _T_4881 = mux(_T_613, deq_vec[5][2].op2_sel, UInt<1>(0h0)) node _T_4882 = mux(_T_614, deq_vec[6][2].op2_sel, UInt<1>(0h0)) node _T_4883 = mux(_T_615, deq_vec[7][2].op2_sel, UInt<1>(0h0)) node _T_4884 = or(_T_4876, _T_4877) node _T_4885 = or(_T_4884, _T_4878) node _T_4886 = or(_T_4885, _T_4879) node _T_4887 = or(_T_4886, _T_4880) node _T_4888 = or(_T_4887, _T_4881) node _T_4889 = or(_T_4888, _T_4882) node _T_4890 = or(_T_4889, _T_4883) wire _WIRE_295 : UInt<3> connect _WIRE_295, _T_4890 connect _WIRE_231.op2_sel, _WIRE_295 node _T_4891 = mux(_T_608, deq_vec[0][2].op1_sel, UInt<1>(0h0)) node _T_4892 = mux(_T_609, deq_vec[1][2].op1_sel, UInt<1>(0h0)) node _T_4893 = mux(_T_610, deq_vec[2][2].op1_sel, UInt<1>(0h0)) node _T_4894 = mux(_T_611, deq_vec[3][2].op1_sel, UInt<1>(0h0)) node _T_4895 = mux(_T_612, deq_vec[4][2].op1_sel, UInt<1>(0h0)) node _T_4896 = mux(_T_613, deq_vec[5][2].op1_sel, UInt<1>(0h0)) node _T_4897 = mux(_T_614, deq_vec[6][2].op1_sel, UInt<1>(0h0)) node _T_4898 = mux(_T_615, deq_vec[7][2].op1_sel, UInt<1>(0h0)) node _T_4899 = or(_T_4891, _T_4892) node _T_4900 = or(_T_4899, _T_4893) node _T_4901 = or(_T_4900, _T_4894) node _T_4902 = or(_T_4901, _T_4895) node _T_4903 = or(_T_4902, _T_4896) node _T_4904 = or(_T_4903, _T_4897) node _T_4905 = or(_T_4904, _T_4898) wire _WIRE_296 : UInt<2> connect _WIRE_296, _T_4905 connect _WIRE_231.op1_sel, _WIRE_296 node _T_4906 = mux(_T_608, deq_vec[0][2].imm_packed, UInt<1>(0h0)) node _T_4907 = mux(_T_609, deq_vec[1][2].imm_packed, UInt<1>(0h0)) node _T_4908 = mux(_T_610, deq_vec[2][2].imm_packed, UInt<1>(0h0)) node _T_4909 = mux(_T_611, deq_vec[3][2].imm_packed, UInt<1>(0h0)) node _T_4910 = mux(_T_612, deq_vec[4][2].imm_packed, UInt<1>(0h0)) node _T_4911 = mux(_T_613, deq_vec[5][2].imm_packed, UInt<1>(0h0)) node _T_4912 = mux(_T_614, deq_vec[6][2].imm_packed, UInt<1>(0h0)) node _T_4913 = mux(_T_615, deq_vec[7][2].imm_packed, UInt<1>(0h0)) node _T_4914 = or(_T_4906, _T_4907) node _T_4915 = or(_T_4914, _T_4908) node _T_4916 = or(_T_4915, _T_4909) node _T_4917 = or(_T_4916, _T_4910) node _T_4918 = or(_T_4917, _T_4911) node _T_4919 = or(_T_4918, _T_4912) node _T_4920 = or(_T_4919, _T_4913) wire _WIRE_297 : UInt<20> connect _WIRE_297, _T_4920 connect _WIRE_231.imm_packed, _WIRE_297 node _T_4921 = mux(_T_608, deq_vec[0][2].pimm, UInt<1>(0h0)) node _T_4922 = mux(_T_609, deq_vec[1][2].pimm, UInt<1>(0h0)) node _T_4923 = mux(_T_610, deq_vec[2][2].pimm, UInt<1>(0h0)) node _T_4924 = mux(_T_611, deq_vec[3][2].pimm, UInt<1>(0h0)) node _T_4925 = mux(_T_612, deq_vec[4][2].pimm, UInt<1>(0h0)) node _T_4926 = mux(_T_613, deq_vec[5][2].pimm, UInt<1>(0h0)) node _T_4927 = mux(_T_614, deq_vec[6][2].pimm, UInt<1>(0h0)) node _T_4928 = mux(_T_615, deq_vec[7][2].pimm, UInt<1>(0h0)) node _T_4929 = or(_T_4921, _T_4922) node _T_4930 = or(_T_4929, _T_4923) node _T_4931 = or(_T_4930, _T_4924) node _T_4932 = or(_T_4931, _T_4925) node _T_4933 = or(_T_4932, _T_4926) node _T_4934 = or(_T_4933, _T_4927) node _T_4935 = or(_T_4934, _T_4928) wire _WIRE_298 : UInt<5> connect _WIRE_298, _T_4935 connect _WIRE_231.pimm, _WIRE_298 node _T_4936 = mux(_T_608, deq_vec[0][2].imm_sel, UInt<1>(0h0)) node _T_4937 = mux(_T_609, deq_vec[1][2].imm_sel, UInt<1>(0h0)) node _T_4938 = mux(_T_610, deq_vec[2][2].imm_sel, UInt<1>(0h0)) node _T_4939 = mux(_T_611, deq_vec[3][2].imm_sel, UInt<1>(0h0)) node _T_4940 = mux(_T_612, deq_vec[4][2].imm_sel, UInt<1>(0h0)) node _T_4941 = mux(_T_613, deq_vec[5][2].imm_sel, UInt<1>(0h0)) node _T_4942 = mux(_T_614, deq_vec[6][2].imm_sel, UInt<1>(0h0)) node _T_4943 = mux(_T_615, deq_vec[7][2].imm_sel, UInt<1>(0h0)) node _T_4944 = or(_T_4936, _T_4937) node _T_4945 = or(_T_4944, _T_4938) node _T_4946 = or(_T_4945, _T_4939) node _T_4947 = or(_T_4946, _T_4940) node _T_4948 = or(_T_4947, _T_4941) node _T_4949 = or(_T_4948, _T_4942) node _T_4950 = or(_T_4949, _T_4943) wire _WIRE_299 : UInt<3> connect _WIRE_299, _T_4950 connect _WIRE_231.imm_sel, _WIRE_299 node _T_4951 = mux(_T_608, deq_vec[0][2].imm_rename, UInt<1>(0h0)) node _T_4952 = mux(_T_609, deq_vec[1][2].imm_rename, UInt<1>(0h0)) node _T_4953 = mux(_T_610, deq_vec[2][2].imm_rename, UInt<1>(0h0)) node _T_4954 = mux(_T_611, deq_vec[3][2].imm_rename, UInt<1>(0h0)) node _T_4955 = mux(_T_612, deq_vec[4][2].imm_rename, UInt<1>(0h0)) node _T_4956 = mux(_T_613, deq_vec[5][2].imm_rename, UInt<1>(0h0)) node _T_4957 = mux(_T_614, deq_vec[6][2].imm_rename, UInt<1>(0h0)) node _T_4958 = mux(_T_615, deq_vec[7][2].imm_rename, UInt<1>(0h0)) node _T_4959 = or(_T_4951, _T_4952) node _T_4960 = or(_T_4959, _T_4953) node _T_4961 = or(_T_4960, _T_4954) node _T_4962 = or(_T_4961, _T_4955) node _T_4963 = or(_T_4962, _T_4956) node _T_4964 = or(_T_4963, _T_4957) node _T_4965 = or(_T_4964, _T_4958) wire _WIRE_300 : UInt<1> connect _WIRE_300, _T_4965 connect _WIRE_231.imm_rename, _WIRE_300 node _T_4966 = mux(_T_608, deq_vec[0][2].taken, UInt<1>(0h0)) node _T_4967 = mux(_T_609, deq_vec[1][2].taken, UInt<1>(0h0)) node _T_4968 = mux(_T_610, deq_vec[2][2].taken, UInt<1>(0h0)) node _T_4969 = mux(_T_611, deq_vec[3][2].taken, UInt<1>(0h0)) node _T_4970 = mux(_T_612, deq_vec[4][2].taken, UInt<1>(0h0)) node _T_4971 = mux(_T_613, deq_vec[5][2].taken, UInt<1>(0h0)) node _T_4972 = mux(_T_614, deq_vec[6][2].taken, UInt<1>(0h0)) node _T_4973 = mux(_T_615, deq_vec[7][2].taken, UInt<1>(0h0)) node _T_4974 = or(_T_4966, _T_4967) node _T_4975 = or(_T_4974, _T_4968) node _T_4976 = or(_T_4975, _T_4969) node _T_4977 = or(_T_4976, _T_4970) node _T_4978 = or(_T_4977, _T_4971) node _T_4979 = or(_T_4978, _T_4972) node _T_4980 = or(_T_4979, _T_4973) wire _WIRE_301 : UInt<1> connect _WIRE_301, _T_4980 connect _WIRE_231.taken, _WIRE_301 node _T_4981 = mux(_T_608, deq_vec[0][2].pc_lob, UInt<1>(0h0)) node _T_4982 = mux(_T_609, deq_vec[1][2].pc_lob, UInt<1>(0h0)) node _T_4983 = mux(_T_610, deq_vec[2][2].pc_lob, UInt<1>(0h0)) node _T_4984 = mux(_T_611, deq_vec[3][2].pc_lob, UInt<1>(0h0)) node _T_4985 = mux(_T_612, deq_vec[4][2].pc_lob, UInt<1>(0h0)) node _T_4986 = mux(_T_613, deq_vec[5][2].pc_lob, UInt<1>(0h0)) node _T_4987 = mux(_T_614, deq_vec[6][2].pc_lob, UInt<1>(0h0)) node _T_4988 = mux(_T_615, deq_vec[7][2].pc_lob, UInt<1>(0h0)) node _T_4989 = or(_T_4981, _T_4982) node _T_4990 = or(_T_4989, _T_4983) node _T_4991 = or(_T_4990, _T_4984) node _T_4992 = or(_T_4991, _T_4985) node _T_4993 = or(_T_4992, _T_4986) node _T_4994 = or(_T_4993, _T_4987) node _T_4995 = or(_T_4994, _T_4988) wire _WIRE_302 : UInt<6> connect _WIRE_302, _T_4995 connect _WIRE_231.pc_lob, _WIRE_302 node _T_4996 = mux(_T_608, deq_vec[0][2].edge_inst, UInt<1>(0h0)) node _T_4997 = mux(_T_609, deq_vec[1][2].edge_inst, UInt<1>(0h0)) node _T_4998 = mux(_T_610, deq_vec[2][2].edge_inst, UInt<1>(0h0)) node _T_4999 = mux(_T_611, deq_vec[3][2].edge_inst, UInt<1>(0h0)) node _T_5000 = mux(_T_612, deq_vec[4][2].edge_inst, UInt<1>(0h0)) node _T_5001 = mux(_T_613, deq_vec[5][2].edge_inst, UInt<1>(0h0)) node _T_5002 = mux(_T_614, deq_vec[6][2].edge_inst, UInt<1>(0h0)) node _T_5003 = mux(_T_615, deq_vec[7][2].edge_inst, UInt<1>(0h0)) node _T_5004 = or(_T_4996, _T_4997) node _T_5005 = or(_T_5004, _T_4998) node _T_5006 = or(_T_5005, _T_4999) node _T_5007 = or(_T_5006, _T_5000) node _T_5008 = or(_T_5007, _T_5001) node _T_5009 = or(_T_5008, _T_5002) node _T_5010 = or(_T_5009, _T_5003) wire _WIRE_303 : UInt<1> connect _WIRE_303, _T_5010 connect _WIRE_231.edge_inst, _WIRE_303 node _T_5011 = mux(_T_608, deq_vec[0][2].ftq_idx, UInt<1>(0h0)) node _T_5012 = mux(_T_609, deq_vec[1][2].ftq_idx, UInt<1>(0h0)) node _T_5013 = mux(_T_610, deq_vec[2][2].ftq_idx, UInt<1>(0h0)) node _T_5014 = mux(_T_611, deq_vec[3][2].ftq_idx, UInt<1>(0h0)) node _T_5015 = mux(_T_612, deq_vec[4][2].ftq_idx, UInt<1>(0h0)) node _T_5016 = mux(_T_613, deq_vec[5][2].ftq_idx, UInt<1>(0h0)) node _T_5017 = mux(_T_614, deq_vec[6][2].ftq_idx, UInt<1>(0h0)) node _T_5018 = mux(_T_615, deq_vec[7][2].ftq_idx, UInt<1>(0h0)) node _T_5019 = or(_T_5011, _T_5012) node _T_5020 = or(_T_5019, _T_5013) node _T_5021 = or(_T_5020, _T_5014) node _T_5022 = or(_T_5021, _T_5015) node _T_5023 = or(_T_5022, _T_5016) node _T_5024 = or(_T_5023, _T_5017) node _T_5025 = or(_T_5024, _T_5018) wire _WIRE_304 : UInt<5> connect _WIRE_304, _T_5025 connect _WIRE_231.ftq_idx, _WIRE_304 node _T_5026 = mux(_T_608, deq_vec[0][2].is_mov, UInt<1>(0h0)) node _T_5027 = mux(_T_609, deq_vec[1][2].is_mov, UInt<1>(0h0)) node _T_5028 = mux(_T_610, deq_vec[2][2].is_mov, UInt<1>(0h0)) node _T_5029 = mux(_T_611, deq_vec[3][2].is_mov, UInt<1>(0h0)) node _T_5030 = mux(_T_612, deq_vec[4][2].is_mov, UInt<1>(0h0)) node _T_5031 = mux(_T_613, deq_vec[5][2].is_mov, UInt<1>(0h0)) node _T_5032 = mux(_T_614, deq_vec[6][2].is_mov, UInt<1>(0h0)) node _T_5033 = mux(_T_615, deq_vec[7][2].is_mov, UInt<1>(0h0)) node _T_5034 = or(_T_5026, _T_5027) node _T_5035 = or(_T_5034, _T_5028) node _T_5036 = or(_T_5035, _T_5029) node _T_5037 = or(_T_5036, _T_5030) node _T_5038 = or(_T_5037, _T_5031) node _T_5039 = or(_T_5038, _T_5032) node _T_5040 = or(_T_5039, _T_5033) wire _WIRE_305 : UInt<1> connect _WIRE_305, _T_5040 connect _WIRE_231.is_mov, _WIRE_305 node _T_5041 = mux(_T_608, deq_vec[0][2].is_rocc, UInt<1>(0h0)) node _T_5042 = mux(_T_609, deq_vec[1][2].is_rocc, UInt<1>(0h0)) node _T_5043 = mux(_T_610, deq_vec[2][2].is_rocc, UInt<1>(0h0)) node _T_5044 = mux(_T_611, deq_vec[3][2].is_rocc, UInt<1>(0h0)) node _T_5045 = mux(_T_612, deq_vec[4][2].is_rocc, UInt<1>(0h0)) node _T_5046 = mux(_T_613, deq_vec[5][2].is_rocc, UInt<1>(0h0)) node _T_5047 = mux(_T_614, deq_vec[6][2].is_rocc, UInt<1>(0h0)) node _T_5048 = mux(_T_615, deq_vec[7][2].is_rocc, UInt<1>(0h0)) node _T_5049 = or(_T_5041, _T_5042) node _T_5050 = or(_T_5049, _T_5043) node _T_5051 = or(_T_5050, _T_5044) node _T_5052 = or(_T_5051, _T_5045) node _T_5053 = or(_T_5052, _T_5046) node _T_5054 = or(_T_5053, _T_5047) node _T_5055 = or(_T_5054, _T_5048) wire _WIRE_306 : UInt<1> connect _WIRE_306, _T_5055 connect _WIRE_231.is_rocc, _WIRE_306 node _T_5056 = mux(_T_608, deq_vec[0][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5057 = mux(_T_609, deq_vec[1][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5058 = mux(_T_610, deq_vec[2][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5059 = mux(_T_611, deq_vec[3][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5060 = mux(_T_612, deq_vec[4][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5061 = mux(_T_613, deq_vec[5][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5062 = mux(_T_614, deq_vec[6][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5063 = mux(_T_615, deq_vec[7][2].is_sys_pc2epc, UInt<1>(0h0)) node _T_5064 = or(_T_5056, _T_5057) node _T_5065 = or(_T_5064, _T_5058) node _T_5066 = or(_T_5065, _T_5059) node _T_5067 = or(_T_5066, _T_5060) node _T_5068 = or(_T_5067, _T_5061) node _T_5069 = or(_T_5068, _T_5062) node _T_5070 = or(_T_5069, _T_5063) wire _WIRE_307 : UInt<1> connect _WIRE_307, _T_5070 connect _WIRE_231.is_sys_pc2epc, _WIRE_307 node _T_5071 = mux(_T_608, deq_vec[0][2].is_eret, UInt<1>(0h0)) node _T_5072 = mux(_T_609, deq_vec[1][2].is_eret, UInt<1>(0h0)) node _T_5073 = mux(_T_610, deq_vec[2][2].is_eret, UInt<1>(0h0)) node _T_5074 = mux(_T_611, deq_vec[3][2].is_eret, UInt<1>(0h0)) node _T_5075 = mux(_T_612, deq_vec[4][2].is_eret, UInt<1>(0h0)) node _T_5076 = mux(_T_613, deq_vec[5][2].is_eret, UInt<1>(0h0)) node _T_5077 = mux(_T_614, deq_vec[6][2].is_eret, UInt<1>(0h0)) node _T_5078 = mux(_T_615, deq_vec[7][2].is_eret, UInt<1>(0h0)) node _T_5079 = or(_T_5071, _T_5072) node _T_5080 = or(_T_5079, _T_5073) node _T_5081 = or(_T_5080, _T_5074) node _T_5082 = or(_T_5081, _T_5075) node _T_5083 = or(_T_5082, _T_5076) node _T_5084 = or(_T_5083, _T_5077) node _T_5085 = or(_T_5084, _T_5078) wire _WIRE_308 : UInt<1> connect _WIRE_308, _T_5085 connect _WIRE_231.is_eret, _WIRE_308 node _T_5086 = mux(_T_608, deq_vec[0][2].is_amo, UInt<1>(0h0)) node _T_5087 = mux(_T_609, deq_vec[1][2].is_amo, UInt<1>(0h0)) node _T_5088 = mux(_T_610, deq_vec[2][2].is_amo, UInt<1>(0h0)) node _T_5089 = mux(_T_611, deq_vec[3][2].is_amo, UInt<1>(0h0)) node _T_5090 = mux(_T_612, deq_vec[4][2].is_amo, UInt<1>(0h0)) node _T_5091 = mux(_T_613, deq_vec[5][2].is_amo, UInt<1>(0h0)) node _T_5092 = mux(_T_614, deq_vec[6][2].is_amo, UInt<1>(0h0)) node _T_5093 = mux(_T_615, deq_vec[7][2].is_amo, UInt<1>(0h0)) node _T_5094 = or(_T_5086, _T_5087) node _T_5095 = or(_T_5094, _T_5088) node _T_5096 = or(_T_5095, _T_5089) node _T_5097 = or(_T_5096, _T_5090) node _T_5098 = or(_T_5097, _T_5091) node _T_5099 = or(_T_5098, _T_5092) node _T_5100 = or(_T_5099, _T_5093) wire _WIRE_309 : UInt<1> connect _WIRE_309, _T_5100 connect _WIRE_231.is_amo, _WIRE_309 node _T_5101 = mux(_T_608, deq_vec[0][2].is_sfence, UInt<1>(0h0)) node _T_5102 = mux(_T_609, deq_vec[1][2].is_sfence, UInt<1>(0h0)) node _T_5103 = mux(_T_610, deq_vec[2][2].is_sfence, UInt<1>(0h0)) node _T_5104 = mux(_T_611, deq_vec[3][2].is_sfence, UInt<1>(0h0)) node _T_5105 = mux(_T_612, deq_vec[4][2].is_sfence, UInt<1>(0h0)) node _T_5106 = mux(_T_613, deq_vec[5][2].is_sfence, UInt<1>(0h0)) node _T_5107 = mux(_T_614, deq_vec[6][2].is_sfence, UInt<1>(0h0)) node _T_5108 = mux(_T_615, deq_vec[7][2].is_sfence, UInt<1>(0h0)) node _T_5109 = or(_T_5101, _T_5102) node _T_5110 = or(_T_5109, _T_5103) node _T_5111 = or(_T_5110, _T_5104) node _T_5112 = or(_T_5111, _T_5105) node _T_5113 = or(_T_5112, _T_5106) node _T_5114 = or(_T_5113, _T_5107) node _T_5115 = or(_T_5114, _T_5108) wire _WIRE_310 : UInt<1> connect _WIRE_310, _T_5115 connect _WIRE_231.is_sfence, _WIRE_310 node _T_5116 = mux(_T_608, deq_vec[0][2].is_fencei, UInt<1>(0h0)) node _T_5117 = mux(_T_609, deq_vec[1][2].is_fencei, UInt<1>(0h0)) node _T_5118 = mux(_T_610, deq_vec[2][2].is_fencei, UInt<1>(0h0)) node _T_5119 = mux(_T_611, deq_vec[3][2].is_fencei, UInt<1>(0h0)) node _T_5120 = mux(_T_612, deq_vec[4][2].is_fencei, UInt<1>(0h0)) node _T_5121 = mux(_T_613, deq_vec[5][2].is_fencei, UInt<1>(0h0)) node _T_5122 = mux(_T_614, deq_vec[6][2].is_fencei, UInt<1>(0h0)) node _T_5123 = mux(_T_615, deq_vec[7][2].is_fencei, UInt<1>(0h0)) node _T_5124 = or(_T_5116, _T_5117) node _T_5125 = or(_T_5124, _T_5118) node _T_5126 = or(_T_5125, _T_5119) node _T_5127 = or(_T_5126, _T_5120) node _T_5128 = or(_T_5127, _T_5121) node _T_5129 = or(_T_5128, _T_5122) node _T_5130 = or(_T_5129, _T_5123) wire _WIRE_311 : UInt<1> connect _WIRE_311, _T_5130 connect _WIRE_231.is_fencei, _WIRE_311 node _T_5131 = mux(_T_608, deq_vec[0][2].is_fence, UInt<1>(0h0)) node _T_5132 = mux(_T_609, deq_vec[1][2].is_fence, UInt<1>(0h0)) node _T_5133 = mux(_T_610, deq_vec[2][2].is_fence, UInt<1>(0h0)) node _T_5134 = mux(_T_611, deq_vec[3][2].is_fence, UInt<1>(0h0)) node _T_5135 = mux(_T_612, deq_vec[4][2].is_fence, UInt<1>(0h0)) node _T_5136 = mux(_T_613, deq_vec[5][2].is_fence, UInt<1>(0h0)) node _T_5137 = mux(_T_614, deq_vec[6][2].is_fence, UInt<1>(0h0)) node _T_5138 = mux(_T_615, deq_vec[7][2].is_fence, UInt<1>(0h0)) node _T_5139 = or(_T_5131, _T_5132) node _T_5140 = or(_T_5139, _T_5133) node _T_5141 = or(_T_5140, _T_5134) node _T_5142 = or(_T_5141, _T_5135) node _T_5143 = or(_T_5142, _T_5136) node _T_5144 = or(_T_5143, _T_5137) node _T_5145 = or(_T_5144, _T_5138) wire _WIRE_312 : UInt<1> connect _WIRE_312, _T_5145 connect _WIRE_231.is_fence, _WIRE_312 node _T_5146 = mux(_T_608, deq_vec[0][2].is_sfb, UInt<1>(0h0)) node _T_5147 = mux(_T_609, deq_vec[1][2].is_sfb, UInt<1>(0h0)) node _T_5148 = mux(_T_610, deq_vec[2][2].is_sfb, UInt<1>(0h0)) node _T_5149 = mux(_T_611, deq_vec[3][2].is_sfb, UInt<1>(0h0)) node _T_5150 = mux(_T_612, deq_vec[4][2].is_sfb, UInt<1>(0h0)) node _T_5151 = mux(_T_613, deq_vec[5][2].is_sfb, UInt<1>(0h0)) node _T_5152 = mux(_T_614, deq_vec[6][2].is_sfb, UInt<1>(0h0)) node _T_5153 = mux(_T_615, deq_vec[7][2].is_sfb, UInt<1>(0h0)) node _T_5154 = or(_T_5146, _T_5147) node _T_5155 = or(_T_5154, _T_5148) node _T_5156 = or(_T_5155, _T_5149) node _T_5157 = or(_T_5156, _T_5150) node _T_5158 = or(_T_5157, _T_5151) node _T_5159 = or(_T_5158, _T_5152) node _T_5160 = or(_T_5159, _T_5153) wire _WIRE_313 : UInt<1> connect _WIRE_313, _T_5160 connect _WIRE_231.is_sfb, _WIRE_313 node _T_5161 = mux(_T_608, deq_vec[0][2].br_type, UInt<1>(0h0)) node _T_5162 = mux(_T_609, deq_vec[1][2].br_type, UInt<1>(0h0)) node _T_5163 = mux(_T_610, deq_vec[2][2].br_type, UInt<1>(0h0)) node _T_5164 = mux(_T_611, deq_vec[3][2].br_type, UInt<1>(0h0)) node _T_5165 = mux(_T_612, deq_vec[4][2].br_type, UInt<1>(0h0)) node _T_5166 = mux(_T_613, deq_vec[5][2].br_type, UInt<1>(0h0)) node _T_5167 = mux(_T_614, deq_vec[6][2].br_type, UInt<1>(0h0)) node _T_5168 = mux(_T_615, deq_vec[7][2].br_type, UInt<1>(0h0)) node _T_5169 = or(_T_5161, _T_5162) node _T_5170 = or(_T_5169, _T_5163) node _T_5171 = or(_T_5170, _T_5164) node _T_5172 = or(_T_5171, _T_5165) node _T_5173 = or(_T_5172, _T_5166) node _T_5174 = or(_T_5173, _T_5167) node _T_5175 = or(_T_5174, _T_5168) wire _WIRE_314 : UInt<4> connect _WIRE_314, _T_5175 connect _WIRE_231.br_type, _WIRE_314 node _T_5176 = mux(_T_608, deq_vec[0][2].br_tag, UInt<1>(0h0)) node _T_5177 = mux(_T_609, deq_vec[1][2].br_tag, UInt<1>(0h0)) node _T_5178 = mux(_T_610, deq_vec[2][2].br_tag, UInt<1>(0h0)) node _T_5179 = mux(_T_611, deq_vec[3][2].br_tag, UInt<1>(0h0)) node _T_5180 = mux(_T_612, deq_vec[4][2].br_tag, UInt<1>(0h0)) node _T_5181 = mux(_T_613, deq_vec[5][2].br_tag, UInt<1>(0h0)) node _T_5182 = mux(_T_614, deq_vec[6][2].br_tag, UInt<1>(0h0)) node _T_5183 = mux(_T_615, deq_vec[7][2].br_tag, UInt<1>(0h0)) node _T_5184 = or(_T_5176, _T_5177) node _T_5185 = or(_T_5184, _T_5178) node _T_5186 = or(_T_5185, _T_5179) node _T_5187 = or(_T_5186, _T_5180) node _T_5188 = or(_T_5187, _T_5181) node _T_5189 = or(_T_5188, _T_5182) node _T_5190 = or(_T_5189, _T_5183) wire _WIRE_315 : UInt<4> connect _WIRE_315, _T_5190 connect _WIRE_231.br_tag, _WIRE_315 node _T_5191 = mux(_T_608, deq_vec[0][2].br_mask, UInt<1>(0h0)) node _T_5192 = mux(_T_609, deq_vec[1][2].br_mask, UInt<1>(0h0)) node _T_5193 = mux(_T_610, deq_vec[2][2].br_mask, UInt<1>(0h0)) node _T_5194 = mux(_T_611, deq_vec[3][2].br_mask, UInt<1>(0h0)) node _T_5195 = mux(_T_612, deq_vec[4][2].br_mask, UInt<1>(0h0)) node _T_5196 = mux(_T_613, deq_vec[5][2].br_mask, UInt<1>(0h0)) node _T_5197 = mux(_T_614, deq_vec[6][2].br_mask, UInt<1>(0h0)) node _T_5198 = mux(_T_615, deq_vec[7][2].br_mask, UInt<1>(0h0)) node _T_5199 = or(_T_5191, _T_5192) node _T_5200 = or(_T_5199, _T_5193) node _T_5201 = or(_T_5200, _T_5194) node _T_5202 = or(_T_5201, _T_5195) node _T_5203 = or(_T_5202, _T_5196) node _T_5204 = or(_T_5203, _T_5197) node _T_5205 = or(_T_5204, _T_5198) wire _WIRE_316 : UInt<16> connect _WIRE_316, _T_5205 connect _WIRE_231.br_mask, _WIRE_316 node _T_5206 = mux(_T_608, deq_vec[0][2].dis_col_sel, UInt<1>(0h0)) node _T_5207 = mux(_T_609, deq_vec[1][2].dis_col_sel, UInt<1>(0h0)) node _T_5208 = mux(_T_610, deq_vec[2][2].dis_col_sel, UInt<1>(0h0)) node _T_5209 = mux(_T_611, deq_vec[3][2].dis_col_sel, UInt<1>(0h0)) node _T_5210 = mux(_T_612, deq_vec[4][2].dis_col_sel, UInt<1>(0h0)) node _T_5211 = mux(_T_613, deq_vec[5][2].dis_col_sel, UInt<1>(0h0)) node _T_5212 = mux(_T_614, deq_vec[6][2].dis_col_sel, UInt<1>(0h0)) node _T_5213 = mux(_T_615, deq_vec[7][2].dis_col_sel, UInt<1>(0h0)) node _T_5214 = or(_T_5206, _T_5207) node _T_5215 = or(_T_5214, _T_5208) node _T_5216 = or(_T_5215, _T_5209) node _T_5217 = or(_T_5216, _T_5210) node _T_5218 = or(_T_5217, _T_5211) node _T_5219 = or(_T_5218, _T_5212) node _T_5220 = or(_T_5219, _T_5213) wire _WIRE_317 : UInt<3> connect _WIRE_317, _T_5220 connect _WIRE_231.dis_col_sel, _WIRE_317 node _T_5221 = mux(_T_608, deq_vec[0][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5222 = mux(_T_609, deq_vec[1][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5223 = mux(_T_610, deq_vec[2][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5224 = mux(_T_611, deq_vec[3][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5225 = mux(_T_612, deq_vec[4][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5226 = mux(_T_613, deq_vec[5][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5227 = mux(_T_614, deq_vec[6][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5228 = mux(_T_615, deq_vec[7][2].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_5229 = or(_T_5221, _T_5222) node _T_5230 = or(_T_5229, _T_5223) node _T_5231 = or(_T_5230, _T_5224) node _T_5232 = or(_T_5231, _T_5225) node _T_5233 = or(_T_5232, _T_5226) node _T_5234 = or(_T_5233, _T_5227) node _T_5235 = or(_T_5234, _T_5228) wire _WIRE_318 : UInt<1> connect _WIRE_318, _T_5235 connect _WIRE_231.iw_p3_bypass_hint, _WIRE_318 node _T_5236 = mux(_T_608, deq_vec[0][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5237 = mux(_T_609, deq_vec[1][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5238 = mux(_T_610, deq_vec[2][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5239 = mux(_T_611, deq_vec[3][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5240 = mux(_T_612, deq_vec[4][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5241 = mux(_T_613, deq_vec[5][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5242 = mux(_T_614, deq_vec[6][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5243 = mux(_T_615, deq_vec[7][2].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_5244 = or(_T_5236, _T_5237) node _T_5245 = or(_T_5244, _T_5238) node _T_5246 = or(_T_5245, _T_5239) node _T_5247 = or(_T_5246, _T_5240) node _T_5248 = or(_T_5247, _T_5241) node _T_5249 = or(_T_5248, _T_5242) node _T_5250 = or(_T_5249, _T_5243) wire _WIRE_319 : UInt<1> connect _WIRE_319, _T_5250 connect _WIRE_231.iw_p2_bypass_hint, _WIRE_319 node _T_5251 = mux(_T_608, deq_vec[0][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5252 = mux(_T_609, deq_vec[1][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5253 = mux(_T_610, deq_vec[2][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5254 = mux(_T_611, deq_vec[3][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5255 = mux(_T_612, deq_vec[4][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5256 = mux(_T_613, deq_vec[5][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5257 = mux(_T_614, deq_vec[6][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5258 = mux(_T_615, deq_vec[7][2].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_5259 = or(_T_5251, _T_5252) node _T_5260 = or(_T_5259, _T_5253) node _T_5261 = or(_T_5260, _T_5254) node _T_5262 = or(_T_5261, _T_5255) node _T_5263 = or(_T_5262, _T_5256) node _T_5264 = or(_T_5263, _T_5257) node _T_5265 = or(_T_5264, _T_5258) wire _WIRE_320 : UInt<1> connect _WIRE_320, _T_5265 connect _WIRE_231.iw_p1_bypass_hint, _WIRE_320 node _T_5266 = mux(_T_608, deq_vec[0][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5267 = mux(_T_609, deq_vec[1][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5268 = mux(_T_610, deq_vec[2][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5269 = mux(_T_611, deq_vec[3][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5270 = mux(_T_612, deq_vec[4][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5271 = mux(_T_613, deq_vec[5][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5272 = mux(_T_614, deq_vec[6][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5273 = mux(_T_615, deq_vec[7][2].iw_p2_speculative_child, UInt<1>(0h0)) node _T_5274 = or(_T_5266, _T_5267) node _T_5275 = or(_T_5274, _T_5268) node _T_5276 = or(_T_5275, _T_5269) node _T_5277 = or(_T_5276, _T_5270) node _T_5278 = or(_T_5277, _T_5271) node _T_5279 = or(_T_5278, _T_5272) node _T_5280 = or(_T_5279, _T_5273) wire _WIRE_321 : UInt<3> connect _WIRE_321, _T_5280 connect _WIRE_231.iw_p2_speculative_child, _WIRE_321 node _T_5281 = mux(_T_608, deq_vec[0][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5282 = mux(_T_609, deq_vec[1][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5283 = mux(_T_610, deq_vec[2][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5284 = mux(_T_611, deq_vec[3][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5285 = mux(_T_612, deq_vec[4][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5286 = mux(_T_613, deq_vec[5][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5287 = mux(_T_614, deq_vec[6][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5288 = mux(_T_615, deq_vec[7][2].iw_p1_speculative_child, UInt<1>(0h0)) node _T_5289 = or(_T_5281, _T_5282) node _T_5290 = or(_T_5289, _T_5283) node _T_5291 = or(_T_5290, _T_5284) node _T_5292 = or(_T_5291, _T_5285) node _T_5293 = or(_T_5292, _T_5286) node _T_5294 = or(_T_5293, _T_5287) node _T_5295 = or(_T_5294, _T_5288) wire _WIRE_322 : UInt<3> connect _WIRE_322, _T_5295 connect _WIRE_231.iw_p1_speculative_child, _WIRE_322 node _T_5296 = mux(_T_608, deq_vec[0][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5297 = mux(_T_609, deq_vec[1][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5298 = mux(_T_610, deq_vec[2][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5299 = mux(_T_611, deq_vec[3][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5300 = mux(_T_612, deq_vec[4][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5301 = mux(_T_613, deq_vec[5][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5302 = mux(_T_614, deq_vec[6][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5303 = mux(_T_615, deq_vec[7][2].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_5304 = or(_T_5296, _T_5297) node _T_5305 = or(_T_5304, _T_5298) node _T_5306 = or(_T_5305, _T_5299) node _T_5307 = or(_T_5306, _T_5300) node _T_5308 = or(_T_5307, _T_5301) node _T_5309 = or(_T_5308, _T_5302) node _T_5310 = or(_T_5309, _T_5303) wire _WIRE_323 : UInt<1> connect _WIRE_323, _T_5310 connect _WIRE_231.iw_issued_partial_dgen, _WIRE_323 node _T_5311 = mux(_T_608, deq_vec[0][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5312 = mux(_T_609, deq_vec[1][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5313 = mux(_T_610, deq_vec[2][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5314 = mux(_T_611, deq_vec[3][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5315 = mux(_T_612, deq_vec[4][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5316 = mux(_T_613, deq_vec[5][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5317 = mux(_T_614, deq_vec[6][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5318 = mux(_T_615, deq_vec[7][2].iw_issued_partial_agen, UInt<1>(0h0)) node _T_5319 = or(_T_5311, _T_5312) node _T_5320 = or(_T_5319, _T_5313) node _T_5321 = or(_T_5320, _T_5314) node _T_5322 = or(_T_5321, _T_5315) node _T_5323 = or(_T_5322, _T_5316) node _T_5324 = or(_T_5323, _T_5317) node _T_5325 = or(_T_5324, _T_5318) wire _WIRE_324 : UInt<1> connect _WIRE_324, _T_5325 connect _WIRE_231.iw_issued_partial_agen, _WIRE_324 node _T_5326 = mux(_T_608, deq_vec[0][2].iw_issued, UInt<1>(0h0)) node _T_5327 = mux(_T_609, deq_vec[1][2].iw_issued, UInt<1>(0h0)) node _T_5328 = mux(_T_610, deq_vec[2][2].iw_issued, UInt<1>(0h0)) node _T_5329 = mux(_T_611, deq_vec[3][2].iw_issued, UInt<1>(0h0)) node _T_5330 = mux(_T_612, deq_vec[4][2].iw_issued, UInt<1>(0h0)) node _T_5331 = mux(_T_613, deq_vec[5][2].iw_issued, UInt<1>(0h0)) node _T_5332 = mux(_T_614, deq_vec[6][2].iw_issued, UInt<1>(0h0)) node _T_5333 = mux(_T_615, deq_vec[7][2].iw_issued, UInt<1>(0h0)) node _T_5334 = or(_T_5326, _T_5327) node _T_5335 = or(_T_5334, _T_5328) node _T_5336 = or(_T_5335, _T_5329) node _T_5337 = or(_T_5336, _T_5330) node _T_5338 = or(_T_5337, _T_5331) node _T_5339 = or(_T_5338, _T_5332) node _T_5340 = or(_T_5339, _T_5333) wire _WIRE_325 : UInt<1> connect _WIRE_325, _T_5340 connect _WIRE_231.iw_issued, _WIRE_325 wire _WIRE_326 : UInt<1>[10] node _T_5341 = mux(_T_608, deq_vec[0][2].fu_code[0], UInt<1>(0h0)) node _T_5342 = mux(_T_609, deq_vec[1][2].fu_code[0], UInt<1>(0h0)) node _T_5343 = mux(_T_610, deq_vec[2][2].fu_code[0], UInt<1>(0h0)) node _T_5344 = mux(_T_611, deq_vec[3][2].fu_code[0], UInt<1>(0h0)) node _T_5345 = mux(_T_612, deq_vec[4][2].fu_code[0], UInt<1>(0h0)) node _T_5346 = mux(_T_613, deq_vec[5][2].fu_code[0], UInt<1>(0h0)) node _T_5347 = mux(_T_614, deq_vec[6][2].fu_code[0], UInt<1>(0h0)) node _T_5348 = mux(_T_615, deq_vec[7][2].fu_code[0], UInt<1>(0h0)) node _T_5349 = or(_T_5341, _T_5342) node _T_5350 = or(_T_5349, _T_5343) node _T_5351 = or(_T_5350, _T_5344) node _T_5352 = or(_T_5351, _T_5345) node _T_5353 = or(_T_5352, _T_5346) node _T_5354 = or(_T_5353, _T_5347) node _T_5355 = or(_T_5354, _T_5348) wire _WIRE_327 : UInt<1> connect _WIRE_327, _T_5355 connect _WIRE_326[0], _WIRE_327 node _T_5356 = mux(_T_608, deq_vec[0][2].fu_code[1], UInt<1>(0h0)) node _T_5357 = mux(_T_609, deq_vec[1][2].fu_code[1], UInt<1>(0h0)) node _T_5358 = mux(_T_610, deq_vec[2][2].fu_code[1], UInt<1>(0h0)) node _T_5359 = mux(_T_611, deq_vec[3][2].fu_code[1], UInt<1>(0h0)) node _T_5360 = mux(_T_612, deq_vec[4][2].fu_code[1], UInt<1>(0h0)) node _T_5361 = mux(_T_613, deq_vec[5][2].fu_code[1], UInt<1>(0h0)) node _T_5362 = mux(_T_614, deq_vec[6][2].fu_code[1], UInt<1>(0h0)) node _T_5363 = mux(_T_615, deq_vec[7][2].fu_code[1], UInt<1>(0h0)) node _T_5364 = or(_T_5356, _T_5357) node _T_5365 = or(_T_5364, _T_5358) node _T_5366 = or(_T_5365, _T_5359) node _T_5367 = or(_T_5366, _T_5360) node _T_5368 = or(_T_5367, _T_5361) node _T_5369 = or(_T_5368, _T_5362) node _T_5370 = or(_T_5369, _T_5363) wire _WIRE_328 : UInt<1> connect _WIRE_328, _T_5370 connect _WIRE_326[1], _WIRE_328 node _T_5371 = mux(_T_608, deq_vec[0][2].fu_code[2], UInt<1>(0h0)) node _T_5372 = mux(_T_609, deq_vec[1][2].fu_code[2], UInt<1>(0h0)) node _T_5373 = mux(_T_610, deq_vec[2][2].fu_code[2], UInt<1>(0h0)) node _T_5374 = mux(_T_611, deq_vec[3][2].fu_code[2], UInt<1>(0h0)) node _T_5375 = mux(_T_612, deq_vec[4][2].fu_code[2], UInt<1>(0h0)) node _T_5376 = mux(_T_613, deq_vec[5][2].fu_code[2], UInt<1>(0h0)) node _T_5377 = mux(_T_614, deq_vec[6][2].fu_code[2], UInt<1>(0h0)) node _T_5378 = mux(_T_615, deq_vec[7][2].fu_code[2], UInt<1>(0h0)) node _T_5379 = or(_T_5371, _T_5372) node _T_5380 = or(_T_5379, _T_5373) node _T_5381 = or(_T_5380, _T_5374) node _T_5382 = or(_T_5381, _T_5375) node _T_5383 = or(_T_5382, _T_5376) node _T_5384 = or(_T_5383, _T_5377) node _T_5385 = or(_T_5384, _T_5378) wire _WIRE_329 : UInt<1> connect _WIRE_329, _T_5385 connect _WIRE_326[2], _WIRE_329 node _T_5386 = mux(_T_608, deq_vec[0][2].fu_code[3], UInt<1>(0h0)) node _T_5387 = mux(_T_609, deq_vec[1][2].fu_code[3], UInt<1>(0h0)) node _T_5388 = mux(_T_610, deq_vec[2][2].fu_code[3], UInt<1>(0h0)) node _T_5389 = mux(_T_611, deq_vec[3][2].fu_code[3], UInt<1>(0h0)) node _T_5390 = mux(_T_612, deq_vec[4][2].fu_code[3], UInt<1>(0h0)) node _T_5391 = mux(_T_613, deq_vec[5][2].fu_code[3], UInt<1>(0h0)) node _T_5392 = mux(_T_614, deq_vec[6][2].fu_code[3], UInt<1>(0h0)) node _T_5393 = mux(_T_615, deq_vec[7][2].fu_code[3], UInt<1>(0h0)) node _T_5394 = or(_T_5386, _T_5387) node _T_5395 = or(_T_5394, _T_5388) node _T_5396 = or(_T_5395, _T_5389) node _T_5397 = or(_T_5396, _T_5390) node _T_5398 = or(_T_5397, _T_5391) node _T_5399 = or(_T_5398, _T_5392) node _T_5400 = or(_T_5399, _T_5393) wire _WIRE_330 : UInt<1> connect _WIRE_330, _T_5400 connect _WIRE_326[3], _WIRE_330 node _T_5401 = mux(_T_608, deq_vec[0][2].fu_code[4], UInt<1>(0h0)) node _T_5402 = mux(_T_609, deq_vec[1][2].fu_code[4], UInt<1>(0h0)) node _T_5403 = mux(_T_610, deq_vec[2][2].fu_code[4], UInt<1>(0h0)) node _T_5404 = mux(_T_611, deq_vec[3][2].fu_code[4], UInt<1>(0h0)) node _T_5405 = mux(_T_612, deq_vec[4][2].fu_code[4], UInt<1>(0h0)) node _T_5406 = mux(_T_613, deq_vec[5][2].fu_code[4], UInt<1>(0h0)) node _T_5407 = mux(_T_614, deq_vec[6][2].fu_code[4], UInt<1>(0h0)) node _T_5408 = mux(_T_615, deq_vec[7][2].fu_code[4], UInt<1>(0h0)) node _T_5409 = or(_T_5401, _T_5402) node _T_5410 = or(_T_5409, _T_5403) node _T_5411 = or(_T_5410, _T_5404) node _T_5412 = or(_T_5411, _T_5405) node _T_5413 = or(_T_5412, _T_5406) node _T_5414 = or(_T_5413, _T_5407) node _T_5415 = or(_T_5414, _T_5408) wire _WIRE_331 : UInt<1> connect _WIRE_331, _T_5415 connect _WIRE_326[4], _WIRE_331 node _T_5416 = mux(_T_608, deq_vec[0][2].fu_code[5], UInt<1>(0h0)) node _T_5417 = mux(_T_609, deq_vec[1][2].fu_code[5], UInt<1>(0h0)) node _T_5418 = mux(_T_610, deq_vec[2][2].fu_code[5], UInt<1>(0h0)) node _T_5419 = mux(_T_611, deq_vec[3][2].fu_code[5], UInt<1>(0h0)) node _T_5420 = mux(_T_612, deq_vec[4][2].fu_code[5], UInt<1>(0h0)) node _T_5421 = mux(_T_613, deq_vec[5][2].fu_code[5], UInt<1>(0h0)) node _T_5422 = mux(_T_614, deq_vec[6][2].fu_code[5], UInt<1>(0h0)) node _T_5423 = mux(_T_615, deq_vec[7][2].fu_code[5], UInt<1>(0h0)) node _T_5424 = or(_T_5416, _T_5417) node _T_5425 = or(_T_5424, _T_5418) node _T_5426 = or(_T_5425, _T_5419) node _T_5427 = or(_T_5426, _T_5420) node _T_5428 = or(_T_5427, _T_5421) node _T_5429 = or(_T_5428, _T_5422) node _T_5430 = or(_T_5429, _T_5423) wire _WIRE_332 : UInt<1> connect _WIRE_332, _T_5430 connect _WIRE_326[5], _WIRE_332 node _T_5431 = mux(_T_608, deq_vec[0][2].fu_code[6], UInt<1>(0h0)) node _T_5432 = mux(_T_609, deq_vec[1][2].fu_code[6], UInt<1>(0h0)) node _T_5433 = mux(_T_610, deq_vec[2][2].fu_code[6], UInt<1>(0h0)) node _T_5434 = mux(_T_611, deq_vec[3][2].fu_code[6], UInt<1>(0h0)) node _T_5435 = mux(_T_612, deq_vec[4][2].fu_code[6], UInt<1>(0h0)) node _T_5436 = mux(_T_613, deq_vec[5][2].fu_code[6], UInt<1>(0h0)) node _T_5437 = mux(_T_614, deq_vec[6][2].fu_code[6], UInt<1>(0h0)) node _T_5438 = mux(_T_615, deq_vec[7][2].fu_code[6], UInt<1>(0h0)) node _T_5439 = or(_T_5431, _T_5432) node _T_5440 = or(_T_5439, _T_5433) node _T_5441 = or(_T_5440, _T_5434) node _T_5442 = or(_T_5441, _T_5435) node _T_5443 = or(_T_5442, _T_5436) node _T_5444 = or(_T_5443, _T_5437) node _T_5445 = or(_T_5444, _T_5438) wire _WIRE_333 : UInt<1> connect _WIRE_333, _T_5445 connect _WIRE_326[6], _WIRE_333 node _T_5446 = mux(_T_608, deq_vec[0][2].fu_code[7], UInt<1>(0h0)) node _T_5447 = mux(_T_609, deq_vec[1][2].fu_code[7], UInt<1>(0h0)) node _T_5448 = mux(_T_610, deq_vec[2][2].fu_code[7], UInt<1>(0h0)) node _T_5449 = mux(_T_611, deq_vec[3][2].fu_code[7], UInt<1>(0h0)) node _T_5450 = mux(_T_612, deq_vec[4][2].fu_code[7], UInt<1>(0h0)) node _T_5451 = mux(_T_613, deq_vec[5][2].fu_code[7], UInt<1>(0h0)) node _T_5452 = mux(_T_614, deq_vec[6][2].fu_code[7], UInt<1>(0h0)) node _T_5453 = mux(_T_615, deq_vec[7][2].fu_code[7], UInt<1>(0h0)) node _T_5454 = or(_T_5446, _T_5447) node _T_5455 = or(_T_5454, _T_5448) node _T_5456 = or(_T_5455, _T_5449) node _T_5457 = or(_T_5456, _T_5450) node _T_5458 = or(_T_5457, _T_5451) node _T_5459 = or(_T_5458, _T_5452) node _T_5460 = or(_T_5459, _T_5453) wire _WIRE_334 : UInt<1> connect _WIRE_334, _T_5460 connect _WIRE_326[7], _WIRE_334 node _T_5461 = mux(_T_608, deq_vec[0][2].fu_code[8], UInt<1>(0h0)) node _T_5462 = mux(_T_609, deq_vec[1][2].fu_code[8], UInt<1>(0h0)) node _T_5463 = mux(_T_610, deq_vec[2][2].fu_code[8], UInt<1>(0h0)) node _T_5464 = mux(_T_611, deq_vec[3][2].fu_code[8], UInt<1>(0h0)) node _T_5465 = mux(_T_612, deq_vec[4][2].fu_code[8], UInt<1>(0h0)) node _T_5466 = mux(_T_613, deq_vec[5][2].fu_code[8], UInt<1>(0h0)) node _T_5467 = mux(_T_614, deq_vec[6][2].fu_code[8], UInt<1>(0h0)) node _T_5468 = mux(_T_615, deq_vec[7][2].fu_code[8], UInt<1>(0h0)) node _T_5469 = or(_T_5461, _T_5462) node _T_5470 = or(_T_5469, _T_5463) node _T_5471 = or(_T_5470, _T_5464) node _T_5472 = or(_T_5471, _T_5465) node _T_5473 = or(_T_5472, _T_5466) node _T_5474 = or(_T_5473, _T_5467) node _T_5475 = or(_T_5474, _T_5468) wire _WIRE_335 : UInt<1> connect _WIRE_335, _T_5475 connect _WIRE_326[8], _WIRE_335 node _T_5476 = mux(_T_608, deq_vec[0][2].fu_code[9], UInt<1>(0h0)) node _T_5477 = mux(_T_609, deq_vec[1][2].fu_code[9], UInt<1>(0h0)) node _T_5478 = mux(_T_610, deq_vec[2][2].fu_code[9], UInt<1>(0h0)) node _T_5479 = mux(_T_611, deq_vec[3][2].fu_code[9], UInt<1>(0h0)) node _T_5480 = mux(_T_612, deq_vec[4][2].fu_code[9], UInt<1>(0h0)) node _T_5481 = mux(_T_613, deq_vec[5][2].fu_code[9], UInt<1>(0h0)) node _T_5482 = mux(_T_614, deq_vec[6][2].fu_code[9], UInt<1>(0h0)) node _T_5483 = mux(_T_615, deq_vec[7][2].fu_code[9], UInt<1>(0h0)) node _T_5484 = or(_T_5476, _T_5477) node _T_5485 = or(_T_5484, _T_5478) node _T_5486 = or(_T_5485, _T_5479) node _T_5487 = or(_T_5486, _T_5480) node _T_5488 = or(_T_5487, _T_5481) node _T_5489 = or(_T_5488, _T_5482) node _T_5490 = or(_T_5489, _T_5483) wire _WIRE_336 : UInt<1> connect _WIRE_336, _T_5490 connect _WIRE_326[9], _WIRE_336 connect _WIRE_231.fu_code, _WIRE_326 wire _WIRE_337 : UInt<1>[4] node _T_5491 = mux(_T_608, deq_vec[0][2].iq_type[0], UInt<1>(0h0)) node _T_5492 = mux(_T_609, deq_vec[1][2].iq_type[0], UInt<1>(0h0)) node _T_5493 = mux(_T_610, deq_vec[2][2].iq_type[0], UInt<1>(0h0)) node _T_5494 = mux(_T_611, deq_vec[3][2].iq_type[0], UInt<1>(0h0)) node _T_5495 = mux(_T_612, deq_vec[4][2].iq_type[0], UInt<1>(0h0)) node _T_5496 = mux(_T_613, deq_vec[5][2].iq_type[0], UInt<1>(0h0)) node _T_5497 = mux(_T_614, deq_vec[6][2].iq_type[0], UInt<1>(0h0)) node _T_5498 = mux(_T_615, deq_vec[7][2].iq_type[0], UInt<1>(0h0)) node _T_5499 = or(_T_5491, _T_5492) node _T_5500 = or(_T_5499, _T_5493) node _T_5501 = or(_T_5500, _T_5494) node _T_5502 = or(_T_5501, _T_5495) node _T_5503 = or(_T_5502, _T_5496) node _T_5504 = or(_T_5503, _T_5497) node _T_5505 = or(_T_5504, _T_5498) wire _WIRE_338 : UInt<1> connect _WIRE_338, _T_5505 connect _WIRE_337[0], _WIRE_338 node _T_5506 = mux(_T_608, deq_vec[0][2].iq_type[1], UInt<1>(0h0)) node _T_5507 = mux(_T_609, deq_vec[1][2].iq_type[1], UInt<1>(0h0)) node _T_5508 = mux(_T_610, deq_vec[2][2].iq_type[1], UInt<1>(0h0)) node _T_5509 = mux(_T_611, deq_vec[3][2].iq_type[1], UInt<1>(0h0)) node _T_5510 = mux(_T_612, deq_vec[4][2].iq_type[1], UInt<1>(0h0)) node _T_5511 = mux(_T_613, deq_vec[5][2].iq_type[1], UInt<1>(0h0)) node _T_5512 = mux(_T_614, deq_vec[6][2].iq_type[1], UInt<1>(0h0)) node _T_5513 = mux(_T_615, deq_vec[7][2].iq_type[1], UInt<1>(0h0)) node _T_5514 = or(_T_5506, _T_5507) node _T_5515 = or(_T_5514, _T_5508) node _T_5516 = or(_T_5515, _T_5509) node _T_5517 = or(_T_5516, _T_5510) node _T_5518 = or(_T_5517, _T_5511) node _T_5519 = or(_T_5518, _T_5512) node _T_5520 = or(_T_5519, _T_5513) wire _WIRE_339 : UInt<1> connect _WIRE_339, _T_5520 connect _WIRE_337[1], _WIRE_339 node _T_5521 = mux(_T_608, deq_vec[0][2].iq_type[2], UInt<1>(0h0)) node _T_5522 = mux(_T_609, deq_vec[1][2].iq_type[2], UInt<1>(0h0)) node _T_5523 = mux(_T_610, deq_vec[2][2].iq_type[2], UInt<1>(0h0)) node _T_5524 = mux(_T_611, deq_vec[3][2].iq_type[2], UInt<1>(0h0)) node _T_5525 = mux(_T_612, deq_vec[4][2].iq_type[2], UInt<1>(0h0)) node _T_5526 = mux(_T_613, deq_vec[5][2].iq_type[2], UInt<1>(0h0)) node _T_5527 = mux(_T_614, deq_vec[6][2].iq_type[2], UInt<1>(0h0)) node _T_5528 = mux(_T_615, deq_vec[7][2].iq_type[2], UInt<1>(0h0)) node _T_5529 = or(_T_5521, _T_5522) node _T_5530 = or(_T_5529, _T_5523) node _T_5531 = or(_T_5530, _T_5524) node _T_5532 = or(_T_5531, _T_5525) node _T_5533 = or(_T_5532, _T_5526) node _T_5534 = or(_T_5533, _T_5527) node _T_5535 = or(_T_5534, _T_5528) wire _WIRE_340 : UInt<1> connect _WIRE_340, _T_5535 connect _WIRE_337[2], _WIRE_340 node _T_5536 = mux(_T_608, deq_vec[0][2].iq_type[3], UInt<1>(0h0)) node _T_5537 = mux(_T_609, deq_vec[1][2].iq_type[3], UInt<1>(0h0)) node _T_5538 = mux(_T_610, deq_vec[2][2].iq_type[3], UInt<1>(0h0)) node _T_5539 = mux(_T_611, deq_vec[3][2].iq_type[3], UInt<1>(0h0)) node _T_5540 = mux(_T_612, deq_vec[4][2].iq_type[3], UInt<1>(0h0)) node _T_5541 = mux(_T_613, deq_vec[5][2].iq_type[3], UInt<1>(0h0)) node _T_5542 = mux(_T_614, deq_vec[6][2].iq_type[3], UInt<1>(0h0)) node _T_5543 = mux(_T_615, deq_vec[7][2].iq_type[3], UInt<1>(0h0)) node _T_5544 = or(_T_5536, _T_5537) node _T_5545 = or(_T_5544, _T_5538) node _T_5546 = or(_T_5545, _T_5539) node _T_5547 = or(_T_5546, _T_5540) node _T_5548 = or(_T_5547, _T_5541) node _T_5549 = or(_T_5548, _T_5542) node _T_5550 = or(_T_5549, _T_5543) wire _WIRE_341 : UInt<1> connect _WIRE_341, _T_5550 connect _WIRE_337[3], _WIRE_341 connect _WIRE_231.iq_type, _WIRE_337 node _T_5551 = mux(_T_608, deq_vec[0][2].debug_pc, UInt<1>(0h0)) node _T_5552 = mux(_T_609, deq_vec[1][2].debug_pc, UInt<1>(0h0)) node _T_5553 = mux(_T_610, deq_vec[2][2].debug_pc, UInt<1>(0h0)) node _T_5554 = mux(_T_611, deq_vec[3][2].debug_pc, UInt<1>(0h0)) node _T_5555 = mux(_T_612, deq_vec[4][2].debug_pc, UInt<1>(0h0)) node _T_5556 = mux(_T_613, deq_vec[5][2].debug_pc, UInt<1>(0h0)) node _T_5557 = mux(_T_614, deq_vec[6][2].debug_pc, UInt<1>(0h0)) node _T_5558 = mux(_T_615, deq_vec[7][2].debug_pc, UInt<1>(0h0)) node _T_5559 = or(_T_5551, _T_5552) node _T_5560 = or(_T_5559, _T_5553) node _T_5561 = or(_T_5560, _T_5554) node _T_5562 = or(_T_5561, _T_5555) node _T_5563 = or(_T_5562, _T_5556) node _T_5564 = or(_T_5563, _T_5557) node _T_5565 = or(_T_5564, _T_5558) wire _WIRE_342 : UInt<40> connect _WIRE_342, _T_5565 connect _WIRE_231.debug_pc, _WIRE_342 node _T_5566 = mux(_T_608, deq_vec[0][2].is_rvc, UInt<1>(0h0)) node _T_5567 = mux(_T_609, deq_vec[1][2].is_rvc, UInt<1>(0h0)) node _T_5568 = mux(_T_610, deq_vec[2][2].is_rvc, UInt<1>(0h0)) node _T_5569 = mux(_T_611, deq_vec[3][2].is_rvc, UInt<1>(0h0)) node _T_5570 = mux(_T_612, deq_vec[4][2].is_rvc, UInt<1>(0h0)) node _T_5571 = mux(_T_613, deq_vec[5][2].is_rvc, UInt<1>(0h0)) node _T_5572 = mux(_T_614, deq_vec[6][2].is_rvc, UInt<1>(0h0)) node _T_5573 = mux(_T_615, deq_vec[7][2].is_rvc, UInt<1>(0h0)) node _T_5574 = or(_T_5566, _T_5567) node _T_5575 = or(_T_5574, _T_5568) node _T_5576 = or(_T_5575, _T_5569) node _T_5577 = or(_T_5576, _T_5570) node _T_5578 = or(_T_5577, _T_5571) node _T_5579 = or(_T_5578, _T_5572) node _T_5580 = or(_T_5579, _T_5573) wire _WIRE_343 : UInt<1> connect _WIRE_343, _T_5580 connect _WIRE_231.is_rvc, _WIRE_343 node _T_5581 = mux(_T_608, deq_vec[0][2].debug_inst, UInt<1>(0h0)) node _T_5582 = mux(_T_609, deq_vec[1][2].debug_inst, UInt<1>(0h0)) node _T_5583 = mux(_T_610, deq_vec[2][2].debug_inst, UInt<1>(0h0)) node _T_5584 = mux(_T_611, deq_vec[3][2].debug_inst, UInt<1>(0h0)) node _T_5585 = mux(_T_612, deq_vec[4][2].debug_inst, UInt<1>(0h0)) node _T_5586 = mux(_T_613, deq_vec[5][2].debug_inst, UInt<1>(0h0)) node _T_5587 = mux(_T_614, deq_vec[6][2].debug_inst, UInt<1>(0h0)) node _T_5588 = mux(_T_615, deq_vec[7][2].debug_inst, UInt<1>(0h0)) node _T_5589 = or(_T_5581, _T_5582) node _T_5590 = or(_T_5589, _T_5583) node _T_5591 = or(_T_5590, _T_5584) node _T_5592 = or(_T_5591, _T_5585) node _T_5593 = or(_T_5592, _T_5586) node _T_5594 = or(_T_5593, _T_5587) node _T_5595 = or(_T_5594, _T_5588) wire _WIRE_344 : UInt<32> connect _WIRE_344, _T_5595 connect _WIRE_231.debug_inst, _WIRE_344 node _T_5596 = mux(_T_608, deq_vec[0][2].inst, UInt<1>(0h0)) node _T_5597 = mux(_T_609, deq_vec[1][2].inst, UInt<1>(0h0)) node _T_5598 = mux(_T_610, deq_vec[2][2].inst, UInt<1>(0h0)) node _T_5599 = mux(_T_611, deq_vec[3][2].inst, UInt<1>(0h0)) node _T_5600 = mux(_T_612, deq_vec[4][2].inst, UInt<1>(0h0)) node _T_5601 = mux(_T_613, deq_vec[5][2].inst, UInt<1>(0h0)) node _T_5602 = mux(_T_614, deq_vec[6][2].inst, UInt<1>(0h0)) node _T_5603 = mux(_T_615, deq_vec[7][2].inst, UInt<1>(0h0)) node _T_5604 = or(_T_5596, _T_5597) node _T_5605 = or(_T_5604, _T_5598) node _T_5606 = or(_T_5605, _T_5599) node _T_5607 = or(_T_5606, _T_5600) node _T_5608 = or(_T_5607, _T_5601) node _T_5609 = or(_T_5608, _T_5602) node _T_5610 = or(_T_5609, _T_5603) wire _WIRE_345 : UInt<32> connect _WIRE_345, _T_5610 connect _WIRE_231.inst, _WIRE_345 connect _WIRE[2], _WIRE_231 connect io.deq.bits.uops[0].bits, _WIRE[0] connect io.deq.bits.uops[1].bits, _WIRE[1] connect io.deq.bits.uops[2].bits, _WIRE[2] node _io_deq_valid_T = or(deq_valids_0, deq_valids_1) node _io_deq_valid_T_1 = or(_io_deq_valid_T, deq_valids_2) connect io.deq.valid, _io_deq_valid_T_1 when do_enq : connect tail, _T_31 node _T_5611 = or(in_mask[0], in_mask[1]) node _T_5612 = or(_T_5611, in_mask[2]) node _T_5613 = or(_T_5612, in_mask[3]) node _T_5614 = or(_T_5613, in_mask[4]) node _T_5615 = or(_T_5614, in_mask[5]) node _T_5616 = or(_T_5615, in_mask[6]) node _T_5617 = or(_T_5616, in_mask[7]) when _T_5617 : connect maybe_full, UInt<1>(0h1) when do_deq : node _head_T = bits(head, 6, 0) node _head_T_1 = bits(head, 7, 7) node _head_T_2 = cat(_head_T, _head_T_1) connect head, _head_T_2 connect maybe_full, UInt<1>(0h0) when io.clear : connect head, UInt<1>(0h1) connect tail, UInt<1>(0h1) connect maybe_full, UInt<1>(0h0) node _T_5618 = asUInt(reset) when _T_5618 : connect io.deq.bits.uops[0].valid, UInt<1>(0h0) connect io.deq.bits.uops[1].valid, UInt<1>(0h0) connect io.deq.bits.uops[2].valid, UInt<1>(0h0)

module FetchBuffer( // @[fetch-buffer.scala:40:7] input clock, // @[fetch-buffer.scala:40:7] input reset, // @[fetch-buffer.scala:40:7] output io_enq_ready, // @[fetch-buffer.scala:45:14] input io_enq_valid, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pc, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_next_pc, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_next_fetch, // @[fetch-buffer.scala:45:14] input io_enq_bits_edge_inst_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_edge_inst_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_2, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_3, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_4, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_5, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_6, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_7, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_2, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_3, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_4, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_5, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_6, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_7, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_0, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_1, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_2, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_3, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_4, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_5, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_6, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_7, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_0, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_1, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_2, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_3, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_4, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_5, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_6, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_sfb_masks_7, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_0, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_1, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_2, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_3, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_4, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_5, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_6, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_sfb_dests_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_idx_valid, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_cfi_idx_bits, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_cfi_type, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_is_call, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_is_ret, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_npc_plus4, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_ras_top, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_ftq_idx, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_mask, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_br_mask, // @[fetch-buffer.scala:45:14] input [63:0] io_enq_bits_ghist_old_history, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_current_saw_branch_not_taken, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_new_saw_branch_not_taken, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_new_saw_branch_taken, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_ghist_ras_idx, // @[fetch-buffer.scala:45:14] input io_enq_bits_lhist_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_lhist_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] input io_enq_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_4, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_5, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_6, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_7, // @[fetch-buffer.scala:45:14] input io_enq_bits_end_half_valid, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_end_half_bits, // @[fetch-buffer.scala:45:14] input [119:0] io_enq_bits_bpd_meta_0, // @[fetch-buffer.scala:45:14] input [119:0] io_enq_bits_bpd_meta_1, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_fsrc, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_tsrc, // @[fetch-buffer.scala:45:14] input io_deq_ready, // @[fetch-buffer.scala:45:14] output io_deq_valid, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_0_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_0_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_0_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_0_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_0_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_0_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_1_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_1_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_1_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_1_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_1_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_1_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_2_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_2_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_2_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_2_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_2_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_2_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_2_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] input io_clear // @[fetch-buffer.scala:45:14] ); wire io_enq_valid_0 = io_enq_valid; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_next_pc_0 = io_enq_bits_next_pc; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_next_fetch_0 = io_enq_bits_next_fetch; // @[fetch-buffer.scala:40:7] wire io_enq_bits_edge_inst_0_0 = io_enq_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_edge_inst_1_0 = io_enq_bits_edge_inst_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_0_0 = io_enq_bits_insts_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_1_0 = io_enq_bits_insts_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_2_0 = io_enq_bits_insts_2; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_3_0 = io_enq_bits_insts_3; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_4_0 = io_enq_bits_insts_4; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_5_0 = io_enq_bits_insts_5; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_6_0 = io_enq_bits_insts_6; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_7_0 = io_enq_bits_insts_7; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_0_0 = io_enq_bits_exp_insts_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_1_0 = io_enq_bits_exp_insts_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_2_0 = io_enq_bits_exp_insts_2; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_3_0 = io_enq_bits_exp_insts_3; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_4_0 = io_enq_bits_exp_insts_4; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_5_0 = io_enq_bits_exp_insts_5; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_6_0 = io_enq_bits_exp_insts_6; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_7_0 = io_enq_bits_exp_insts_7; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_0_0 = io_enq_bits_pcs_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_1_0 = io_enq_bits_pcs_1; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_2_0 = io_enq_bits_pcs_2; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_3_0 = io_enq_bits_pcs_3; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_4_0 = io_enq_bits_pcs_4; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_5_0 = io_enq_bits_pcs_5; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_6_0 = io_enq_bits_pcs_6; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_7_0 = io_enq_bits_pcs_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_0_0 = io_enq_bits_sfbs_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_1_0 = io_enq_bits_sfbs_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_2_0 = io_enq_bits_sfbs_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_3_0 = io_enq_bits_sfbs_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_4_0 = io_enq_bits_sfbs_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_5_0 = io_enq_bits_sfbs_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_6_0 = io_enq_bits_sfbs_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_7_0 = io_enq_bits_sfbs_7; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_0_0 = io_enq_bits_sfb_masks_0; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_1_0 = io_enq_bits_sfb_masks_1; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_2_0 = io_enq_bits_sfb_masks_2; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_3_0 = io_enq_bits_sfb_masks_3; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_4_0 = io_enq_bits_sfb_masks_4; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_5_0 = io_enq_bits_sfb_masks_5; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_6_0 = io_enq_bits_sfb_masks_6; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_sfb_masks_7_0 = io_enq_bits_sfb_masks_7; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_0_0 = io_enq_bits_sfb_dests_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_1_0 = io_enq_bits_sfb_dests_1; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_2_0 = io_enq_bits_sfb_dests_2; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_3_0 = io_enq_bits_sfb_dests_3; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_4_0 = io_enq_bits_sfb_dests_4; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_5_0 = io_enq_bits_sfb_dests_5; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_6_0 = io_enq_bits_sfb_dests_6; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_sfb_dests_7_0 = io_enq_bits_sfb_dests_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_0_0 = io_enq_bits_shadowable_mask_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_1_0 = io_enq_bits_shadowable_mask_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_2_0 = io_enq_bits_shadowable_mask_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_3_0 = io_enq_bits_shadowable_mask_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_4_0 = io_enq_bits_shadowable_mask_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_5_0 = io_enq_bits_shadowable_mask_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_6_0 = io_enq_bits_shadowable_mask_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_7_0 = io_enq_bits_shadowable_mask_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_0_0 = io_enq_bits_shadowed_mask_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_1_0 = io_enq_bits_shadowed_mask_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_2_0 = io_enq_bits_shadowed_mask_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_3_0 = io_enq_bits_shadowed_mask_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_4_0 = io_enq_bits_shadowed_mask_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_5_0 = io_enq_bits_shadowed_mask_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_6_0 = io_enq_bits_shadowed_mask_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_7_0 = io_enq_bits_shadowed_mask_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_idx_valid_0 = io_enq_bits_cfi_idx_valid; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_cfi_idx_bits_0 = io_enq_bits_cfi_idx_bits; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_cfi_type_0 = io_enq_bits_cfi_type; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_is_call_0 = io_enq_bits_cfi_is_call; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_is_ret_0 = io_enq_bits_cfi_is_ret; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_npc_plus4_0 = io_enq_bits_cfi_npc_plus4; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_ras_top_0 = io_enq_bits_ras_top; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_ftq_idx_0 = io_enq_bits_ftq_idx; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_br_mask_0 = io_enq_bits_br_mask; // @[fetch-buffer.scala:40:7] wire [63:0] io_enq_bits_ghist_old_history_0 = io_enq_bits_ghist_old_history; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_current_saw_branch_not_taken_0 = io_enq_bits_ghist_current_saw_branch_not_taken; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_new_saw_branch_not_taken_0 = io_enq_bits_ghist_new_saw_branch_not_taken; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_new_saw_branch_taken_0 = io_enq_bits_ghist_new_saw_branch_taken; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_ghist_ras_idx_0 = io_enq_bits_ghist_ras_idx; // @[fetch-buffer.scala:40:7] wire io_enq_bits_lhist_0_0 = io_enq_bits_lhist_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_lhist_1_0 = io_enq_bits_lhist_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_xcpt_pf_if_0 = io_enq_bits_xcpt_pf_if; // @[fetch-buffer.scala:40:7] wire io_enq_bits_xcpt_ae_if_0 = io_enq_bits_xcpt_ae_if; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_0_0 = io_enq_bits_bp_debug_if_oh_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_1_0 = io_enq_bits_bp_debug_if_oh_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_2_0 = io_enq_bits_bp_debug_if_oh_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_3_0 = io_enq_bits_bp_debug_if_oh_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_4_0 = io_enq_bits_bp_debug_if_oh_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_5_0 = io_enq_bits_bp_debug_if_oh_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_6_0 = io_enq_bits_bp_debug_if_oh_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_7_0 = io_enq_bits_bp_debug_if_oh_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_0_0 = io_enq_bits_bp_xcpt_if_oh_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_1_0 = io_enq_bits_bp_xcpt_if_oh_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_2_0 = io_enq_bits_bp_xcpt_if_oh_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_3_0 = io_enq_bits_bp_xcpt_if_oh_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_4_0 = io_enq_bits_bp_xcpt_if_oh_4; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_5_0 = io_enq_bits_bp_xcpt_if_oh_5; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_6_0 = io_enq_bits_bp_xcpt_if_oh_6; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_7_0 = io_enq_bits_bp_xcpt_if_oh_7; // @[fetch-buffer.scala:40:7] wire io_enq_bits_end_half_valid_0 = io_enq_bits_end_half_valid; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_end_half_bits_0 = io_enq_bits_end_half_bits; // @[fetch-buffer.scala:40:7] wire [119:0] io_enq_bits_bpd_meta_0_0 = io_enq_bits_bpd_meta_0; // @[fetch-buffer.scala:40:7] wire [119:0] io_enq_bits_bpd_meta_1_0 = io_enq_bits_bpd_meta_1; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_fsrc_0 = io_enq_bits_fsrc; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_tsrc_0 = io_enq_bits_tsrc; // @[fetch-buffer.scala:40:7] wire io_deq_ready_0 = io_deq_ready; // @[fetch-buffer.scala:40:7] wire io_clear_0 = io_clear; // @[fetch-buffer.scala:40:7] wire _tail_collisions_T_6 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_10 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_18 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_22 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_30 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_34 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_42 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_46 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_54 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_58 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_66 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_70 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_78 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_82 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_90 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_94 = 1'h1; // @[fetch-buffer.scala:155:61] wire [5:0] io_deq_bits_uops_0_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] deq_vec_0_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_2_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] in_uops_0_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [63:0] io_deq_bits_uops_0_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] io_deq_bits_uops_1_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] io_deq_bits_uops_2_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] deq_vec_0_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_0_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_0_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_2_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] in_uops_0_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_1_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_2_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_3_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_4_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_5_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_6_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_7_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [6:0] io_deq_bits_uops_0_bits_rob_idx = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_rob_idx = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_rob_idx = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_2_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] deq_vec_0_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_rob_idx = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] in_uops_0_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_4_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_5_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_6_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_rob_idx = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_7_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [1:0] io_deq_bits_uops_0_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_2_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] deq_vec_0_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_2_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] in_uops_0_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_4_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_5_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_6_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_7_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [19:0] io_deq_bits_uops_0_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] io_deq_bits_uops_1_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] io_deq_bits_uops_2_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] deq_vec_0_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_0_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_0_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_2_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] in_uops_0_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_1_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_2_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_3_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_4_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_5_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_6_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_7_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [4:0] io_deq_bits_uops_0_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ldq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_stq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ldq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_stq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_ldq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_stq_idx = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] deq_vec_0_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_stq_idx = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_2_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] in_uops_0_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_4_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_5_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_6_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_ldq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_stq_idx = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_7_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [3:0] io_deq_bits_uops_0_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_0_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_2_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_2_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] deq_vec_0_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_2_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_2_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] in_uops_0_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_0_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_4_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_4_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_5_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_5_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_6_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_6_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_7_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_7_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [15:0] io_deq_bits_uops_0_bits_br_mask = 16'h0; // @[fetch-buffer.scala:40:7] wire [15:0] io_deq_bits_uops_1_bits_br_mask = 16'h0; // @[fetch-buffer.scala:40:7] wire [15:0] io_deq_bits_uops_2_bits_br_mask = 16'h0; // @[fetch-buffer.scala:40:7] wire [15:0] deq_vec_0_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_0_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_0_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_1_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_1_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_1_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_2_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_2_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_2_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_3_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_3_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_3_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_4_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_4_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_4_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_5_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_5_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_5_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_6_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_6_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_6_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_7_0_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_7_1_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] deq_vec_7_2_br_mask = 16'h0; // @[fetch-buffer.scala:59:21] wire [15:0] in_uops_0_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_1_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_2_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_3_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_4_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_5_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_6_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [15:0] in_uops_7_br_mask = 16'h0; // @[fetch-buffer.scala:88:21] wire [2:0] io_deq_bits_uops_0_bits_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_dis_col_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_dis_col_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_dis_col_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] deq_vec_0_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] in_uops_0_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_4_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_5_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_6_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_iw_p1_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_iw_p2_speculative_child = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_dis_col_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_7_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire io_deq_bits_uops_0_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire deq_vec_0_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire do_enq; // @[fetch-buffer.scala:82:16] wire in_uops_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_4_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_5_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_6_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_7_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_edge_inst = io_enq_bits_edge_inst_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_edge_inst = io_enq_bits_edge_inst_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_0_debug_inst = io_enq_bits_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_1_debug_inst = io_enq_bits_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_2_debug_inst = io_enq_bits_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_3_debug_inst = io_enq_bits_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_4_debug_inst = io_enq_bits_insts_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_5_debug_inst = io_enq_bits_insts_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_6_debug_inst = io_enq_bits_insts_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_7_debug_inst = io_enq_bits_insts_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_0_inst = io_enq_bits_exp_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_1_inst = io_enq_bits_exp_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_2_inst = io_enq_bits_exp_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_3_inst = io_enq_bits_exp_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_4_inst = io_enq_bits_exp_insts_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_5_inst = io_enq_bits_exp_insts_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_6_inst = io_enq_bits_exp_insts_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_7_inst = io_enq_bits_exp_insts_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_0_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_1_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_2_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_3_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_4_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_5_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_6_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_7_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_bp_debug_if = io_enq_bits_bp_debug_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_bp_debug_if = io_enq_bits_bp_debug_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_bp_debug_if = io_enq_bits_bp_debug_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_bp_debug_if = io_enq_bits_bp_debug_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_bp_debug_if = io_enq_bits_bp_debug_if_oh_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_bp_debug_if = io_enq_bits_bp_debug_if_oh_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_bp_debug_if = io_enq_bits_bp_debug_if_oh_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_bp_debug_if = io_enq_bits_bp_debug_if_oh_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_4_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_4_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_5_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_5_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_6_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_6_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_7_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_7_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_0_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_1_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_2_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_3_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_4_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_5_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_6_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_7_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire _io_deq_valid_T_1; // @[fetch-buffer.scala:170:38] wire io_enq_ready_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_1_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_1_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_1_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_valid_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_2_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_2_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_2_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_2_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_2_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_2_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_2_valid_0; // @[fetch-buffer.scala:40:7] wire io_deq_valid_0; // @[fetch-buffer.scala:40:7] reg [31:0] fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_0_inst = fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_0_debug_inst = fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_is_rvc = fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_0_debug_pc = fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_is_sfb = fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_0_ftq_idx = fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_edge_inst = fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_0_pc_lob = fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_taken = fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_xcpt_pf_if = fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_xcpt_ae_if = fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_bp_debug_if = fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_bp_xcpt_if = fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_0_debug_fsrc = fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_1_inst = fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_1_debug_inst = fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_is_rvc = fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_1_debug_pc = fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_is_sfb = fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_1_ftq_idx = fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_edge_inst = fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_1_pc_lob = fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_taken = fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_xcpt_pf_if = fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_xcpt_ae_if = fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_bp_debug_if = fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_bp_xcpt_if = fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_1_debug_fsrc = fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_2_inst = fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_2_debug_inst = fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_is_rvc = fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_2_debug_pc = fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_is_sfb = fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_2_ftq_idx = fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_edge_inst = fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_2_pc_lob = fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_taken = fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_xcpt_pf_if = fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_xcpt_ae_if = fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_bp_debug_if = fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_2_bp_xcpt_if = fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_2_debug_fsrc = fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_0_inst = fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_0_debug_inst = fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_is_rvc = fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_0_debug_pc = fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_is_sfb = fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_0_ftq_idx = fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_edge_inst = fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_0_pc_lob = fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_taken = fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_xcpt_pf_if = fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_xcpt_ae_if = fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_bp_debug_if = fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_bp_xcpt_if = fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_0_debug_fsrc = fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_1_inst = fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_1_debug_inst = fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_is_rvc = fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_1_debug_pc = fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_is_sfb = fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_1_ftq_idx = fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_edge_inst = fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_1_pc_lob = fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_taken = fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_xcpt_pf_if = fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_xcpt_ae_if = fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_bp_debug_if = fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_bp_xcpt_if = fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_1_debug_fsrc = fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_2_inst = fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_2_debug_inst = fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_is_rvc = fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_2_debug_pc = fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_is_sfb = fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_2_ftq_idx = fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_edge_inst = fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_2_pc_lob = fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_taken = fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_xcpt_pf_if = fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_xcpt_ae_if = fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_bp_debug_if = fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_2_bp_xcpt_if = fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_2_debug_fsrc = fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_0_inst = fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_0_debug_inst = fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_is_rvc = fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_0_debug_pc = fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_is_sfb = fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_0_ftq_idx = fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_edge_inst = fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_0_pc_lob = fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_taken = fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_xcpt_pf_if = fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_xcpt_ae_if = fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_bp_debug_if = fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_bp_xcpt_if = fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_0_debug_fsrc = fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_1_inst = fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_1_debug_inst = fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_is_rvc = fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_1_debug_pc = fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_is_sfb = fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_1_ftq_idx = fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_edge_inst = fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_1_pc_lob = fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_taken = fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_xcpt_pf_if = fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_xcpt_ae_if = fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_bp_debug_if = fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_bp_xcpt_if = fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_1_debug_fsrc = fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_8_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_2_inst = fb_uop_ram_8_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_8_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_2_debug_inst = fb_uop_ram_8_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_is_rvc = fb_uop_ram_8_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_8_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_2_debug_pc = fb_uop_ram_8_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_is_sfb = fb_uop_ram_8_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_8_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_2_ftq_idx = fb_uop_ram_8_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_edge_inst = fb_uop_ram_8_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_8_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_2_pc_lob = fb_uop_ram_8_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_taken = fb_uop_ram_8_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_xcpt_pf_if = fb_uop_ram_8_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_xcpt_ae_if = fb_uop_ram_8_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_bp_debug_if = fb_uop_ram_8_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_2_bp_xcpt_if = fb_uop_ram_8_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_8_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_2_debug_fsrc = fb_uop_ram_8_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_9_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_0_inst = fb_uop_ram_9_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_9_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_0_debug_inst = fb_uop_ram_9_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_is_rvc = fb_uop_ram_9_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_9_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_0_debug_pc = fb_uop_ram_9_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_is_sfb = fb_uop_ram_9_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_9_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_0_ftq_idx = fb_uop_ram_9_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_edge_inst = fb_uop_ram_9_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_9_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_0_pc_lob = fb_uop_ram_9_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_taken = fb_uop_ram_9_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_xcpt_pf_if = fb_uop_ram_9_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_xcpt_ae_if = fb_uop_ram_9_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_bp_debug_if = fb_uop_ram_9_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_bp_xcpt_if = fb_uop_ram_9_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_9_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_0_debug_fsrc = fb_uop_ram_9_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_10_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_1_inst = fb_uop_ram_10_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_10_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_1_debug_inst = fb_uop_ram_10_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_is_rvc = fb_uop_ram_10_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_10_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_1_debug_pc = fb_uop_ram_10_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_is_sfb = fb_uop_ram_10_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_10_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_1_ftq_idx = fb_uop_ram_10_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_edge_inst = fb_uop_ram_10_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_10_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_1_pc_lob = fb_uop_ram_10_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_taken = fb_uop_ram_10_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_xcpt_pf_if = fb_uop_ram_10_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_xcpt_ae_if = fb_uop_ram_10_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_bp_debug_if = fb_uop_ram_10_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_bp_xcpt_if = fb_uop_ram_10_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_10_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_1_debug_fsrc = fb_uop_ram_10_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_11_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_2_inst = fb_uop_ram_11_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_11_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_2_debug_inst = fb_uop_ram_11_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_is_rvc = fb_uop_ram_11_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_11_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_2_debug_pc = fb_uop_ram_11_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_is_sfb = fb_uop_ram_11_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_11_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_2_ftq_idx = fb_uop_ram_11_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_edge_inst = fb_uop_ram_11_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_11_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_2_pc_lob = fb_uop_ram_11_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_taken = fb_uop_ram_11_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_xcpt_pf_if = fb_uop_ram_11_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_xcpt_ae_if = fb_uop_ram_11_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_bp_debug_if = fb_uop_ram_11_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_2_bp_xcpt_if = fb_uop_ram_11_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_11_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_2_debug_fsrc = fb_uop_ram_11_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_12_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_0_inst = fb_uop_ram_12_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_12_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_0_debug_inst = fb_uop_ram_12_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_is_rvc = fb_uop_ram_12_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_12_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_0_debug_pc = fb_uop_ram_12_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_is_sfb = fb_uop_ram_12_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_12_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_0_ftq_idx = fb_uop_ram_12_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_edge_inst = fb_uop_ram_12_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_12_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_0_pc_lob = fb_uop_ram_12_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_taken = fb_uop_ram_12_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_xcpt_pf_if = fb_uop_ram_12_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_xcpt_ae_if = fb_uop_ram_12_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_bp_debug_if = fb_uop_ram_12_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_bp_xcpt_if = fb_uop_ram_12_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_12_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_0_debug_fsrc = fb_uop_ram_12_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_13_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_1_inst = fb_uop_ram_13_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_13_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_1_debug_inst = fb_uop_ram_13_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_is_rvc = fb_uop_ram_13_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_13_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_1_debug_pc = fb_uop_ram_13_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_is_sfb = fb_uop_ram_13_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_13_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_1_ftq_idx = fb_uop_ram_13_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_edge_inst = fb_uop_ram_13_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_13_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_1_pc_lob = fb_uop_ram_13_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_taken = fb_uop_ram_13_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_xcpt_pf_if = fb_uop_ram_13_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_xcpt_ae_if = fb_uop_ram_13_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_bp_debug_if = fb_uop_ram_13_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_bp_xcpt_if = fb_uop_ram_13_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_13_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_1_debug_fsrc = fb_uop_ram_13_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_14_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_2_inst = fb_uop_ram_14_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_14_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_2_debug_inst = fb_uop_ram_14_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_is_rvc = fb_uop_ram_14_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_14_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_2_debug_pc = fb_uop_ram_14_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_is_sfb = fb_uop_ram_14_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_14_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_2_ftq_idx = fb_uop_ram_14_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_edge_inst = fb_uop_ram_14_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_14_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_2_pc_lob = fb_uop_ram_14_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_taken = fb_uop_ram_14_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_xcpt_pf_if = fb_uop_ram_14_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_xcpt_ae_if = fb_uop_ram_14_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_bp_debug_if = fb_uop_ram_14_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_2_bp_xcpt_if = fb_uop_ram_14_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_14_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_2_debug_fsrc = fb_uop_ram_14_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_15_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_0_inst = fb_uop_ram_15_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_15_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_0_debug_inst = fb_uop_ram_15_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_is_rvc = fb_uop_ram_15_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_15_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_0_debug_pc = fb_uop_ram_15_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_is_sfb = fb_uop_ram_15_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_15_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_0_ftq_idx = fb_uop_ram_15_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_edge_inst = fb_uop_ram_15_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_15_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_0_pc_lob = fb_uop_ram_15_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_taken = fb_uop_ram_15_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_xcpt_pf_if = fb_uop_ram_15_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_xcpt_ae_if = fb_uop_ram_15_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_bp_debug_if = fb_uop_ram_15_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_bp_xcpt_if = fb_uop_ram_15_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_15_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_0_debug_fsrc = fb_uop_ram_15_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_16_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_1_inst = fb_uop_ram_16_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_16_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_1_debug_inst = fb_uop_ram_16_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_is_rvc = fb_uop_ram_16_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_16_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_1_debug_pc = fb_uop_ram_16_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_is_sfb = fb_uop_ram_16_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_16_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_1_ftq_idx = fb_uop_ram_16_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_edge_inst = fb_uop_ram_16_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_16_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_1_pc_lob = fb_uop_ram_16_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_taken = fb_uop_ram_16_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_xcpt_pf_if = fb_uop_ram_16_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_xcpt_ae_if = fb_uop_ram_16_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_bp_debug_if = fb_uop_ram_16_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_16_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_bp_xcpt_if = fb_uop_ram_16_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_16_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_1_debug_fsrc = fb_uop_ram_16_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_17_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_2_inst = fb_uop_ram_17_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_17_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_2_debug_inst = fb_uop_ram_17_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_is_rvc = fb_uop_ram_17_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_17_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_2_debug_pc = fb_uop_ram_17_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_is_sfb = fb_uop_ram_17_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_17_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_2_ftq_idx = fb_uop_ram_17_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_edge_inst = fb_uop_ram_17_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_17_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_2_pc_lob = fb_uop_ram_17_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_taken = fb_uop_ram_17_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_xcpt_pf_if = fb_uop_ram_17_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_xcpt_ae_if = fb_uop_ram_17_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_bp_debug_if = fb_uop_ram_17_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_17_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_2_bp_xcpt_if = fb_uop_ram_17_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_17_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_2_debug_fsrc = fb_uop_ram_17_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_18_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_0_inst = fb_uop_ram_18_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_18_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_0_debug_inst = fb_uop_ram_18_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_is_rvc = fb_uop_ram_18_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_18_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_0_debug_pc = fb_uop_ram_18_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_is_sfb = fb_uop_ram_18_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_18_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_0_ftq_idx = fb_uop_ram_18_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_edge_inst = fb_uop_ram_18_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_18_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_0_pc_lob = fb_uop_ram_18_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_taken = fb_uop_ram_18_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_xcpt_pf_if = fb_uop_ram_18_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_xcpt_ae_if = fb_uop_ram_18_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_bp_debug_if = fb_uop_ram_18_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_18_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_bp_xcpt_if = fb_uop_ram_18_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_18_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_0_debug_fsrc = fb_uop_ram_18_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_19_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_1_inst = fb_uop_ram_19_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_19_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_1_debug_inst = fb_uop_ram_19_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_is_rvc = fb_uop_ram_19_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_19_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_1_debug_pc = fb_uop_ram_19_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_is_sfb = fb_uop_ram_19_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_19_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_1_ftq_idx = fb_uop_ram_19_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_edge_inst = fb_uop_ram_19_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_19_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_1_pc_lob = fb_uop_ram_19_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_taken = fb_uop_ram_19_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_xcpt_pf_if = fb_uop_ram_19_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_xcpt_ae_if = fb_uop_ram_19_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_bp_debug_if = fb_uop_ram_19_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_19_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_bp_xcpt_if = fb_uop_ram_19_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_19_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_1_debug_fsrc = fb_uop_ram_19_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_20_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_2_inst = fb_uop_ram_20_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_20_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_2_debug_inst = fb_uop_ram_20_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_is_rvc = fb_uop_ram_20_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_20_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_2_debug_pc = fb_uop_ram_20_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_is_sfb = fb_uop_ram_20_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_20_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_2_ftq_idx = fb_uop_ram_20_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_edge_inst = fb_uop_ram_20_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_20_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_2_pc_lob = fb_uop_ram_20_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_taken = fb_uop_ram_20_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_xcpt_pf_if = fb_uop_ram_20_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_xcpt_ae_if = fb_uop_ram_20_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_bp_debug_if = fb_uop_ram_20_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_20_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_2_bp_xcpt_if = fb_uop_ram_20_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_20_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_2_debug_fsrc = fb_uop_ram_20_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_21_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_0_inst = fb_uop_ram_21_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_21_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_0_debug_inst = fb_uop_ram_21_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_is_rvc = fb_uop_ram_21_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_21_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_0_debug_pc = fb_uop_ram_21_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_is_sfb = fb_uop_ram_21_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_21_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_0_ftq_idx = fb_uop_ram_21_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_edge_inst = fb_uop_ram_21_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_21_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_0_pc_lob = fb_uop_ram_21_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_taken = fb_uop_ram_21_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_xcpt_pf_if = fb_uop_ram_21_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_xcpt_ae_if = fb_uop_ram_21_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_bp_debug_if = fb_uop_ram_21_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_21_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_bp_xcpt_if = fb_uop_ram_21_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_21_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_0_debug_fsrc = fb_uop_ram_21_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_22_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_1_inst = fb_uop_ram_22_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_22_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_1_debug_inst = fb_uop_ram_22_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_is_rvc = fb_uop_ram_22_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_22_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_1_debug_pc = fb_uop_ram_22_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_is_sfb = fb_uop_ram_22_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_22_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_1_ftq_idx = fb_uop_ram_22_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_edge_inst = fb_uop_ram_22_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_22_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_1_pc_lob = fb_uop_ram_22_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_taken = fb_uop_ram_22_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_xcpt_pf_if = fb_uop_ram_22_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_xcpt_ae_if = fb_uop_ram_22_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_bp_debug_if = fb_uop_ram_22_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_22_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_bp_xcpt_if = fb_uop_ram_22_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_22_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_1_debug_fsrc = fb_uop_ram_22_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_23_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_2_inst = fb_uop_ram_23_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_23_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_2_debug_inst = fb_uop_ram_23_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_is_rvc = fb_uop_ram_23_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_23_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_2_debug_pc = fb_uop_ram_23_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_is_sfb = fb_uop_ram_23_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_23_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_2_ftq_idx = fb_uop_ram_23_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_edge_inst = fb_uop_ram_23_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_23_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_2_pc_lob = fb_uop_ram_23_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_taken = fb_uop_ram_23_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_xcpt_pf_if = fb_uop_ram_23_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_xcpt_ae_if = fb_uop_ram_23_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_bp_debug_if = fb_uop_ram_23_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_23_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_2_bp_xcpt_if = fb_uop_ram_23_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_23_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_2_debug_fsrc = fb_uop_ram_23_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [7:0] head; // @[fetch-buffer.scala:61:21] reg [23:0] tail; // @[fetch-buffer.scala:62:21] wire [23:0] enq_idxs_0 = tail; // @[fetch-buffer.scala:62:21, :128:22] reg maybe_full; // @[fetch-buffer.scala:64:27] wire [22:0] _might_hit_head_T = tail[22:0]; // @[fetch-buffer.scala:62:21, :75:11] wire _might_hit_head_T_1 = tail[23]; // @[fetch-buffer.scala:62:21, :75:24] wire _at_head_T_23 = tail[23]; // @[fetch-buffer.scala:62:21, :75:24, :80:31] wire [23:0] _might_hit_head_T_2 = {_might_hit_head_T, _might_hit_head_T_1}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_3 = _might_hit_head_T_2[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_0 = _might_hit_head_T_3; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_4 = _might_hit_head_T_2[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_5 = _might_hit_head_T_2[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_6 = _might_hit_head_T_2[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1 = _might_hit_head_T_6; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_7 = _might_hit_head_T_2[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_8 = _might_hit_head_T_2[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_9 = _might_hit_head_T_2[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2 = _might_hit_head_T_9; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_10 = _might_hit_head_T_2[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_11 = _might_hit_head_T_2[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_12 = _might_hit_head_T_2[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3 = _might_hit_head_T_12; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_13 = _might_hit_head_T_2[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_14 = _might_hit_head_T_2[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_15 = _might_hit_head_T_2[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4 = _might_hit_head_T_15; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_16 = _might_hit_head_T_2[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_17 = _might_hit_head_T_2[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_18 = _might_hit_head_T_2[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5 = _might_hit_head_T_18; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_19 = _might_hit_head_T_2[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_20 = _might_hit_head_T_2[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_21 = _might_hit_head_T_2[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6 = _might_hit_head_T_21; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_22 = _might_hit_head_T_2[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_23 = _might_hit_head_T_2[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_24 = _might_hit_head_T_2[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_7 = _might_hit_head_T_24; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_25 = _might_hit_head_T_2[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_26 = _might_hit_head_T_2[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo = {_might_hit_head_WIRE_1, _might_hit_head_WIRE_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi = {_might_hit_head_WIRE_3, _might_hit_head_WIRE_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo = {might_hit_head_lo_hi, might_hit_head_lo_lo}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo = {_might_hit_head_WIRE_5, _might_hit_head_WIRE_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi = {_might_hit_head_WIRE_7, _might_hit_head_WIRE_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi = {might_hit_head_hi_hi, might_hit_head_hi_lo}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_27 = {might_hit_head_hi, might_hit_head_lo}; // @[fetch-buffer.scala:79:63] wire [21:0] _might_hit_head_T_28 = tail[21:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [1:0] _might_hit_head_T_29 = tail[23:22]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_30 = {_might_hit_head_T_28, _might_hit_head_T_29}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_31 = _might_hit_head_T_30[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_0 = _might_hit_head_T_31; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_32 = _might_hit_head_T_30[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_33 = _might_hit_head_T_30[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_34 = _might_hit_head_T_30[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_1 = _might_hit_head_T_34; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_35 = _might_hit_head_T_30[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_36 = _might_hit_head_T_30[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_37 = _might_hit_head_T_30[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_2 = _might_hit_head_T_37; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_38 = _might_hit_head_T_30[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_39 = _might_hit_head_T_30[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_40 = _might_hit_head_T_30[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_3 = _might_hit_head_T_40; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_41 = _might_hit_head_T_30[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_42 = _might_hit_head_T_30[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_43 = _might_hit_head_T_30[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_4 = _might_hit_head_T_43; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_44 = _might_hit_head_T_30[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_45 = _might_hit_head_T_30[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_46 = _might_hit_head_T_30[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_5 = _might_hit_head_T_46; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_47 = _might_hit_head_T_30[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_48 = _might_hit_head_T_30[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_49 = _might_hit_head_T_30[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_6 = _might_hit_head_T_49; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_50 = _might_hit_head_T_30[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_51 = _might_hit_head_T_30[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_52 = _might_hit_head_T_30[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_7 = _might_hit_head_T_52; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_53 = _might_hit_head_T_30[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_54 = _might_hit_head_T_30[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_1 = {_might_hit_head_WIRE_1_1, _might_hit_head_WIRE_1_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_1 = {_might_hit_head_WIRE_1_3, _might_hit_head_WIRE_1_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_1 = {might_hit_head_lo_hi_1, might_hit_head_lo_lo_1}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_1 = {_might_hit_head_WIRE_1_5, _might_hit_head_WIRE_1_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_1 = {_might_hit_head_WIRE_1_7, _might_hit_head_WIRE_1_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_1 = {might_hit_head_hi_hi_1, might_hit_head_hi_lo_1}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_55 = {might_hit_head_hi_1, might_hit_head_lo_1}; // @[fetch-buffer.scala:79:63] wire [20:0] _might_hit_head_T_56 = tail[20:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [2:0] _might_hit_head_T_57 = tail[23:21]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_58 = {_might_hit_head_T_56, _might_hit_head_T_57}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_59 = _might_hit_head_T_58[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_0 = _might_hit_head_T_59; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_60 = _might_hit_head_T_58[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_61 = _might_hit_head_T_58[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_62 = _might_hit_head_T_58[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_1 = _might_hit_head_T_62; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_63 = _might_hit_head_T_58[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_64 = _might_hit_head_T_58[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_65 = _might_hit_head_T_58[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_2 = _might_hit_head_T_65; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_66 = _might_hit_head_T_58[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_67 = _might_hit_head_T_58[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_68 = _might_hit_head_T_58[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_3 = _might_hit_head_T_68; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_69 = _might_hit_head_T_58[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_70 = _might_hit_head_T_58[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_71 = _might_hit_head_T_58[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_4 = _might_hit_head_T_71; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_72 = _might_hit_head_T_58[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_73 = _might_hit_head_T_58[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_74 = _might_hit_head_T_58[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_5 = _might_hit_head_T_74; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_75 = _might_hit_head_T_58[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_76 = _might_hit_head_T_58[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_77 = _might_hit_head_T_58[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_6 = _might_hit_head_T_77; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_78 = _might_hit_head_T_58[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_79 = _might_hit_head_T_58[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_80 = _might_hit_head_T_58[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_7 = _might_hit_head_T_80; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_81 = _might_hit_head_T_58[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_82 = _might_hit_head_T_58[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_2 = {_might_hit_head_WIRE_2_1, _might_hit_head_WIRE_2_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_2 = {_might_hit_head_WIRE_2_3, _might_hit_head_WIRE_2_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_2 = {might_hit_head_lo_hi_2, might_hit_head_lo_lo_2}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_2 = {_might_hit_head_WIRE_2_5, _might_hit_head_WIRE_2_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_2 = {_might_hit_head_WIRE_2_7, _might_hit_head_WIRE_2_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_2 = {might_hit_head_hi_hi_2, might_hit_head_hi_lo_2}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_83 = {might_hit_head_hi_2, might_hit_head_lo_2}; // @[fetch-buffer.scala:79:63] wire [19:0] _might_hit_head_T_84 = tail[19:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [3:0] _might_hit_head_T_85 = tail[23:20]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_86 = {_might_hit_head_T_84, _might_hit_head_T_85}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_87 = _might_hit_head_T_86[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_0 = _might_hit_head_T_87; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_88 = _might_hit_head_T_86[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_89 = _might_hit_head_T_86[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_90 = _might_hit_head_T_86[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_1 = _might_hit_head_T_90; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_91 = _might_hit_head_T_86[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_92 = _might_hit_head_T_86[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_93 = _might_hit_head_T_86[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_2 = _might_hit_head_T_93; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_94 = _might_hit_head_T_86[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_95 = _might_hit_head_T_86[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_96 = _might_hit_head_T_86[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_3 = _might_hit_head_T_96; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_97 = _might_hit_head_T_86[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_98 = _might_hit_head_T_86[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_99 = _might_hit_head_T_86[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_4 = _might_hit_head_T_99; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_100 = _might_hit_head_T_86[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_101 = _might_hit_head_T_86[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_102 = _might_hit_head_T_86[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_5 = _might_hit_head_T_102; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_103 = _might_hit_head_T_86[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_104 = _might_hit_head_T_86[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_105 = _might_hit_head_T_86[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_6 = _might_hit_head_T_105; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_106 = _might_hit_head_T_86[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_107 = _might_hit_head_T_86[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_108 = _might_hit_head_T_86[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3_7 = _might_hit_head_T_108; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_109 = _might_hit_head_T_86[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_110 = _might_hit_head_T_86[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_3 = {_might_hit_head_WIRE_3_1, _might_hit_head_WIRE_3_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_3 = {_might_hit_head_WIRE_3_3, _might_hit_head_WIRE_3_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_3 = {might_hit_head_lo_hi_3, might_hit_head_lo_lo_3}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_3 = {_might_hit_head_WIRE_3_5, _might_hit_head_WIRE_3_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_3 = {_might_hit_head_WIRE_3_7, _might_hit_head_WIRE_3_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_3 = {might_hit_head_hi_hi_3, might_hit_head_hi_lo_3}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_111 = {might_hit_head_hi_3, might_hit_head_lo_3}; // @[fetch-buffer.scala:79:63] wire [18:0] _might_hit_head_T_112 = tail[18:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [4:0] _might_hit_head_T_113 = tail[23:19]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_114 = {_might_hit_head_T_112, _might_hit_head_T_113}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_115 = _might_hit_head_T_114[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_0 = _might_hit_head_T_115; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_116 = _might_hit_head_T_114[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_117 = _might_hit_head_T_114[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_118 = _might_hit_head_T_114[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_1 = _might_hit_head_T_118; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_119 = _might_hit_head_T_114[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_120 = _might_hit_head_T_114[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_121 = _might_hit_head_T_114[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_2 = _might_hit_head_T_121; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_122 = _might_hit_head_T_114[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_123 = _might_hit_head_T_114[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_124 = _might_hit_head_T_114[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_3 = _might_hit_head_T_124; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_125 = _might_hit_head_T_114[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_126 = _might_hit_head_T_114[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_127 = _might_hit_head_T_114[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_4 = _might_hit_head_T_127; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_128 = _might_hit_head_T_114[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_129 = _might_hit_head_T_114[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_130 = _might_hit_head_T_114[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_5 = _might_hit_head_T_130; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_131 = _might_hit_head_T_114[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_132 = _might_hit_head_T_114[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_133 = _might_hit_head_T_114[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_6 = _might_hit_head_T_133; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_134 = _might_hit_head_T_114[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_135 = _might_hit_head_T_114[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_136 = _might_hit_head_T_114[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4_7 = _might_hit_head_T_136; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_137 = _might_hit_head_T_114[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_138 = _might_hit_head_T_114[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_4 = {_might_hit_head_WIRE_4_1, _might_hit_head_WIRE_4_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_4 = {_might_hit_head_WIRE_4_3, _might_hit_head_WIRE_4_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_4 = {might_hit_head_lo_hi_4, might_hit_head_lo_lo_4}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_4 = {_might_hit_head_WIRE_4_5, _might_hit_head_WIRE_4_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_4 = {_might_hit_head_WIRE_4_7, _might_hit_head_WIRE_4_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_4 = {might_hit_head_hi_hi_4, might_hit_head_hi_lo_4}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_139 = {might_hit_head_hi_4, might_hit_head_lo_4}; // @[fetch-buffer.scala:79:63] wire [17:0] _might_hit_head_T_140 = tail[17:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [5:0] _might_hit_head_T_141 = tail[23:18]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_142 = {_might_hit_head_T_140, _might_hit_head_T_141}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_143 = _might_hit_head_T_142[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_0 = _might_hit_head_T_143; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_144 = _might_hit_head_T_142[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_145 = _might_hit_head_T_142[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_146 = _might_hit_head_T_142[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_1 = _might_hit_head_T_146; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_147 = _might_hit_head_T_142[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_148 = _might_hit_head_T_142[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_149 = _might_hit_head_T_142[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_2 = _might_hit_head_T_149; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_150 = _might_hit_head_T_142[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_151 = _might_hit_head_T_142[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_152 = _might_hit_head_T_142[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_3 = _might_hit_head_T_152; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_153 = _might_hit_head_T_142[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_154 = _might_hit_head_T_142[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_155 = _might_hit_head_T_142[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_4 = _might_hit_head_T_155; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_156 = _might_hit_head_T_142[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_157 = _might_hit_head_T_142[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_158 = _might_hit_head_T_142[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_5 = _might_hit_head_T_158; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_159 = _might_hit_head_T_142[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_160 = _might_hit_head_T_142[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_161 = _might_hit_head_T_142[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_6 = _might_hit_head_T_161; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_162 = _might_hit_head_T_142[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_163 = _might_hit_head_T_142[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_164 = _might_hit_head_T_142[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5_7 = _might_hit_head_T_164; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_165 = _might_hit_head_T_142[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_166 = _might_hit_head_T_142[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_5 = {_might_hit_head_WIRE_5_1, _might_hit_head_WIRE_5_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_5 = {_might_hit_head_WIRE_5_3, _might_hit_head_WIRE_5_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_5 = {might_hit_head_lo_hi_5, might_hit_head_lo_lo_5}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_5 = {_might_hit_head_WIRE_5_5, _might_hit_head_WIRE_5_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_5 = {_might_hit_head_WIRE_5_7, _might_hit_head_WIRE_5_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_5 = {might_hit_head_hi_hi_5, might_hit_head_hi_lo_5}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_167 = {might_hit_head_hi_5, might_hit_head_lo_5}; // @[fetch-buffer.scala:79:63] wire [16:0] _might_hit_head_T_168 = tail[16:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [6:0] _might_hit_head_T_169 = tail[23:17]; // @[fetch-buffer.scala:62:21, :75:24] wire [23:0] _might_hit_head_T_170 = {_might_hit_head_T_168, _might_hit_head_T_169}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_171 = _might_hit_head_T_170[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_0 = _might_hit_head_T_171; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_172 = _might_hit_head_T_170[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_173 = _might_hit_head_T_170[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_174 = _might_hit_head_T_170[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_1 = _might_hit_head_T_174; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_175 = _might_hit_head_T_170[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_176 = _might_hit_head_T_170[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_177 = _might_hit_head_T_170[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_2 = _might_hit_head_T_177; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_178 = _might_hit_head_T_170[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_179 = _might_hit_head_T_170[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_180 = _might_hit_head_T_170[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_3 = _might_hit_head_T_180; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_181 = _might_hit_head_T_170[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_182 = _might_hit_head_T_170[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_183 = _might_hit_head_T_170[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_4 = _might_hit_head_T_183; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_184 = _might_hit_head_T_170[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_185 = _might_hit_head_T_170[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_186 = _might_hit_head_T_170[15]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_5 = _might_hit_head_T_186; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_187 = _might_hit_head_T_170[16]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_188 = _might_hit_head_T_170[17]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_189 = _might_hit_head_T_170[18]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_6 = _might_hit_head_T_189; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_190 = _might_hit_head_T_170[19]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_191 = _might_hit_head_T_170[20]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_192 = _might_hit_head_T_170[21]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6_7 = _might_hit_head_T_192; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_193 = _might_hit_head_T_170[22]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_194 = _might_hit_head_T_170[23]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_6 = {_might_hit_head_WIRE_6_1, _might_hit_head_WIRE_6_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_6 = {_might_hit_head_WIRE_6_3, _might_hit_head_WIRE_6_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_6 = {might_hit_head_lo_hi_6, might_hit_head_lo_lo_6}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_6 = {_might_hit_head_WIRE_6_5, _might_hit_head_WIRE_6_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_6 = {_might_hit_head_WIRE_6_7, _might_hit_head_WIRE_6_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_6 = {might_hit_head_hi_hi_6, might_hit_head_hi_lo_6}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_195 = {might_hit_head_hi_6, might_hit_head_lo_6}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_196 = head & _might_hit_head_T_27; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_197 = head & _might_hit_head_T_55; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_198 = head & _might_hit_head_T_83; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_199 = head & _might_hit_head_T_111; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_200 = head & _might_hit_head_T_139; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_201 = head & _might_hit_head_T_167; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_202 = head & _might_hit_head_T_195; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_203 = _might_hit_head_T_196 | _might_hit_head_T_197; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_204 = _might_hit_head_T_203 | _might_hit_head_T_198; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_205 = _might_hit_head_T_204 | _might_hit_head_T_199; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_206 = _might_hit_head_T_205 | _might_hit_head_T_200; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_207 = _might_hit_head_T_206 | _might_hit_head_T_201; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_208 = _might_hit_head_T_207 | _might_hit_head_T_202; // @[fetch-buffer.scala:79:{88,104}] wire might_hit_head = |_might_hit_head_T_208; // @[fetch-buffer.scala:79:{104,108}] wire _at_head_T = tail[0]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_0 = _at_head_T; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_1 = tail[1]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_2 = tail[2]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_3 = tail[3]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_1 = _at_head_T_3; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_4 = tail[4]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_5 = tail[5]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_6 = tail[6]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_2 = _at_head_T_6; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_7 = tail[7]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_8 = tail[8]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_9 = tail[9]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_3 = _at_head_T_9; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_10 = tail[10]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_11 = tail[11]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_12 = tail[12]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_4 = _at_head_T_12; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_13 = tail[13]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_14 = tail[14]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_15 = tail[15]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_5 = _at_head_T_15; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_16 = tail[16]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_17 = tail[17]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_18 = tail[18]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_6 = _at_head_T_18; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_19 = tail[19]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_20 = tail[20]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_21 = tail[21]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_7 = _at_head_T_21; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_22 = tail[22]; // @[fetch-buffer.scala:62:21, :80:31] wire [1:0] at_head_lo_lo = {_at_head_WIRE_1, _at_head_WIRE_0}; // @[fetch-buffer.scala:80:25, :81:29] wire [1:0] at_head_lo_hi = {_at_head_WIRE_3, _at_head_WIRE_2}; // @[fetch-buffer.scala:80:25, :81:29] wire [3:0] at_head_lo = {at_head_lo_hi, at_head_lo_lo}; // @[fetch-buffer.scala:81:29] wire [1:0] at_head_hi_lo = {_at_head_WIRE_5, _at_head_WIRE_4}; // @[fetch-buffer.scala:80:25, :81:29] wire [1:0] at_head_hi_hi = {_at_head_WIRE_7, _at_head_WIRE_6}; // @[fetch-buffer.scala:80:25, :81:29] wire [3:0] at_head_hi = {at_head_hi_hi, at_head_hi_lo}; // @[fetch-buffer.scala:81:29] wire [7:0] _at_head_T_24 = {at_head_hi, at_head_lo}; // @[fetch-buffer.scala:81:29] wire [7:0] _at_head_T_25 = _at_head_T_24 & head; // @[fetch-buffer.scala:61:21, :81:{29,36}] wire at_head = |_at_head_T_25; // @[fetch-buffer.scala:81:{36,44}] wire _do_enq_T = at_head & maybe_full; // @[fetch-buffer.scala:64:27, :81:44, :82:26] wire _do_enq_T_1 = _do_enq_T | might_hit_head; // @[fetch-buffer.scala:79:108, :82:{26,40}] assign do_enq = ~_do_enq_T_1; // @[fetch-buffer.scala:82:{16,40}] assign io_enq_ready_0 = do_enq; // @[fetch-buffer.scala:40:7, :82:16] wire _in_mask_0_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_1_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_2_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_3_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_4_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_5_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_6_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_7_T_1; // @[fetch-buffer.scala:98:49] wire in_mask_0; // @[fetch-buffer.scala:87:21] wire in_mask_1; // @[fetch-buffer.scala:87:21] wire in_mask_2; // @[fetch-buffer.scala:87:21] wire in_mask_3; // @[fetch-buffer.scala:87:21] wire in_mask_4; // @[fetch-buffer.scala:87:21] wire in_mask_5; // @[fetch-buffer.scala:87:21] wire in_mask_6; // @[fetch-buffer.scala:87:21] wire in_mask_7; // @[fetch-buffer.scala:87:21] wire _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_0_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_1; // @[fetch-buffer.scala:95:43] wire _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_1_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_2; // @[fetch-buffer.scala:95:43] wire _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_2_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_3; // @[fetch-buffer.scala:95:43] wire _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_3_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_4_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire _in_uops_4_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_4_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_5_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_5; // @[fetch-buffer.scala:95:43] wire _in_uops_5_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_5_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_6_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_6; // @[fetch-buffer.scala:95:43] wire _in_uops_6_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_6_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_7_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_7; // @[fetch-buffer.scala:95:43] wire _in_uops_7_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_7_taken_T_1; // @[fetch-buffer.scala:116:69] wire in_uops_0_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_0_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_0_taken; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_1_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_1_taken; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_2_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_2_taken; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_3_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_3_taken; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_4_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_4_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_4_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_4_taken; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_5_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_5_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_5_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_5_taken; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_6_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_6_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_6_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_6_taken; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_7_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_7_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_7_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_7_taken; // @[fetch-buffer.scala:88:21] wire [39:0] _pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_1 = {_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_2 = ~_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_3 = {1'h0, _pc_T_2}; // @[frontend.scala:147:31] wire [39:0] pc = _pc_T_3[39:0]; // @[fetch-buffer.scala:95:43] wire _in_mask_0_T = io_enq_bits_mask_0[0]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_0_T_1 = io_enq_valid_0 & _in_mask_0_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_0 = _in_mask_0_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign _in_uops_0_is_sfb_T = io_enq_bits_sfbs_0_0 | io_enq_bits_shadowed_mask_0_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_0_is_sfb = _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [39:0] _in_uops_0_debug_pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_0_debug_pc_T_1 = {_in_uops_0_debug_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_0_debug_pc_T_2 = ~_in_uops_0_debug_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_0_debug_pc_T_3 = {1'h0, _in_uops_0_debug_pc_T_2}; // @[frontend.scala:147:31] wire [39:0] _in_uops_0_debug_pc_T_4 = _in_uops_0_debug_pc_T_3[39:0]; // @[fetch-buffer.scala:107:61] wire [40:0] _in_uops_0_debug_pc_T_5 = {1'h0, _in_uops_0_debug_pc_T_4} - 41'h2; // @[fetch-buffer.scala:107:{61,81}] wire [39:0] _in_uops_0_debug_pc_T_6 = _in_uops_0_debug_pc_T_5[39:0]; // @[fetch-buffer.scala:107:81] assign in_uops_0_debug_pc = io_enq_bits_edge_inst_0_0 ? _in_uops_0_debug_pc_T_6 : pc; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :100:33, :106:41, :107:{32,81}] wire [39:0] _in_uops_0_pc_lob_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_0_pc_lob_T_1 = {_in_uops_0_pc_lob_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_0_pc_lob_T_2 = ~_in_uops_0_pc_lob_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_0_pc_lob_T_3 = {1'h0, _in_uops_0_pc_lob_T_2}; // @[frontend.scala:147:31] wire [39:0] _in_uops_0_pc_lob_T_4 = _in_uops_0_pc_lob_T_3[39:0]; // @[fetch-buffer.scala:108:61] assign in_uops_0_pc_lob = io_enq_bits_edge_inst_0_0 ? _in_uops_0_pc_lob_T_4[5:0] : pc[5:0]; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :101:33, :106:41, :108:{32,61}] wire [1:0] _in_uops_0_is_rvc_T = io_enq_bits_insts_0_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_0_is_rvc_T_1 = _in_uops_0_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_0_is_rvc = _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_0_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h0; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_0_taken_T_1 = _in_uops_0_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_0_taken = _in_uops_0_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_4 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_5 = {_pc_T_4[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_6 = ~_pc_T_5; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_7 = {1'h0, _pc_T_6} + 41'h2; // @[frontend.scala:147:31] assign pc_1 = _pc_T_7[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_1_debug_pc = pc_1; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_1_T = io_enq_bits_mask_0[1]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_1_T_1 = io_enq_valid_0 & _in_mask_1_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_1 = _in_mask_1_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_1_pc_lob = pc_1[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_1_is_sfb_T = io_enq_bits_sfbs_1_0 | io_enq_bits_shadowed_mask_1_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_1_is_sfb = _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_1_is_rvc_T = io_enq_bits_insts_1_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_1_is_rvc_T_1 = _in_uops_1_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_1_is_rvc = _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_1_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h1; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_1_taken_T_1 = _in_uops_1_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_1_taken = _in_uops_1_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_8 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_9 = {_pc_T_8[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_10 = ~_pc_T_9; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_11 = {1'h0, _pc_T_10} + 41'h4; // @[frontend.scala:147:31] assign pc_2 = _pc_T_11[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_2_debug_pc = pc_2; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_2_T = io_enq_bits_mask_0[2]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_2_T_1 = io_enq_valid_0 & _in_mask_2_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_2 = _in_mask_2_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_2_pc_lob = pc_2[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_2_is_sfb_T = io_enq_bits_sfbs_2_0 | io_enq_bits_shadowed_mask_2_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_2_is_sfb = _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_2_is_rvc_T = io_enq_bits_insts_2_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_2_is_rvc_T_1 = _in_uops_2_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_2_is_rvc = _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_2_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h2; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_2_taken_T_1 = _in_uops_2_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_2_taken = _in_uops_2_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_12 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_13 = {_pc_T_12[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_14 = ~_pc_T_13; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_15 = {1'h0, _pc_T_14} + 41'h6; // @[frontend.scala:147:31] assign pc_3 = _pc_T_15[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_3_debug_pc = pc_3; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_3_T = io_enq_bits_mask_0[3]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_3_T_1 = io_enq_valid_0 & _in_mask_3_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_3 = _in_mask_3_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_3_pc_lob = pc_3[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_3_is_sfb_T = io_enq_bits_sfbs_3_0 | io_enq_bits_shadowed_mask_3_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_3_is_sfb = _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_3_is_rvc_T = io_enq_bits_insts_3_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_3_is_rvc_T_1 = _in_uops_3_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_3_is_rvc = _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_3_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h3; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_3_taken_T_1 = _in_uops_3_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_3_taken = _in_uops_3_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_16 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_17 = {_pc_T_16[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_18 = ~_pc_T_17; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_19 = {1'h0, _pc_T_18} + 41'h8; // @[frontend.scala:147:31] wire [39:0] pc_4 = _pc_T_19[39:0]; // @[fetch-buffer.scala:95:43] wire _in_mask_4_T = io_enq_bits_mask_0[4]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_4_T_1 = io_enq_valid_0 & _in_mask_4_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_4 = _in_mask_4_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign _in_uops_4_is_sfb_T = io_enq_bits_sfbs_4_0 | io_enq_bits_shadowed_mask_4_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_4_is_sfb = _in_uops_4_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [39:0] _in_uops_4_debug_pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_4_debug_pc_T_1 = {_in_uops_4_debug_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_4_debug_pc_T_2 = ~_in_uops_4_debug_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_4_debug_pc_T_3 = {1'h0, _in_uops_4_debug_pc_T_2} + 41'h8; // @[frontend.scala:147:31] wire [39:0] _in_uops_4_debug_pc_T_4 = _in_uops_4_debug_pc_T_3[39:0]; // @[fetch-buffer.scala:107:61] wire [40:0] _in_uops_4_debug_pc_T_5 = {1'h0, _in_uops_4_debug_pc_T_4} - 41'h2; // @[fetch-buffer.scala:107:{61,81}] wire [39:0] _in_uops_4_debug_pc_T_6 = _in_uops_4_debug_pc_T_5[39:0]; // @[fetch-buffer.scala:107:81] assign in_uops_4_debug_pc = io_enq_bits_edge_inst_1_0 ? _in_uops_4_debug_pc_T_6 : pc_4; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :100:33, :106:41, :107:{32,81}] wire [39:0] _in_uops_4_pc_lob_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_4_pc_lob_T_1 = {_in_uops_4_pc_lob_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_4_pc_lob_T_2 = ~_in_uops_4_pc_lob_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_4_pc_lob_T_3 = {1'h0, _in_uops_4_pc_lob_T_2} + 41'h8; // @[frontend.scala:147:31] wire [39:0] _in_uops_4_pc_lob_T_4 = _in_uops_4_pc_lob_T_3[39:0]; // @[fetch-buffer.scala:108:61] assign in_uops_4_pc_lob = io_enq_bits_edge_inst_1_0 ? _in_uops_4_pc_lob_T_4[5:0] : pc_4[5:0]; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :101:33, :106:41, :108:{32,61}] wire [1:0] _in_uops_4_is_rvc_T = io_enq_bits_insts_4_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_4_is_rvc_T_1 = _in_uops_4_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_4_is_rvc = _in_uops_4_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_4_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h4; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_4_taken_T_1 = _in_uops_4_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_4_taken = _in_uops_4_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_20 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_21 = {_pc_T_20[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_22 = ~_pc_T_21; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_23 = {1'h0, _pc_T_22} + 41'hA; // @[frontend.scala:147:31] assign pc_5 = _pc_T_23[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_5_debug_pc = pc_5; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_5_T = io_enq_bits_mask_0[5]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_5_T_1 = io_enq_valid_0 & _in_mask_5_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_5 = _in_mask_5_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_5_pc_lob = pc_5[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_5_is_sfb_T = io_enq_bits_sfbs_5_0 | io_enq_bits_shadowed_mask_5_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_5_is_sfb = _in_uops_5_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_5_is_rvc_T = io_enq_bits_insts_5_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_5_is_rvc_T_1 = _in_uops_5_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_5_is_rvc = _in_uops_5_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_5_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h5; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_5_taken_T_1 = _in_uops_5_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_5_taken = _in_uops_5_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_24 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_25 = {_pc_T_24[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_26 = ~_pc_T_25; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_27 = {1'h0, _pc_T_26} + 41'hC; // @[frontend.scala:147:31] assign pc_6 = _pc_T_27[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_6_debug_pc = pc_6; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_6_T = io_enq_bits_mask_0[6]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_6_T_1 = io_enq_valid_0 & _in_mask_6_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_6 = _in_mask_6_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_6_pc_lob = pc_6[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_6_is_sfb_T = io_enq_bits_sfbs_6_0 | io_enq_bits_shadowed_mask_6_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_6_is_sfb = _in_uops_6_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_6_is_rvc_T = io_enq_bits_insts_6_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_6_is_rvc_T_1 = _in_uops_6_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_6_is_rvc = _in_uops_6_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_6_taken_T = io_enq_bits_cfi_idx_bits_0 == 3'h6; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_6_taken_T_1 = _in_uops_6_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_6_taken = _in_uops_6_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_28 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_29 = {_pc_T_28[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_30 = ~_pc_T_29; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_31 = {1'h0, _pc_T_30} + 41'hE; // @[frontend.scala:147:31] assign pc_7 = _pc_T_31[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_7_debug_pc = pc_7; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_7_T = io_enq_bits_mask_0[7]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_7_T_1 = io_enq_valid_0 & _in_mask_7_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_7 = _in_mask_7_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_7_pc_lob = pc_7[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_7_is_sfb_T = io_enq_bits_sfbs_7_0 | io_enq_bits_shadowed_mask_7_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_7_is_sfb = _in_uops_7_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_7_is_rvc_T = io_enq_bits_insts_7_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_7_is_rvc_T_1 = _in_uops_7_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_7_is_rvc = _in_uops_7_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_7_taken_T = &io_enq_bits_cfi_idx_bits_0; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_7_taken_T_1 = _in_uops_7_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_7_taken = _in_uops_7_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [23:0] enq_idxs_1; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_2; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_3; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_4; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_5; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_6; // @[fetch-buffer.scala:128:22] wire [23:0] enq_idxs_7; // @[fetch-buffer.scala:128:22] wire [23:0] _T_2 = {_might_hit_head_T, tail[23]}; // @[fetch-buffer.scala:62:21, :75:{11,24}, :132:8] assign enq_idxs_1 = in_mask_0 ? _T_2 : tail; // @[fetch-buffer.scala:62:21, :87:21, :128:22, :132:8, :138:18] wire [23:0] _T_6 = {enq_idxs_1[22:0], enq_idxs_1[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_2 = in_mask_1 ? _T_6 : enq_idxs_1; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_10 = {enq_idxs_2[22:0], enq_idxs_2[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_3 = in_mask_2 ? _T_10 : enq_idxs_2; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_14 = {enq_idxs_3[22:0], enq_idxs_3[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_4 = in_mask_3 ? _T_14 : enq_idxs_3; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_18 = {enq_idxs_4[22:0], enq_idxs_4[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_5 = in_mask_4 ? _T_18 : enq_idxs_4; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_22 = {enq_idxs_5[22:0], enq_idxs_5[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_6 = in_mask_5 ? _T_22 : enq_idxs_5; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [23:0] _T_26 = {enq_idxs_6[22:0], enq_idxs_6[23]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_7 = in_mask_6 ? _T_26 : enq_idxs_6; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire _tail_collisions_T = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_4 = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_8 = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_1 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_2 = _tail_collisions_T_1; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_3 = _tail_collisions_T & _tail_collisions_T_2; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_0 = _tail_collisions_T_3; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_7 = _tail_collisions_T_4; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_5 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_1 = _tail_collisions_T_7; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_11 = _tail_collisions_T_8; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_9 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_2 = _tail_collisions_T_11; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_12 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_16 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_20 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_13 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_14 = _tail_collisions_T_13; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_15 = _tail_collisions_T_12 & _tail_collisions_T_14; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_3 = _tail_collisions_T_15; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_19 = _tail_collisions_T_16; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_17 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_4 = _tail_collisions_T_19; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_23 = _tail_collisions_T_20; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_21 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_5 = _tail_collisions_T_23; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_24 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_28 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_32 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_25 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_26 = _tail_collisions_T_25; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_27 = _tail_collisions_T_24 & _tail_collisions_T_26; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_6 = _tail_collisions_T_27; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_31 = _tail_collisions_T_28; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_29 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_7 = _tail_collisions_T_31; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_35 = _tail_collisions_T_32; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_33 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_8 = _tail_collisions_T_35; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_36 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_40 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_44 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_37 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_38 = _tail_collisions_T_37; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_39 = _tail_collisions_T_36 & _tail_collisions_T_38; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_9 = _tail_collisions_T_39; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_43 = _tail_collisions_T_40; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_41 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_10 = _tail_collisions_T_43; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_47 = _tail_collisions_T_44; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_45 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_11 = _tail_collisions_T_47; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_48 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_52 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_56 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_49 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_50 = _tail_collisions_T_49; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_51 = _tail_collisions_T_48 & _tail_collisions_T_50; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_12 = _tail_collisions_T_51; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_55 = _tail_collisions_T_52; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_53 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_13 = _tail_collisions_T_55; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_59 = _tail_collisions_T_56; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_57 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_14 = _tail_collisions_T_59; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_60 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_64 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_68 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_61 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_62 = _tail_collisions_T_61; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_63 = _tail_collisions_T_60 & _tail_collisions_T_62; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_15 = _tail_collisions_T_63; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_67 = _tail_collisions_T_64; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_65 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_16 = _tail_collisions_T_67; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_71 = _tail_collisions_T_68; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_69 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_17 = _tail_collisions_T_71; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_72 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_76 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_80 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_73 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_74 = _tail_collisions_T_73; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_75 = _tail_collisions_T_72 & _tail_collisions_T_74; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_18 = _tail_collisions_T_75; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_79 = _tail_collisions_T_76; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_77 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_19 = _tail_collisions_T_79; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_83 = _tail_collisions_T_80; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_81 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_20 = _tail_collisions_T_83; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_84 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_88 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_92 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _head_T_1 = head[7]; // @[fetch-buffer.scala:61:21, :132:24, :155:31] wire _tail_collisions_T_85 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_86 = _tail_collisions_T_85; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_87 = _tail_collisions_T_84 & _tail_collisions_T_86; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_21 = _tail_collisions_T_87; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_91 = _tail_collisions_T_88; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_89 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_22 = _tail_collisions_T_91; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_95 = _tail_collisions_T_92; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_93 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_23 = _tail_collisions_T_95; // @[fetch-buffer.scala:154:32, :155:45] wire [1:0] tail_collisions_lo_lo_lo_hi = {_tail_collisions_WIRE_2, _tail_collisions_WIRE_1}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_lo_lo = {tail_collisions_lo_lo_lo_hi, _tail_collisions_WIRE_0}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_lo_lo_hi_hi = {_tail_collisions_WIRE_5, _tail_collisions_WIRE_4}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_lo_hi = {tail_collisions_lo_lo_hi_hi, _tail_collisions_WIRE_3}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_lo_lo = {tail_collisions_lo_lo_hi, tail_collisions_lo_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_lo_hi_lo_hi = {_tail_collisions_WIRE_8, _tail_collisions_WIRE_7}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_hi_lo = {tail_collisions_lo_hi_lo_hi, _tail_collisions_WIRE_6}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_lo_hi_hi_hi = {_tail_collisions_WIRE_11, _tail_collisions_WIRE_10}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_lo_hi_hi = {tail_collisions_lo_hi_hi_hi, _tail_collisions_WIRE_9}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_lo_hi = {tail_collisions_lo_hi_hi, tail_collisions_lo_hi_lo}; // @[fetch-buffer.scala:155:90] wire [11:0] tail_collisions_lo = {tail_collisions_lo_hi, tail_collisions_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_hi_lo_lo_hi = {_tail_collisions_WIRE_14, _tail_collisions_WIRE_13}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_lo_lo = {tail_collisions_hi_lo_lo_hi, _tail_collisions_WIRE_12}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_hi_lo_hi_hi = {_tail_collisions_WIRE_17, _tail_collisions_WIRE_16}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_lo_hi = {tail_collisions_hi_lo_hi_hi, _tail_collisions_WIRE_15}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_hi_lo = {tail_collisions_hi_lo_hi, tail_collisions_hi_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_hi_hi_lo_hi = {_tail_collisions_WIRE_20, _tail_collisions_WIRE_19}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_hi_lo = {tail_collisions_hi_hi_lo_hi, _tail_collisions_WIRE_18}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_hi_hi_hi_hi = {_tail_collisions_WIRE_23, _tail_collisions_WIRE_22}; // @[fetch-buffer.scala:154:32, :155:90] wire [2:0] tail_collisions_hi_hi_hi = {tail_collisions_hi_hi_hi_hi, _tail_collisions_WIRE_21}; // @[fetch-buffer.scala:154:32, :155:90] wire [5:0] tail_collisions_hi_hi = {tail_collisions_hi_hi_hi, tail_collisions_hi_hi_lo}; // @[fetch-buffer.scala:155:90] wire [11:0] tail_collisions_hi = {tail_collisions_hi_hi, tail_collisions_hi_lo}; // @[fetch-buffer.scala:155:90] wire [23:0] _tail_collisions_T_96 = {tail_collisions_hi, tail_collisions_lo}; // @[fetch-buffer.scala:155:90] wire [23:0] tail_collisions = _tail_collisions_T_96 & tail; // @[fetch-buffer.scala:62:21, :155:{90,97}] wire [2:0] _slot_will_hit_tail_T = tail_collisions[2:0]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_1 = tail_collisions[5:3]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_2 = tail_collisions[8:6]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_3 = tail_collisions[11:9]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_4 = tail_collisions[14:12]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_5 = tail_collisions[17:15]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_6 = tail_collisions[20:18]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_7 = tail_collisions[23:21]; // @[fetch-buffer.scala:155:97, :156:70] wire [2:0] _slot_will_hit_tail_T_8 = _slot_will_hit_tail_T | _slot_will_hit_tail_T_1; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_9 = _slot_will_hit_tail_T_8 | _slot_will_hit_tail_T_2; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_10 = _slot_will_hit_tail_T_9 | _slot_will_hit_tail_T_3; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_11 = _slot_will_hit_tail_T_10 | _slot_will_hit_tail_T_4; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_12 = _slot_will_hit_tail_T_11 | _slot_will_hit_tail_T_5; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] _slot_will_hit_tail_T_13 = _slot_will_hit_tail_T_12 | _slot_will_hit_tail_T_6; // @[fetch-buffer.scala:156:{70,112}] wire [2:0] slot_will_hit_tail = _slot_will_hit_tail_T_13 | _slot_will_hit_tail_T_7; // @[fetch-buffer.scala:156:{70,112}] wire will_hit_tail = |slot_will_hit_tail; // @[fetch-buffer.scala:156:112, :157:42] wire _do_deq_T = ~will_hit_tail; // @[fetch-buffer.scala:157:42, :159:32] wire do_deq = io_deq_ready_0 & _do_deq_T; // @[fetch-buffer.scala:40:7, :159:{29,32}] wire [3:0] _deq_valids_T = {1'h0, slot_will_hit_tail}; // @[util.scala:394:30] wire [2:0] _deq_valids_T_1 = _deq_valids_T[2:0]; // @[util.scala:394:{30,37}] wire [3:0] _deq_valids_T_2 = {slot_will_hit_tail, 1'h0}; // @[util.scala:394:30] wire [2:0] _deq_valids_T_3 = _deq_valids_T_2[2:0]; // @[util.scala:394:{30,37}] wire [5:0] _deq_valids_T_4 = {1'h0, slot_will_hit_tail, 2'h0}; // @[util.scala:394:30] wire [2:0] _deq_valids_T_5 = _deq_valids_T_4[2:0]; // @[util.scala:394:{30,37}] wire [2:0] _deq_valids_T_6 = _deq_valids_T_1 | _deq_valids_T_3; // @[util.scala:394:{37,54}] wire [2:0] _deq_valids_T_7 = _deq_valids_T_6 | _deq_valids_T_5; // @[util.scala:394:{37,54}] wire [2:0] _deq_valids_T_8 = ~_deq_valids_T_7; // @[util.scala:394:54] wire deq_valids_0 = _deq_valids_T_8[0]; // @[fetch-buffer.scala:161:{21,53}] wire deq_valids_1 = _deq_valids_T_8[1]; // @[fetch-buffer.scala:161:{21,53}] wire deq_valids_2 = _deq_valids_T_8[2]; // @[fetch-buffer.scala:161:{21,53}] assign io_deq_bits_uops_0_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_0_debug_fsrc : 3'h0) | (head[1] ? deq_vec_1_0_debug_fsrc : 3'h0) | (head[2] ? deq_vec_2_0_debug_fsrc : 3'h0) | (head[3] ? deq_vec_3_0_debug_fsrc : 3'h0) | (head[4] ? deq_vec_4_0_debug_fsrc : 3'h0) | (head[5] ? deq_vec_5_0_debug_fsrc : 3'h0) | (head[6] ? deq_vec_6_0_debug_fsrc : 3'h0) | (head[7] ? deq_vec_7_0_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_0_bp_xcpt_if | head[1] & deq_vec_1_0_bp_xcpt_if | head[2] & deq_vec_2_0_bp_xcpt_if | head[3] & deq_vec_3_0_bp_xcpt_if | head[4] & deq_vec_4_0_bp_xcpt_if | head[5] & deq_vec_5_0_bp_xcpt_if | head[6] & deq_vec_6_0_bp_xcpt_if | head[7] & deq_vec_7_0_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_bp_debug_if_0 = head[0] & deq_vec_0_0_bp_debug_if | head[1] & deq_vec_1_0_bp_debug_if | head[2] & deq_vec_2_0_bp_debug_if | head[3] & deq_vec_3_0_bp_debug_if | head[4] & deq_vec_4_0_bp_debug_if | head[5] & deq_vec_5_0_bp_debug_if | head[6] & deq_vec_6_0_bp_debug_if | head[7] & deq_vec_7_0_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_0_xcpt_ae_if | head[1] & deq_vec_1_0_xcpt_ae_if | head[2] & deq_vec_2_0_xcpt_ae_if | head[3] & deq_vec_3_0_xcpt_ae_if | head[4] & deq_vec_4_0_xcpt_ae_if | head[5] & deq_vec_5_0_xcpt_ae_if | head[6] & deq_vec_6_0_xcpt_ae_if | head[7] & deq_vec_7_0_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_0_xcpt_pf_if | head[1] & deq_vec_1_0_xcpt_pf_if | head[2] & deq_vec_2_0_xcpt_pf_if | head[3] & deq_vec_3_0_xcpt_pf_if | head[4] & deq_vec_4_0_xcpt_pf_if | head[5] & deq_vec_5_0_xcpt_pf_if | head[6] & deq_vec_6_0_xcpt_pf_if | head[7] & deq_vec_7_0_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_taken_0 = head[0] & deq_vec_0_0_taken | head[1] & deq_vec_1_0_taken | head[2] & deq_vec_2_0_taken | head[3] & deq_vec_3_0_taken | head[4] & deq_vec_4_0_taken | head[5] & deq_vec_5_0_taken | head[6] & deq_vec_6_0_taken | head[7] & deq_vec_7_0_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_pc_lob_0 = (head[0] ? deq_vec_0_0_pc_lob : 6'h0) | (head[1] ? deq_vec_1_0_pc_lob : 6'h0) | (head[2] ? deq_vec_2_0_pc_lob : 6'h0) | (head[3] ? deq_vec_3_0_pc_lob : 6'h0) | (head[4] ? deq_vec_4_0_pc_lob : 6'h0) | (head[5] ? deq_vec_5_0_pc_lob : 6'h0) | (head[6] ? deq_vec_6_0_pc_lob : 6'h0) | (head[7] ? deq_vec_7_0_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_edge_inst_0 = head[0] & deq_vec_0_0_edge_inst | head[1] & deq_vec_1_0_edge_inst | head[2] & deq_vec_2_0_edge_inst | head[3] & deq_vec_3_0_edge_inst | head[4] & deq_vec_4_0_edge_inst | head[5] & deq_vec_5_0_edge_inst | head[6] & deq_vec_6_0_edge_inst | head[7] & deq_vec_7_0_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_ftq_idx_0 = (head[0] ? deq_vec_0_0_ftq_idx : 5'h0) | (head[1] ? deq_vec_1_0_ftq_idx : 5'h0) | (head[2] ? deq_vec_2_0_ftq_idx : 5'h0) | (head[3] ? deq_vec_3_0_ftq_idx : 5'h0) | (head[4] ? deq_vec_4_0_ftq_idx : 5'h0) | (head[5] ? deq_vec_5_0_ftq_idx : 5'h0) | (head[6] ? deq_vec_6_0_ftq_idx : 5'h0) | (head[7] ? deq_vec_7_0_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_is_sfb_0 = head[0] & deq_vec_0_0_is_sfb | head[1] & deq_vec_1_0_is_sfb | head[2] & deq_vec_2_0_is_sfb | head[3] & deq_vec_3_0_is_sfb | head[4] & deq_vec_4_0_is_sfb | head[5] & deq_vec_5_0_is_sfb | head[6] & deq_vec_6_0_is_sfb | head[7] & deq_vec_7_0_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_debug_pc_0 = (head[0] ? deq_vec_0_0_debug_pc : 40'h0) | (head[1] ? deq_vec_1_0_debug_pc : 40'h0) | (head[2] ? deq_vec_2_0_debug_pc : 40'h0) | (head[3] ? deq_vec_3_0_debug_pc : 40'h0) | (head[4] ? deq_vec_4_0_debug_pc : 40'h0) | (head[5] ? deq_vec_5_0_debug_pc : 40'h0) | (head[6] ? deq_vec_6_0_debug_pc : 40'h0) | (head[7] ? deq_vec_7_0_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_is_rvc_0 = head[0] & deq_vec_0_0_is_rvc | head[1] & deq_vec_1_0_is_rvc | head[2] & deq_vec_2_0_is_rvc | head[3] & deq_vec_3_0_is_rvc | head[4] & deq_vec_4_0_is_rvc | head[5] & deq_vec_5_0_is_rvc | head[6] & deq_vec_6_0_is_rvc | head[7] & deq_vec_7_0_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_debug_inst_0 = (head[0] ? deq_vec_0_0_debug_inst : 32'h0) | (head[1] ? deq_vec_1_0_debug_inst : 32'h0) | (head[2] ? deq_vec_2_0_debug_inst : 32'h0) | (head[3] ? deq_vec_3_0_debug_inst : 32'h0) | (head[4] ? deq_vec_4_0_debug_inst : 32'h0) | (head[5] ? deq_vec_5_0_debug_inst : 32'h0) | (head[6] ? deq_vec_6_0_debug_inst : 32'h0) | (head[7] ? deq_vec_7_0_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_inst_0 = (head[0] ? deq_vec_0_0_inst : 32'h0) | (head[1] ? deq_vec_1_0_inst : 32'h0) | (head[2] ? deq_vec_2_0_inst : 32'h0) | (head[3] ? deq_vec_3_0_inst : 32'h0) | (head[4] ? deq_vec_4_0_inst : 32'h0) | (head[5] ? deq_vec_5_0_inst : 32'h0) | (head[6] ? deq_vec_6_0_inst : 32'h0) | (head[7] ? deq_vec_7_0_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_1_debug_fsrc : 3'h0) | (head[1] ? deq_vec_1_1_debug_fsrc : 3'h0) | (head[2] ? deq_vec_2_1_debug_fsrc : 3'h0) | (head[3] ? deq_vec_3_1_debug_fsrc : 3'h0) | (head[4] ? deq_vec_4_1_debug_fsrc : 3'h0) | (head[5] ? deq_vec_5_1_debug_fsrc : 3'h0) | (head[6] ? deq_vec_6_1_debug_fsrc : 3'h0) | (head[7] ? deq_vec_7_1_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_1_bp_xcpt_if | head[1] & deq_vec_1_1_bp_xcpt_if | head[2] & deq_vec_2_1_bp_xcpt_if | head[3] & deq_vec_3_1_bp_xcpt_if | head[4] & deq_vec_4_1_bp_xcpt_if | head[5] & deq_vec_5_1_bp_xcpt_if | head[6] & deq_vec_6_1_bp_xcpt_if | head[7] & deq_vec_7_1_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_bp_debug_if_0 = head[0] & deq_vec_0_1_bp_debug_if | head[1] & deq_vec_1_1_bp_debug_if | head[2] & deq_vec_2_1_bp_debug_if | head[3] & deq_vec_3_1_bp_debug_if | head[4] & deq_vec_4_1_bp_debug_if | head[5] & deq_vec_5_1_bp_debug_if | head[6] & deq_vec_6_1_bp_debug_if | head[7] & deq_vec_7_1_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_1_xcpt_ae_if | head[1] & deq_vec_1_1_xcpt_ae_if | head[2] & deq_vec_2_1_xcpt_ae_if | head[3] & deq_vec_3_1_xcpt_ae_if | head[4] & deq_vec_4_1_xcpt_ae_if | head[5] & deq_vec_5_1_xcpt_ae_if | head[6] & deq_vec_6_1_xcpt_ae_if | head[7] & deq_vec_7_1_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_1_xcpt_pf_if | head[1] & deq_vec_1_1_xcpt_pf_if | head[2] & deq_vec_2_1_xcpt_pf_if | head[3] & deq_vec_3_1_xcpt_pf_if | head[4] & deq_vec_4_1_xcpt_pf_if | head[5] & deq_vec_5_1_xcpt_pf_if | head[6] & deq_vec_6_1_xcpt_pf_if | head[7] & deq_vec_7_1_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_taken_0 = head[0] & deq_vec_0_1_taken | head[1] & deq_vec_1_1_taken | head[2] & deq_vec_2_1_taken | head[3] & deq_vec_3_1_taken | head[4] & deq_vec_4_1_taken | head[5] & deq_vec_5_1_taken | head[6] & deq_vec_6_1_taken | head[7] & deq_vec_7_1_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_pc_lob_0 = (head[0] ? deq_vec_0_1_pc_lob : 6'h0) | (head[1] ? deq_vec_1_1_pc_lob : 6'h0) | (head[2] ? deq_vec_2_1_pc_lob : 6'h0) | (head[3] ? deq_vec_3_1_pc_lob : 6'h0) | (head[4] ? deq_vec_4_1_pc_lob : 6'h0) | (head[5] ? deq_vec_5_1_pc_lob : 6'h0) | (head[6] ? deq_vec_6_1_pc_lob : 6'h0) | (head[7] ? deq_vec_7_1_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_edge_inst_0 = head[0] & deq_vec_0_1_edge_inst | head[1] & deq_vec_1_1_edge_inst | head[2] & deq_vec_2_1_edge_inst | head[3] & deq_vec_3_1_edge_inst | head[4] & deq_vec_4_1_edge_inst | head[5] & deq_vec_5_1_edge_inst | head[6] & deq_vec_6_1_edge_inst | head[7] & deq_vec_7_1_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_ftq_idx_0 = (head[0] ? deq_vec_0_1_ftq_idx : 5'h0) | (head[1] ? deq_vec_1_1_ftq_idx : 5'h0) | (head[2] ? deq_vec_2_1_ftq_idx : 5'h0) | (head[3] ? deq_vec_3_1_ftq_idx : 5'h0) | (head[4] ? deq_vec_4_1_ftq_idx : 5'h0) | (head[5] ? deq_vec_5_1_ftq_idx : 5'h0) | (head[6] ? deq_vec_6_1_ftq_idx : 5'h0) | (head[7] ? deq_vec_7_1_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_is_sfb_0 = head[0] & deq_vec_0_1_is_sfb | head[1] & deq_vec_1_1_is_sfb | head[2] & deq_vec_2_1_is_sfb | head[3] & deq_vec_3_1_is_sfb | head[4] & deq_vec_4_1_is_sfb | head[5] & deq_vec_5_1_is_sfb | head[6] & deq_vec_6_1_is_sfb | head[7] & deq_vec_7_1_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_pc_0 = (head[0] ? deq_vec_0_1_debug_pc : 40'h0) | (head[1] ? deq_vec_1_1_debug_pc : 40'h0) | (head[2] ? deq_vec_2_1_debug_pc : 40'h0) | (head[3] ? deq_vec_3_1_debug_pc : 40'h0) | (head[4] ? deq_vec_4_1_debug_pc : 40'h0) | (head[5] ? deq_vec_5_1_debug_pc : 40'h0) | (head[6] ? deq_vec_6_1_debug_pc : 40'h0) | (head[7] ? deq_vec_7_1_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_is_rvc_0 = head[0] & deq_vec_0_1_is_rvc | head[1] & deq_vec_1_1_is_rvc | head[2] & deq_vec_2_1_is_rvc | head[3] & deq_vec_3_1_is_rvc | head[4] & deq_vec_4_1_is_rvc | head[5] & deq_vec_5_1_is_rvc | head[6] & deq_vec_6_1_is_rvc | head[7] & deq_vec_7_1_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_inst_0 = (head[0] ? deq_vec_0_1_debug_inst : 32'h0) | (head[1] ? deq_vec_1_1_debug_inst : 32'h0) | (head[2] ? deq_vec_2_1_debug_inst : 32'h0) | (head[3] ? deq_vec_3_1_debug_inst : 32'h0) | (head[4] ? deq_vec_4_1_debug_inst : 32'h0) | (head[5] ? deq_vec_5_1_debug_inst : 32'h0) | (head[6] ? deq_vec_6_1_debug_inst : 32'h0) | (head[7] ? deq_vec_7_1_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_inst_0 = (head[0] ? deq_vec_0_1_inst : 32'h0) | (head[1] ? deq_vec_1_1_inst : 32'h0) | (head[2] ? deq_vec_2_1_inst : 32'h0) | (head[3] ? deq_vec_3_1_inst : 32'h0) | (head[4] ? deq_vec_4_1_inst : 32'h0) | (head[5] ? deq_vec_5_1_inst : 32'h0) | (head[6] ? deq_vec_6_1_inst : 32'h0) | (head[7] ? deq_vec_7_1_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_2_debug_fsrc : 3'h0) | (head[1] ? deq_vec_1_2_debug_fsrc : 3'h0) | (head[2] ? deq_vec_2_2_debug_fsrc : 3'h0) | (head[3] ? deq_vec_3_2_debug_fsrc : 3'h0) | (head[4] ? deq_vec_4_2_debug_fsrc : 3'h0) | (head[5] ? deq_vec_5_2_debug_fsrc : 3'h0) | (head[6] ? deq_vec_6_2_debug_fsrc : 3'h0) | (head[7] ? deq_vec_7_2_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_2_bp_xcpt_if | head[1] & deq_vec_1_2_bp_xcpt_if | head[2] & deq_vec_2_2_bp_xcpt_if | head[3] & deq_vec_3_2_bp_xcpt_if | head[4] & deq_vec_4_2_bp_xcpt_if | head[5] & deq_vec_5_2_bp_xcpt_if | head[6] & deq_vec_6_2_bp_xcpt_if | head[7] & deq_vec_7_2_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_bp_debug_if_0 = head[0] & deq_vec_0_2_bp_debug_if | head[1] & deq_vec_1_2_bp_debug_if | head[2] & deq_vec_2_2_bp_debug_if | head[3] & deq_vec_3_2_bp_debug_if | head[4] & deq_vec_4_2_bp_debug_if | head[5] & deq_vec_5_2_bp_debug_if | head[6] & deq_vec_6_2_bp_debug_if | head[7] & deq_vec_7_2_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_2_xcpt_ae_if | head[1] & deq_vec_1_2_xcpt_ae_if | head[2] & deq_vec_2_2_xcpt_ae_if | head[3] & deq_vec_3_2_xcpt_ae_if | head[4] & deq_vec_4_2_xcpt_ae_if | head[5] & deq_vec_5_2_xcpt_ae_if | head[6] & deq_vec_6_2_xcpt_ae_if | head[7] & deq_vec_7_2_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_2_xcpt_pf_if | head[1] & deq_vec_1_2_xcpt_pf_if | head[2] & deq_vec_2_2_xcpt_pf_if | head[3] & deq_vec_3_2_xcpt_pf_if | head[4] & deq_vec_4_2_xcpt_pf_if | head[5] & deq_vec_5_2_xcpt_pf_if | head[6] & deq_vec_6_2_xcpt_pf_if | head[7] & deq_vec_7_2_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_taken_0 = head[0] & deq_vec_0_2_taken | head[1] & deq_vec_1_2_taken | head[2] & deq_vec_2_2_taken | head[3] & deq_vec_3_2_taken | head[4] & deq_vec_4_2_taken | head[5] & deq_vec_5_2_taken | head[6] & deq_vec_6_2_taken | head[7] & deq_vec_7_2_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_pc_lob_0 = (head[0] ? deq_vec_0_2_pc_lob : 6'h0) | (head[1] ? deq_vec_1_2_pc_lob : 6'h0) | (head[2] ? deq_vec_2_2_pc_lob : 6'h0) | (head[3] ? deq_vec_3_2_pc_lob : 6'h0) | (head[4] ? deq_vec_4_2_pc_lob : 6'h0) | (head[5] ? deq_vec_5_2_pc_lob : 6'h0) | (head[6] ? deq_vec_6_2_pc_lob : 6'h0) | (head[7] ? deq_vec_7_2_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_edge_inst_0 = head[0] & deq_vec_0_2_edge_inst | head[1] & deq_vec_1_2_edge_inst | head[2] & deq_vec_2_2_edge_inst | head[3] & deq_vec_3_2_edge_inst | head[4] & deq_vec_4_2_edge_inst | head[5] & deq_vec_5_2_edge_inst | head[6] & deq_vec_6_2_edge_inst | head[7] & deq_vec_7_2_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_ftq_idx_0 = (head[0] ? deq_vec_0_2_ftq_idx : 5'h0) | (head[1] ? deq_vec_1_2_ftq_idx : 5'h0) | (head[2] ? deq_vec_2_2_ftq_idx : 5'h0) | (head[3] ? deq_vec_3_2_ftq_idx : 5'h0) | (head[4] ? deq_vec_4_2_ftq_idx : 5'h0) | (head[5] ? deq_vec_5_2_ftq_idx : 5'h0) | (head[6] ? deq_vec_6_2_ftq_idx : 5'h0) | (head[7] ? deq_vec_7_2_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_is_sfb_0 = head[0] & deq_vec_0_2_is_sfb | head[1] & deq_vec_1_2_is_sfb | head[2] & deq_vec_2_2_is_sfb | head[3] & deq_vec_3_2_is_sfb | head[4] & deq_vec_4_2_is_sfb | head[5] & deq_vec_5_2_is_sfb | head[6] & deq_vec_6_2_is_sfb | head[7] & deq_vec_7_2_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_debug_pc_0 = (head[0] ? deq_vec_0_2_debug_pc : 40'h0) | (head[1] ? deq_vec_1_2_debug_pc : 40'h0) | (head[2] ? deq_vec_2_2_debug_pc : 40'h0) | (head[3] ? deq_vec_3_2_debug_pc : 40'h0) | (head[4] ? deq_vec_4_2_debug_pc : 40'h0) | (head[5] ? deq_vec_5_2_debug_pc : 40'h0) | (head[6] ? deq_vec_6_2_debug_pc : 40'h0) | (head[7] ? deq_vec_7_2_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_is_rvc_0 = head[0] & deq_vec_0_2_is_rvc | head[1] & deq_vec_1_2_is_rvc | head[2] & deq_vec_2_2_is_rvc | head[3] & deq_vec_3_2_is_rvc | head[4] & deq_vec_4_2_is_rvc | head[5] & deq_vec_5_2_is_rvc | head[6] & deq_vec_6_2_is_rvc | head[7] & deq_vec_7_2_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_debug_inst_0 = (head[0] ? deq_vec_0_2_debug_inst : 32'h0) | (head[1] ? deq_vec_1_2_debug_inst : 32'h0) | (head[2] ? deq_vec_2_2_debug_inst : 32'h0) | (head[3] ? deq_vec_3_2_debug_inst : 32'h0) | (head[4] ? deq_vec_4_2_debug_inst : 32'h0) | (head[5] ? deq_vec_5_2_debug_inst : 32'h0) | (head[6] ? deq_vec_6_2_debug_inst : 32'h0) | (head[7] ? deq_vec_7_2_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_2_bits_inst_0 = (head[0] ? deq_vec_0_2_inst : 32'h0) | (head[1] ? deq_vec_1_2_inst : 32'h0) | (head[2] ? deq_vec_2_2_inst : 32'h0) | (head[3] ? deq_vec_3_2_inst : 32'h0) | (head[4] ? deq_vec_4_2_inst : 32'h0) | (head[5] ? deq_vec_5_2_inst : 32'h0) | (head[6] ? deq_vec_6_2_inst : 32'h0) | (head[7] ? deq_vec_7_2_inst : 32'h0); // @[Mux.scala:30:73] wire _io_deq_valid_T = deq_valids_0 | deq_valids_1; // @[fetch-buffer.scala:161:53, :170:38] assign _io_deq_valid_T_1 = _io_deq_valid_T | deq_valids_2; // @[fetch-buffer.scala:161:53, :170:38] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[fetch-buffer.scala:40:7, :170:38] wire [6:0] _head_T = head[6:0]; // @[fetch-buffer.scala:61:21, :132:12] wire [7:0] _head_T_2 = {_head_T, _head_T_1}; // @[fetch-buffer.scala:132:{8,12,24}] assign io_deq_bits_uops_0_valid_0 = ~reset & deq_valids_0; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] assign io_deq_bits_uops_1_valid_0 = ~reset & deq_valids_1; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] assign io_deq_bits_uops_2_valid_0 = ~reset & deq_valids_2; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] wire _T_101 = do_enq & in_mask_0; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_34 = _T_101 & enq_idxs_0[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_37 = _T_101 & enq_idxs_0[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_40 = _T_101 & enq_idxs_0[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_43 = _T_101 & enq_idxs_0[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_46 = _T_101 & enq_idxs_0[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_49 = _T_101 & enq_idxs_0[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_52 = _T_101 & enq_idxs_0[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_55 = _T_101 & enq_idxs_0[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_58 = _T_101 & enq_idxs_0[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_61 = _T_101 & enq_idxs_0[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_64 = _T_101 & enq_idxs_0[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_67 = _T_101 & enq_idxs_0[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_70 = _T_101 & enq_idxs_0[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_73 = _T_101 & enq_idxs_0[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_76 = _T_101 & enq_idxs_0[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_79 = _T_101 & enq_idxs_0[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_82 = _T_101 & enq_idxs_0[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_85 = _T_101 & enq_idxs_0[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_88 = _T_101 & enq_idxs_0[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_91 = _T_101 & enq_idxs_0[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_94 = _T_101 & enq_idxs_0[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_97 = _T_101 & enq_idxs_0[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_100 = _T_101 & enq_idxs_0[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_103 = _T_101 & enq_idxs_0[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_173 = do_enq & in_mask_1; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_106 = _T_173 & enq_idxs_1[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_109 = _T_173 & enq_idxs_1[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_112 = _T_173 & enq_idxs_1[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_115 = _T_173 & enq_idxs_1[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_118 = _T_173 & enq_idxs_1[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_121 = _T_173 & enq_idxs_1[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_124 = _T_173 & enq_idxs_1[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_127 = _T_173 & enq_idxs_1[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_130 = _T_173 & enq_idxs_1[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_133 = _T_173 & enq_idxs_1[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_136 = _T_173 & enq_idxs_1[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_139 = _T_173 & enq_idxs_1[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_142 = _T_173 & enq_idxs_1[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_145 = _T_173 & enq_idxs_1[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_148 = _T_173 & enq_idxs_1[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_151 = _T_173 & enq_idxs_1[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_154 = _T_173 & enq_idxs_1[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_157 = _T_173 & enq_idxs_1[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_160 = _T_173 & enq_idxs_1[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_163 = _T_173 & enq_idxs_1[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_166 = _T_173 & enq_idxs_1[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_169 = _T_173 & enq_idxs_1[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_172 = _T_173 & enq_idxs_1[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_175 = _T_173 & enq_idxs_1[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_245 = do_enq & in_mask_2; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_178 = _T_245 & enq_idxs_2[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_181 = _T_245 & enq_idxs_2[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_184 = _T_245 & enq_idxs_2[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_187 = _T_245 & enq_idxs_2[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_190 = _T_245 & enq_idxs_2[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_193 = _T_245 & enq_idxs_2[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_196 = _T_245 & enq_idxs_2[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_199 = _T_245 & enq_idxs_2[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_202 = _T_245 & enq_idxs_2[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_205 = _T_245 & enq_idxs_2[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_208 = _T_245 & enq_idxs_2[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_211 = _T_245 & enq_idxs_2[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_214 = _T_245 & enq_idxs_2[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_217 = _T_245 & enq_idxs_2[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_220 = _T_245 & enq_idxs_2[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_223 = _T_245 & enq_idxs_2[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_226 = _T_245 & enq_idxs_2[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_229 = _T_245 & enq_idxs_2[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_232 = _T_245 & enq_idxs_2[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_235 = _T_245 & enq_idxs_2[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_238 = _T_245 & enq_idxs_2[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_241 = _T_245 & enq_idxs_2[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_244 = _T_245 & enq_idxs_2[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_247 = _T_245 & enq_idxs_2[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_317 = do_enq & in_mask_3; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_250 = _T_317 & enq_idxs_3[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_253 = _T_317 & enq_idxs_3[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_256 = _T_317 & enq_idxs_3[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_259 = _T_317 & enq_idxs_3[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_262 = _T_317 & enq_idxs_3[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_265 = _T_317 & enq_idxs_3[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_268 = _T_317 & enq_idxs_3[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_271 = _T_317 & enq_idxs_3[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_274 = _T_317 & enq_idxs_3[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_277 = _T_317 & enq_idxs_3[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_280 = _T_317 & enq_idxs_3[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_283 = _T_317 & enq_idxs_3[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_286 = _T_317 & enq_idxs_3[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_289 = _T_317 & enq_idxs_3[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_292 = _T_317 & enq_idxs_3[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_295 = _T_317 & enq_idxs_3[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_298 = _T_317 & enq_idxs_3[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_301 = _T_317 & enq_idxs_3[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_304 = _T_317 & enq_idxs_3[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_307 = _T_317 & enq_idxs_3[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_310 = _T_317 & enq_idxs_3[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_313 = _T_317 & enq_idxs_3[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_316 = _T_317 & enq_idxs_3[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_319 = _T_317 & enq_idxs_3[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_389 = do_enq & in_mask_4; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_322 = _T_389 & enq_idxs_4[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_325 = _T_389 & enq_idxs_4[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_328 = _T_389 & enq_idxs_4[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_331 = _T_389 & enq_idxs_4[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_334 = _T_389 & enq_idxs_4[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_337 = _T_389 & enq_idxs_4[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_340 = _T_389 & enq_idxs_4[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_343 = _T_389 & enq_idxs_4[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_346 = _T_389 & enq_idxs_4[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_349 = _T_389 & enq_idxs_4[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_352 = _T_389 & enq_idxs_4[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_355 = _T_389 & enq_idxs_4[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_358 = _T_389 & enq_idxs_4[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_361 = _T_389 & enq_idxs_4[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_364 = _T_389 & enq_idxs_4[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_367 = _T_389 & enq_idxs_4[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_370 = _T_389 & enq_idxs_4[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_373 = _T_389 & enq_idxs_4[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_376 = _T_389 & enq_idxs_4[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_379 = _T_389 & enq_idxs_4[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_382 = _T_389 & enq_idxs_4[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_385 = _T_389 & enq_idxs_4[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_388 = _T_389 & enq_idxs_4[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_391 = _T_389 & enq_idxs_4[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_461 = do_enq & in_mask_5; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_394 = _T_461 & enq_idxs_5[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_397 = _T_461 & enq_idxs_5[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_400 = _T_461 & enq_idxs_5[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_403 = _T_461 & enq_idxs_5[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_406 = _T_461 & enq_idxs_5[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_409 = _T_461 & enq_idxs_5[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_412 = _T_461 & enq_idxs_5[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_415 = _T_461 & enq_idxs_5[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_418 = _T_461 & enq_idxs_5[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_421 = _T_461 & enq_idxs_5[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_424 = _T_461 & enq_idxs_5[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_427 = _T_461 & enq_idxs_5[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_430 = _T_461 & enq_idxs_5[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_433 = _T_461 & enq_idxs_5[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_436 = _T_461 & enq_idxs_5[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_439 = _T_461 & enq_idxs_5[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_442 = _T_461 & enq_idxs_5[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_445 = _T_461 & enq_idxs_5[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_448 = _T_461 & enq_idxs_5[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_451 = _T_461 & enq_idxs_5[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_454 = _T_461 & enq_idxs_5[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_457 = _T_461 & enq_idxs_5[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_460 = _T_461 & enq_idxs_5[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_463 = _T_461 & enq_idxs_5[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_533 = do_enq & in_mask_6; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_466 = _T_533 & enq_idxs_6[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_469 = _T_533 & enq_idxs_6[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_472 = _T_533 & enq_idxs_6[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_475 = _T_533 & enq_idxs_6[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_478 = _T_533 & enq_idxs_6[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_481 = _T_533 & enq_idxs_6[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_484 = _T_533 & enq_idxs_6[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_487 = _T_533 & enq_idxs_6[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_490 = _T_533 & enq_idxs_6[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_493 = _T_533 & enq_idxs_6[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_496 = _T_533 & enq_idxs_6[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_499 = _T_533 & enq_idxs_6[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_502 = _T_533 & enq_idxs_6[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_505 = _T_533 & enq_idxs_6[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_508 = _T_533 & enq_idxs_6[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_511 = _T_533 & enq_idxs_6[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_514 = _T_533 & enq_idxs_6[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_517 = _T_533 & enq_idxs_6[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_520 = _T_533 & enq_idxs_6[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_523 = _T_533 & enq_idxs_6[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_526 = _T_533 & enq_idxs_6[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_529 = _T_533 & enq_idxs_6[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_532 = _T_533 & enq_idxs_6[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_535 = _T_533 & enq_idxs_6[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_605 = do_enq & in_mask_7; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_538 = _T_605 & enq_idxs_7[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_541 = _T_605 & enq_idxs_7[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_544 = _T_605 & enq_idxs_7[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_547 = _T_605 & enq_idxs_7[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_550 = _T_605 & enq_idxs_7[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_553 = _T_605 & enq_idxs_7[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_556 = _T_605 & enq_idxs_7[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_559 = _T_605 & enq_idxs_7[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_562 = _T_605 & enq_idxs_7[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_565 = _T_605 & enq_idxs_7[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_568 = _T_605 & enq_idxs_7[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_571 = _T_605 & enq_idxs_7[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_574 = _T_605 & enq_idxs_7[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_577 = _T_605 & enq_idxs_7[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_580 = _T_605 & enq_idxs_7[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_583 = _T_605 & enq_idxs_7[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_586 = _T_605 & enq_idxs_7[16]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_589 = _T_605 & enq_idxs_7[17]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_592 = _T_605 & enq_idxs_7[18]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_595 = _T_605 & enq_idxs_7[19]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_598 = _T_605 & enq_idxs_7[20]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_601 = _T_605 & enq_idxs_7[21]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_604 = _T_605 & enq_idxs_7[22]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_607 = _T_605 & enq_idxs_7[23]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] always @(posedge clock) begin // @[fetch-buffer.scala:40:7] if (_T_538) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_466) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_394) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_322) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_250) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_178) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_106) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_34) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_0_edge_inst <= ~(_T_538 | _T_466 | _T_394) & (_T_322 ? in_uops_4_edge_inst : ~(_T_250 | _T_178 | _T_106) & (_T_34 ? in_uops_0_edge_inst : fb_uop_ram_0_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_541) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_469) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_397) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_325) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_253) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_181) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_109) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_37) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_1_edge_inst <= ~(_T_541 | _T_469 | _T_397) & (_T_325 ? in_uops_4_edge_inst : ~(_T_253 | _T_181 | _T_109) & (_T_37 ? in_uops_0_edge_inst : fb_uop_ram_1_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_544) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_472) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_400) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_328) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_256) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_184) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_112) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_40) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_2_edge_inst <= ~(_T_544 | _T_472 | _T_400) & (_T_328 ? in_uops_4_edge_inst : ~(_T_256 | _T_184 | _T_112) & (_T_40 ? in_uops_0_edge_inst : fb_uop_ram_2_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_547) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_475) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_403) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_331) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_259) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_187) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_115) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_43) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_3_edge_inst <= ~(_T_547 | _T_475 | _T_403) & (_T_331 ? in_uops_4_edge_inst : ~(_T_259 | _T_187 | _T_115) & (_T_43 ? in_uops_0_edge_inst : fb_uop_ram_3_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_550) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_478) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_406) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_334) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_262) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_190) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_118) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_46) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_4_edge_inst <= ~(_T_550 | _T_478 | _T_406) & (_T_334 ? in_uops_4_edge_inst : ~(_T_262 | _T_190 | _T_118) & (_T_46 ? in_uops_0_edge_inst : fb_uop_ram_4_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_553) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_481) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_409) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_337) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_265) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_193) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_121) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_49) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_5_edge_inst <= ~(_T_553 | _T_481 | _T_409) & (_T_337 ? in_uops_4_edge_inst : ~(_T_265 | _T_193 | _T_121) & (_T_49 ? in_uops_0_edge_inst : fb_uop_ram_5_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_556) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_484) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_412) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_340) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_268) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_196) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_124) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_52) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_6_edge_inst <= ~(_T_556 | _T_484 | _T_412) & (_T_340 ? in_uops_4_edge_inst : ~(_T_268 | _T_196 | _T_124) & (_T_52 ? in_uops_0_edge_inst : fb_uop_ram_6_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_559) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_487) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_415) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_343) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_271) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_199) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_127) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_55) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_7_edge_inst <= ~(_T_559 | _T_487 | _T_415) & (_T_343 ? in_uops_4_edge_inst : ~(_T_271 | _T_199 | _T_127) & (_T_55 ? in_uops_0_edge_inst : fb_uop_ram_7_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_562) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_490) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_418) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_346) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_274) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_202) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_130) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_58) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_8_edge_inst <= ~(_T_562 | _T_490 | _T_418) & (_T_346 ? in_uops_4_edge_inst : ~(_T_274 | _T_202 | _T_130) & (_T_58 ? in_uops_0_edge_inst : fb_uop_ram_8_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_565) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_493) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_421) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_349) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_277) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_205) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_133) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_61) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_9_edge_inst <= ~(_T_565 | _T_493 | _T_421) & (_T_349 ? in_uops_4_edge_inst : ~(_T_277 | _T_205 | _T_133) & (_T_61 ? in_uops_0_edge_inst : fb_uop_ram_9_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_568) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_496) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_424) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_352) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_280) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_208) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_136) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_64) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_10_edge_inst <= ~(_T_568 | _T_496 | _T_424) & (_T_352 ? in_uops_4_edge_inst : ~(_T_280 | _T_208 | _T_136) & (_T_64 ? in_uops_0_edge_inst : fb_uop_ram_10_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_571) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_499) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_427) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_355) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_283) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_211) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_139) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_67) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_11_edge_inst <= ~(_T_571 | _T_499 | _T_427) & (_T_355 ? in_uops_4_edge_inst : ~(_T_283 | _T_211 | _T_139) & (_T_67 ? in_uops_0_edge_inst : fb_uop_ram_11_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_574) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_502) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_430) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_358) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_286) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_214) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_142) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_70) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_12_edge_inst <= ~(_T_574 | _T_502 | _T_430) & (_T_358 ? in_uops_4_edge_inst : ~(_T_286 | _T_214 | _T_142) & (_T_70 ? in_uops_0_edge_inst : fb_uop_ram_12_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_577) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_505) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_433) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_361) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_289) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_217) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_145) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_73) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_13_edge_inst <= ~(_T_577 | _T_505 | _T_433) & (_T_361 ? in_uops_4_edge_inst : ~(_T_289 | _T_217 | _T_145) & (_T_73 ? in_uops_0_edge_inst : fb_uop_ram_13_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_580) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_508) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_436) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_364) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_292) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_220) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_148) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_76) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_14_edge_inst <= ~(_T_580 | _T_508 | _T_436) & (_T_364 ? in_uops_4_edge_inst : ~(_T_292 | _T_220 | _T_148) & (_T_76 ? in_uops_0_edge_inst : fb_uop_ram_14_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_583) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_511) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_439) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_367) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_295) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_223) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_151) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_79) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_15_edge_inst <= ~(_T_583 | _T_511 | _T_439) & (_T_367 ? in_uops_4_edge_inst : ~(_T_295 | _T_223 | _T_151) & (_T_79 ? in_uops_0_edge_inst : fb_uop_ram_15_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_586) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_514) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_442) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_370) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_298) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_226) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_154) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_82) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_16_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_16_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_16_edge_inst <= ~(_T_586 | _T_514 | _T_442) & (_T_370 ? in_uops_4_edge_inst : ~(_T_298 | _T_226 | _T_154) & (_T_82 ? in_uops_0_edge_inst : fb_uop_ram_16_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_589) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_517) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_445) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_373) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_301) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_229) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_157) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_85) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_17_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_17_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_17_edge_inst <= ~(_T_589 | _T_517 | _T_445) & (_T_373 ? in_uops_4_edge_inst : ~(_T_301 | _T_229 | _T_157) & (_T_85 ? in_uops_0_edge_inst : fb_uop_ram_17_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_592) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_520) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_448) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_376) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_304) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_232) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_160) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_88) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_18_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_18_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_18_edge_inst <= ~(_T_592 | _T_520 | _T_448) & (_T_376 ? in_uops_4_edge_inst : ~(_T_304 | _T_232 | _T_160) & (_T_88 ? in_uops_0_edge_inst : fb_uop_ram_18_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_595) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_523) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_451) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_379) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_307) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_235) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_163) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_91) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_19_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_19_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_19_edge_inst <= ~(_T_595 | _T_523 | _T_451) & (_T_379 ? in_uops_4_edge_inst : ~(_T_307 | _T_235 | _T_163) & (_T_91 ? in_uops_0_edge_inst : fb_uop_ram_19_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_598) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_526) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_454) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_382) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_310) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_238) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_166) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_94) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_20_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_20_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_20_edge_inst <= ~(_T_598 | _T_526 | _T_454) & (_T_382 ? in_uops_4_edge_inst : ~(_T_310 | _T_238 | _T_166) & (_T_94 ? in_uops_0_edge_inst : fb_uop_ram_20_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_601) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_529) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_457) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_385) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_313) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_241) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_169) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_97) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_21_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_21_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_21_edge_inst <= ~(_T_601 | _T_529 | _T_457) & (_T_385 ? in_uops_4_edge_inst : ~(_T_313 | _T_241 | _T_169) & (_T_97 ? in_uops_0_edge_inst : fb_uop_ram_21_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_604) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_532) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_460) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_388) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_316) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_244) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_172) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_100) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_22_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_22_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_22_edge_inst <= ~(_T_604 | _T_532 | _T_460) & (_T_388 ? in_uops_4_edge_inst : ~(_T_316 | _T_244 | _T_172) & (_T_100 ? in_uops_0_edge_inst : fb_uop_ram_22_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_607) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_7_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_7_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_7_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_7_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_7_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_7_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_7_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_7_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_535) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_6_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_6_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_6_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_6_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_6_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_6_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_6_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_6_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_463) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_5_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_5_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_5_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_5_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_5_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_5_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_5_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_5_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_391) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_4_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_4_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_4_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_4_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_4_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_4_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_4_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_4_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_319) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_247) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_175) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_103) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_23_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_23_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_23_edge_inst <= ~(_T_607 | _T_535 | _T_463) & (_T_391 ? in_uops_4_edge_inst : ~(_T_319 | _T_247 | _T_175) & (_T_103 ? in_uops_0_edge_inst : fb_uop_ram_23_edge_inst)); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (reset) begin // @[fetch-buffer.scala:40:7] head <= 8'h1; // @[fetch-buffer.scala:61:21] tail <= 24'h1; // @[fetch-buffer.scala:62:21] maybe_full <= 1'h0; // @[fetch-buffer.scala:64:27] end else begin // @[fetch-buffer.scala:40:7] if (io_clear_0) begin // @[fetch-buffer.scala:40:7] head <= 8'h1; // @[fetch-buffer.scala:61:21] tail <= 24'h1; // @[fetch-buffer.scala:62:21] end else begin // @[fetch-buffer.scala:40:7] if (do_deq) // @[fetch-buffer.scala:159:29] head <= _head_T_2; // @[fetch-buffer.scala:61:21, :132:8] if (do_enq) begin // @[fetch-buffer.scala:82:16] if (in_mask_7) // @[fetch-buffer.scala:87:21] tail <= {enq_idxs_7[22:0], enq_idxs_7[23]}; // @[fetch-buffer.scala:62:21, :128:22, :132:{8,12,24}] else if (in_mask_6) // @[fetch-buffer.scala:87:21] tail <= _T_26; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_5) // @[fetch-buffer.scala:87:21] tail <= _T_22; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_4) // @[fetch-buffer.scala:87:21] tail <= _T_18; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_3) // @[fetch-buffer.scala:87:21] tail <= _T_14; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_2) // @[fetch-buffer.scala:87:21] tail <= _T_10; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_1) // @[fetch-buffer.scala:87:21] tail <= _T_6; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_0) // @[fetch-buffer.scala:87:21] tail <= _T_2; // @[fetch-buffer.scala:62:21, :132:8] end end maybe_full <= ~(io_clear_0 | do_deq) & (do_enq & (in_mask_0 | in_mask_1 | in_mask_2 | in_mask_3 | in_mask_4 | in_mask_5 | in_mask_6 | in_mask_7) | maybe_full); // @[fetch-buffer.scala:40:7, :64:27, :82:16, :87:21, :159:29, :176:17, :178:{27,33}, :179:18, :183:17, :185:16, :188:19, :191:16] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[fetch-buffer.scala:40:7] assign io_deq_valid = io_deq_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_valid = io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_inst = io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_inst = io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_is_rvc = io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_pc = io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_is_sfb = io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_ftq_idx = io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_edge_inst = io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_pc_lob = io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_taken = io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_xcpt_pf_if = io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_xcpt_ae_if = io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_bp_debug_if = io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_bp_xcpt_if = io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_fsrc = io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_valid = io_deq_bits_uops_1_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_inst = io_deq_bits_uops_1_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_inst = io_deq_bits_uops_1_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_is_rvc = io_deq_bits_uops_1_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_pc = io_deq_bits_uops_1_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_is_sfb = io_deq_bits_uops_1_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_ftq_idx = io_deq_bits_uops_1_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_edge_inst = io_deq_bits_uops_1_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_pc_lob = io_deq_bits_uops_1_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_taken = io_deq_bits_uops_1_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_xcpt_pf_if = io_deq_bits_uops_1_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_xcpt_ae_if = io_deq_bits_uops_1_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_bp_debug_if = io_deq_bits_uops_1_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_bp_xcpt_if = io_deq_bits_uops_1_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_fsrc = io_deq_bits_uops_1_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_valid = io_deq_bits_uops_2_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_inst = io_deq_bits_uops_2_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_debug_inst = io_deq_bits_uops_2_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_is_rvc = io_deq_bits_uops_2_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_debug_pc = io_deq_bits_uops_2_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_is_sfb = io_deq_bits_uops_2_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_ftq_idx = io_deq_bits_uops_2_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_edge_inst = io_deq_bits_uops_2_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_pc_lob = io_deq_bits_uops_2_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_taken = io_deq_bits_uops_2_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_xcpt_pf_if = io_deq_bits_uops_2_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_xcpt_ae_if = io_deq_bits_uops_2_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_bp_debug_if = io_deq_bits_uops_2_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_bp_xcpt_if = io_deq_bits_uops_2_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_2_bits_debug_fsrc = io_deq_bits_uops_2_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_81 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_81( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_8 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_8 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_16 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulRecFN_8( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_8 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_16 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_267 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_267( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_151 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_151( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_116 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_116 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_10 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id connect route_arbiter.io.in[4].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[4].bits.flow.egress_node_id invalidate route_arbiter.io.in[4].bits.flow.egress_node invalidate route_arbiter.io.in[4].bits.flow.ingress_node_id invalidate route_arbiter.io.in[4].bits.flow.ingress_node invalidate route_arbiter.io.in[4].bits.flow.vnet_id invalidate route_arbiter.io.in[4].bits.src_virt_id connect route_arbiter.io.in[5].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[5].bits.flow.egress_node_id invalidate route_arbiter.io.in[5].bits.flow.egress_node invalidate route_arbiter.io.in[5].bits.flow.ingress_node_id invalidate route_arbiter.io.in[5].bits.flow.ingress_node invalidate route_arbiter.io.in[5].bits.flow.vnet_id invalidate route_arbiter.io.in[5].bits.src_virt_id connect route_arbiter.io.in[6].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[6].bits.flow.egress_node_id invalidate route_arbiter.io.in[6].bits.flow.egress_node invalidate route_arbiter.io.in[6].bits.flow.ingress_node_id invalidate route_arbiter.io.in[6].bits.flow.ingress_node invalidate route_arbiter.io.in[6].bits.flow.vnet_id invalidate route_arbiter.io.in[6].bits.src_virt_id connect route_arbiter.io.in[7].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[7].bits.flow.egress_node_id invalidate route_arbiter.io.in[7].bits.flow.egress_node invalidate route_arbiter.io.in[7].bits.flow.ingress_node_id invalidate route_arbiter.io.in[7].bits.flow.ingress_node invalidate route_arbiter.io.in[7].bits.flow.vnet_id invalidate route_arbiter.io.in[7].bits.src_virt_id node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_9 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_9 : connect states[8].g, UInt<3>(0h2) connect route_arbiter.io.in[9].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[9].bits.flow.egress_node_id invalidate route_arbiter.io.in[9].bits.flow.egress_node invalidate route_arbiter.io.in[9].bits.flow.ingress_node_id invalidate route_arbiter.io.in[9].bits.flow.ingress_node invalidate route_arbiter.io.in[9].bits.flow.vnet_id invalidate route_arbiter.io.in[9].bits.src_virt_id node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_20 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_20 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_21 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_21 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_22 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_22 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_23 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_24 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_25 = and(io.router_req.ready, io.router_req.valid) when _T_25 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_26 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_27 = or(_T_26, vcalloc_vals[2]) node _T_28 = or(_T_27, vcalloc_vals[3]) node _T_29 = or(_T_28, vcalloc_vals[4]) node _T_30 = or(_T_29, vcalloc_vals[5]) node _T_31 = or(_T_30, vcalloc_vals[6]) node _T_32 = or(_T_31, vcalloc_vals[7]) node _T_33 = or(_T_32, vcalloc_vals[8]) node _T_34 = or(_T_33, vcalloc_vals[9]) when _T_34 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>[10] node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24[0], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410) node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_24[1], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435) node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436) node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446 connect _io_vcalloc_req_bits_WIRE_24[2], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450) node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451) node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452) node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453) node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454) node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455) node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465 connect _io_vcalloc_req_bits_WIRE_24[3], _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467) node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468) node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469) node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470) node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475) wire _io_vcalloc_req_bits_WIRE_29 : UInt<1> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484 connect _io_vcalloc_req_bits_WIRE_24[4], _io_vcalloc_req_bits_WIRE_29 node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503 connect _io_vcalloc_req_bits_WIRE_24[5], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_512 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_513 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_504, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_518 = or(_io_vcalloc_req_bits_T_517, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_519 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_510) node _io_vcalloc_req_bits_T_520 = or(_io_vcalloc_req_bits_T_519, _io_vcalloc_req_bits_T_511) node _io_vcalloc_req_bits_T_521 = or(_io_vcalloc_req_bits_T_520, _io_vcalloc_req_bits_T_512) node _io_vcalloc_req_bits_T_522 = or(_io_vcalloc_req_bits_T_521, _io_vcalloc_req_bits_T_513) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_522 connect _io_vcalloc_req_bits_WIRE_24[6], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_527 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_528 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_529 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_530 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_531 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_532 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_533 = or(_io_vcalloc_req_bits_T_523, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_534 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_525) node _io_vcalloc_req_bits_T_535 = or(_io_vcalloc_req_bits_T_534, _io_vcalloc_req_bits_T_526) node _io_vcalloc_req_bits_T_536 = or(_io_vcalloc_req_bits_T_535, _io_vcalloc_req_bits_T_527) node _io_vcalloc_req_bits_T_537 = or(_io_vcalloc_req_bits_T_536, _io_vcalloc_req_bits_T_528) node _io_vcalloc_req_bits_T_538 = or(_io_vcalloc_req_bits_T_537, _io_vcalloc_req_bits_T_529) node _io_vcalloc_req_bits_T_539 = or(_io_vcalloc_req_bits_T_538, _io_vcalloc_req_bits_T_530) node _io_vcalloc_req_bits_T_540 = or(_io_vcalloc_req_bits_T_539, _io_vcalloc_req_bits_T_531) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_540, _io_vcalloc_req_bits_T_532) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_541 connect _io_vcalloc_req_bits_WIRE_24[7], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_542 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_543 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_544 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_545 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_546 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_547 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_543) node _io_vcalloc_req_bits_T_553 = or(_io_vcalloc_req_bits_T_552, _io_vcalloc_req_bits_T_544) node _io_vcalloc_req_bits_T_554 = or(_io_vcalloc_req_bits_T_553, _io_vcalloc_req_bits_T_545) node _io_vcalloc_req_bits_T_555 = or(_io_vcalloc_req_bits_T_554, _io_vcalloc_req_bits_T_546) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_555, _io_vcalloc_req_bits_T_547) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_548) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_551) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_560 connect _io_vcalloc_req_bits_WIRE_24[8], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_561 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_562 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_562) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_563) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_578 = or(_io_vcalloc_req_bits_T_577, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_579 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_579 connect _io_vcalloc_req_bits_WIRE_24[9], _io_vcalloc_req_bits_WIRE_34 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_24 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_587 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_588 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_589 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_580, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_593 = or(_io_vcalloc_req_bits_T_592, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_594 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_585) node _io_vcalloc_req_bits_T_595 = or(_io_vcalloc_req_bits_T_594, _io_vcalloc_req_bits_T_586) node _io_vcalloc_req_bits_T_596 = or(_io_vcalloc_req_bits_T_595, _io_vcalloc_req_bits_T_587) node _io_vcalloc_req_bits_T_597 = or(_io_vcalloc_req_bits_T_596, _io_vcalloc_req_bits_T_588) node _io_vcalloc_req_bits_T_598 = or(_io_vcalloc_req_bits_T_597, _io_vcalloc_req_bits_T_589) wire _io_vcalloc_req_bits_WIRE_35 : UInt<4> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_598 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_35 wire _io_vcalloc_req_bits_WIRE_36 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_602 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_603 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_604 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_605 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_606 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_607 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = or(_io_vcalloc_req_bits_T_599, _io_vcalloc_req_bits_T_600) node _io_vcalloc_req_bits_T_610 = or(_io_vcalloc_req_bits_T_609, _io_vcalloc_req_bits_T_601) node _io_vcalloc_req_bits_T_611 = or(_io_vcalloc_req_bits_T_610, _io_vcalloc_req_bits_T_602) node _io_vcalloc_req_bits_T_612 = or(_io_vcalloc_req_bits_T_611, _io_vcalloc_req_bits_T_603) node _io_vcalloc_req_bits_T_613 = or(_io_vcalloc_req_bits_T_612, _io_vcalloc_req_bits_T_604) node _io_vcalloc_req_bits_T_614 = or(_io_vcalloc_req_bits_T_613, _io_vcalloc_req_bits_T_605) node _io_vcalloc_req_bits_T_615 = or(_io_vcalloc_req_bits_T_614, _io_vcalloc_req_bits_T_606) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_615, _io_vcalloc_req_bits_T_607) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_608) wire _io_vcalloc_req_bits_WIRE_37 : UInt<3> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_617 connect _io_vcalloc_req_bits_WIRE_36.egress_node_id, _io_vcalloc_req_bits_WIRE_37 node _io_vcalloc_req_bits_T_618 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_619 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_620 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_621 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_622 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_619) node _io_vcalloc_req_bits_T_629 = or(_io_vcalloc_req_bits_T_628, _io_vcalloc_req_bits_T_620) node _io_vcalloc_req_bits_T_630 = or(_io_vcalloc_req_bits_T_629, _io_vcalloc_req_bits_T_621) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_630, _io_vcalloc_req_bits_T_622) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_623) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_627) wire _io_vcalloc_req_bits_WIRE_38 : UInt<4> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_636 connect _io_vcalloc_req_bits_WIRE_36.egress_node, _io_vcalloc_req_bits_WIRE_38 node _io_vcalloc_req_bits_T_637 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_637, _io_vcalloc_req_bits_T_638) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_653 = or(_io_vcalloc_req_bits_T_652, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_654 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_645) node _io_vcalloc_req_bits_T_655 = or(_io_vcalloc_req_bits_T_654, _io_vcalloc_req_bits_T_646) wire _io_vcalloc_req_bits_WIRE_39 : UInt<2> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_655 connect _io_vcalloc_req_bits_WIRE_36.ingress_node_id, _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_662 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_663 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_664 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_665 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_656, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_668 = or(_io_vcalloc_req_bits_T_667, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_669 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_660) node _io_vcalloc_req_bits_T_670 = or(_io_vcalloc_req_bits_T_669, _io_vcalloc_req_bits_T_661) node _io_vcalloc_req_bits_T_671 = or(_io_vcalloc_req_bits_T_670, _io_vcalloc_req_bits_T_662) node _io_vcalloc_req_bits_T_672 = or(_io_vcalloc_req_bits_T_671, _io_vcalloc_req_bits_T_663) node _io_vcalloc_req_bits_T_673 = or(_io_vcalloc_req_bits_T_672, _io_vcalloc_req_bits_T_664) node _io_vcalloc_req_bits_T_674 = or(_io_vcalloc_req_bits_T_673, _io_vcalloc_req_bits_T_665) wire _io_vcalloc_req_bits_WIRE_40 : UInt<4> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_674 connect _io_vcalloc_req_bits_WIRE_36.ingress_node, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_677 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_678 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_679 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_680 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_681 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_682 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = or(_io_vcalloc_req_bits_T_675, _io_vcalloc_req_bits_T_676) node _io_vcalloc_req_bits_T_686 = or(_io_vcalloc_req_bits_T_685, _io_vcalloc_req_bits_T_677) node _io_vcalloc_req_bits_T_687 = or(_io_vcalloc_req_bits_T_686, _io_vcalloc_req_bits_T_678) node _io_vcalloc_req_bits_T_688 = or(_io_vcalloc_req_bits_T_687, _io_vcalloc_req_bits_T_679) node _io_vcalloc_req_bits_T_689 = or(_io_vcalloc_req_bits_T_688, _io_vcalloc_req_bits_T_680) node _io_vcalloc_req_bits_T_690 = or(_io_vcalloc_req_bits_T_689, _io_vcalloc_req_bits_T_681) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_690, _io_vcalloc_req_bits_T_682) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_683) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_684) wire _io_vcalloc_req_bits_WIRE_41 : UInt<3> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_693 connect _io_vcalloc_req_bits_WIRE_36.vnet_id, _io_vcalloc_req_bits_WIRE_41 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_36 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`0`[8] invalidate vcalloc_reqs[0].vc_sel.`0`[9] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[8] invalidate vcalloc_reqs[0].vc_sel.`1`[9] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[8] invalidate vcalloc_reqs[0].vc_sel.`2`[9] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`0`[5] invalidate vcalloc_reqs[1].vc_sel.`0`[6] invalidate vcalloc_reqs[1].vc_sel.`0`[7] invalidate vcalloc_reqs[1].vc_sel.`0`[8] invalidate vcalloc_reqs[1].vc_sel.`0`[9] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[5] invalidate vcalloc_reqs[1].vc_sel.`1`[6] invalidate vcalloc_reqs[1].vc_sel.`1`[7] invalidate vcalloc_reqs[1].vc_sel.`1`[8] invalidate vcalloc_reqs[1].vc_sel.`1`[9] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[3] invalidate vcalloc_reqs[1].vc_sel.`2`[4] invalidate vcalloc_reqs[1].vc_sel.`2`[5] invalidate vcalloc_reqs[1].vc_sel.`2`[6] invalidate vcalloc_reqs[1].vc_sel.`2`[7] invalidate vcalloc_reqs[1].vc_sel.`2`[8] invalidate vcalloc_reqs[1].vc_sel.`2`[9] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`0`[5] invalidate vcalloc_reqs[2].vc_sel.`0`[6] invalidate vcalloc_reqs[2].vc_sel.`0`[7] invalidate vcalloc_reqs[2].vc_sel.`0`[8] invalidate vcalloc_reqs[2].vc_sel.`0`[9] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[5] invalidate vcalloc_reqs[2].vc_sel.`1`[6] invalidate vcalloc_reqs[2].vc_sel.`1`[7] invalidate vcalloc_reqs[2].vc_sel.`1`[8] invalidate vcalloc_reqs[2].vc_sel.`1`[9] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[3] invalidate vcalloc_reqs[2].vc_sel.`2`[4] invalidate vcalloc_reqs[2].vc_sel.`2`[5] invalidate vcalloc_reqs[2].vc_sel.`2`[6] invalidate vcalloc_reqs[2].vc_sel.`2`[7] invalidate vcalloc_reqs[2].vc_sel.`2`[8] invalidate vcalloc_reqs[2].vc_sel.`2`[9] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`0`[5] invalidate vcalloc_reqs[3].vc_sel.`0`[6] invalidate vcalloc_reqs[3].vc_sel.`0`[7] invalidate vcalloc_reqs[3].vc_sel.`0`[8] invalidate vcalloc_reqs[3].vc_sel.`0`[9] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[5] invalidate vcalloc_reqs[3].vc_sel.`1`[6] invalidate vcalloc_reqs[3].vc_sel.`1`[7] invalidate vcalloc_reqs[3].vc_sel.`1`[8] invalidate vcalloc_reqs[3].vc_sel.`1`[9] invalidate vcalloc_reqs[3].vc_sel.`2`[0] invalidate vcalloc_reqs[3].vc_sel.`2`[1] invalidate vcalloc_reqs[3].vc_sel.`2`[2] invalidate vcalloc_reqs[3].vc_sel.`2`[3] invalidate vcalloc_reqs[3].vc_sel.`2`[4] invalidate vcalloc_reqs[3].vc_sel.`2`[5] invalidate vcalloc_reqs[3].vc_sel.`2`[6] invalidate vcalloc_reqs[3].vc_sel.`2`[7] invalidate vcalloc_reqs[3].vc_sel.`2`[8] invalidate vcalloc_reqs[3].vc_sel.`2`[9] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id connect vcalloc_vals[4], UInt<1>(0h0) invalidate vcalloc_reqs[4].vc_sel.`0`[0] invalidate vcalloc_reqs[4].vc_sel.`0`[1] invalidate vcalloc_reqs[4].vc_sel.`0`[2] invalidate vcalloc_reqs[4].vc_sel.`0`[3] invalidate vcalloc_reqs[4].vc_sel.`0`[4] invalidate vcalloc_reqs[4].vc_sel.`0`[5] invalidate vcalloc_reqs[4].vc_sel.`0`[6] invalidate vcalloc_reqs[4].vc_sel.`0`[7] invalidate vcalloc_reqs[4].vc_sel.`0`[8] invalidate vcalloc_reqs[4].vc_sel.`0`[9] invalidate vcalloc_reqs[4].vc_sel.`1`[0] invalidate vcalloc_reqs[4].vc_sel.`1`[1] invalidate vcalloc_reqs[4].vc_sel.`1`[2] invalidate vcalloc_reqs[4].vc_sel.`1`[3] invalidate vcalloc_reqs[4].vc_sel.`1`[4] invalidate vcalloc_reqs[4].vc_sel.`1`[5] invalidate vcalloc_reqs[4].vc_sel.`1`[6] invalidate vcalloc_reqs[4].vc_sel.`1`[7] invalidate vcalloc_reqs[4].vc_sel.`1`[8] invalidate vcalloc_reqs[4].vc_sel.`1`[9] invalidate vcalloc_reqs[4].vc_sel.`2`[0] invalidate vcalloc_reqs[4].vc_sel.`2`[1] invalidate vcalloc_reqs[4].vc_sel.`2`[2] invalidate vcalloc_reqs[4].vc_sel.`2`[3] invalidate vcalloc_reqs[4].vc_sel.`2`[4] invalidate vcalloc_reqs[4].vc_sel.`2`[5] invalidate vcalloc_reqs[4].vc_sel.`2`[6] invalidate vcalloc_reqs[4].vc_sel.`2`[7] invalidate vcalloc_reqs[4].vc_sel.`2`[8] invalidate vcalloc_reqs[4].vc_sel.`2`[9] invalidate vcalloc_reqs[4].in_vc invalidate vcalloc_reqs[4].flow.egress_node_id invalidate vcalloc_reqs[4].flow.egress_node invalidate vcalloc_reqs[4].flow.ingress_node_id invalidate vcalloc_reqs[4].flow.ingress_node invalidate vcalloc_reqs[4].flow.vnet_id connect vcalloc_vals[5], UInt<1>(0h0) invalidate vcalloc_reqs[5].vc_sel.`0`[0] invalidate vcalloc_reqs[5].vc_sel.`0`[1] invalidate vcalloc_reqs[5].vc_sel.`0`[2] invalidate vcalloc_reqs[5].vc_sel.`0`[3] invalidate vcalloc_reqs[5].vc_sel.`0`[4] invalidate vcalloc_reqs[5].vc_sel.`0`[5] invalidate vcalloc_reqs[5].vc_sel.`0`[6] invalidate vcalloc_reqs[5].vc_sel.`0`[7] invalidate vcalloc_reqs[5].vc_sel.`0`[8] invalidate vcalloc_reqs[5].vc_sel.`0`[9] invalidate vcalloc_reqs[5].vc_sel.`1`[0] invalidate vcalloc_reqs[5].vc_sel.`1`[1] invalidate vcalloc_reqs[5].vc_sel.`1`[2] invalidate vcalloc_reqs[5].vc_sel.`1`[3] invalidate vcalloc_reqs[5].vc_sel.`1`[4] invalidate vcalloc_reqs[5].vc_sel.`1`[5] invalidate vcalloc_reqs[5].vc_sel.`1`[6] invalidate vcalloc_reqs[5].vc_sel.`1`[7] invalidate vcalloc_reqs[5].vc_sel.`1`[8] invalidate vcalloc_reqs[5].vc_sel.`1`[9] invalidate vcalloc_reqs[5].vc_sel.`2`[0] invalidate vcalloc_reqs[5].vc_sel.`2`[1] invalidate vcalloc_reqs[5].vc_sel.`2`[2] invalidate vcalloc_reqs[5].vc_sel.`2`[3] invalidate vcalloc_reqs[5].vc_sel.`2`[4] invalidate vcalloc_reqs[5].vc_sel.`2`[5] invalidate vcalloc_reqs[5].vc_sel.`2`[6] invalidate vcalloc_reqs[5].vc_sel.`2`[7] invalidate vcalloc_reqs[5].vc_sel.`2`[8] invalidate vcalloc_reqs[5].vc_sel.`2`[9] invalidate vcalloc_reqs[5].in_vc invalidate vcalloc_reqs[5].flow.egress_node_id invalidate vcalloc_reqs[5].flow.egress_node invalidate vcalloc_reqs[5].flow.ingress_node_id invalidate vcalloc_reqs[5].flow.ingress_node invalidate vcalloc_reqs[5].flow.vnet_id connect vcalloc_vals[6], UInt<1>(0h0) invalidate vcalloc_reqs[6].vc_sel.`0`[0] invalidate vcalloc_reqs[6].vc_sel.`0`[1] invalidate vcalloc_reqs[6].vc_sel.`0`[2] invalidate vcalloc_reqs[6].vc_sel.`0`[3] invalidate vcalloc_reqs[6].vc_sel.`0`[4] invalidate vcalloc_reqs[6].vc_sel.`0`[5] invalidate vcalloc_reqs[6].vc_sel.`0`[6] invalidate vcalloc_reqs[6].vc_sel.`0`[7] invalidate vcalloc_reqs[6].vc_sel.`0`[8] invalidate vcalloc_reqs[6].vc_sel.`0`[9] invalidate vcalloc_reqs[6].vc_sel.`1`[0] invalidate vcalloc_reqs[6].vc_sel.`1`[1] invalidate vcalloc_reqs[6].vc_sel.`1`[2] invalidate vcalloc_reqs[6].vc_sel.`1`[3] invalidate vcalloc_reqs[6].vc_sel.`1`[4] invalidate vcalloc_reqs[6].vc_sel.`1`[5] invalidate vcalloc_reqs[6].vc_sel.`1`[6] invalidate vcalloc_reqs[6].vc_sel.`1`[7] invalidate vcalloc_reqs[6].vc_sel.`1`[8] invalidate vcalloc_reqs[6].vc_sel.`1`[9] invalidate vcalloc_reqs[6].vc_sel.`2`[0] invalidate vcalloc_reqs[6].vc_sel.`2`[1] invalidate vcalloc_reqs[6].vc_sel.`2`[2] invalidate vcalloc_reqs[6].vc_sel.`2`[3] invalidate vcalloc_reqs[6].vc_sel.`2`[4] invalidate vcalloc_reqs[6].vc_sel.`2`[5] invalidate vcalloc_reqs[6].vc_sel.`2`[6] invalidate vcalloc_reqs[6].vc_sel.`2`[7] invalidate vcalloc_reqs[6].vc_sel.`2`[8] invalidate vcalloc_reqs[6].vc_sel.`2`[9] invalidate vcalloc_reqs[6].in_vc invalidate vcalloc_reqs[6].flow.egress_node_id invalidate vcalloc_reqs[6].flow.egress_node invalidate vcalloc_reqs[6].flow.ingress_node_id invalidate vcalloc_reqs[6].flow.ingress_node invalidate vcalloc_reqs[6].flow.vnet_id connect vcalloc_vals[7], UInt<1>(0h0) invalidate vcalloc_reqs[7].vc_sel.`0`[0] invalidate vcalloc_reqs[7].vc_sel.`0`[1] invalidate vcalloc_reqs[7].vc_sel.`0`[2] invalidate vcalloc_reqs[7].vc_sel.`0`[3] invalidate vcalloc_reqs[7].vc_sel.`0`[4] invalidate vcalloc_reqs[7].vc_sel.`0`[5] invalidate vcalloc_reqs[7].vc_sel.`0`[6] invalidate vcalloc_reqs[7].vc_sel.`0`[7] invalidate vcalloc_reqs[7].vc_sel.`0`[8] invalidate vcalloc_reqs[7].vc_sel.`0`[9] invalidate vcalloc_reqs[7].vc_sel.`1`[0] invalidate vcalloc_reqs[7].vc_sel.`1`[1] invalidate vcalloc_reqs[7].vc_sel.`1`[2] invalidate vcalloc_reqs[7].vc_sel.`1`[3] invalidate vcalloc_reqs[7].vc_sel.`1`[4] invalidate vcalloc_reqs[7].vc_sel.`1`[5] invalidate vcalloc_reqs[7].vc_sel.`1`[6] invalidate vcalloc_reqs[7].vc_sel.`1`[7] invalidate vcalloc_reqs[7].vc_sel.`1`[8] invalidate vcalloc_reqs[7].vc_sel.`1`[9] invalidate vcalloc_reqs[7].vc_sel.`2`[0] invalidate vcalloc_reqs[7].vc_sel.`2`[1] invalidate vcalloc_reqs[7].vc_sel.`2`[2] invalidate vcalloc_reqs[7].vc_sel.`2`[3] invalidate vcalloc_reqs[7].vc_sel.`2`[4] invalidate vcalloc_reqs[7].vc_sel.`2`[5] invalidate vcalloc_reqs[7].vc_sel.`2`[6] invalidate vcalloc_reqs[7].vc_sel.`2`[7] invalidate vcalloc_reqs[7].vc_sel.`2`[8] invalidate vcalloc_reqs[7].vc_sel.`2`[9] invalidate vcalloc_reqs[7].in_vc invalidate vcalloc_reqs[7].flow.egress_node_id invalidate vcalloc_reqs[7].flow.egress_node invalidate vcalloc_reqs[7].flow.ingress_node_id invalidate vcalloc_reqs[7].flow.ingress_node invalidate vcalloc_reqs[7].flow.vnet_id node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].flow, states[8].flow node _T_35 = bits(vcalloc_sel, 8, 8) node _T_36 = and(vcalloc_vals[8], _T_35) node _T_37 = and(_T_36, io.vcalloc_req.ready) when _T_37 : connect states[8].g, UInt<3>(0h3) connect vcalloc_vals[9], UInt<1>(0h0) invalidate vcalloc_reqs[9].vc_sel.`0`[0] invalidate vcalloc_reqs[9].vc_sel.`0`[1] invalidate vcalloc_reqs[9].vc_sel.`0`[2] invalidate vcalloc_reqs[9].vc_sel.`0`[3] invalidate vcalloc_reqs[9].vc_sel.`0`[4] invalidate vcalloc_reqs[9].vc_sel.`0`[5] invalidate vcalloc_reqs[9].vc_sel.`0`[6] invalidate vcalloc_reqs[9].vc_sel.`0`[7] invalidate vcalloc_reqs[9].vc_sel.`0`[8] invalidate vcalloc_reqs[9].vc_sel.`0`[9] invalidate vcalloc_reqs[9].vc_sel.`1`[0] invalidate vcalloc_reqs[9].vc_sel.`1`[1] invalidate vcalloc_reqs[9].vc_sel.`1`[2] invalidate vcalloc_reqs[9].vc_sel.`1`[3] invalidate vcalloc_reqs[9].vc_sel.`1`[4] invalidate vcalloc_reqs[9].vc_sel.`1`[5] invalidate vcalloc_reqs[9].vc_sel.`1`[6] invalidate vcalloc_reqs[9].vc_sel.`1`[7] invalidate vcalloc_reqs[9].vc_sel.`1`[8] invalidate vcalloc_reqs[9].vc_sel.`1`[9] invalidate vcalloc_reqs[9].vc_sel.`2`[0] invalidate vcalloc_reqs[9].vc_sel.`2`[1] invalidate vcalloc_reqs[9].vc_sel.`2`[2] invalidate vcalloc_reqs[9].vc_sel.`2`[3] invalidate vcalloc_reqs[9].vc_sel.`2`[4] invalidate vcalloc_reqs[9].vc_sel.`2`[5] invalidate vcalloc_reqs[9].vc_sel.`2`[6] invalidate vcalloc_reqs[9].vc_sel.`2`[7] invalidate vcalloc_reqs[9].vc_sel.`2`[8] invalidate vcalloc_reqs[9].vc_sel.`2`[9] invalidate vcalloc_reqs[9].in_vc invalidate vcalloc_reqs[9].flow.egress_node_id invalidate vcalloc_reqs[9].flow.egress_node invalidate vcalloc_reqs[9].flow.ingress_node_id invalidate vcalloc_reqs[9].flow.ingress_node invalidate vcalloc_reqs[9].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_38 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_38 : node _T_39 = bits(vcalloc_sel, 0, 0) when _T_39 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_40 = eq(states[0].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_40, UInt<1>(0h1), "") : assert_3 node _T_44 = bits(vcalloc_sel, 1, 1) when _T_44 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_45 = eq(states[1].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_45, UInt<1>(0h1), "") : assert_4 node _T_49 = bits(vcalloc_sel, 2, 2) when _T_49 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_50 = eq(states[2].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_50, UInt<1>(0h1), "") : assert_5 node _T_54 = bits(vcalloc_sel, 3, 3) when _T_54 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_55 = eq(states[3].g, UInt<3>(0h2)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_55, UInt<1>(0h1), "") : assert_6 node _T_59 = bits(vcalloc_sel, 4, 4) when _T_59 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_60 = eq(states[4].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_60, UInt<1>(0h1), "") : assert_7 node _T_64 = bits(vcalloc_sel, 5, 5) when _T_64 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_65 = eq(states[5].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_65, UInt<1>(0h1), "") : assert_8 node _T_69 = bits(vcalloc_sel, 6, 6) when _T_69 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_70 = eq(states[6].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_70, UInt<1>(0h1), "") : assert_9 node _T_74 = bits(vcalloc_sel, 7, 7) when _T_74 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_75 = eq(states[7].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_75, UInt<1>(0h1), "") : assert_10 node _T_79 = bits(vcalloc_sel, 8, 8) when _T_79 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].g, UInt<3>(0h3) node _T_80 = eq(states[8].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_80, UInt<1>(0h1), "") : assert_11 node _T_84 = bits(vcalloc_sel, 9, 9) when _T_84 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].g, UInt<3>(0h3) node _T_85 = eq(states[9].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_85, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_312 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[9] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[9] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[9] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[9] connect salloc_arb.io.in[4].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[4].bits.tail invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[9] connect salloc_arb.io.in[5].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[5].bits.tail invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[5].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[5].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[5].bits.vc_sel.`2`[9] connect salloc_arb.io.in[6].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[6].bits.tail invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[9] connect salloc_arb.io.in[7].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[7].bits.tail invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[7].bits.vc_sel.`2`[9] node credit_available_lo_lo = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[8].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[8].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0]) node credit_available_lo_hi_hi_1 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[8].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5]) node credit_available_hi_hi_hi_1 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[8].vc_sel.`1`[7]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[8].vc_sel.`2`[1], states[8].vc_sel.`2`[0]) node credit_available_lo_hi_hi_2 = cat(states[8].vc_sel.`2`[4], states[8].vc_sel.`2`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[8].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[8].vc_sel.`2`[6], states[8].vc_sel.`2`[5]) node credit_available_hi_hi_hi_2 = cat(states[8].vc_sel.`2`[9], states[8].vc_sel.`2`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[8].vc_sel.`2`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, io.out_credit_available.`1`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_4 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, io.out_credit_available.`1`[7]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`2`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`2`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1] connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2] connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3] connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4] connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5] connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6] connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7] connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8] connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[1], states[8].vc_sel.`2`[1] connect salloc_arb.io.in[8].bits.vc_sel.`2`[2], states[8].vc_sel.`2`[2] connect salloc_arb.io.in[8].bits.vc_sel.`2`[3], states[8].vc_sel.`2`[3] connect salloc_arb.io.in[8].bits.vc_sel.`2`[4], states[8].vc_sel.`2`[4] connect salloc_arb.io.in[8].bits.vc_sel.`2`[5], states[8].vc_sel.`2`[5] connect salloc_arb.io.in[8].bits.vc_sel.`2`[6], states[8].vc_sel.`2`[6] connect salloc_arb.io.in[8].bits.vc_sel.`2`[7], states[8].vc_sel.`2`[7] connect salloc_arb.io.in[8].bits.vc_sel.`2`[8], states[8].vc_sel.`2`[8] connect salloc_arb.io.in[8].bits.vc_sel.`2`[9], states[8].vc_sel.`2`[9] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_89 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_90 = and(_T_89, input_buffer.io.deq[8].bits.tail) when _T_90 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready connect salloc_arb.io.in[9].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[9].bits.tail invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[9].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[9].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[9].bits.vc_sel.`2`[9] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[10] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_237 connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13 node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_256 connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14 node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_275 connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15 node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_294 connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16 node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298) node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299) node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300) node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301) node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302) node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303) node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_313 connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17 node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315) node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316) node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317) node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318) node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319) node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320) node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321) node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_332 connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18 node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334) node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335) node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336) node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_351 connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19 node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358) node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359) node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360) node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_370 connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20 node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373) node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374) node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375) node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376) node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377) node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378) node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379) node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_389 connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_22 : UInt<1>[10] node _vc_sel_T_390 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_391 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_392 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_393 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_394 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_395 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_396 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_397 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_398 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_400 = or(_vc_sel_T_390, _vc_sel_T_391) node _vc_sel_T_401 = or(_vc_sel_T_400, _vc_sel_T_392) node _vc_sel_T_402 = or(_vc_sel_T_401, _vc_sel_T_393) node _vc_sel_T_403 = or(_vc_sel_T_402, _vc_sel_T_394) node _vc_sel_T_404 = or(_vc_sel_T_403, _vc_sel_T_395) node _vc_sel_T_405 = or(_vc_sel_T_404, _vc_sel_T_396) node _vc_sel_T_406 = or(_vc_sel_T_405, _vc_sel_T_397) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_398) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_399) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_408 connect _vc_sel_WIRE_22[0], _vc_sel_WIRE_23 node _vc_sel_T_409 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_410 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_411 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_412 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_413 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_419 = or(_vc_sel_T_409, _vc_sel_T_410) node _vc_sel_T_420 = or(_vc_sel_T_419, _vc_sel_T_411) node _vc_sel_T_421 = or(_vc_sel_T_420, _vc_sel_T_412) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_413) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_414) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_415) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_416) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_417) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_418) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_427 connect _vc_sel_WIRE_22[1], _vc_sel_WIRE_24 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_436 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_437 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_438 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_430) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_431) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_432) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_433) node _vc_sel_T_443 = or(_vc_sel_T_442, _vc_sel_T_434) node _vc_sel_T_444 = or(_vc_sel_T_443, _vc_sel_T_435) node _vc_sel_T_445 = or(_vc_sel_T_444, _vc_sel_T_436) node _vc_sel_T_446 = or(_vc_sel_T_445, _vc_sel_T_437) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_446 connect _vc_sel_WIRE_22[2], _vc_sel_WIRE_25 node _vc_sel_T_447 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_451 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_452 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_453 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_454 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_455 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_456 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_457 = or(_vc_sel_T_447, _vc_sel_T_448) node _vc_sel_T_458 = or(_vc_sel_T_457, _vc_sel_T_449) node _vc_sel_T_459 = or(_vc_sel_T_458, _vc_sel_T_450) node _vc_sel_T_460 = or(_vc_sel_T_459, _vc_sel_T_451) node _vc_sel_T_461 = or(_vc_sel_T_460, _vc_sel_T_452) node _vc_sel_T_462 = or(_vc_sel_T_461, _vc_sel_T_453) node _vc_sel_T_463 = or(_vc_sel_T_462, _vc_sel_T_454) node _vc_sel_T_464 = or(_vc_sel_T_463, _vc_sel_T_455) node _vc_sel_T_465 = or(_vc_sel_T_464, _vc_sel_T_456) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_465 connect _vc_sel_WIRE_22[3], _vc_sel_WIRE_26 node _vc_sel_T_466 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_467 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_468 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_469 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_470 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_471 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_472 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_473 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_476 = or(_vc_sel_T_466, _vc_sel_T_467) node _vc_sel_T_477 = or(_vc_sel_T_476, _vc_sel_T_468) node _vc_sel_T_478 = or(_vc_sel_T_477, _vc_sel_T_469) node _vc_sel_T_479 = or(_vc_sel_T_478, _vc_sel_T_470) node _vc_sel_T_480 = or(_vc_sel_T_479, _vc_sel_T_471) node _vc_sel_T_481 = or(_vc_sel_T_480, _vc_sel_T_472) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_473) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_474) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_475) wire _vc_sel_WIRE_27 : UInt<1> connect _vc_sel_WIRE_27, _vc_sel_T_484 connect _vc_sel_WIRE_22[4], _vc_sel_WIRE_27 node _vc_sel_T_485 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_486 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_487 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_488 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_495 = or(_vc_sel_T_485, _vc_sel_T_486) node _vc_sel_T_496 = or(_vc_sel_T_495, _vc_sel_T_487) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_488) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_489) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_490) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_491) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_492) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_493) node _vc_sel_T_503 = or(_vc_sel_T_502, _vc_sel_T_494) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_503 connect _vc_sel_WIRE_22[5], _vc_sel_WIRE_28 node _vc_sel_T_504 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_511 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_512 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_513 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_514 = or(_vc_sel_T_504, _vc_sel_T_505) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_506) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_507) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_508) node _vc_sel_T_518 = or(_vc_sel_T_517, _vc_sel_T_509) node _vc_sel_T_519 = or(_vc_sel_T_518, _vc_sel_T_510) node _vc_sel_T_520 = or(_vc_sel_T_519, _vc_sel_T_511) node _vc_sel_T_521 = or(_vc_sel_T_520, _vc_sel_T_512) node _vc_sel_T_522 = or(_vc_sel_T_521, _vc_sel_T_513) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_522 connect _vc_sel_WIRE_22[6], _vc_sel_WIRE_29 node _vc_sel_T_523 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_526 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_527 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_528 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_529 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_530 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_531 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_532 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_533 = or(_vc_sel_T_523, _vc_sel_T_524) node _vc_sel_T_534 = or(_vc_sel_T_533, _vc_sel_T_525) node _vc_sel_T_535 = or(_vc_sel_T_534, _vc_sel_T_526) node _vc_sel_T_536 = or(_vc_sel_T_535, _vc_sel_T_527) node _vc_sel_T_537 = or(_vc_sel_T_536, _vc_sel_T_528) node _vc_sel_T_538 = or(_vc_sel_T_537, _vc_sel_T_529) node _vc_sel_T_539 = or(_vc_sel_T_538, _vc_sel_T_530) node _vc_sel_T_540 = or(_vc_sel_T_539, _vc_sel_T_531) node _vc_sel_T_541 = or(_vc_sel_T_540, _vc_sel_T_532) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_541 connect _vc_sel_WIRE_22[7], _vc_sel_WIRE_30 node _vc_sel_T_542 = mux(_vc_sel_T, states[0].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_543 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_544 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_545 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_546 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_547 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_548 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_552 = or(_vc_sel_T_542, _vc_sel_T_543) node _vc_sel_T_553 = or(_vc_sel_T_552, _vc_sel_T_544) node _vc_sel_T_554 = or(_vc_sel_T_553, _vc_sel_T_545) node _vc_sel_T_555 = or(_vc_sel_T_554, _vc_sel_T_546) node _vc_sel_T_556 = or(_vc_sel_T_555, _vc_sel_T_547) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_548) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_549) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_550) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_551) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_560 connect _vc_sel_WIRE_22[8], _vc_sel_WIRE_31 node _vc_sel_T_561 = mux(_vc_sel_T, states[0].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_562 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_563 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_561, _vc_sel_T_562) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_563) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_564) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_565) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_566) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_567) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_568) node _vc_sel_T_578 = or(_vc_sel_T_577, _vc_sel_T_569) node _vc_sel_T_579 = or(_vc_sel_T_578, _vc_sel_T_570) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_579 connect _vc_sel_WIRE_22[9], _vc_sel_WIRE_32 connect vc_sel.`2`, _vc_sel_WIRE_22 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4]) node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8]) node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9]) node _channel_oh_T_16 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[2]) node _channel_oh_T_18 = or(_channel_oh_T_17, vc_sel.`2`[3]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`2`[4]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`2`[5]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`2`[6]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`2`[7]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`2`[8]) node channel_oh_2 = or(_channel_oh_T_23, vc_sel.`2`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2]) node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5]) node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8]) node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7]) node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8) node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0) node _virt_channel_T_12 = orr(virt_channel_hi_5) node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5) node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4) node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0) node _virt_channel_T_14 = orr(virt_channel_hi_6) node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2) node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19) node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_lo_hi_2 = cat(virt_channel_lo_hi_hi_2, vc_sel.`2`[2]) node virt_channel_lo_8 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[6], vc_sel.`2`[5]) node virt_channel_hi_hi_hi_2 = cat(vc_sel.`2`[9], vc_sel.`2`[8]) node virt_channel_hi_hi_2 = cat(virt_channel_hi_hi_hi_2, vc_sel.`2`[7]) node virt_channel_hi_8 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_22 = cat(virt_channel_hi_8, virt_channel_lo_8) node virt_channel_hi_9 = bits(_virt_channel_T_22, 9, 8) node virt_channel_lo_9 = bits(_virt_channel_T_22, 7, 0) node _virt_channel_T_23 = orr(virt_channel_hi_9) node _virt_channel_T_24 = or(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = cat(_virt_channel_T_23, _virt_channel_T_31) node _virt_channel_T_33 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_2, _virt_channel_T_32, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_33, _virt_channel_T_34) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_35) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_37 node _T_91 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_91 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`0`[8] invalidate states[0].vc_sel.`0`[9] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`1`[8] invalidate states[0].vc_sel.`1`[9] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`2`[8] invalidate states[0].vc_sel.`2`[9] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`0`[5] invalidate states[1].vc_sel.`0`[6] invalidate states[1].vc_sel.`0`[7] invalidate states[1].vc_sel.`0`[8] invalidate states[1].vc_sel.`0`[9] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].vc_sel.`1`[5] invalidate states[1].vc_sel.`1`[6] invalidate states[1].vc_sel.`1`[7] invalidate states[1].vc_sel.`1`[8] invalidate states[1].vc_sel.`1`[9] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`2`[3] invalidate states[1].vc_sel.`2`[4] invalidate states[1].vc_sel.`2`[5] invalidate states[1].vc_sel.`2`[6] invalidate states[1].vc_sel.`2`[7] invalidate states[1].vc_sel.`2`[8] invalidate states[1].vc_sel.`2`[9] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`0`[5] invalidate states[2].vc_sel.`0`[6] invalidate states[2].vc_sel.`0`[7] invalidate states[2].vc_sel.`0`[8] invalidate states[2].vc_sel.`0`[9] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].vc_sel.`1`[5] invalidate states[2].vc_sel.`1`[6] invalidate states[2].vc_sel.`1`[7] invalidate states[2].vc_sel.`1`[8] invalidate states[2].vc_sel.`1`[9] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`2`[3] invalidate states[2].vc_sel.`2`[4] invalidate states[2].vc_sel.`2`[5] invalidate states[2].vc_sel.`2`[6] invalidate states[2].vc_sel.`2`[7] invalidate states[2].vc_sel.`2`[8] invalidate states[2].vc_sel.`2`[9] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`0`[5] invalidate states[3].vc_sel.`0`[6] invalidate states[3].vc_sel.`0`[7] invalidate states[3].vc_sel.`0`[8] invalidate states[3].vc_sel.`0`[9] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].vc_sel.`1`[5] invalidate states[3].vc_sel.`1`[6] invalidate states[3].vc_sel.`1`[7] invalidate states[3].vc_sel.`1`[8] invalidate states[3].vc_sel.`1`[9] invalidate states[3].vc_sel.`2`[0] invalidate states[3].vc_sel.`2`[1] invalidate states[3].vc_sel.`2`[2] invalidate states[3].vc_sel.`2`[3] invalidate states[3].vc_sel.`2`[4] invalidate states[3].vc_sel.`2`[5] invalidate states[3].vc_sel.`2`[6] invalidate states[3].vc_sel.`2`[7] invalidate states[3].vc_sel.`2`[8] invalidate states[3].vc_sel.`2`[9] invalidate states[3].g invalidate states[4].fifo_deps invalidate states[4].flow.egress_node_id invalidate states[4].flow.egress_node invalidate states[4].flow.ingress_node_id invalidate states[4].flow.ingress_node invalidate states[4].flow.vnet_id invalidate states[4].vc_sel.`0`[0] invalidate states[4].vc_sel.`0`[1] invalidate states[4].vc_sel.`0`[2] invalidate states[4].vc_sel.`0`[3] invalidate states[4].vc_sel.`0`[4] invalidate states[4].vc_sel.`0`[5] invalidate states[4].vc_sel.`0`[6] invalidate states[4].vc_sel.`0`[7] invalidate states[4].vc_sel.`0`[8] invalidate states[4].vc_sel.`0`[9] invalidate states[4].vc_sel.`1`[0] invalidate states[4].vc_sel.`1`[1] invalidate states[4].vc_sel.`1`[2] invalidate states[4].vc_sel.`1`[3] invalidate states[4].vc_sel.`1`[4] invalidate states[4].vc_sel.`1`[5] invalidate states[4].vc_sel.`1`[6] invalidate states[4].vc_sel.`1`[7] invalidate states[4].vc_sel.`1`[8] invalidate states[4].vc_sel.`1`[9] invalidate states[4].vc_sel.`2`[0] invalidate states[4].vc_sel.`2`[1] invalidate states[4].vc_sel.`2`[2] invalidate states[4].vc_sel.`2`[3] invalidate states[4].vc_sel.`2`[4] invalidate states[4].vc_sel.`2`[5] invalidate states[4].vc_sel.`2`[6] invalidate states[4].vc_sel.`2`[7] invalidate states[4].vc_sel.`2`[8] invalidate states[4].vc_sel.`2`[9] invalidate states[4].g invalidate states[5].fifo_deps invalidate states[5].flow.egress_node_id invalidate states[5].flow.egress_node invalidate states[5].flow.ingress_node_id invalidate states[5].flow.ingress_node invalidate states[5].flow.vnet_id invalidate states[5].vc_sel.`0`[0] invalidate states[5].vc_sel.`0`[1] invalidate states[5].vc_sel.`0`[2] invalidate states[5].vc_sel.`0`[3] invalidate states[5].vc_sel.`0`[4] invalidate states[5].vc_sel.`0`[5] invalidate states[5].vc_sel.`0`[6] invalidate states[5].vc_sel.`0`[7] invalidate states[5].vc_sel.`0`[8] invalidate states[5].vc_sel.`0`[9] invalidate states[5].vc_sel.`1`[0] invalidate states[5].vc_sel.`1`[1] invalidate states[5].vc_sel.`1`[2] invalidate states[5].vc_sel.`1`[3] invalidate states[5].vc_sel.`1`[4] invalidate states[5].vc_sel.`1`[5] invalidate states[5].vc_sel.`1`[6] invalidate states[5].vc_sel.`1`[7] invalidate states[5].vc_sel.`1`[8] invalidate states[5].vc_sel.`1`[9] invalidate states[5].vc_sel.`2`[0] invalidate states[5].vc_sel.`2`[1] invalidate states[5].vc_sel.`2`[2] invalidate states[5].vc_sel.`2`[3] invalidate states[5].vc_sel.`2`[4] invalidate states[5].vc_sel.`2`[5] invalidate states[5].vc_sel.`2`[6] invalidate states[5].vc_sel.`2`[7] invalidate states[5].vc_sel.`2`[8] invalidate states[5].vc_sel.`2`[9] invalidate states[5].g invalidate states[6].fifo_deps invalidate states[6].flow.egress_node_id invalidate states[6].flow.egress_node invalidate states[6].flow.ingress_node_id invalidate states[6].flow.ingress_node invalidate states[6].flow.vnet_id invalidate states[6].vc_sel.`0`[0] invalidate states[6].vc_sel.`0`[1] invalidate states[6].vc_sel.`0`[2] invalidate states[6].vc_sel.`0`[3] invalidate states[6].vc_sel.`0`[4] invalidate states[6].vc_sel.`0`[5] invalidate states[6].vc_sel.`0`[6] invalidate states[6].vc_sel.`0`[7] invalidate states[6].vc_sel.`0`[8] invalidate states[6].vc_sel.`0`[9] invalidate states[6].vc_sel.`1`[0] invalidate states[6].vc_sel.`1`[1] invalidate states[6].vc_sel.`1`[2] invalidate states[6].vc_sel.`1`[3] invalidate states[6].vc_sel.`1`[4] invalidate states[6].vc_sel.`1`[5] invalidate states[6].vc_sel.`1`[6] invalidate states[6].vc_sel.`1`[7] invalidate states[6].vc_sel.`1`[8] invalidate states[6].vc_sel.`1`[9] invalidate states[6].vc_sel.`2`[0] invalidate states[6].vc_sel.`2`[1] invalidate states[6].vc_sel.`2`[2] invalidate states[6].vc_sel.`2`[3] invalidate states[6].vc_sel.`2`[4] invalidate states[6].vc_sel.`2`[5] invalidate states[6].vc_sel.`2`[6] invalidate states[6].vc_sel.`2`[7] invalidate states[6].vc_sel.`2`[8] invalidate states[6].vc_sel.`2`[9] invalidate states[6].g invalidate states[7].fifo_deps invalidate states[7].flow.egress_node_id invalidate states[7].flow.egress_node invalidate states[7].flow.ingress_node_id invalidate states[7].flow.ingress_node invalidate states[7].flow.vnet_id invalidate states[7].vc_sel.`0`[0] invalidate states[7].vc_sel.`0`[1] invalidate states[7].vc_sel.`0`[2] invalidate states[7].vc_sel.`0`[3] invalidate states[7].vc_sel.`0`[4] invalidate states[7].vc_sel.`0`[5] invalidate states[7].vc_sel.`0`[6] invalidate states[7].vc_sel.`0`[7] invalidate states[7].vc_sel.`0`[8] invalidate states[7].vc_sel.`0`[9] invalidate states[7].vc_sel.`1`[0] invalidate states[7].vc_sel.`1`[1] invalidate states[7].vc_sel.`1`[2] invalidate states[7].vc_sel.`1`[3] invalidate states[7].vc_sel.`1`[4] invalidate states[7].vc_sel.`1`[5] invalidate states[7].vc_sel.`1`[6] invalidate states[7].vc_sel.`1`[7] invalidate states[7].vc_sel.`1`[8] invalidate states[7].vc_sel.`1`[9] invalidate states[7].vc_sel.`2`[0] invalidate states[7].vc_sel.`2`[1] invalidate states[7].vc_sel.`2`[2] invalidate states[7].vc_sel.`2`[3] invalidate states[7].vc_sel.`2`[4] invalidate states[7].vc_sel.`2`[5] invalidate states[7].vc_sel.`2`[6] invalidate states[7].vc_sel.`2`[7] invalidate states[7].vc_sel.`2`[8] invalidate states[7].vc_sel.`2`[9] invalidate states[7].g connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[0], UInt<1>(0h0) connect states[8].vc_sel.`1`[1], UInt<1>(0h0) connect states[8].vc_sel.`1`[2], UInt<1>(0h0) connect states[8].vc_sel.`1`[3], UInt<1>(0h0) connect states[8].vc_sel.`1`[4], UInt<1>(0h0) connect states[8].vc_sel.`1`[5], UInt<1>(0h0) connect states[8].vc_sel.`1`[6], UInt<1>(0h0) connect states[8].vc_sel.`1`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[8], UInt<1>(0h0) connect states[8].vc_sel.`1`[9], UInt<1>(0h0) connect states[8].vc_sel.`2`[0], UInt<1>(0h0) connect states[8].vc_sel.`2`[1], UInt<1>(0h0) connect states[8].vc_sel.`2`[2], UInt<1>(0h0) connect states[8].vc_sel.`2`[3], UInt<1>(0h0) connect states[8].vc_sel.`2`[4], UInt<1>(0h0) connect states[8].vc_sel.`2`[5], UInt<1>(0h0) connect states[8].vc_sel.`2`[6], UInt<1>(0h0) connect states[8].vc_sel.`2`[7], UInt<1>(0h0) connect states[8].vc_sel.`2`[8], UInt<1>(0h0) connect states[8].vc_sel.`2`[9], UInt<1>(0h0) invalidate states[9].fifo_deps invalidate states[9].flow.egress_node_id invalidate states[9].flow.egress_node invalidate states[9].flow.ingress_node_id invalidate states[9].flow.ingress_node invalidate states[9].flow.vnet_id invalidate states[9].vc_sel.`0`[0] invalidate states[9].vc_sel.`0`[1] invalidate states[9].vc_sel.`0`[2] invalidate states[9].vc_sel.`0`[3] invalidate states[9].vc_sel.`0`[4] invalidate states[9].vc_sel.`0`[5] invalidate states[9].vc_sel.`0`[6] invalidate states[9].vc_sel.`0`[7] invalidate states[9].vc_sel.`0`[8] invalidate states[9].vc_sel.`0`[9] invalidate states[9].vc_sel.`1`[0] invalidate states[9].vc_sel.`1`[1] invalidate states[9].vc_sel.`1`[2] invalidate states[9].vc_sel.`1`[3] invalidate states[9].vc_sel.`1`[4] invalidate states[9].vc_sel.`1`[5] invalidate states[9].vc_sel.`1`[6] invalidate states[9].vc_sel.`1`[7] invalidate states[9].vc_sel.`1`[8] invalidate states[9].vc_sel.`1`[9] invalidate states[9].vc_sel.`2`[0] invalidate states[9].vc_sel.`2`[1] invalidate states[9].vc_sel.`2`[2] invalidate states[9].vc_sel.`2`[3] invalidate states[9].vc_sel.`2`[4] invalidate states[9].vc_sel.`2`[5] invalidate states[9].vc_sel.`2`[6] invalidate states[9].vc_sel.`2`[7] invalidate states[9].vc_sel.`2`[8] invalidate states[9].vc_sel.`2`[9] invalidate states[9].g node _T_92 = asUInt(reset) when _T_92 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)

module InputUnit_116( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_8, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_1_9, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {1'h0, vcalloc_vals_8, 8'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : {1'h0, vcalloc_vals_8, 18'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_8; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_135 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_135( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h8)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h8)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = and(_T_16, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 node _T_29 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_29 : node _T_30 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_31 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_32 = and(_T_30, _T_31) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_33 = shr(io.in.a.bits.source, 4) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = leq(UInt<1>(0h0), uncommonBits_1) node _T_36 = and(_T_34, _T_35) node _T_37 = leq(uncommonBits_1, UInt<4>(0h8)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_40 = or(_T_38, _T_39) node _T_41 = and(_T_32, _T_40) node _T_42 = or(UInt<1>(0h0), _T_41) node _T_43 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<13>(0h1000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = or(_T_48, _T_53) node _T_60 = or(_T_59, _T_58) node _T_61 = and(_T_43, _T_60) node _T_62 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_63 = or(UInt<1>(0h0), _T_62) node _T_64 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<29>(0h10000000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = and(_T_63, _T_68) node _T_70 = or(UInt<1>(0h0), _T_61) node _T_71 = or(_T_70, _T_69) node _T_72 = and(_T_42, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_76 = shr(io.in.a.bits.source, 4) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_2) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_2, UInt<4>(0h8)) node _T_81 = and(_T_79, _T_80) node _T_82 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_81 connect _WIRE[1], _T_82 node _T_83 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_84 = mux(_WIRE[0], _T_83, UInt<1>(0h0)) node _T_85 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = or(_T_84, _T_85) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_86 node _T_87 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_88 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(UInt<1>(0h0), _T_89) node _T_91 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<13>(0h1000))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<18>(0h2f000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<29>(0h10000000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_95, _T_100) node _T_112 = or(_T_111, _T_105) node _T_113 = or(_T_112, _T_110) node _T_114 = and(_T_90, _T_113) node _T_115 = or(UInt<1>(0h0), _T_114) node _T_116 = and(_WIRE_1, _T_115) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_116, UInt<1>(0h1), "") : assert_3 node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(source_ok, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_123 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_123, UInt<1>(0h1), "") : assert_5 node _T_127 = asUInt(reset) node _T_128 = eq(_T_127, UInt<1>(0h0)) when _T_128 : node _T_129 = eq(is_aligned, UInt<1>(0h0)) when _T_129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_130 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_130, UInt<1>(0h1), "") : assert_7 node _T_134 = not(io.in.a.bits.mask) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_135, UInt<1>(0h1), "") : assert_8 node _T_139 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_139, UInt<1>(0h1), "") : assert_9 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_147 = shr(io.in.a.bits.source, 4) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = leq(UInt<1>(0h0), uncommonBits_3) node _T_150 = and(_T_148, _T_149) node _T_151 = leq(uncommonBits_3, UInt<4>(0h8)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_154 = or(_T_152, _T_153) node _T_155 = and(_T_146, _T_154) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_158 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_159 = cvt(_T_158) node _T_160 = and(_T_159, asSInt(UInt<13>(0h1000))) node _T_161 = asSInt(_T_160) node _T_162 = eq(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<18>(0h2f000))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<13>(0h1000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_162, _T_167) node _T_174 = or(_T_173, _T_172) node _T_175 = and(_T_157, _T_174) node _T_176 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<29>(0h10000000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = and(_T_177, _T_182) node _T_184 = or(UInt<1>(0h0), _T_175) node _T_185 = or(_T_184, _T_183) node _T_186 = and(_T_156, _T_185) node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_T_186, UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_186, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_190 = shr(io.in.a.bits.source, 4) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = leq(UInt<1>(0h0), uncommonBits_4) node _T_193 = and(_T_191, _T_192) node _T_194 = leq(uncommonBits_4, UInt<4>(0h8)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.a.bits.source, UInt<4>(0h9)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_195 connect _WIRE_2[1], _T_196 node _T_197 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_198 = mux(_WIRE_2[0], _T_197, UInt<1>(0h0)) node _T_199 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = or(_T_198, _T_199) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_200 node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_203 = and(_T_201, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<18>(0h2f000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<29>(0h10000000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = or(_T_209, _T_214) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_224) node _T_228 = and(_T_204, _T_227) node _T_229 = or(UInt<1>(0h0), _T_228) node _T_230 = and(_WIRE_3, _T_229) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_230, UInt<1>(0h1), "") : assert_11 node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(source_ok, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_237 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(_T_237, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_237, UInt<1>(0h1), "") : assert_13 node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(is_aligned, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_244 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(_T_244, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_244, UInt<1>(0h1), "") : assert_15 node _T_248 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_248, UInt<1>(0h1), "") : assert_16 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_253, UInt<1>(0h1), "") : assert_17 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_257, UInt<1>(0h1), "") : assert_18 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_265 = shr(io.in.a.bits.source, 4) node _T_266 = eq(_T_265, UInt<1>(0h0)) node _T_267 = leq(UInt<1>(0h0), uncommonBits_5) node _T_268 = and(_T_266, _T_267) node _T_269 = leq(uncommonBits_5, UInt<4>(0h8)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_272 = or(_T_270, _T_271) node _T_273 = and(_T_264, _T_272) node _T_274 = or(UInt<1>(0h0), _T_273) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_274, UInt<1>(0h1), "") : assert_19 node _T_278 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_279 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_280 = and(_T_278, _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<13>(0h1000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = and(_T_281, _T_286) node _T_288 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_289 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_290 = and(_T_288, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<18>(0h2f000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_298 = cvt(_T_297) node _T_299 = and(_T_298, asSInt(UInt<13>(0h1000))) node _T_300 = asSInt(_T_299) node _T_301 = eq(_T_300, asSInt(UInt<1>(0h0))) node _T_302 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_303 = cvt(_T_302) node _T_304 = and(_T_303, asSInt(UInt<29>(0h10000000))) node _T_305 = asSInt(_T_304) node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0))) node _T_307 = or(_T_296, _T_301) node _T_308 = or(_T_307, _T_306) node _T_309 = and(_T_291, _T_308) node _T_310 = or(UInt<1>(0h0), _T_287) node _T_311 = or(_T_310, _T_309) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_311, UInt<1>(0h1), "") : assert_20 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(source_ok, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(is_aligned, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_321 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : node _T_324 = eq(_T_321, UInt<1>(0h0)) when _T_324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_321, UInt<1>(0h1), "") : assert_23 node _T_325 = eq(io.in.a.bits.mask, mask) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_325, UInt<1>(0h1), "") : assert_24 node _T_329 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_330 = asUInt(reset) node _T_331 = eq(_T_330, UInt<1>(0h0)) when _T_331 : node _T_332 = eq(_T_329, UInt<1>(0h0)) when _T_332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_329, UInt<1>(0h1), "") : assert_25 node _T_333 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_333 : node _T_334 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_335 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_337 = shr(io.in.a.bits.source, 4) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_6) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_6, UInt<4>(0h8)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_344 = or(_T_342, _T_343) node _T_345 = and(_T_336, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_348 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_349 = and(_T_347, _T_348) node _T_350 = or(UInt<1>(0h0), _T_349) node _T_351 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<13>(0h1000))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = and(_T_350, _T_355) node _T_357 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_358 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_359 = and(_T_357, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_362 = cvt(_T_361) node _T_363 = and(_T_362, asSInt(UInt<18>(0h2f000))) node _T_364 = asSInt(_T_363) node _T_365 = eq(_T_364, asSInt(UInt<1>(0h0))) node _T_366 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_367 = cvt(_T_366) node _T_368 = and(_T_367, asSInt(UInt<13>(0h1000))) node _T_369 = asSInt(_T_368) node _T_370 = eq(_T_369, asSInt(UInt<1>(0h0))) node _T_371 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_372 = cvt(_T_371) node _T_373 = and(_T_372, asSInt(UInt<29>(0h10000000))) node _T_374 = asSInt(_T_373) node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0))) node _T_376 = or(_T_365, _T_370) node _T_377 = or(_T_376, _T_375) node _T_378 = and(_T_360, _T_377) node _T_379 = or(UInt<1>(0h0), _T_356) node _T_380 = or(_T_379, _T_378) node _T_381 = and(_T_346, _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_381, UInt<1>(0h1), "") : assert_26 node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(source_ok, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(is_aligned, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_391 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_391, UInt<1>(0h1), "") : assert_29 node _T_395 = eq(io.in.a.bits.mask, mask) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_395, UInt<1>(0h1), "") : assert_30 node _T_399 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_403 = shr(io.in.a.bits.source, 4) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = leq(UInt<1>(0h0), uncommonBits_7) node _T_406 = and(_T_404, _T_405) node _T_407 = leq(uncommonBits_7, UInt<4>(0h8)) node _T_408 = and(_T_406, _T_407) node _T_409 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_410 = or(_T_408, _T_409) node _T_411 = and(_T_402, _T_410) node _T_412 = or(UInt<1>(0h0), _T_411) node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<18>(0h2f000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<13>(0h1000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<29>(0h10000000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = or(_T_431, _T_436) node _T_443 = or(_T_442, _T_441) node _T_444 = and(_T_426, _T_443) node _T_445 = or(UInt<1>(0h0), _T_422) node _T_446 = or(_T_445, _T_444) node _T_447 = and(_T_412, _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_447, UInt<1>(0h1), "") : assert_31 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_457, UInt<1>(0h1), "") : assert_34 node _T_461 = not(mask) node _T_462 = and(io.in.a.bits.mask, _T_461) node _T_463 = eq(_T_462, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_463, UInt<1>(0h1), "") : assert_35 node _T_467 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_471 = shr(io.in.a.bits.source, 4) node _T_472 = eq(_T_471, UInt<1>(0h0)) node _T_473 = leq(UInt<1>(0h0), uncommonBits_8) node _T_474 = and(_T_472, _T_473) node _T_475 = leq(uncommonBits_8, UInt<4>(0h8)) node _T_476 = and(_T_474, _T_475) node _T_477 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_478 = or(_T_476, _T_477) node _T_479 = and(_T_470, _T_478) node _T_480 = or(UInt<1>(0h0), _T_479) node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_482 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_491 = cvt(_T_490) node _T_492 = and(_T_491, asSInt(UInt<18>(0h2f000))) node _T_493 = asSInt(_T_492) node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0))) node _T_495 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<13>(0h1000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<29>(0h10000000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = or(_T_489, _T_494) node _T_506 = or(_T_505, _T_499) node _T_507 = or(_T_506, _T_504) node _T_508 = and(_T_484, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = and(_T_480, _T_509) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_510, UInt<1>(0h1), "") : assert_36 node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(source_ok, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(is_aligned, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_520 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_520, UInt<1>(0h1), "") : assert_39 node _T_524 = eq(io.in.a.bits.mask, mask) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_524, UInt<1>(0h1), "") : assert_40 node _T_528 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_528 : node _T_529 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_530 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_532 = shr(io.in.a.bits.source, 4) node _T_533 = eq(_T_532, UInt<1>(0h0)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<4>(0h8)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_539 = or(_T_537, _T_538) node _T_540 = and(_T_531, _T_539) node _T_541 = or(UInt<1>(0h0), _T_540) node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_544 = and(_T_542, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<18>(0h2f000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<13>(0h1000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<29>(0h10000000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = or(_T_550, _T_555) node _T_567 = or(_T_566, _T_560) node _T_568 = or(_T_567, _T_565) node _T_569 = and(_T_545, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = and(_T_541, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_571, UInt<1>(0h1), "") : assert_41 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(source_ok, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_581 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_581, UInt<1>(0h1), "") : assert_44 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_585, UInt<1>(0h1), "") : assert_45 node _T_589 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_593 = shr(io.in.a.bits.source, 4) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_10) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_10, UInt<4>(0h8)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.a.bits.source, UInt<4>(0h9)) node _T_600 = or(_T_598, _T_599) node _T_601 = and(_T_592, _T_600) node _T_602 = or(UInt<1>(0h0), _T_601) node _T_603 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_604 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_605 = and(_T_603, _T_604) node _T_606 = or(UInt<1>(0h0), _T_605) node _T_607 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_608 = cvt(_T_607) node _T_609 = and(_T_608, asSInt(UInt<13>(0h1000))) node _T_610 = asSInt(_T_609) node _T_611 = eq(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = and(_T_606, _T_611) node _T_613 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_614 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<18>(0h2f000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = or(_T_618, _T_623) node _T_625 = and(_T_613, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<29>(0h10000000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = and(_T_629, _T_634) node _T_636 = or(UInt<1>(0h0), _T_612) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_635) node _T_639 = and(_T_602, _T_638) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_639, UInt<1>(0h1), "") : assert_46 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(source_ok, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(is_aligned, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_649 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_649, UInt<1>(0h1), "") : assert_49 node _T_653 = eq(io.in.a.bits.mask, mask) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_653, UInt<1>(0h1), "") : assert_50 node _T_657 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(_T_657, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_657, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_661 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_661, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_7 = shr(io.in.d.bits.source, 4) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<4>(0h8)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.d.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_12 connect _source_ok_WIRE_1[1], _source_ok_T_13 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_665 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_665 : node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(source_ok_1, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_669 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_669, UInt<1>(0h1), "") : assert_54 node _T_673 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_673, UInt<1>(0h1), "") : assert_55 node _T_677 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_T_677, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_677, UInt<1>(0h1), "") : assert_56 node _T_681 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_681, UInt<1>(0h1), "") : assert_57 node _T_685 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_685 : node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(source_ok_1, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(sink_ok, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_692 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_692, UInt<1>(0h1), "") : assert_60 node _T_696 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_696, UInt<1>(0h1), "") : assert_61 node _T_700 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_700, UInt<1>(0h1), "") : assert_62 node _T_704 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_704, UInt<1>(0h1), "") : assert_63 node _T_708 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_709 = or(UInt<1>(0h1), _T_708) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_709, UInt<1>(0h1), "") : assert_64 node _T_713 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_713 : node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(source_ok_1, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(sink_ok, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_720 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_720, UInt<1>(0h1), "") : assert_67 node _T_724 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_724, UInt<1>(0h1), "") : assert_68 node _T_728 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_728, UInt<1>(0h1), "") : assert_69 node _T_732 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_733 = or(_T_732, io.in.d.bits.corrupt) node _T_734 = asUInt(reset) node _T_735 = eq(_T_734, UInt<1>(0h0)) when _T_735 : node _T_736 = eq(_T_733, UInt<1>(0h0)) when _T_736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_733, UInt<1>(0h1), "") : assert_70 node _T_737 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_738 = or(UInt<1>(0h1), _T_737) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_738, UInt<1>(0h1), "") : assert_71 node _T_742 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_742 : node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(source_ok_1, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_746 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_746, UInt<1>(0h1), "") : assert_73 node _T_750 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_750, UInt<1>(0h1), "") : assert_74 node _T_754 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_755 = or(UInt<1>(0h1), _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_755, UInt<1>(0h1), "") : assert_75 node _T_759 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_759 : node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(source_ok_1, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_763 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_763, UInt<1>(0h1), "") : assert_77 node _T_767 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_768 = or(_T_767, io.in.d.bits.corrupt) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_768, UInt<1>(0h1), "") : assert_78 node _T_772 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_773 = or(UInt<1>(0h1), _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_773, UInt<1>(0h1), "") : assert_79 node _T_777 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_777 : node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(source_ok_1, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_781 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_781, UInt<1>(0h1), "") : assert_81 node _T_785 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_785, UInt<1>(0h1), "") : assert_82 node _T_789 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_790 = or(UInt<1>(0h1), _T_789) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_790, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_794 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_794, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_798 = shr(io.in.b.bits.source, 4) node _T_799 = eq(_T_798, UInt<1>(0h0)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_11) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_11, UInt<4>(0h8)) node _T_803 = and(_T_801, _T_802) node _T_804 = eq(_T_803, UInt<1>(0h0)) node _T_805 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_804, _T_809) node _T_811 = eq(io.in.b.bits.source, UInt<4>(0h9)) node _T_812 = eq(_T_811, UInt<1>(0h0)) node _T_813 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = or(_T_812, _T_817) node _T_819 = and(_T_810, _T_818) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_819, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<13>(0h1000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<29>(0h10000000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[5] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 node _address_ok_T_25 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_26 = or(_address_ok_T_25, _address_ok_WIRE[2]) node _address_ok_T_27 = or(_address_ok_T_26, _address_ok_WIRE[3]) node address_ok = or(_address_ok_T_27, _address_ok_WIRE[4]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0) node _legal_source_T = shr(io.in.b.bits.source, 4) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h8)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<4>(0h9)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 node _legal_source_T_7 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_8 = mux(_legal_source_WIRE[1], UInt<4>(0h9), UInt<1>(0h0)) node _legal_source_T_9 = or(_legal_source_T_7, _legal_source_T_8) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_9 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_823 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_823 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_824 = shr(io.in.b.bits.source, 4) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_12) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_12, UInt<4>(0h8)) node _T_829 = and(_T_827, _T_828) node _T_830 = eq(io.in.b.bits.source, UInt<4>(0h9)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_829 connect _WIRE_4[1], _T_830 node _T_831 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_832 = mux(_WIRE_4[0], _T_831, UInt<1>(0h0)) node _T_833 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_834 = or(_T_832, _T_833) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_834 node _T_835 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_836 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_837 = and(_T_835, _T_836) node _T_838 = or(UInt<1>(0h0), _T_837) node _T_839 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<18>(0h2f000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<29>(0h10000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = or(_T_843, _T_848) node _T_860 = or(_T_859, _T_853) node _T_861 = or(_T_860, _T_858) node _T_862 = and(_T_838, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = and(_WIRE_5, _T_863) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_864, UInt<1>(0h1), "") : assert_86 node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(address_ok, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(legal_source, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(is_aligned_1, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_877 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_877, UInt<1>(0h1), "") : assert_90 node _T_881 = eq(io.in.b.bits.mask, mask_1) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_881, UInt<1>(0h1), "") : assert_91 node _T_885 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_885, UInt<1>(0h1), "") : assert_92 node _T_889 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_889 : node _T_890 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_891 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_892 = and(_T_890, _T_891) node _T_893 = or(UInt<1>(0h0), _T_892) node _T_894 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<18>(0h2f000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = or(_T_898, _T_903) node _T_915 = or(_T_914, _T_908) node _T_916 = or(_T_915, _T_913) node _T_917 = and(_T_893, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(UInt<1>(0h0), _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_919, UInt<1>(0h1), "") : assert_93 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(legal_source, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(is_aligned_1, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_932 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_932, UInt<1>(0h1), "") : assert_97 node _T_936 = eq(io.in.b.bits.mask, mask_1) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_936, UInt<1>(0h1), "") : assert_98 node _T_940 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_940, UInt<1>(0h1), "") : assert_99 node _T_944 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_944 : node _T_945 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_946 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_947 = and(_T_945, _T_946) node _T_948 = or(UInt<1>(0h0), _T_947) node _T_949 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_950 = cvt(_T_949) node _T_951 = and(_T_950, asSInt(UInt<13>(0h1000))) node _T_952 = asSInt(_T_951) node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0))) node _T_954 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_955 = cvt(_T_954) node _T_956 = and(_T_955, asSInt(UInt<18>(0h2f000))) node _T_957 = asSInt(_T_956) node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0))) node _T_959 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_960 = cvt(_T_959) node _T_961 = and(_T_960, asSInt(UInt<13>(0h1000))) node _T_962 = asSInt(_T_961) node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0))) node _T_964 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_965 = cvt(_T_964) node _T_966 = and(_T_965, asSInt(UInt<29>(0h10000000))) node _T_967 = asSInt(_T_966) node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0))) node _T_969 = or(_T_953, _T_958) node _T_970 = or(_T_969, _T_963) node _T_971 = or(_T_970, _T_968) node _T_972 = and(_T_948, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = and(UInt<1>(0h0), _T_973) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_974, UInt<1>(0h1), "") : assert_100 node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(address_ok, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(legal_source, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(is_aligned_1, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_987 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_987, UInt<1>(0h1), "") : assert_104 node _T_991 = eq(io.in.b.bits.mask, mask_1) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_991, UInt<1>(0h1), "") : assert_105 node _T_995 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_995 : node _T_996 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_997 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<13>(0h1000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<18>(0h2f000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<13>(0h1000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1016 = cvt(_T_1015) node _T_1017 = and(_T_1016, asSInt(UInt<29>(0h10000000))) node _T_1018 = asSInt(_T_1017) node _T_1019 = eq(_T_1018, asSInt(UInt<1>(0h0))) node _T_1020 = or(_T_1004, _T_1009) node _T_1021 = or(_T_1020, _T_1014) node _T_1022 = or(_T_1021, _T_1019) node _T_1023 = and(_T_999, _T_1022) node _T_1024 = or(UInt<1>(0h0), _T_1023) node _T_1025 = and(UInt<1>(0h0), _T_1024) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_106 node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(address_ok, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(legal_source, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1038 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_110 node _T_1042 = not(mask_1) node _T_1043 = and(io.in.b.bits.mask, _T_1042) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_111 node _T_1048 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1048 : node _T_1049 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1050 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = or(UInt<1>(0h0), _T_1051) node _T_1053 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1054 = cvt(_T_1053) node _T_1055 = and(_T_1054, asSInt(UInt<13>(0h1000))) node _T_1056 = asSInt(_T_1055) node _T_1057 = eq(_T_1056, asSInt(UInt<1>(0h0))) node _T_1058 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1059 = cvt(_T_1058) node _T_1060 = and(_T_1059, asSInt(UInt<18>(0h2f000))) node _T_1061 = asSInt(_T_1060) node _T_1062 = eq(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1069 = cvt(_T_1068) node _T_1070 = and(_T_1069, asSInt(UInt<29>(0h10000000))) node _T_1071 = asSInt(_T_1070) node _T_1072 = eq(_T_1071, asSInt(UInt<1>(0h0))) node _T_1073 = or(_T_1057, _T_1062) node _T_1074 = or(_T_1073, _T_1067) node _T_1075 = or(_T_1074, _T_1072) node _T_1076 = and(_T_1052, _T_1075) node _T_1077 = or(UInt<1>(0h0), _T_1076) node _T_1078 = and(UInt<1>(0h0), _T_1077) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_112 node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(address_ok, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(legal_source, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1091 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_116 node _T_1095 = eq(io.in.b.bits.mask, mask_1) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_117 node _T_1099 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1099 : node _T_1100 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1101 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = or(UInt<1>(0h0), _T_1102) node _T_1104 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1105 = cvt(_T_1104) node _T_1106 = and(_T_1105, asSInt(UInt<13>(0h1000))) node _T_1107 = asSInt(_T_1106) node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0))) node _T_1109 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1110 = cvt(_T_1109) node _T_1111 = and(_T_1110, asSInt(UInt<18>(0h2f000))) node _T_1112 = asSInt(_T_1111) node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0))) node _T_1114 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1115 = cvt(_T_1114) node _T_1116 = and(_T_1115, asSInt(UInt<13>(0h1000))) node _T_1117 = asSInt(_T_1116) node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0))) node _T_1119 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<29>(0h10000000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = or(_T_1108, _T_1113) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = or(_T_1125, _T_1123) node _T_1127 = and(_T_1103, _T_1126) node _T_1128 = or(UInt<1>(0h0), _T_1127) node _T_1129 = and(UInt<1>(0h0), _T_1128) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_118 node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(address_ok, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(legal_source, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1142 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_122 node _T_1146 = eq(io.in.b.bits.mask, mask_1) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_123 node _T_1150 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1150 : node _T_1151 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1152 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1156 = cvt(_T_1155) node _T_1157 = and(_T_1156, asSInt(UInt<13>(0h1000))) node _T_1158 = asSInt(_T_1157) node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0))) node _T_1160 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<18>(0h2f000))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1166 = cvt(_T_1165) node _T_1167 = and(_T_1166, asSInt(UInt<13>(0h1000))) node _T_1168 = asSInt(_T_1167) node _T_1169 = eq(_T_1168, asSInt(UInt<1>(0h0))) node _T_1170 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<29>(0h10000000))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1159, _T_1164) node _T_1176 = or(_T_1175, _T_1169) node _T_1177 = or(_T_1176, _T_1174) node _T_1178 = and(_T_1154, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = and(UInt<1>(0h0), _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_124 node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(address_ok, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(legal_source, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1193 = eq(io.in.b.bits.mask, mask_1) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_128 node _T_1197 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1201 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_14 = shr(io.in.c.bits.source, 4) node _source_ok_T_15 = eq(_source_ok_T_14, UInt<1>(0h0)) node _source_ok_T_16 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_T_18 = leq(source_ok_uncommonBits_2, UInt<4>(0h8)) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = eq(io.in.c.bits.source, UInt<4>(0h9)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_19 connect _source_ok_WIRE_2[1], _source_ok_T_20 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_28 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_29 = cvt(_address_ok_T_28) node _address_ok_T_30 = and(_address_ok_T_29, asSInt(UInt<13>(0h1000))) node _address_ok_T_31 = asSInt(_address_ok_T_30) node _address_ok_T_32 = eq(_address_ok_T_31, asSInt(UInt<1>(0h0))) node _address_ok_T_33 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_34 = cvt(_address_ok_T_33) node _address_ok_T_35 = and(_address_ok_T_34, asSInt(UInt<13>(0h1000))) node _address_ok_T_36 = asSInt(_address_ok_T_35) node _address_ok_T_37 = eq(_address_ok_T_36, asSInt(UInt<1>(0h0))) node _address_ok_T_38 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_39 = cvt(_address_ok_T_38) node _address_ok_T_40 = and(_address_ok_T_39, asSInt(UInt<13>(0h1000))) node _address_ok_T_41 = asSInt(_address_ok_T_40) node _address_ok_T_42 = eq(_address_ok_T_41, asSInt(UInt<1>(0h0))) node _address_ok_T_43 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_44 = cvt(_address_ok_T_43) node _address_ok_T_45 = and(_address_ok_T_44, asSInt(UInt<13>(0h1000))) node _address_ok_T_46 = asSInt(_address_ok_T_45) node _address_ok_T_47 = eq(_address_ok_T_46, asSInt(UInt<1>(0h0))) node _address_ok_T_48 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_49 = cvt(_address_ok_T_48) node _address_ok_T_50 = and(_address_ok_T_49, asSInt(UInt<29>(0h10000000))) node _address_ok_T_51 = asSInt(_address_ok_T_50) node _address_ok_T_52 = eq(_address_ok_T_51, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[5] connect _address_ok_WIRE_1[0], _address_ok_T_32 connect _address_ok_WIRE_1[1], _address_ok_T_37 connect _address_ok_WIRE_1[2], _address_ok_T_42 connect _address_ok_WIRE_1[3], _address_ok_T_47 connect _address_ok_WIRE_1[4], _address_ok_T_52 node _address_ok_T_53 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_54 = or(_address_ok_T_53, _address_ok_WIRE_1[2]) node _address_ok_T_55 = or(_address_ok_T_54, _address_ok_WIRE_1[3]) node address_ok_1 = or(_address_ok_T_55, _address_ok_WIRE_1[4]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_1205 = shr(io.in.c.bits.source, 4) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) node _T_1207 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1208 = and(_T_1206, _T_1207) node _T_1209 = leq(uncommonBits_13, UInt<4>(0h8)) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = or(_T_1211, _T_1216) node _T_1218 = eq(io.in.c.bits.source, UInt<4>(0h9)) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = or(_T_1219, _T_1224) node _T_1226 = and(_T_1217, _T_1225) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_131 node _T_1230 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1230 : node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(address_ok_1, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(source_ok_2, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1237 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_134 node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_136 node _T_1248 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_137 node _T_1252 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1252 : node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(address_ok_1, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(source_ok_2, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1259 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_140 node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1266 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_142 node _T_1270 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1270 : node _T_1271 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1272 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1273 = and(_T_1271, _T_1272) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_1274 = shr(io.in.c.bits.source, 4) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = leq(uncommonBits_14, UInt<4>(0h8)) node _T_1279 = and(_T_1277, _T_1278) node _T_1280 = eq(io.in.c.bits.source, UInt<4>(0h9)) node _T_1281 = or(_T_1279, _T_1280) node _T_1282 = and(_T_1273, _T_1281) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1285 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<18>(0h2f000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<13>(0h1000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = or(_T_1289, _T_1294) node _T_1301 = or(_T_1300, _T_1299) node _T_1302 = and(_T_1284, _T_1301) node _T_1303 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1304 = or(UInt<1>(0h0), _T_1303) node _T_1305 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = and(_T_1304, _T_1309) node _T_1311 = or(UInt<1>(0h0), _T_1302) node _T_1312 = or(_T_1311, _T_1310) node _T_1313 = and(_T_1283, _T_1312) node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(_T_1313, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1313, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_1317 = shr(io.in.c.bits.source, 4) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = leq(UInt<1>(0h0), uncommonBits_15) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = leq(uncommonBits_15, UInt<4>(0h8)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = eq(io.in.c.bits.source, UInt<4>(0h9)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1322 connect _WIRE_6[1], _T_1323 node _T_1324 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1325 = mux(_WIRE_6[0], _T_1324, UInt<1>(0h0)) node _T_1326 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1327 = or(_T_1325, _T_1326) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1327 node _T_1328 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1329 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = or(UInt<1>(0h0), _T_1330) node _T_1332 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<13>(0h1000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1338 = cvt(_T_1337) node _T_1339 = and(_T_1338, asSInt(UInt<18>(0h2f000))) node _T_1340 = asSInt(_T_1339) node _T_1341 = eq(_T_1340, asSInt(UInt<1>(0h0))) node _T_1342 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1343 = cvt(_T_1342) node _T_1344 = and(_T_1343, asSInt(UInt<13>(0h1000))) node _T_1345 = asSInt(_T_1344) node _T_1346 = eq(_T_1345, asSInt(UInt<1>(0h0))) node _T_1347 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1348 = cvt(_T_1347) node _T_1349 = and(_T_1348, asSInt(UInt<29>(0h10000000))) node _T_1350 = asSInt(_T_1349) node _T_1351 = eq(_T_1350, asSInt(UInt<1>(0h0))) node _T_1352 = or(_T_1336, _T_1341) node _T_1353 = or(_T_1352, _T_1346) node _T_1354 = or(_T_1353, _T_1351) node _T_1355 = and(_T_1331, _T_1354) node _T_1356 = or(UInt<1>(0h0), _T_1355) node _T_1357 = and(_WIRE_7, _T_1356) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_144 node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(source_ok_2, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1364 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_146 node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1371 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_148 node _T_1375 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_149 node _T_1379 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1379 : node _T_1380 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1381 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1382 = and(_T_1380, _T_1381) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_1383 = shr(io.in.c.bits.source, 4) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) node _T_1385 = leq(UInt<1>(0h0), uncommonBits_16) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = leq(uncommonBits_16, UInt<4>(0h8)) node _T_1388 = and(_T_1386, _T_1387) node _T_1389 = eq(io.in.c.bits.source, UInt<4>(0h9)) node _T_1390 = or(_T_1388, _T_1389) node _T_1391 = and(_T_1382, _T_1390) node _T_1392 = or(UInt<1>(0h0), _T_1391) node _T_1393 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1394 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1395 = cvt(_T_1394) node _T_1396 = and(_T_1395, asSInt(UInt<13>(0h1000))) node _T_1397 = asSInt(_T_1396) node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0))) node _T_1399 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1400 = cvt(_T_1399) node _T_1401 = and(_T_1400, asSInt(UInt<18>(0h2f000))) node _T_1402 = asSInt(_T_1401) node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0))) node _T_1404 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1405 = cvt(_T_1404) node _T_1406 = and(_T_1405, asSInt(UInt<13>(0h1000))) node _T_1407 = asSInt(_T_1406) node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0))) node _T_1409 = or(_T_1398, _T_1403) node _T_1410 = or(_T_1409, _T_1408) node _T_1411 = and(_T_1393, _T_1410) node _T_1412 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1413 = or(UInt<1>(0h0), _T_1412) node _T_1414 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1415 = cvt(_T_1414) node _T_1416 = and(_T_1415, asSInt(UInt<29>(0h10000000))) node _T_1417 = asSInt(_T_1416) node _T_1418 = eq(_T_1417, asSInt(UInt<1>(0h0))) node _T_1419 = and(_T_1413, _T_1418) node _T_1420 = or(UInt<1>(0h0), _T_1411) node _T_1421 = or(_T_1420, _T_1419) node _T_1422 = and(_T_1392, _T_1421) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_1426 = shr(io.in.c.bits.source, 4) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) node _T_1428 = leq(UInt<1>(0h0), uncommonBits_17) node _T_1429 = and(_T_1427, _T_1428) node _T_1430 = leq(uncommonBits_17, UInt<4>(0h8)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = eq(io.in.c.bits.source, UInt<4>(0h9)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_1431 connect _WIRE_8[1], _T_1432 node _T_1433 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1434 = mux(_WIRE_8[0], _T_1433, UInt<1>(0h0)) node _T_1435 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1436 = or(_T_1434, _T_1435) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1436 node _T_1437 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1438 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = or(UInt<1>(0h0), _T_1439) node _T_1441 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<13>(0h1000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1447 = cvt(_T_1446) node _T_1448 = and(_T_1447, asSInt(UInt<18>(0h2f000))) node _T_1449 = asSInt(_T_1448) node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1452 = cvt(_T_1451) node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000))) node _T_1454 = asSInt(_T_1453) node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0))) node _T_1456 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = or(_T_1445, _T_1450) node _T_1462 = or(_T_1461, _T_1455) node _T_1463 = or(_T_1462, _T_1460) node _T_1464 = and(_T_1440, _T_1463) node _T_1465 = or(UInt<1>(0h0), _T_1464) node _T_1466 = and(_WIRE_9, _T_1465) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_151 node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(source_ok_2, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1473 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_153 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1480 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_155 node _T_1484 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1484 : node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(address_ok_1, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(source_ok_2, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1494 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_159 node _T_1498 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_160 node _T_1502 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1502 : node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(address_ok_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(source_ok_2, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1512 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_164 node _T_1516 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1516 : node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(address_ok_1, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(source_ok_2, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1523 = asUInt(reset) node _T_1524 = eq(_T_1523, UInt<1>(0h0)) when _T_1524 : node _T_1525 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1526 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1527 = asUInt(reset) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = eq(_T_1526, UInt<1>(0h0)) when _T_1529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1526, UInt<1>(0h1), "") : assert_168 node _T_1530 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(_T_1530, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1530, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1537 = eq(a_first, UInt<1>(0h0)) node _T_1538 = and(io.in.a.valid, _T_1537) when _T_1538 : node _T_1539 = eq(io.in.a.bits.opcode, opcode) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_171 node _T_1543 = eq(io.in.a.bits.param, param) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_172 node _T_1547 = eq(io.in.a.bits.size, size) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_173 node _T_1551 = eq(io.in.a.bits.source, source) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_174 node _T_1555 = eq(io.in.a.bits.address, address) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_175 node _T_1559 = and(io.in.a.ready, io.in.a.valid) node _T_1560 = and(_T_1559, a_first) when _T_1560 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1561 = eq(d_first, UInt<1>(0h0)) node _T_1562 = and(io.in.d.valid, _T_1561) when _T_1562 : node _T_1563 = eq(io.in.d.bits.opcode, opcode_1) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_176 node _T_1567 = eq(io.in.d.bits.param, param_1) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_177 node _T_1571 = eq(io.in.d.bits.size, size_1) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_178 node _T_1575 = eq(io.in.d.bits.source, source_1) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_179 node _T_1579 = eq(io.in.d.bits.sink, sink) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_180 node _T_1583 = eq(io.in.d.bits.denied, denied) node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(_T_1583, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1583, UInt<1>(0h1), "") : assert_181 node _T_1587 = and(io.in.d.ready, io.in.d.valid) node _T_1588 = and(_T_1587, d_first) when _T_1588 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1589 = eq(b_first, UInt<1>(0h0)) node _T_1590 = and(io.in.b.valid, _T_1589) when _T_1590 : node _T_1591 = eq(io.in.b.bits.opcode, opcode_2) node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(_T_1591, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1591, UInt<1>(0h1), "") : assert_182 node _T_1595 = eq(io.in.b.bits.param, param_2) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_183 node _T_1599 = eq(io.in.b.bits.size, size_2) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_184 node _T_1603 = eq(io.in.b.bits.source, source_2) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_185 node _T_1607 = eq(io.in.b.bits.address, address_1) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_186 node _T_1611 = and(io.in.b.ready, io.in.b.valid) node _T_1612 = and(_T_1611, b_first) when _T_1612 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1613 = eq(c_first, UInt<1>(0h0)) node _T_1614 = and(io.in.c.valid, _T_1613) when _T_1614 : node _T_1615 = eq(io.in.c.bits.opcode, opcode_3) node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(_T_1615, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1615, UInt<1>(0h1), "") : assert_187 node _T_1619 = eq(io.in.c.bits.param, param_3) node _T_1620 = asUInt(reset) node _T_1621 = eq(_T_1620, UInt<1>(0h0)) when _T_1621 : node _T_1622 = eq(_T_1619, UInt<1>(0h0)) when _T_1622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1619, UInt<1>(0h1), "") : assert_188 node _T_1623 = eq(io.in.c.bits.size, size_3) node _T_1624 = asUInt(reset) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(_T_1623, UInt<1>(0h0)) when _T_1626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1623, UInt<1>(0h1), "") : assert_189 node _T_1627 = eq(io.in.c.bits.source, source_3) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_190 node _T_1631 = eq(io.in.c.bits.address, address_2) node _T_1632 = asUInt(reset) node _T_1633 = eq(_T_1632, UInt<1>(0h0)) when _T_1633 : node _T_1634 = eq(_T_1631, UInt<1>(0h0)) when _T_1634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1631, UInt<1>(0h1), "") : assert_191 node _T_1635 = and(io.in.c.ready, io.in.c.valid) node _T_1636 = and(_T_1635, c_first) when _T_1636 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1637 = and(io.in.a.valid, a_first_1) node _T_1638 = and(_T_1637, UInt<1>(0h1)) when _T_1638 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1639 = and(io.in.a.ready, io.in.a.valid) node _T_1640 = and(_T_1639, a_first_1) node _T_1641 = and(_T_1640, UInt<1>(0h1)) when _T_1641 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1642 = dshr(inflight, io.in.a.bits.source) node _T_1643 = bits(_T_1642, 0, 0) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1648 = and(io.in.d.valid, d_first_1) node _T_1649 = and(_T_1648, UInt<1>(0h1)) node _T_1650 = eq(d_release_ack, UInt<1>(0h0)) node _T_1651 = and(_T_1649, _T_1650) when _T_1651 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1652 = and(io.in.d.ready, io.in.d.valid) node _T_1653 = and(_T_1652, d_first_1) node _T_1654 = and(_T_1653, UInt<1>(0h1)) node _T_1655 = eq(d_release_ack, UInt<1>(0h0)) node _T_1656 = and(_T_1654, _T_1655) when _T_1656 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1657 = and(io.in.d.valid, d_first_1) node _T_1658 = and(_T_1657, UInt<1>(0h1)) node _T_1659 = eq(d_release_ack, UInt<1>(0h0)) node _T_1660 = and(_T_1658, _T_1659) when _T_1660 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1661 = dshr(inflight, io.in.d.bits.source) node _T_1662 = bits(_T_1661, 0, 0) node _T_1663 = or(_T_1662, same_cycle_resp) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1667 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1668 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1669 = or(_T_1667, _T_1668) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_194 node _T_1673 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_195 else : node _T_1677 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1678 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1679 = or(_T_1677, _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_196 node _T_1683 = eq(io.in.d.bits.size, a_size_lookup) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_197 node _T_1687 = and(io.in.d.valid, d_first_1) node _T_1688 = and(_T_1687, a_first_1) node _T_1689 = and(_T_1688, io.in.a.valid) node _T_1690 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1691 = and(_T_1689, _T_1690) node _T_1692 = eq(d_release_ack, UInt<1>(0h0)) node _T_1693 = and(_T_1691, _T_1692) when _T_1693 : node _T_1694 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1695 = or(_T_1694, io.in.a.ready) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_198 node _T_1699 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1700 = orr(a_set_wo_ready) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) node _T_1702 = or(_T_1699, _T_1701) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_1706 = orr(inflight) node _T_1707 = eq(_T_1706, UInt<1>(0h0)) node _T_1708 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1709 = or(_T_1707, _T_1708) node _T_1710 = lt(watchdog, plusarg_reader.out) node _T_1711 = or(_T_1709, _T_1710) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1715 = and(io.in.a.ready, io.in.a.valid) node _T_1716 = and(io.in.d.ready, io.in.d.valid) node _T_1717 = or(_T_1715, _T_1716) when _T_1717 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_1718 = and(io.in.c.valid, c_first_1) node _T_1719 = bits(io.in.c.bits.opcode, 2, 2) node _T_1720 = bits(io.in.c.bits.opcode, 1, 1) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = and(_T_1718, _T_1721) when _T_1722 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1723 = and(io.in.c.ready, io.in.c.valid) node _T_1724 = and(_T_1723, c_first_1) node _T_1725 = bits(io.in.c.bits.opcode, 2, 2) node _T_1726 = bits(io.in.c.bits.opcode, 1, 1) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = and(_T_1724, _T_1727) when _T_1728 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1729 = dshr(inflight_1, io.in.c.bits.source) node _T_1730 = bits(_T_1729, 0, 0) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) node _T_1732 = asUInt(reset) node _T_1733 = eq(_T_1732, UInt<1>(0h0)) when _T_1733 : node _T_1734 = eq(_T_1731, UInt<1>(0h0)) when _T_1734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1731, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1735 = and(io.in.d.valid, d_first_2) node _T_1736 = and(_T_1735, UInt<1>(0h1)) node _T_1737 = and(_T_1736, d_release_ack_1) when _T_1737 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1738 = and(io.in.d.ready, io.in.d.valid) node _T_1739 = and(_T_1738, d_first_2) node _T_1740 = and(_T_1739, UInt<1>(0h1)) node _T_1741 = and(_T_1740, d_release_ack_1) when _T_1741 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1742 = and(io.in.d.valid, d_first_2) node _T_1743 = and(_T_1742, UInt<1>(0h1)) node _T_1744 = and(_T_1743, d_release_ack_1) when _T_1744 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1745 = dshr(inflight_1, io.in.d.bits.source) node _T_1746 = bits(_T_1745, 0, 0) node _T_1747 = or(_T_1746, same_cycle_resp_1) node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(_T_1747, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1747, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1751 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1752 = asUInt(reset) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) when _T_1753 : node _T_1754 = eq(_T_1751, UInt<1>(0h0)) when _T_1754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1751, UInt<1>(0h1), "") : assert_203 else : node _T_1755 = eq(io.in.d.bits.size, c_size_lookup) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_204 node _T_1759 = and(io.in.d.valid, d_first_2) node _T_1760 = and(_T_1759, c_first_1) node _T_1761 = and(_T_1760, io.in.c.valid) node _T_1762 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1763 = and(_T_1761, _T_1762) node _T_1764 = and(_T_1763, d_release_ack_1) node _T_1765 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1766 = and(_T_1764, _T_1765) when _T_1766 : node _T_1767 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1768 = or(_T_1767, io.in.c.ready) node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(_T_1768, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1768, UInt<1>(0h1), "") : assert_205 node _T_1772 = orr(c_set_wo_ready) when _T_1772 : node _T_1773 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_1777 = orr(inflight_1) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) node _T_1779 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1780 = or(_T_1778, _T_1779) node _T_1781 = lt(watchdog_1, plusarg_reader_1.out) node _T_1782 = or(_T_1780, _T_1781) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1786 = and(io.in.c.ready, io.in.c.valid) node _T_1787 = and(io.in.d.ready, io.in.d.valid) node _T_1788 = or(_T_1786, _T_1787) when _T_1788 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1789 = and(io.in.d.ready, io.in.d.valid) node _T_1790 = and(_T_1789, d_first_3) node _T_1791 = bits(io.in.d.bits.opcode, 2, 2) node _T_1792 = bits(io.in.d.bits.opcode, 1, 1) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = and(_T_1791, _T_1793) node _T_1795 = and(_T_1790, _T_1794) when _T_1795 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1796 = dshr(inflight_2, io.in.d.bits.sink) node _T_1797 = bits(_T_1796, 0, 0) node _T_1798 = eq(_T_1797, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1802 = and(io.in.e.ready, io.in.e.valid) node _T_1803 = and(_T_1802, UInt<1>(0h1)) node _T_1804 = and(_T_1803, UInt<1>(0h1)) when _T_1804 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1805 = or(d_set, inflight_2) node _T_1806 = dshr(_T_1805, io.in.e.bits.sink) node _T_1807 = bits(_T_1806, 0, 0) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_d_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [20:0] _GEN_1 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:21], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [25:0] _GEN_2 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:26], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_20 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire _address_ok_T_25 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_26 = _address_ok_T_25 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_27 = _address_ok_T_26 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_27 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [3:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [3:0] _legal_source_T_8 = _legal_source_WIRE_1 ? 4'h9 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = io_in_c_bits_source_0 == 4'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_3 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_3; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [13:0] _GEN_4 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_28 = {io_in_c_bits_address_0[31:14], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_29 = {1'h0, _address_ok_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_30 = _address_ok_T_29 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_31 = _address_ok_T_30; // @[Parameters.scala:137:46] wire _address_ok_T_32 = _address_ok_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_32; // @[Parameters.scala:612:40] wire [20:0] _GEN_5 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_33 = {io_in_c_bits_address_0[31:21], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_34 = {1'h0, _address_ok_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_35 = _address_ok_T_34 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_36 = _address_ok_T_35; // @[Parameters.scala:137:46] wire _address_ok_T_37 = _address_ok_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_37; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_38 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_39 = {1'h0, _address_ok_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_40 = _address_ok_T_39 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_41 = _address_ok_T_40; // @[Parameters.scala:137:46] wire _address_ok_T_42 = _address_ok_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_42; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_43 = {io_in_c_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_44 = {1'h0, _address_ok_T_43}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_45 = _address_ok_T_44 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_46 = _address_ok_T_45; // @[Parameters.scala:137:46] wire _address_ok_T_47 = _address_ok_T_46 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_47; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_48 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_49 = {1'h0, _address_ok_T_48}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_50 = _address_ok_T_49 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_51 = _address_ok_T_50; // @[Parameters.scala:137:46] wire _address_ok_T_52 = _address_ok_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_52; // @[Parameters.scala:612:40] wire _address_ok_T_53 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_54 = _address_ok_T_53 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_55 = _address_ok_T_54 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_55 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire [3:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_1715 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1715; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1715; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1789 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1789; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1789; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1789; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1789; // @[Decoupled.scala:51:35] wire [26:0] _GEN_7 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_7; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_7; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_7; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_7; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_1786 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1786; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1786; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_8 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_8; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_8; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_8; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_8; // @[Monitor.scala:637:69, :790:101] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_9 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_9; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_9; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_9; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_9; // @[Monitor.scala:641:65, :791:99] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {72'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_10 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_10; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_10; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1641 = _T_1715 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1641 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1641 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1641 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1641 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1641 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_11 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_11; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_11; // @[Monitor.scala:673:46, :783:46] wire _T_1687 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_12 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_12; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_12; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_12; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_12; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1687 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1656 = _T_1789 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1656 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1656 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1656 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] c_set; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {72'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_13 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_13; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_13; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1728 = _T_1786 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1728 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1728 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1728 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1728 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1728 ? _c_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1759 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1759 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1741 = _T_1789 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1741 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1741 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1741 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_1795 = _T_1789 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_14 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_14; // @[OneHot.scala:58:35] assign d_set = _T_1795 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_1804 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_15 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_15; // @[OneHot.scala:58:35] assign e_clr = _T_1804 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module PlusArgTimeout_6 : input clock : Clock input reset : Reset output io : { flip count : UInt<32>} inst plusarg_reader of plusarg_reader_142 node _T = gt(plusarg_reader.out, UInt<1>(0h0)) when _T : node _T_1 = lt(io.count, plusarg_reader.out) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert

module PlusArgTimeout_6( // @[PlusArg.scala:58:7] input clock, // @[PlusArg.scala:58:7] input reset, // @[PlusArg.scala:58:7] input [31:0] io_count // @[PlusArg.scala:59:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19] wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7]

Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s8k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s8k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s8k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s8k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_13 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset

module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [7:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] in_xbar__addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] in_xbar__requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29] wire [7:0] in_xbar_requestBOI_uncommonBits = 8'h0; // @[Parameters.scala:52:56] wire [7:0] in_xbar__beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] in_xbar__beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] in_xbar__portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] in_xbar_portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [128:0] fixer__allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] reg fixer_flight_65; // @[FIFOFixer.scala:79:27] reg fixer_flight_66; // @[FIFOFixer.scala:79:27] reg fixer_flight_67; // @[FIFOFixer.scala:79:27] reg fixer_flight_68; // @[FIFOFixer.scala:79:27] reg fixer_flight_69; // @[FIFOFixer.scala:79:27] reg fixer_flight_70; // @[FIFOFixer.scala:79:27] reg fixer_flight_71; // @[FIFOFixer.scala:79:27] reg fixer_flight_72; // @[FIFOFixer.scala:79:27] reg fixer_flight_73; // @[FIFOFixer.scala:79:27] reg fixer_flight_74; // @[FIFOFixer.scala:79:27] reg fixer_flight_75; // @[FIFOFixer.scala:79:27] reg fixer_flight_76; // @[FIFOFixer.scala:79:27] reg fixer_flight_77; // @[FIFOFixer.scala:79:27] reg fixer_flight_78; // @[FIFOFixer.scala:79:27] reg fixer_flight_79; // @[FIFOFixer.scala:79:27] reg fixer_flight_80; // @[FIFOFixer.scala:79:27] reg fixer_flight_81; // @[FIFOFixer.scala:79:27] reg fixer_flight_82; // @[FIFOFixer.scala:79:27] reg fixer_flight_83; // @[FIFOFixer.scala:79:27] reg fixer_flight_84; // @[FIFOFixer.scala:79:27] reg fixer_flight_85; // @[FIFOFixer.scala:79:27] reg fixer_flight_86; // @[FIFOFixer.scala:79:27] reg fixer_flight_87; // @[FIFOFixer.scala:79:27] reg fixer_flight_88; // @[FIFOFixer.scala:79:27] reg fixer_flight_89; // @[FIFOFixer.scala:79:27] reg fixer_flight_90; // @[FIFOFixer.scala:79:27] reg fixer_flight_91; // @[FIFOFixer.scala:79:27] reg fixer_flight_92; // @[FIFOFixer.scala:79:27] reg fixer_flight_93; // @[FIFOFixer.scala:79:27] reg fixer_flight_94; // @[FIFOFixer.scala:79:27] reg fixer_flight_95; // @[FIFOFixer.scala:79:27] reg fixer_flight_96; // @[FIFOFixer.scala:79:27] reg fixer_flight_97; // @[FIFOFixer.scala:79:27] reg fixer_flight_98; // @[FIFOFixer.scala:79:27] reg fixer_flight_99; // @[FIFOFixer.scala:79:27] reg fixer_flight_100; // @[FIFOFixer.scala:79:27] reg fixer_flight_101; // @[FIFOFixer.scala:79:27] reg fixer_flight_102; // @[FIFOFixer.scala:79:27] reg fixer_flight_103; // @[FIFOFixer.scala:79:27] reg fixer_flight_104; // @[FIFOFixer.scala:79:27] reg fixer_flight_105; // @[FIFOFixer.scala:79:27] reg fixer_flight_106; // @[FIFOFixer.scala:79:27] reg fixer_flight_107; // @[FIFOFixer.scala:79:27] reg fixer_flight_108; // @[FIFOFixer.scala:79:27] reg fixer_flight_109; // @[FIFOFixer.scala:79:27] reg fixer_flight_110; // @[FIFOFixer.scala:79:27] reg fixer_flight_111; // @[FIFOFixer.scala:79:27] reg fixer_flight_112; // @[FIFOFixer.scala:79:27] reg fixer_flight_113; // @[FIFOFixer.scala:79:27] reg fixer_flight_114; // @[FIFOFixer.scala:79:27] reg fixer_flight_115; // @[FIFOFixer.scala:79:27] reg fixer_flight_116; // @[FIFOFixer.scala:79:27] reg fixer_flight_117; // @[FIFOFixer.scala:79:27] reg fixer_flight_118; // @[FIFOFixer.scala:79:27] reg fixer_flight_119; // @[FIFOFixer.scala:79:27] reg fixer_flight_120; // @[FIFOFixer.scala:79:27] reg fixer_flight_121; // @[FIFOFixer.scala:79:27] reg fixer_flight_122; // @[FIFOFixer.scala:79:27] reg fixer_flight_123; // @[FIFOFixer.scala:79:27] reg fixer_flight_124; // @[FIFOFixer.scala:79:27] reg fixer_flight_125; // @[FIFOFixer.scala:79:27] reg fixer_flight_126; // @[FIFOFixer.scala:79:27] reg fixer_flight_127; // @[FIFOFixer.scala:79:27] reg fixer_flight_128; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [128:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [128:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [128:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [255:0] fixer__SourceIdSet_T = 256'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [255:0] fixer__SourceIdClear_T = 256'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [128:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [7:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [7:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [7:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [7:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [7:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire in_ready; // @[RegisterRouter.scala:73:18] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34] wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52] wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 129'h0; // @[FIFOFixer.scala:115:35] bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_65 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h41) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h41 | fixer_flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_66 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h42) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h42 | fixer_flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_67 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h43) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h43 | fixer_flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_68 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h44) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h44 | fixer_flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_69 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h45) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h45 | fixer_flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_70 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h46) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h46 | fixer_flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_71 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h47) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h47 | fixer_flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_72 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h48) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h48 | fixer_flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_73 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h49) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h49 | fixer_flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_74 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4A | fixer_flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_75 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4B | fixer_flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_76 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4C | fixer_flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_77 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4D | fixer_flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_78 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4E | fixer_flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_79 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4F | fixer_flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_80 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h50) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h50 | fixer_flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_81 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h51) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h51 | fixer_flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_82 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h52) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h52 | fixer_flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_83 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h53) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h53 | fixer_flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_84 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h54) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h54 | fixer_flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_85 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h55) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h55 | fixer_flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_86 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h56) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h56 | fixer_flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_87 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h57) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h57 | fixer_flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_88 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h58) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h58 | fixer_flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_89 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h59) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h59 | fixer_flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_90 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5A | fixer_flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_91 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5B | fixer_flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_92 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5C | fixer_flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_93 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5D | fixer_flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_94 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5E | fixer_flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_95 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5F | fixer_flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_96 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h60) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h60 | fixer_flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_97 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h61) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h61 | fixer_flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_98 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h62) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h62 | fixer_flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_99 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h63) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h63 | fixer_flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_100 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h64) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h64 | fixer_flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_101 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h65) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h65 | fixer_flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_102 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h66) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h66 | fixer_flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_103 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h67) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h67 | fixer_flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_104 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h68) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h68 | fixer_flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_105 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h69) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h69 | fixer_flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_106 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6A | fixer_flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_107 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6B | fixer_flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_108 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6C | fixer_flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_109 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6D | fixer_flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_110 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6E | fixer_flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_111 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6F | fixer_flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_112 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h70) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h70 | fixer_flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_113 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h71) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h71 | fixer_flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_114 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h72) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h72 | fixer_flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_115 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h73) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h73 | fixer_flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_116 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h74) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h74 | fixer_flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_117 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h75) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h75 | fixer_flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_118 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h76) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h76 | fixer_flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_119 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h77) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h77 | fixer_flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_120 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h78) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h78 | fixer_flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_121 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h79) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h79 | fixer_flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_122 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7A | fixer_flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_123 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7B | fixer_flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_124 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7C | fixer_flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_125 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7D | fixer_flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_126 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7E | fixer_flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_127 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7F | fixer_flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_128 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h80) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h80 | fixer_flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_pbus_out_i1_o2_a29d64s8k1z3u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s8k1z3u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] TLBuffer_a29d64s8k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (bus_xingOut_a_ready), .auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (bus_xingOut_d_valid), .auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode), .auto_in_d_bits_param (bus_xingOut_d_bits_param), .auto_in_d_bits_size (bus_xingOut_d_bits_size), .auto_in_d_bits_source (bus_xingOut_d_bits_source), .auto_in_d_bits_sink (bus_xingOut_d_bits_sink), .auto_in_d_bits_denied (bus_xingOut_d_bits_denied), .auto_in_d_bits_data (bus_xingOut_d_bits_data), .auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt), .auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_out_a_valid (in_xbar_auto_anon_in_a_valid), .auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param), .auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size), .auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source), .auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (in_xbar_auto_anon_in_d_ready), .auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9] .auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9] .auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_a_valid (nodeIn_a_valid), .auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param), .auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size), .auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source), .auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address), .auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask), .auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data), .auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_fragmenter_anon_out_d_ready (nodeIn_d_ready), .auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0), .auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0), .auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0), .auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0), .auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0), .auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0), .auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0), .auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0), .auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0), .auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0), .auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLMonitor_13 monitor ( // @[Nodes.scala:27:25] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_2 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_2 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut

module DivSqrtRecFMToRaw_small_e5_s11_2( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_2 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DatPath : input clock : Clock input reset : Reset output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ctl : { stall : UInt<1>, if_kill : UInt<1>, pc_sel : UInt<3>, op1_sel : UInt<2>, op2_sel : UInt<3>, alu_fun : UInt<5>, wb_sel : UInt<2>, rf_wen : UInt<1>, csr_cmd : UInt<3>, mem_val : UInt<1>, mem_fcn : UInt<2>, mem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>, pc_sel_no_xept : UInt<3>}, dat : { if_valid_resp : UInt<1>, inst : UInt<32>, br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, inst_misaligned : UInt<1>, data_misaligned : UInt<1>, mem_store : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} invalidate io.reset_vector invalidate io.hartid invalidate io.interrupt.meip invalidate io.interrupt.msip invalidate io.interrupt.mtip invalidate io.interrupt.debug invalidate io.dat.csr_interrupt invalidate io.dat.csr_eret invalidate io.dat.mem_store invalidate io.dat.data_misaligned invalidate io.dat.inst_misaligned invalidate io.dat.br_ltu invalidate io.dat.br_lt invalidate io.dat.br_eq invalidate io.dat.inst invalidate io.dat.if_valid_resp invalidate io.ctl.pc_sel_no_xept invalidate io.ctl.exception_cause invalidate io.ctl.exception invalidate io.ctl.mem_typ invalidate io.ctl.mem_fcn invalidate io.ctl.mem_val invalidate io.ctl.csr_cmd invalidate io.ctl.rf_wen invalidate io.ctl.wb_sel invalidate io.ctl.alu_fun invalidate io.ctl.op2_sel invalidate io.ctl.op1_sel invalidate io.ctl.pc_sel invalidate io.ctl.if_kill invalidate io.ctl.stall invalidate io.dmem.resp.bits.data invalidate io.dmem.resp.valid invalidate io.dmem.req.bits.typ invalidate io.dmem.req.bits.fcn invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.addr invalidate io.dmem.req.valid invalidate io.dmem.req.ready invalidate io.imem.resp.bits.data invalidate io.imem.resp.valid invalidate io.imem.req.bits.typ invalidate io.imem.req.bits.fcn invalidate io.imem.req.bits.data invalidate io.imem.req.bits.addr invalidate io.imem.req.valid invalidate io.imem.req.ready invalidate io.ddpath.resetpc invalidate io.ddpath.rdata invalidate io.ddpath.validreq invalidate io.ddpath.wdata invalidate io.ddpath.addr wire tval_data_ma : UInt<32> wire tval_inst_ma : UInt<32> regreset if_reg_pc : UInt, clock, reset, io.reset_vector regreset exe_reg_pc : UInt<32>, clock, reset, UInt<32>(0h0) regreset exe_reg_pc_plus4 : UInt<32>, clock, reset, UInt<32>(0h0) regreset exe_reg_inst : UInt<32>, clock, reset, UInt<32>(0h4033) regreset exe_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) wire if_pc_next : UInt<32> wire exe_br_target : UInt<32> wire exe_jmp_target : UInt<32> wire exe_jump_reg_target : UInt<32> wire exception_target : UInt<32> node _T = eq(io.ctl.stall, UInt<1>(0h0)) when _T : connect if_reg_pc, if_pc_next node _if_pc_plus4_T = add(if_reg_pc, UInt<32>(0h4)) node if_pc_plus4 = tail(_if_pc_plus4_T, 1) node _if_pc_next_T = eq(io.ctl.pc_sel, UInt<3>(0h0)) node _if_pc_next_T_1 = eq(io.ctl.pc_sel, UInt<3>(0h1)) node _if_pc_next_T_2 = eq(io.ctl.pc_sel, UInt<3>(0h2)) node _if_pc_next_T_3 = eq(io.ctl.pc_sel, UInt<3>(0h3)) node _if_pc_next_T_4 = eq(io.ctl.pc_sel, UInt<3>(0h4)) node _if_pc_next_T_5 = mux(_if_pc_next_T_4, exception_target, if_pc_plus4) node _if_pc_next_T_6 = mux(_if_pc_next_T_3, exe_jump_reg_target, _if_pc_next_T_5) node _if_pc_next_T_7 = mux(_if_pc_next_T_2, exe_jmp_target, _if_pc_next_T_6) node _if_pc_next_T_8 = mux(_if_pc_next_T_1, exe_br_target, _if_pc_next_T_7) node _if_pc_next_T_9 = mux(_if_pc_next_T, if_pc_plus4, _if_pc_next_T_8) connect if_pc_next, _if_pc_next_T_9 regreset if_inst_buffer : UInt<32>, clock, reset, UInt<32>(0h0) regreset if_inst_buffer_valid : UInt<1>, clock, reset, UInt<1>(0h0) when io.ctl.stall : when io.imem.resp.valid : connect if_inst_buffer_valid, UInt<1>(0h1) connect if_inst_buffer, io.imem.resp.bits.data else : connect if_inst_buffer, UInt<32>(0h0) connect if_inst_buffer_valid, UInt<1>(0h0) node _io_dat_if_valid_resp_T = or(if_inst_buffer_valid, io.imem.resp.valid) connect io.dat.if_valid_resp, _io_dat_if_valid_resp_T node _io_imem_req_valid_T = eq(if_inst_buffer_valid, UInt<1>(0h0)) connect io.imem.req.valid, _io_imem_req_valid_T connect io.imem.req.bits.fcn, UInt<1>(0h0) connect io.imem.req.bits.typ, UInt<3>(0h7) connect io.imem.req.bits.addr, if_reg_pc node if_inst = mux(if_inst_buffer_valid, if_inst_buffer, io.imem.resp.bits.data) when io.ctl.stall : connect exe_reg_inst, exe_reg_inst connect exe_reg_pc, exe_reg_pc else : when io.ctl.if_kill : connect exe_reg_inst, UInt<32>(0h4033) connect exe_reg_pc, UInt<1>(0h0) connect exe_reg_valid, UInt<1>(0h0) else : connect exe_reg_inst, if_inst connect exe_reg_pc, if_reg_pc connect exe_reg_valid, UInt<1>(0h1) connect exe_reg_pc_plus4, if_pc_plus4 node exe_rs1_addr = bits(exe_reg_inst, 19, 15) node exe_rs2_addr = bits(exe_reg_inst, 24, 20) node exe_wbaddr = bits(exe_reg_inst, 11, 7) wire exe_wbdata : UInt<32> node _exe_wben_T = eq(io.ctl.exception, UInt<1>(0h0)) node exe_wben = and(io.ctl.rf_wen, _exe_wben_T) cmem regfile : UInt<32> [32] infer mport io_ddpath_rdata_MPORT = regfile[io.ddpath.addr], clock connect io.ddpath.rdata, io_ddpath_rdata_MPORT when io.ddpath.validreq : infer mport MPORT = regfile[io.ddpath.addr], clock connect MPORT, io.ddpath.wdata node _T_1 = neq(exe_wbaddr, UInt<1>(0h0)) node _T_2 = and(exe_wben, _T_1) when _T_2 : infer mport MPORT_1 = regfile[exe_wbaddr], clock connect MPORT_1, exe_wbdata node _exe_rs1_data_T = neq(exe_rs1_addr, UInt<1>(0h0)) infer mport exe_rs1_data_MPORT = regfile[exe_rs1_addr], clock node exe_rs1_data = mux(_exe_rs1_data_T, exe_rs1_data_MPORT, UInt<1>(0h0)) node _exe_rs2_data_T = neq(exe_rs2_addr, UInt<1>(0h0)) infer mport exe_rs2_data_MPORT = regfile[exe_rs2_addr], clock node exe_rs2_data = mux(_exe_rs2_data_T, exe_rs2_data_MPORT, UInt<1>(0h0)) node imm_i = bits(exe_reg_inst, 31, 20) node _imm_s_T = bits(exe_reg_inst, 31, 25) node _imm_s_T_1 = bits(exe_reg_inst, 11, 7) node imm_s = cat(_imm_s_T, _imm_s_T_1) node _imm_b_T = bits(exe_reg_inst, 31, 31) node _imm_b_T_1 = bits(exe_reg_inst, 7, 7) node _imm_b_T_2 = bits(exe_reg_inst, 30, 25) node _imm_b_T_3 = bits(exe_reg_inst, 11, 8) node imm_b_lo = cat(_imm_b_T_2, _imm_b_T_3) node imm_b_hi = cat(_imm_b_T, _imm_b_T_1) node imm_b = cat(imm_b_hi, imm_b_lo) node imm_u = bits(exe_reg_inst, 31, 12) node _imm_j_T = bits(exe_reg_inst, 31, 31) node _imm_j_T_1 = bits(exe_reg_inst, 19, 12) node _imm_j_T_2 = bits(exe_reg_inst, 20, 20) node _imm_j_T_3 = bits(exe_reg_inst, 30, 21) node imm_j_lo = cat(_imm_j_T_2, _imm_j_T_3) node imm_j_hi = cat(_imm_j_T, _imm_j_T_1) node imm_j = cat(imm_j_hi, imm_j_lo) node _imm_z_T = mux(UInt<1>(0h0), UInt<27>(0h7ffffff), UInt<27>(0h0)) node _imm_z_T_1 = bits(exe_reg_inst, 19, 15) node imm_z = cat(_imm_z_T, _imm_z_T_1) node _imm_i_sext_T = bits(imm_i, 11, 11) node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) node _imm_s_sext_T = bits(imm_s, 11, 11) node _imm_s_sext_T_1 = mux(_imm_s_sext_T, UInt<20>(0hfffff), UInt<20>(0h0)) node imm_s_sext = cat(_imm_s_sext_T_1, imm_s) node _imm_b_sext_T = bits(imm_b, 11, 11) node _imm_b_sext_T_1 = mux(_imm_b_sext_T, UInt<19>(0h7ffff), UInt<19>(0h0)) node imm_b_sext_hi = cat(_imm_b_sext_T_1, imm_b) node imm_b_sext = cat(imm_b_sext_hi, UInt<1>(0h0)) node _imm_u_sext_T = mux(UInt<1>(0h0), UInt<12>(0hfff), UInt<12>(0h0)) node imm_u_sext = cat(imm_u, _imm_u_sext_T) node _imm_j_sext_T = bits(imm_j, 19, 19) node _imm_j_sext_T_1 = mux(_imm_j_sext_T, UInt<11>(0h7ff), UInt<11>(0h0)) node imm_j_sext_hi = cat(_imm_j_sext_T_1, imm_j) node imm_j_sext = cat(imm_j_sext_hi, UInt<1>(0h0)) node _exe_alu_op1_T = eq(io.ctl.op1_sel, UInt<2>(0h0)) node _exe_alu_op1_T_1 = eq(io.ctl.op1_sel, UInt<2>(0h1)) node _exe_alu_op1_T_2 = eq(io.ctl.op1_sel, UInt<2>(0h2)) node _exe_alu_op1_T_3 = mux(_exe_alu_op1_T_2, imm_z, UInt<1>(0h0)) node _exe_alu_op1_T_4 = mux(_exe_alu_op1_T_1, imm_u_sext, _exe_alu_op1_T_3) node exe_alu_op1 = mux(_exe_alu_op1_T, exe_rs1_data, _exe_alu_op1_T_4) node _exe_alu_op2_T = eq(io.ctl.op2_sel, UInt<3>(0h0)) node _exe_alu_op2_T_1 = eq(io.ctl.op2_sel, UInt<3>(0h1)) node _exe_alu_op2_T_2 = eq(io.ctl.op2_sel, UInt<3>(0h2)) node _exe_alu_op2_T_3 = eq(io.ctl.op2_sel, UInt<3>(0h3)) node _exe_alu_op2_T_4 = mux(_exe_alu_op2_T_3, imm_s_sext, UInt<1>(0h0)) node _exe_alu_op2_T_5 = mux(_exe_alu_op2_T_2, imm_i_sext, _exe_alu_op2_T_4) node _exe_alu_op2_T_6 = mux(_exe_alu_op2_T_1, exe_reg_pc, _exe_alu_op2_T_5) node exe_alu_op2 = mux(_exe_alu_op2_T, exe_rs2_data, _exe_alu_op2_T_6) wire exe_alu_out : UInt<32> node alu_shamt = bits(exe_alu_op2, 4, 0) node _exe_alu_out_T = eq(io.ctl.alu_fun, UInt<4>(0h1)) node _exe_alu_out_T_1 = add(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) node _exe_alu_out_T_3 = eq(io.ctl.alu_fun, UInt<4>(0h2)) node _exe_alu_out_T_4 = sub(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) node _exe_alu_out_T_6 = eq(io.ctl.alu_fun, UInt<4>(0h6)) node _exe_alu_out_T_7 = and(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_8 = eq(io.ctl.alu_fun, UInt<4>(0h7)) node _exe_alu_out_T_9 = or(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_10 = eq(io.ctl.alu_fun, UInt<4>(0h8)) node _exe_alu_out_T_11 = xor(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_12 = eq(io.ctl.alu_fun, UInt<4>(0h9)) node _exe_alu_out_T_13 = asSInt(exe_alu_op1) node _exe_alu_out_T_14 = asSInt(exe_alu_op2) node _exe_alu_out_T_15 = lt(_exe_alu_out_T_13, _exe_alu_out_T_14) node _exe_alu_out_T_16 = eq(io.ctl.alu_fun, UInt<4>(0ha)) node _exe_alu_out_T_17 = lt(exe_alu_op1, exe_alu_op2) node _exe_alu_out_T_18 = eq(io.ctl.alu_fun, UInt<4>(0h3)) node _exe_alu_out_T_19 = dshl(exe_alu_op1, alu_shamt) node _exe_alu_out_T_20 = bits(_exe_alu_out_T_19, 31, 0) node _exe_alu_out_T_21 = eq(io.ctl.alu_fun, UInt<4>(0h5)) node _exe_alu_out_T_22 = asSInt(exe_alu_op1) node _exe_alu_out_T_23 = dshr(_exe_alu_out_T_22, alu_shamt) node _exe_alu_out_T_24 = asUInt(_exe_alu_out_T_23) node _exe_alu_out_T_25 = eq(io.ctl.alu_fun, UInt<4>(0h4)) node _exe_alu_out_T_26 = dshr(exe_alu_op1, alu_shamt) node _exe_alu_out_T_27 = eq(io.ctl.alu_fun, UInt<4>(0hb)) node _exe_alu_out_T_28 = mux(_exe_alu_out_T_27, exe_alu_op1, UInt<1>(0h0)) node _exe_alu_out_T_29 = mux(_exe_alu_out_T_25, _exe_alu_out_T_26, _exe_alu_out_T_28) node _exe_alu_out_T_30 = mux(_exe_alu_out_T_21, _exe_alu_out_T_24, _exe_alu_out_T_29) node _exe_alu_out_T_31 = mux(_exe_alu_out_T_18, _exe_alu_out_T_20, _exe_alu_out_T_30) node _exe_alu_out_T_32 = mux(_exe_alu_out_T_16, _exe_alu_out_T_17, _exe_alu_out_T_31) node _exe_alu_out_T_33 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_32) node _exe_alu_out_T_34 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_33) node _exe_alu_out_T_35 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_34) node _exe_alu_out_T_36 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_35) node _exe_alu_out_T_37 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_36) node _exe_alu_out_T_38 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_37) connect exe_alu_out, _exe_alu_out_T_38 node _exe_br_target_T = add(exe_reg_pc, imm_b_sext) node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) connect exe_br_target, _exe_br_target_T_1 node _exe_jmp_target_T = add(exe_reg_pc, imm_j_sext) node _exe_jmp_target_T_1 = tail(_exe_jmp_target_T, 1) connect exe_jmp_target, _exe_jmp_target_T_1 node _exe_jump_reg_target_T = add(exe_rs1_data, imm_i_sext) node _exe_jump_reg_target_T_1 = tail(_exe_jump_reg_target_T, 1) node _exe_jump_reg_target_T_2 = not(UInt<32>(0h1)) node _exe_jump_reg_target_T_3 = and(_exe_jump_reg_target_T_1, _exe_jump_reg_target_T_2) connect exe_jump_reg_target, _exe_jump_reg_target_T_3 node _io_dat_inst_misaligned_T = bits(exe_br_target, 1, 0) node _io_dat_inst_misaligned_T_1 = orr(_io_dat_inst_misaligned_T) node _io_dat_inst_misaligned_T_2 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h1)) node _io_dat_inst_misaligned_T_3 = and(_io_dat_inst_misaligned_T_1, _io_dat_inst_misaligned_T_2) node _io_dat_inst_misaligned_T_4 = bits(exe_jmp_target, 1, 0) node _io_dat_inst_misaligned_T_5 = orr(_io_dat_inst_misaligned_T_4) node _io_dat_inst_misaligned_T_6 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h2)) node _io_dat_inst_misaligned_T_7 = and(_io_dat_inst_misaligned_T_5, _io_dat_inst_misaligned_T_6) node _io_dat_inst_misaligned_T_8 = or(_io_dat_inst_misaligned_T_3, _io_dat_inst_misaligned_T_7) node _io_dat_inst_misaligned_T_9 = bits(exe_jump_reg_target, 1, 0) node _io_dat_inst_misaligned_T_10 = orr(_io_dat_inst_misaligned_T_9) node _io_dat_inst_misaligned_T_11 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h3)) node _io_dat_inst_misaligned_T_12 = and(_io_dat_inst_misaligned_T_10, _io_dat_inst_misaligned_T_11) node _io_dat_inst_misaligned_T_13 = or(_io_dat_inst_misaligned_T_8, _io_dat_inst_misaligned_T_12) connect io.dat.inst_misaligned, _io_dat_inst_misaligned_T_13 node _tval_inst_ma_T = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h1)) node _tval_inst_ma_T_1 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h2)) node _tval_inst_ma_T_2 = eq(io.ctl.pc_sel_no_xept, UInt<3>(0h3)) node _tval_inst_ma_T_3 = mux(_tval_inst_ma_T_2, exe_jump_reg_target, UInt<1>(0h0)) node _tval_inst_ma_T_4 = mux(_tval_inst_ma_T_1, exe_jmp_target, _tval_inst_ma_T_3) node _tval_inst_ma_T_5 = mux(_tval_inst_ma_T, exe_br_target, _tval_inst_ma_T_4) connect tval_inst_ma, _tval_inst_ma_T_5 wire _hits_WIRE : UInt<1>[1] connect _hits_WIRE[0], UInt<1>(0h0) wire hits : UInt<1>[1] connect hits, _hits_WIRE inst csr of CSRFile connect csr.clock, clock connect csr.reset, reset invalidate csr.io.fiom invalidate csr.io.scontext invalidate csr.io.mcontext invalidate csr.io.trace[0].tval invalidate csr.io.trace[0].cause invalidate csr.io.trace[0].interrupt invalidate csr.io.trace[0].exception invalidate csr.io.trace[0].priv invalidate csr.io.trace[0].insn invalidate csr.io.trace[0].iaddr invalidate csr.io.trace[0].valid invalidate csr.io.inst[0] invalidate csr.io.inhibit_cycle invalidate csr.io.csrw_counter invalidate csr.io.interrupt_cause invalidate csr.io.interrupt invalidate csr.io.rocc_interrupt invalidate csr.io.fcsr_flags.bits invalidate csr.io.fcsr_flags.valid invalidate csr.io.fcsr_rm invalidate csr.io.time invalidate csr.io.gva invalidate csr.io.mhtinst_read_pseudo invalidate csr.io.htval invalidate csr.io.tval invalidate csr.io.pc invalidate csr.io.cause invalidate csr.io.retire invalidate csr.io.exception invalidate csr.io.evec invalidate csr.io.vsatp.ppn invalidate csr.io.vsatp.asid invalidate csr.io.vsatp.mode invalidate csr.io.hgatp.ppn invalidate csr.io.hgatp.asid invalidate csr.io.hgatp.mode invalidate csr.io.ptbr.ppn invalidate csr.io.ptbr.asid invalidate csr.io.ptbr.mode invalidate csr.io.gstatus.uie invalidate csr.io.gstatus.sie invalidate csr.io.gstatus.hie invalidate csr.io.gstatus.mie invalidate csr.io.gstatus.upie invalidate csr.io.gstatus.spie invalidate csr.io.gstatus.ube invalidate csr.io.gstatus.mpie invalidate csr.io.gstatus.spp invalidate csr.io.gstatus.vs invalidate csr.io.gstatus.mpp invalidate csr.io.gstatus.fs invalidate csr.io.gstatus.xs invalidate csr.io.gstatus.mprv invalidate csr.io.gstatus.sum invalidate csr.io.gstatus.mxr invalidate csr.io.gstatus.tvm invalidate csr.io.gstatus.tw invalidate csr.io.gstatus.tsr invalidate csr.io.gstatus.zero1 invalidate csr.io.gstatus.sd_rv32 invalidate csr.io.gstatus.uxl invalidate csr.io.gstatus.sxl invalidate csr.io.gstatus.sbe invalidate csr.io.gstatus.mbe invalidate csr.io.gstatus.gva invalidate csr.io.gstatus.mpv invalidate csr.io.gstatus.zero2 invalidate csr.io.gstatus.sd invalidate csr.io.gstatus.v invalidate csr.io.gstatus.prv invalidate csr.io.gstatus.dv invalidate csr.io.gstatus.dprv invalidate csr.io.gstatus.isa invalidate csr.io.gstatus.wfi invalidate csr.io.gstatus.cease invalidate csr.io.gstatus.debug invalidate csr.io.hstatus.zero1 invalidate csr.io.hstatus.vsbe invalidate csr.io.hstatus.gva invalidate csr.io.hstatus.spv invalidate csr.io.hstatus.spvp invalidate csr.io.hstatus.hu invalidate csr.io.hstatus.zero2 invalidate csr.io.hstatus.vgein invalidate csr.io.hstatus.zero3 invalidate csr.io.hstatus.vtvm invalidate csr.io.hstatus.vtw invalidate csr.io.hstatus.vtsr invalidate csr.io.hstatus.zero5 invalidate csr.io.hstatus.vsxl invalidate csr.io.hstatus.zero6 invalidate csr.io.status.uie invalidate csr.io.status.sie invalidate csr.io.status.hie invalidate csr.io.status.mie invalidate csr.io.status.upie invalidate csr.io.status.spie invalidate csr.io.status.ube invalidate csr.io.status.mpie invalidate csr.io.status.spp invalidate csr.io.status.vs invalidate csr.io.status.mpp invalidate csr.io.status.fs invalidate csr.io.status.xs invalidate csr.io.status.mprv invalidate csr.io.status.sum invalidate csr.io.status.mxr invalidate csr.io.status.tvm invalidate csr.io.status.tw invalidate csr.io.status.tsr invalidate csr.io.status.zero1 invalidate csr.io.status.sd_rv32 invalidate csr.io.status.uxl invalidate csr.io.status.sxl invalidate csr.io.status.sbe invalidate csr.io.status.mbe invalidate csr.io.status.gva invalidate csr.io.status.mpv invalidate csr.io.status.zero2 invalidate csr.io.status.sd invalidate csr.io.status.v invalidate csr.io.status.prv invalidate csr.io.status.dv invalidate csr.io.status.dprv invalidate csr.io.status.isa invalidate csr.io.status.wfi invalidate csr.io.status.cease invalidate csr.io.status.debug invalidate csr.io.singleStep invalidate csr.io.eret invalidate csr.io.rw_stall invalidate csr.io.csr_stall invalidate csr.io.decode[0].virtual_system_illegal invalidate csr.io.decode[0].virtual_access_illegal invalidate csr.io.decode[0].system_illegal invalidate csr.io.decode[0].write_flush invalidate csr.io.decode[0].write_illegal invalidate csr.io.decode[0].read_illegal invalidate csr.io.decode[0].rocc_illegal invalidate csr.io.decode[0].vector_csr invalidate csr.io.decode[0].fp_csr invalidate csr.io.decode[0].vector_illegal invalidate csr.io.decode[0].fp_illegal invalidate csr.io.decode[0].inst invalidate csr.io.rw.wdata invalidate csr.io.rw.rdata invalidate csr.io.rw.cmd invalidate csr.io.rw.addr invalidate csr.io.hartid invalidate csr.io.interrupts.meip invalidate csr.io.interrupts.msip invalidate csr.io.interrupts.mtip invalidate csr.io.interrupts.debug invalidate csr.io.ungated_clock connect csr.io.decode[0].inst, exe_reg_inst node _csr_io_rw_addr_T = bits(exe_reg_inst, 31, 20) connect csr.io.rw.addr, _csr_io_rw_addr_T connect csr.io.rw.cmd, io.ctl.csr_cmd connect csr.io.rw.wdata, exe_alu_out node _csr_io_retire_T = or(io.ctl.stall, io.ctl.exception) node _csr_io_retire_T_1 = eq(_csr_io_retire_T, UInt<1>(0h0)) node _csr_io_retire_T_2 = and(exe_reg_valid, _csr_io_retire_T_1) connect csr.io.retire, _csr_io_retire_T_2 connect csr.io.exception, io.ctl.exception connect csr.io.pc, exe_reg_pc connect exception_target, csr.io.evec node _csr_io_tval_T = eq(io.ctl.exception_cause, UInt<2>(0h2)) node _csr_io_tval_T_1 = eq(io.ctl.exception_cause, UInt<1>(0h0)) node _csr_io_tval_T_2 = eq(io.ctl.exception_cause, UInt<3>(0h6)) node _csr_io_tval_T_3 = eq(io.ctl.exception_cause, UInt<3>(0h4)) node _csr_io_tval_T_4 = mux(_csr_io_tval_T_3, tval_data_ma, UInt<1>(0h0)) node _csr_io_tval_T_5 = mux(_csr_io_tval_T_2, tval_data_ma, _csr_io_tval_T_4) node _csr_io_tval_T_6 = mux(_csr_io_tval_T_1, tval_inst_ma, _csr_io_tval_T_5) node _csr_io_tval_T_7 = mux(_csr_io_tval_T, exe_reg_inst, _csr_io_tval_T_6) connect csr.io.tval, _csr_io_tval_T_7 regreset reg_interrupt_handled : UInt<1>, clock, reset, UInt<1>(0h0) node _T_3 = eq(io.ctl.stall, UInt<1>(0h0)) when _T_3 : connect reg_interrupt_handled, csr.io.interrupt node _interrupt_edge_T = eq(reg_interrupt_handled, UInt<1>(0h0)) node interrupt_edge = and(csr.io.interrupt, _interrupt_edge_T) connect csr.io.interrupts.meip, io.interrupt.meip connect csr.io.interrupts.msip, io.interrupt.msip connect csr.io.interrupts.mtip, io.interrupt.mtip connect csr.io.interrupts.debug, io.interrupt.debug connect csr.io.hartid, io.hartid connect io.dat.csr_interrupt, interrupt_edge node _csr_io_cause_T = mux(io.ctl.exception, io.ctl.exception_cause, csr.io.interrupt_cause) connect csr.io.cause, _csr_io_cause_T connect csr.io.ungated_clock, clock connect io.dat.csr_eret, csr.io.eret node _exe_wbdata_T = eq(io.ctl.wb_sel, UInt<2>(0h0)) node _exe_wbdata_T_1 = eq(io.ctl.wb_sel, UInt<2>(0h1)) node _exe_wbdata_T_2 = eq(io.ctl.wb_sel, UInt<2>(0h2)) node _exe_wbdata_T_3 = eq(io.ctl.wb_sel, UInt<2>(0h3)) node _exe_wbdata_T_4 = mux(_exe_wbdata_T_3, csr.io.rw.rdata, exe_alu_out) node _exe_wbdata_T_5 = mux(_exe_wbdata_T_2, exe_reg_pc_plus4, _exe_wbdata_T_4) node _exe_wbdata_T_6 = mux(_exe_wbdata_T_1, io.dmem.resp.bits.data, _exe_wbdata_T_5) node _exe_wbdata_T_7 = mux(_exe_wbdata_T, exe_alu_out, _exe_wbdata_T_6) connect exe_wbdata, _exe_wbdata_T_7 connect io.dat.inst, exe_reg_inst node _io_dat_br_eq_T = eq(exe_rs1_data, exe_rs2_data) connect io.dat.br_eq, _io_dat_br_eq_T node _io_dat_br_lt_T = asSInt(exe_rs1_data) node _io_dat_br_lt_T_1 = asSInt(exe_rs2_data) node _io_dat_br_lt_T_2 = lt(_io_dat_br_lt_T, _io_dat_br_lt_T_1) connect io.dat.br_lt, _io_dat_br_lt_T_2 node _io_dat_br_ltu_T = lt(exe_rs1_data, exe_rs2_data) connect io.dat.br_ltu, _io_dat_br_ltu_T wire misaligned_mask : UInt<3> node _misaligned_mask_T = sub(io.ctl.mem_typ, UInt<1>(0h1)) node _misaligned_mask_T_1 = tail(_misaligned_mask_T, 1) node _misaligned_mask_T_2 = bits(_misaligned_mask_T_1, 1, 0) node _misaligned_mask_T_3 = dshl(UInt<3>(0h7), _misaligned_mask_T_2) node _misaligned_mask_T_4 = not(_misaligned_mask_T_3) connect misaligned_mask, _misaligned_mask_T_4 node _io_dat_data_misaligned_T = bits(exe_alu_out, 2, 0) node _io_dat_data_misaligned_T_1 = and(misaligned_mask, _io_dat_data_misaligned_T) node _io_dat_data_misaligned_T_2 = orr(_io_dat_data_misaligned_T_1) node _io_dat_data_misaligned_T_3 = and(_io_dat_data_misaligned_T_2, io.ctl.mem_val) connect io.dat.data_misaligned, _io_dat_data_misaligned_T_3 node _io_dat_mem_store_T = eq(io.ctl.mem_fcn, UInt<1>(0h1)) connect io.dat.mem_store, _io_dat_mem_store_T connect tval_data_ma, exe_alu_out connect io.dmem.req.bits.addr, exe_alu_out connect io.dmem.req.bits.data, exe_rs2_data node _T_4 = bits(csr.io.time, 31, 0) node _T_5 = mux(io.ctl.if_kill, UInt<8>(0h4b), UInt<8>(0h20)) node _T_6 = mux(io.ctl.stall, UInt<8>(0h53), _T_5) node _T_7 = eq(UInt<3>(0h1), io.ctl.pc_sel) node _T_8 = mux(_T_7, UInt<8>(0h42), UInt<8>(0h3f)) node _T_9 = eq(UInt<3>(0h2), io.ctl.pc_sel) node _T_10 = mux(_T_9, UInt<8>(0h4a), _T_8) node _T_11 = eq(UInt<3>(0h3), io.ctl.pc_sel) node _T_12 = mux(_T_11, UInt<8>(0h52), _T_10) node _T_13 = eq(UInt<3>(0h4), io.ctl.pc_sel) node _T_14 = mux(_T_13, UInt<8>(0h45), _T_12) node _T_15 = eq(UInt<3>(0h0), io.ctl.pc_sel) node _T_16 = mux(_T_15, UInt<8>(0h20), _T_14) node _T_17 = mux(csr.io.exception, UInt<8>(0h58), UInt<8>(0h20)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Cyc= %d [%d] pc=[%x] W[r%d=%x][%d] Op1=[r%d][%x] Op2=[r%d][%x] inst=[%x] %c%c%c DASM(%x)\n", _T_4, csr.io.retire, exe_reg_pc, exe_wbaddr, exe_wbdata, exe_wben, exe_rs1_addr, exe_alu_op1, exe_rs2_addr, exe_alu_op2, exe_reg_inst, _T_6, _T_16, _T_17, exe_reg_inst) : printf

module DatPath( // @[dpath.scala:46:7] input clock, // @[dpath.scala:46:7] input reset, // @[dpath.scala:46:7] output [31:0] io_ddpath_rdata, // @[dpath.scala:48:15] input io_imem_req_ready, // @[dpath.scala:48:15] output io_imem_req_valid, // @[dpath.scala:48:15] output [31:0] io_imem_req_bits_addr, // @[dpath.scala:48:15] input io_imem_resp_valid, // @[dpath.scala:48:15] input [31:0] io_imem_resp_bits_data, // @[dpath.scala:48:15] input io_dmem_req_ready, // @[dpath.scala:48:15] output [31:0] io_dmem_req_bits_addr, // @[dpath.scala:48:15] output [31:0] io_dmem_req_bits_data, // @[dpath.scala:48:15] input io_dmem_resp_valid, // @[dpath.scala:48:15] input [31:0] io_dmem_resp_bits_data, // @[dpath.scala:48:15] input io_ctl_stall, // @[dpath.scala:48:15] input io_ctl_if_kill, // @[dpath.scala:48:15] input [2:0] io_ctl_pc_sel, // @[dpath.scala:48:15] input [1:0] io_ctl_op1_sel, // @[dpath.scala:48:15] input [2:0] io_ctl_op2_sel, // @[dpath.scala:48:15] input [4:0] io_ctl_alu_fun, // @[dpath.scala:48:15] input [1:0] io_ctl_wb_sel, // @[dpath.scala:48:15] input io_ctl_rf_wen, // @[dpath.scala:48:15] input [2:0] io_ctl_csr_cmd, // @[dpath.scala:48:15] input io_ctl_mem_val, // @[dpath.scala:48:15] input [1:0] io_ctl_mem_fcn, // @[dpath.scala:48:15] input [2:0] io_ctl_mem_typ, // @[dpath.scala:48:15] input io_ctl_exception, // @[dpath.scala:48:15] input [31:0] io_ctl_exception_cause, // @[dpath.scala:48:15] input [2:0] io_ctl_pc_sel_no_xept, // @[dpath.scala:48:15] output io_dat_if_valid_resp, // @[dpath.scala:48:15] output [31:0] io_dat_inst, // @[dpath.scala:48:15] output io_dat_br_eq, // @[dpath.scala:48:15] output io_dat_br_lt, // @[dpath.scala:48:15] output io_dat_br_ltu, // @[dpath.scala:48:15] output io_dat_inst_misaligned, // @[dpath.scala:48:15] output io_dat_data_misaligned, // @[dpath.scala:48:15] output io_dat_mem_store, // @[dpath.scala:48:15] output io_dat_csr_eret, // @[dpath.scala:48:15] output io_dat_csr_interrupt, // @[dpath.scala:48:15] input io_interrupt_debug, // @[dpath.scala:48:15] input io_interrupt_mtip, // @[dpath.scala:48:15] input io_interrupt_msip, // @[dpath.scala:48:15] input io_interrupt_meip, // @[dpath.scala:48:15] input io_hartid // @[dpath.scala:48:15] ); wire [31:0] _csr_io_rw_rdata; // @[dpath.scala:228:20] wire [31:0] _csr_io_time; // @[dpath.scala:228:20] wire _csr_io_interrupt; // @[dpath.scala:228:20] wire [31:0] _csr_io_interrupt_cause; // @[dpath.scala:228:20] wire [31:0] _regfile_ext_R1_data; // @[dpath.scala:142:21] wire [31:0] _regfile_ext_R2_data; // @[dpath.scala:142:21] wire io_imem_req_ready_0 = io_imem_req_ready; // @[dpath.scala:46:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[dpath.scala:46:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[dpath.scala:46:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[dpath.scala:46:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[dpath.scala:46:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[dpath.scala:46:7] wire io_ctl_stall_0 = io_ctl_stall; // @[dpath.scala:46:7] wire io_ctl_if_kill_0 = io_ctl_if_kill; // @[dpath.scala:46:7] wire [2:0] io_ctl_pc_sel_0 = io_ctl_pc_sel; // @[dpath.scala:46:7] wire [1:0] io_ctl_op1_sel_0 = io_ctl_op1_sel; // @[dpath.scala:46:7] wire [2:0] io_ctl_op2_sel_0 = io_ctl_op2_sel; // @[dpath.scala:46:7] wire [4:0] io_ctl_alu_fun_0 = io_ctl_alu_fun; // @[dpath.scala:46:7] wire [1:0] io_ctl_wb_sel_0 = io_ctl_wb_sel; // @[dpath.scala:46:7] wire io_ctl_rf_wen_0 = io_ctl_rf_wen; // @[dpath.scala:46:7] wire [2:0] io_ctl_csr_cmd_0 = io_ctl_csr_cmd; // @[dpath.scala:46:7] wire io_ctl_mem_val_0 = io_ctl_mem_val; // @[dpath.scala:46:7] wire [1:0] io_ctl_mem_fcn_0 = io_ctl_mem_fcn; // @[dpath.scala:46:7] wire [2:0] io_ctl_mem_typ_0 = io_ctl_mem_typ; // @[dpath.scala:46:7] wire io_ctl_exception_0 = io_ctl_exception; // @[dpath.scala:46:7] wire [31:0] io_ctl_exception_cause_0 = io_ctl_exception_cause; // @[dpath.scala:46:7] wire [2:0] io_ctl_pc_sel_no_xept_0 = io_ctl_pc_sel_no_xept; // @[dpath.scala:46:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[dpath.scala:46:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[dpath.scala:46:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[dpath.scala:46:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[dpath.scala:46:7] wire io_hartid_0 = io_hartid; // @[dpath.scala:46:7] wire [4:0] io_ddpath_addr = 5'h0; // @[dpath.scala:46:7] wire [31:0] io_ddpath_wdata = 32'h0; // @[dpath.scala:46:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[dpath.scala:46:7] wire io_ddpath_validreq = 1'h0; // @[dpath.scala:46:7] wire io_ddpath_resetpc = 1'h0; // @[dpath.scala:46:7] wire io_imem_req_bits_fcn = 1'h0; // @[dpath.scala:46:7] wire io_dmem_req_valid = 1'h0; // @[dpath.scala:46:7] wire io_dmem_req_bits_fcn = 1'h0; // @[dpath.scala:46:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[dpath.scala:46:7] wire [2:0] io_dmem_req_bits_typ = 3'h0; // @[dpath.scala:46:7] wire [31:0] io_reset_vector = 32'h10000; // @[dpath.scala:46:7] wire [31:0] _exe_jump_reg_target_T_2 = 32'hFFFFFFFE; // @[dpath.scala:213:71] wire [11:0] _imm_u_sext_T = 12'h0; // @[dpath.scala:173:36] wire [26:0] _imm_z_T = 27'h0; // @[dpath.scala:167:24] wire _io_imem_req_valid_T; // @[dpath.scala:106:28] wire [31:0] exe_alu_out; // @[dpath.scala:192:28] wire [31:0] exe_rs2_data; // @[dpath.scala:158:26] wire _io_dat_if_valid_resp_T; // @[dpath.scala:103:49] wire _io_dat_br_eq_T; // @[dpath.scala:278:35] wire _io_dat_br_lt_T_2; // @[dpath.scala:279:42] wire _io_dat_br_ltu_T; // @[dpath.scala:280:42] wire _io_dat_inst_misaligned_T_13; // @[dpath.scala:219:98] wire _io_dat_data_misaligned_T_3; // @[dpath.scala:286:85] wire _io_dat_mem_store_T; // @[dpath.scala:287:39] wire interrupt_edge; // @[dpath.scala:253:42] wire [31:0] io_ddpath_rdata_0; // @[dpath.scala:46:7] wire [31:0] io_imem_req_bits_addr_0; // @[dpath.scala:46:7] wire io_imem_req_valid_0; // @[dpath.scala:46:7] wire [31:0] io_dmem_req_bits_addr_0; // @[dpath.scala:46:7] wire [31:0] io_dmem_req_bits_data_0; // @[dpath.scala:46:7] wire io_dat_if_valid_resp_0; // @[dpath.scala:46:7] wire [31:0] io_dat_inst_0; // @[dpath.scala:46:7] wire io_dat_br_eq_0; // @[dpath.scala:46:7] wire io_dat_br_lt_0; // @[dpath.scala:46:7] wire io_dat_br_ltu_0; // @[dpath.scala:46:7] wire io_dat_inst_misaligned_0; // @[dpath.scala:46:7] wire io_dat_data_misaligned_0; // @[dpath.scala:46:7] wire io_dat_mem_store_0; // @[dpath.scala:46:7] wire io_dat_csr_eret_0; // @[dpath.scala:46:7] wire io_dat_csr_interrupt_0; // @[dpath.scala:46:7] wire [31:0] tval_data_ma; // @[dpath.scala:52:27] wire [31:0] _tval_inst_ma_T_5; // @[Mux.scala:126:16] wire [31:0] tval_inst_ma; // @[dpath.scala:53:27] reg [31:0] if_reg_pc; // @[dpath.scala:57:27] assign io_imem_req_bits_addr_0 = if_reg_pc; // @[dpath.scala:46:7, :57:27] reg [31:0] exe_reg_pc; // @[dpath.scala:59:34] reg [31:0] exe_reg_pc_plus4; // @[dpath.scala:60:34] reg [31:0] exe_reg_inst; // @[dpath.scala:61:34] assign io_dat_inst_0 = exe_reg_inst; // @[dpath.scala:46:7, :61:34] reg exe_reg_valid; // @[dpath.scala:62:34] wire [31:0] _if_pc_next_T_9; // @[Mux.scala:126:16] wire [31:0] if_pc_next; // @[dpath.scala:66:34] wire [31:0] _exe_br_target_T_1; // @[dpath.scala:211:38] wire [31:0] exe_br_target; // @[dpath.scala:67:34] wire [31:0] _exe_jmp_target_T_1; // @[dpath.scala:212:38] wire [31:0] exe_jmp_target; // @[dpath.scala:68:34] wire [31:0] _exe_jump_reg_target_T_3; // @[dpath.scala:213:69] wire [31:0] exe_jump_reg_target; // @[dpath.scala:69:34] wire [31:0] exception_target; // @[dpath.scala:70:34] wire [32:0] _if_pc_plus4_T = {1'h0, if_reg_pc} + 33'h4; // @[dpath.scala:57:27, :77:33] wire [31:0] if_pc_plus4 = _if_pc_plus4_T[31:0]; // @[dpath.scala:77:33] wire _if_pc_next_T = io_ctl_pc_sel_0 == 3'h0; // @[dpath.scala:46:7, :80:34] wire _if_pc_next_T_1 = io_ctl_pc_sel_0 == 3'h1; // @[dpath.scala:46:7, :81:34] wire _if_pc_next_T_2 = io_ctl_pc_sel_0 == 3'h2; // @[dpath.scala:46:7, :82:34] wire _if_pc_next_T_3 = io_ctl_pc_sel_0 == 3'h3; // @[dpath.scala:46:7, :83:34] wire _if_pc_next_T_4 = io_ctl_pc_sel_0 == 3'h4; // @[dpath.scala:46:7, :84:34] wire [31:0] _if_pc_next_T_5 = _if_pc_next_T_4 ? exception_target : if_pc_plus4; // @[Mux.scala:126:16] wire [31:0] _if_pc_next_T_6 = _if_pc_next_T_3 ? exe_jump_reg_target : _if_pc_next_T_5; // @[Mux.scala:126:16] wire [31:0] _if_pc_next_T_7 = _if_pc_next_T_2 ? exe_jmp_target : _if_pc_next_T_6; // @[Mux.scala:126:16] wire [31:0] _if_pc_next_T_8 = _if_pc_next_T_1 ? exe_br_target : _if_pc_next_T_7; // @[Mux.scala:126:16] assign _if_pc_next_T_9 = _if_pc_next_T ? if_pc_plus4 : _if_pc_next_T_8; // @[Mux.scala:126:16] assign if_pc_next = _if_pc_next_T_9; // @[Mux.scala:126:16] reg [31:0] if_inst_buffer; // @[dpath.scala:89:32] reg if_inst_buffer_valid; // @[dpath.scala:90:38] assign _io_dat_if_valid_resp_T = if_inst_buffer_valid | io_imem_resp_valid_0; // @[dpath.scala:46:7, :90:38, :103:49] assign io_dat_if_valid_resp_0 = _io_dat_if_valid_resp_T; // @[dpath.scala:46:7, :103:49] assign _io_imem_req_valid_T = ~if_inst_buffer_valid; // @[dpath.scala:90:38, :106:28] assign io_imem_req_valid_0 = _io_imem_req_valid_T; // @[dpath.scala:46:7, :106:28] wire [31:0] if_inst = if_inst_buffer_valid ? if_inst_buffer : io_imem_resp_bits_data_0; // @[dpath.scala:46:7, :89:32, :90:38, :110:21] wire [4:0] exe_rs1_addr = exe_reg_inst[19:15]; // @[dpath.scala:61:34, :134:35] wire [4:0] _imm_z_T_1 = exe_reg_inst[19:15]; // @[dpath.scala:61:34, :134:35, :167:46] wire [4:0] exe_rs2_addr = exe_reg_inst[24:20]; // @[dpath.scala:61:34, :135:35] wire [4:0] exe_wbaddr = exe_reg_inst[11:7]; // @[dpath.scala:61:34, :136:35] wire [4:0] _imm_s_T_1 = exe_reg_inst[11:7]; // @[dpath.scala:61:34, :136:35, :163:54] wire [31:0] _exe_wbdata_T_7; // @[Mux.scala:126:16] wire [31:0] exe_wbdata; // @[dpath.scala:138:25] wire _exe_wben_T = ~io_ctl_exception_0; // @[dpath.scala:46:7, :139:36] wire exe_wben = io_ctl_rf_wen_0 & _exe_wben_T; // @[dpath.scala:46:7, :139:{33,36}] wire _exe_rs1_data_T = |exe_rs1_addr; // @[dpath.scala:134:35, :157:41] wire [31:0] exe_rs1_data = _exe_rs1_data_T ? _regfile_ext_R2_data : 32'h0; // @[dpath.scala:142:21, :157:{26,41}] wire [31:0] _io_dat_br_lt_T = exe_rs1_data; // @[dpath.scala:157:26, :279:35] wire _exe_rs2_data_T = |exe_rs2_addr; // @[dpath.scala:135:35, :158:41] assign exe_rs2_data = _exe_rs2_data_T ? _regfile_ext_R1_data : 32'h0; // @[dpath.scala:142:21, :158:{26,41}] assign io_dmem_req_bits_data_0 = exe_rs2_data; // @[dpath.scala:46:7, :158:26] wire [31:0] _io_dat_br_lt_T_1 = exe_rs2_data; // @[dpath.scala:158:26, :279:57] wire [11:0] imm_i = exe_reg_inst[31:20]; // @[dpath.scala:61:34, :162:28] wire [11:0] _csr_io_rw_addr_T = exe_reg_inst[31:20]; // @[dpath.scala:61:34, :162:28, :231:35] wire [6:0] _imm_s_T = exe_reg_inst[31:25]; // @[dpath.scala:61:34, :163:32] wire [11:0] imm_s = {_imm_s_T, _imm_s_T_1}; // @[dpath.scala:163:{19,32,54}] wire _imm_b_T = exe_reg_inst[31]; // @[dpath.scala:61:34, :164:32] wire _imm_j_T = exe_reg_inst[31]; // @[dpath.scala:61:34, :164:32, :166:32] wire _imm_b_T_1 = exe_reg_inst[7]; // @[dpath.scala:61:34, :164:50] wire [5:0] _imm_b_T_2 = exe_reg_inst[30:25]; // @[dpath.scala:61:34, :164:67] wire [3:0] _imm_b_T_3 = exe_reg_inst[11:8]; // @[dpath.scala:61:34, :164:88] wire [9:0] imm_b_lo = {_imm_b_T_2, _imm_b_T_3}; // @[dpath.scala:164:{19,67,88}] wire [1:0] imm_b_hi = {_imm_b_T, _imm_b_T_1}; // @[dpath.scala:164:{19,32,50}] wire [11:0] imm_b = {imm_b_hi, imm_b_lo}; // @[dpath.scala:164:19] wire [19:0] imm_u = exe_reg_inst[31:12]; // @[dpath.scala:61:34, :165:28] wire [7:0] _imm_j_T_1 = exe_reg_inst[19:12]; // @[dpath.scala:61:34, :166:50] wire _imm_j_T_2 = exe_reg_inst[20]; // @[dpath.scala:61:34, :166:71] wire [9:0] _imm_j_T_3 = exe_reg_inst[30:21]; // @[dpath.scala:61:34, :166:89] wire [10:0] imm_j_lo = {_imm_j_T_2, _imm_j_T_3}; // @[dpath.scala:166:{19,71,89}] wire [8:0] imm_j_hi = {_imm_j_T, _imm_j_T_1}; // @[dpath.scala:166:{19,32,50}] wire [19:0] imm_j = {imm_j_hi, imm_j_lo}; // @[dpath.scala:166:19] wire [31:0] imm_z = {27'h0, _imm_z_T_1}; // @[dpath.scala:167:{19,46}] wire _imm_i_sext_T = imm_i[11]; // @[dpath.scala:162:28, :170:38] wire [19:0] _imm_i_sext_T_1 = {20{_imm_i_sext_T}}; // @[dpath.scala:170:{29,38}] wire [31:0] imm_i_sext = {_imm_i_sext_T_1, imm_i}; // @[dpath.scala:162:28, :170:{24,29}] wire _imm_s_sext_T = imm_s[11]; // @[dpath.scala:163:19, :171:38] wire [19:0] _imm_s_sext_T_1 = {20{_imm_s_sext_T}}; // @[dpath.scala:171:{29,38}] wire [31:0] imm_s_sext = {_imm_s_sext_T_1, imm_s}; // @[dpath.scala:163:19, :171:{24,29}] wire _imm_b_sext_T = imm_b[11]; // @[dpath.scala:164:19, :172:38] wire [18:0] _imm_b_sext_T_1 = {19{_imm_b_sext_T}}; // @[dpath.scala:172:{29,38}] wire [30:0] imm_b_sext_hi = {_imm_b_sext_T_1, imm_b}; // @[dpath.scala:164:19, :172:{24,29}] wire [31:0] imm_b_sext = {imm_b_sext_hi, 1'h0}; // @[dpath.scala:172:24] wire [31:0] imm_u_sext = {imm_u, 12'h0}; // @[dpath.scala:165:28, :173:24] wire _imm_j_sext_T = imm_j[19]; // @[dpath.scala:166:19, :174:38] wire [10:0] _imm_j_sext_T_1 = {11{_imm_j_sext_T}}; // @[dpath.scala:174:{29,38}] wire [30:0] imm_j_sext_hi = {_imm_j_sext_T_1, imm_j}; // @[dpath.scala:166:19, :174:{24,29}] wire [31:0] imm_j_sext = {imm_j_sext_hi, 1'h0}; // @[dpath.scala:174:24] wire _exe_alu_op1_T = io_ctl_op1_sel_0 == 2'h0; // @[dpath.scala:46:7, :178:32] wire _exe_alu_op1_T_1 = io_ctl_op1_sel_0 == 2'h1; // @[dpath.scala:46:7, :179:32] wire _exe_alu_op1_T_2 = io_ctl_op1_sel_0 == 2'h2; // @[dpath.scala:46:7, :180:32] wire [31:0] _exe_alu_op1_T_3 = _exe_alu_op1_T_2 ? imm_z : 32'h0; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op1_T_4 = _exe_alu_op1_T_1 ? imm_u_sext : _exe_alu_op1_T_3; // @[Mux.scala:126:16] wire [31:0] exe_alu_op1 = _exe_alu_op1_T ? exe_rs1_data : _exe_alu_op1_T_4; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_13 = exe_alu_op1; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_22 = exe_alu_op1; // @[Mux.scala:126:16] wire _exe_alu_op2_T = io_ctl_op2_sel_0 == 3'h0; // @[dpath.scala:46:7, :184:32] wire _exe_alu_op2_T_1 = io_ctl_op2_sel_0 == 3'h1; // @[dpath.scala:46:7, :185:32] wire _exe_alu_op2_T_2 = io_ctl_op2_sel_0 == 3'h2; // @[dpath.scala:46:7, :186:32] wire _exe_alu_op2_T_3 = io_ctl_op2_sel_0 == 3'h3; // @[dpath.scala:46:7, :187:32] wire [31:0] _exe_alu_op2_T_4 = _exe_alu_op2_T_3 ? imm_s_sext : 32'h0; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op2_T_5 = _exe_alu_op2_T_2 ? imm_i_sext : _exe_alu_op2_T_4; // @[Mux.scala:126:16] wire [31:0] _exe_alu_op2_T_6 = _exe_alu_op2_T_1 ? exe_reg_pc : _exe_alu_op2_T_5; // @[Mux.scala:126:16] wire [31:0] exe_alu_op2 = _exe_alu_op2_T ? exe_rs2_data : _exe_alu_op2_T_6; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_14 = exe_alu_op2; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_38; // @[Mux.scala:126:16] assign io_dmem_req_bits_addr_0 = exe_alu_out; // @[dpath.scala:46:7, :192:28] assign tval_data_ma = exe_alu_out; // @[dpath.scala:52:27, :192:28] wire [4:0] alu_shamt = exe_alu_op2[4:0]; // @[Mux.scala:126:16] wire _exe_alu_out_T = io_ctl_alu_fun_0 == 5'h1; // @[dpath.scala:46:7, :197:35] wire [32:0] _GEN = {1'h0, exe_alu_op1}; // @[Mux.scala:126:16] wire [32:0] _GEN_0 = {1'h0, exe_alu_op2}; // @[Mux.scala:126:16] wire [32:0] _exe_alu_out_T_1 = _GEN + _GEN_0; // @[dpath.scala:197:65] wire [31:0] _exe_alu_out_T_2 = _exe_alu_out_T_1[31:0]; // @[dpath.scala:197:65] wire _exe_alu_out_T_3 = io_ctl_alu_fun_0 == 5'h2; // @[dpath.scala:46:7, :198:35] wire [32:0] _exe_alu_out_T_4 = _GEN - _GEN_0; // @[dpath.scala:197:65, :198:65] wire [31:0] _exe_alu_out_T_5 = _exe_alu_out_T_4[31:0]; // @[dpath.scala:198:65] wire _exe_alu_out_T_6 = io_ctl_alu_fun_0 == 5'h6; // @[dpath.scala:46:7, :199:35] wire [31:0] _exe_alu_out_T_7 = exe_alu_op1 & exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_8 = io_ctl_alu_fun_0 == 5'h7; // @[dpath.scala:46:7, :200:35] wire [31:0] _exe_alu_out_T_9 = exe_alu_op1 | exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_10 = io_ctl_alu_fun_0 == 5'h8; // @[dpath.scala:46:7, :201:35] wire [31:0] _exe_alu_out_T_11 = exe_alu_op1 ^ exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_12 = io_ctl_alu_fun_0 == 5'h9; // @[dpath.scala:46:7, :202:35] wire _exe_alu_out_T_15 = $signed(_exe_alu_out_T_13) < $signed(_exe_alu_out_T_14); // @[dpath.scala:202:{65,72,86}] wire _exe_alu_out_T_16 = io_ctl_alu_fun_0 == 5'hA; // @[dpath.scala:46:7, :203:35] wire _exe_alu_out_T_17 = exe_alu_op1 < exe_alu_op2; // @[Mux.scala:126:16] wire _exe_alu_out_T_18 = io_ctl_alu_fun_0 == 5'h3; // @[dpath.scala:46:7, :204:35] wire [62:0] _exe_alu_out_T_19 = {31'h0, exe_alu_op1} << alu_shamt; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_20 = _exe_alu_out_T_19[31:0]; // @[dpath.scala:204:{66,79}] wire _exe_alu_out_T_21 = io_ctl_alu_fun_0 == 5'h5; // @[dpath.scala:46:7, :205:35] wire [31:0] _GEN_1 = {27'h0, alu_shamt}; // @[dpath.scala:194:31, :205:72] wire [31:0] _exe_alu_out_T_23 = $signed($signed(_exe_alu_out_T_22) >>> _GEN_1); // @[dpath.scala:205:{65,72}] wire [31:0] _exe_alu_out_T_24 = _exe_alu_out_T_23; // @[dpath.scala:205:{72,86}] wire _exe_alu_out_T_25 = io_ctl_alu_fun_0 == 5'h4; // @[dpath.scala:46:7, :206:35] wire [31:0] _exe_alu_out_T_26 = exe_alu_op1 >> _GEN_1; // @[Mux.scala:126:16] wire _exe_alu_out_T_27 = io_ctl_alu_fun_0 == 5'hB; // @[dpath.scala:46:7, :207:35] wire [31:0] _exe_alu_out_T_28 = _exe_alu_out_T_27 ? exe_alu_op1 : 32'h0; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_25 ? _exe_alu_out_T_26 : _exe_alu_out_T_28; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_30 = _exe_alu_out_T_21 ? _exe_alu_out_T_24 : _exe_alu_out_T_29; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_31 = _exe_alu_out_T_18 ? _exe_alu_out_T_20 : _exe_alu_out_T_30; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_32 = _exe_alu_out_T_16 ? {31'h0, _exe_alu_out_T_17} : _exe_alu_out_T_31; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_33 = _exe_alu_out_T_12 ? {31'h0, _exe_alu_out_T_15} : _exe_alu_out_T_32; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_34 = _exe_alu_out_T_10 ? _exe_alu_out_T_11 : _exe_alu_out_T_33; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_35 = _exe_alu_out_T_8 ? _exe_alu_out_T_9 : _exe_alu_out_T_34; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_36 = _exe_alu_out_T_6 ? _exe_alu_out_T_7 : _exe_alu_out_T_35; // @[Mux.scala:126:16] wire [31:0] _exe_alu_out_T_37 = _exe_alu_out_T_3 ? _exe_alu_out_T_5 : _exe_alu_out_T_36; // @[Mux.scala:126:16] assign _exe_alu_out_T_38 = _exe_alu_out_T ? _exe_alu_out_T_2 : _exe_alu_out_T_37; // @[Mux.scala:126:16] assign exe_alu_out = _exe_alu_out_T_38; // @[Mux.scala:126:16] wire [32:0] _GEN_2 = {1'h0, exe_reg_pc}; // @[dpath.scala:59:34, :211:38] wire [32:0] _exe_br_target_T = _GEN_2 + {1'h0, imm_b_sext}; // @[dpath.scala:172:24, :211:38] assign _exe_br_target_T_1 = _exe_br_target_T[31:0]; // @[dpath.scala:211:38] assign exe_br_target = _exe_br_target_T_1; // @[dpath.scala:67:34, :211:38] wire [32:0] _exe_jmp_target_T = _GEN_2 + {1'h0, imm_j_sext}; // @[dpath.scala:174:24, :211:38, :212:38] assign _exe_jmp_target_T_1 = _exe_jmp_target_T[31:0]; // @[dpath.scala:212:38] assign exe_jmp_target = _exe_jmp_target_T_1; // @[dpath.scala:68:34, :212:38] wire [32:0] _exe_jump_reg_target_T = {1'h0, exe_rs1_data} + {1'h0, imm_i_sext}; // @[dpath.scala:157:26, :170:24, :213:48] wire [31:0] _exe_jump_reg_target_T_1 = _exe_jump_reg_target_T[31:0]; // @[dpath.scala:213:48] assign _exe_jump_reg_target_T_3 = _exe_jump_reg_target_T_1 & 32'hFFFFFFFE; // @[dpath.scala:213:{48,69}] assign exe_jump_reg_target = _exe_jump_reg_target_T_3; // @[dpath.scala:69:34, :213:69] wire [1:0] _io_dat_inst_misaligned_T = exe_br_target[1:0]; // @[dpath.scala:67:34, :218:45] wire _io_dat_inst_misaligned_T_1 = |_io_dat_inst_misaligned_T; // @[dpath.scala:218:{45,52}] wire _GEN_3 = io_ctl_pc_sel_no_xept_0 == 3'h1; // @[dpath.scala:46:7, :218:87] wire _io_dat_inst_misaligned_T_2; // @[dpath.scala:218:87] assign _io_dat_inst_misaligned_T_2 = _GEN_3; // @[dpath.scala:218:87] wire _tval_inst_ma_T; // @[dpath.scala:222:42] assign _tval_inst_ma_T = _GEN_3; // @[dpath.scala:218:87, :222:42] wire _io_dat_inst_misaligned_T_3 = _io_dat_inst_misaligned_T_1 & _io_dat_inst_misaligned_T_2; // @[dpath.scala:218:{52,62,87}] wire [1:0] _io_dat_inst_misaligned_T_4 = exe_jmp_target[1:0]; // @[dpath.scala:68:34, :219:46] wire _io_dat_inst_misaligned_T_5 = |_io_dat_inst_misaligned_T_4; // @[dpath.scala:219:{46,53}] wire _GEN_4 = io_ctl_pc_sel_no_xept_0 == 3'h2; // @[dpath.scala:46:7, :219:87] wire _io_dat_inst_misaligned_T_6; // @[dpath.scala:219:87] assign _io_dat_inst_misaligned_T_6 = _GEN_4; // @[dpath.scala:219:87] wire _tval_inst_ma_T_1; // @[dpath.scala:223:42] assign _tval_inst_ma_T_1 = _GEN_4; // @[dpath.scala:219:87, :223:42] wire _io_dat_inst_misaligned_T_7 = _io_dat_inst_misaligned_T_5 & _io_dat_inst_misaligned_T_6; // @[dpath.scala:219:{53,62,87}] wire _io_dat_inst_misaligned_T_8 = _io_dat_inst_misaligned_T_3 | _io_dat_inst_misaligned_T_7; // @[dpath.scala:218:{62,98}, :219:62] wire [1:0] _io_dat_inst_misaligned_T_9 = exe_jump_reg_target[1:0]; // @[dpath.scala:69:34, :220:51] wire _io_dat_inst_misaligned_T_10 = |_io_dat_inst_misaligned_T_9; // @[dpath.scala:220:{51,58}] wire _GEN_5 = io_ctl_pc_sel_no_xept_0 == 3'h3; // @[dpath.scala:46:7, :220:87] wire _io_dat_inst_misaligned_T_11; // @[dpath.scala:220:87] assign _io_dat_inst_misaligned_T_11 = _GEN_5; // @[dpath.scala:220:87] wire _tval_inst_ma_T_2; // @[dpath.scala:224:42] assign _tval_inst_ma_T_2 = _GEN_5; // @[dpath.scala:220:87, :224:42] wire _io_dat_inst_misaligned_T_12 = _io_dat_inst_misaligned_T_10 & _io_dat_inst_misaligned_T_11; // @[dpath.scala:220:{58,62,87}] assign _io_dat_inst_misaligned_T_13 = _io_dat_inst_misaligned_T_8 | _io_dat_inst_misaligned_T_12; // @[dpath.scala:218:98, :219:98, :220:62] assign io_dat_inst_misaligned_0 = _io_dat_inst_misaligned_T_13; // @[dpath.scala:46:7, :219:98] wire [31:0] _tval_inst_ma_T_3 = _tval_inst_ma_T_2 ? exe_jump_reg_target : 32'h0; // @[Mux.scala:126:16] wire [31:0] _tval_inst_ma_T_4 = _tval_inst_ma_T_1 ? exe_jmp_target : _tval_inst_ma_T_3; // @[Mux.scala:126:16] assign _tval_inst_ma_T_5 = _tval_inst_ma_T ? exe_br_target : _tval_inst_ma_T_4; // @[Mux.scala:126:16] assign tval_inst_ma = _tval_inst_ma_T_5; // @[Mux.scala:126:16] wire _csr_io_retire_T = io_ctl_stall_0 | io_ctl_exception_0; // @[dpath.scala:46:7, :236:56] wire _csr_io_retire_T_1 = ~_csr_io_retire_T; // @[dpath.scala:236:{41,56}] wire _csr_io_retire_T_2 = exe_reg_valid & _csr_io_retire_T_1; // @[dpath.scala:62:34, :236:{38,41}] wire _csr_io_tval_T = io_ctl_exception_cause_0 == 32'h2; // @[dpath.scala:46:7, :242:43] wire _csr_io_tval_T_1 = io_ctl_exception_cause_0 == 32'h0; // @[dpath.scala:46:7, :243:43] wire _csr_io_tval_T_2 = io_ctl_exception_cause_0 == 32'h6; // @[dpath.scala:46:7, :244:43] wire _csr_io_tval_T_3 = io_ctl_exception_cause_0 == 32'h4; // @[dpath.scala:46:7, :245:43] wire [31:0] _csr_io_tval_T_4 = _csr_io_tval_T_3 ? tval_data_ma : 32'h0; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_5 = _csr_io_tval_T_2 ? tval_data_ma : _csr_io_tval_T_4; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_6 = _csr_io_tval_T_1 ? tval_inst_ma : _csr_io_tval_T_5; // @[Mux.scala:126:16] wire [31:0] _csr_io_tval_T_7 = _csr_io_tval_T ? exe_reg_inst : _csr_io_tval_T_6; // @[Mux.scala:126:16] reg reg_interrupt_handled; // @[dpath.scala:249:39] wire _interrupt_edge_T = ~reg_interrupt_handled; // @[dpath.scala:249:39, :253:45] assign interrupt_edge = _csr_io_interrupt & _interrupt_edge_T; // @[dpath.scala:228:20, :253:{42,45}] assign io_dat_csr_interrupt_0 = interrupt_edge; // @[dpath.scala:46:7, :253:42] wire [31:0] _csr_io_cause_T = io_ctl_exception_0 ? io_ctl_exception_cause_0 : _csr_io_interrupt_cause; // @[dpath.scala:46:7, :228:20, :258:23] wire _exe_wbdata_T = io_ctl_wb_sel_0 == 2'h0; // @[dpath.scala:46:7, :269:34] wire _exe_wbdata_T_1 = io_ctl_wb_sel_0 == 2'h1; // @[dpath.scala:46:7, :270:34] wire _exe_wbdata_T_2 = io_ctl_wb_sel_0 == 2'h2; // @[dpath.scala:46:7, :271:34] wire _exe_wbdata_T_3 = &io_ctl_wb_sel_0; // @[dpath.scala:46:7, :272:34] wire [31:0] _exe_wbdata_T_4 = _exe_wbdata_T_3 ? _csr_io_rw_rdata : exe_alu_out; // @[Mux.scala:126:16] wire [31:0] _exe_wbdata_T_5 = _exe_wbdata_T_2 ? exe_reg_pc_plus4 : _exe_wbdata_T_4; // @[Mux.scala:126:16] wire [31:0] _exe_wbdata_T_6 = _exe_wbdata_T_1 ? io_dmem_resp_bits_data_0 : _exe_wbdata_T_5; // @[Mux.scala:126:16] assign _exe_wbdata_T_7 = _exe_wbdata_T ? exe_alu_out : _exe_wbdata_T_6; // @[Mux.scala:126:16] assign exe_wbdata = _exe_wbdata_T_7; // @[Mux.scala:126:16] assign _io_dat_br_eq_T = exe_rs1_data == exe_rs2_data; // @[dpath.scala:157:26, :158:26, :278:35] assign io_dat_br_eq_0 = _io_dat_br_eq_T; // @[dpath.scala:46:7, :278:35] assign _io_dat_br_lt_T_2 = $signed(_io_dat_br_lt_T) < $signed(_io_dat_br_lt_T_1); // @[dpath.scala:279:{35,42,57}] assign io_dat_br_lt_0 = _io_dat_br_lt_T_2; // @[dpath.scala:46:7, :279:42] assign _io_dat_br_ltu_T = exe_rs1_data < exe_rs2_data; // @[dpath.scala:157:26, :158:26, :280:42] assign io_dat_br_ltu_0 = _io_dat_br_ltu_T; // @[dpath.scala:46:7, :280:42] wire [2:0] misaligned_mask; // @[dpath.scala:284:30] wire [3:0] _misaligned_mask_T = {1'h0, io_ctl_mem_typ_0} - 4'h1; // @[dpath.scala:46:7, :285:53] wire [2:0] _misaligned_mask_T_1 = _misaligned_mask_T[2:0]; // @[dpath.scala:285:53] wire [1:0] _misaligned_mask_T_2 = _misaligned_mask_T_1[1:0]; // @[dpath.scala:285:{53,59}] wire [5:0] _misaligned_mask_T_3 = 6'h7 << _misaligned_mask_T_2; // @[dpath.scala:285:{34,59}] wire [5:0] _misaligned_mask_T_4 = ~_misaligned_mask_T_3; // @[dpath.scala:285:{23,34}] assign misaligned_mask = _misaligned_mask_T_4[2:0]; // @[dpath.scala:284:30, :285:{20,23}] wire [2:0] _io_dat_data_misaligned_T = exe_alu_out[2:0]; // @[dpath.scala:192:28, :286:73] wire [2:0] _io_dat_data_misaligned_T_1 = misaligned_mask & _io_dat_data_misaligned_T; // @[dpath.scala:284:30, :286:{47,73}] wire _io_dat_data_misaligned_T_2 = |_io_dat_data_misaligned_T_1; // @[dpath.scala:286:{47,81}] assign _io_dat_data_misaligned_T_3 = _io_dat_data_misaligned_T_2 & io_ctl_mem_val_0; // @[dpath.scala:46:7, :286:{81,85}] assign io_dat_data_misaligned_0 = _io_dat_data_misaligned_T_3; // @[dpath.scala:46:7, :286:85] assign _io_dat_mem_store_T = io_ctl_mem_fcn_0 == 2'h1; // @[dpath.scala:46:7, :287:39] assign io_dat_mem_store_0 = _io_dat_mem_store_T; // @[dpath.scala:46:7, :287:39]

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 13, 13) wire common_expOut : UInt<6> wire common_fractOut : UInt<10> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 5, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _roundMask_T_1) node _roundMask_T_2 = bits(roundMask_shift, 18, 7) node _roundMask_T_3 = bits(_roundMask_T_2, 7, 0) node _roundMask_T_4 = shl(UInt<4>(0hf), 4) node _roundMask_T_5 = xor(UInt<8>(0hff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 4) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 3, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 4) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 5, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 2) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 2) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 5, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 2) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 6, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 1) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 1) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 6, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 1) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_2, 11, 8) node _roundMask_T_34 = bits(_roundMask_T_33, 1, 0) node _roundMask_T_35 = bits(_roundMask_T_34, 0, 0) node _roundMask_T_36 = bits(_roundMask_T_34, 1, 1) node _roundMask_T_37 = cat(_roundMask_T_35, _roundMask_T_36) node _roundMask_T_38 = bits(_roundMask_T_33, 3, 2) node _roundMask_T_39 = bits(_roundMask_T_38, 0, 0) node _roundMask_T_40 = bits(_roundMask_T_38, 1, 1) node _roundMask_T_41 = cat(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = cat(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = cat(_roundMask_T_32, _roundMask_T_42) node _roundMask_T_44 = or(_roundMask_T_43, doShiftSigDown1) node roundMask = cat(_roundMask_T_44, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<13>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 11) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 5, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 10, 1) node _common_fractOut_T_1 = bits(roundedSig, 9, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 4) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<5>(0h8))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 12, 12) node _roundCarry_T_1 = bits(roundedSig, 11, 11) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 5) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<6>(0h38), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<6>(0h8)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<6>(0h10), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<6>(0h8), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<6>(0h8), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<6>(0h2f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<6>(0h30), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<6>(0h38), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<10>(0h200), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<10>(0h3ff), UInt<10>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_1( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20] wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [13:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[13]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [5:0] _roundMask_T = io_in_sExp_0[5:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56] wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22] wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22] wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20] wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20] wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_44 = {_roundMask_T_43[11:1], _roundMask_T_43[0] | doShiftSigDown1}; // @[primitives.scala:77:20] wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [13:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [7:0] sRoundedExp = {io_in_sExp_0[6], io_in_sExp_0} + {{5{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[7:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 8'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[6:5]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [5:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [5:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<15>(0h4000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_38, _T_43) node _T_85 = or(_T_84, _T_48) node _T_86 = or(_T_85, _T_53) node _T_87 = or(_T_86, _T_58) node _T_88 = or(_T_87, _T_63) node _T_89 = or(_T_88, _T_68) node _T_90 = or(_T_89, _T_73) node _T_91 = or(_T_90, _T_78) node _T_92 = or(_T_91, _T_83) node _T_93 = and(_T_33, _T_92) node _T_94 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<29>(0h10000000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = or(_T_100, _T_105) node _T_107 = and(_T_95, _T_106) node _T_108 = or(UInt<1>(0h0), _T_93) node _T_109 = or(_T_108, _T_107) node _T_110 = and(_T_32, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_110, UInt<1>(0h1), "") : assert_2 node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_115 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_114 connect _WIRE[1], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_117, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_119 node _T_120 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_121 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_122 = and(_T_120, _T_121) node _T_123 = or(UInt<1>(0h0), _T_122) node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_125 = cvt(_T_124) node _T_126 = and(_T_125, asSInt(UInt<14>(0h2000))) node _T_127 = asSInt(_T_126) node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0))) node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<17>(0h10000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<15>(0h4000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<18>(0h2f000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<17>(0h10000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<17>(0h10000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = or(_T_128, _T_133) node _T_185 = or(_T_184, _T_138) node _T_186 = or(_T_185, _T_143) node _T_187 = or(_T_186, _T_148) node _T_188 = or(_T_187, _T_153) node _T_189 = or(_T_188, _T_158) node _T_190 = or(_T_189, _T_163) node _T_191 = or(_T_190, _T_168) node _T_192 = or(_T_191, _T_173) node _T_193 = or(_T_192, _T_178) node _T_194 = or(_T_193, _T_183) node _T_195 = and(_T_123, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = and(_WIRE_1, _T_196) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_197, UInt<1>(0h1), "") : assert_3 node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(source_ok, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_204 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_204, UInt<1>(0h1), "") : assert_5 node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(is_aligned, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_211 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_211, UInt<1>(0h1), "") : assert_7 node _T_215 = not(io.in.a.bits.mask) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_216, UInt<1>(0h1), "") : assert_8 node _T_220 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_220, UInt<1>(0h1), "") : assert_9 node _T_224 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_224 : node _T_225 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_226 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_229 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_230 = or(_T_228, _T_229) node _T_231 = and(_T_227, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<15>(0h4000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<13>(0h1000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<18>(0h2f000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<17>(0h10000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<27>(0h4000000))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<13>(0h1000))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_238, _T_243) node _T_285 = or(_T_284, _T_248) node _T_286 = or(_T_285, _T_253) node _T_287 = or(_T_286, _T_258) node _T_288 = or(_T_287, _T_263) node _T_289 = or(_T_288, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = and(_T_233, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_232, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _T_314 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_314 connect _WIRE_2[1], _T_315 node _T_316 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_317 = mux(_WIRE_2[0], _T_316, UInt<1>(0h0)) node _T_318 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = or(_T_317, _T_318) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_319 node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<14>(0h2000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<13>(0h1000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<15>(0h4000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<18>(0h2f000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_328, _T_333) node _T_385 = or(_T_384, _T_338) node _T_386 = or(_T_385, _T_343) node _T_387 = or(_T_386, _T_348) node _T_388 = or(_T_387, _T_353) node _T_389 = or(_T_388, _T_358) node _T_390 = or(_T_389, _T_363) node _T_391 = or(_T_390, _T_368) node _T_392 = or(_T_391, _T_373) node _T_393 = or(_T_392, _T_378) node _T_394 = or(_T_393, _T_383) node _T_395 = and(_T_323, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = and(_WIRE_3, _T_396) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_397, UInt<1>(0h1), "") : assert_11 node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(source_ok, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_404 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_404, UInt<1>(0h1), "") : assert_13 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(is_aligned, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_411 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_411, UInt<1>(0h1), "") : assert_15 node _T_415 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_415, UInt<1>(0h1), "") : assert_16 node _T_419 = not(io.in.a.bits.mask) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_420, UInt<1>(0h1), "") : assert_17 node _T_424 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_424, UInt<1>(0h1), "") : assert_18 node _T_428 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_428 : node _T_429 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_430 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_433 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_434 = or(_T_432, _T_433) node _T_435 = and(_T_431, _T_434) node _T_436 = or(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_436, UInt<1>(0h1), "") : assert_19 node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = and(_T_443, _T_448) node _T_450 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_451 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_452 = and(_T_450, _T_451) node _T_453 = or(UInt<1>(0h0), _T_452) node _T_454 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<14>(0h2000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<18>(0h2f000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<13>(0h1000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<27>(0h4000000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<29>(0h10000000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = or(_T_458, _T_463) node _T_500 = or(_T_499, _T_468) node _T_501 = or(_T_500, _T_473) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_483) node _T_504 = or(_T_503, _T_488) node _T_505 = or(_T_504, _T_493) node _T_506 = or(_T_505, _T_498) node _T_507 = and(_T_453, _T_506) node _T_508 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_509 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_510 = and(_T_508, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<15>(0h4000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = or(_T_516, _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = or(UInt<1>(0h0), _T_449) node _T_525 = or(_T_524, _T_507) node _T_526 = or(_T_525, _T_523) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_526, UInt<1>(0h1), "") : assert_20 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_536 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_536, UInt<1>(0h1), "") : assert_23 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_540, UInt<1>(0h1), "") : assert_24 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_544, UInt<1>(0h1), "") : assert_25 node _T_548 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_553 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_554 = or(_T_552, _T_553) node _T_555 = and(_T_551, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = and(_T_560, _T_565) node _T_567 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_568 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<14>(0h2000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<18>(0h2f000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<17>(0h10000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<17>(0h10000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<27>(0h4000000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<13>(0h1000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<29>(0h10000000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = or(_T_575, _T_580) node _T_612 = or(_T_611, _T_585) node _T_613 = or(_T_612, _T_590) node _T_614 = or(_T_613, _T_595) node _T_615 = or(_T_614, _T_600) node _T_616 = or(_T_615, _T_605) node _T_617 = or(_T_616, _T_610) node _T_618 = and(_T_570, _T_617) node _T_619 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_620 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<15>(0h4000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = or(_T_634, _T_639) node _T_641 = and(_T_629, _T_640) node _T_642 = or(UInt<1>(0h0), _T_566) node _T_643 = or(_T_642, _T_618) node _T_644 = or(_T_643, _T_625) node _T_645 = or(_T_644, _T_641) node _T_646 = and(_T_556, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_646, UInt<1>(0h1), "") : assert_26 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(is_aligned, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_656 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(_T_656, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_656, UInt<1>(0h1), "") : assert_29 node _T_660 = eq(io.in.a.bits.mask, mask) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_660, UInt<1>(0h1), "") : assert_30 node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_664 : node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_669 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_670 = or(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_675 = and(_T_673, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<13>(0h1000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_685 = and(_T_683, _T_684) node _T_686 = or(UInt<1>(0h0), _T_685) node _T_687 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_688 = cvt(_T_687) node _T_689 = and(_T_688, asSInt(UInt<14>(0h2000))) node _T_690 = asSInt(_T_689) node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0))) node _T_692 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<18>(0h2f000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<17>(0h10000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<13>(0h1000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_718 = cvt(_T_717) node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000))) node _T_720 = asSInt(_T_719) node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0))) node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_723 = cvt(_T_722) node _T_724 = and(_T_723, asSInt(UInt<29>(0h10000000))) node _T_725 = asSInt(_T_724) node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0))) node _T_727 = or(_T_691, _T_696) node _T_728 = or(_T_727, _T_701) node _T_729 = or(_T_728, _T_706) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_716) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_726) node _T_734 = and(_T_686, _T_733) node _T_735 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_736 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = and(_T_735, _T_740) node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_743 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_744 = and(_T_742, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_682) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_757) node _T_762 = and(_T_672, _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_762, UInt<1>(0h1), "") : assert_31 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(is_aligned, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_772 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_772, UInt<1>(0h1), "") : assert_34 node _T_776 = not(mask) node _T_777 = and(io.in.a.bits.mask, _T_776) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_778, UInt<1>(0h1), "") : assert_35 node _T_782 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_787 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_788 = or(_T_786, _T_787) node _T_789 = and(_T_785, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<15>(0h4000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<18>(0h2f000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<29>(0h10000000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_799, _T_804) node _T_851 = or(_T_850, _T_809) node _T_852 = or(_T_851, _T_814) node _T_853 = or(_T_852, _T_819) node _T_854 = or(_T_853, _T_824) node _T_855 = or(_T_854, _T_829) node _T_856 = or(_T_855, _T_834) node _T_857 = or(_T_856, _T_839) node _T_858 = or(_T_857, _T_844) node _T_859 = or(_T_858, _T_849) node _T_860 = and(_T_794, _T_859) node _T_861 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_862 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<17>(0h10000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = and(_T_861, _T_866) node _T_868 = or(UInt<1>(0h0), _T_860) node _T_869 = or(_T_868, _T_867) node _T_870 = and(_T_790, _T_869) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_870, UInt<1>(0h1), "") : assert_36 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(source_ok, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(is_aligned, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_880 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_880, UInt<1>(0h1), "") : assert_39 node _T_884 = eq(io.in.a.bits.mask, mask) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_884, UInt<1>(0h1), "") : assert_40 node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_888 : node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_893 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_894 = or(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<14>(0h2000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<15>(0h4000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<13>(0h1000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<18>(0h2f000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<17>(0h10000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_932 = cvt(_T_931) node _T_933 = and(_T_932, asSInt(UInt<13>(0h1000))) node _T_934 = asSInt(_T_933) node _T_935 = eq(_T_934, asSInt(UInt<1>(0h0))) node _T_936 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<17>(0h10000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_942 = cvt(_T_941) node _T_943 = and(_T_942, asSInt(UInt<27>(0h4000000))) node _T_944 = asSInt(_T_943) node _T_945 = eq(_T_944, asSInt(UInt<1>(0h0))) node _T_946 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<13>(0h1000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<29>(0h10000000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = or(_T_905, _T_910) node _T_957 = or(_T_956, _T_915) node _T_958 = or(_T_957, _T_920) node _T_959 = or(_T_958, _T_925) node _T_960 = or(_T_959, _T_930) node _T_961 = or(_T_960, _T_935) node _T_962 = or(_T_961, _T_940) node _T_963 = or(_T_962, _T_945) node _T_964 = or(_T_963, _T_950) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_900, _T_965) node _T_967 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = and(_T_967, _T_972) node _T_974 = or(UInt<1>(0h0), _T_966) node _T_975 = or(_T_974, _T_973) node _T_976 = and(_T_896, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_976, UInt<1>(0h1), "") : assert_41 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_986 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_986, UInt<1>(0h1), "") : assert_44 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_990, UInt<1>(0h1), "") : assert_45 node _T_994 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_994 : node _T_995 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_996 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_997 = and(_T_995, _T_996) node _T_998 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_999 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_1000 = or(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) node _T_1002 = or(UInt<1>(0h0), _T_1001) node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = and(_T_1006, _T_1011) node _T_1013 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1014 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<14>(0h2000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<15>(0h4000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<18>(0h2f000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<13>(0h1000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<27>(0h4000000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1055 = cvt(_T_1054) node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000))) node _T_1057 = asSInt(_T_1056) node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0))) node _T_1059 = or(_T_1018, _T_1023) node _T_1060 = or(_T_1059, _T_1028) node _T_1061 = or(_T_1060, _T_1033) node _T_1062 = or(_T_1061, _T_1038) node _T_1063 = or(_T_1062, _T_1043) node _T_1064 = or(_T_1063, _T_1048) node _T_1065 = or(_T_1064, _T_1053) node _T_1066 = or(_T_1065, _T_1058) node _T_1067 = and(_T_1013, _T_1066) node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = or(UInt<1>(0h0), _T_1070) node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1073 = cvt(_T_1072) node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000))) node _T_1075 = asSInt(_T_1074) node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0))) node _T_1077 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<29>(0h10000000))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _T_1083 = and(_T_1071, _T_1082) node _T_1084 = or(UInt<1>(0h0), _T_1012) node _T_1085 = or(_T_1084, _T_1067) node _T_1086 = or(_T_1085, _T_1083) node _T_1087 = and(_T_1002, _T_1086) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_46 node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(is_aligned, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1097 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_49 node _T_1101 = eq(io.in.a.bits.mask, mask) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_50 node _T_1105 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1109 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_54 node _T_1121 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_55 node _T_1125 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_56 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_57 node _T_1133 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1133 : node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(source_ok_1, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(sink_ok, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1140 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_60 node _T_1144 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_61 node _T_1148 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_62 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_63 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = or(UInt<1>(0h1), _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_64 node _T_1161 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1161 : node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok_1, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(sink_ok, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1168 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_67 node _T_1172 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_68 node _T_1176 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_69 node _T_1180 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1181 = or(_T_1180, io.in.d.bits.corrupt) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_70 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_71 node _T_1190 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1190 : node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(source_ok_1, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1194 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_73 node _T_1198 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_74 node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1203 = or(UInt<1>(0h1), _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_75 node _T_1207 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1207 : node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(source_ok_1, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1211 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_77 node _T_1215 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1216 = or(_T_1215, io.in.d.bits.corrupt) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_78 node _T_1220 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1221 = or(UInt<1>(0h1), _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_79 node _T_1225 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1225 : node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(source_ok_1, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_81 node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_82 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1242 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_84 node _T_1246 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = or(_T_1247, _T_1252) node _T_1254 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) node _T_1256 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1255, _T_1260) node _T_1262 = and(_T_1253, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<18>(0h21000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<18>(0h22000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<13>(0h1000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<18>(0h23000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<13>(0h1000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[17] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2]) node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3]) node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4]) node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5]) node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15]) node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1266 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1266 : node _T_1267 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1268 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1267 connect _WIRE_4[1], _T_1268 node _T_1269 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1270 = mux(_WIRE_4[0], _T_1269, UInt<1>(0h0)) node _T_1271 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1272 = or(_T_1270, _T_1271) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1272 node _T_1273 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1274 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = or(UInt<1>(0h0), _T_1275) node _T_1277 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1278 = cvt(_T_1277) node _T_1279 = and(_T_1278, asSInt(UInt<14>(0h2000))) node _T_1280 = asSInt(_T_1279) node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0))) node _T_1282 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1288 = cvt(_T_1287) node _T_1289 = and(_T_1288, asSInt(UInt<17>(0h10000))) node _T_1290 = asSInt(_T_1289) node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0))) node _T_1292 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1293 = cvt(_T_1292) node _T_1294 = and(_T_1293, asSInt(UInt<15>(0h4000))) node _T_1295 = asSInt(_T_1294) node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0))) node _T_1297 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<18>(0h2f000))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1308 = cvt(_T_1307) node _T_1309 = and(_T_1308, asSInt(UInt<17>(0h10000))) node _T_1310 = asSInt(_T_1309) node _T_1311 = eq(_T_1310, asSInt(UInt<1>(0h0))) node _T_1312 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1313 = cvt(_T_1312) node _T_1314 = and(_T_1313, asSInt(UInt<13>(0h1000))) node _T_1315 = asSInt(_T_1314) node _T_1316 = eq(_T_1315, asSInt(UInt<1>(0h0))) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<27>(0h4000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<29>(0h10000000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1281, _T_1286) node _T_1338 = or(_T_1337, _T_1291) node _T_1339 = or(_T_1338, _T_1296) node _T_1340 = or(_T_1339, _T_1301) node _T_1341 = or(_T_1340, _T_1306) node _T_1342 = or(_T_1341, _T_1311) node _T_1343 = or(_T_1342, _T_1316) node _T_1344 = or(_T_1343, _T_1321) node _T_1345 = or(_T_1344, _T_1326) node _T_1346 = or(_T_1345, _T_1331) node _T_1347 = or(_T_1346, _T_1336) node _T_1348 = and(_T_1276, _T_1347) node _T_1349 = or(UInt<1>(0h0), _T_1348) node _T_1350 = and(_WIRE_5, _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_86 node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(address_ok, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(legal_source, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1363 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_90 node _T_1367 = eq(io.in.b.bits.mask, mask_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_91 node _T_1371 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_92 node _T_1375 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1375 : node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = or(UInt<1>(0h0), _T_1378) node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1391 = cvt(_T_1390) node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000))) node _T_1393 = asSInt(_T_1392) node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0))) node _T_1395 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1396 = cvt(_T_1395) node _T_1397 = and(_T_1396, asSInt(UInt<15>(0h4000))) node _T_1398 = asSInt(_T_1397) node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0))) node _T_1400 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1401 = cvt(_T_1400) node _T_1402 = and(_T_1401, asSInt(UInt<13>(0h1000))) node _T_1403 = asSInt(_T_1402) node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0))) node _T_1405 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<18>(0h2f000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1416 = cvt(_T_1415) node _T_1417 = and(_T_1416, asSInt(UInt<13>(0h1000))) node _T_1418 = asSInt(_T_1417) node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0))) node _T_1420 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1421 = cvt(_T_1420) node _T_1422 = and(_T_1421, asSInt(UInt<17>(0h10000))) node _T_1423 = asSInt(_T_1422) node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1426 = cvt(_T_1425) node _T_1427 = and(_T_1426, asSInt(UInt<27>(0h4000000))) node _T_1428 = asSInt(_T_1427) node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0))) node _T_1430 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1431 = cvt(_T_1430) node _T_1432 = and(_T_1431, asSInt(UInt<13>(0h1000))) node _T_1433 = asSInt(_T_1432) node _T_1434 = eq(_T_1433, asSInt(UInt<1>(0h0))) node _T_1435 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<29>(0h10000000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1384, _T_1389) node _T_1441 = or(_T_1440, _T_1394) node _T_1442 = or(_T_1441, _T_1399) node _T_1443 = or(_T_1442, _T_1404) node _T_1444 = or(_T_1443, _T_1409) node _T_1445 = or(_T_1444, _T_1414) node _T_1446 = or(_T_1445, _T_1419) node _T_1447 = or(_T_1446, _T_1424) node _T_1448 = or(_T_1447, _T_1429) node _T_1449 = or(_T_1448, _T_1434) node _T_1450 = or(_T_1449, _T_1439) node _T_1451 = and(_T_1379, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = and(UInt<1>(0h0), _T_1452) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_93 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(address_ok, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(legal_source, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1466 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_97 node _T_1470 = eq(io.in.b.bits.mask, mask_1) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_98 node _T_1474 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_99 node _T_1478 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1478 : node _T_1479 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1480 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = or(UInt<1>(0h0), _T_1481) node _T_1483 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1484 = cvt(_T_1483) node _T_1485 = and(_T_1484, asSInt(UInt<14>(0h2000))) node _T_1486 = asSInt(_T_1485) node _T_1487 = eq(_T_1486, asSInt(UInt<1>(0h0))) node _T_1488 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1489 = cvt(_T_1488) node _T_1490 = and(_T_1489, asSInt(UInt<13>(0h1000))) node _T_1491 = asSInt(_T_1490) node _T_1492 = eq(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1494 = cvt(_T_1493) node _T_1495 = and(_T_1494, asSInt(UInt<17>(0h10000))) node _T_1496 = asSInt(_T_1495) node _T_1497 = eq(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<15>(0h4000))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1504 = cvt(_T_1503) node _T_1505 = and(_T_1504, asSInt(UInt<13>(0h1000))) node _T_1506 = asSInt(_T_1505) node _T_1507 = eq(_T_1506, asSInt(UInt<1>(0h0))) node _T_1508 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<18>(0h2f000))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1514 = cvt(_T_1513) node _T_1515 = and(_T_1514, asSInt(UInt<17>(0h10000))) node _T_1516 = asSInt(_T_1515) node _T_1517 = eq(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1519 = cvt(_T_1518) node _T_1520 = and(_T_1519, asSInt(UInt<13>(0h1000))) node _T_1521 = asSInt(_T_1520) node _T_1522 = eq(_T_1521, asSInt(UInt<1>(0h0))) node _T_1523 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1524 = cvt(_T_1523) node _T_1525 = and(_T_1524, asSInt(UInt<17>(0h10000))) node _T_1526 = asSInt(_T_1525) node _T_1527 = eq(_T_1526, asSInt(UInt<1>(0h0))) node _T_1528 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<27>(0h4000000))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1534 = cvt(_T_1533) node _T_1535 = and(_T_1534, asSInt(UInt<13>(0h1000))) node _T_1536 = asSInt(_T_1535) node _T_1537 = eq(_T_1536, asSInt(UInt<1>(0h0))) node _T_1538 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<29>(0h10000000))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1487, _T_1492) node _T_1544 = or(_T_1543, _T_1497) node _T_1545 = or(_T_1544, _T_1502) node _T_1546 = or(_T_1545, _T_1507) node _T_1547 = or(_T_1546, _T_1512) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1522) node _T_1550 = or(_T_1549, _T_1527) node _T_1551 = or(_T_1550, _T_1532) node _T_1552 = or(_T_1551, _T_1537) node _T_1553 = or(_T_1552, _T_1542) node _T_1554 = and(_T_1482, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = and(UInt<1>(0h0), _T_1555) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(address_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(legal_source, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1569 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_104 node _T_1573 = eq(io.in.b.bits.mask, mask_1) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_105 node _T_1577 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1579 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = or(UInt<1>(0h0), _T_1580) node _T_1582 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1583 = cvt(_T_1582) node _T_1584 = and(_T_1583, asSInt(UInt<14>(0h2000))) node _T_1585 = asSInt(_T_1584) node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0))) node _T_1587 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<15>(0h4000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<18>(0h2f000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<17>(0h10000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<13>(0h1000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<17>(0h10000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<27>(0h4000000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<29>(0h10000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1586, _T_1591) node _T_1643 = or(_T_1642, _T_1596) node _T_1644 = or(_T_1643, _T_1601) node _T_1645 = or(_T_1644, _T_1606) node _T_1646 = or(_T_1645, _T_1611) node _T_1647 = or(_T_1646, _T_1616) node _T_1648 = or(_T_1647, _T_1621) node _T_1649 = or(_T_1648, _T_1626) node _T_1650 = or(_T_1649, _T_1631) node _T_1651 = or(_T_1650, _T_1636) node _T_1652 = or(_T_1651, _T_1641) node _T_1653 = and(_T_1581, _T_1652) node _T_1654 = or(UInt<1>(0h0), _T_1653) node _T_1655 = and(UInt<1>(0h0), _T_1654) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_106 node _T_1659 = asUInt(reset) node _T_1660 = eq(_T_1659, UInt<1>(0h0)) when _T_1660 : node _T_1661 = eq(address_ok, UInt<1>(0h0)) when _T_1661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(legal_source, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1668 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_110 node _T_1672 = not(mask_1) node _T_1673 = and(io.in.b.bits.mask, _T_1672) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_111 node _T_1678 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1678 : node _T_1679 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1680 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = or(UInt<1>(0h0), _T_1681) node _T_1683 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1684 = cvt(_T_1683) node _T_1685 = and(_T_1684, asSInt(UInt<14>(0h2000))) node _T_1686 = asSInt(_T_1685) node _T_1687 = eq(_T_1686, asSInt(UInt<1>(0h0))) node _T_1688 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1689 = cvt(_T_1688) node _T_1690 = and(_T_1689, asSInt(UInt<13>(0h1000))) node _T_1691 = asSInt(_T_1690) node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0))) node _T_1693 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1699 = cvt(_T_1698) node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000))) node _T_1701 = asSInt(_T_1700) node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0))) node _T_1703 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1704 = cvt(_T_1703) node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000))) node _T_1706 = asSInt(_T_1705) node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0))) node _T_1708 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1709 = cvt(_T_1708) node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000))) node _T_1711 = asSInt(_T_1710) node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0))) node _T_1713 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1714 = cvt(_T_1713) node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000))) node _T_1716 = asSInt(_T_1715) node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0))) node _T_1718 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1719 = cvt(_T_1718) node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000))) node _T_1721 = asSInt(_T_1720) node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1724 = cvt(_T_1723) node _T_1725 = and(_T_1724, asSInt(UInt<17>(0h10000))) node _T_1726 = asSInt(_T_1725) node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0))) node _T_1728 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<27>(0h4000000))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1734 = cvt(_T_1733) node _T_1735 = and(_T_1734, asSInt(UInt<13>(0h1000))) node _T_1736 = asSInt(_T_1735) node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0))) node _T_1738 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<29>(0h10000000))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1687, _T_1692) node _T_1744 = or(_T_1743, _T_1697) node _T_1745 = or(_T_1744, _T_1702) node _T_1746 = or(_T_1745, _T_1707) node _T_1747 = or(_T_1746, _T_1712) node _T_1748 = or(_T_1747, _T_1717) node _T_1749 = or(_T_1748, _T_1722) node _T_1750 = or(_T_1749, _T_1727) node _T_1751 = or(_T_1750, _T_1732) node _T_1752 = or(_T_1751, _T_1737) node _T_1753 = or(_T_1752, _T_1742) node _T_1754 = and(_T_1682, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_112 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_116 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_117 node _T_1777 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<15>(0h4000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<13>(0h1000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1786, _T_1791) node _T_1843 = or(_T_1842, _T_1796) node _T_1844 = or(_T_1843, _T_1801) node _T_1845 = or(_T_1844, _T_1806) node _T_1846 = or(_T_1845, _T_1811) node _T_1847 = or(_T_1846, _T_1816) node _T_1848 = or(_T_1847, _T_1821) node _T_1849 = or(_T_1848, _T_1826) node _T_1850 = or(_T_1849, _T_1831) node _T_1851 = or(_T_1850, _T_1836) node _T_1852 = or(_T_1851, _T_1841) node _T_1853 = and(_T_1781, _T_1852) node _T_1854 = or(UInt<1>(0h0), _T_1853) node _T_1855 = and(UInt<1>(0h0), _T_1854) node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(_T_1855, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1855, UInt<1>(0h1), "") : assert_118 node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(address_ok, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(legal_source, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1868 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_122 node _T_1872 = eq(io.in.b.bits.mask, mask_1) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_123 node _T_1876 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1876 : node _T_1877 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1878 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1879 = and(_T_1877, _T_1878) node _T_1880 = or(UInt<1>(0h0), _T_1879) node _T_1881 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<14>(0h2000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<13>(0h1000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<17>(0h10000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<15>(0h4000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1907 = cvt(_T_1906) node _T_1908 = and(_T_1907, asSInt(UInt<18>(0h2f000))) node _T_1909 = asSInt(_T_1908) node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0))) node _T_1911 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1912 = cvt(_T_1911) node _T_1913 = and(_T_1912, asSInt(UInt<17>(0h10000))) node _T_1914 = asSInt(_T_1913) node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0))) node _T_1916 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1917 = cvt(_T_1916) node _T_1918 = and(_T_1917, asSInt(UInt<13>(0h1000))) node _T_1919 = asSInt(_T_1918) node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0))) node _T_1921 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1922 = cvt(_T_1921) node _T_1923 = and(_T_1922, asSInt(UInt<17>(0h10000))) node _T_1924 = asSInt(_T_1923) node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0))) node _T_1926 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1927 = cvt(_T_1926) node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000))) node _T_1929 = asSInt(_T_1928) node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0))) node _T_1931 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<13>(0h1000))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h10000000))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1885, _T_1890) node _T_1942 = or(_T_1941, _T_1895) node _T_1943 = or(_T_1942, _T_1900) node _T_1944 = or(_T_1943, _T_1905) node _T_1945 = or(_T_1944, _T_1910) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1920) node _T_1948 = or(_T_1947, _T_1925) node _T_1949 = or(_T_1948, _T_1930) node _T_1950 = or(_T_1949, _T_1935) node _T_1951 = or(_T_1950, _T_1940) node _T_1952 = and(_T_1880, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = and(UInt<1>(0h0), _T_1953) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_124 node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(address_ok, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(legal_source, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1967 = eq(io.in.b.bits.mask, mask_1) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_128 node _T_1971 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1975 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<13>(0h1000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<17>(0h10000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<18>(0h21000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<13>(0h1000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<18>(0h22000)) node _address_ok_T_131 = cvt(_address_ok_T_130) node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<13>(0h1000))) node _address_ok_T_133 = asSInt(_address_ok_T_132) node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0))) node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<18>(0h23000)) node _address_ok_T_136 = cvt(_address_ok_T_135) node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000))) node _address_ok_T_138 = asSInt(_address_ok_T_137) node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0))) node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _address_ok_T_141 = cvt(_address_ok_T_140) node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<13>(0h1000))) node _address_ok_T_143 = asSInt(_address_ok_T_142) node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0))) node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_146 = cvt(_address_ok_T_145) node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000))) node _address_ok_T_148 = asSInt(_address_ok_T_147) node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0))) node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_151 = cvt(_address_ok_T_150) node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000))) node _address_ok_T_153 = asSInt(_address_ok_T_152) node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0))) node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_156 = cvt(_address_ok_T_155) node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000))) node _address_ok_T_158 = asSInt(_address_ok_T_157) node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0))) node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_161 = cvt(_address_ok_T_160) node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000))) node _address_ok_T_163 = asSInt(_address_ok_T_162) node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0))) node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_166 = cvt(_address_ok_T_165) node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000))) node _address_ok_T_168 = asSInt(_address_ok_T_167) node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0))) node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_171 = cvt(_address_ok_T_170) node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000))) node _address_ok_T_173 = asSInt(_address_ok_T_172) node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0))) node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_176 = cvt(_address_ok_T_175) node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000))) node _address_ok_T_178 = asSInt(_address_ok_T_177) node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0))) node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_181 = cvt(_address_ok_T_180) node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000))) node _address_ok_T_183 = asSInt(_address_ok_T_182) node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[17] connect _address_ok_WIRE_1[0], _address_ok_T_104 connect _address_ok_WIRE_1[1], _address_ok_T_109 connect _address_ok_WIRE_1[2], _address_ok_T_114 connect _address_ok_WIRE_1[3], _address_ok_T_119 connect _address_ok_WIRE_1[4], _address_ok_T_124 connect _address_ok_WIRE_1[5], _address_ok_T_129 connect _address_ok_WIRE_1[6], _address_ok_T_134 connect _address_ok_WIRE_1[7], _address_ok_T_139 connect _address_ok_WIRE_1[8], _address_ok_T_144 connect _address_ok_WIRE_1[9], _address_ok_T_149 connect _address_ok_WIRE_1[10], _address_ok_T_154 connect _address_ok_WIRE_1[11], _address_ok_T_159 connect _address_ok_WIRE_1[12], _address_ok_T_164 connect _address_ok_WIRE_1[13], _address_ok_T_169 connect _address_ok_WIRE_1[14], _address_ok_T_174 connect _address_ok_WIRE_1[15], _address_ok_T_179 connect _address_ok_WIRE_1[16], _address_ok_T_184 node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2]) node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3]) node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4]) node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5]) node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6]) node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7]) node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8]) node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9]) node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10]) node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11]) node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15]) node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16]) node _T_1979 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) node _T_1981 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = or(_T_1980, _T_1985) node _T_1987 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) node _T_1989 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = or(_T_1988, _T_1993) node _T_1995 = and(_T_1986, _T_1994) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_131 node _T_1999 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1999 : node _T_2000 = asUInt(reset) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) when _T_2001 : node _T_2002 = eq(address_ok_1, UInt<1>(0h0)) when _T_2002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(source_ok_2, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2006 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_134 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2013 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_136 node _T_2017 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_137 node _T_2021 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2021 : node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(address_ok_1, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(source_ok_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2028 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_140 node _T_2032 = asUInt(reset) node _T_2033 = eq(_T_2032, UInt<1>(0h0)) when _T_2033 : node _T_2034 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2035 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2036 = asUInt(reset) node _T_2037 = eq(_T_2036, UInt<1>(0h0)) when _T_2037 : node _T_2038 = eq(_T_2035, UInt<1>(0h0)) when _T_2038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2035, UInt<1>(0h1), "") : assert_142 node _T_2039 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2039 : node _T_2040 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2041 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2044 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2045 = or(_T_2043, _T_2044) node _T_2046 = and(_T_2042, _T_2045) node _T_2047 = or(UInt<1>(0h0), _T_2046) node _T_2048 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<14>(0h2000))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2055 = cvt(_T_2054) node _T_2056 = and(_T_2055, asSInt(UInt<13>(0h1000))) node _T_2057 = asSInt(_T_2056) node _T_2058 = eq(_T_2057, asSInt(UInt<1>(0h0))) node _T_2059 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2060 = cvt(_T_2059) node _T_2061 = and(_T_2060, asSInt(UInt<17>(0h10000))) node _T_2062 = asSInt(_T_2061) node _T_2063 = eq(_T_2062, asSInt(UInt<1>(0h0))) node _T_2064 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2065 = cvt(_T_2064) node _T_2066 = and(_T_2065, asSInt(UInt<15>(0h4000))) node _T_2067 = asSInt(_T_2066) node _T_2068 = eq(_T_2067, asSInt(UInt<1>(0h0))) node _T_2069 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2070 = cvt(_T_2069) node _T_2071 = and(_T_2070, asSInt(UInt<13>(0h1000))) node _T_2072 = asSInt(_T_2071) node _T_2073 = eq(_T_2072, asSInt(UInt<1>(0h0))) node _T_2074 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2075 = cvt(_T_2074) node _T_2076 = and(_T_2075, asSInt(UInt<18>(0h2f000))) node _T_2077 = asSInt(_T_2076) node _T_2078 = eq(_T_2077, asSInt(UInt<1>(0h0))) node _T_2079 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<17>(0h10000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<27>(0h4000000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<13>(0h1000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2053, _T_2058) node _T_2100 = or(_T_2099, _T_2063) node _T_2101 = or(_T_2100, _T_2068) node _T_2102 = or(_T_2101, _T_2073) node _T_2103 = or(_T_2102, _T_2078) node _T_2104 = or(_T_2103, _T_2083) node _T_2105 = or(_T_2104, _T_2088) node _T_2106 = or(_T_2105, _T_2093) node _T_2107 = or(_T_2106, _T_2098) node _T_2108 = and(_T_2048, _T_2107) node _T_2109 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2110 = or(UInt<1>(0h0), _T_2109) node _T_2111 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<17>(0h10000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<29>(0h10000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = or(_T_2115, _T_2120) node _T_2122 = and(_T_2110, _T_2121) node _T_2123 = or(UInt<1>(0h0), _T_2108) node _T_2124 = or(_T_2123, _T_2122) node _T_2125 = and(_T_2047, _T_2124) node _T_2126 = asUInt(reset) node _T_2127 = eq(_T_2126, UInt<1>(0h0)) when _T_2127 : node _T_2128 = eq(_T_2125, UInt<1>(0h0)) when _T_2128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2125, UInt<1>(0h1), "") : assert_143 node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2130 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_2129 connect _WIRE_6[1], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_6[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = or(_T_2132, _T_2133) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2134 node _T_2135 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2136 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = or(UInt<1>(0h0), _T_2137) node _T_2139 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2140 = cvt(_T_2139) node _T_2141 = and(_T_2140, asSInt(UInt<14>(0h2000))) node _T_2142 = asSInt(_T_2141) node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0))) node _T_2144 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2145 = cvt(_T_2144) node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000))) node _T_2147 = asSInt(_T_2146) node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0))) node _T_2149 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2150 = cvt(_T_2149) node _T_2151 = and(_T_2150, asSInt(UInt<17>(0h10000))) node _T_2152 = asSInt(_T_2151) node _T_2153 = eq(_T_2152, asSInt(UInt<1>(0h0))) node _T_2154 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2155 = cvt(_T_2154) node _T_2156 = and(_T_2155, asSInt(UInt<15>(0h4000))) node _T_2157 = asSInt(_T_2156) node _T_2158 = eq(_T_2157, asSInt(UInt<1>(0h0))) node _T_2159 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2160 = cvt(_T_2159) node _T_2161 = and(_T_2160, asSInt(UInt<13>(0h1000))) node _T_2162 = asSInt(_T_2161) node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0))) node _T_2164 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2165 = cvt(_T_2164) node _T_2166 = and(_T_2165, asSInt(UInt<18>(0h2f000))) node _T_2167 = asSInt(_T_2166) node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<17>(0h10000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<27>(0h4000000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<13>(0h1000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<29>(0h10000000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = or(_T_2143, _T_2148) node _T_2200 = or(_T_2199, _T_2153) node _T_2201 = or(_T_2200, _T_2158) node _T_2202 = or(_T_2201, _T_2163) node _T_2203 = or(_T_2202, _T_2168) node _T_2204 = or(_T_2203, _T_2173) node _T_2205 = or(_T_2204, _T_2178) node _T_2206 = or(_T_2205, _T_2183) node _T_2207 = or(_T_2206, _T_2188) node _T_2208 = or(_T_2207, _T_2193) node _T_2209 = or(_T_2208, _T_2198) node _T_2210 = and(_T_2138, _T_2209) node _T_2211 = or(UInt<1>(0h0), _T_2210) node _T_2212 = and(_WIRE_7, _T_2211) node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(_T_2212, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2212, UInt<1>(0h1), "") : assert_144 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(source_ok_2, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2219 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_146 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_148 node _T_2230 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_149 node _T_2234 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2234 : node _T_2235 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2236 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2239 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2240 = or(_T_2238, _T_2239) node _T_2241 = and(_T_2237, _T_2240) node _T_2242 = or(UInt<1>(0h0), _T_2241) node _T_2243 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2244 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2245 = cvt(_T_2244) node _T_2246 = and(_T_2245, asSInt(UInt<14>(0h2000))) node _T_2247 = asSInt(_T_2246) node _T_2248 = eq(_T_2247, asSInt(UInt<1>(0h0))) node _T_2249 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2250 = cvt(_T_2249) node _T_2251 = and(_T_2250, asSInt(UInt<13>(0h1000))) node _T_2252 = asSInt(_T_2251) node _T_2253 = eq(_T_2252, asSInt(UInt<1>(0h0))) node _T_2254 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2255 = cvt(_T_2254) node _T_2256 = and(_T_2255, asSInt(UInt<17>(0h10000))) node _T_2257 = asSInt(_T_2256) node _T_2258 = eq(_T_2257, asSInt(UInt<1>(0h0))) node _T_2259 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2260 = cvt(_T_2259) node _T_2261 = and(_T_2260, asSInt(UInt<15>(0h4000))) node _T_2262 = asSInt(_T_2261) node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0))) node _T_2264 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2265 = cvt(_T_2264) node _T_2266 = and(_T_2265, asSInt(UInt<13>(0h1000))) node _T_2267 = asSInt(_T_2266) node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0))) node _T_2269 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = or(_T_2248, _T_2253) node _T_2295 = or(_T_2294, _T_2258) node _T_2296 = or(_T_2295, _T_2263) node _T_2297 = or(_T_2296, _T_2268) node _T_2298 = or(_T_2297, _T_2273) node _T_2299 = or(_T_2298, _T_2278) node _T_2300 = or(_T_2299, _T_2283) node _T_2301 = or(_T_2300, _T_2288) node _T_2302 = or(_T_2301, _T_2293) node _T_2303 = and(_T_2243, _T_2302) node _T_2304 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2305 = or(UInt<1>(0h0), _T_2304) node _T_2306 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2307 = cvt(_T_2306) node _T_2308 = and(_T_2307, asSInt(UInt<17>(0h10000))) node _T_2309 = asSInt(_T_2308) node _T_2310 = eq(_T_2309, asSInt(UInt<1>(0h0))) node _T_2311 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2312 = cvt(_T_2311) node _T_2313 = and(_T_2312, asSInt(UInt<29>(0h10000000))) node _T_2314 = asSInt(_T_2313) node _T_2315 = eq(_T_2314, asSInt(UInt<1>(0h0))) node _T_2316 = or(_T_2310, _T_2315) node _T_2317 = and(_T_2305, _T_2316) node _T_2318 = or(UInt<1>(0h0), _T_2303) node _T_2319 = or(_T_2318, _T_2317) node _T_2320 = and(_T_2242, _T_2319) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_150 node _T_2324 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2325 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2324 connect _WIRE_8[1], _T_2325 node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = mux(_WIRE_8[0], _T_2326, UInt<1>(0h0)) node _T_2328 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2329 = or(_T_2327, _T_2328) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2329 node _T_2330 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2331 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2332 = and(_T_2330, _T_2331) node _T_2333 = or(UInt<1>(0h0), _T_2332) node _T_2334 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2335 = cvt(_T_2334) node _T_2336 = and(_T_2335, asSInt(UInt<14>(0h2000))) node _T_2337 = asSInt(_T_2336) node _T_2338 = eq(_T_2337, asSInt(UInt<1>(0h0))) node _T_2339 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2340 = cvt(_T_2339) node _T_2341 = and(_T_2340, asSInt(UInt<13>(0h1000))) node _T_2342 = asSInt(_T_2341) node _T_2343 = eq(_T_2342, asSInt(UInt<1>(0h0))) node _T_2344 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2345 = cvt(_T_2344) node _T_2346 = and(_T_2345, asSInt(UInt<17>(0h10000))) node _T_2347 = asSInt(_T_2346) node _T_2348 = eq(_T_2347, asSInt(UInt<1>(0h0))) node _T_2349 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2350 = cvt(_T_2349) node _T_2351 = and(_T_2350, asSInt(UInt<15>(0h4000))) node _T_2352 = asSInt(_T_2351) node _T_2353 = eq(_T_2352, asSInt(UInt<1>(0h0))) node _T_2354 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2355 = cvt(_T_2354) node _T_2356 = and(_T_2355, asSInt(UInt<13>(0h1000))) node _T_2357 = asSInt(_T_2356) node _T_2358 = eq(_T_2357, asSInt(UInt<1>(0h0))) node _T_2359 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2360 = cvt(_T_2359) node _T_2361 = and(_T_2360, asSInt(UInt<18>(0h2f000))) node _T_2362 = asSInt(_T_2361) node _T_2363 = eq(_T_2362, asSInt(UInt<1>(0h0))) node _T_2364 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2365 = cvt(_T_2364) node _T_2366 = and(_T_2365, asSInt(UInt<17>(0h10000))) node _T_2367 = asSInt(_T_2366) node _T_2368 = eq(_T_2367, asSInt(UInt<1>(0h0))) node _T_2369 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2370 = cvt(_T_2369) node _T_2371 = and(_T_2370, asSInt(UInt<13>(0h1000))) node _T_2372 = asSInt(_T_2371) node _T_2373 = eq(_T_2372, asSInt(UInt<1>(0h0))) node _T_2374 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2375 = cvt(_T_2374) node _T_2376 = and(_T_2375, asSInt(UInt<17>(0h10000))) node _T_2377 = asSInt(_T_2376) node _T_2378 = eq(_T_2377, asSInt(UInt<1>(0h0))) node _T_2379 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2380 = cvt(_T_2379) node _T_2381 = and(_T_2380, asSInt(UInt<27>(0h4000000))) node _T_2382 = asSInt(_T_2381) node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0))) node _T_2384 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2385 = cvt(_T_2384) node _T_2386 = and(_T_2385, asSInt(UInt<13>(0h1000))) node _T_2387 = asSInt(_T_2386) node _T_2388 = eq(_T_2387, asSInt(UInt<1>(0h0))) node _T_2389 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2390 = cvt(_T_2389) node _T_2391 = and(_T_2390, asSInt(UInt<29>(0h10000000))) node _T_2392 = asSInt(_T_2391) node _T_2393 = eq(_T_2392, asSInt(UInt<1>(0h0))) node _T_2394 = or(_T_2338, _T_2343) node _T_2395 = or(_T_2394, _T_2348) node _T_2396 = or(_T_2395, _T_2353) node _T_2397 = or(_T_2396, _T_2358) node _T_2398 = or(_T_2397, _T_2363) node _T_2399 = or(_T_2398, _T_2368) node _T_2400 = or(_T_2399, _T_2373) node _T_2401 = or(_T_2400, _T_2378) node _T_2402 = or(_T_2401, _T_2383) node _T_2403 = or(_T_2402, _T_2388) node _T_2404 = or(_T_2403, _T_2393) node _T_2405 = and(_T_2333, _T_2404) node _T_2406 = or(UInt<1>(0h0), _T_2405) node _T_2407 = and(_WIRE_9, _T_2406) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_151 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_2, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2414 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_153 node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2421 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_155 node _T_2425 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2425 : node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(address_ok_1, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(source_ok_2, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2435 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_159 node _T_2439 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_160 node _T_2443 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2443 : node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(address_ok_1, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(source_ok_2, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2453 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_164 node _T_2457 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2457 : node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(address_ok_1, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(source_ok_2, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2467 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_168 node _T_2471 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2472 = asUInt(reset) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) when _T_2473 : node _T_2474 = eq(_T_2471, UInt<1>(0h0)) when _T_2474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2471, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2478 = eq(a_first, UInt<1>(0h0)) node _T_2479 = and(io.in.a.valid, _T_2478) when _T_2479 : node _T_2480 = eq(io.in.a.bits.opcode, opcode) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_171 node _T_2484 = eq(io.in.a.bits.param, param) node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(_T_2484, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2484, UInt<1>(0h1), "") : assert_172 node _T_2488 = eq(io.in.a.bits.size, size) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_173 node _T_2492 = eq(io.in.a.bits.source, source) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_174 node _T_2496 = eq(io.in.a.bits.address, address) node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(_T_2496, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2496, UInt<1>(0h1), "") : assert_175 node _T_2500 = and(io.in.a.ready, io.in.a.valid) node _T_2501 = and(_T_2500, a_first) when _T_2501 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2502 = eq(d_first, UInt<1>(0h0)) node _T_2503 = and(io.in.d.valid, _T_2502) when _T_2503 : node _T_2504 = eq(io.in.d.bits.opcode, opcode_1) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_176 node _T_2508 = eq(io.in.d.bits.param, param_1) node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(_T_2508, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2508, UInt<1>(0h1), "") : assert_177 node _T_2512 = eq(io.in.d.bits.size, size_1) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_178 node _T_2516 = eq(io.in.d.bits.source, source_1) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_179 node _T_2520 = eq(io.in.d.bits.sink, sink) node _T_2521 = asUInt(reset) node _T_2522 = eq(_T_2521, UInt<1>(0h0)) when _T_2522 : node _T_2523 = eq(_T_2520, UInt<1>(0h0)) when _T_2523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2520, UInt<1>(0h1), "") : assert_180 node _T_2524 = eq(io.in.d.bits.denied, denied) node _T_2525 = asUInt(reset) node _T_2526 = eq(_T_2525, UInt<1>(0h0)) when _T_2526 : node _T_2527 = eq(_T_2524, UInt<1>(0h0)) when _T_2527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2524, UInt<1>(0h1), "") : assert_181 node _T_2528 = and(io.in.d.ready, io.in.d.valid) node _T_2529 = and(_T_2528, d_first) when _T_2529 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2530 = eq(b_first, UInt<1>(0h0)) node _T_2531 = and(io.in.b.valid, _T_2530) when _T_2531 : node _T_2532 = eq(io.in.b.bits.opcode, opcode_2) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_182 node _T_2536 = eq(io.in.b.bits.param, param_2) node _T_2537 = asUInt(reset) node _T_2538 = eq(_T_2537, UInt<1>(0h0)) when _T_2538 : node _T_2539 = eq(_T_2536, UInt<1>(0h0)) when _T_2539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2536, UInt<1>(0h1), "") : assert_183 node _T_2540 = eq(io.in.b.bits.size, size_2) node _T_2541 = asUInt(reset) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) when _T_2542 : node _T_2543 = eq(_T_2540, UInt<1>(0h0)) when _T_2543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2540, UInt<1>(0h1), "") : assert_184 node _T_2544 = eq(io.in.b.bits.source, source_2) node _T_2545 = asUInt(reset) node _T_2546 = eq(_T_2545, UInt<1>(0h0)) when _T_2546 : node _T_2547 = eq(_T_2544, UInt<1>(0h0)) when _T_2547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2544, UInt<1>(0h1), "") : assert_185 node _T_2548 = eq(io.in.b.bits.address, address_1) node _T_2549 = asUInt(reset) node _T_2550 = eq(_T_2549, UInt<1>(0h0)) when _T_2550 : node _T_2551 = eq(_T_2548, UInt<1>(0h0)) when _T_2551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2548, UInt<1>(0h1), "") : assert_186 node _T_2552 = and(io.in.b.ready, io.in.b.valid) node _T_2553 = and(_T_2552, b_first) when _T_2553 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2554 = eq(c_first, UInt<1>(0h0)) node _T_2555 = and(io.in.c.valid, _T_2554) when _T_2555 : node _T_2556 = eq(io.in.c.bits.opcode, opcode_3) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_187 node _T_2560 = eq(io.in.c.bits.param, param_3) node _T_2561 = asUInt(reset) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) when _T_2562 : node _T_2563 = eq(_T_2560, UInt<1>(0h0)) when _T_2563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2560, UInt<1>(0h1), "") : assert_188 node _T_2564 = eq(io.in.c.bits.size, size_3) node _T_2565 = asUInt(reset) node _T_2566 = eq(_T_2565, UInt<1>(0h0)) when _T_2566 : node _T_2567 = eq(_T_2564, UInt<1>(0h0)) when _T_2567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2564, UInt<1>(0h1), "") : assert_189 node _T_2568 = eq(io.in.c.bits.source, source_3) node _T_2569 = asUInt(reset) node _T_2570 = eq(_T_2569, UInt<1>(0h0)) when _T_2570 : node _T_2571 = eq(_T_2568, UInt<1>(0h0)) when _T_2571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2568, UInt<1>(0h1), "") : assert_190 node _T_2572 = eq(io.in.c.bits.address, address_2) node _T_2573 = asUInt(reset) node _T_2574 = eq(_T_2573, UInt<1>(0h0)) when _T_2574 : node _T_2575 = eq(_T_2572, UInt<1>(0h0)) when _T_2575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2572, UInt<1>(0h1), "") : assert_191 node _T_2576 = and(io.in.c.ready, io.in.c.valid) node _T_2577 = and(_T_2576, c_first) when _T_2577 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2578 = and(io.in.a.valid, a_first_1) node _T_2579 = and(_T_2578, UInt<1>(0h1)) when _T_2579 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2580 = and(io.in.a.ready, io.in.a.valid) node _T_2581 = and(_T_2580, a_first_1) node _T_2582 = and(_T_2581, UInt<1>(0h1)) when _T_2582 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2583 = dshr(inflight, io.in.a.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_1) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = eq(d_release_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2593 = and(io.in.d.ready, io.in.d.valid) node _T_2594 = and(_T_2593, d_first_1) node _T_2595 = and(_T_2594, UInt<1>(0h1)) node _T_2596 = eq(d_release_ack, UInt<1>(0h0)) node _T_2597 = and(_T_2595, _T_2596) when _T_2597 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2598 = and(io.in.d.valid, d_first_1) node _T_2599 = and(_T_2598, UInt<1>(0h1)) node _T_2600 = eq(d_release_ack, UInt<1>(0h0)) node _T_2601 = and(_T_2599, _T_2600) when _T_2601 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2602 = dshr(inflight, io.in.d.bits.source) node _T_2603 = bits(_T_2602, 0, 0) node _T_2604 = or(_T_2603, same_cycle_resp) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2608 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2609 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2610 = or(_T_2608, _T_2609) node _T_2611 = asUInt(reset) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) when _T_2612 : node _T_2613 = eq(_T_2610, UInt<1>(0h0)) when _T_2613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2610, UInt<1>(0h1), "") : assert_194 node _T_2614 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2615 = asUInt(reset) node _T_2616 = eq(_T_2615, UInt<1>(0h0)) when _T_2616 : node _T_2617 = eq(_T_2614, UInt<1>(0h0)) when _T_2617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2614, UInt<1>(0h1), "") : assert_195 else : node _T_2618 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2619 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2620 = or(_T_2618, _T_2619) node _T_2621 = asUInt(reset) node _T_2622 = eq(_T_2621, UInt<1>(0h0)) when _T_2622 : node _T_2623 = eq(_T_2620, UInt<1>(0h0)) when _T_2623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2620, UInt<1>(0h1), "") : assert_196 node _T_2624 = eq(io.in.d.bits.size, a_size_lookup) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_197 node _T_2628 = and(io.in.d.valid, d_first_1) node _T_2629 = and(_T_2628, a_first_1) node _T_2630 = and(_T_2629, io.in.a.valid) node _T_2631 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2632 = and(_T_2630, _T_2631) node _T_2633 = eq(d_release_ack, UInt<1>(0h0)) node _T_2634 = and(_T_2632, _T_2633) when _T_2634 : node _T_2635 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2636 = or(_T_2635, io.in.a.ready) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_198 node _T_2640 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2641 = orr(a_set_wo_ready) node _T_2642 = eq(_T_2641, UInt<1>(0h0)) node _T_2643 = or(_T_2640, _T_2642) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_14 node _T_2647 = orr(inflight) node _T_2648 = eq(_T_2647, UInt<1>(0h0)) node _T_2649 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2650 = or(_T_2648, _T_2649) node _T_2651 = lt(watchdog, plusarg_reader.out) node _T_2652 = or(_T_2650, _T_2651) node _T_2653 = asUInt(reset) node _T_2654 = eq(_T_2653, UInt<1>(0h0)) when _T_2654 : node _T_2655 = eq(_T_2652, UInt<1>(0h0)) when _T_2655 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2652, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2656 = and(io.in.a.ready, io.in.a.valid) node _T_2657 = and(io.in.d.ready, io.in.d.valid) node _T_2658 = or(_T_2656, _T_2657) when _T_2658 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2659 = and(io.in.c.valid, c_first_1) node _T_2660 = bits(io.in.c.bits.opcode, 2, 2) node _T_2661 = bits(io.in.c.bits.opcode, 1, 1) node _T_2662 = and(_T_2660, _T_2661) node _T_2663 = and(_T_2659, _T_2662) when _T_2663 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2664 = and(io.in.c.ready, io.in.c.valid) node _T_2665 = and(_T_2664, c_first_1) node _T_2666 = bits(io.in.c.bits.opcode, 2, 2) node _T_2667 = bits(io.in.c.bits.opcode, 1, 1) node _T_2668 = and(_T_2666, _T_2667) node _T_2669 = and(_T_2665, _T_2668) when _T_2669 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2670 = dshr(inflight_1, io.in.c.bits.source) node _T_2671 = bits(_T_2670, 0, 0) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) node _T_2673 = asUInt(reset) node _T_2674 = eq(_T_2673, UInt<1>(0h0)) when _T_2674 : node _T_2675 = eq(_T_2672, UInt<1>(0h0)) when _T_2675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2672, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2676 = and(io.in.d.valid, d_first_2) node _T_2677 = and(_T_2676, UInt<1>(0h1)) node _T_2678 = and(_T_2677, d_release_ack_1) when _T_2678 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2679 = and(io.in.d.ready, io.in.d.valid) node _T_2680 = and(_T_2679, d_first_2) node _T_2681 = and(_T_2680, UInt<1>(0h1)) node _T_2682 = and(_T_2681, d_release_ack_1) when _T_2682 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2683 = and(io.in.d.valid, d_first_2) node _T_2684 = and(_T_2683, UInt<1>(0h1)) node _T_2685 = and(_T_2684, d_release_ack_1) when _T_2685 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2686 = dshr(inflight_1, io.in.d.bits.source) node _T_2687 = bits(_T_2686, 0, 0) node _T_2688 = or(_T_2687, same_cycle_resp_1) node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(_T_2688, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2688, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2692 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2693 = asUInt(reset) node _T_2694 = eq(_T_2693, UInt<1>(0h0)) when _T_2694 : node _T_2695 = eq(_T_2692, UInt<1>(0h0)) when _T_2695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2692, UInt<1>(0h1), "") : assert_203 else : node _T_2696 = eq(io.in.d.bits.size, c_size_lookup) node _T_2697 = asUInt(reset) node _T_2698 = eq(_T_2697, UInt<1>(0h0)) when _T_2698 : node _T_2699 = eq(_T_2696, UInt<1>(0h0)) when _T_2699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2696, UInt<1>(0h1), "") : assert_204 node _T_2700 = and(io.in.d.valid, d_first_2) node _T_2701 = and(_T_2700, c_first_1) node _T_2702 = and(_T_2701, io.in.c.valid) node _T_2703 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2704 = and(_T_2702, _T_2703) node _T_2705 = and(_T_2704, d_release_ack_1) node _T_2706 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2707 = and(_T_2705, _T_2706) when _T_2707 : node _T_2708 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2709 = or(_T_2708, io.in.c.ready) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_205 node _T_2713 = orr(c_set_wo_ready) when _T_2713 : node _T_2714 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2715 = asUInt(reset) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) when _T_2716 : node _T_2717 = eq(_T_2714, UInt<1>(0h0)) when _T_2717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2714, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_15 node _T_2718 = orr(inflight_1) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) node _T_2720 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2721 = or(_T_2719, _T_2720) node _T_2722 = lt(watchdog_1, plusarg_reader_1.out) node _T_2723 = or(_T_2721, _T_2722) node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(_T_2723, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2723, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2727 = and(io.in.c.ready, io.in.c.valid) node _T_2728 = and(io.in.d.ready, io.in.d.valid) node _T_2729 = or(_T_2727, _T_2728) when _T_2729 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2730 = and(io.in.d.ready, io.in.d.valid) node _T_2731 = and(_T_2730, d_first_3) node _T_2732 = bits(io.in.d.bits.opcode, 2, 2) node _T_2733 = bits(io.in.d.bits.opcode, 1, 1) node _T_2734 = eq(_T_2733, UInt<1>(0h0)) node _T_2735 = and(_T_2732, _T_2734) node _T_2736 = and(_T_2731, _T_2735) when _T_2736 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2737 = dshr(inflight_2, io.in.d.bits.sink) node _T_2738 = bits(_T_2737, 0, 0) node _T_2739 = eq(_T_2738, UInt<1>(0h0)) node _T_2740 = asUInt(reset) node _T_2741 = eq(_T_2740, UInt<1>(0h0)) when _T_2741 : node _T_2742 = eq(_T_2739, UInt<1>(0h0)) when _T_2742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2739, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2743 = and(io.in.e.ready, io.in.e.valid) node _T_2744 = and(_T_2743, UInt<1>(0h1)) node _T_2745 = and(_T_2744, UInt<1>(0h1)) when _T_2745 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2746 = or(d_set, inflight_2) node _T_2747 = dshr(_T_2746, io.in.e.bits.sink) node _T_2748 = bits(_T_2747, 0, 0) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_7( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 | _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 | _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 | _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 | _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_10 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_10; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_11 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_11; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_12 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_13 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_15 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_16 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_18 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_20 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_21 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_21}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 | _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 | _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 | _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 | _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_22 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_22; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_23 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_23; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_23; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_24 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_24; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_24; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_25 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_26 = 2'h1 << _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_26; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_27 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_27; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_27; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_28 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_29 = 2'h1 << _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_29; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_30 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_31 = 2'h1 << _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_31; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_31; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_33 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_33; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_55 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} inst input_buffer of InputBuffer_55 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) inst route_arbiter of Arbiter2_RouteComputerReq_9 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2] wire vcalloc_vals : UInt<1>[2] node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0)) node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11) node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1]) when _T_19 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = bits(vcalloc_sel, 0, 0) node _mask_T_6 = bits(vcalloc_sel, 1, 1) node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_7, _mask_T_8) wire _mask_WIRE : UInt<2> connect _mask_WIRE, _mask_T_9 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2] node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10 connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2] node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_14 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_14.egress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_14.egress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_34 connect _io_vcalloc_req_bits_WIRE_14.ingress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_14.ingress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_14.vnet_id, _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_14 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_20 = bits(vcalloc_sel, 1, 1) node _T_21 = and(vcalloc_vals[1], _T_20) node _T_22 = and(_T_21, io.vcalloc_req.ready) when _T_22 : connect states[1].g, UInt<3>(0h3) node _T_23 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_23 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready) node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1) connect io.debug.va_stall, _io_debug_va_stall_T_3 node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_24 : node _T_25 = bits(vcalloc_sel, 0, 0) when _T_25 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_26 = bits(vcalloc_sel, 1, 1) when _T_26 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_136 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] node _credit_available_T = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node _credit_available_T_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node _credit_available_T_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi = cat(states[1].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi, credit_available_lo) node _credit_available_T_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _credit_available_T_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node _credit_available_T_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_1 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_27 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_28 = and(_T_27, input_buffer.io.deq[1].bits.tail) when _T_28 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_5 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5 node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_7 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1) connect salloc_outs[0].vid, _salloc_outs_0_vid_T node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _vc_sel_WIRE : UInt<1>[2] node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_4 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_7 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_3 : UInt<1>[2] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_10 connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4 node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_13 connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5 connect vc_sel.`1`, _vc_sel_WIRE_3 wire _vc_sel_WIRE_6 : UInt<1>[2] node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_16 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_19 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 connect vc_sel.`2`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_22 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`3`, _vc_sel_WIRE_9 node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1) node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0)) node _virt_channel_T_7 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0)) node _virt_channel_T_8 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = or(_virt_channel_T_6, _virt_channel_T_7) node _virt_channel_T_11 = or(_virt_channel_T_10, _virt_channel_T_8) node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_9) wire virt_channel : UInt<1> connect virt_channel, _virt_channel_T_12 node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_29 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3) wire _salloc_outs_0_flit_payload_WIRE : UInt<37> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`3`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) node _T_30 = asUInt(reset) when _T_30 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0)

module InputUnit_55( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output io_debug_va_stall, // @[InputUnit.scala:170:14] output io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [1:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire _GEN_1 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<14>(0h2000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<18>(0h2f000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<17>(0h10000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<27>(0h4000000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = or(_T_386, _T_391) node _T_423 = or(_T_422, _T_396) node _T_424 = or(_T_423, _T_401) node _T_425 = or(_T_424, _T_406) node _T_426 = or(_T_425, _T_411) node _T_427 = or(_T_426, _T_416) node _T_428 = or(_T_427, _T_421) node _T_429 = and(_T_381, _T_428) node _T_430 = or(UInt<1>(0h0), _T_429) node _T_431 = and(_T_380, _T_430) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_431, UInt<1>(0h1), "") : assert_2 node _T_435 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<1>(0h0)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_8) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_442 = shr(io.in.a.bits.source, 2) node _T_443 = eq(_T_442, UInt<1>(0h1)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_9) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_448 = shr(io.in.a.bits.source, 2) node _T_449 = eq(_T_448, UInt<2>(0h2)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_10) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_453 = and(_T_451, _T_452) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_454 = shr(io.in.a.bits.source, 2) node _T_455 = eq(_T_454, UInt<2>(0h3)) node _T_456 = leq(UInt<1>(0h0), uncommonBits_11) node _T_457 = and(_T_455, _T_456) node _T_458 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_484 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_435 connect _WIRE[1], _T_441 connect _WIRE[2], _T_447 connect _WIRE[3], _T_453 connect _WIRE[4], _T_459 connect _WIRE[5], _T_460 connect _WIRE[6], _T_461 connect _WIRE[7], _T_462 connect _WIRE[8], _T_463 connect _WIRE[9], _T_464 connect _WIRE[10], _T_465 connect _WIRE[11], _T_466 connect _WIRE[12], _T_467 connect _WIRE[13], _T_468 connect _WIRE[14], _T_469 connect _WIRE[15], _T_470 connect _WIRE[16], _T_471 connect _WIRE[17], _T_472 connect _WIRE[18], _T_473 connect _WIRE[19], _T_474 connect _WIRE[20], _T_475 connect _WIRE[21], _T_476 connect _WIRE[22], _T_477 connect _WIRE[23], _T_478 connect _WIRE[24], _T_479 connect _WIRE[25], _T_480 connect _WIRE[26], _T_481 connect _WIRE[27], _T_482 connect _WIRE[28], _T_483 connect _WIRE[29], _T_484 node _T_485 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_486 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_487 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_488 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_489 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_490 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_491 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_492 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_493 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_494 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_495 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_496 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_497 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_498 = mux(_WIRE[5], _T_485, UInt<1>(0h0)) node _T_499 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_500 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_501 = mux(_WIRE[8], _T_486, UInt<1>(0h0)) node _T_502 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_503 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_504 = mux(_WIRE[11], _T_487, UInt<1>(0h0)) node _T_505 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_506 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_507 = mux(_WIRE[14], _T_488, UInt<1>(0h0)) node _T_508 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_509 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_510 = mux(_WIRE[17], _T_489, UInt<1>(0h0)) node _T_511 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_512 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = mux(_WIRE[20], _T_490, UInt<1>(0h0)) node _T_514 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_515 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_516 = mux(_WIRE[23], _T_491, UInt<1>(0h0)) node _T_517 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_518 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE[26], _T_492, UInt<1>(0h0)) node _T_520 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_522 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = or(_T_493, _T_494) node _T_524 = or(_T_523, _T_495) node _T_525 = or(_T_524, _T_496) node _T_526 = or(_T_525, _T_497) node _T_527 = or(_T_526, _T_498) node _T_528 = or(_T_527, _T_499) node _T_529 = or(_T_528, _T_500) node _T_530 = or(_T_529, _T_501) node _T_531 = or(_T_530, _T_502) node _T_532 = or(_T_531, _T_503) node _T_533 = or(_T_532, _T_504) node _T_534 = or(_T_533, _T_505) node _T_535 = or(_T_534, _T_506) node _T_536 = or(_T_535, _T_507) node _T_537 = or(_T_536, _T_508) node _T_538 = or(_T_537, _T_509) node _T_539 = or(_T_538, _T_510) node _T_540 = or(_T_539, _T_511) node _T_541 = or(_T_540, _T_512) node _T_542 = or(_T_541, _T_513) node _T_543 = or(_T_542, _T_514) node _T_544 = or(_T_543, _T_515) node _T_545 = or(_T_544, _T_516) node _T_546 = or(_T_545, _T_517) node _T_547 = or(_T_546, _T_518) node _T_548 = or(_T_547, _T_519) node _T_549 = or(_T_548, _T_520) node _T_550 = or(_T_549, _T_521) node _T_551 = or(_T_550, _T_522) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_551 node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_553 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_554 = and(_T_552, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<14>(0h2000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<17>(0h10000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<18>(0h2f000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<17>(0h10000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<13>(0h1000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<27>(0h4000000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<13>(0h1000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = or(_T_560, _T_565) node _T_597 = or(_T_596, _T_570) node _T_598 = or(_T_597, _T_575) node _T_599 = or(_T_598, _T_580) node _T_600 = or(_T_599, _T_585) node _T_601 = or(_T_600, _T_590) node _T_602 = or(_T_601, _T_595) node _T_603 = and(_T_555, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = and(_WIRE_1, _T_604) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_605, UInt<1>(0h1), "") : assert_3 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(source_ok, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_612 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_612, UInt<1>(0h1), "") : assert_5 node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(is_aligned, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_619 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_619, UInt<1>(0h1), "") : assert_7 node _T_623 = not(io.in.a.bits.mask) node _T_624 = eq(_T_623, UInt<1>(0h0)) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_624, UInt<1>(0h1), "") : assert_8 node _T_628 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_628, UInt<1>(0h1), "") : assert_9 node _T_632 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_632 : node _T_633 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_634 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_635 = and(_T_633, _T_634) node _T_636 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<1>(0h0)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_12) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<1>(0h1)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_13) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_649 = shr(io.in.a.bits.source, 2) node _T_650 = eq(_T_649, UInt<2>(0h2)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_14) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_654 = and(_T_652, _T_653) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_655 = shr(io.in.a.bits.source, 2) node _T_656 = eq(_T_655, UInt<2>(0h3)) node _T_657 = leq(UInt<1>(0h0), uncommonBits_15) node _T_658 = and(_T_656, _T_657) node _T_659 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_662 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_663 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_664 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_667 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_668 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_669 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_685 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_686 = or(_T_636, _T_642) node _T_687 = or(_T_686, _T_648) node _T_688 = or(_T_687, _T_654) node _T_689 = or(_T_688, _T_660) node _T_690 = or(_T_689, _T_661) node _T_691 = or(_T_690, _T_662) node _T_692 = or(_T_691, _T_663) node _T_693 = or(_T_692, _T_664) node _T_694 = or(_T_693, _T_665) node _T_695 = or(_T_694, _T_666) node _T_696 = or(_T_695, _T_667) node _T_697 = or(_T_696, _T_668) node _T_698 = or(_T_697, _T_669) node _T_699 = or(_T_698, _T_670) node _T_700 = or(_T_699, _T_671) node _T_701 = or(_T_700, _T_672) node _T_702 = or(_T_701, _T_673) node _T_703 = or(_T_702, _T_674) node _T_704 = or(_T_703, _T_675) node _T_705 = or(_T_704, _T_676) node _T_706 = or(_T_705, _T_677) node _T_707 = or(_T_706, _T_678) node _T_708 = or(_T_707, _T_679) node _T_709 = or(_T_708, _T_680) node _T_710 = or(_T_709, _T_681) node _T_711 = or(_T_710, _T_682) node _T_712 = or(_T_711, _T_683) node _T_713 = or(_T_712, _T_684) node _T_714 = or(_T_713, _T_685) node _T_715 = and(_T_635, _T_714) node _T_716 = or(UInt<1>(0h0), _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<14>(0h2000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<13>(0h1000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<27>(0h4000000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = or(_T_722, _T_727) node _T_759 = or(_T_758, _T_732) node _T_760 = or(_T_759, _T_737) node _T_761 = or(_T_760, _T_742) node _T_762 = or(_T_761, _T_747) node _T_763 = or(_T_762, _T_752) node _T_764 = or(_T_763, _T_757) node _T_765 = and(_T_717, _T_764) node _T_766 = or(UInt<1>(0h0), _T_765) node _T_767 = and(_T_716, _T_766) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_767, UInt<1>(0h1), "") : assert_10 node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_16) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_17) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_18) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_19) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_817 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_818 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_819 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_771 connect _WIRE_2[1], _T_777 connect _WIRE_2[2], _T_783 connect _WIRE_2[3], _T_789 connect _WIRE_2[4], _T_795 connect _WIRE_2[5], _T_796 connect _WIRE_2[6], _T_797 connect _WIRE_2[7], _T_798 connect _WIRE_2[8], _T_799 connect _WIRE_2[9], _T_800 connect _WIRE_2[10], _T_801 connect _WIRE_2[11], _T_802 connect _WIRE_2[12], _T_803 connect _WIRE_2[13], _T_804 connect _WIRE_2[14], _T_805 connect _WIRE_2[15], _T_806 connect _WIRE_2[16], _T_807 connect _WIRE_2[17], _T_808 connect _WIRE_2[18], _T_809 connect _WIRE_2[19], _T_810 connect _WIRE_2[20], _T_811 connect _WIRE_2[21], _T_812 connect _WIRE_2[22], _T_813 connect _WIRE_2[23], _T_814 connect _WIRE_2[24], _T_815 connect _WIRE_2[25], _T_816 connect _WIRE_2[26], _T_817 connect _WIRE_2[27], _T_818 connect _WIRE_2[28], _T_819 connect _WIRE_2[29], _T_820 node _T_821 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_822 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_823 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_824 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_825 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_826 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_827 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_828 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_829 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_831 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_832 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_833 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_834 = mux(_WIRE_2[5], _T_821, UInt<1>(0h0)) node _T_835 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_836 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_837 = mux(_WIRE_2[8], _T_822, UInt<1>(0h0)) node _T_838 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_839 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_840 = mux(_WIRE_2[11], _T_823, UInt<1>(0h0)) node _T_841 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_842 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_843 = mux(_WIRE_2[14], _T_824, UInt<1>(0h0)) node _T_844 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_845 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_846 = mux(_WIRE_2[17], _T_825, UInt<1>(0h0)) node _T_847 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_848 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_849 = mux(_WIRE_2[20], _T_826, UInt<1>(0h0)) node _T_850 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_851 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_852 = mux(_WIRE_2[23], _T_827, UInt<1>(0h0)) node _T_853 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_855 = mux(_WIRE_2[26], _T_828, UInt<1>(0h0)) node _T_856 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_857 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_858 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_859 = or(_T_829, _T_830) node _T_860 = or(_T_859, _T_831) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = or(_T_886, _T_858) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_887 node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<14>(0h2000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<13>(0h1000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<18>(0h2f000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<27>(0h4000000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = or(_T_896, _T_901) node _T_933 = or(_T_932, _T_906) node _T_934 = or(_T_933, _T_911) node _T_935 = or(_T_934, _T_916) node _T_936 = or(_T_935, _T_921) node _T_937 = or(_T_936, _T_926) node _T_938 = or(_T_937, _T_931) node _T_939 = and(_T_891, _T_938) node _T_940 = or(UInt<1>(0h0), _T_939) node _T_941 = and(_WIRE_3, _T_940) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_941, UInt<1>(0h1), "") : assert_11 node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(source_ok, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_948 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_948, UInt<1>(0h1), "") : assert_13 node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(is_aligned, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_955 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_955, UInt<1>(0h1), "") : assert_15 node _T_959 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_959, UInt<1>(0h1), "") : assert_16 node _T_963 = not(io.in.a.bits.mask) node _T_964 = eq(_T_963, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_964, UInt<1>(0h1), "") : assert_17 node _T_968 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_968, UInt<1>(0h1), "") : assert_18 node _T_972 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_972 : node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_974 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_975 = and(_T_973, _T_974) node _T_976 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_977 = shr(io.in.a.bits.source, 2) node _T_978 = eq(_T_977, UInt<1>(0h0)) node _T_979 = leq(UInt<1>(0h0), uncommonBits_20) node _T_980 = and(_T_978, _T_979) node _T_981 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_983 = shr(io.in.a.bits.source, 2) node _T_984 = eq(_T_983, UInt<1>(0h1)) node _T_985 = leq(UInt<1>(0h0), uncommonBits_21) node _T_986 = and(_T_984, _T_985) node _T_987 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_988 = and(_T_986, _T_987) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_989 = shr(io.in.a.bits.source, 2) node _T_990 = eq(_T_989, UInt<2>(0h2)) node _T_991 = leq(UInt<1>(0h0), uncommonBits_22) node _T_992 = and(_T_990, _T_991) node _T_993 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_994 = and(_T_992, _T_993) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_995 = shr(io.in.a.bits.source, 2) node _T_996 = eq(_T_995, UInt<2>(0h3)) node _T_997 = leq(UInt<1>(0h0), uncommonBits_23) node _T_998 = and(_T_996, _T_997) node _T_999 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1025 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1026 = or(_T_976, _T_982) node _T_1027 = or(_T_1026, _T_988) node _T_1028 = or(_T_1027, _T_994) node _T_1029 = or(_T_1028, _T_1000) node _T_1030 = or(_T_1029, _T_1001) node _T_1031 = or(_T_1030, _T_1002) node _T_1032 = or(_T_1031, _T_1003) node _T_1033 = or(_T_1032, _T_1004) node _T_1034 = or(_T_1033, _T_1005) node _T_1035 = or(_T_1034, _T_1006) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = or(_T_1036, _T_1008) node _T_1038 = or(_T_1037, _T_1009) node _T_1039 = or(_T_1038, _T_1010) node _T_1040 = or(_T_1039, _T_1011) node _T_1041 = or(_T_1040, _T_1012) node _T_1042 = or(_T_1041, _T_1013) node _T_1043 = or(_T_1042, _T_1014) node _T_1044 = or(_T_1043, _T_1015) node _T_1045 = or(_T_1044, _T_1016) node _T_1046 = or(_T_1045, _T_1017) node _T_1047 = or(_T_1046, _T_1018) node _T_1048 = or(_T_1047, _T_1019) node _T_1049 = or(_T_1048, _T_1020) node _T_1050 = or(_T_1049, _T_1021) node _T_1051 = or(_T_1050, _T_1022) node _T_1052 = or(_T_1051, _T_1023) node _T_1053 = or(_T_1052, _T_1024) node _T_1054 = or(_T_1053, _T_1025) node _T_1055 = and(_T_975, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_19 node _T_1060 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1061 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1065 = cvt(_T_1064) node _T_1066 = and(_T_1065, asSInt(UInt<13>(0h1000))) node _T_1067 = asSInt(_T_1066) node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0))) node _T_1069 = and(_T_1063, _T_1068) node _T_1070 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1071 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = or(UInt<1>(0h0), _T_1072) node _T_1074 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1075 = cvt(_T_1074) node _T_1076 = and(_T_1075, asSInt(UInt<14>(0h2000))) node _T_1077 = asSInt(_T_1076) node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0))) node _T_1079 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1080 = cvt(_T_1079) node _T_1081 = and(_T_1080, asSInt(UInt<17>(0h10000))) node _T_1082 = asSInt(_T_1081) node _T_1083 = eq(_T_1082, asSInt(UInt<1>(0h0))) node _T_1084 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1085 = cvt(_T_1084) node _T_1086 = and(_T_1085, asSInt(UInt<18>(0h2f000))) node _T_1087 = asSInt(_T_1086) node _T_1088 = eq(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1090 = cvt(_T_1089) node _T_1091 = and(_T_1090, asSInt(UInt<17>(0h10000))) node _T_1092 = asSInt(_T_1091) node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0))) node _T_1094 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1095 = cvt(_T_1094) node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000))) node _T_1097 = asSInt(_T_1096) node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0))) node _T_1099 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<27>(0h4000000))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1105 = cvt(_T_1104) node _T_1106 = and(_T_1105, asSInt(UInt<13>(0h1000))) node _T_1107 = asSInt(_T_1106) node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0))) node _T_1109 = or(_T_1078, _T_1083) node _T_1110 = or(_T_1109, _T_1088) node _T_1111 = or(_T_1110, _T_1093) node _T_1112 = or(_T_1111, _T_1098) node _T_1113 = or(_T_1112, _T_1103) node _T_1114 = or(_T_1113, _T_1108) node _T_1115 = and(_T_1073, _T_1114) node _T_1116 = or(UInt<1>(0h0), _T_1069) node _T_1117 = or(_T_1116, _T_1115) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_20 node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(source_ok, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(is_aligned, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1127 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_23 node _T_1131 = eq(io.in.a.bits.mask, mask) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_24 node _T_1135 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_25 node _T_1139 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1139 : node _T_1140 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1141 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1144 = shr(io.in.a.bits.source, 2) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) node _T_1146 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1149 = and(_T_1147, _T_1148) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1150 = shr(io.in.a.bits.source, 2) node _T_1151 = eq(_T_1150, UInt<1>(0h1)) node _T_1152 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1155 = and(_T_1153, _T_1154) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1156 = shr(io.in.a.bits.source, 2) node _T_1157 = eq(_T_1156, UInt<2>(0h2)) node _T_1158 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1159 = and(_T_1157, _T_1158) node _T_1160 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1161 = and(_T_1159, _T_1160) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1162 = shr(io.in.a.bits.source, 2) node _T_1163 = eq(_T_1162, UInt<2>(0h3)) node _T_1164 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1165 = and(_T_1163, _T_1164) node _T_1166 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1169 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1170 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1171 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1172 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1173 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1174 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1175 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1176 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1177 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1178 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1179 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1180 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1181 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1182 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1193 = or(_T_1143, _T_1149) node _T_1194 = or(_T_1193, _T_1155) node _T_1195 = or(_T_1194, _T_1161) node _T_1196 = or(_T_1195, _T_1167) node _T_1197 = or(_T_1196, _T_1168) node _T_1198 = or(_T_1197, _T_1169) node _T_1199 = or(_T_1198, _T_1170) node _T_1200 = or(_T_1199, _T_1171) node _T_1201 = or(_T_1200, _T_1172) node _T_1202 = or(_T_1201, _T_1173) node _T_1203 = or(_T_1202, _T_1174) node _T_1204 = or(_T_1203, _T_1175) node _T_1205 = or(_T_1204, _T_1176) node _T_1206 = or(_T_1205, _T_1177) node _T_1207 = or(_T_1206, _T_1178) node _T_1208 = or(_T_1207, _T_1179) node _T_1209 = or(_T_1208, _T_1180) node _T_1210 = or(_T_1209, _T_1181) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = and(_T_1142, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = or(UInt<1>(0h0), _T_1226) node _T_1228 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1229 = cvt(_T_1228) node _T_1230 = and(_T_1229, asSInt(UInt<13>(0h1000))) node _T_1231 = asSInt(_T_1230) node _T_1232 = eq(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = and(_T_1227, _T_1232) node _T_1234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1235 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1236 = and(_T_1234, _T_1235) node _T_1237 = or(UInt<1>(0h0), _T_1236) node _T_1238 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<14>(0h2000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<18>(0h2f000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h10000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<13>(0h1000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<27>(0h4000000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<13>(0h1000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = or(_T_1242, _T_1247) node _T_1269 = or(_T_1268, _T_1252) node _T_1270 = or(_T_1269, _T_1257) node _T_1271 = or(_T_1270, _T_1262) node _T_1272 = or(_T_1271, _T_1267) node _T_1273 = and(_T_1237, _T_1272) node _T_1274 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1275 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<17>(0h10000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = and(_T_1274, _T_1279) node _T_1281 = or(UInt<1>(0h0), _T_1233) node _T_1282 = or(_T_1281, _T_1273) node _T_1283 = or(_T_1282, _T_1280) node _T_1284 = and(_T_1223, _T_1283) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_26 node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(source_ok, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(is_aligned, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1294 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_29 node _T_1298 = eq(io.in.a.bits.mask, mask) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_30 node _T_1302 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1302 : node _T_1303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1307 = shr(io.in.a.bits.source, 2) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) node _T_1309 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1310 = and(_T_1308, _T_1309) node _T_1311 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1312 = and(_T_1310, _T_1311) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1313 = shr(io.in.a.bits.source, 2) node _T_1314 = eq(_T_1313, UInt<1>(0h1)) node _T_1315 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1318 = and(_T_1316, _T_1317) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1319 = shr(io.in.a.bits.source, 2) node _T_1320 = eq(_T_1319, UInt<2>(0h2)) node _T_1321 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1324 = and(_T_1322, _T_1323) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1325 = shr(io.in.a.bits.source, 2) node _T_1326 = eq(_T_1325, UInt<2>(0h3)) node _T_1327 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1332 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1333 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1334 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1335 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1336 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1337 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1338 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1339 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1340 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1341 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1342 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1343 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1344 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1352 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1353 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1354 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1356 = or(_T_1306, _T_1312) node _T_1357 = or(_T_1356, _T_1318) node _T_1358 = or(_T_1357, _T_1324) node _T_1359 = or(_T_1358, _T_1330) node _T_1360 = or(_T_1359, _T_1331) node _T_1361 = or(_T_1360, _T_1332) node _T_1362 = or(_T_1361, _T_1333) node _T_1363 = or(_T_1362, _T_1334) node _T_1364 = or(_T_1363, _T_1335) node _T_1365 = or(_T_1364, _T_1336) node _T_1366 = or(_T_1365, _T_1337) node _T_1367 = or(_T_1366, _T_1338) node _T_1368 = or(_T_1367, _T_1339) node _T_1369 = or(_T_1368, _T_1340) node _T_1370 = or(_T_1369, _T_1341) node _T_1371 = or(_T_1370, _T_1342) node _T_1372 = or(_T_1371, _T_1343) node _T_1373 = or(_T_1372, _T_1344) node _T_1374 = or(_T_1373, _T_1345) node _T_1375 = or(_T_1374, _T_1346) node _T_1376 = or(_T_1375, _T_1347) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1349) node _T_1379 = or(_T_1378, _T_1350) node _T_1380 = or(_T_1379, _T_1351) node _T_1381 = or(_T_1380, _T_1352) node _T_1382 = or(_T_1381, _T_1353) node _T_1383 = or(_T_1382, _T_1354) node _T_1384 = or(_T_1383, _T_1355) node _T_1385 = and(_T_1305, _T_1384) node _T_1386 = or(UInt<1>(0h0), _T_1385) node _T_1387 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1388 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1389 = and(_T_1387, _T_1388) node _T_1390 = or(UInt<1>(0h0), _T_1389) node _T_1391 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = and(_T_1390, _T_1395) node _T_1397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1398 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1399 = and(_T_1397, _T_1398) node _T_1400 = or(UInt<1>(0h0), _T_1399) node _T_1401 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1402 = cvt(_T_1401) node _T_1403 = and(_T_1402, asSInt(UInt<14>(0h2000))) node _T_1404 = asSInt(_T_1403) node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0))) node _T_1406 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1407 = cvt(_T_1406) node _T_1408 = and(_T_1407, asSInt(UInt<18>(0h2f000))) node _T_1409 = asSInt(_T_1408) node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0))) node _T_1411 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<17>(0h10000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<27>(0h4000000))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1427 = cvt(_T_1426) node _T_1428 = and(_T_1427, asSInt(UInt<13>(0h1000))) node _T_1429 = asSInt(_T_1428) node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0))) node _T_1431 = or(_T_1405, _T_1410) node _T_1432 = or(_T_1431, _T_1415) node _T_1433 = or(_T_1432, _T_1420) node _T_1434 = or(_T_1433, _T_1425) node _T_1435 = or(_T_1434, _T_1430) node _T_1436 = and(_T_1400, _T_1435) node _T_1437 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1438 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1439 = cvt(_T_1438) node _T_1440 = and(_T_1439, asSInt(UInt<17>(0h10000))) node _T_1441 = asSInt(_T_1440) node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0))) node _T_1443 = and(_T_1437, _T_1442) node _T_1444 = or(UInt<1>(0h0), _T_1396) node _T_1445 = or(_T_1444, _T_1436) node _T_1446 = or(_T_1445, _T_1443) node _T_1447 = and(_T_1386, _T_1446) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_31 node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(source_ok, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(is_aligned, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1458 = asUInt(reset) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) when _T_1459 : node _T_1460 = eq(_T_1457, UInt<1>(0h0)) when _T_1460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1457, UInt<1>(0h1), "") : assert_34 node _T_1461 = not(mask) node _T_1462 = and(io.in.a.bits.mask, _T_1461) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_35 node _T_1467 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1467 : node _T_1468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1472 = shr(io.in.a.bits.source, 2) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) node _T_1474 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1475 = and(_T_1473, _T_1474) node _T_1476 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1477 = and(_T_1475, _T_1476) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1478 = shr(io.in.a.bits.source, 2) node _T_1479 = eq(_T_1478, UInt<1>(0h1)) node _T_1480 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1483 = and(_T_1481, _T_1482) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1484 = shr(io.in.a.bits.source, 2) node _T_1485 = eq(_T_1484, UInt<2>(0h2)) node _T_1486 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1489 = and(_T_1487, _T_1488) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1490 = shr(io.in.a.bits.source, 2) node _T_1491 = eq(_T_1490, UInt<2>(0h3)) node _T_1492 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1495 = and(_T_1493, _T_1494) node _T_1496 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1497 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1498 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1499 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1500 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1501 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1502 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1520 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1521 = or(_T_1471, _T_1477) node _T_1522 = or(_T_1521, _T_1483) node _T_1523 = or(_T_1522, _T_1489) node _T_1524 = or(_T_1523, _T_1495) node _T_1525 = or(_T_1524, _T_1496) node _T_1526 = or(_T_1525, _T_1497) node _T_1527 = or(_T_1526, _T_1498) node _T_1528 = or(_T_1527, _T_1499) node _T_1529 = or(_T_1528, _T_1500) node _T_1530 = or(_T_1529, _T_1501) node _T_1531 = or(_T_1530, _T_1502) node _T_1532 = or(_T_1531, _T_1503) node _T_1533 = or(_T_1532, _T_1504) node _T_1534 = or(_T_1533, _T_1505) node _T_1535 = or(_T_1534, _T_1506) node _T_1536 = or(_T_1535, _T_1507) node _T_1537 = or(_T_1536, _T_1508) node _T_1538 = or(_T_1537, _T_1509) node _T_1539 = or(_T_1538, _T_1510) node _T_1540 = or(_T_1539, _T_1511) node _T_1541 = or(_T_1540, _T_1512) node _T_1542 = or(_T_1541, _T_1513) node _T_1543 = or(_T_1542, _T_1514) node _T_1544 = or(_T_1543, _T_1515) node _T_1545 = or(_T_1544, _T_1516) node _T_1546 = or(_T_1545, _T_1517) node _T_1547 = or(_T_1546, _T_1518) node _T_1548 = or(_T_1547, _T_1519) node _T_1549 = or(_T_1548, _T_1520) node _T_1550 = and(_T_1470, _T_1549) node _T_1551 = or(UInt<1>(0h0), _T_1550) node _T_1552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1553 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1554 = and(_T_1552, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1557 = cvt(_T_1556) node _T_1558 = and(_T_1557, asSInt(UInt<15>(0h5000))) node _T_1559 = asSInt(_T_1558) node _T_1560 = eq(_T_1559, asSInt(UInt<1>(0h0))) node _T_1561 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1562 = cvt(_T_1561) node _T_1563 = and(_T_1562, asSInt(UInt<13>(0h1000))) node _T_1564 = asSInt(_T_1563) node _T_1565 = eq(_T_1564, asSInt(UInt<1>(0h0))) node _T_1566 = or(_T_1560, _T_1565) node _T_1567 = and(_T_1555, _T_1566) node _T_1568 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1569 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<17>(0h10000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1580 = cvt(_T_1579) node _T_1581 = and(_T_1580, asSInt(UInt<18>(0h2f000))) node _T_1582 = asSInt(_T_1581) node _T_1583 = eq(_T_1582, asSInt(UInt<1>(0h0))) node _T_1584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1585 = cvt(_T_1584) node _T_1586 = and(_T_1585, asSInt(UInt<17>(0h10000))) node _T_1587 = asSInt(_T_1586) node _T_1588 = eq(_T_1587, asSInt(UInt<1>(0h0))) node _T_1589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1590 = cvt(_T_1589) node _T_1591 = and(_T_1590, asSInt(UInt<13>(0h1000))) node _T_1592 = asSInt(_T_1591) node _T_1593 = eq(_T_1592, asSInt(UInt<1>(0h0))) node _T_1594 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1595 = cvt(_T_1594) node _T_1596 = and(_T_1595, asSInt(UInt<27>(0h4000000))) node _T_1597 = asSInt(_T_1596) node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0))) node _T_1599 = or(_T_1573, _T_1578) node _T_1600 = or(_T_1599, _T_1583) node _T_1601 = or(_T_1600, _T_1588) node _T_1602 = or(_T_1601, _T_1593) node _T_1603 = or(_T_1602, _T_1598) node _T_1604 = and(_T_1568, _T_1603) node _T_1605 = or(UInt<1>(0h0), _T_1567) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = and(_T_1551, _T_1606) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_36 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(source_ok, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1617 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_39 node _T_1621 = eq(io.in.a.bits.mask, mask) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_40 node _T_1625 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1627 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1630 = shr(io.in.a.bits.source, 2) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) node _T_1632 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1633 = and(_T_1631, _T_1632) node _T_1634 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1635 = and(_T_1633, _T_1634) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1636 = shr(io.in.a.bits.source, 2) node _T_1637 = eq(_T_1636, UInt<1>(0h1)) node _T_1638 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1639 = and(_T_1637, _T_1638) node _T_1640 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1641 = and(_T_1639, _T_1640) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1642 = shr(io.in.a.bits.source, 2) node _T_1643 = eq(_T_1642, UInt<2>(0h2)) node _T_1644 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1645 = and(_T_1643, _T_1644) node _T_1646 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1647 = and(_T_1645, _T_1646) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1648 = shr(io.in.a.bits.source, 2) node _T_1649 = eq(_T_1648, UInt<2>(0h3)) node _T_1650 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1651 = and(_T_1649, _T_1650) node _T_1652 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1653 = and(_T_1651, _T_1652) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1662 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1663 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1664 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1665 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1666 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1667 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1668 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1669 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1670 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1671 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1672 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1673 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1674 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1675 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1676 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1677 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1678 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1679 = or(_T_1629, _T_1635) node _T_1680 = or(_T_1679, _T_1641) node _T_1681 = or(_T_1680, _T_1647) node _T_1682 = or(_T_1681, _T_1653) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1655) node _T_1685 = or(_T_1684, _T_1656) node _T_1686 = or(_T_1685, _T_1657) node _T_1687 = or(_T_1686, _T_1658) node _T_1688 = or(_T_1687, _T_1659) node _T_1689 = or(_T_1688, _T_1660) node _T_1690 = or(_T_1689, _T_1661) node _T_1691 = or(_T_1690, _T_1662) node _T_1692 = or(_T_1691, _T_1663) node _T_1693 = or(_T_1692, _T_1664) node _T_1694 = or(_T_1693, _T_1665) node _T_1695 = or(_T_1694, _T_1666) node _T_1696 = or(_T_1695, _T_1667) node _T_1697 = or(_T_1696, _T_1668) node _T_1698 = or(_T_1697, _T_1669) node _T_1699 = or(_T_1698, _T_1670) node _T_1700 = or(_T_1699, _T_1671) node _T_1701 = or(_T_1700, _T_1672) node _T_1702 = or(_T_1701, _T_1673) node _T_1703 = or(_T_1702, _T_1674) node _T_1704 = or(_T_1703, _T_1675) node _T_1705 = or(_T_1704, _T_1676) node _T_1706 = or(_T_1705, _T_1677) node _T_1707 = or(_T_1706, _T_1678) node _T_1708 = and(_T_1628, _T_1707) node _T_1709 = or(UInt<1>(0h0), _T_1708) node _T_1710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1711 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1712 = and(_T_1710, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<15>(0h5000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<13>(0h1000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = or(_T_1718, _T_1723) node _T_1725 = and(_T_1713, _T_1724) node _T_1726 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1727 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<13>(0h1000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<17>(0h10000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<18>(0h2f000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<17>(0h10000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<13>(0h1000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = or(_T_1731, _T_1736) node _T_1758 = or(_T_1757, _T_1741) node _T_1759 = or(_T_1758, _T_1746) node _T_1760 = or(_T_1759, _T_1751) node _T_1761 = or(_T_1760, _T_1756) node _T_1762 = and(_T_1726, _T_1761) node _T_1763 = or(UInt<1>(0h0), _T_1725) node _T_1764 = or(_T_1763, _T_1762) node _T_1765 = and(_T_1709, _T_1764) node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(_T_1765, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1765, UInt<1>(0h1), "") : assert_41 node _T_1769 = asUInt(reset) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(source_ok, UInt<1>(0h0)) when _T_1771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(is_aligned, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1775 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_44 node _T_1779 = eq(io.in.a.bits.mask, mask) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_45 node _T_1783 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1783 : node _T_1784 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1785 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1788 = shr(io.in.a.bits.source, 2) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1791 = and(_T_1789, _T_1790) node _T_1792 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1793 = and(_T_1791, _T_1792) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1794 = shr(io.in.a.bits.source, 2) node _T_1795 = eq(_T_1794, UInt<1>(0h1)) node _T_1796 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1797 = and(_T_1795, _T_1796) node _T_1798 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1799 = and(_T_1797, _T_1798) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1800 = shr(io.in.a.bits.source, 2) node _T_1801 = eq(_T_1800, UInt<2>(0h2)) node _T_1802 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1803 = and(_T_1801, _T_1802) node _T_1804 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1805 = and(_T_1803, _T_1804) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1806 = shr(io.in.a.bits.source, 2) node _T_1807 = eq(_T_1806, UInt<2>(0h3)) node _T_1808 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1809 = and(_T_1807, _T_1808) node _T_1810 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1813 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1814 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1815 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1816 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1817 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1818 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1819 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1820 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1821 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1822 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1823 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1824 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1825 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1826 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1836 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1837 = or(_T_1787, _T_1793) node _T_1838 = or(_T_1837, _T_1799) node _T_1839 = or(_T_1838, _T_1805) node _T_1840 = or(_T_1839, _T_1811) node _T_1841 = or(_T_1840, _T_1812) node _T_1842 = or(_T_1841, _T_1813) node _T_1843 = or(_T_1842, _T_1814) node _T_1844 = or(_T_1843, _T_1815) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1817) node _T_1847 = or(_T_1846, _T_1818) node _T_1848 = or(_T_1847, _T_1819) node _T_1849 = or(_T_1848, _T_1820) node _T_1850 = or(_T_1849, _T_1821) node _T_1851 = or(_T_1850, _T_1822) node _T_1852 = or(_T_1851, _T_1823) node _T_1853 = or(_T_1852, _T_1824) node _T_1854 = or(_T_1853, _T_1825) node _T_1855 = or(_T_1854, _T_1826) node _T_1856 = or(_T_1855, _T_1827) node _T_1857 = or(_T_1856, _T_1828) node _T_1858 = or(_T_1857, _T_1829) node _T_1859 = or(_T_1858, _T_1830) node _T_1860 = or(_T_1859, _T_1831) node _T_1861 = or(_T_1860, _T_1832) node _T_1862 = or(_T_1861, _T_1833) node _T_1863 = or(_T_1862, _T_1834) node _T_1864 = or(_T_1863, _T_1835) node _T_1865 = or(_T_1864, _T_1836) node _T_1866 = and(_T_1786, _T_1865) node _T_1867 = or(UInt<1>(0h0), _T_1866) node _T_1868 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1869 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1870 = and(_T_1868, _T_1869) node _T_1871 = or(UInt<1>(0h0), _T_1870) node _T_1872 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1873 = cvt(_T_1872) node _T_1874 = and(_T_1873, asSInt(UInt<13>(0h1000))) node _T_1875 = asSInt(_T_1874) node _T_1876 = eq(_T_1875, asSInt(UInt<1>(0h0))) node _T_1877 = and(_T_1871, _T_1876) node _T_1878 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1879 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1880 = cvt(_T_1879) node _T_1881 = and(_T_1880, asSInt(UInt<14>(0h2000))) node _T_1882 = asSInt(_T_1881) node _T_1883 = eq(_T_1882, asSInt(UInt<1>(0h0))) node _T_1884 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h10000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<18>(0h2f000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<13>(0h1000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<27>(0h4000000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = or(_T_1883, _T_1888) node _T_1915 = or(_T_1914, _T_1893) node _T_1916 = or(_T_1915, _T_1898) node _T_1917 = or(_T_1916, _T_1903) node _T_1918 = or(_T_1917, _T_1908) node _T_1919 = or(_T_1918, _T_1913) node _T_1920 = and(_T_1878, _T_1919) node _T_1921 = or(UInt<1>(0h0), _T_1877) node _T_1922 = or(_T_1921, _T_1920) node _T_1923 = and(_T_1867, _T_1922) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_46 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(source_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1930 = asUInt(reset) node _T_1931 = eq(_T_1930, UInt<1>(0h0)) when _T_1931 : node _T_1932 = eq(is_aligned, UInt<1>(0h0)) when _T_1932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1933 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1934 = asUInt(reset) node _T_1935 = eq(_T_1934, UInt<1>(0h0)) when _T_1935 : node _T_1936 = eq(_T_1933, UInt<1>(0h0)) when _T_1936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1933, UInt<1>(0h1), "") : assert_49 node _T_1937 = eq(io.in.a.bits.mask, mask) node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(_T_1937, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1937, UInt<1>(0h1), "") : assert_50 node _T_1941 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1945 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1946 = asUInt(reset) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) when _T_1947 : node _T_1948 = eq(_T_1945, UInt<1>(0h0)) when _T_1948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1945, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1949 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1949 : node _T_1950 = asUInt(reset) node _T_1951 = eq(_T_1950, UInt<1>(0h0)) when _T_1951 : node _T_1952 = eq(source_ok_1, UInt<1>(0h0)) when _T_1952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1953 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(_T_1953, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1953, UInt<1>(0h1), "") : assert_54 node _T_1957 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_55 node _T_1961 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_56 node _T_1965 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_57 node _T_1969 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(sink_ok, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1976 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_60 node _T_1980 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_61 node _T_1984 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1985 = asUInt(reset) node _T_1986 = eq(_T_1985, UInt<1>(0h0)) when _T_1986 : node _T_1987 = eq(_T_1984, UInt<1>(0h0)) when _T_1987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1984, UInt<1>(0h1), "") : assert_62 node _T_1988 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1989 = asUInt(reset) node _T_1990 = eq(_T_1989, UInt<1>(0h0)) when _T_1990 : node _T_1991 = eq(_T_1988, UInt<1>(0h0)) when _T_1991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1988, UInt<1>(0h1), "") : assert_63 node _T_1992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1993 = or(UInt<1>(0h1), _T_1992) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_64 node _T_1997 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1997 : node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(source_ok_1, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(sink_ok, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2004 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_67 node _T_2008 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_68 node _T_2012 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_69 node _T_2016 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2017 = or(_T_2016, io.in.d.bits.corrupt) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_70 node _T_2021 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2022 = or(UInt<1>(0h1), _T_2021) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_71 node _T_2026 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2026 : node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(source_ok_1, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2030 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_73 node _T_2034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_74 node _T_2038 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2039 = or(UInt<1>(0h1), _T_2038) node _T_2040 = asUInt(reset) node _T_2041 = eq(_T_2040, UInt<1>(0h0)) when _T_2041 : node _T_2042 = eq(_T_2039, UInt<1>(0h0)) when _T_2042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2039, UInt<1>(0h1), "") : assert_75 node _T_2043 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2043 : node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(source_ok_1, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2047 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2048 = asUInt(reset) node _T_2049 = eq(_T_2048, UInt<1>(0h0)) when _T_2049 : node _T_2050 = eq(_T_2047, UInt<1>(0h0)) when _T_2050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2047, UInt<1>(0h1), "") : assert_77 node _T_2051 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2052 = or(_T_2051, io.in.d.bits.corrupt) node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(_T_2052, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2052, UInt<1>(0h1), "") : assert_78 node _T_2056 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2057 = or(UInt<1>(0h1), _T_2056) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_79 node _T_2061 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2061 : node _T_2062 = asUInt(reset) node _T_2063 = eq(_T_2062, UInt<1>(0h0)) when _T_2063 : node _T_2064 = eq(source_ok_1, UInt<1>(0h0)) when _T_2064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2065 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_81 node _T_2069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_82 node _T_2073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2074 = or(UInt<1>(0h1), _T_2073) node _T_2075 = asUInt(reset) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) when _T_2076 : node _T_2077 = eq(_T_2074, UInt<1>(0h0)) when _T_2077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2074, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2079 = asUInt(reset) node _T_2080 = eq(_T_2079, UInt<1>(0h0)) when _T_2080 : node _T_2081 = eq(_T_2078, UInt<1>(0h0)) when _T_2081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2078, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2082 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2083 = asUInt(reset) node _T_2084 = eq(_T_2083, UInt<1>(0h0)) when _T_2084 : node _T_2085 = eq(_T_2082, UInt<1>(0h0)) when _T_2085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2082, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2086 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2087 = asUInt(reset) node _T_2088 = eq(_T_2087, UInt<1>(0h0)) when _T_2088 : node _T_2089 = eq(_T_2086, UInt<1>(0h0)) when _T_2089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2086, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2090 = eq(a_first, UInt<1>(0h0)) node _T_2091 = and(io.in.a.valid, _T_2090) when _T_2091 : node _T_2092 = eq(io.in.a.bits.opcode, opcode) node _T_2093 = asUInt(reset) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) when _T_2094 : node _T_2095 = eq(_T_2092, UInt<1>(0h0)) when _T_2095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2092, UInt<1>(0h1), "") : assert_87 node _T_2096 = eq(io.in.a.bits.param, param) node _T_2097 = asUInt(reset) node _T_2098 = eq(_T_2097, UInt<1>(0h0)) when _T_2098 : node _T_2099 = eq(_T_2096, UInt<1>(0h0)) when _T_2099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2096, UInt<1>(0h1), "") : assert_88 node _T_2100 = eq(io.in.a.bits.size, size) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_89 node _T_2104 = eq(io.in.a.bits.source, source) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_90 node _T_2108 = eq(io.in.a.bits.address, address) node _T_2109 = asUInt(reset) node _T_2110 = eq(_T_2109, UInt<1>(0h0)) when _T_2110 : node _T_2111 = eq(_T_2108, UInt<1>(0h0)) when _T_2111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2108, UInt<1>(0h1), "") : assert_91 node _T_2112 = and(io.in.a.ready, io.in.a.valid) node _T_2113 = and(_T_2112, a_first) when _T_2113 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2114 = eq(d_first, UInt<1>(0h0)) node _T_2115 = and(io.in.d.valid, _T_2114) when _T_2115 : node _T_2116 = eq(io.in.d.bits.opcode, opcode_1) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_92 node _T_2120 = eq(io.in.d.bits.param, param_1) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_93 node _T_2124 = eq(io.in.d.bits.size, size_1) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_94 node _T_2128 = eq(io.in.d.bits.source, source_1) node _T_2129 = asUInt(reset) node _T_2130 = eq(_T_2129, UInt<1>(0h0)) when _T_2130 : node _T_2131 = eq(_T_2128, UInt<1>(0h0)) when _T_2131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2128, UInt<1>(0h1), "") : assert_95 node _T_2132 = eq(io.in.d.bits.sink, sink) node _T_2133 = asUInt(reset) node _T_2134 = eq(_T_2133, UInt<1>(0h0)) when _T_2134 : node _T_2135 = eq(_T_2132, UInt<1>(0h0)) when _T_2135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2132, UInt<1>(0h1), "") : assert_96 node _T_2136 = eq(io.in.d.bits.denied, denied) node _T_2137 = asUInt(reset) node _T_2138 = eq(_T_2137, UInt<1>(0h0)) when _T_2138 : node _T_2139 = eq(_T_2136, UInt<1>(0h0)) when _T_2139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2136, UInt<1>(0h1), "") : assert_97 node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = and(_T_2140, d_first) when _T_2141 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2142 = and(io.in.a.valid, a_first_1) node _T_2143 = and(_T_2142, UInt<1>(0h1)) when _T_2143 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2144 = and(io.in.a.ready, io.in.a.valid) node _T_2145 = and(_T_2144, a_first_1) node _T_2146 = and(_T_2145, UInt<1>(0h1)) when _T_2146 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2147 = dshr(inflight, io.in.a.bits.source) node _T_2148 = bits(_T_2147, 0, 0) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = asUInt(reset) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) when _T_2151 : node _T_2152 = eq(_T_2149, UInt<1>(0h0)) when _T_2152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2149, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2153 = and(io.in.d.valid, d_first_1) node _T_2154 = and(_T_2153, UInt<1>(0h1)) node _T_2155 = eq(d_release_ack, UInt<1>(0h0)) node _T_2156 = and(_T_2154, _T_2155) when _T_2156 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2157 = and(io.in.d.ready, io.in.d.valid) node _T_2158 = and(_T_2157, d_first_1) node _T_2159 = and(_T_2158, UInt<1>(0h1)) node _T_2160 = eq(d_release_ack, UInt<1>(0h0)) node _T_2161 = and(_T_2159, _T_2160) when _T_2161 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2162 = and(io.in.d.valid, d_first_1) node _T_2163 = and(_T_2162, UInt<1>(0h1)) node _T_2164 = eq(d_release_ack, UInt<1>(0h0)) node _T_2165 = and(_T_2163, _T_2164) when _T_2165 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2166 = dshr(inflight, io.in.d.bits.source) node _T_2167 = bits(_T_2166, 0, 0) node _T_2168 = or(_T_2167, same_cycle_resp) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2172 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2173 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2174 = or(_T_2172, _T_2173) node _T_2175 = asUInt(reset) node _T_2176 = eq(_T_2175, UInt<1>(0h0)) when _T_2176 : node _T_2177 = eq(_T_2174, UInt<1>(0h0)) when _T_2177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2174, UInt<1>(0h1), "") : assert_100 node _T_2178 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2179 = asUInt(reset) node _T_2180 = eq(_T_2179, UInt<1>(0h0)) when _T_2180 : node _T_2181 = eq(_T_2178, UInt<1>(0h0)) when _T_2181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2178, UInt<1>(0h1), "") : assert_101 else : node _T_2182 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2183 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2184 = or(_T_2182, _T_2183) node _T_2185 = asUInt(reset) node _T_2186 = eq(_T_2185, UInt<1>(0h0)) when _T_2186 : node _T_2187 = eq(_T_2184, UInt<1>(0h0)) when _T_2187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2184, UInt<1>(0h1), "") : assert_102 node _T_2188 = eq(io.in.d.bits.size, a_size_lookup) node _T_2189 = asUInt(reset) node _T_2190 = eq(_T_2189, UInt<1>(0h0)) when _T_2190 : node _T_2191 = eq(_T_2188, UInt<1>(0h0)) when _T_2191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2188, UInt<1>(0h1), "") : assert_103 node _T_2192 = and(io.in.d.valid, d_first_1) node _T_2193 = and(_T_2192, a_first_1) node _T_2194 = and(_T_2193, io.in.a.valid) node _T_2195 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2196 = and(_T_2194, _T_2195) node _T_2197 = eq(d_release_ack, UInt<1>(0h0)) node _T_2198 = and(_T_2196, _T_2197) when _T_2198 : node _T_2199 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2200 = or(_T_2199, io.in.a.ready) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_72 node _T_2204 = orr(inflight) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) node _T_2206 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2207 = or(_T_2205, _T_2206) node _T_2208 = lt(watchdog, plusarg_reader.out) node _T_2209 = or(_T_2207, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2213 = and(io.in.a.ready, io.in.a.valid) node _T_2214 = and(io.in.d.ready, io.in.d.valid) node _T_2215 = or(_T_2213, _T_2214) when _T_2215 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2216 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2217 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2218 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2219 = and(_T_2217, _T_2218) node _T_2220 = and(_T_2216, _T_2219) when _T_2220 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2221 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2222 = and(_T_2221, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2223 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2224 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2225 = and(_T_2223, _T_2224) node _T_2226 = and(_T_2222, _T_2225) when _T_2226 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2227 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2228 = bits(_T_2227, 0, 0) node _T_2229 = eq(_T_2228, UInt<1>(0h0)) node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(_T_2229, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2229, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2233 = and(io.in.d.valid, d_first_2) node _T_2234 = and(_T_2233, UInt<1>(0h1)) node _T_2235 = and(_T_2234, d_release_ack_1) when _T_2235 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2236 = and(io.in.d.ready, io.in.d.valid) node _T_2237 = and(_T_2236, d_first_2) node _T_2238 = and(_T_2237, UInt<1>(0h1)) node _T_2239 = and(_T_2238, d_release_ack_1) when _T_2239 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2240 = and(io.in.d.valid, d_first_2) node _T_2241 = and(_T_2240, UInt<1>(0h1)) node _T_2242 = and(_T_2241, d_release_ack_1) when _T_2242 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2243 = dshr(inflight_1, io.in.d.bits.source) node _T_2244 = bits(_T_2243, 0, 0) node _T_2245 = or(_T_2244, same_cycle_resp_1) node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : node _T_2248 = eq(_T_2245, UInt<1>(0h0)) when _T_2248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2245, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2249 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : node _T_2252 = eq(_T_2249, UInt<1>(0h0)) when _T_2252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2249, UInt<1>(0h1), "") : assert_108 else : node _T_2253 = eq(io.in.d.bits.size, c_size_lookup) node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : node _T_2256 = eq(_T_2253, UInt<1>(0h0)) when _T_2256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2253, UInt<1>(0h1), "") : assert_109 node _T_2257 = and(io.in.d.valid, d_first_2) node _T_2258 = and(_T_2257, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2259 = and(_T_2258, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2260 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2261 = and(_T_2259, _T_2260) node _T_2262 = and(_T_2261, d_release_ack_1) node _T_2263 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2264 = and(_T_2262, _T_2263) when _T_2264 : node _T_2265 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2266 = or(_T_2265, _WIRE_27.ready) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_73 node _T_2270 = orr(inflight_1) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) node _T_2272 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2273 = or(_T_2271, _T_2272) node _T_2274 = lt(watchdog_1, plusarg_reader_1.out) node _T_2275 = or(_T_2273, _T_2274) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2279 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2280 = and(io.in.d.ready, io.in.d.valid) node _T_2281 = or(_T_2279, _T_2280) when _T_2281 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_2 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d64s6k5z4c_2 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<4>(0hf)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<4>(0he)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<4>(0hd)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<4>(0hc)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_5 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_5 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_5, 1, 0) node _io_flit_bits_egress_id_requestOH_T_25 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_26 = eq(_io_flit_bits_egress_id_requestOH_T_25, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_27 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_5) node _io_flit_bits_egress_id_requestOH_T_28 = and(_io_flit_bits_egress_id_requestOH_T_26, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_5, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_5 = and(_io_flit_bits_egress_id_requestOH_T_28, _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_6 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_6 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_6, 1, 0) node _io_flit_bits_egress_id_requestOH_T_30 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_31 = eq(_io_flit_bits_egress_id_requestOH_T_30, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_32 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_6) node _io_flit_bits_egress_id_requestOH_T_33 = and(_io_flit_bits_egress_id_requestOH_T_31, _io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_6, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_6 = and(_io_flit_bits_egress_id_requestOH_T_33, _io_flit_bits_egress_id_requestOH_T_34) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_7 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_7 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_7, 1, 0) node _io_flit_bits_egress_id_requestOH_T_35 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_36 = eq(_io_flit_bits_egress_id_requestOH_T_35, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_37 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_7) node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_36, _io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_7, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_7 = and(_io_flit_bits_egress_id_requestOH_T_38, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_8 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_8 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_8, 1, 0) node _io_flit_bits_egress_id_requestOH_T_40 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_41 = eq(_io_flit_bits_egress_id_requestOH_T_40, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_42 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_8) node _io_flit_bits_egress_id_requestOH_T_43 = and(_io_flit_bits_egress_id_requestOH_T_41, _io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_8, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_8 = and(_io_flit_bits_egress_id_requestOH_T_43, _io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<4>(0hd), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<4>(0hf), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_8 = mux(io_flit_bits_egress_id_requestOH_8, UInt<5>(0h11), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_9 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_10 = or(_io_flit_bits_egress_id_T_9, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_11 = or(_io_flit_bits_egress_id_T_10, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_12 = or(_io_flit_bits_egress_id_T_11, _io_flit_bits_egress_id_T_4) node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T_12, _io_flit_bits_egress_id_T_5) node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_6) node _io_flit_bits_egress_id_T_15 = or(_io_flit_bits_egress_id_T_14, _io_flit_bits_egress_id_T_7) node _io_flit_bits_egress_id_T_16 = or(_io_flit_bits_egress_id_T_15, _io_flit_bits_egress_id_T_8) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_16 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<5>(0h10)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T

module TLDToNoC_2( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 | tail_beats1 == 3'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_270 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_270( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module BankBinder : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_39 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn

module BankBinder( // @[BankBinder.scala:61:9] input clock, // @[BankBinder.scala:61:9] input reset, // @[BankBinder.scala:61:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BankBinder.scala:61:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BankBinder.scala:61:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BankBinder.scala:61:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BankBinder.scala:61:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BankBinder.scala:61:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BankBinder.scala:61:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BankBinder.scala:61:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BankBinder.scala:61:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BankBinder.scala:61:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BankBinder.scala:61:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[BankBinder.scala:61:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[BankBinder.scala:61:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[BankBinder.scala:61:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[BankBinder.scala:61:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[BankBinder.scala:61:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[BankBinder.scala:61:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[BankBinder.scala:61:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[BankBinder.scala:61:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[BankBinder.scala:61:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[BankBinder.scala:61:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BankBinder.scala:61:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BankBinder.scala:61:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BankBinder.scala:61:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BankBinder.scala:61:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BankBinder.scala:61:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BankBinder.scala:61:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BankBinder.scala:61:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BankBinder.scala:61:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[BankBinder.scala:61:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[BankBinder.scala:61:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[BankBinder.scala:61:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[BankBinder.scala:61:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[BankBinder.scala:61:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[BankBinder.scala:61:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[BankBinder.scala:61:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[BankBinder.scala:61:9] wire auto_in_a_ready_0; // @[BankBinder.scala:61:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9] wire [1:0] auto_in_d_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] auto_in_d_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] auto_in_d_bits_source_0; // @[BankBinder.scala:61:9] wire auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9] wire auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9] wire [63:0] auto_in_d_bits_data_0; // @[BankBinder.scala:61:9] wire auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9] wire auto_in_d_valid_0; // @[BankBinder.scala:61:9] wire [2:0] auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9] wire [2:0] auto_out_a_bits_param_0; // @[BankBinder.scala:61:9] wire [2:0] auto_out_a_bits_size_0; // @[BankBinder.scala:61:9] wire [4:0] auto_out_a_bits_source_0; // @[BankBinder.scala:61:9] wire [31:0] auto_out_a_bits_address_0; // @[BankBinder.scala:61:9] wire [7:0] auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9] wire [63:0] auto_out_a_bits_data_0; // @[BankBinder.scala:61:9] wire auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9] wire auto_out_a_valid_0; // @[BankBinder.scala:61:9] wire auto_out_d_ready_0; // @[BankBinder.scala:61:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BankBinder.scala:61:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BankBinder.scala:61:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BankBinder.scala:61:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BankBinder.scala:61:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BankBinder.scala:61:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BankBinder.scala:61:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BankBinder.scala:61:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BankBinder.scala:61:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BankBinder.scala:61:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BankBinder.scala:61:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[BankBinder.scala:61:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BankBinder.scala:61:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[BankBinder.scala:61:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[BankBinder.scala:61:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[BankBinder.scala:61:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[BankBinder.scala:61:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[BankBinder.scala:61:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[BankBinder.scala:61:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[BankBinder.scala:61:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] TLMonitor_39 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BankBinder.scala:61:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BankBinder.scala:61:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[BankBinder.scala:61:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[BankBinder.scala:61:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_6 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_6( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64_mulAddZ31 : input clock : Clock input reset : Reset output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} inst divSqrtRecF64ToRaw of DivSqrtRecF64ToRaw_mulAddZ31 connect divSqrtRecF64ToRaw.clock, clock connect divSqrtRecF64ToRaw.reset, reset connect io.inReady_div, divSqrtRecF64ToRaw.io.inReady_div connect io.inReady_sqrt, divSqrtRecF64ToRaw.io.inReady_sqrt connect divSqrtRecF64ToRaw.io.inValid, io.inValid connect divSqrtRecF64ToRaw.io.sqrtOp, io.sqrtOp connect divSqrtRecF64ToRaw.io.a, io.a connect divSqrtRecF64ToRaw.io.b, io.b connect divSqrtRecF64ToRaw.io.roundingMode, io.roundingMode connect io.usingMulAdd, divSqrtRecF64ToRaw.io.usingMulAdd connect io.latchMulAddA_0, divSqrtRecF64ToRaw.io.latchMulAddA_0 connect io.mulAddA_0, divSqrtRecF64ToRaw.io.mulAddA_0 connect io.latchMulAddB_0, divSqrtRecF64ToRaw.io.latchMulAddB_0 connect io.mulAddB_0, divSqrtRecF64ToRaw.io.mulAddB_0 connect io.mulAddC_2, divSqrtRecF64ToRaw.io.mulAddC_2 connect divSqrtRecF64ToRaw.io.mulAddResult_3, io.mulAddResult_3 connect io.outValid_div, divSqrtRecF64ToRaw.io.rawOutValid_div connect io.outValid_sqrt, divSqrtRecF64ToRaw.io.rawOutValid_sqrt inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_5 connect roundRawFNToRecFN.io.invalidExc, divSqrtRecF64ToRaw.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecF64ToRaw.io.infiniteExc connect roundRawFNToRecFN.io.in.sig, divSqrtRecF64ToRaw.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, divSqrtRecF64ToRaw.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, divSqrtRecF64ToRaw.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, divSqrtRecF64ToRaw.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, divSqrtRecF64ToRaw.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecF64ToRaw.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, divSqrtRecF64ToRaw.io.roundingModeOut connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module DivSqrtRecF64_mulAddZ31( // @[DivSqrtRecF64_mulAddZ31.scala:719:7] input clock, // @[DivSqrtRecF64_mulAddZ31.scala:719:7] input reset, // @[DivSqrtRecF64_mulAddZ31.scala:719:7] output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_outValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output io_outValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [64:0] io_out, // @[DivSqrtRecF64_mulAddZ31.scala:721:16] output [4:0] io_exceptionFlags // @[DivSqrtRecF64_mulAddZ31.scala:721:16] ); wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_invalidExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_infiniteExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isNaN; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isInf; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_isZero; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire _divSqrtRecF64ToRaw_io_rawOut_sign; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig; // @[DivSqrtRecF64_mulAddZ31.scala:751:36] wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_detectTininess = 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7, :721:16, :775:15] wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [64:0] io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] DivSqrtRecF64ToRaw_mulAddZ31 divSqrtRecF64ToRaw ( // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .clock (clock), .reset (reset), .io_inReady_div (io_inReady_div_0), .io_inReady_sqrt (io_inReady_sqrt_0), .io_inValid (io_inValid_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_a (io_a_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_b (io_b_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_usingMulAdd (io_usingMulAdd_0), .io_latchMulAddA_0 (io_latchMulAddA_0_0), .io_mulAddA_0 (io_mulAddA_0_0), .io_latchMulAddB_0 (io_latchMulAddB_0_0), .io_mulAddB_0 (io_mulAddB_0_0), .io_mulAddC_2 (io_mulAddC_2_0), .io_mulAddResult_3 (io_mulAddResult_3_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7] .io_rawOutValid_div (io_outValid_div_0), .io_rawOutValid_sqrt (io_outValid_sqrt_0), .io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut), .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), .io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), .io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), .io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), .io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), .io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), .io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig) ); // @[DivSqrtRecF64_mulAddZ31.scala:751:36] RoundRawFNToRecFN_e11_s53_5 roundRawFNToRecFN ( // @[DivSqrtRecF64_mulAddZ31.scala:775:15] .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut), // @[DivSqrtRecF64_mulAddZ31.scala:751:36] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[DivSqrtRecF64_mulAddZ31.scala:775:15] assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_out = io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7] endmodule